LPC1311_12_技术文档

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and

8 kB SRAM; USB device

Rev. 5 — 6 June 2012

Product data sheet

1. General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash

memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus

I²C-bus interface, one UART, four general purpose timers, and up to 42 general purpose

I/O pins.

Remark: The LPC1311/13/42/43 series consists of the LPC1300 series (parts

LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The

LPC1300L series features the following enhancements over the LPC1300 series:

• Power profiles with lower power consumption in Active and Sleep modes.

• Four levels for BOD forced reset.

• Second SSP controller (LPC1313FBD48/01 only).

• Windowed Watchdog Timer (WWDT).

• Internal pull-up resistors pull up pins to full V_DDlevel.

• Programmable pseudo open-drain mode for GPIO pins.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming

memory.

 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Selectable boot-up: UART or USB (USB on LPC1342/43 only).

 On LPC1342/43: USB MSC and HID on-chip drivers.

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

 Serial interfaces:

 USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43

only).

 UART with fractional baud rate generation, modem, internal FIFO, and

RS-485/EIA-485 support.

 SSP controller with FIFO and multi-protocol capabilities.

 Additional SSP controller on LPC1313FBD48/01.

 I²C-bus interface supporting full I²C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

 Other peripherals:

 Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors.

 Four general purpose counter/timers with a total of four capture inputs and 13

match outputs.

 Programmable WatchDog Timer (WDT).

 Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and

LPC1313/01.

 System tick timer.

 Serial Wire Debug and Serial Wire Trace port.

 High-current output driver (20 mA) on one pin.

 High-current sink drivers (20 mA) on two I²C-bus pins in Fast-mode Plus.

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

 Power profiles residing in boot ROM allowing to optimize performance and minimize

power consumption for any given application through one simple function call.

(LPC1300L series, on LPC1311/01 and LPC1313/01 only.)

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

 Single power supply (2.0 V to 3.6 V).

 10-bit ADC with input multiplexing among 8 pins.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, or the watchdog clock.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of

the functional pins.

 Brownout detect with four separate thresholds for interrupt and one threshold for

forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01

parts).

 Power-On Reset (POR).

 Integrated oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature

and voltage range that can optionally be used as a system clock.

 Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

 System PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

 For USB (LPC1342/43), a second, dedicated PLL is provided.

 Code Read Protection (CRP) with different security levels.

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

2 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

 Unique device serial number for identification.

 Available as 48-pin LQFP package and 33-pin HVQFN package.

3. Applications

 eMetering

 Lighting

 Alarm systems

 White goods

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1311FHN33

LPC1311FHN33/01

LPC1313FHN33

LPC1313FHN33/01

LPC1313FBD48

LPC1313FBD48/01

LPC1342FHN33

LPC1342FBD48

LPC1343FHN33

LPC1343FBD48

HVQFN33

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

n/a

HVQFN33

LQFP48

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

n/a

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

n/a

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

n/a

LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm

SOT313-2

n/a

LQFP48

LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm

HVQFN33

LQFP48

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm

SOT313-2

n/a

HVQFN33

LQFP48

HVQFN33: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 × 7 × 0.85 mm

LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

1.4 mm

SOT313-2

4.1 Ordering options

Table 2.

Ordering options for LPC1311/13/42/43

Type number

Flash

Total

SRAM

USB

Power

UART

I²C/

SSP ADC

channels

Pins Package

profiles RS-485 Fast+

LPC1311FHN33

LPC1311FHN33/01

LPC1313FHN33

LPC1313FHN33/01

LPC1313FBD48

LPC1313FBD48/01

8 kB

4 kB

8 kB

-

no

1

2

8

33

48

HVQFN33

LQFP48

8 kB

yes

no

8

32 kB

yes

no

yes

LQFP48

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

3 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 2.

Ordering options for LPC1311/13/42/43 …continued

Type number

Flash

Total

SRAM

USB

Power

UART

I²C/

SSP ADC

channels

Pins Package

profiles RS-485 Fast+

LPC1342FHN33

LPC1342FBD48

LPC1343FHN33

LPC1343FBD48

16 kB

32 kB

4 kB

8 kB

Device no

1

8

33

48

33

48

HVQFN33

LQFP48

8

HVQFN33

LQFP48

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

4 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

5. Block diagram

XTALIN

XTALOUT

RESET

USB pins

SWD

LPC1311/13/42/43

(1)

USB PHY

TEST/DEBUG

INTERFACE

IRC

WDO

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

CLKOUT

ARM

CORTEX-M3

USB DEVICE

CONTROLLER

FUNCTIONS

(1)

clocks and

controls

I-code

bus

D-code

bus

system

bus

slave

ROM

AHB-LITE BUS

slave

SRAM

4/8 kB

slave

HIGH-SPEED

GPIO

GPIO ports

PIO0/1/2/3

FLASH

8/16/32 kB

AHB TO

APB

BRIDGE

RXD

TXD

UART

AD[7:0]

10-bit ADC

SSP0

(2)

DTR, DSR , CTS,

(2)

DCD , RI , RTS

SCK0,SSEL0

MISO0, MOSI0

CT32B0_MAT[3:0]

CT32B0_CAP0

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

SCK1,SSEL1

MISO1, MOSI0

(3)

SSP1

CT32B1_MAT[3:0]

CT32B1_CAP0

SCL

SDA

2

I C-BUS

CT16B0_MAT[2:0]

CT16B0_CAP0

(4)

WDT/WWDT

CT16B1_MAT[1:0]

CT16B1_CAP0

IOCONFIG

SYSTEM CONTROL

002aae722

(1) LPC1342/43 only.

(2) LQFP48 package only.

(3) On LPC1313FBD48/01 only.

(4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.

Fig 1. Block diagram

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

5 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

PIO2_6

PIO3_0

PIO2_0/DTR

RESET/PIO0_0

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0

3

4

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE

5

V

SS

6

XTALIN

LPC1342FBD48

LPC1343FBD48

7

XTALOUT

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

PIO2_2/DCD

8

V

DD

9

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

10

11

12

PIO2_8

PIO2_10

002aae505

Fig 2. LPC1342/43 LQFP48 package

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

6 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

PIO2_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE

XTALIN

LPC1342FHN33

LPC1343FHN33

XTALOUT

V

DD

PIO1_8/CT16B1_CAP0

33 V

SS

PIO0_2/SSEL0/CT16B0_CAP0

002aae516

Transparent top view

Fig 3. LPC1342/43 HVQFN33 package

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

7 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

1

2

36

35

34

33

32

31

30

29

28

27

26

25

PIO2_6

PIO3_0

(1)

PIO2_0/DTR/SSEL1

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO2_11/SCK0

3

RESET/PIO0_0

4

PIO0_1/CLKOUT/CT32B0_MAT2

5

V

SS

LPC1313FBD48

LPC1313FBD48/01

6

XTALIN

7

XTALOUT

PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

8

V

DD

9

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO2_7

10

11

12

(1)

PIO2_2/DCD/MISO1

PIO2_8

PIO2_10

002aae513

(1) SSP1 or UART function on LPC1313FBD48/01 only.

Fig 4. LPC1313 LQFP48 package

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

8 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

PIO2_0/DTR

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO1_1/AD2/CT32B1_MAT0

R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

PIO1_10/AD6/CT16B1_MAT1

RESET/PIO0_0

PIO0_1/CLKOUT/CT32B0_MAT2

LPC1311FHN33

LPC1311FHN33/01

LPC1313FHN33

XTALIN

XTALOUT

LPC1313FHN33/01

V

DD

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

33 V

SS

PIO0_2/SSEL0/CT16B0_CAP0

002aae517

Transparent top view

Fig 5. LPC1311/13 HVQFN33 package

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

9 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

6.2 Pin description

Table 3.

Symbol

LPC1313/42/43 LQFP48 pin description table

Pin Start Type Reset Description

logic

input

state

[1]

RESET/PIO0_0

3^[2]yes

I

I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0.

I/O

-

PIO0_0 — General purpose digital input/output pin with 10 ns glitch

filter.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

4^[3]yes

I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler or the USB

device enumeration (USB on LPC1342/43 only, see description of

PIO0_3).

O

-

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43

only).

PIO0_2/SSEL0/

CT16B0_CAP0

10^[3]yes

14^[3]yes

I/O

I

I; PU PIO0_2 — General purpose digital input/output pin.

-

SSEL0 — Slave select for SSP0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3/USB_VBUS

I/O

I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43

only: A LOW level on this pin during reset starts the ISP command

handler, a HIGH level starts the USB device enumeration.

I

-

USB_VBUS — Monitors the presence of USB bus power

(LPC1342/43 only).

PIO0_4/SCL

PIO0_5/SDA

15^[4]yes

16^[4]yes

22^[3]yes

I/O

I; IA

-

PIO0_4 — General purpose digital input/output pin (open-drain).

SCL — I²C-bus clock input/output (open-drain). High-current sink

only if I²C Fast-mode Plus is selected in the I/O configuration

register.

I/O

I; IA

-

PIO0_5 — General purpose digital input/output pin (open-drain).

SDA — I²C-bus data input/output (open-drain). High-current sink

only if I²C Fast-mode Plus is selected in the I/O configuration

register.

PIO0_6/

USB_CONNECT/

SCK0

I/O

O

I; PU PIO0_6 — General purpose digital input/output pin.

-

USB_CONNECT — Signal used to switch an external 1.5 kΩ

resistor under software control. Used with the SoftConnect USB

feature (LPC1342/43 only).

I/O

-

SCK0 — Serial clock for SSP0.

PIO0_7/CTS

23^[3]yes

27^[3]yes

I; PU PIO0_7 — General purpose digital input/output pin (high-current

output driver).

I

-

CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

I/O

O

I; PU PIO0_8 — General purpose digital input/output pin.

-

MISO0 — Master In Slave Out for SSP0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

LPC1311_13_42_43

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Product data sheet

Rev. 5 — 6 June 2012

10 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

LPC1313/42/43 LQFP48 pin description table …continued

Pin Start Type Reset Description

logic

input

state

[1]

PIO0_9/MOSI0/

CT16B0_MAT1/

SWO

28^[3]yes

I/O

O

I; PU PIO0_9 — General purpose digital input/output pin.

-

MOSI0 — Master Out Slave In for SSP0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWO — Serial wire trace output.

O

SWCLK/PIO0_10/

29^[3]yes

I

I; PU SWCLK — Serial wire clock.

SCK0/CT16B0_MAT2

I/O

O

-

PIO0_10 — General purpose digital input/output pin.

SCK0 — Serial clock for SSP0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/

32^[5]yes

-

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

AD0/CT32B0_MAT3

block.

I/O

I

-

PIO0_11 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

O

-

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

R/PIO1_0/

AD1/CT32B1_CAP0

33^[5]yes

34^[5]yes

35^[5]yes

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

-

PIO1_0 — General purpose digital input/output pin.

AD1 — A/D converter, input 1.

I

-

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/

AD2/CT32B1_MAT0

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

I

-

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

O

-

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

AD3/CT32B1_MAT1

block.

I/O

I

-

PIO1_2 — General purpose digital input/output pin.

AD3 — A/D converter, input 3.

O

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

39^[5]yes

I/O

I

I; PU SWDIO — Serial wire debug input/output.

-

PIO1_3 — General purpose digital input/output pin.

AD4 — A/D converter, input 4.

O

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

40^[5]yes

I/O

I; PU PIO1_4 — General purpose digital input/output pin.

I

-

AD5 — A/D converter, input 5.

O

I

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch

filter. This pin must be pulled HIGH externally to enter Deep

power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

LPC1311_13_42_43

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 6 June 2012

11 of 74

LPC1311/13/42/43

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

Table 3.

Symbol

LPC1313/42/43 LQFP48 pin description table …continued

Pin Start Type Reset Description

logic

input

state

[1]

PIO1_5/RTS/

CT32B0_CAP0

45^[3]yes

I/O

O

I; PU PIO1_5 — General purpose digital input/output pin.

-

RTS — Request To Send output for UART.

I

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0

46^[3]yes

47^[3]yes

I/O

I

I; PU PIO1_6 — General purpose digital input/output pin.

-

RXD — Receiver input for UART.

O

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1

I/O

O

I; PU PIO1_7 — General purpose digital input/output pin.

-

TXD — Transmitter output for UART.

O

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/CT16B1_CAP0 9^[3]yes

PIO1_9/CT16B1_MAT0 17^[3]yes

I/O

I

I; PU PIO1_8 — General purpose digital input/output pin.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

I; PU PIO1_9 — General purpose digital input/output pin.

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

I; PU PIO1_10 — General purpose digital input/output pin.

-

I/O

O

-

PIO1_10/AD6/

CT16B1_MAT1

30^[5]yes

I/O

I

-

AD6 — A/D converter, input 6.

O

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7

42^[5]yes

2^[3]yes

I/O

I

I; PU PIO1_11 — General purpose digital input/output pin.

AD7 — A/D converter, input 7.

I; PU PIO2_0 — General purpose digital input/output pin.

-

PIO2_0/DTR/SSEL1

I/O

O

-

DTR — Data Terminal Ready output for UART.

I/O

I

SSEL1 — Slave Select for SSP1 (LPC1313FBD48/01 only).

PIO2_1/DSR/SCK1

PIO2_2/DCD/MISO1

PIO2_3/RI/MOSI1

PIO2_4

13^[3]yes

26^[3]yes

38^[3]yes

18^[3]yes

I; PU PIO2_1 — General purpose digital input/output pin.

-

DSR — Data Set Ready input for UART.

I/O

I

SCK1 — Serial clock for SSP1 (LPC1313FBD48/01 only).

I; PU PIO2_2 — General purpose digital input/output pin.

-

DCD — Data Carrier Detect input for UART.

I/O

I

MISO1 — Master In Slave Out for SSP1 (LPC1313FBD48/01 only).

I; PU PIO2_3 — General purpose digital input/output pin.

-

RI — Ring Indicator input for UART.

I/O

MOSI1 — Master Out Slave In for SSP1 (LPC1313FBD48/01 only).

I; PU PIO2_4 — General purpose digital input/output pin (LPC1342/43

only).

PIO2_4

PIO2_5

19^[3]yes

21^[3]yes

I/O

I; PU PIO2_4 — General purpose digital input/output pin (LPC1313 only).

I; PU PIO2_5 — General purpose digital input/output pin (LPC1342/43

only).

PIO2_5

PIO2_6

PIO2_7

PIO2_8

PIO2_9

20^[3]yes

1^[3]yes

11^[3]yes

12^[3]yes

24^[3]yes

I/O

I; PU PIO2_5 — General purpose digital input/output pin (LPC1313 only).

I; PU PIO2_6 — General purpose digital input/output pin.

I; PU PIO2_7 — General purpose digital input/output pin.

I; PU PIO2_8 — General purpose digital input/output pin.

I; PU PIO2_9 — General purpose digital input/output pin.

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Table 3.

Symbol

LPC1313/42/43 LQFP48 pin description table …continued

Pin Start Type Reset Description

logic

input

state

[1]

PIO2_10

25^[3]yes

I/O

O

I; PU PIO2_10 — General purpose digital input/output pin.

I; PU PIO2_11 — General purpose digital input/output pin.

PIO2_11/SCK0

31^[3]yes

36^[3]yes

-

SCK0 — Serial clock for SSP0.

PIO3_0/DTR

PIO3_1/DSR

PIO3_2/DCD

PIO3_3/RI

I; PU PIO3_0 — General purpose digital input/output pin.

-

DTR — Data Terminal Ready output for UART (LPC1311/01 and

LPC1313/01 only).

37^[3]yes

43^[3]yes

48^[3]yes

I/O

I

I; PU PIO3_1 — General purpose digital input/output pin.

-

DSR — Data Set Ready input for UART (LPC1311/01 and

LPC1313/01 only).

I/O

I

I; PU PIO3_2 — General purpose digital input/output pin.

-

DCD — Data Carrier Detect input for UART (LPC1311/01 and

LPC1313/01 only).

I/O

I

I; PU PIO3_3 — General purpose digital input/output pin.

-

RI — Ring Indicator input for UART (LPC1311/01 and LPC1313/01

only).

PIO3_4

PIO3_5

USB_DM

USB_DP

V_DD

18^[3]no

21^[3]no

19^[6]no

20^[6]no

I/O

I

I; PU PIO3_4 — General purpose digital input/output pin (LPC1313 only).

I; PU PIO3_5 — General purpose digital input/output pin (LPC1313 only).

F

-

USB_DM — USB bidirectional D− line (LPC1342/43 only).

USB_DP — USB bidirectional D+ line (LPC1342/43 only).

8;

-

3.3 V supply voltage to the internal regulator, the external rail, and

the ADC. Also used as the ADC reference voltage.

44

XTALIN

6^[7]

-

I

-

Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT

V_SS

7^[7]

-

O

I

-

Output from the oscillator amplifier.

Ground.

5;

41

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for V_DD= 3.3 V, pin is pulled up to 2.6 V for

parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled;

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See Figure 37 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the

Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 36).

[4] I²C-bus pads compliant with the I²C-bus specification for I²C standard mode and I²C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 36).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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32-bit ARM Cortex-M3 microcontroller

Table 4.

Symbol

LPC1311/13/42/43 HVQFN33 pin description table

Pin Start Type Reset Description

logic

input

state

[1]

RESET/PIO0_0

2^[2]yes

I

I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse

as short as 50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to

begin at address 0.

I/O

-

PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

3^[3]yes

I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this

pin during reset starts the ISP command handler or the USB device

enumeration (USB on LPC1342/43 only, see description of PIO0_3).

O

-

CLKOUT — Clock out pin.

O

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).

O

PIO0_2/SSEL0/

CT16B0_CAP0

8^[3]yes

I/O

I

I; PU PIO0_2 — General purpose digital input/output pin.

-

SSEL0 — Slave select for SSP0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3/

USB_VBUS

9^[3]yes

I/O

I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A

LOW level on this pin during reset starts the ISP command handler, a

HIGH level starts the USB device enumeration.

I

-

USB_VBUS — Monitors the presence of USB bus power (LPC1342/43

only).

PIO0_4/SCL

PIO0_5/SDA

10^[4]yes

11^[4]yes

15^[3]yes

I/O

I; IA

-

PIO0_4 — General purpose digital input/output pin (open-drain).

SCL — I²C-bus clock input/output (open-drain). High-current sink only if

I²C Fast-mode Plus is selected in the I/O configuration register.

I/O

I; IA

-

PIO0_5 — General purpose digital input/output pin (open-drain).

SDA — I²C-bus data input/output (open-drain). High-current sink only if

I²C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/

USB_CONNECT/

SCK0

I/O

O

I; PU PIO0_6 — General purpose digital input/output pin.

-

USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor

under software control. Used with the SoftConnect USB feature

(LPC1342/43 only).

I/O

-

SCK0 — Serial clock for SSP0.

PIO0_7/CTS

16^[3]yes

17^[3]yes

I; PU PIO0_7 — General purpose digital input/output pin (high-current output

driver).

I

-

CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

I/O

O

I; PU PIO0_8 — General purpose digital input/output pin.

-

MISO0 — Master In Slave Out for SSP0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1/

SWO

18^[3]yes

I/O

O

I; PU PIO0_9 — General purpose digital input/output pin.

-

MOSI0 — Master Out Slave In for SSP0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWO — Serial wire trace output.

O

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32-bit ARM Cortex-M3 microcontroller

Table 4.

Symbol

LPC1311/13/42/43 HVQFN33 pin description table …continued

Pin Start Type Reset Description

logic

input

state

[1]

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

19^[3]yes

I

I; PU SWCLK — Serial wire clock.

I/O

O

-

PIO0_10 — General purpose digital input/output pin.

SCK0 — Serial clock for SSP0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/AD0/

CT32B0_MAT3

21^[5]yes

22^[5]yes

23^[5]yes

24^[5]yes

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

I

-

PIO0_11 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

O

-

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

R/PIO1_0/AD1/

CT32B1_CAP0

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

-

PIO1_0 — General purpose digital input/output pin.

AD1 — A/D converter, input 1.

I

-

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/AD2/

CT32B1_MAT0

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

I

-

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

O

-

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/AD3/

CT32B1_MAT1

I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O

I

-

PIO1_2 — General purpose digital input/output pin.

AD3 — A/D converter, input 3.

O

I/O

I

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

25^[5]yes

I; PU SWDIO — Serial wire debug input/output.

-

PIO1_3 — General purpose digital input/output pin.

AD4 — A/D converter, input 4.

CT32B1_MAT2

O

I/O

I

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

26^[5]yes

I; PU PIO1_4 — General purpose digital input/output pin.

-

AD5 — A/D converter, input 5.

O

I

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter.

This pin must be pulled HIGH externally to enter Deep power-down mode

and pulled LOW to exit Deep power-down mode. A LOW-going pulse as

short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0

30^[3]yes

31^[3]yes

I/O

O

I

I; PU PIO1_5 — General purpose digital input/output pin.

-

RTS — Request To Send output for UART.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0

I/O

I

I; PU PIO1_6 — General purpose digital input/output pin.

-

RXD — Receiver input for UART.

O

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

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32-bit ARM Cortex-M3 microcontroller

Table 4.

Symbol

LPC1311/13/42/43 HVQFN33 pin description table …continued

Pin Start Type Reset Description

logic

input

state

[1]

PIO1_7/TXD/

CT32B0_MAT1

32^[3]yes

I/O

O

I; PU PIO1_7 — General purpose digital input/output pin.

-

TXD — Transmitter output for UART.

O

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0

7^[3]yes

12^[3]yes

20^[5]yes

I/O

I

I; PU PIO1_8 — General purpose digital input/output pin.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

I; PU PIO1_9 — General purpose digital input/output pin.

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

I; PU PIO1_10 — General purpose digital input/output pin.

-

PIO1_9/

CT16B1_MAT0

I/O

O

-

PIO1_10/AD6/

CT16B1_MAT1

I/O

I

-

AD6 — A/D converter, input 6.

O

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7

PIO2_0/DTR

27^[5]yes

1^[3]yes

I/O

I

I; PU PIO1_11 — General purpose digital input/output pin.

AD7 — A/D converter, input 7.

I; PU PIO2_0 — General purpose digital input/output pin.

DTR — Data Terminal Ready output for UART.

-

I/O

O

-

PIO3_2

PIO3_4

PIO3_5

USB_DM

USB_DP

V_DD

28^[3]yes

13^[3]no

14^[3]no

13^[6]no

14^[6]no

I/O

I

I; PU PIO3_2 — General purpose digital input/output pin.

I; PU PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).

I; PU PIO3_5 — General purpose digital input/output pin (LPC1311/13 only).

F

-

USB_DM — USB bidirectional D− line (LPC1342/43 only).

USB_DP — USB bidirectional D+ line (LPC1342/43 only).

6;

-

3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

29

XTALIN

4^[7]

-

I

-

Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT

V_SS

5^[7]

33

-

O

-

Output from the oscillator amplifier.

Thermal pad. Connect to ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for V_DD= 3.3 V, pin is pulled up to 2.6 V for

parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled.

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See Figure 37 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the

Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 36).

[4] I²C-bus pads compliant with the I²C-bus specification for I²C standard mode and I²C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 36).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

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32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to TCM interfaces: one bus dedicated for instruction

fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for

simultaneous operations if concurrent operations target different devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptible/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller, and multiple core buses

capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual which is available on the official ARM website.

7.3 On-chip flash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or

8 kB (LPC1311) of on-chip flash memory.

7.4 On-chip SRAM

The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (LPC1342

and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC1311/13/42/43 incorporate several distinct memory regions. Figure 6 shows the

overall map of the entire address space from the user program viewpoint following reset.

The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

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AHB peripherals

0x5020 0000

LPC1311/13/42/43

4 GB

0xFFFF FFFF

reserved

0xE010 0000

0xE000 0000

16 - 127 reserved

0x5004 0000

private peripheral bus

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

12-15

8-11

4-7

reserved

0x5003 0000

0x5002 0000

0x5020 0000

0x5000 0000

AHB peripherals

0x5001 0000

0x5000 0000

0-3

reserved

APB peripherals

23 - 31 reserved

0x4008 0000

0x4005 C000

0x4005 8000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4008 0000

0x4000 0000

SSP1 (LPC1313FBD48/01)

19 - 21 reserved

system control

22

APB peripherals

1 GB

18

17

IOCONFIG

SSP0

reserved

16

15

flash controller

0x4003 C000

0x4003 8000

14

PMU

0x2000 0000

0.5 GB

10 - 13 reserved

reserved

0x4002 8000

0x4002 4000

0x4002 0000

reserved

9

8

7

6

5

4

3

2

0x1FFF 4000

0x1FFF 0000

16 kB boot ROM

USB (LPC1342/43 only)

ADC

0x4001 C000

0x4001 8000

32-bit counter/timer 1

reserved

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x1000 2000

0x1000 1000

0x1000 0000

8 kB SRAM (LPC1313/1343)

4 kB SRAM (LPC1311/1342)

I-code/D-code

memory space

WDT/WWDT

1

0

0x4000 4000

0x4000 0000

reserved

2

I C-bus

0x0000 8000

32 kB on-chip flash (LPC1313/43)

16 kB on-chip flash (LPC1342)

8 kB on-chip flash (LPC1311)

0x0000 4000

0x0000 2000

+ 256 words

active interrupt vectors

0x0000 0400

0x0000 0000

0 GB

002aae723

Fig 6. LPC1311/13/42/43 memory map

7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

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7.6.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC1311/13/42/43, the NVIC supports up to 17 vectored interrupts. In

addition, up to 40 of the individual GPIO inputs are NVIC-vector capable.

• 8 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table.

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.7 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC1311/13/42/43 use accelerated GPIO functions:

• GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can

be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.8.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-up resistors enabled after reset with the exception of

the I²C-bus pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

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• On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up

to 2.6 V (V_DD= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

• On the LPC1311/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) are

pulled up to 3.3 V (V_DD= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG

block.

7.9 USB interface (LPC1342/43 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports

hot-plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The LPC1342/43 USB interface is a device controller with on-chip PHY for device

functions.

7.9.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, and endpoint buffer memory. The

serial interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

7.9.1.1 Features

• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).

• Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per

endpoint (see Table 5).

• Supports Control, Bulk, Isochronous, and Interrupt endpoints.

• Supports SoftConnect feature.

• Double buffer implementation for Bulk and Isochronous endpoints.

Table 5.

Logical

endpoint endpoint

USB device endpoint configuration

Physical

Endpoint type

Direction Packet size

(byte)

Double buffer

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

Control

out

in

64

no

Control

no

Interrupt/Bulk

Isochronous

out

in

64

no

64

no

out

in

64

no

64

no

out

in

64

yes

64

out

in

512

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7.10 UART

32-bit ARM Cortex-M3 microcontroller

The LPC1311/13/42/43 contains one UART.

Support for RS-485/9-bit mode allows both software address detection and automatic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

• Maximum UART data bit rate of 4.5 MBit/s.

• 16-byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.11 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. An additional SSP controller is

available on the LPC1313FBD48/01 package.

The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.11.1 Features

• Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I²C-bus serial I/O controller

The LPC1311/13/42/43 contain one I²C-bus controller.

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The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.12.1 Features

• The I²C-bus interface is a standard I²C-bus compliant interface with true open-drain

pins. The I²C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• The I²C-bus controller supports multiple address recognition and a bus monitor mode.

7.13 10-bit ADC

The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation

ADC with eight channels.

7.13.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to V_DD

.

• 10-bit conversion time ≥ 2.44 μs (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

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7.14 General purpose external event counter/timers

The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers.

The counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.14.1 Features

• A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.15 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.

7.16 Watchdog timer

Remark: The standard Watchdog timer is available on parts LPC1311/13/42/43.

The purpose of the watchdog is to reset the microcontroller within a selectable time

period. When enabled, the watchdog will generate a system reset if the user program fails

to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

7.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

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• Selectable time period from (T_cy(WDCLK)× 256 × 4) to (T_cy(WDCLK)× 2²⁴× 4) in

multiples of T_cy(WDCLK)× 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

7.17 Windowed WatchDog Timer (WWDT)

Remark: The windowed watchdog timer is available on parts LPC1311/01 and

LPC1313/01.

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.17.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK)× 256 × 4) to (T_cy(WDCLK)× 2²⁴× 4) in

multiples of T_cy(WDCLK)× 4.

• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated

watchdog oscillator (WDO). This gives a wide range of potential timing choices of

watchdog operation under different power conditions.

7.18 Clocking and power control

7.18.1 Integrated oscillators

The LPC1311/13/42/43 include three independent oscillators. These are the system

oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can

be used for more than one purpose as required in a particular application.

Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until

switched by software. This allows systems to operate without any external crystal and the

bootloader code to operate at a known frequency.

See Figure 7 for an overview of the LPC1311/13/42/43 clock generation.

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AHB clock 0

(system)

system clock

SYSTEM CLOCK

DIVIDER

AHB clock 1

(ROM)

AHBCLKCTRL

(AHB clock enable)

AHB clocks

2 to 15

14

(memories

and peripherals)

AHBCLKCTRL

AHB clock 16

(IOCONFIG)

AHBCLKCTRL

2

SSP0/1 PERIPHERAL

CLOCK DIVIDER

SSP0/1

UART

IRC oscillator

main clock

UART PERIPHERAL

CLOCK DIVIDER

watchdog oscillator

ARM TRACE

CLOCK DIVIDER

ARM

trace clock

MAINCLKSEL

(main clock select)

SYSTICK TIMER

CLOCK DIVIDER

SYSTICK

timer

IRC oscillator

SYSTEM PLL

system oscillator

IRC oscillator

WDT CLOCK

DIVIDER

WDT

USB

SYSPLLCLKSEL

watchdog oscillator

(system PLL clock select)

WDTUEN

(WDT clock update enable)

USB PLL

system oscillator

USB 48 MHz CLOCK

DIVIDER

USBPLLCLKSEL

(USB clock select)

USBUEN

(USB clock update enable)

IRC oscillator

system oscillator

watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aae859

The USB clock is available on LPC1342/43 only. SSP1 is available on LPC1313FBD48/01 only.

Fig 7. LPC1311/13/42/43 clocking generation block diagram

7.18.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC

is trimmed to 1 % accuracy over the entire voltage and temperature range.

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Upon power-up, any chip reset, or wake-up from Deep power-down mode, the

LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of

the other available clock sources.

7.18.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. On the LPC1342/43, the system oscillator must be used to provide the clock

source to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.18.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and

temperature is 40 % (see also Table 16).

7.18.2 System PLL and USB PLL

The LPC1342/43 contain a system PLL and a dedicated PLL for generating the 48 MHz

USB clock. The LPC131x contain the system PLL only. The system and USB PLLs are

identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output

frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 μs.

7.18.3 Clock output

The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.18.4 Wake-up process

The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

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7.18.5 Power control

The LPC1311/13/42/43 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Selected peripherals have

their own clock divider which provides even better power control.

7.18.5.1 Power profiles (LPC1300L series, LPC1311/01 and LPC1313/01 only)

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC1311/01 and the LPC1313/01 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

7.18.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.18.5.3 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows

for additional power savings.

Up to 40 pins total can serve as external wake-up pins to the start logic to wake up the

chip from Deep-sleep mode (see Section 7.19.1).

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

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7.18.5.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the

WAKEUP pin.

A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.19 System control

7.19.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 and Table 4 as input to the start logic has an individual interrupt in the

NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when

the chip is running. In addition, an input signal on the start logic pins can wake up the chip

from Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.19.2 Reset

Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset,

power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the flash controller.

When the internal reset is removed, the processor begins executing at address 0, which is

initially the reset vector mapped from the boot block. At that point, all of the processor and

peripheral registers have been initialized to predetermined values.

7.19.3 Brownout detection

The LPC1311/13/42/43 includes four levels for monitoring the voltage on the V_DDpin. If

this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal

to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading

a dedicated status register. An additional threshold level can be selected to cause a

forced reset of the chip.

7.19.4 Code security (Code Read Protection - CRP)

This feature of the LPC1311/13/42/43 allows user to enable different levels of security in

the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. In-Application

Programming (IAP) commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP (NO_ISP

mode). For details see the LPC13xx user manual.

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There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

7.19.5 Boot loader

The boot loader controls initial operation after reset and also provides the means to

program the flash memory. This could be initial programming of a blank device, erasure

and re-programming of a previously programmed device, or programming of the flash

memory by the application program in a running system.

The boot loader code is executed every time the part is reset or powered up. The loader

can either execute the ISP command handler or the user application code, or, on the

LPC1342/43, it can program the flash image via an attached MSC device through USB

(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is

considered as an external hardware request to start the ISP command handler or the USB

device enumeration. The state of PIO0_3 determines whether the UART or USB interface

will be used (LPC1342/43 only).

7.19.6 APB interface

The APB peripherals are located on one APB bus.

7.19.7 AHB-Lite

The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM

Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.

7.19.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.19.1).

7.19.9 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

Register contained in the NVIC.

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The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 256 word boundary.

7.20 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.

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8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

V_DD

supply voltage (core and

external rail)

2.0

3.6

V

[2]

V_I

input voltage

5 V tolerant I/O pins; only valid

when the V_DDsupply voltage is

present

−0.5

+5.5

V

I_DD

supply current

per supply pin

-

100

mA

I_SS

ground current

I/O latch-up current

per ground pin

−(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 °C

I_latch

[3]

[4]

T_stg

storage temperature

non-operating

−65

+150

150

1.5

°C

W

T_j(max)

P_tot(pack)

maximum junction temperature

-

total power dissipation (per

package)

based on package heat transfer, not

device power consumption

V_ESD

electrostatic discharge voltage human body model; all pins

−6500

+6500

V

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC specification J-STD-033B.1 for further details.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

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9. Static characteristics

Table 7.

Static characteristics

T

_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Conditions

Min

Typ^[1]

Max

Unit

[2]

V_DD

supply voltage (core

and external rail)

2.0

3.3

3.6

V

LPC1300 series (LPC1311/13/42/43) power consumption

I_DD

supply current

Active mode; V_DD= 3.3 V;

T_amb= 25 °C; code

while(1){}

executed from flash;

system clock = 12 MHz

[3][4][5]

[6][7]

-

4

-

mA

[4][5][6]

[8][7]

system clock = 72 MHz

17

2

[3][4][5]

[6][7]

Sleep mode;

V_DD= 3.3 V; T_amb= 25 °C;

system clock = 12 MHz

[4][9][7]

[10]

Deep-sleep mode; V_DD= 3.3 V;

T_amb= 25 °C

-

30

-

μA

Deep power-down mode;

220

nA

V_DD= 3.3 V; T_amb= 25 °C

LPC1300L series (LPC1311/01, LPC1313/01) power consumption in low-current mode^[11]

I_DD

supply current

Active mode; V_DD= 3.3 V;

T_amb= 25 °C; code

while(1){}

executed from flash;

system clock = 12 MHz

[3][4][5]

[6][7]

-

2

-

mA

[4][5][6]

[8][7]

system clock = 72 MHz

13

1

[3][4][5]

[6][7]

Sleep mode;

V_DD= 3.3 V; T_amb= 25 °C;

system clock = 12 MHz

[4][9][7]

[10]

Deep-sleep mode; V_DD= 3.3 V;

T_amb= 25 °C

-

2

-

μA

Deep power-down mode;

220

nA

V_DD= 3.3 V; T_amb= 25 °C

Standard port pins and RESET pin; see Figure 21, Figure 22, Figure 23, Figure 24

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

-

10

5.0

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD; on-chip pull-down resistor

disabled

-

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

[12][13]

[14]

input voltage

pin configured to provide a digital

function

0

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Table 7.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

0

Typ^[1]

Max

V_DD

-

Unit

V

V_O

output voltage

output active

-

V_IH

HIGH-level input

voltage

0.7V_DD

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

V

HIGH-level output

voltage

2.5 V ≤ V_DD≤ 3.6 V; I_OH= −4 mA

2.0 V ≤ V_DD< 2.5 V; I_OH= −3 mA

2.5 V ≤ V_DD≤ 3.6 V; I_OL= 4 mA

2.0 V ≤ V_DD< 2.5 V; I_OL= 3 mA

2.5 V≤ V_DD≤ 3.6 V;

V_DD− 0.4

-

V

V_DD− 0.4

-

V

V_OL

LOW-level output

voltage

-

0.4

-

V

-

V

I_OH

HIGH-level output

current

−4

mA

V_OH= V_DD− 0.4 V

2.0 V ≤ V_DD< 2.5 V;

V_OH= V_DD− 0.4 V

−3

-

mA

I_OL

LOW-level output

current

2.5 V ≤ V_DD≤ 3.6 V; V_OL= 0.4 V

2.0 V ≤ V_DD< 2.5 V; V_OL= 0.4 V

4

3

-

mA

-

[15]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

−45

LOW-level short-circuit V_OL= V_DD

output current

-

50

mA

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

μA

V_I= 0 V

V_DD< V_I< 5 V

High-drive output pin (PIO0_7); see Figure 19 and Figure 21

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

-

10

5.0

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD; on-chip pull-down resistor

disabled

-

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

[12][13]

[14]

input voltage

pin configured to provide a digital

function

0

V_O

output voltage

output active

0

-

V_DD

-

V

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

HIGH-level output

voltage

2.5 V ≤ V_DD≤ 3.6 V; I_OH= −20 mA

2.0 V ≤ V_DD< 2.5 V; I_OH= −12 mA

2.5 V ≤ V_DD≤ 3.6 V; I_OL= 4 mA

2.0 V ≤ V_DD< 2.5 V; I_OL= 3 mA

V_DD− 0.4

-

V_DD− 0.4

-

V_OL

LOW-level output

voltage

-

0.4

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Table 7.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

I_OHHIGH-level output

2.5 V ≤ V_DD≤ 3.6 V;

V_OH= V_DD− 0.4 V

20

-

mA

current

2.0 V ≤ V_DD< 2.5 V;

12

-

mA

V

_OH= V_DD− 0.4 V;

I_OL

LOW-level output

current

2.5 V ≤ V_DD≤ 3.6 V; V_OL= 0.4 V

2.0 V ≤ V_DD< 2.5 V; V_OL= 0.4 V

V_I= 5 V

4

-

mA

μA

3

-

I_pd

I_pu

pull-down current

pull-up current

10

−15

0

50

−50

0

150

−85

0

V_I= 0 V

V_DD< V_I< 5 V

I²C-bus pins (PIO0_4 and PIO0_5); see Figure 20

V_IH

HIGH-level input

voltage

0.7V_DD

-

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

-

V

V_hys

I_OL

0.05V_DD

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins configured

as standard mode pins

2.5 V ≤ V_DD≤ 3.6 V

2.0 V ≤ V_DD< 2.5 V

3.5

3.0

-

mA

I_OL

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins configured

as Fast-mode Plus pins

2.5 V ≤ V_DD≤ 3.6 V

2.0 V ≤ V_DD< 2.5 V

V_I= V_DD

20

16

-

mA

-

[16]

I_LI

input leakage current

2

10

4

22

μA

V_I= 5 V

-

Oscillator pins

V_i(xtal)crystal input voltage

V_o(xtal)crystal output voltage

USB pins (LPC1342/43 only)

−0.5

+1.8

+1.95

V

[17]

I_OZ

OFF-state output

current

0 V < V_I< 3.3 V

-

10

μA

[17]

V_BUS

V_DI

bus supply voltage

-

5.25

-

V

differential input

sensitivity voltage

|(D+) − (D−)|

0.2

[17]

V_CM

differential common

mode voltage range

includes V_DIrange

0.8

-

2.5

2.0

V

V_th(rs)sesingle-ended receiver

switching threshold

voltage

[17]

V_OL

LOW-level output

voltage

for low-/full-speed;

R_Lof 1.5 kΩ to 3.6 V

-

0.18

V

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Table 7.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

[17]

V_OH

HIGH-level output

voltage

driven; for low-/full-speed;

R_Lof 15 kΩ to GND

2.8

-

3.5

V

[17]

C_trans

Z_DRV

transceiver capacitance pin to GND

-

20

pF

[18][17]

driver output

with 33 Ω series resistor; steady state

drive

36

44.1

Ω

impedance for driver

which is not high-speed

capable

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] For LPC1342 and LPC1343 only: For USB operation 3.0 V ≤ V_DD≤ 3.6 V. Guaranteed by design.

[3] IRC enabled; system oscillator disabled; system PLL disabled.

[4]

I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in

the syscon block.

[7] For LPC1342/43: USB_DP and USB_DM pulled LOW externally.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.

[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.

[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[12] Including voltage on outputs in 3-state mode.

[13] V_DDsupply voltage must be present.

[14] 3-state outputs go into 3-state mode in Deep power-down mode.

[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[16] To V_SS

.

[17] 3.0 V ≤ V_DD≤ 3.6 V.

[18] Includes external resistors of 33 Ω 1 % on USB_DP and USB_DM.

Table 8.

ADC static characteristics

T_amb= −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, V_DD= 2.5 V to 3.6 V.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DD

1

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

C_ia

pF

[1][2]

[3]

E_D

1

LSB

%

E_L(adj)

E_O

1.5

3.5

0.6

4

[4]

[5]

E_G

gain error

[6]

E_T

absolute error

LSB

kΩ

R_vsi

voltage source interface

resistance

40

[7][8]

R_i

input resistance

-

2.5

MΩ

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 8.

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[3] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 8.

[4] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 8.

[5] The gain error (E_G) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 8.

[6] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 8.

[7] T_amb= 25 °C; maximum sampling frequency f_s= 400 kSamples/s and analog input capacitance C_ia= 1 pF.

[8] Input resistance R_idepends on the sampling frequency f_s: R_i= 1 / (f_s× C_ia).

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offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

(LSB

)

ideal

IA

offset error

E

O

V

− V

SS

DD

1 LSB =

1024

002aaf426

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 8. ADC characteristics

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9.1 BOD static characteristics for LPC1300 series

Remark: Applies to parts LPC1311/13/42/43 and all their packages.

Table 9.

BOD static characteristics^[1]

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 0

assertion

-

1.69

1.84

-

V

de-assertion

interrupt level 1

assertion

-

2.29

2.44

-

V

de-assertion

interrupt level 2

assertion

-

2.59

2.74

-

V

de-assertion

interrupt level 3

assertion

-

2.87

2.98

-

V

de-assertion

reset level 0

assertion

-

1.49

1.64

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx

user manual.

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9.2 BOD static characteristics for LPC1300L series (LPC1311/01 and

LPC1313/01)

Remark: Applies to parts LPC1311/01 and LPC1313/01 and all packages.

Table 10. BOD static characteristics^[1]

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 0

assertion

-

1.65

1.80

-

V

de-assertion

interrupt level 1

assertion

-

2.22

2.35

-

V

de-assertion

interrupt level 2

assertion

-

2.52

2.66

-

V

de-assertion

interrupt level 3

assertion

-

2.80

2.90

-

V

de-assertion

reset level 0

assertion

-

1.46

1.63

-

V

de-assertion

reset level 1

assertion

-

2.06

2.15

-

V

de-assertion

reset level 2

assertion

-

2.35

2.43

-

V

de-assertion

reset level 3

assertion

-

2.63

2.71

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx

user manual.

9.3 Power consumption for LPC1300 series

Remark: Applies to parts LPC1311/13/42/43 and all their packages.

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions (see LPC13xx user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

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002aae993

18

I

72 MHz

DD

(mA)

15

12

9

48 MHz

36 MHz

24 MHz

12 MHz

6

3

2.0

2.4

2.8

3.2

3.6

V

(V)

DD

Conditions: T_amb= 25 °C; Active mode entered executing code while(1){} from flash;

internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled;

all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all

peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).

Fig 9. Typical supply current versus regulator supply voltage V_DDin Active mode

(LPC1311/13/42/43)

002aae994

18

I

DD

72 MHz

(mA)

15

48 MHz

36 MHz

24 MHz

12

9

6

12 MHz

3

−40

−15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; Active mode entered executing code while(1){} from flash; internal

pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).

Fig 10. Typical supply current versus temperature in Active mode (LPC1311/13/42/43)

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002aae995

10

72 MHz

I

DD

(mA)

8

6

4

2

0

48 MHz

36 MHz

24 MHz

12 MHz

−40

−15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system

oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP

and USB_DM pulled LOW externally (LPC1342/43).

Fig 11. Typical supply current versus temperature in Sleep mode (LPC1311/13/42/43)

002aae998

80

I

DD

(μA)

60

V

= 3.6 V

3.3 V

DD

2.0 V

40

20

0

−40

−15

10

35

60

85

temperature (°C)

Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG

register; PDSLEEPCFG = 0x0000 0FFF; USB_DP and USB_DM pulled LOW externally

(LPC1342/43).

Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks

disabled; LPC1311/13/42/43)

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002aae996

1.2

I

DD

(μA)

0.6

VDD = 3.6 V

3.3 V

2.0 V

0.4

0

−40

−15

10

35

60

85

temperature (°C)

Fig 13. Typical supply current versus temperature in Deep power-down mode

(LPC1311/13/42/43)

9.4 Power consumption for LPC1300L series (LPC1311/01 and

LPC1313/01)

Remark: Applies to parts LPC1311/01 and LPC1313/01 and all their packages.

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions (see LPC13xx user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

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002aag235

16

I

DD

(mA)

72 MHz

48 MHz

12

8

4

0

36 MHz

24 MHz

12 MHz

2.0

2.4

2.8

3.2

3.6

V

(V)

DD

Conditions: T_amb= 25 °C; Active mode entered executing code while(1){} from flash;

internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled;

all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all

peripheral clocks disabled; low-current mode.

Fig 14. Typical supply current versus regulator supply voltage V_DDin Active mode

(LPC1311/01 and LPC1313/01)

002aag236

16

I

DD

(mA)

72 MHz

12

48 MHz

36 MHz

24 MHz

12 MHz

8

4

0

˗40

˗15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; Active mode entered executing code while(1){} from flash; internal

pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; low-current mode.

Fig 15. Typical supply current versus temperature in Active mode (LPC1311/01 and

LPC1313/01)

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002aag237

8

6

4

2

0

72 MHz

I

DD

(mA)

48 MHz

36 MHz

24 MHz

12 MHz

˗40

˗15

10

35

60

85

temperature (°C)

Conditions: V_DD= 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system

oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled;

low-current mode.

Fig 16. Typical supply current versus temperature in Sleep mode (LPC1311/01 and

LPC1313/01)

002aag238

8

I

DD

(μA)

6

4

2

0

VDD = 2.0 V

3.3 V

3.6 V

˗40

˗15

10

35

60

85

temperature (°C)

Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG

register; PDSLEEPCFG = 0x0000 0FFF.

Fig 17. Typical supply current versus temperature in Deep-sleep mode (analog blocks

disabled, LPC1311/01 and LPC1313/01)

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002aag239

0.6

I

DD

(µA)

VDD = 3.6 V

3.3 V

0.4

2.0 V

0.2

0

˗40

˗15

10

35

60

85

temperature (°C)

Fig 18. Typical supply current versus temperature in Deep power-down mode

(LPC1311/01 and LPC1313/01)

9.5 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or

PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers

and no code is executed. Measured on a typical sample at T_amb= 25 °C. Unless noted

otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and

72 MHz.

Table 11. Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in mA

Notes

n/a

12 MHz 48 MHz 72 MHz

IRC

0.23

-

System oscillator running; PLL off; independent of main clock

frequency.

System oscillator 0.23

at 12 MHz

IRC running; PLL off; independent of main clock frequency.

Watchdog

oscillator at

500 kHz/2

0.002

System oscillator running; PLL off; independent of main clock

frequency.

BOD

0.045

-

Independent of main clock frequency.

Main or USB PLL

ADC

-

0.26

0.07

0.14

0.01

0.34

0.25

0.56

0.05

0.04

0.05

0.04

0.48

0.37

0.82

0.08

0.06

0.07

0.06

-

CLKOUT

CT16B0

CT16B1

CT32B0

CT32B1

Main clock divided by 4 in the CLKOUTDIV register.

-

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Table 11. Power consumption for individual analog and digital blocks …continued

Peripheral

Typical supply current in mA

Notes

n/a

12 MHz 48 MHz 72 MHz

GPIO

-

0.21

0.80

1.17

GPIO pins configured as outputs and set to LOW. Direction

and pin state are maintained if the GPIO is disabled in the

SYSAHBCLKCFG register.

IOCONFIG

I2C

-

0.00

0.03

0.04

0.11

0.20

0.01

-

0.02

0.12

0.15

0.41

0.76

0.05

3.91

0.02

0.17

0.22

0.60

1.11

0.08

-

ROM

-

SSP0

SSP1

UART

WDT

-

On LPC1313FBD48/01 only.

-

Main clock selected as clock source for the WDT.

USB

Main clock selected as clock source for the USB. USB_DP

and USB_DM pulled LOW externally.

USB

-

1.84

4.19

5.71

Dedicated USB PLL selected as clock source for the USB.

USB_DP and USB_DM pulled LOW externally.

9.6 Electrical pin characteristics

002aae990

3.6

V

(V)

OH

T = 85 °C

25 °C

−40 °C

3.2

2.8

2.4

2

0

10

20

30

40

50

60

I

(mA)

OH

Conditions: V_DD= 3.3 V; on pin PIO0_7.

Fig 19. High-drive output: Typical HIGH-level output voltage V_OHversus HIGH-level

output current I_OH

.

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002aaf019

60

I

T = 85 °C

25 °C

−40 °C

OL

(mA)

40

20

0

0.2

0.4

0.6

V

(V)

OL

Conditions: V_DD= 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 20. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus

LOW-level output voltage V_OL

002aae991

15

I

OL

T = 85 °C

25 °C

−40 °C

(mA)

10

5

0

0.2

0.4

0.6

V

(V)

OL

Conditions: V_DD= 3.3 V; standard port pins and PIO0_7.

Fig 21. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

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002aae992

3.6

V

OH

(V)

T = 85 °C

25 °C

−40 °C

3.2

2.8

2.4

2

0

8

16

24

I

(mA)

OH

Conditions: V_DD= 3.3 V; standard port pins.

Fig 22. Typical HIGH-level output voltage V_OHversus HIGH-level output source current

I_OH

002aae988

10

I

pu

(μA)

−10

−30

−50

−70

T = 85 °C

25 °C

−40 °C

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 3.3 V; standard port pins.

Fig 23. Typical pull-up current I_puversus input voltage V_i

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002aae989

80

T = 85 °C

25 °C

−40 °C

I

pd

(μA)

60

40

20

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 3.3 V; standard port pins.

Fig 24. Typical pull-down current I_pdversus input voltage V_i

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10. Dynamic characteristics

10.1 Power-up ramp conditions

Table 12. Power-up characteristics

_amb= −40 °C to +85 °C.

T

Symbol Parameter

Conditions

Min

0

Typ

Max

500

-

Unit

ms

μs

[1]

t_r

rise time

at t = t₁: 0 < V_I≤ 400 mV

-

[1][2]

t_wait

V_I

wait time

12

0

input voltage

at t = t₁on pin V_DD

400

mV

[1] See Figure 25.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t

r

V

DD

400 mV

0

t

wait

t = t

1

002aag001

Condition: 0 < V_I≤ 400 mV at start of power-up (t = t₁)

Fig 25. Power-up ramp

10.2 Flash memory

Table 13. Flash characteristics

T_amb= −40 °C to +85 °C, unless otherwise specified.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

Typ

Max

Unit

[1]

10000

10

100000

-

cycles

years

ms

retention time

powered

-

unpowered

20

-

t_er

erase time

sector or multiple

95

100

105

consecutive sectors

[2]

t_prog

programming time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

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10.3 External clock

Table 14. Dynamic characteristic: external clock

T_amb= −40 °C to +85 °C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk)× 0.4

-

ns

T_cy(clk)× 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 26. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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10.4 Internal oscillators

Table 15. Dynamic characteristics: IRC

T_amb= −40 °C to +85 °C; 2.7 V ≤ V_DD≤ 3.6 V^[1].

Symbol

Parameter

Conditions

Min

Typ^[2]

Max

Unit

f_osc(RC)

internal RC oscillator frequency

-

11.88

12

12.12

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

002aae987

12.15

V

= 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

DD

f

(MHz)

12.05

11.95

11.85

−40

−15

10

35

60

85

temperature (°C)

Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for

2.7 V ≤ V_DD≤ 3.6 V and T_amb= −40 °C to +85 °C. Variations between parts may cause the IRC to

fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.

Fig 27. Internal RC oscillator frequency f versus temperature

Table 16. Dynamic characteristics: Watchdog oscillator

Symbol Parameter

f_osc(int)internal oscillator frequency

Conditions

Min Typ^[1]

Max Unit

[2][3]

DIVSEL = 0x1F, FREQSEL = 0x1 in the

WDTOSCCTRL register;

-

7.8

-

kHz

DIVSEL = 0x00, FREQSEL = 0xF in the

WDTOSCCTRL register

-

1700

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= −40 °C to +85 °C) is 40 %.

[3] See the LPC13xx user manual.

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10.5 I/O pins

Table 17. Dynamic characteristics: I/O pins^[1]

T_amb= −40 °C to +85 °C; 3.0 V ≤ V_DD≤ 3.6 V.

Symbol

Parameter

rise time

fall time

Conditions

Min

3.0

2.5

Typ

Max

5.0

Unit

ns

t_r

t_f

pin configured as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

10.6 I²C-bus

Table 18. Dynamic characteristic: I²C-bus pins^[1]

T_amb= −40 °C to +85 °C.^[2]

Symbol

Parameter

Conditions

Min

Max

100

400

1

Unit

f_SCL

SCL clock

frequency

Standard-mode

Fast-mode

0

-

kHz

MHz

ns

Fast-mode Plus

[4][5][6][7]

t_f

fall time

of both SDA and SCL

signals

300

Standard-mode

Fast-mode

20 + 0.1 × C_b

300

ns

μs

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of the

SCL clock

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

HIGH period of the

SCL clock

Fast-mode Plus

Standard-mode

Fast-mode

[3][4][8]

[9][10]

t_HD;DAT

data hold time

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] See the I²C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

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[8] The maximum t_HD;DATcould be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t_VD;ACKby a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the

SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 28. I²C-bus pins clock timing

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10.7 SSP0/1 interface

Remark: The SSP1 interface is available on the LPC1313FBD48/01 only.

Table 19. Dynamic characteristics: SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Max

Unit

SSP master

T_cy(clk)

[1]

[2]

clock cycle time

data set-up time

full-duplex mode

when only transmitting

in SPI mode;

40

-

ns

27.8

15

t_DS

2.4 V ≤ V_DD≤ 3.6 V

2.0 V ≤ V_DD< 2.4 V

in SPI mode

[2]

20

0

-

ns

t_DH

data hold time

-

t_v(Q)

data output valid time

data output hold time

in SPI mode

-

10

-

t_h(Q)

in SPI mode

0

SSP slave

T_cy(PCLK)

t_DS

PCLK cycle time

data set-up time

13.9

-

ns

[3][4]

in SPI mode

0

-

t_DH

data hold time

3 × T_cy(PCLK)+ 4

-

t_v(Q)

data output valid time

data output hold time

-

3 × T_cy(PCLK)+ 11

2 × T_cy(PCLK)+ 5

t_h(Q)

[1] T_cy(clk)= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2] T_amb= −40 °C to +85 °C.

[3]

T_cy(clk)= 12 × T_cy(PCLK).

[4] T_amb= 25 °C; V_DD= 3.3 V.

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T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Fig 29. SSP master timing in SPI mode

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T

t

clk(L)

cy(clk)

clk(H)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Fig 30. SSP slave timing in SPI mode

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10.8 USB interface (LPC1342/43 only)

Table 20. Dynamic characteristics: USB pins (full-speed)

C_L= 50 pF; R_pu= 1.5 kΩ on D+ to V_DD, unless otherwise specified. 3.0 V ≤ V_DD≤ 3.6 V

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

8.5

7.7

-

Typ

Max

13.8

13.7

109

Unit

ns

t_r

-

t_f

ns

t_FRFM

differential rise and fall time

matching

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

−2

-

2.0

175

+5

V

t_FEOPT

t_FDEOP

see Figure 31

ns

source jitter for differential transition see Figure 31

to SE0 transition

t_JR1

receiver jitter to next transition

−18.5

−9

-

+18.5

ns

t_JR2

receiver jitter for paired transitions

EOP width at receiver

10 % to 90 %

+9

-

[1]

t_EOPR1

must reject as

EOP; see

Figure 31

40

t_EOPR2

EOP width at receiver

must accept as

EOP; see

82

-

ns

Figure 31

[1] Characterized but not implemented as production test. Guaranteed by design.

T

PERIOD

crossover point

extended

crossover point

differential

data lines

source EOP width: t

FEOPT

differential data to

SE0/EOP skew

n × T

+ t

PERIOD

FDEOP

receiver EOP width: t

, t

EOPR1 EOPR2

002aab561

Fig 31. Differential data-to-EOP transition skew and EOP width

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11. Application information

11.1 Suggested USB interface solutions (LPC1342/43 only)

V

DD

USB_CONNECT

LPC134x

soft-connect switch

R1

1.5 kΩ

USB_VBUS

R

= 33 Ω

S

USB-B

connector

USB_DP

USB_DM

R

V

SS

002aae608

Fig 32. LPC1342/43 USB interface on a self-powered device

V

DD

LPC134x

R1

1.5 kΩ

USB_VBUS

USB-B

connector

R

= 33 Ω

S

USB_DP

R

S

USB_DM

V

SS

002aae609

Fig 33. LPC1342/43 USB interface on a bus-powered device

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV(RMS) is needed.

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LPC1xxx

XTALIN

C

i

C

g

100 pF

002aae788

Fig 34. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 34), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 35 and in

Table 21 and Table 22. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, C_Land

R_S). Capacitance C_Pin Figure 35 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer.

LPC1xxx

L

XTALIN

XTALOUT

C

L

C

P

=

XTAL

R

S

C

X2

C

X1

002aaf424

Fig 35. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

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Table 21. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

1 MHz - 5 MHz

10 pF

< 300 Ω

< 200 Ω

< 100 Ω

< 160 Ω

< 60 Ω

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz - 10 MHz

10 pF

20 pF

30 pF

10 MHz - 15 MHz

15 MHz - 20 MHz

10 pF

20 pF

10 pF

< 80 Ω

Table 22. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz - 20 MHz

10 pF

< 180 Ω

< 100 Ω

< 160 Ω

< 80 Ω

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz - 25 MHz

10 pF

20 pF

11.3 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1, C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

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11.4 Standard I/O pad configuration

Figure 36 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Analog input

V

DD

ESD

output enable

pin configured

as digital output

driver

output

ESD

V

DD

V

SS

weak

pull-up

pull-up enable

weak

pull-down

repeater mode

enable

pin configured

as digital input

pull-down enable

data input

select analog input

pin configured

as analog input

analog input

002aaf304

Fig 36. Standard I/O pad configuration

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11.5 Reset pad configuration

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

002aaf274

Fig 37. Reset pad configuration

11.6 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 8:

• The ADC input trace must be short and as close as possible to the LPC1311/13/42/43

chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply

line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

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11.7 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for the LPC1343FBD48 in Table 23.

Table 23. ElectroMagnetic Compatibility (EMC) for part LPC1343FBD48 (TEM-cell method)

V_DD= 3.3 V; T_amb= 25 °C.

Parameter

Frequency band

System clock =

Unit

12 MHz

24 MHz

48 MHz

72 MHz

Input clock: IRC (12 MHz)

maximum

peak level

150 kHz - 30 MHz

−6

−5

−7

dBμV

30 MHz - 150 MHz

−1

+3

O

+3

+7

N

+9

+15

M

+13

+19

L

dBμV

-

150 MHz - 1 GHz

-

IEC level^[1]

Input clock: crystal oscillator (12 MHz)

maximum

peak level

150 kHz - 30 MHz

-5

−5

−7

dBμV

30 MHz - 150 MHz

0

+4

+8

N

+9

+15

M

+13

+20

L

dBμV

-

150 MHz - 1 GHz

-

3

IEC level^[1]

O

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

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12. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 38. Package outline SOT313-2 (LQFP48)

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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

D

B

A

terminal 1

index area

E

A

1

c

detail X

e

1

C

v

C

A

B

e

b

y

1

y

w

C

9

16

L

8

17

e

E

e

2

h

33

1

24

X

terminal 1

index area

32

25

0

D

h

2.5

scale

5 mm

v

Dimensions

Unit

(1)

A

b

c

D

E

e

1

e

2

L

w

y

1

h

max 1.00 0.05 0.35

mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1

min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45

7.1 4.85 7.1 4.85

0.75

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

hvqfn33_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

- - -

09-03-17

09-03-23

Fig 39. Package outline (HVQFN33)

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13. Soldering

Footprint information for reflow soldering of LQFP48 package

SOT313-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650

sot313-2_fr

Fig 40. Reflow soldering of the LQFP48 package

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Footprint information for reflow soldering of HVQFN33 package

OID = 8.20 OA

PID = 7.25 PA+OA

OwDtot = 5.10 OA

evia = 4.25

0.20 SR

chamfer (4×)

W = 0.30 CU

e = 0.65

SPD = 1.00 SP

0.45 DM

GapD = 0.70 SP

evia = 2.40

B-side

SDhtot = 2.70 SP

Solder resist

covered via

4.55 SR

DHS = 4.85 CU

LbD = 5.80 CU

LaD = 7.95 CU

0.30 PH

0.60 SR cover

0.60 CU

(A-side fully covered)

number of vias: 20

solder land

solder land plus solder paste

solder paste deposit

occupied area

solder resist

Remark:

Stencil thickness: 0.125 mm

Dimensions in mm

001aao134

Fig 41. Reflow soldering of the HVQFN33 package

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14. Abbreviations

Table 24. Abbreviations

Acronym

A/D

Description

Analog-to-Digital

ADC

AHB

AMBA

APB

BOD

EOP

ETM

FIFO

GPIO

HID

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

BrownOut Detection

End Of Packet

Embedded Trace Macrocell

First-In, First-Out

General Purpose Input/Output

Human Interface Device

Input/Output

I/O

LSB

Least Significant Bit

MSC

PHY

PLL

Mass Storage Class

Physical Layer

Phase-Locked Loop

SE0

Single Ended Zero

SPI

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

Start-of-Frame

SSI

SSP

SoF

TCM

TTL

Tightly-Coupled Memory

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

UART

USB

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15. Revision history

Table 25. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC1311_13_42_43 v.5

Modifications:

20120606

Product data sheet

-

LPC1311_13_42_43 v.4

• Parameters V_OL, V_OH, I_OL, I_OHupdated for voltage range 2.0 V ≤ V_DD< 2.5 V in

Table 7.

• Condition “The peak current is limited to 25 times the corresponding maximum

current.” removed from parameters I_DDand I_SSin Table 6.

LPC1311_13_42_43 v.4

LPC1311_13_42_43 v.3

LPC1311_13_42_43 v.2

LPC1311_13_42_43 v.1

20110620

Product data sheet

-

LPC1311_13_42_43 v.3

LPC1311_13_42_43 v.2

LPC1311_13_42_43 v.1

-

20100810

20100506

20091211

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16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

16.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.18.4

7.18.5

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 27

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.18.5.1 Power profiles (LPC1300L series,

3

LPC1311/01 and LPC1313/01 only) . . . . . . . 27

4

4.1

5

7.18.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27

7.18.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 28

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10

7.19

System control . . . . . . . . . . . . . . . . . . . . . . . . 28

Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Brownout detection . . . . . . . . . . . . . . . . . . . . 28

Code security (Code Read Protection - CRP) 28

Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 29

AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External interrupt inputs. . . . . . . . . . . . . . . . . 29

Memory mapping control . . . . . . . . . . . . . . . . 29

Emulation and debugging . . . . . . . . . . . . . . . 30

7.19.1

7.19.2

7.19.3

7.19.4

7.19.5

7.19.6

7.19.7

7.19.8

7.19.9

7.20

7

7.1

7.2

7.3

7.4

7.5

7.6

7.6.1

7.6.2

7.7

7.8

7.8.1

7.9

7.9.1

7.9.1.1

7.10

7.10.1

7.11

7.11.1

7.12

7.12.1

7.13

7.13.1

7.14

Functional description . . . . . . . . . . . . . . . . . . 17

Architectural overview . . . . . . . . . . . . . . . . . . 17

ARM Cortex-M3 processor . . . . . . . . . . . . . . . 17

On-chip flash program memory . . . . . . . . . . . 17

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Nested Vectored Interrupt Controller (NVIC) . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19

IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 19

Fast general purpose parallel I/O . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

USB interface (LPC1342/43 only) . . . . . . . . . 20

Full-speed USB device controller . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SSP serial I/O controller . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I²C-bus serial I/O controller . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

General purpose external event

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

9

9.1

9.2

Static characteristics . . . . . . . . . . . . . . . . . . . 32

BOD static characteristics for LPC1300 series 38

BOD static characteristics for LPC1300L series

(LPC1311/01 and LPC1313/01). . . . . . . . . . . 39

Power consumption for LPC1300 series . . . . 39

Power consumption for LPC1300L series

(LPC1311/01 and LPC1313/01). . . . . . . . . . . 42

Peripheral power consumption . . . . . . . . . . . 45

Electrical pin characteristics. . . . . . . . . . . . . . 46

9.3

9.4

9.5

9.6

10

Dynamic characteristics. . . . . . . . . . . . . . . . . 50

Power-up ramp conditions . . . . . . . . . . . . . . . 50

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 51

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 52

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

I²C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SSP0/1 interface . . . . . . . . . . . . . . . . . . . . . . 55

USB interface (LPC1342/43 only) . . . . . . . . . 58

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

System tick timer . . . . . . . . . . . . . . . . . . . . . . 23

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Windowed WatchDog Timer (WWDT) . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clocking and power control . . . . . . . . . . . . . . 24

Integrated oscillators . . . . . . . . . . . . . . . . . . . 24

7.14.1

7.15

7.16

7.16.1

7.17

7.17.1

7.18

11

11.1

Application information . . . . . . . . . . . . . . . . . 59


型号：	LPC1311_12
厂家：	NXP
描述：	32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device 32位ARM Cortex -M3微控制器;高达32 KB的闪存和8 KB的SRAM ; USB设备闪存微控制器静态存储器
文件：	总74页 (文件大小：1289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC1311_12 [NXP]

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SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB