LPC1764FBD100_技术文档

UM10360

LPC17xx User manual

Rev. 01 — 4 January 2010

User manual

Document information

Info

Content

Keywords

LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759,

LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3,

32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract

LPC17xx user manual

UM10360

NXP Semiconductors

LPC17xx user manual

Revision history

Rev

Date

Description

1

20100104

LPC17xx user manual revision.

Modifications:

• “Draft” status removed.

• Editorial updates and typographical corrections throughout the user manual.

• LPC1758, LPC1767, and LPC1768 have been added to the keywords list on the front cover,

the ordering information in section Section 1–4, and the part identification number table in

Section 32–7.11.

• The note about DMA operation in Sleep mode was removed from Section 4–8.1.

• In Table 8–81, the CLKOUT function was removed from the description of P1.25.

• In section the Ethernet chapter, in Section 10–16.1 and Section 10–17.2, it has been noted

that the external PHY must be initialized and PHY clocks received by the Ethernet block prior

to further initialization of the Ethernet block. Also, in Section 10–17.1, under the heading

"Ownership of descriptors", the sentence about AHB arbitration was removed. A general and

more correct discussion of the subject was added in Section 2–5.

• The UART fractional baud rate generator is disabled in auto baud mode (see

Section 14–14.4.10.1 and Section 15–4.14).

• In section Section 14–4.12 and Section 15–4.16, the description of the value of the DLL

register has been is corrected to read "the value of the DLL register must be greater than 2".

• *** Motor Control PWM ***

• The description of RPM calculation in the QEI chapter (see Section 26–4.3), definitions for the

formula values are added, and the description improved. The description of the position and

index compare registers incorrectly indicated that the less than,equal to, and greater than

compare could be selected. It is changed to only indicate “equal to”.

• A description of Flash signature generation has been added in Section 32–10.

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Chapter 1: LPC17xx Introductory information

Rev. 01 — 4 January 2010

User manual

1. Introduction

The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications

requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a

next generation core that offers system enhancements such as modernized debug

features and a higher level of support block integration.

High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU

frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branches.

The peripheral complement of the LPC17xx includes up to 512 kB of flash memory, up to

64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either

Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN

channels, 2 SSP controllers, SPI interface, 3 I²C interfaces, 2-input plus 2-output I²S

interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder

interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC

with separate battery supply, and up to 70 general purpose I/O pins.

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Chapter 1: LPC17xx Introductory information

2. Features

Refer to Section 1–4.1 for details of features on specific part numbers.

• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed

versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory

Protection Unit (MPU) supporting eight regions is included.

• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. The combination of an enhanced flash

memory accelerator and location of the flash memory on the CPU local code/data bus

provides high code performance from flash.

• Up to 64 kB on-chip SRAM includes:

– Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as

for general purpose instruction and data storage.

• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I²S, UART, the Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, GPIO, and for

memory-to-memory transfers.

• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and

the USB interface. This interconnect provides communication with no arbitration

delays unless two masters attempt to access the same slave at the same time.

• Split APB bus allows for higher throughput with fewer stalls between the CPU and

DMA. A single level of write buffering allows the CPU to continue without waiting for

completion of APB writes if the APB was not already busy.

• Serial interfaces:

– Ethernet MAC with RMII interface and dedicated DMA controller.

– USB 2.0 full-speed controller that can be configured for either device, Host, or

OTG operation with an on-chip PHY for device and Host functions and a dedicated

DMA controller.

– Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA

support. One UART has modem control I/O and RS-485/EIA-485 support.

– Two-channel CAN controller.

– Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces

can be used with the GPDMA controller.

– SPI controller with synchronous, serial, full duplex communication and

programmable data length. SPI is included as a legacy peripheral and can be used

instead of SSP0.

– Three enhanced I²C-bus interfaces, one with an open-drain output supporting the

full I²C specification and Fast mode plus with data rates of 1Mbit/s, two with

standard port pins. Enhancements include multiple address recognition and

monitor mode.

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Chapter 1: LPC17xx Introductory information

– I²S (Inter-IC Sound) interface for digital audio input or output, with fractional rate

control. The I²S interface can be used with the GPDMA. The I²S interface supports

3-wire data transmit and receive or 4-wire combined transmit and receive

connections, as well as master clock output.

• Other peripherals:

– 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with

configurable pull-up/down resistors, open drain mode, and repeater mode. All

GPIOs are located on an AHB bus for fast access, and support Cortex-M3

bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any

pin of ports 0 and 2 can be used to generate an interrupt.

– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA

support.

– Four general purpose timers/counters, with a total of eight capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

– One motor control PWM with support for three-phase motor control.

– Quadrature encoder interface that can monitor one external quadrature encoder.

– One standard PWM/timer block with external count input.

– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a

dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered

backup registers, allowing system status to be stored when the rest of the chip is

powered off. Battery power can be supplied from a standard 3 V Lithium button

cell. The RTC will continue working when the battery voltage drops to as low as

2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.

– Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

– Cortex-M3 system tick timer, including an external clock input option.

– Repetitive interrupt timer provides programmable and repeating timed interrupts.

• Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire

Trace Port options.

• Emulation trace module supports real-time trace.

• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

• Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.

• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0

and PORT2 can be used as edge sensitive interrupt sources.

• Non-maskable Interrupt (NMI) input.

• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,

CPU clock, or the USB clock.

• The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from

any priority interrupt that can occur while the clocks are stopped in deep sleep,

Power-down, and Deep power-down modes.

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Chapter 1: LPC17xx Introductory information

• Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).

• Each peripheral has its own clock divider for further power savings.

• Brownout detect with separate threshold for interrupt and forced reset.

• On-chip Power-On Reset (POR).

• On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.

• 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a

system clock.

• An on-chip PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency crystal. May be run from the main oscillator, the internal RC

oscillator, or the RTC oscillator.

• A second, dedicated PLL may be used for the USB interface in order to allow added

flexibility for the Main PLL settings.

• Versatile pin function selection feature allows many possibilities for using on-chip

peripheral functions.

• Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm)

packages.

3. Applications

• eMetering

• Lighting

• Industrial networking

• Alarm systems

• White goods

• Motor control

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Chapter 1: LPC17xx Introductory information

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1769FBD100

LPC1768FBD100

LPC1767FBD100

LPC1766FBD100

LPC1765FBD100

LPC1764FBD100

LPC1759FBD80

LPC1758FBD80

LPC1756FBD80

LPC1754FBD80

LPC1752FBD80

LPC1751FBD80

LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm

SOT407-1

LQFP80

plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm

SOT315-1

4.1 Part options summary

Table 2.

Ordering options for LPC17xx parts

Type number

Max. CPU Flash

speed

Total

SRAM

Ethernet USB

CAN I²S

DAC Package

LPC1769FBD100

LPC1768FBD100

LPC1767FBD100

LPC1766FBD100

LPC1765FBD100

LPC1764FBD100

LPC1759FBD80

LPC1758FBD80

LPC1756FBD80

LPC1754FBD80

LPC1752FBD80

LPC1751FBD80

120 MHz

100 MHz

120 MHz

100 MHz

512 kB

256 kB

128 kB

512 kB

256 kB

128 kB

64 kB

32 kB

64 kB

32 kB

16 kB

8 kB

yes

no

Device/Host/OTG

2

no

2

1

yes

no

yes

no

100 pin

80 pin

Device/Host/OTG

no

Device/Host/OTG

Device

yes

no

Device/Host/OTG

Device

yes

no

yes

no

yes

no

80 pin

no

80 pin

no

80 pin

32 kB

no

Device

no

80 pin

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Chapter 1: LPC17xx Introductory information

5. Simplified block diagram

Ethernet

Trace

Port

JTAG

interface

PHY

interface

USB

interface

Test/Debug Interface

USB

device,

host,

Clock Generation,

Power Control,

Brownout Detect,

and other

Ethernet

10/100

MAC

DMA

controller

Clocks

and

Controls

ARM Cortex-M3

OTG

system functions

Flash

Accelerator

512 kB

SRAM

64 kB

High Speed GPIO

Multilayer AHB Matrix

ROM

8 kB

AHB to

APB bridge

APB slave group 0

APB slave group 1

SSP1

SSP0

UARTs 0 & 1

CAN 1 & 2

I²C 0 & 1

SPI0

UARTs 2 & 3

I2S

I²C2

Repetitive Interrupt

Timer

Capture/Compare

Timers 0 & 1

Capture/Compare

Timers 2 & 3

Watchdog Timer

PWM1

External Interrupts

DAC

12-bit ADC

System Control

Motor Control PWM

Quadrature Encoder

Pin Connect Block

GPIO Interrupt Ctl

32 kHz

oscillator

Real Time Clock

Note: shaded peripheral blocks

support General Purpose DMA

20 bytes of backup

registers

RTC Power Domain

Fig 1. LPC1768 simplified block diagram

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Chapter 1: LPC17xx Introductory information

6. Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and

D-code buses which are faster and are used similarly to TCM interfaces: one bus

dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of

two core buses allows for simultaneous operations if concurrent operations target different

devices.

The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other

bus masters to peripherals in a flexible manner that optimizes performance by allowing

peripherals on different slaves ports of the matrix to be accessed simultaneously by

different bus masters. Details of the multilayer matrix connections are shown in

Figure 1–2.

APB peripherals are connected to the CPU via two APB busses using separate slave

ports from the multilayer AHB matrix. This allows for better performance by reducing

collisions between the CPU and the DMA controller. The APB bus bridges are configured

to buffer writes so that the CPU or DMA controller can write to APB devices without

always waiting for APB write completion.

7. ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The Cortex-M3 offers many new features,

including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptible/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with Wakeup Interrupt

Controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is

appended to this manual.

7.1 Cortex-M3 Configuration Options

The LPC17xx uses the r2p0 version of the Cortex-M3 CPU, which includes a number of

configurable options, as noted below.

System options:

• The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the

SYSTICK timer.

• The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful

options for waking up the CPU from reduced power modes.

• A Memory Protection Unit (MPU) is included.

• A ROM Table in included. The ROM Table provides addresses of debug components

to external debug systems.

Debug related options:

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• A JTAG debug interface is included.

• Serial Wire Debug is included. Serial Wire Debug allows debug operations using only

2 wires, simple trace functions can be added with a third wire.

• The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction

trace capabilities.

• The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data

address or data value matches to be trace information or trigger other events. The

DWT includes 4 comparators and counters for certain internal events.

• An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in

order to send messages to the trace port.

• The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides

trace information to the outside world. This can be on the Serial Wire Viewer pin or the

4-bit parallel trace port.

• A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware

breakpoints and remap specific addresses in code space to SRAM as a temporary

method of altering non-volatile code. The FPB include 2 literal comparators and 6

instruction comparators.

8. On-chip flash memory system

The LPC17xx contains up to 512 kB of on-chip flash memory. A new two-port flash

memory accelerator maximizes performance for use with the two fast AHB-Lite buses.

This memory may be used for both code and data storage. Programming of the flash

memory may be accomplished in several ways. It may be programmed In System via the

serial port. The application program may also erase and/or program the flash while the

application is running, allowing a great degree of flexibility for data storage field firmware

upgrades, etc.

9. On-chip Static RAM

The LPC17xx contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of SRAM,

accessible by the CPU and all three DMA controllers are on a higher-speed bus. Devices

containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each situated

on separate slave ports on the AHB multilayer matrix.

This architecture allows the possibility for CPU and DMA accesses to be separated in

such a way that there are few or no delays for the bus masters.

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Chapter 1: LPC17xx Introductory information

10. Block diagram

JTAG

interface

Ethernet PHY

interface

USB

interface

Debug Port

CLK

OUT

clock generation,

power control,

and other

TEST/DEBUG

INTERFACE

clocks

and

USB

device,

host,

Ethernet

10/100

MAC

DMA

controller

controls

system functions

OTG

ARM Cortex-M3

Vdd

internal

power

voltage regulator

I-code

bus

D-code System

bus bus

Flash

Accelerator

Flash

512 kB

SRAM

32 kB

ROM

8 kB

SRAM

16 kB

SRAM

16 kB

HS

GPIO

DMAC

regs

USB

regs

Ethernet

regs

AHB to

APB bridge

Multilayer

AHB Matrix

AHB to

APB bridge

APB slave group 1

APB slave group 0

SSP1

SSP0

UARTs 2 & 3

I2S

UARTs 0 & 1

CAN 1 & 2

I²C 0 & 1

I²C2

SPI0

Capture/compare

timers 2 & 3

Capture/compare

timers 0 & 1

Repetitive interrupt

timer

Watchdog timer

PWM1

External interrupts

DAC

12-bit ADC

System control

Motor control PWM

Quadrature encoder

Pin connect block

GPIO interrupt control

32 kHz

oscillator

Real Time Clock

Note: shaded peripheral blocks

support General Purpose DMA

Vbat

ultra-low power

regulator

Backup registers

(20 bytes)

RTC Power Domain

Fig 2. LPC1768 block diagram, CPU and buses

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Chapter 2: LPC17xx Memory map

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1. Memory map and peripheral addressing

The ARM Cortex-M3 processor has a single 4 GB address space. The following table

shows how this space is used on the LPC17xx.

Table 3.

LPC17xx memory usage and details

Address range General Use

Address range details and description

For devices with 512 kB of flash memory.

0x0000 0000 to On-chip non-volatile 0x0000 0000 - 0x0007 FFFF

0x1FFF FFFF

memory

0x0000 0000 - 0x0003 FFFF

0x0000 0000 - 0x0001 FFFF

0x0000 0000 - 0x0000 FFFF

0x0000 0000 - 0x0000 7FFF

0x1000 0000 - 0x1000 7FFF

0x1000 0000 - 0x1000 3FFF

0x1000 0000 - 0x1000 1FFF

0x1FFF 0000 - 0x1FFF 1FFF

0x2007 C000 - 0x2007 FFFF

For devices with 256 kB of flash memory.

For devices with 128 kB of flash memory.

For devices with 64 kB of flash memory.

For devices with 32 kB of flash memory.

For devices with 32 kB of local SRAM.

For devices with 16 kB of local SRAM.

For devices with 8 kB of local SRAM.

8 kB Boot ROM with flash services.

On-chip SRAM

Boot ROM

0x2000 0000 to On-chip SRAM

0x3FFF FFFF

AHB SRAM - bank 0 (16 kB), present on

devices with 32 kB or 64 kB of total SRAM.

(typically used for

peripheral data)

0x2008 0000 - 0x2008 3FFF

AHB SRAM - bank 1 (16 kB), present on

devices with 64 kB of total SRAM.

GPIO

0x2009 C000 - 0x2009 FFFF

0x4000 0000 - 0x4007 FFFF

GPIO.

0x4000 0000 to APB Peripherals

0x5FFF FFFF

APB0 Peripherals, up to 32 peripheral

blocks, 16 kB each.

0x4008 0000 - 0x400F FFFF

0x5000 0000 - 0x501F FFFF

0xE000 0000 - 0xE00F FFFF

APB1 Peripherals, up to 32 peripheral

blocks, 16 kB each.

AHB peripherals

DMA Controller, Ethernet interface, and

USB interface.

0xE000 0000 to Cortex-M3 Private

Cortex-M3 related functions, includes the

NVIC and System Tick Timer.

0xE00F FFFF

Peripheral Bus

2. Memory maps

The LPC17xx incorporates several distinct memory regions, shown in the following

figures. Figure 2–3 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping,

which is described later in this section.

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Figure 2–3 and Table 2–4 show different views of the peripheral address space. The AHB

peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of

their size. This eliminates the need for byte lane mapping hardware that would be required

to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An

implication of this is that word and half-word registers must be accessed all at once. For

example, it is not possible to read or write the upper byte of a word register separately.

3. APB peripheral addresses

The following table shows the APB0/1 address maps. No APB peripheral uses all of the

16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at

multiple locations within each 16 kB range.

Table 4.

APB0 peripherals and base addresses

APB0 peripheral

Base address

0x4000 0000

Peripheral name

0

Watchdog Timer

1

0x4000 4000

Timer 0

2

0x4000 8000

Timer 1

3

0x4000 C000

0x4001 0000

UART0

4

UART1

5

0x4001 4000

reserved

6

0x4001 8000

PWM1

7

0x4001 C000

0x4002 0000

I²C0

8

SPI

9

0x4002 4000

RTC

10

0x4002 8000

GPIO interrupts

Pin Connect Block

SSP1

11

0x4002 C000

0x4003 0000

12

13

0x4003 4000

ADC

14

0x4003 8000

CAN Acceptance Filter RAM

CAN Acceptance Filter Registers

CAN Common Registers

CAN Controller 1

CAN Controller 2

reserved

15

0x4003 C000

0x4004 0000

16

17

0x4004 4000

18

0x4004 8000

19 to 22

23

0x4004 C000 to 0x4005 8000

0x4005 C000

0x4006 0000 to 0x4007 C000

I²C1

24 to 31

reserved

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Table 5.

APB1 peripherals and base addresses

APB1 peripheral

Base address

0x4008 0000

0x4008 4000

0x4008 8000

0x4008 C000

0x4009 0000

0x4009 4000

0x4009 8000

0x4009 C000

0x400A 0000

0x400A 4000

0x400A 8000

0x400A C000

0x400B 0000

0x400B 4000

0x400B 8000

0x400B C000

0x400C 0000 to 0x400F 8000

0x400F C000

Peripheral name

reserved

0

1

reserved

2

SSP0

3

DAC

4

Timer 2

5

Timer 3

6

UART2

7

UART3

8

I²C2

9

reserved

I²S

10

11

reserved

12

Repetitive interrupt timer

reserved

13

14

Motor control PWM

Quadrature Encoder Interface

reserved

15

16 to 30

31

System control

4. Memory re-mapping

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

Register contained in the Cortex-M3. Refer to Section 6–4 and Section 34–4.3.5 of the

Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset

feature.

Boot ROM re-mapping

Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is

normally transparent to the user. However, if execution is halted immediately after reset by

a debugger, it should correct the mapping for the user. See Section 33–6.

5. AHB arbitration

The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3

D-code bus has the highest priority, followed by the I-Code bus. All other masters share a

lower priority.

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Chapter 2: LPC17xx Memory map

6. Bus fault exceptions

The LPC17xx generates Bus Fault exception if an access is attempted for an address that

is in a reserved or unassigned address region. The regions are areas of the memory map

that are not implemented for a specific derivative. These include all spaces marked

“reserved” in Figure 2–3.

For these areas, both attempted data access and instruction fetch generate an exception.

In addition, a Bus Fault exception is generated for any instruction fetch that maps to an

AHB or APB peripheral address.

Within the address space of an existing APB peripheral, an exception is not generated in

response to an access to an undefined address. Address decoding within each peripheral

is limited to that needed to distinguish defined registers within the peripheral itself. For

example, an access to address 0x4000 D000 (an undefined address within the UART0

space) may result in an access to the register defined at address 0x4000 C000. Details of

such address aliasing within a peripheral space are not defined in the LPC17xx

documentation and are not a supported feature.

If software executes a write directly to the flash memory, the flash accelerator will

generate a Bus Fault exception. Flash programming must be accomplished by using the

specified flash programming interface provided by the Boot Code.

Note that the Cortex-M3 core stores the exception flag along with the associated

instruction in the pipeline and processes the exception only if an attempt is made to

execute the instruction fetched from the disallowed address. This prevents accidental

aborts that could be caused by prefetches that occur when code is executed very near a

memory boundary.

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1. Introduction

The system control block includes several system features and control registers for a

number of functions that are not related to specific peripheral devices. These include:

• Reset

• Brown-Out Detection

• External Interrupt Inputs

• Miscellaneous System Controls and Status

• Code Security vs. Debugging

Each type of function has its own register(s) if any are required and unneeded bits are

defined as reserved in order to allow future expansion. Unrelated functions never share

the same register addresses

2. Pin description

Table 3–6 shows pins that are associated with System Control block functions.

Table 6.

Pin name Pin

direction

Pin summary

Pin description

EINT0

Input

External Interrupt Input 0 - An active low/high level or falling/rising

edge general purpose interrupt input. This pin may be used to wake up

the processor from Sleep, Deep-sleep, or Power-down modes.

EINT1

EINT2

EINT3

RESET

Input

External Interrupt Input 1 - See the EINT0 description above.

External Interrupt Input 2 - See the EINT0 description above.

External Interrupt Input 3 - See the EINT0 description above.

External Reset input - A LOW on this pin resets the chip, causing I/O

ports and peripherals to take on their default states, and the processor to

begin execution at address 0x0000 0000.

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3. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

Table 7.

Name

Summary of system control registers

Description

Access Reset value

Address

External Interrupts

EXTINT

External Interrupt Flag Register

External Interrupt Mode register

R/W

0

0x400F C140

0x400F C148

0x400F C14C

EXTMODE

EXTPOLAR External Interrupt Polarity Register

Reset

RSID

Syscon Miscellaneous Registers

SCS System Control and Status

Reset Source Identification Register

R/W

see Table 3–8 0x400F C180

0

0x400F C1A0

4. Reset

Reset has 4 sources on the LPC17xx: the RESET pin, Watchdog Reset, Power On Reset

(POR), and Brown Out Detect (BOD).

The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once

the operating voltage attains a usable level, starts the wake-up timer (see description in

Section 4–9 “Wake-up timer” in this chapter), causing reset to remain asserted until the

external Reset is de-asserted, the oscillator is running, a fixed number of clocks have

passed, and the flash controller has completed its initialization. The reset logic is shown in

the following block diagram (see Figure 3–4).

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Reset to the

on-chip circuitry

external

reset

C

S

Q

watchdog

reset

Reset to

PCON.PD

POR

BOD

WAKE-UP TIMER

START

COUNT 2ⁿ

power-down

C

S

Q

internal RC

oscillator

EINT0 wake-up

EINT1 wake-up

write “1”

from APB

EINT2 wake-up

EINT3 wake-up

RTC wake-up

BOD wake-up

Ethernet MAC wake-up

reset

APB read of

PDBIT

in PCON

USB need_clk wake-up

CAN wake-up

GPIO0 port wake-up

GPIO2 port wake-up

F_OSC

to other

blocks

Fig 4. Reset block diagram including the wake-up timer

On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,

External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time

(maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the

reset signal is latched and synchronized on the IRC clock. Then the following two

sequences start simultaneously:

1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is

de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times

out. The boot code performs the boot tasks and may jump to the flash. If the flash is

not ready to access, the Flash Accelerator will insert wait cycles until the flash is

ready.

2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is

de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it

times out, the flash initialization sequence is started, which takes about 250 cycles.

When it’s done, the Flash Accelerator will be granted access to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Figure 3–5 shows an example of the relationship between the RESET, the IRC, and the

processor status when the LPC17xx starts up after reset. See Section 4–3.2 “Main

oscillator” for start-up of the main oscillator if selected by the user code.

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IRC

starts

stable

IRC status

RESET

V

DD(REG)(3V3)

valid threshold

GND

60 μs

1 μs; IRC stability count

boot time

boot code executing

supply ramp-up

time

user code

processor status

boot code

execution

finishes;

user code starts

Fig 5. Example of start-up after reset

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4.1 Reset Source Identification Register (RSID - 0x400F C180)

This register contains one bit for each source of Reset. Writing a 1 to any of these bits

clears the corresponding read-side bit to 0. The interactions among the four sources are

described below.

Table 8.

Reset Source Identification register (RSID - address 0x400F C180) bit description

Bit

Symbol Description

Reset

value

0

POR

Assertion of the POR signal sets this bit, and clears all of the other bits in See

this register. But if another Reset signal (e.g., External Reset) remains

asserted after the POR signal is negated, then its bit is set. This bit is not

affected by any of the other sources of Reset.

text

1

2

EXTR

Assertion of the RESET signal sets this bit. This bit is cleared by POR, but See

is not affected by WDT or BOD reset. text

WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit See

in the Watchdog Mode Register is 1. It is cleared by any of the other

sources of Reset.

text

3

BODR This bit is set when the V_DD(REG)(3V3)voltage reaches a level below the

BOD reset trip level (typically 1.85 V under nominal room temperature

conditions).

See

text

If the V_DD(REG)(3V3)voltage dips from the normal operating range to below

the BOD reset trip level and recovers, the BODR bit will be set to 1.

If the V_DD(REG)(3V3)voltage dips from the normal operating range to below

the BOD reset trip level and continues to decline to the level at which POR

is asserted (nominally 1 V), the BODR bit is cleared.

If the V_DD(REG)(3V3)voltage rises continuously from below 1 V to a level

above the BOD reset trip level, the BODR will be set to 1.

This bit is not affected by External Reset nor Watchdog Reset.

Note: Only in the case where a reset occurs and the POR = 0, the BODR

bit indicates if the V_DD(REG)(3V3)voltage was below the BOD reset trip level

or not.

31:4

-

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

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5. Brown-out detection

The LPC17xx includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of

the voltage on the V_DD(REG)(3V3)pins. If this voltage falls below the BOD interrupt trip level

(typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt

signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the

signal by reading the Raw Interrupt Status Register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC17xx when

the voltage on the V_DD(REG)(3V3)pins falls below the BOD reset trip level (typically 1.85 V

under nominal room temperature conditions). This Reset prevents alteration of the flash

as operation of the various elements of the chip would otherwise become unreliable due

to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the

Power-On Reset circuitry maintains the overall Reset.

Both the BOD reset interrupt level and the BOD reset trip level thresholds include some

hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level

detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode

(which is itself not a guaranteed operation -- see Section 4–8.7 “Power Mode Control

register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before

the wake-up timer has completed its delay. In this case, the net result of the transient BOD

is that the part wakes up and continues operation after the instructions that set

Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being

0. Since all other wake-up conditions have latching flags (see Section 3–6.2 “External

Interrupt flag register (EXTINT - 0x400F C140)” and Section 27–6.2), a wake-up of this

type, without any apparent cause, can be assumed to be a Brown-Out that has gone

away.

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6. External interrupt inputs

TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. The logic

of an individual external interrupt is represented in Figure 3–6. In addition, external

interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section

4–8.8 “Wake-up from Reduced Power Modes” for details.

wakeup enable

(one bit of EXTWAKE)

APB Read

of EXTWAKE

EINTi to wakeup

timer¹

APB Bus Data

D

Q

GLITCH

FILTER

EINTi

PCLK

interrupt flag

(one bit of EXTINT)

EXTPOLARi

S

1

D

S

R

S

Q

to VIC

Q

R

EXTMODEi

APB read of

EXTINT

PCLK

reset

write 1 to EXTINTi

Fig 6. External interrupt logic

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6.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register

contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level

and edge sensitivity parameters.

Table 9.

Name

External Interrupt registers

Description

Access Reset

value^[1]

Address

EXTINT

The External Interrupt Flag Register contains

interrupt flags for EINT0, EINT1, EINT2 and

EINT3. See Table 3–10.

R/W

0x00

0x400F C140

EXTMODE The External Interrupt Mode Register controls R/W

whether each pin is edge- or level-sensitive.

See Table 3–11.

0x400F C148

0x400F C14C

EXTPOLAR The External Interrupt Polarity Register controls R/W

which level or edge on each pin will cause an

interrupt. See Table 3–12.

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.2 External Interrupt flag register (EXTINT - 0x400F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin

(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in

this register. This asserts the corresponding interrupt request to the NVIC, which will

cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding

bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive

state.

Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling

wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise

event that was just triggered by activity on the EINT pin will not be recognized in future.

Important: whenever a change of external interrupt operating mode (i.e. active

level/edge) is performed (including the initialization of an external interrupt), the

corresponding bit in the EXTINT register must be cleared! For details see Section

3–6.3 “External Interrupt Mode register (EXTMODE - 0x400F C148)” and Section 3–6.4

“External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”.

For example, if a system wakes up from Power-down using low level on external interrupt

0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the

Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke

Power-down mode will fail. The same goes for external interrupt handling.

More details on Power-down mode will be discussed in the following chapters.

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Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description

Bit Symbol Description Reset

value

0

1

2

3

EINT0

EINT1

EINT2

EINT3

In level-sensitive mode, this bit is set if the EINT0 function is selected for

its pin, and the pin is in its active state. In edge-sensitive mode, this bit is

set if the EINT0 function is selected for its pin, and the selected edge

occurs on the pin.

0

This bit is cleared by writing a one to it, except in level sensitive mode

when the pin is in its active state.^[1]

In level-sensitive mode, this bit is set if the EINT1 function is selected for

its pin, and the pin is in its active state. In edge-sensitive mode, this bit is

set if the EINT1 function is selected for its pin, and the selected edge

occurs on the pin.

0

This bit is cleared by writing a one to it, except in level sensitive mode

when the pin is in its active state.^[1]

In level-sensitive mode, this bit is set if the EINT2 function is selected for

its pin, and the pin is in its active state. In edge-sensitive mode, this bit is

set if the EINT2 function is selected for its pin, and the selected edge

occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode

when the pin is in its active state.^[1]

In level-sensitive mode, this bit is set if the EINT3 function is selected for

its pin, and the pin is in its active state. In edge-sensitive mode, this bit is

set if the EINT3 function is selected for its pin, and the selected edge

occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode

when the pin is in its active state.^[1]

31:4 -

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

[1] Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on

corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the

pin becomes high.

6.3 External Interrupt Mode register (EXTMODE - 0x400F C148)

The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins

that are selected for the EINT function (see Section 8–5) and enabled in the appropriate

NVIC register) can cause interrupts from the External Interrupt function (though of course

pins selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is

disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write

the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the

interrupt. An extraneous interrupt(s) could be set by changing the mode and not

having the EXTINT cleared.

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Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit

description

Bit Symbol Value Description

Reset

value

0

1

2

3

EXTMODE0

EXTMODE1

EXTMODE2

EXTMODE3

0

1

0

1

0

1

0

1

-

Level-sensitivity is selected for EINT0.

EINT0 is edge sensitive.

0

Level-sensitivity is selected for EINT1.

EINT1 is edge sensitive.

0

Level-sensitivity is selected for EINT2.

EINT2 is edge sensitive.

0

Level-sensitivity is selected for EINT3.

EINT3 is edge sensitive.

0

31:4 -

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

NA

6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is

high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or

falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are

selected for the EINT function (see Section 8–5) and enabled in the appropriate NVIC

register) can cause interrupts from the External Interrupt function (though of course pins

selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is

disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write

the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the

interrupt. An extraneous interrupt(s) could be set by changing the polarity and not

having the EXTINT cleared.

Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit

description

Bit Symbol

Value Description

Reset

value

0

1

2

EXTPOLAR0

0

1

0

1

0

1

EINT0 is low-active or falling-edge sensitive (depending on

EXTMODE0).

0

EINT0 is high-active or rising-edge sensitive (depending on

EXTMODE0).

EXTPOLAR1

EXTPOLAR2

EINT1 is low-active or falling-edge sensitive (depending on

EXTMODE1).

EINT1 is high-active or rising-edge sensitive (depending on

EXTMODE1).

EINT2 is low-active or falling-edge sensitive (depending on

EXTMODE2).

EINT2 is high-active or rising-edge sensitive (depending on

EXTMODE2).

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Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit

description

Bit Symbol

Value Description

Reset

value

3

EXTPOLAR3

0

1

-

EINT3 is low-active or falling-edge sensitive (depending on

EXTMODE3).

0

EINT3 is high-active or rising-edge sensitive (depending on

EXTMODE3).

31:4 -

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

NA

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7. Other system controls and status flags

Some aspects of controlling LPC17xx operation that do not fit into peripheral or other

registers are grouped here.

7.1 System Controls and Status register (SCS - 0x400F C1A0)

The SCS register contains several control/status bits related to the main oscillator. Since

chip operation always begins using the Internal RC Oscillator, and the main oscillator may

not be used at all in some applications, it will only be started by software request. This is

accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13.

The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that

software can determine when the oscillator is running and stable. At that point, software

can control switching to the main oscillator as a clock source. Prior to starting the main

oscillator, a frequency range must be selected by configuring the

OSCRANGE bit in the SCS register.

Table 13. System Controls and Status register (SCS - address 0x400F C1A0) bit description

Bit Symbol

Value Description

Access Reset

value

3:0

4

-

Reserved. User software should not write ones to

reserved bits. The value read from a reserved bit is

not defined.

-

NA

OSCRANGE

Main oscillator range select.

R/W

0

1

The frequency range of the main oscillator is 1 MHz

to 20 MHz.

The frequency range of the main oscillator is

15 MHz to 25 MHz.

5

6

OSCEN

Main oscillator enable.

R/W

RO

0

1

The main oscillator is disabled.

The main oscillator is enabled, and will start up if

the correct external circuitry is connected to the

XTAL1 and XTAL2 pins.

OSCSTAT

Main oscillator status.

0

1

The main oscillator is not ready to be used as a

clock source.

The main oscillator is ready to be used as a clock

source. The main oscillator must be enabled via the

OSCEN bit.

31:7 -

-

Reserved. User software should not write ones to

reserved bits. The value read from a reserved bit is

not defined.

-

NA

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1. Summary of clocking and power control functions

This section describes the generation of the various clocks needed by the LPC17xx and

options of clock source selection, as well as power control and wake-up from reduced

power modes. Functions described in the following subsections include:

• Oscillators

• Clock source selection

• PLLs

• Clock dividers

• APB dividers

• Power control

• Wake-up timer

• External clock output

USB PLL settings

(PLL1...)

USB PLL

select

(PLL1CON)

USB PLL

(PLL1)

usb_clk

USB

Clock

Divider

CPU PLL

main PLL

settings

select

(PLL0CON)

(PLL0...)

USB clock divider setting

USBCLKCFG[3:0]

osc_clk

rtc_clk

irc_osc

sysclk

Main PLL

(PLL0)

CPU

pllclk

cclk

`

Clock

Divider

system clock select

CLKSRCSEL[1:0]

CPU clock divider setting

CCLKCFG[7:0]

pclk1

pclk2

pclk4

pclk8

Peripheral

watchdog clock select

WDCLKSEL[1:0]

Clock

Divider

wd_clk

PCLK_WDT

Fig 7. Clock generation for the LPC17xx

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2. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

Table 14. Summary of system control registers

Name

Description

Access Reset value Address

Clock source selection

CLKSRCSEL Clock Source Select Register

Phase Locked Loop (PLL0, Main PLL)

R/W

0

0x400F C10C

PLL0CON

PLL0CFG

PLL0STAT

PLL0FEED

PLL0 Control Register

PLL0 Configuration Register

PLL0 Status Register

PLL0 Feed Register

R/W

RO

0

0x400F C080

0x400F C084

0x400F C088

0x400F C08C

0

WO

NA

Phase Locked Loop (PLL1, USB PLL)

PLL1CON

PLL1 Control Register

PLL1 Configuration Register

PLL1 Status Register

PLL1 Feed Register

R/W

RO

0

0x400F C0A0

0x400F C0A4

0x400F C0A8

0x400F C0AC

PLL1CFG

0

PLL1STAT

PLL1FEED

Clock dividers

CCLKCFG

0

WO

NA

CPU Clock Configuration Register

R/W

0

0x400F C104

0x400F C108

0x400F C1A8

0x400F C1AC

USBCLKCFG USB Clock Configuration Register

PCLKSEL0

PCLKSEL1

Power control

PCON

Peripheral Clock Selection register 0.

Peripheral Clock Selection register 1.

Power Control Register

R/W

0

0x400F C0C0

0x400F C0C4

PCONP

Power Control for Peripherals Register R/W

0x03BE

Utility

CLKOUTCFG Clock Output Configuration Register

R/W

0

0x400F C1C8

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3. Oscillators

The LPC17xx includes three independent oscillators. These are the Main Oscillator, the

Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than

one purpose as required in a particular application. This can be seen in Figure 4–7.

Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched

by software. This allows systems to operate without any external crystal, and allows the

boot loader code to operate at a known frequency.

3.1 Internal RC oscillator

The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer,

and/or as the clock that drives PLL0 and subsequently the CPU. The precision of the IRC

does not allow for use of the USB interface, which requires a much more precise time

base in order to comply with the USB specification. Also, the IRC should not be used with

the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The nominal IRC

frequency is 4 MHz.

Upon power-up or any chip reset, the LPC17xx uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

3.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using

PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency

can be boosted to a higher frequency, up to the maximum CPU operating frequency, by

the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the

PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK

for purposes of rate equations, etc. elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer

to Section 4–5 “PLL0 (Phase Locked Loop 0)” for details.

The on-board oscillator in the LPC17xx can operate in one of two modes: slave mode and

oscillation mode.

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(C_Cin Figure 4–8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms.

This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4

V. The XTAL2 pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 4–8,

drawings b and c, and in Table 4–15 and Table 4–16. Since the feedback resistance is

integrated on chip, only a crystal and the capacitances C_X1and C_X2need to be connected

externally in case of fundamental mode oscillation (the fundamental frequency is

represented by L, C_Land R_S). Capacitance C_Pin Figure 4–8, drawing c, represents the

parallel package capacitance and should not be larger than 7 pF. Parameters F_C, C_L, R_S

and C_Pare supplied by the crystal manufacturer.

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LPC17xx

XTAL1

XTAL2

XTAL1

XTAL2

L

< = >

C_C

Clock

C_L

R_S

C_P

Xtal

C_X1

C_X2

a)

b)

c)

Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external

crystal model used for C_{X1 X2}evaluation

/

Table 15. Recommended values for C_X1/X2in oscillation mode (crystal and external

components parameters) low frequency mode (OSCRANGE = 0, see Table 3–13)

Fundamental oscillation Crystal load

Maximum crystal

series resistance R_S

External load

capacitors C_X1,

CX2

frequency F_OSC

capacitance C_L

1 MHz - 5 MHz

10 pF

< 300 Ω

< 200 Ω

< 100 Ω

< 160 Ω

< 60 Ω

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz - 10 MHz

10 pF

20 pF

30 pF

10 MHz - 15 MHz

15 MHz - 20 MHz

10 pF

20 pF

10 pF

< 80 Ω

Table 16. Recommended values for C_X1/X2in oscillation mode (crystal and external

components parameters) high frequency mode (OSCRANGE = 1, see Table 3–13)

Fundamental oscillation Crystal load

Maximum crystal

series resistance R_S

External load

capacitors C_X1,

CX2

frequency F_OSC

capacitance C_L

15 MHz - 20 MHz

10 pF

< 180 Ω

< 100 Ω

< 160 Ω

< 80 Ω

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz - 25 MHz

10 pF

20 pF

Since chip operation always begins using the Internal RC Oscillator, and the main

oscillator may not be used at all in some applications, it will only be started by software

request. This is accomplished by setting the OSCEN bit in the SCS register, as described

in Table 3–13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS

register) so that software can determine when the oscillator is running and stable. At that

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point, software can control switching to the main oscillator as a clock source. Prior to

starting the main oscillator, a frequency range must be selected by configuring the

OSCRANGE bit in the SCS register.

3.3 RTC oscillator

The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can

be used as the clock source for PLL0 and CPU and/or the watchdog timer.

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4. Clock source selection multiplexer

Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip

peripheral devices. The clock sources available are the main oscillator, the RTC oscillator,

and the Internal RC oscillator.

The clock source selection can only be changed safely when PLL0 is not connected. For a

detailed description of how to change the clock source in a system using PLL0 see

Section 4–5.13 “PLL0 setup sequence”.

Note the following restrictions regarding the choice of clock sources:

• The IRC oscillator should not be used (via PLL0) as the clock source for the USB

subsystem.

• The IRC oscillator should not be used (via PLL0) as the clock source for the CAN

controllers if the CAN baud rate is higher than 100 kbit/s.

4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C)

The CLKSRCSEL register contains the bits that select the clock source for PLL0.

Table 17. Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit

description

Bit

Symbol

Value Description

Reset

value

1:0

CLKSRC

Selects the clock source for PLL0 as follows:

0

00

Selects the Internal RC oscillator as the PLL0 clock source

(default).

01

10

11

Selects the main oscillator as the PLL0 clock source.

Selects the RTC oscillator as the PLL0 clock source.

Reserved, do not use this setting.

Warning: Improper setting of this value, or an incorrect sequence of

changing this value may result in incorrect operation of the device.

31:2

-

0

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

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5. PLL0 (Phase Locked Loop 0)

PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock

source is selected in the CLKSRCSEL register (see Section 4–4). The input frequency is

multiplied up to a high frequency, then divided down to provide the actual clock used by

the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem

has its own dedicated PLL (see Section 4–6). PLL0 can produce a clock up to the

maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and

LPC1759), and 100 MHz on other versions.

5.1 PLL0 operation

The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value

"N", which may be in the range of 1 to 256. This input division provides a greater number

of possibilities in providing a wide range of output frequencies from the same input

frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the

range of 6 through 512, plus additional values listed in Table 4–21. The resulting

frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing

the CCO output by the value of M, then using a phase-frequency detector to compare the

divided CCO output to the multiplier input. The error value is used to adjust the CCO

frequency.

There are additional dividers at the output of PLL0 to bring the frequency down to what is

needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output

dividers are described in the Clock Dividers section following the PLL0 description. A

block diagram of PLL0 is shown in Figure 4–9

PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values

are controlled by the PLL0CFG register. These two registers are protected in order to

prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip

operations, including the Watchdog Timer, could be dependent on PLL0 if so configured

(for example when it is providing the chip clock), accidental changes to the PLL0 setup

values could result in unexpected or fatal behavior of the microcontroller. The protection is

accomplished by a feed sequence similar to that of the Watchdog Timer. Details are

provided in the description of the PLL0FEED register.

PLL0 is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL0 must be configured, enabled, and connected to the system by software.

It is important that the setup procedure described in Section 4–5.13 “PLL0 setup

sequence” is followed or PLL0 might not operate at all!

5.1.1 PLL0 and startup/boot code interaction

When there is no valid user code (determined by the checksum word) in the user flash or

the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the

boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is

disabled when the user opens a debug session to debug the application code. The user

startup code must follow the steps described in this chapter to disconnect the PLL.

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5.2 PLL0 register description

PLL0 is controlled by the registers shown in Table 4–18. More detailed descriptions follow.

Warning: Improper setting of PLL0 values may result in incorrect operation of the

device!

Table 18. PLL0 registers

Name

Description

Access Reset

value^[1]

Address

PLL0CON PLL0 Control Register. Holding register for

updating PLL0 control bits. Values written to this

register do not take effect until a valid PLL0 feed

sequence has taken place.

R/W

0

0x400F C080

PLL0CFG

PLL0 Configuration Register. Holding register for R/W

0x400F C084

0x400F C088

updating PLL0 configuration values. Values

written to this register do not take effect until a

valid PLL0 feed sequence has taken place.

PLL0STAT PLL0 Status Register. Read-back register for

PLL0 control and configuration information. If

PLL0CON or PLL0CFG have been written to, but

a PLL0 feed sequence has not yet occurred, they

will not reflect the current PLL0 state. Reading

this register provides the actual values controlling

the PLL0, as well as the PLL0 status.

RO

PLL0FEED PLL0 Feed Register. This register enables

loading of the PLL0 control and configuration

information from the PLL0CON and PLL0CFG

registers into the shadow registers that actually

affect PLL0 operation.

WO

NA

0x400F C08C

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

PLLC

PLLE

PLOCK

pd

refclk

PHASE-

pllclkin

FREQUENCY

DETECTOR

FILTER

/2

CCO

N-DIVIDER

pllclk

NSEL

[7:0]

M-DIVIDER

MSEL

[14:0]

Fig 9. PLL0 block diagram

5.3 PLL0 Control register (PLL0CON - 0x400F C080)

The PLL0CON register contains the bits that enable and connect PLL0. Enabling PLL0

allows it to attempt to lock to the current settings of the multiplier and divider values.

Connecting PLL0 causes the processor and most chip functions to run from the PLL0

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output clock. Changes to the PLL0CON register do not take effect until a correct PLL0

feed sequence has been given (see Section 4–5.8 “PLL0 Feed register (PLL0FEED -

0x400F C08C)”).

Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description

Bit

Symbol Description

Reset

value

0

PLLE0

PLLC0

PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate

PLL0 and allow it to lock to the requested frequency. See PLL0STAT

register, Table 4–22.

0

1

PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and

locked, then followed by a valid PLL0 feed sequence causes PLL0 to

become the clock source for the CPU, AHB peripherals, and used to

derive the clocks for APB peripherals. The PLL0 output may potentially

be used to clock the USB subsystem if the frequency is 48 MHz. See

PLL0STAT register, Table 4–22.

0

31:2

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

PLL0 must be set up, enabled, and Lock established before it may be used as a clock

source. When switching from the oscillator clock to the PLL0 output or vice versa, internal

circuitry synchronizes the operation in order to ensure that glitches are not generated.

Hardware does not insure that PLL0 is locked before it is connected or automatically

disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is

likely that the oscillator clock has become unstable and disconnecting PLL0 will not

remedy the situation.

5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084)

The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the

PLL0CFG register do not take effect until a correct PLL feed sequence has been given

(see Section 4–5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Calculations for

the PLL frequency, and multiplier and divider values are found in the Section 4–5.10

“PLL0 frequency calculation”.

Table 20. PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description

Bit

Symbol

Description

Reset

value

14:0 MSEL0

PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency

calculations. The value stored here is M - 1. Supported values for M

are 6 through 512 and those listed in Table 4–21.

0

Note: Not all values of M are needed, and therefore some are not

supported by hardware. For details on selecting values for MSEL0 see

Section 4–5.10 “PLL0 frequency calculation”.

15

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

0

23:16 NSEL0

PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency

calculations. The value stored here is N - 1. Supported values for N are

1 through 32.

Note: For details on selecting the right value for NSEL0 see Section

4–5.10 “PLL0 frequency calculation”.

31:24 -

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

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Table 21. Multiplier values for PLL0 with a 32 kHz input

Multiplier Pre-divide F_CCOMultiplier Pre-divide F_CCO

(M)

(N)

1

2

(M)

(N)

2

3

2

3

2

3

2

3

2

3

2

3

4272

4395

4578

4725

4807

5127

5188

5400

5493

5859

6042

6075

6104

6409

6592

6750

6836

6866

6958

7050

7324

7425

7690

7813

7935

8057

8100

8545

8789

9155

9613

10254

10376

10986

11719

279.9698

288.0307

300.0238

309.6576

315.0316

336.0031

340.0008

353.8944

359.9892

383.9754

395.9685

398.1312

400.0317

420.0202

432.0133

442.3680

448.0041

449.9702

455.9995

462.0288

479.9857

486.6048

503.9718

512.0328

520.0282

528.0236

530.8416

280.0026

287.9980

299.9910

314.9988

336.0031

340.0008

359.9892

384.0082

12085

12207

12817

13184

13672

13733

13916

14099

14420

14648

15381

15564

15625

15869

16113

16479

17578

18127

18311

19226

19775

20508

20599

20874

21149

21973

23071

23438

23804

24170

396.0013

399.9990

419.9875

279.9916

432.0133

288.0089

448.0041

450.0029

300.0020

455.9995

461.9960

315.0097

479.9857

504.0046

336.0031

340.0008

512.0000

519.9954

527.9908

359.9892

383.9973

395.9904

400.0099

419.9984

431.9915

448.0041

449.9920

455.9995

462.0070

480.0075

503.9937

512.0109

520.0063

528.0017

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5.5 PLL0 Status register (PLL0STAT - 0x400F C088)

The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect

at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in

PLL0CON and PLL0CFG because changes to those registers do not take effect until a

proper PLL0 feed has occurred (see Section 4–5.8 “PLL0 Feed register (PLL0FEED -

0x400F C08C)”).

Table 22. PLL Status register (PLL0STAT - address 0x400F C088) bit description

Bit

14:0 MSEL0

15

23:16 NSEL0

Symbol

Description

Reset

value

Read-back for the PLL0 Multiplier value. This is the value currently

used by PLL0, and is one less than the actual multiplier.

0

-

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

0

Read-back for the PLL0 Pre-Divider value. This is the value

currently used by PLL0, and is one less than the actual divider.

24

PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the

PLEC0 bit in PLL0CON (see Table 4–19) after a valid PLL0 feed.

0

When one, PLL0 is currently enabled. When zero, PLL0 is turned

off. This bit is automatically cleared when Power-down mode is

entered.

25

PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of

0

the PLLC0 bit in PLL0CON (see Table 4–19) after a valid PLL0

feed.

When PLLC0 and PLLE0 are both one, PLL0 is connected as the

clock source for the CPU. When either PLLC0 or PLLE0 is zero,

PLL0 is bypassed. This bit is automatically cleared when

Power-down mode is entered.

26

PLOCK0

Reflects the PLL0 Lock status. When zero, PLL0 is not locked.

When one, PLL0 is locked onto the requested frequency. See text

for details.

0

31:27 -

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

5.6 PLL0 Interrupt: PLOCK0

The PLOCK0 bit in the PLL0STAT register reflects the lock status of PLL0. When PLL0 is

enabled, or parameters are changed, PLL0 requires some time to establish lock under the

new conditions. PLOCK0 can be monitored to determine when PLL0 may be connected

for use. The value of PLOCK0 may not be stable when the PLL reference frequency

(F_REF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the

pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL

may be assumed to be stable after a start-up time has passed. This time is 500 μs when

FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz

PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0

and continue with other functions without having to wait for PLL0 to achieve lock. When

the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0

appears as interrupt 32 in Table 6–50. Note that PLOCK0 remains asserted whenever

PLL0 is locked, so if the interrupt is used, the interrupt service routine must disable the

PLOCK0 interrupt prior to exiting.

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5.7 PLL0 Modes

The combinations of PLLE0 and PLLC0 are shown in Table 4–23.

Table 23. PLL control bit combinations

PLLC0 PLLE0 PLL Function

0

1

PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input.

PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is

asserted.

1

0

1

Same as 00 combination. This prevents the possibility of PLL0 being connected

without also being enabled.

PLL0 is active and has been connected as the system clock source.

5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C)

A correct feed sequence must be written to the PLL0FEED register in order for changes to

the PLL0CON and PLL0CFG registers to take effect. The feed sequence is:

1. Write the value 0xAA to PLL0FEED.

2. Write the value 0x55 to PLL0FEED.

The two writes must be in the correct sequence, and there must be no other register

access in the same address space (0x400F C000 to 0x400F FFFF) between them.

Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed

operation, if there is a possibility that an interrupt service routine could write to another

register in that space. If either of the feed values is incorrect, or one of the previously

mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will

not become effective.

Table 24. PLL Feed register (PLL0FEED - address 0x400F C08C) bit description

Bit

Symbol

Description

Reset

value

7:0

PLL0FEED The PLL0 feed sequence must be written to this register in order for 0x00

PLL0 configuration and control register changes to take effect.

31:8

-

Reserved, user software should not write ones to reserved bits. The NA

value read from a reserved bit is not defined.

5.9 PLL0 and Power-down mode

Power-down mode automatically turns off and disconnects PLL0. Wake-up from

Power-down mode does not automatically restore PLL0 settings, this must be done in

software. Typically, a routine to activate PLL0, wait for lock, and then connect PLL0 can be

called at the beginning of any interrupt service routine that might be called due to the

wake-up. It is important not to attempt to restart PLL0 by simply feeding it when execution

resumes after a wake-up from Power-down mode. This would enable and connect PLL0

at the same time, before PLL lock is established.

5.10 PLL0 frequency calculation

PLL0 equations use the following parameters:

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Table 25. PLL frequency parameter

Parameter Description

F_IN

F_CCO

N

the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.

the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator)

PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG

NSEL0 field + 1). N is an integer from 1 through 32.

M

PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG

MSEL0 field + 1). Not all potential values are supported. See below.

F_REF

PLL internal reference frequency, F_INdivided by N.

The PLL0 output frequency (when PLL0 is both active and connected) is given by:

F_CCO= (2 × M × F_IN) / N

PLL inputs and settings must meet the following:

• F_INis in the range of 32 kHz to 50 MHz.

• F_CCOis in the range of 275 MHz to 550 MHz.

The equation can be solved for other PLL parameters:

M = (F_CCO× N) / (2 × F_IN)

N = (2 × M × F_IN) / F_CCO

F_IN= (F_CCO× N) / (2 × M)

Allowed values for M:

At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are

allowed. This supports the entire useful range of both the main oscillator and the IRC.

For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65

additional M values have been selected for supporting baud rate generation, CAN/USB

operation, and obtaining integer MHz frequencies. These values are shown in Table 4–26.

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Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input

Low Frequency PLL Multipliers

4272

5127

4395

5188

4578

5400

4725

5493

4807

5859

6042

6075

6104

6409

6592

6750

6836

6866

6958

7050

7324

7425

7690

7813

7935

8057

8100

8545

8789

9155

9613

10254

12207

13916

15564

17578

20508

23071

10376

12817

14099

15625

18127

20599

23438

10986

13184

14420

15869

18311

20874

23804

11719

13672

14648

16113

19226

21149

24170

12085

13733

15381

16479

19775

21973

5.11 Procedure for determining PLL0 settings

PLL0 parameter determination can be simplified by using a spreadsheet available from

NXP. To determine PLL0 parameters by hand, the following general procedure may be

used:

1. Determine if the application requires use of the USB interface, and whether it will be

clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very

small tolerance, which means that F_CCOmust be an even integer multiple of 48 MHz

(i.e. an integer multiple of 96 MHz), within a very small tolerance.

2. Choose the desired processor operating frequency (CCLK). This may be based on

processor throughput requirements, need to support a specific set of UART baud

rates, etc. Bear in mind that peripheral devices may be running from a lower clock

frequency than that of the processor (see Section 4–7 “Clock dividers” on page 55

and Section 4–8 “Power control” on page 59). Find a value for F_CCOthat is close to a

multiple of the desired CCLK frequency, bearing in mind the requirement for USB

support in [1] above, and that lower values of F_CCOresult in lower power dissipation.

3. Choose a value for the PLL input frequency (F_IN). This can be a clock obtained from

the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,

the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used

to clock the USB subsystem, this affects the choice of the main oscillator frequency.

4. Calculate values for M and N to produce a sufficiently accurate F_CCOfrequency. The

desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value

-1 will be written to the NSEL0 field in PLL0CFG.

In general, it is better to use a smaller value for N, to reduce the level of multiplication that

must be accomplished by the CCO. Due to the difficulty in finding the best values in some

cases, it is recommended to use a spreadsheet or similar method to show many

possibilities at once, from which an overall best choice may be selected. A spreadsheet is

available from NXP for this purpose.

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5.12 Examples of PLL0 settings

The following table gives a summary of examples that illustrate selecting PLL0 values

based on different system requirements.

Table 27. Summary of PLL0 examples

Example Description

1

2

3

• The PLL0 clock source is 10 MHz.

• PLL0 is not used as the USB clock source, or the USB interface is not used.

• The desired CPU clock is 100 MHz.

• The PLL0 clock source is 4 MHz.

• PLL0 is used as the USB clock source.

• The desired CPU clock is 60 MHz.

• The PLL0 clock source is the 32.768 kHz RTC clock.

• PLL0 is not used as the USB clock source, or the USB interface is not used.

• The desired CPU clock is 72 MHz.

Example 1

Assumptions:

• The USB interface will not be used in the application, or will be clocked by PLL1.

• The desired CPU rate is 100 MHz.

• An external 10 MHz crystal or clock source will be used as the system clock source.

Calculations:

M = (F_CCO× N) / (2 × F_IN)

A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),

both result in better PLL operational stability and lower output jitter. Lower values of F_CCO

also save power. So, the process of determining PLL setup parameters involves looking

for the smallest N and M values giving the lowest F_CCOvalue that will support the required

CPU and/or USB clocks. It is usually easier to work backward from the desired output

clock rate and determine a target F_CCOrate, then find a way to obtain that F_CCOrate from

the available input clock.

Potential precise values of F_CCOare integer multiples of the desired CPU clock. In this

example, it is clear that the smallest frequency for F_CCOthat can produce the desired CPU

clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz

(3 × 100 MHz).

Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives

M = ((300 × 10⁶× 1) / (2 × 10 × 10⁶) = 300 / 20 = 15. Since the result is an integer, there is

no need to look any further for a good set of PLL0 configuration values. The value written

to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E).

The PLL output must be further divided in order to produce the CPU clock. This is

accomplished using a separate divider that is described later in this chapter, see

Section 4–7.1.

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Example 2

Assumptions:

• The USB interface will be used in the application and will be clocked from PLL0.

• The desired CPU rate is 60 MHz.

• An external 4 MHz crystal or clock source will be used as the system clock source.

This clock source could be the Internal RC oscillator (IRC).

Calculations:

M = (F_CCO× N) / (2 × F_IN)

Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that

need must be addressed first. Potential precise values of F_CCOare integer multiples of the

2 × the 48 MHz USB clock. The 2 × insures that the clock has a 50% duty cycle, which

would not be the case for a division of the PLL output by an odd number.

The possibilities for the F_CCOrate when the USB is used are 288 MHz, 384 MHz, and 480

MHz. The smallest frequency for F_CCOthat can produce a valid USB clock rate and is

within the PLL0 operating range is 288 MHz (3 × 2 × 48 MHz).

Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So,

M = ((288 × 10⁶) × 1) / (2 × (4 × 10⁶⁾) = 288 / 8 = 36. The result is an integer, which is

necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23

(N - 1 = 0; M - 1 = 35 = 0x23).

The potential CPU clock rate can be determined by dividing F_CCOby the desired CPU

frequency: 288 × 10⁶/ 60 × 10⁶= 4.8. The nearest integer value for the CPU Clock

Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.

If it is important to obtain exactly 60 MHz, an F_CCOrate must be found that can be divided

down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the F_CCOrate

when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is

also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle

needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0

settings for 480 MHz are N = 1 and M = 60.

The PLL output must be further divided in order to produce both the CPU clock and the

USB clock. This is accomplished using separate dividers that are described later in this

chapter. See Section 4–7.1 and Section 4–7.2.

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Example 3

Assumptions:

• The USB interface will not be used in the application, or will be clocked by PLL1.

• The desired CPU rate is 72 MHz

• The 32.768 kHz RTC clock source will be used as the system clock source

Calculations:

M = (F_CCO× N) / (2 × F_IN)

The smallest integer multiple of the desired CPU clock rate that is within the PLL0

operating range is 288 MHz (4 × 72 MHz).

Using the equation above and assuming that N = 1, M = ((288 × 10⁶) × 1) / (2 × 32,768) =

4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with

this setting. Since this example is less obvious, it may be useful to make a table of

possibilities for different values of N (see below).

Table 28. Potential values for PLL example

N

M

M Rounded F_REFin Hz F_CCOin MHz CCLK in MHz % Error

(F_IN/ N)

(F_REFx M)

288.0307

287.9980

288.0089

287.9980

288.0045

(F_CCO/ 4)

72.0077

71.9995

72.0022

71.9995

72.0011

(CCLK-72) / 72

1

2

3

4

5

4394.53125

8789.0625

4395

32768

0.0107

8789

16384

-0.0007

13183.59375

17578.125

13184

17578

21973

10922.67

8192

0.0031

-0.0007

21972.65625

6553.6

0.0016

Beyond N = 5, the value of M is out of range or not supported, so the table stops at that

point. In the third column of the table, the calculated M value is rounded to the nearest

integer. If this results in CCLK being above the maximum operating frequency, it is

allowed if it is not more than 1/2 % above the maximum frequency.

In general, larger values of F_REFresult in a more stable PLL when the input clock is a low

frequency. Even the first table entry shows a very small error of just over 1 hundredth of a

percent, or 107 parts per million (ppm). If that is not accurate enough in the application,

the second case gives a much smaller error of 7 ppm. There are no allowed combinations

that give a smaller error than that.

Remember that when a frequency below about 1 MHz is used as the PLL0 clock source,

not all multiplier values are available. As it turns out, all of the rounded M values found in

Table 4–28 of this example are supported, which may be confirmed in Table 4–26. If PLL0

calculations suggest use of unsupported multiplier values, those values must be

disregarded and other values examined to find the best fit.

The value written to PLL0CFG for the second table entry would be 0x12254

(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).

The PLL output must be further divided in order to produce the CPU clock. This is

accomplished using a separate divider that is described later in this chapter, see

Section 4–7.1.

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5.13 PLL0 setup sequence

The following sequence must be followed step by step in order to have PLL0 initialized

and running:

1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.

2. Disable PLL0 with one feed sequence.

3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.

4. Write to the Clock Source Selection Control register to change the clock source if

needed.

5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG

can only be updated when PLL0 is disabled.

6. Enable PLL0 with one feed sequence.

7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do

this before connecting PLL0.

8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,

or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is

slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference

frequency (FREF, the frequency of REFCLK, which is equal to the PLL input

frequency divided by the pre-divider value) is less than 100 kHz or greater than

20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time

has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF

seconds when FREF is less than 400 kHz.

9. Connect PLL0 with one feed sequence.

It is very important not to merge any steps above. For example, do not update the

PLL0CFG and enable PLL0 simultaneously with the same feed sequence.

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6. PLL1 (Phase Locked Loop 1)

PLL1 receives its clock input from the main oscillator only and can be used to provide a

fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the

possibility of generating the USB clock from PLL0.

PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be

supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is

enabled and connected via the PLL1CON register (see Section 4–6.2), it is automatically

selected to drive the USB subsystem (see Figure 4–7).

PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values

are controlled by the PLL1CFG register. These two registers are protected in order to

prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection

is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are

provided in the description of the PLL1FEED register.

PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input

frequency is multiplied up to the range of 48 MHz for the USB clock using a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB,

the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz

to 320 MHz, so there is an additional divider in the loop to keep the CCO within its

frequency range while PLL1 is providing the desired output frequency. The output divider

may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum

output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A

block diagram of PLL1 is shown in Figure 4–10.

6.1 PLL1 register description

PLL1 is controlled by the registers shown in Table 4–29. More detailed descriptions follow.

Writes to any unused bits are ignored. A read of any unused bits will return a logic zero.

Warning: Improper setting of PLL1 values may result in incorrect operation of the

USB subsystem!

Table 29. PLL1 registers

Name

Description

Access Reset

value^[1]

Address

PLL1CON

PLL1 Control Register. Holding register for

updating PLL1 control bits. Values written to this

register do not take effect until a valid PLL1 feed

sequence has taken place.

R/W

0

0x400F C0A0

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Table 29. PLL1 registers

Name

Description

Access Reset

value^[1]

Address

PLL1CFG

PLL1 Configuration Register. Holding register

for updating PLL1 configuration values. Values

written to this register do not take effect until a

valid PLL1 feed sequence has taken place.

R/W

0

0x400F C0A4

PLL1STAT

PLL1 Status Register. Read-back register for

PLL1 control and configuration information. If

PLL1CON or PLL1CFG have been written to,

but a PLL1 feed sequence has not yet occurred,

they will not reflect the current PL1L state.

Reading this register provides the actual values

controlling PLL1, as well as PLL1 status.

RO

0

0x400F C0A8

0x400F C0AC

PLL1FEED PLL1 Feed Register. This register enables

loading of PLL1 control and configuration

information from the PLL1CON and PLL1CFG

registers into the shadow registers that actually

affect PLL1 operation.

WO

NA

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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PLLC

CLOCK

SYNCHRONIZATION

direct

0

PSEL[1:0]

PD

PLLE

bypass

0

F_OSC

1

CD

PHASE-

F_CCO

CCO

0

FREQUENCY

DETECTOR

0

PLOCK

/2P

0

1

CCLK

1

PD

CD

F_OUT

DIV-BY-M

MSEL<4:0>

MSEL[4:0]

Fig 10. PLL1 block diagram

6.2 PLL1 Control register (PLL1CON - 0x400F C0A0)

The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1

allows it to attempt to lock to the current settings of the multiplier and divider values.

Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes

to the PLL1CON register do not take effect until a correct PLL feed sequence has been

given (see Section 4–6.6 and Section 4–6.3).

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Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description

Bit

Symbol Description

Reset

value

0

PLLE1

PLLC1

PLL1 Enable. When one, and after a valid PLL1 feed, this bit will

activate PLL1 and allow it to lock to the requested frequency. See

PLL1STAT register, Table 4–32.

0

1

PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and

locked, then followed by a valid PLL1 feed sequence causes PLL1 to

become the clock source for the USB subsystem via the USB clock

divider. See PLL1STAT register, Table 4–32.

0

31:2

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

PLL1 must be set up, enabled, and lock established before it may be used as a clock

source for the USB subsystem. The hardware does not insure that the PLL is locked

before it is connected nor does it automatically disconnect the PLL if lock is lost during

operation.

6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4)

The PLL1CFG register contains the PLL1 multiplier and divider values. Changes to the

PLL1CFG register do not take effect until a correct PLL1 feed sequence has been given

(see Section 4–6.6). Calculations for the PLL1 frequency, and multiplier and divider

values are found in Section 4–6.9.

Table 31. PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description

Bit

Symbol Description

Reset

value

4:0

MSEL1

PSEL1

-

PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency

calculations.

0

Note: For details on selecting the right value for MSEL1 see

Section 4–5.10.

6:5

PLL1 Divider value. Supplies the value "P" in the PLL1 frequency

calculations.

0

Note: For details on selecting the right value for PSEL1 see

Section 4–5.10.

31:7

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8)

The read-only PLL1STAT register provides the actual PLL1 parameters that are in effect

at the time it is read, as well as the PLL1 status. PLL1STAT may disagree with values

found in PLL1CON and PLL1CFG because changes to those registers do not take effect

until a proper PLL1 feed has occurred (see Section 4–6.6 “PLL1 Feed register

(PLL1FEED - 0x400F C0AC)”).

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Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description

Bit

4:0

6:5

7

Symbol

MSEL1

PSEL1

-

Description

Reset

value

Read-back for the PLL1 Multiplier value. This is the value currently

used by PLL1.

0

Read-back for the PLL1 Divider value. This is the value currently

used by PLL1.

0

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

0

8

PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently

activated. When zero, PLL1 is turned off. This bit is automatically

cleared when Power-down mode is activated.

9

PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are

both one, PLL1 is connected as the clock source for the

microcontroller. When either PLLC or PLLE is zero, PLL1 is

bypassed and the oscillator clock is used directly by the

microcontroller. This bit is automatically cleared when Power-down

mode is activated.

0

10

PLOCK1

Reflects the PLL1 Lock status. When zero, PLL1 is not locked.

When one, PLL1 is locked onto the requested frequency.

0

31:11 -

Reserved, user software should not write ones to reserved bits.

The value read from a reserved bit is not defined.

NA

6.4.1 PLL1 modes

The combinations of PLLE1 and PLLC1 are shown in Table 4–33.

Table 33. PLL1 control bit combinations

PLLC1 PLLE1 PLL1 Function

0

1

PLL1 is turned off and disconnected.

PLL1 is active, but not yet connected. PLL1 can be connected after PLOCK1

is asserted.

1

0

1

Same as 00 combination. This prevents the possibility of PLL1 being

connected without also being enabled.

PLL1 is active and has been connected. The clock for the USB subsystem is

sourced from PLL1.

6.5 PLL1 Interrupt: PLOCK1

The PLOCK1 bit in the PLL1STAT register reflects the lock status of PLL1. When PLL1 is

enabled, or parameters are changed, the PLL requires some time to establish lock under

the new conditions. PLOCK1 can be monitored to determine when the PLL may be

connected for use.

PLOCK1 is connected to the interrupt controller. This allows for software to turn on the

PLL and continue with other functions without having to wait for the PLL to achieve lock.

When the interrupt occurs, the PLL may be connected, and the interrupt disabled.

PLOCK1 appears as interrupt 48 in Table 6–50. Note that PLOCK1 remains asserted

whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must

disable the PLOCK1 interrupt prior to exiting.

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6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC)

A correct feed sequence must be written to the PLL1FEED register in order for changes to

the PLL1CON and PLL1CFG registers to take effect. The feed sequence is:

1. Write the value 0xAA to PLL1FEED.

2. Write the value 0x55 to PLL1FEED.

The two writes must be in the correct sequence, and there must be no other register

access in the same address space (0x400F C000 to 0x400F FFFF) between them.

Because of this, it may be necessary to disable interrupts for the duration of the PLL feed

operation, if there is a possibility that an interrupt service routine could write to another

register in that space. If either of the feed values is incorrect, or one of the previously

mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will

not become effective.

Table 34. PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description

Bit

Symbol

Description

Reset

value

7:0

PLL1FEED The PLL1 feed sequence must be written to this register in order for 0x00

PLL1 configuration and control register changes to take effect.

31:8

-

Reserved, user software should not write ones to reserved bits. The NA

value read from a reserved bit is not defined.

6.7 PLL1 and Power-down mode

Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up

from Power-down mode does not automatically restore PLL settings, this must be done in

software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL

can be called at the beginning of any interrupt service routine that might be called due to

the wake-up. It is important not to attempt to restart a PLL by simply feeding it when

execution resumes after a wake-up from Power-down mode. This would enable and

connect the PLL at the same time, before PLL lock is established.

If activity on the USB data lines is not selected to wake the microcontroller from

Power-down mode (see Section 4–8.8 for details of wake up from reduced modes), both

the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and

disconnected when Power-down mode is invoked, as described above. However, if the

USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 11–190 for a

description of USB_NEED_CLK), it is not possible to go into Power-down mode and any

attempt to set the PD bit will fail, leaving the PLLs in the current state.

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6.8 PLL1 frequency calculation

The PLL1 equations use the following parameters:

Table 35. Elements determining PLL frequency

Element

F_OSC

F_CCO

USBCLK

M

Description

the frequency from the crystal oscillator

the frequency of the PLL1 current controlled oscillator

the PLL1 output frequency (48 MHz for USB)

PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register

PLL1 Divider value from the PSEL1 bits in the PLL1CFG register

P

The PLL1 output frequency (when the PLL is both active and connected) is given by:

USBCLK = M × F_OSCor USBCLK = F_CCO/ (2 × P)

The CCO frequency can be computed as:

F_CCO= USBCLK × 2 × P or F_CCO= F_OSC× M × 2 × P

The PLL1 inputs and settings must meet the following criteria:

• F_OSCis in the range of 10 MHz to 25 MHz.

• USBCLK is 48 MHz.

• F_CCOis in the range of 156 MHz to 320 MHz.

6.9 Procedure for determining PLL1 settings

The PLL1 configuration for USB may be determined as follows:

1. The desired PLL1 output frequency is USBCLK = 48 MHz.

2. Choose an oscillator frequency (F_OSC). USBCLK must be the whole (non-fractional)

multiple of F_OSCmeaning that the possible values for F_OSCare 12 MHz, 16 MHz, and

24 MHz.

3. Calculate the value of M to configure the MSEL1 bits. M = USBCLK / F_OSC. In this

case, the possible values for M = 2, 3, or 4 (F_OSC= 24 MHz, 16 MHz, or 12 MHz). The

value written to the MSEL1 bits in PLL1CFG is M − 1 (see Table 4–37).

4. Find a value for P to configure the PSEL1 bits, such that F_CCOis within its defined

frequency limits of 156 MHz to 320 MHz. F_CCOis calculated using F_CCO= USBCLK ×

2 × P. It follows that P = 2 is the only P value to yield F_CCOin the allowed range. The

value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see Table 4–36).

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Table 36. PLL1 Divider values

Values allowed for using PLL1 with USB are highlighted.

PSEL1 Bits (PLL1CFG bits [6:5]) Value of P

00

01

10

11

1

2

4

8

Table 37. PLL1 Multiplier values

Values allowed for using PLL1 with USB are highlighted.

MSEL1 Bits (PLL1CFG bits [4:0]) Value of M

00000

00001

00010

00011

...

1

2

3

4

...

31

32

11110

11111

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7. Clock dividers

The output of the PLL0 must be divided down for use by the CPU and the USB subsystem

(if used with PLL0, see Section 4–6). Separate dividers are provided such that the CPU

frequency can be determined independently from the USB subsystem, which always

requires 48 MHz with a 50% duty cycle for proper operation.

USB PLL settings

USB PLL select

(PLL1CON)

(PLL1...)

osc_clk

sysclk

USB PLL

(PLL1)

usb_clk

USB

Clock

Divider

main PLL

settings

(PLL0...)

CPU PLL

select

(PLL0CON)

USB clock divider setting

USBCLKCFG[3:0]

Main PLL

(PLL0)

CPU

Clock

Divider

cclk

pllclk

CPU clock divider setting

CCLKCFG[7:0]

Fig 11. PLLs and clock dividers

7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)

The CCLKCFG register controls the division of the PLL0 output before it is used by the

CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the

output must be divided in order to bring the CPU clock frequency (CCLK) within operating

limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low

rate for temporary power savings without turning off PLL0.

Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in

order to support internal operations of the USB subsystem.

Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit

description

Bit

Symbol

Value Description

Reset

value

7:0

CCLKSEL

Selects the divide value for creating the CPU clock (CCLK)

0x00

from the PLL0 output.

0 to 1 Not allowed, the CPU clock will always be greater than 100

MHz.

2

PLL0 output is divided by 3 to produce the CPU clock.

PLL0 output is divided by 4 to produce the CPU clock.

PLL0 output is divided by 5 to produce the CPU clock.

:

3

4

:

255

PLL0 output is divided by 256 to produce the CPU clock.

31:8

-

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

NA

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The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having

CCLKSEL = 1 results in CCLK being one half the PLL0 output, CCLKSEL = 3 results in

CCLK being one quarter of the PLL0 output, etc.

7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108)

This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in

PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock

source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB

subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the

USB clock divider.

The USBCLKCFG register controls the division of the PLL0 output before it is used by the

USB subsystem.The PLL0 output must be divided in order to bring the USB clock

frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct

USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL

operating range.

Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is

using PLL0 as a clock source because a more precise clock is needed for USB

specification compliance (see Table 4–17).

Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit

description

Bit

Symbol

Value Description

Reset

value

3:0

USBSEL

Selects the divide value for creating the USB clock from the

0

PLL0 output. Only the values shown below can produce even

number multiples of 48 MHz from the PLL0 output.

Warning: Improper setting of this value will result in incorrect

operation of the USB interface.

5

7

9

PLL0 output is divided by 6. PLL0 output must be 288 MHz.

PLL0 output is divided by 8. PLL0 output must be 384 MHz.

PLL0 output is divided by 10. PLL0 output must be 480 MHz.

31:4

-

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

NA

7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 -

0x400F C1A8 and PCLKSEL1 - 0x400F C1AC)

A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal

that will be supplied to the corresponding peripheral as specified in Table 4–40,

Table 4–41 and Table 4–42.

Remark: The peripheral clock for the RTC block is fixed at CCLK/8.

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Table 40. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit

description

Bit

Symbol

Description

Reset

value

1:0

PCLK_WDT

PCLK_TIMER0

PCLK_TIMER1

PCLK_UART0

PCLK_UART1

-

Peripheral clock selection for WDT.

Peripheral clock selection for TIMER0.

Peripheral clock selection for TIMER1.

Peripheral clock selection for UART0.

Peripheral clock selection for UART1.

Reserved.

00

NA

00

NA

00

3:2

5:4

7:6

9:8

11:10

13:12 PCLK_PWM1

15:14 PCLK_I2C0

17:16 PCLK_SPI

Peripheral clock selection for PWM1.

Peripheral clock selection for I²C0.

Peripheral clock selection for SPI.

Reserved.

19:18

-

21:20 PCLK_SSP1

23:22 PCLK_DAC

25:24 PCLK_ADC

27:26 PCLK_CAN1

29:28 PCLK_CAN2

31:30 PCLK_ACF

Peripheral clock selection for SSP1.

Peripheral clock selection for DAC.

Peripheral clock selection for ADC.

Peripheral clock selection for CAN1.^[1]

Peripheral clock selection for CAN2.^[1]

Peripheral clock selection for CAN acceptance filtering.^[1]

[1] PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.

Table 41. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit

description

Bit

Symbol

Description

Reset

value

1:0

PCLK_QEI

Peripheral clock selection for the Quadrature Encoder

Interface.

00

3:2

5:4

7:6

9:8

PCLK_GPIOINT

PCLK_PCB

PCLK_I2C1

-

Peripheral clock selection for GPIO interrupts.

Peripheral clock selection for the Pin Connect block.

Peripheral clock selection for I²C1.

Reserved.

00

NA

00

NA

00

11:10 PCLK_SSP0

13:12 PCLK_TIMER2

15:14 PCLK_TIMER3

17:16 PCLK_UART2

19:18 PCLK_UART3

21:20 PCLK_I2C2

23:22 PCLK_I2S

Peripheral clock selection for SSP0.

Peripheral clock selection for TIMER2.

Peripheral clock selection for TIMER3.

Peripheral clock selection for UART2.

Peripheral clock selection for UART3.

Peripheral clock selection for I²C2.

Peripheral clock selection for I²S.

Reserved.

25:24

-

27:26 PCLK_RIT

Peripheral clock selection for Repetitive Interrupt Timer.

29:28 PCLK_SYSCON Peripheral clock selection for the System Control block.

31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM.

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Table 42. Peripheral Clock Selection register bit values

PCLKSEL0 and PCLKSEL1 Function

individual peripheral’s clock

select options

Reset

value

00

01

10

11

PCLK_peripheral = CCLK/4

PCLK_peripheral = CCLK

PCLK_peripheral = CCLK/2

00

PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and

CAN filtering when “11” selects = CCLK/6.

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8. Power control

The LPC17xx supports a variety of power control features: Sleep mode, Deep Sleep

mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be

controlled as needed by changing clock sources, re-configuring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application requirements. In addition, Peripheral Power Control allows

shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application.

Entry to any reduced power mode begins with the execution of either a WFI (Wait For

Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3

internally supports two reduced power modes: Sleep and Deep Sleep. These are selected

by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep

Power-down modes are selected by bits in the PCON register. See Table 4–44. The same

register contains flags that indicate whether entry into each reduced power mode actually

occurred.

The LPC17xx also implements a separate power domain in order to allow turning off

power to the bulk of the device while maintaining operation of the Real Time Clock.

Reduced power modes have some limitation during debug, see Section 33–5 for more

information.

8.1 Sleep mode

Note: Sleep mode on the LPC17xx corresponds to the Idle mode on LPC2xxx series

devices. The name is changed because ARM has incorporated portions of reduced power

mode control into the Cortex-M3. LPC17xx documentation uses the Cortex-M3

terminology where applicable.

When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in

PCON is set, see Table 4–44.Resumption from the Sleep mode does not need any

special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

8.2 Deep Sleep mode

Note: Deep Sleep mode on the LPC17xx corresponds to the Sleep mode on LPC23xx

and LPC24xx series devices. The name is changed because ARM has incorporated

portions of reduced power mode control into the Cortex-M3. LPC17xx documentation

uses the Cortex-M3 terminology where applicable.

When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly

all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 4–44. The IRC

remains running and can be configured to drive the Watchdog Timer, allowing the

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Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC

interrupts may be used as a wake-up source. The flash is left in the standby mode

allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The

CCLK and USBCLK clock dividers automatically get reset to zero.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Deep Sleep mode and the logic levels of chip pins remain static.

The Deep Sleep mode can be terminated and normal operation resumed by either a

Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power

consumption to a very low value.

On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep

mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities

will resume after the timer expires (4 cycles). If the main external oscillator was used, the

12-bit main oscillator timer starts counting and the code execution will resume when the

timer expires (4096 cycles). The user must remember to re-configure any required PLLs

and clock dividers after the wake-up.

Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0

through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,

an RTC Alarm interrupt, a Watchdog Timer timeout, a USB input pin transition (USB

activity interrupt), or a CAN input pin transition, when the related interrupt is enabled.

Wake-up will occur whenever any enabled interrupt occurs.

8.3 Power-down mode

Power-down mode does everything that Deep Sleep mode does, but also turns off the

flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see

Table 4–44. This saves more power, but requires waiting for resumption of flash operation

before execution of code or data access in the flash memory can be accomplished.

When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are

stopped. The RTC remains running if it has been enabled and RTC interrupts may be

used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are

automatically turned off and disconnected. The CCLK and USBCLK clock dividers

automatically get reset to zero.

Upon wake-up from Power-down mode, if the IRC was used before entering Power-down

mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and

expiring in 4 cycles. Code execution can then be resumed immediately following the

expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash

wake-up timer measures flash start-up time of about 100 μs. When it times out, access to

the flash is enabled. The user must remember to re-configure any required PLLs and

clock dividers after the wake-up.

Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0

through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,

an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input

pin transition, when the related interrupt is enabled.

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8.4 Deep Power-down mode

In Deep Power-down mode, power is shut off to the entire chip with the exception of the

Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep

Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 4–44.

To optimize power conservation, the user has the additional option of turning off or

retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn

off power to the on-chip regulator via the V_DD(REG)(3V3)pins after entering Deep

Power-down mode.Power to the on-chip regulator must be restored before device

operation can be restarted.

Wake-up from Deep Power-down mode will occur when an external reset signal is

applied, or the RTC interrupt is enabled and an RTC interrupt is generated.

8.5 Peripheral power control

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings. This is

detailed in the description of the PCONP register.

8.6 Register description

The Power Control function uses registers shown in Table 4–43. More detailed

descriptions follow.

Table 43. Power Control registers

Name

Description

Access Reset

value^[1]

Address

PCON

Power Control Register. This register contains

control bits that enable some reduced power

operating modes of the LPC17xx. See

Table 4–44.

R/W

0x00

0x400F C0C0

PCONP Power Control for Peripherals Register. This

register contains control bits that enable and

disable individual peripheral functions, allowing

elimination of power consumption by peripherals

that are not needed.

R/W

0x400F C0C4

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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8.7 Power Mode Control register (PCON - 0x400F C0C0)

Controls for some reduced power modes and other power related controls are contained

in the PCON register, as described in Table 4–44.

Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description

Bit

Symbol

Description

Reset

value

0

PM0

Power mode control bit 0. This bit controls entry to the Power-down

mode. See Section 4–8.7.1 below for details.

0

1

PM1

Power mode control bit 1. This bit controls entry to the Deep

Power-down mode. See Section 4–8.7.1 below for details.

2

BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the

Brown-Out Detect circuitry will be turned off when chip Power-down

mode or Deep Sleep mode is entered, resulting in a further reduction

in power usage. However, the possibility of using Brown-Out Detect as

a wake-up source from the reduced power mode will be lost.

When 0, the Brown-Out Detect function remains active during

Power-down and Deep Sleep modes.

See the System Control Block chapter for details of Brown-Out

detection.

3

4

BOGD

BORD

-

Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect

circuitry is fully disabled at all times, and does not consume power.

0

When 0, the Brown-Out Detect circuitry is enabled.

See the System Control Block chapter for details of Brown-Out

detection.

Brown-Out Reset Disable. When BORD is 1, the BOD will not reset

the device when the V_DD(REG)(3V3)voltage dips goes below the BOD

reset trip level. The Brown-Out interrupt is not affected.

When BORD is 0, the BOD reset is enabled.

See the Section 3–5 for details of Brown-Out detection.

7:3

8

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

SMFLAG Sleep Mode entry flag. Set when the Sleep mode is successfully

entered. Cleared by software writing a one to this bit.

0 ^[1][2]

9

DSFLAG Deep Sleep entry flag. Set when the Deep Sleep mode is successfully 0 ^[1][2]

entered. Cleared by software writing a one to this bit.

10

11

PDFLAG Power-down entry flag. Set when the Power-down mode is

successfully entered. Cleared by software writing a one to this bit.

DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode 0 ^[1][3]

is successfully entered. Cleared by software writing a one to this bit.

0 ^[1][2]

31:12 -

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

[1] Only one of these flags will be valid at a specific time.

[2] Hardware reset only for a power-up of core power or by a brownout detect event.

[3] Hardware reset only for a power-up event on Vbat.

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8.7.1 Encoding of Reduced Power Modes

The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The

encoding of these bits allows backward compatibility with devices that previously only

supported Sleep and Power-down modes. Table 4–45 below shows the encoding for the

three reduced power modes supported by the LPC17xx.

Table 45. Encoding of reduced power modes

PM1, PM0

Description

00

Execution of WFI or WFE enters either Sleep or Deep Sleep mode as defined by the

SLEEPDEEP bit in the Cortex-M3 System Control Register.

01

Execution of WFI or WFE enters Power-down mode if the SLEEPDEEP bit in the

Cortex-M3 System Control Register is 1.

10

11

Reserved, this setting should not be used.

Execution of WFI or WFE enters Deep Power-down mode if the SLEEPDEEP bit in

the Cortex-M3 System Control Register is 1.

8.8 Wake-up from Reduced Power Modes

Any enabled interrupt can wake up the CPU from Sleep mode. Certain interrupts can

wake up the processor if it is in either Deep Sleep mode or Power-down mode.

Interrupts that can occur during Deep Sleep or Power-down mode will wake up the CPU if

the interrupt is enabled. After wake-up, execution will continue to the appropriate interrupt

service routine. These interrupts are NMI, External Interrupts EINT0 through EINT3, GPIO

interrupts, Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN Activity

Interrupt, and USB Activity Interrupt. In addition, the watchdog timer can wake up the part

from Deep Sleep mode if the watchdog timer is being clocked by the IRC oscillator. For

the wake-up process to take place the corresponding interrupt must be enabled in the

NVIC. For pin-related peripheral functions, the related functions must also be mapped to

pins.

The CAN Activity Interrupt is generated by activity on the CAN bus pins, and the USB

Activity Interrupt is generated by activity on the USB bus pins. These interrupts are only

useful to wake up the CPU when it is on Deep Sleep or Power-down mode, when the

peripheral functions are powered up, but not active. Typically, if these interrupts are used,

their flags should be polled just before enabling the interrupt and entering the desired

reduced power mode. This can save time and power by avoiding an immediate wake-up.

Upon wake-up, the interrupt service can turn off the related activity interrupt, do any

application specific setup, and exit to await a normal peripheral interrupt.

8.9 Power Control for Peripherals register (PCONP - 0x400F C0C4)

The PCONP register allows turning off selected peripheral functions for the purpose of

saving power. This is accomplished by gating off the clock source to the specified

peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,

the Pin Connect block, and the System Control block).

Some peripherals, particularly those that include analog functions, may consume power

that is not clock dependent. These peripherals may contain a separate disable control that

turns off additional circuitry to reduce power. Information on peripheral specific power

saving features may be found in the chapter describing that peripheral.

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Each bit in PCONP controls one peripheral as shown in Table 4–46.

If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that

peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the

I²C1 interface is enabled. If bit 19 is 0, the I²C1 interface is disabled.

Important: valid read from a peripheral register and valid write to a peripheral

register is possible only if that peripheral is enabled in the PCONP register!

Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit

description

Bit Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

-

Reserved.

NA

1

PCTIM0

PCTIM1

PCUART0

PCUART1

-

Timer/Counter 0 power/clock control bit.

Timer/Counter 1 power/clock control bit.

UART0 power/clock control bit.

UART1 power/clock control bit.

Reserved.

1

NA

1

PCPWM1

PCI2C0

PCSPI

PCRTC

PWM1 power/clock control bit.

The I²C0 interface power/clock control bit.

The SPI interface power/clock control bit.

The RTC power/clock control bit.

The SSP 1 interface power/clock control bit.

Reserved.

1

10 PCSSP1

11

1

-

NA

0

12 PCADC

A/D converter (ADC) power/clock control bit.

Note: Clear the PDN bit in the AD0CR before clearing this bit, and set

this bit before setting PDN.

13 PCCAN1

14 PCCAN2

CAN Controller 1 power/clock control bit.

CAN Controller 2 power/clock control bit.

Reserved.

0

15

-

NA

0

16 PCRIT

Repetitive Interrupt Timer power/clock control bit.

17 PCMCPWM Motor Control PWM

0

18 PCQEI

19 PCI2C1

Quadrature Encoder Interface power/clock control bit.

0

The I²C1 interface power/clock control bit.

1

20

-

Reserved.

NA

1

21 PCSSP0

22 PCTIM2

23 PCTIM3

24 PCUART2

25 PCUART3

26 PCI2C2

27 PCI2S

The SSP0 interface power/clock control bit.

Timer 2 power/clock control bit.

Timer 3 power/clock control bit.

UART 2 power/clock control bit.

UART 3 power/clock control bit.

I²C interface 2 power/clock control bit.

I²S interface power/clock control bit.

Reserved.

0

1

0

28

-

NA

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Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit

description

Bit Symbol

Description

Reset

value

29 PCGPDMA GPDMA function power/clock control bit.

0

30 PCENET

31 PCUSB

Ethernet block power/clock control bit.

USB interface power/clock control bit.

Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC,

its output must be selected to appear on the related pin, P0.26, by configuring the

PINSEL1 register. See Section 8–5.2 “Pin Function Select Register 1 (PINSEL1 -

0x4002 C004)”.

8.10 Power control usage notes

After every reset, the PCONP register contains the value that enables selected interfaces

and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper

configuring via peripheral dedicated registers, the user’s application might have to access

the PCONP in order to start using some of the on-board peripherals.

Power saving oriented systems should have 1s in the PCONP register only in positions

that match peripherals really used in the application. All other bits, declared to be

"Reserved" or dedicated to the peripherals not used in the current application, must be

cleared to 0.

8.11 Power domains

The LPC17xx provides two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the Real Time Clock.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of

power to operate, which can be supplied by an external battery. Whenever the device core

power is present, that power is used to operate the RTC, causing no power drain from a

battery when main power is available.

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9. Wake-up timer

The LPC17xx begins operation at power-up and when awakened from Power-down mode

by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin

quickly. If the main oscillator or one or both PLLs are needed by the application, software

will need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power-on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DD(REG)(3V3)ramp (in the case of power on), the type

of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other

external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the

existing ambient conditions.

Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096),

then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator

is ready for use. Software can then switch to the main oscillator and start any required

PLLs. Refer to the Main Oscillator description in this chapter for details.

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10. External clock output pin

For system test and development purposes, any one of several internal clocks may be

brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 4–12.

Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator

(osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock

(rtc_clk).

CLKOUTCFG[3:0]

cclk

CLKOUTCFG[7:4]

CLKOUTCFG[8]

000

001

010

011

100

osc_clk

irc_osc

usb_clk

rtc_clk

CLKOUT

Divider

Clock Enable

Syncronizer

CLKOUTCFG[9]

Fig 12. CLKOUT selection

10.1 Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8)

The CLKOUTCFG register controls the selection of the internal clock that appears on the

CLKOUT pin and allows dividing the clock by an integer value up to 16. The divider can be

used to produce a system clock that is related to one of the on-chip clocks. For most clock

sources, the division may be by 1. When the CPU clock is selected and is higher than

approximately 50 MHz, the output must be divided in order to bring the frequency within

the ability of the pin to switch with reasonable logic levels.

Note: The CLKOUT multiplexer is designed to switch cleanly, without glitches, between

the possible clock sources. The divider is also designed to allow changing the divide value

without glitches.

Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description

Bit

Symbol

Value Description

Reset

value

3:0

CLKOUTSEL

Selects the clock source for the CLKOUT function.

0

0000 Selects the CPU clock as the CLKOUT source.

0001 Selects the main oscillator as the CLKOUT source.

0010 Selects the Internal RC oscillator as the CLKOUT source

(default).

0011 Selects the USB clock as the CLKOUT source.

0100 Selects the RTC oscillator as the CLKOUT source.

others Reserved, do not use these settings.

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Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description

Bit

Symbol

Value Description

Reset

value

7:4

CLKOUTDIV

Integer value to divide the output clock by, minus one.

0

0000 Clock is divided by 1.

0001 Clock is divided by 2.

0010 Clock is divided by 3.

...

1111

Clock is divided by 16.

8

9

CLKOUT_EN

CLKOUT enable control, allows switching the CLKOUT

source without glitches. Clear to stop CLKOUT on the

next falling edge. Set to enable CLKOUT. Used in concert

with the CLKOUT_EN bit below.

0

CLKOUT_ACT

CLKOUT activity indication. Reads as 1 when CLKOUT is

enabled. Read as 0 when CLKOUT has been disabled via

the CLKOUT_EN bit and the clock has completed being

stopped.

31:10 -

Reserved, user software should not write ones to reserved NA

bits. The value read from a reserved bit is not defined.

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1. Introduction

The flash accelerator block in the LPC17xx allows maximization of the performance of the

Cortex-M3 processor when it is running code from flash memory, while also saving power.

The flash accelerator also provides speed and power improvements for data accesses to

the flash memory.

2. Flash accelerator blocks

The flash accelerator is divided into several functional blocks:

• AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as

well as by the General Purpose DMA Controller

• An array of eight 128-bit buffers

• Flash accelerator control logic, including address compare and flash control

• A flash memory interface

Figure 5–13 shows a simplified diagram of the flash accelerator blocks and data paths.

Bus

Matrix

DCode

bus

Flash Accelerator

Combined

AHB

Cortex-M3

CPU

AHB-Lite

bus interface

Buffer

Array

Flash

Interface

Flash

Memory

ICode

bus

Flash

Accelerator

Control

DMA

Master Port

General

Purpose

DMA

Controller

Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections

In the following descriptions, the term “fetch” applies to an explicit flash read request from

the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current

processor fetch address.

2.1 Flash memory bank

There is one bank of flash memory controlled by the LPC17xx flash accelerator.

Flash programming operations are not controlled by the flash accelerator, but are handled

as a separate function. A Boot ROM contains flash programming algorithms that may be

called as part of the application program, and a loader that may be run to allow

programming of the flash memory.

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2.2 Flash programming Issues

Since the flash memory does not allow accesses during programming and erase

operations, it is necessary for the flash accelerator to force the CPU to wait if a memory

access to a flash address is requested while the flash memory is busy with a

programming operation. Under some conditions, this delay could result in a Watchdog

time-out. The user will need to be aware of this possibility and take steps to insure that an

unwanted Watchdog reset does not cause a system failure while programming or erasing

the flash memory.

In order to preclude the possibility of stale data being read from the flash memory, the

LPC17xx flash accelerator buffers are automatically invalidated at the beginning of any

flash programming or erase operation. Any subsequent read from a flash address will

cause a new fetch to be initiated after the flash operation has completed.

3. Register description

The flash accelerator is controlled by the register shown in Table 5–48. More detailed

descriptions follow.

Table 48. Summary of flash accelerator registers

Name

Description

Access Reset

value^[1]

Address

FLASHCFG

Flash Accelerator Configuration Register.

R/W

0x303A 0x400F C000

Controls flash access timing. See Table 5–49.

[1] Reset Value reflects the data stored in defined bits only. It does not include reserved bits content.

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Chapter 5: LPC17xx Flash accelerator

4. Flash Accelerator Configuration register (FLASHCFG - 0x400F C000)

Configuration bits select the flash access time, as shown in Table 5–49. The lower bits of

FLASHCFG control internal flash accelerator functions and should not be altered.

Following reset, flash accelerator functions are enabled and flash access timing is set to a

default value of 4 clocks.

Changing the FLASHCFG register value causes the flash accelerator to invalidate all of

the holding latches, resulting in new reads of flash information as required. This

guarantees synchronization of the flash accelerator to CPU operation.

Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description

Bit

Symbol

Value Description

Reset

value

11:0

-

Reserved, user software should not change these bits from the reset value.

0x03A

15:12 FLASHTIM

Flash access time. The value of this field plus 1 gives the number of CPU clocks used 0x3

for a flash access.

Warning: improper setting of this value may result in incorrect operation of the device.

Important Note: Frequency values shown below are estimates at this time.

0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.

0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.

0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.

0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.

0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock.

Use for up to 120 Mhz for LPC1759 and LPC1769 only.

0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions.

Other Intended for potential future higher speed devices.

31:16

-

Reserved. The value read from a reserved bit is not defined.

NA

5. Operation

Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will

be needed in its latches in time to prevent CPU fetch stalls. The LPC17xx uses one bank

of flash memory. The flash accelerator includes an array of eight 128-bit buffers to store

both instructions and data in a configurable manner. Each 128-bit buffer in the array can

include four 32-bit instructions, eight 16-bit instructions or some combination of the two.

During sequential code execution, a buffer typically contains the current instruction and

the entire flash line that contains that instruction, or one flash line of data containing a

previously requested address. Buffers are marked according to how they are used (as

instruction or data buffers), and when they have been accessed. This information is used

to carry out the buffer replacement strategy.

The Cortex-M3 provides a separate bus for instruction access (I-code) and data access

(D-code) in the code memory space. These buses, plus the General Purpose DMA

Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the

flash memory’s address space is presented to the flash accelerator.

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If a flash instruction fetch and a flash data access from the CPU occur at the same time,

the multilayer matrix gives precedence to the data access. This is because a stalled data

access always slows down execution, while a stalled instruction fetch often does not.

When the flash data access is concluded, any flash fetch or prefetch that had been in

progress is re-initiated.

Branches and other program flow changes cause a break in the sequential flow of

instruction fetches described above. Buffer replacement strategy in the flash accelerator

attempts to maximize the chances that potentially reusable information is retained until it

is needed again.

If an attempt is made to write directly to the flash memory without using the normal flash

programming interface (via Boot ROM function calls), the flash accelerator generates an

error condition. The CPU treats this error as a data abort. The GPDMA handles error

conditions as described in Section 31–4.1.6.3.

When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has

a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated

for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the

CPU is stalled for a shorter time since the required flash access is already in progress.

Typically, a flash prefetch is begun whenever an access is made to a just prefetched

address, or to a buffer whose immediate successor is not already in another buffer. A

prefetch in progress may be aborted by a data access, in order to minimize CPU stalls.

A prefetched flash line is latched within the flash memory, but the flash accelerator does

not capture the line in a buffer until the CPU presents an address that is contained within

the prefetched flash line. If the core presents an instruction address that is not already

buffered and is not contained in the prefetched flash line, the prefetched line will be

discarded.

Some special cases include the possibility that the CPU will request a data access to an

address already contained in an instruction buffer. In this case, the data will be read from

the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction

address that can be satisfied from an existing data buffer, causes the instruction to be

supplied from the data buffer, and the buffer to be changed into an instruction buffer. This

causes the buffer to be handled differently when the flash accelerator is determining which

buffer is to be overwritten next.

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1. Features

• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3

• Tightly coupled interrupt controller provides low interrupt latency

• Controls system exceptions and peripheral interrupts

• In the LPC17xx, the NVIC supports 35 vectored interrupts

• 32 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table

• Non-Maskable Interrupt

• Software interrupt generation

2. Description

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

Refer to the Cortex-M3 User Guide Section 34–4.2 for details of NVIC operation.

3. Interrupt sources

Table 6–50 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source, as noted.

Exception numbers relate to where entries are stored in the exception vector table.

Interrupt numbers are used in some other contexts, such as software interrupts.

In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to

operate from an external signal, the NMI function must be connected to the related device

pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be

processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User

Manual.

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Table 50. Connection of interrupt sources to the Vectored Interrupt Controller

Interrupt Exception Vector Function

Flag(s)

ID

Number

Offset

0

16

0x40

WDT

Watchdog Interrupt (WDINT)

Match 0 - 1 (MR0, MR1)

1

17

0x44

Timer 0

Capture 0 - 1 (CR0, CR1)

Match 0 - 2 (MR0, MR1, MR2)

Capture 0 - 1 (CR0, CR1)

Match 0-3

2

3

4

5

18

19

20

21

0x48

0x4C

0x50

0x54

Timer 1

Timer 2

Timer 3

UART0

Capture 0-1

Match 0-3

Capture 0-1

Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

Rx Line Status (RLS)

6

22

0x58

UART1

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Control Change

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

Rx Line Status (RLS)

7

8

9

23

24

25

0x5C

0x60

0x64

UART 2

UART 3

PWM1

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

Rx Line Status (RLS)

Transmit Holding Register Empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

End of Auto-Baud (ABEO)

Auto-Baud Time-Out (ABTO)

Match 0 - 6 of PWM1

Capture 0-1 of PWM1

10

11

12

13

26

27

28

29

0x68

0x6C

0x70

0x74

I²C0

I²C1

I²C2

SPI

SI (state change)

SPI Interrupt Flag (SPIF)

Mode Fault (MODF)

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Table 50. Connection of interrupt sources to the Vectored Interrupt Controller

Interrupt Exception Vector Function

Flag(s)

ID

Number

Offset

14

30

0x78

SSP0

Tx FIFO half empty of SSP0

Rx FIFO half full of SSP0

Rx Timeout of SSP0

Rx Overrun of SSP0

15

31

0x7C

SSP 1

Tx FIFO half empty

Rx FIFO half full

Rx Timeout

Rx Overrun

16

17

32

33

0x80

0x84

PLL0 (Main PLL)

RTC

PLL0 Lock (PLOCK0)

Counter Increment (RTCCIF)

Alarm (RTCALF)

18

19

20

21

34

35

36

37

0x88

0x8C

0x90

0x94

External Interrupt

External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3).

Note: EINT3 channel is shared with GPIO interrupts

A/D Converter end of conversion

Brown Out detect

22

23

24

25

26

27

28

38

39

40

41

42

43

44

0x98

0x9C

0xA0

0xA4

0xA8

0xAC

0xB0

ADC

BOD

USB

USB_INT_REQ_LP, USB_INT_REQ_HP, USB_INT_REQ_DMA

CAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx, CAN 1 Rx

IntStatus of DMA channel 0, IntStatus of DMA channel 1

irq, dmareq1, dmareq2

CAN

GPDMA

I²S

Ethernet

WakeupInt, SoftInt, TxDoneInt, TxFinishedInt, TxErrorInt,

TxUnderrunInt, RxDoneInt, RxFinishedInt, RxErrorInt,

RxOverrunInt.

29

45

0xB4

Repetitive Interrupt

Timer

RITINT

30

31

46

47

0xB8

0xBC

Motor Control PWM

IPER[2:0], IPW[2:0], ICAP[2:0], FES

Quadrature Encoder INX_Int, TIM_Int, VELC_Int, DIR_Int, ERR_Int, ENCLK_Int,

POS0_Int, POS1_Int, POS2_Int, REV_Int, POS0REV_Int,

POS1REV_Int, POS2REV_Int

32

33

34

48

49

50

0xC0

0xC4

0xC8

PLL1 (USB PLL)

PLL1 Lock (PLOCK1)

USB Activity Interrupt USB_NEED_CLK

CAN Activity Interrupt CAN1WAKE, CAN2WAKE

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4. Vector table remapping

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

Register (VTOR) contained in the Cortex-M3.

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table should be located on a 256 word (1024 byte) boundary to insure

alignment on LPC17xx family devices. Refer to Section 34–4.3.5 of the Cortex-M3 User

Guide appended to this manual for details of the Vector Table Offset feature.

ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code

or SRAM. For simplicity, this bit can be thought as simply part of the address offset since

the split between the “code” space and the “SRAM” space occurs at the location

corresponding to bit 29 in a memory address.

Examples:

To place the vector table at the beginning of the “local” static RAM, starting at address

0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address

0x1000 0000 in the code space, since bit 29 of the VTOR equals 0.

To place the vector table at the beginning of the AHB static RAM, starting at address

0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address

0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1.

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5. Register description

The following table summarizes the registers in the NVIC as implemented in the LPC17xx.

The Cortex-M3 User Guide Section 34–4.2 provides a functional description of the NVIC.

Table 51. NVIC register map

Name Description

Access Reset Address

value

ISER0 to Interrupt Set-Enable Registers. These 2 registers allow enabling

RW

0

ISER0 - 0xE000 E100

ISER1 - 0xE000 E104

ISER1

interrupts and reading back the interrupt enables for specific

peripheral functions.

ICER0to Interrupt Clear-Enable Registers. These 2 registers allow disabling RW

ICER0 - 0xE000 E180

ICER1 - 0xE000 E184

ICER1

interrupts and reading back the interrupt enables for specific

peripheral functions.

ISPR0 to Interrupt Set-Pending Registers. These 2 registers allow changing RW

ISPR0 - 0xE000 E200

ISPR1 - 0xE000 E204

ISPR1

the interrupt state to pending and reading back the interrupt

pending state for specific peripheral functions.

ICPR0to Interrupt Clear-Pending Registers. These 2 registers allow

RW

ICPR0 - 0xE000 E280

ICPR1 - 0xE000 E284

ICPR1

changing the interrupt state to not pending and reading back the

interrupt pending state for specific peripheral functions.

IABR0 to Interrupt Active Bit Registers. These 2 registers allow reading the

IABR1 current interrupt active state for specific peripheral functions.

RO

0

IABR0 - 0xE000 E300

IABR1 - 0xE000 E304

IPR0 - 0xE000 E400

IPR1 - 0xE000 E404

IPR2 - 0xE000 E408

IPR3 - 0xE000 E40C

IPR4 - 0xE000 E410

IPR5 - 0xE000 E414

IPR6 - 0xE000 E418

IPR7 - 0xE000 E41C

IPR8 - 0xE000 E420

STIR - 0xE000 EF00

IPR0 to Interrupt Priority Registers. These 9 registers allow assigning a

RW

IPR8

priority to each interrupt. Each register contains the 5-bit priority

fields for 4 interrupts.

STIR

Software Trigger Interrupt Register. This register allows software to WO

generate an interrupt.

0

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5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)

The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the

enabled state of those interrupts. The remaining interrupts are enabled via the ISER1

register (Section 6–5.2). Disabling interrupts is done through the ICER0 and ICER1

registers (Section 6–5.3 and Section 6–5.4).

Table 52. Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)

Bit

Name

Function

0

ISE_WDT

Watchdog Timer Interrupt Enable.

Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Timer 0 Interrupt Enable. See functional description for bit 0.

Timer 1. Interrupt Enable. See functional description for bit 0.

Timer 2 Interrupt Enable. See functional description for bit 0.

Timer 3 Interrupt Enable. See functional description for bit 0.

UART0 Interrupt Enable. See functional description for bit 0.

UART1 Interrupt Enable. See functional description for bit 0.

UART2 Interrupt Enable. See functional description for bit 0.

UART3 Interrupt Enable. See functional description for bit 0.

PWM1 Interrupt Enable. See functional description for bit 0.

I²C0 Interrupt Enable. See functional description for bit 0.

I²C1 Interrupt Enable. See functional description for bit 0.

I²C2 Interrupt Enable. See functional description for bit 0.

SPI Interrupt Enable. See functional description for bit 0.

SSP0 Interrupt Enable. See functional description for bit 0.

SSP1 Interrupt Enable. See functional description for bit 0.

PLL0 (Main PLL) Interrupt Enable. See functional description for bit 0.

Real Time Clock (RTC) Interrupt Enable. See functional description for bit 0.

External Interrupt 0 Interrupt Enable. See functional description for bit 0.

External Interrupt 1 Interrupt Enable. See functional description for bit 0.

External Interrupt 2 Interrupt Enable. See functional description for bit 0.

External Interrupt 3 Interrupt Enable. See functional description for bit 0.

ADC Interrupt Enable. See functional description for bit 0.

BOD Interrupt Enable. See functional description for bit 0.

USB Interrupt Enable. See functional description for bit 0.

CAN Interrupt Enable. See functional description for bit 0.

GPDMA Interrupt Enable. See functional description for bit 0.

I²S Interrupt Enable. See functional description for bit 0.

1

ISE_TIMER0

ISE_TIMER1

ISE_TIMER2

ISE_TIMER3

ISE_UART0

ISE_UART1

ISE_UART2

ISE_UART3

ISE_PWM

ISE_I2C0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ISE_I2C1

ISE_I2C2

ISE_SPI

ISE_SSP0

ISE_SSP1

ISE_PLL0

ISE_RTC

ISE_EINT0

ISE_EINT1

ISE_EINT2

ISE_EINT3

ISE_ADC

ISE_BOD

ISE_USB

ISE_CAN

ISE_DMA

ISE_I2S

ISE_ENET

ISE_RIT

Ethernet Interrupt Enable. See functional description for bit 0.

Repetitive Interrupt Timer Interrupt Enable. See functional description for bit 0.

Motor Control PWM Interrupt Enable. See functional description for bit 0.

Quadrature Encoder Interface Interrupt Enable. See functional description for bit 0.

ISE_MCPWM

ISE_QEI

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5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)

The ISER1 register allows enabling the second group of peripheral interrupts, or for

reading the enabled state of those interrupts. Disabling interrupts is done through the

ICER0 and ICER1 registers (Section 6–5.3 and Section 6–5.4).

Table 53. Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)

Bit

Name

Function

0

ISE_PLL1

PLL1 (USB PLL) Interrupt Enable.

Write: writing 0 has no effect, writing 1 enables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

USB Activity Interrupt Enable. See functional description for bit 0.

1

ISE_USBACT

2

ISE_CANACT CAN Activity Interrupt Enable. See functional description for bit 0.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit

is not defined.

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5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180)

The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the

enabled state of those interrupts. The remaining interrupts are disabled via the ICER1

register (Section 6–5.4). Enabling interrupts is done through the ISER0 and ISER1

registers (Section 6–5.1 and Section 6–5.2).

Table 54. Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180)

Bit

Name

Function

0

ICE_WDT

Watchdog Timer Interrupt Disable.

Write: writing 0 has no effect, writing 1 disables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Timer 0 Interrupt Disable. See functional description for bit 0.

Timer 1. Interrupt Disable. See functional description for bit 0.

Timer 2 Interrupt Disable. See functional description for bit 0.

Timer 3 Interrupt Disable. See functional description for bit 0.

UART0 Interrupt Disable. See functional description for bit 0.

UART1 Interrupt Disable. See functional description for bit 0.

UART2 Interrupt Disable. See functional description for bit 0.

UART3 Interrupt Disable. See functional description for bit 0.

PWM1 Interrupt Disable. See functional description for bit 0.

I²C0 Interrupt Disable. See functional description for bit 0.

I²C1 Interrupt Disable. See functional description for bit 0.

I²C2 Interrupt Disable. See functional description for bit 0.

SPI Interrupt Disable. See functional description for bit 0.

SSP0 Interrupt Disable. See functional description for bit 0.

SSP1 Interrupt Disable. See functional description for bit 0.

PLL0 (Main PLL) Interrupt Disable. See functional description for bit 0.

Real Time Clock (RTC) Interrupt Disable. See functional description for bit 0.

External Interrupt 0 Interrupt Disable. See functional description for bit 0.

External Interrupt 1 Interrupt Disable. See functional description for bit 0.

External Interrupt 2 Interrupt Disable. See functional description for bit 0.

External Interrupt 3 Interrupt Disable. See functional description for bit 0.

ADC Interrupt Disable. See functional description for bit 0.

BOD Interrupt Disable. See functional description for bit 0.

USB Interrupt Disable. See functional description for bit 0.

CAN Interrupt Disable. See functional description for bit 0.

GPDMA Interrupt Disable. See functional description for bit 0.

I²S Interrupt Disable. See functional description for bit 0.

1

ICE_TIMER0

ICE_TIMER1

ICE_TIMER2

ICE_TIMER3

ICE_UART0

ICE_UART1

ICE_UART2

ICE_UART3

ICE_PWM

ICE_I2C0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ICE_I2C1

ICE_I2C2

ICE_SPI

ICE_SSP0

ICE_SSP1

ICE_PLL0

ICE_RTC

ICE_EINT0

ICE_EINT1

ICE_EINT2

ICE_EINT3

ICE_ADC

ICE_BOD

ICE_USB

ICE_CAN

ICE_DMA

ICE_I2S

ICE_ENET

ICE_RIT

Ethernet Interrupt Disable. See functional description for bit 0.

Repetitive Interrupt Timer Interrupt Disable. See functional description for bit 0.

Motor Control PWM Interrupt Disable. See functional description for bit 0.

Quadrature Encoder Interface Interrupt Disable. See functional description for bit 0.

ICE_MCPWM

ICE_QEI

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5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)

The ICER1 register allows disabling the second group of peripheral interrupts, or for

reading the enabled state of those interrupts. Enabling interrupts is done through the

ISER0 and ISER1 registers (Section 6–5.1 and Section 6–5.2).

Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)

Bit

Name

Function

0

ICE_PLL1

PLL1 (USB PLL) Interrupt Disable.

Write: writing 0 has no effect, writing 1 disables the interrupt.

Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

1

ICE_USBACT USB Activity Interrupt Disable. See functional description for bit 0.

ICE_CANACT CAN Activity Interrupt Disable. See functional description for bit 0.

2

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit

is not defined.

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5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)

The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or

for reading the pending state of those interrupts. The remaining interrupts can have their

pending state set via the ISPR1 register (Section 6–5.6). Clearing the pending state of

interrupts is done through the ICPR0 and ICPR1 registers (Section 6–5.7 and

Section 6–5.8).

Table 56. Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)

Bit

Name

Function

0

ISP_WDT

Watchdog Timer Interrupt Pending set.

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.

Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

Timer 0 Interrupt Pending set. See functional description for bit 0.

Timer 1. Interrupt Pending set. See functional description for bit 0.

Timer 2 Interrupt Pending set. See functional description for bit 0.

Timer 3 Interrupt Pending set. See functional description for bit 0.

UART0 Interrupt Pending set. See functional description for bit 0.

UART1 Interrupt Pending set. See functional description for bit 0.

UART2 Interrupt Pending set. See functional description for bit 0.

UART3 Interrupt Pending set. See functional description for bit 0.

PWM1 Interrupt Pending set. See functional description for bit 0.

I²C0 Interrupt Pending set. See functional description for bit 0.

I²C1 Interrupt Pending set. See functional description for bit 0.

I²C2 Interrupt Pending set. See functional description for bit 0.

SPI Interrupt Pending set. See functional description for bit 0.

SSP0 Interrupt Pending set. See functional description for bit 0.

SSP1 Interrupt Pending set. See functional description for bit 0.

PLL0 (Main PLL) Interrupt Pending set. See functional description for bit 0.

Real Time Clock (RTC) Interrupt Pending set. See functional description for bit 0.

External Interrupt 0 Interrupt Pending set. See functional description for bit 0.

External Interrupt 1 Interrupt Pending set. See functional description for bit 0.

External Interrupt 2 Interrupt Pending set. See functional description for bit 0.

External Interrupt 3 Interrupt Pending set. See functional description for bit 0.

ADC Interrupt Pending set. See functional description for bit 0.

BOD Interrupt Pending set. See functional description for bit 0.

USB Interrupt Pending set. See functional description for bit 0.

CAN Interrupt Pending set. See functional description for bit 0.

GPDMA Interrupt Pending set. See functional description for bit 0.

I²S Interrupt Pending set. See functional description for bit 0.

Ethernet Interrupt Pending set. See functional description for bit 0.

Repetitive Interrupt Timer Interrupt Pending set. See functional description for bit 0.

Motor Control PWM Interrupt Pending set. See functional description for bit 0.

Quadrature Encoder Interface Interrupt Pending set. See functional description for bit 0.

1

ISP_TIMER0

ISP_TIMER1

ISP_TIMER2

ISP_TIMER3

ISP_UART0

ISP_UART1

ISP_UART2

ISP_UART3

ISP_PWM

ISP_I2C0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ISP_I2C1

ISP_I2C2

ISP_SPI

ISP_SSP0

ISP_SSP1

ISP_PLL0

ISP_RTC

ISP_EINT0

ISP_EINT1

ISP_EINT2

ISP_EINT3

ISP_ADC

ISP_BOD

ISP_USB

ISP_CAN

ISP_DMA

ISP_I2S

ISP_ENET

ISP_RIT

ISP_MCPWM

ISP_QEI

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5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)

The ISPR1 register allows setting the pending state of the second group of peripheral

interrupts, or for reading the pending state of those interrupts. Clearing the pending state

of interrupts is done through the ICPR0 and ICPR1 registers (Section 6–5.7 and

Section 6–5.8).

Table 57. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)

Bit

Name

Function

0

ISP_PLL1

PLL1 (USB PLL) Interrupt Pending set.

Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.

Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

USB Activity Interrupt Pending set. See functional description for bit 0.

1

ISP_USBACT

2

ISP_CANACT CAN Activity Interrupt Pending set. See functional description for bit 0.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit

is not defined.

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5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)

The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts,

or for reading the pending state of those interrupts. The remaining interrupts can have

their pending state cleared via the ICPR1 register (Section 6–5.8). Setting the pending

state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6–5.5 and

Section 6–5.6).

Table 58. Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)

Bit

Name

Function

0

ICP_WDT

Watchdog Timer Interrupt Pending clear.

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.

Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

Timer 0 Interrupt Pending clear. See functional description for bit 0.

Timer 1. Interrupt Pending clear. See functional description for bit 0.

Timer 2 Interrupt Pending clear. See functional description for bit 0.

Timer 3 Interrupt Pending clear. See functional description for bit 0.

UART0 Interrupt Pending clear. See functional description for bit 0.

UART1 Interrupt Pending clear. See functional description for bit 0.

UART2 Interrupt Pending clear. See functional description for bit 0.

UART3 Interrupt Pending clear. See functional description for bit 0.

PWM1 Interrupt Pending clear. See functional description for bit 0.

I²C0 Interrupt Pending clear. See functional description for bit 0.

I²C1 Interrupt Pending clear. See functional description for bit 0.

I²C2 Interrupt Pending clear. See functional description for bit 0.

SPI Interrupt Pending clear. See functional description for bit 0.

SSP0 Interrupt Pending clear. See functional description for bit 0.

SSP1 Interrupt Pending clear. See functional description for bit 0.

PLL0 (Main PLL) Interrupt Pending clear. See functional description for bit 0.

Real Time Clock (RTC) Interrupt Pending clear. See functional description for bit 0.

External Interrupt 0 Interrupt Pending clear. See functional description for bit 0.

External Interrupt 1 Interrupt Pending clear. See functional description for bit 0.

External Interrupt 2 Interrupt Pending clear. See functional description for bit 0.

External Interrupt 3 Interrupt Pending clear. See functional description for bit 0.

ADC Interrupt Pending clear. See functional description for bit 0.

BOD Interrupt Pending clear. See functional description for bit 0.

USB Interrupt Pending clear. See functional description for bit 0.

CAN Interrupt Pending clear. See functional description for bit 0.

GPDMA Interrupt Pending clear. See functional description for bit 0.

I²S Interrupt Pending clear. See functional description for bit 0.

Ethernet Interrupt Pending clear. See functional description for bit 0.

Repetitive Interrupt Timer Interrupt Pending clear. See functional description for bit 0.

Motor Control PWM Interrupt Pending clear. See functional description for bit 0.

Quadrature Encoder Interface Interrupt Pending clear. See functional description for bit 0.

1

ICP_TIMER0

ICP_TIMER1

ICP_TIMER2

ICP_TIMER3

ICP_UART0

ICP_UART1

ICP_UART2

ICP_UART3

ICP_PWM

ICP_I2C0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

ICP_I2C1

ICP_I2C2

ICP_SPI

ICP_SSP0

ICP_SSP1

ICP_PLL0

ICP_RTC

ICP_EINT0

ICP_EINT1

ICP_EINT2

ICP_EINT3

ICP_ADC

ICP_BOD

ICP_USB

ICP_CAN

ICP_DMA

ICP_I2S

ICP_ENET

ICP_RIT

ICP_MCPWM

ICP_QEI

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5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284)

The ICPR1 register allows clearing the pending state of the second group of peripheral

interrupts, or for reading the pending state of those interrupts. Setting the pending state of

interrupts is done through the ISPR0 and ISPR1 registers (Section 6–5.5 and

Section 6–5.6).

Table 59. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)

Bit

Name

Function

0

ICP_PLL1

PLL1 (USB PLL) Interrupt Pending clear.

Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.

Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

1

ICP_USBACT USB Activity Interrupt Pending clear. See functional description for bit 0.

ICP_CANACT CAN Activity Interrupt Pending clear. See functional description for bit 0.

2

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit

is not defined.

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5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300)

The IABR0 register is a read-only register that allows reading the active state of the first

32 peripheral interrupts. This allows determining which peripherals are asserting an

interrupt to the NVIC, and may also be pending if there are enabled. The remaining

interrupts can have their active state read via the IABR1 register (Section 6–5.10).

Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300)

Bit

Name

Function

0

IAB_WDT

Watchdog Timer Interrupt Active.

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

Timer 0 Interrupt Active. See functional description for bit 0.

Timer 1. Interrupt Active. See functional description for bit 0.

Timer 2 Interrupt Active. See functional description for bit 0.

Timer 3 Interrupt Active. See functional description for bit 0.

UART0 Interrupt Active. See functional description for bit 0.

UART1 Interrupt Active. See functional description for bit 0.

UART2 Interrupt Active. See functional description for bit 0.

UART3 Interrupt Active. See functional description for bit 0.

PWM1 Interrupt Active. See functional description for bit 0.

I²C0 Interrupt Active. See functional description for bit 0.

I²C1 Interrupt Active. See functional description for bit 0.

I²C2 Interrupt Active. See functional description for bit 0.

SPI Interrupt Active. See functional description for bit 0.

SSP0 Interrupt Active. See functional description for bit 0.

SSP1 Interrupt Active. See functional description for bit 0.

PLL0 (Main PLL) Interrupt Active. See functional description for bit 0.

Real Time Clock (RTC) Interrupt Active. See functional description for bit 0.

External Interrupt 0 Interrupt Active. See functional description for bit 0.

External Interrupt 1 Interrupt Active. See functional description for bit 0.

External Interrupt 2 Interrupt Active. See functional description for bit 0.

External Interrupt 3 Interrupt Active. See functional description for bit 0.

ADC Interrupt Active. See functional description for bit 0.

BOD Interrupt Active. See functional description for bit 0.

USB Interrupt Active. See functional description for bit 0.

CAN Interrupt Active. See functional description for bit 0.

GPDMA Interrupt Active. See functional description for bit 0.

I²S Interrupt Active. See functional description for bit 0.

1

IAB_TIMER0

IAB_TIMER1

IAB_TIMER2

IAB_TIMER3

IAB_UART0

IAB_UART1

IAB_UART2

IAB_UART3

IAB_PWM

IAB_I2C0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

IAB_I2C1

IAB_I2C2

IAB_SPI

IAB_SSP0

IAB_SSP1

IAB_PLL0

IAB_RTC

IAB_EINT0

IAB_EINT1

IAB_EINT2

IAB_EINT3

IAB_ADC

IAB_BOD

IAB_USB

IAB_CAN

IAB_DMA

IAB_I2S

IAB_ENET

IAB_RIT

Ethernet Interrupt Active. See functional description for bit 0.

Repetitive Interrupt Timer Interrupt Active. See functional description for bit 0.

Motor Control PWM Interrupt Active. See functional description for bit 0.

Quadrature Encoder Interface Interrupt Active. See functional description for bit 0.

IAB_MCPWM

IAB_QEI

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5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)

The IABR1 register is a read-only register that allows reading the active state of the

second group of peripheral interrupts. This allows determining which peripherals are

asserting an interrupt to the NVIC, and may also be pending if there are enabled.

Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)

Bit

Name

Function

0

IAB_PLL1

PLL1 (USB PLL) Interrupt Active.

Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

USB Activity Interrupt Active. See functional description for bit 0.

1

IAB_USBACT

2

IAB_CANACT CAN Activity Interrupt Active. See functional description for bit 0.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit

is not defined.

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5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400)

The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can

have one of 32 priorities, where 0 is the highest priority.

Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_WDT Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_TIMER0

Timer 0 Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_TIMER1

Timer 1 Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_TIMER2

Timer 2 Interrupt Priority. See functional description for bits 7-3.

5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404)

The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000 E404)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_TIMER3 Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_UART0

UART0 Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_UART1

UART1 Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_UART2

UART2 Interrupt Priority. See functional description for bits 7-3.

5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408)

The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000 E408)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_UART3 UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_PWM

PWM Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_I2C0

I²C0 Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_I2C1

I²C1 Interrupt Priority. See functional description for bits 7-3.

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5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)

The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_I2C2

I²C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_SPI

SPI Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_SSP0

SSP0 Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_SSP1

SSP1 Interrupt Priority. See functional description for bits 7-3.

5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410)

The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000 E410)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_PLL0 PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_RTC

Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_EINT0

External Interrupt 0 Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_EINT1

External Interrupt 1 Interrupt Priority. See functional description for bits 7-3.

5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414)

The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_EINT2 External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_EINT3

External Interrupt 3 Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_ADC

ADC Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_BOD

BOD Interrupt Priority. See functional description for bits 7-3.

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5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418)

The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_USB USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_CAN

CAN Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_DMA

GPDMA Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_I2S

I²S Interrupt Priority. See functional description for bits 7-3.

5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)

The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each

interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_ENET Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_RIT

Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_MCPWM

Motor Control PWM Interrupt Priority. See functional description for bits 7-3.

26:24 Unimplemented These bits ignore writes, and read as 0.

31:27 IP_QEI

Quadrature Encoder Interface Interrupt Priority. See functional description for bits 7-3.

5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420)

The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts.

Each interrupt can have one of 32 priorities, where 0 is the highest priority.

Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000 E420)

Bit

2:0

7:3

Name

Unimplemented These bits ignore writes, and read as 0.

IP_PLL1 PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.

Function

10:8 Unimplemented These bits ignore writes, and read as 0.

15:11 IP_USBACT

USB Activity Interrupt Priority. See functional description for bits 7-3.

18:16 Unimplemented These bits ignore writes, and read as 0.

23:19 IP_CANACT

CAN Activity Interrupt Priority. See functional description for bits 7-3.

31:24 Unimplemented These bits ignore writes, and read as 0.

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5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00)

The STIR register provides an alternate way for software to generate an interrupt, in

addition to using the ISPR registers. This mechanism can only be used to generate

peripheral interrupts, not system exceptions.

By default, only privileged software can write to the STIR register. Unprivileged software

can be given this ability if privileged software sets the USERSETMPEND bit in the CCR

register (see Section 34–4.3.8).

Table 71. Software Trigger Interrupt Register (STIR - 0xE000 EF00)

Bit

Name

Function

8:0

INTID

Writing a value to this field generates an interrupt for the specified the interrupt number (see

Table 6–50). The range allowed for the LPC17xx is 0 to 111.

31:9

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved

bit is not defined.

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1. LPC17xx pin configuration

1

75

25

51

002aad945_1

Fig 14. LPC176x LQFP100 pin configuration

1

60

20

41

002aae158

Fig 15. LPC175x LQFP80 pin configuration

1.1 LPC17xx pin description

I/O pins on the LPC17xx are 5V tolerant and have input hysteresis unless indicated in the

table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In

addition, when pins are selected to be A to D converter inputs, they are no longer 5V

tolerant and must be limited to the voltage at the ADC positive reference pin (V_REFP).

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Table 72. Pin description

Symbol

LQFP

100

LQFP

80

Type Description

P0[0] to P0[31]

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each

bit. The operation of port 0 pins depends upon the pin function selected via

the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.

P0[0] / RD1 /

TXD3 / SDA1

46

47

37

38

I/O

I

P0[0] — General purpose digital input/output pin.

RD1 — CAN1 receiver input.

O

TXD3 — Transmitter output for UART3.

SDA1 — I²C1 data input/output (this pin is not fully compliant with the

I²C-bus specification, see Section 19–4 for details).

I/O

P0[1] / TD1 /

RXD3 / SCL1

I/O

O

P0[1] — General purpose digital input/output pin.

TD1 — CAN1 transmitter output.

I

RXD3 — Receiver input for UART3.

I/O

SCL1 — I²C1 clock input/output (this pin is not fully compliant with the

I²C-bus specification, see Section 19–4 for details).

P0[2] / TXD0 /

AD0[7]

98

99

81

79

80

-

I/O

P0[2] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

O

I

TXD0 — Transmitter output for UART0.

AD0[7] — A/D converter 0, input 7.

P0[3] / RXD0 /

AD0[6]

I/O

P0[3] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I

RXD0 — Receiver input for UART0.

I

AD0[6] — A/D converter 0, input 6.

P0[4] /

I/O

P0[4] — General purpose digital input/output pin.

I2SRX_CLK /

RD2 / CAP2[0]

I2SRX_CLK — Receive Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S bus specification.

I

RD2 — CAN2 receiver input.

I

CAP2[0] — Capture input for Timer 2, channel 0.

P0[5] — General purpose digital input/output pin.

P0[5] / I2SRX_WS / 80

TD2 / CAP2[1]

-

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S bus

specification.

O

TD2 — CAN2 transmitter output.

I

CAP2[1] — Capture input for Timer 2, channel 1.

P0[6] — General purpose digital input/output pin.

P0[6] /

79

78

64

63

I/O

I2SRX_SDA /

SSEL1 / MAT2[0]

I2SRX_SDA — Receive data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S bus specification.

I/O

O

SSEL1 — Slave Select for SSP1.

MAT2[0] — Match output for Timer 2, channel 0.

P0[7] — General purpose digital input/output pin.

P0[7] /

I/O

I2STX_CLK /

SCK1 / MAT2[1]

I2STX_CLK — Transmit Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S bus specification.

I/O

O

SCK1 — Serial Clock for SSP1.

MAT2[1] — Match output for Timer 2, channel 1.

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Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P0[8] / I2STX_WS / 77

MISO1 / MAT2[2]

62

I/O

P0[8] — General purpose digital input/output pin.

I2STX_WS — Transmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S bus

specification.

I/O

O

MISO1 — Master In Slave Out for SSP1.

MAT2[2] — Match output for Timer 2, channel 2.

P0[9] — General purpose digital input/output pin.

P0[9] /

76

61

I/O

I2STX_SDA /

MOSI1 / MAT2[3]

I2STX_SDA — Transmit data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S bus specification.

I/O

O

MOSI1 — Master Out Slave In for SSP1.

MAT2[3] — Match output for Timer 2, channel 3.

P0[10] — General purpose digital input/output pin.

TXD2 — Transmitter output for UART2.

P0[10] / TXD2 /

SDA2 / MAT3[0]

48

49

62

63

61

60

59

39

40

47

48

46

45

-

I/O

O

I/O

O

SDA2 — I²C2 data input/output (this is not an open-drain pin).

MAT3[0] — Match output for Timer 3, channel 0.

P0[11] — General purpose digital input/output pin.

RXD2 — Receiver input for UART2.

P0[11] / RXD2 /

SCL2 / MAT3[1]

I/O

I

I/O

O

SCL2 — I²C2 clock input/output (this is not an open-drain pin).

MAT3[1] — Match output for Timer 3, channel 1.

P0[15] — General purpose digital input/output pin.

TXD1 — Transmitter output for UART1.

P0[15] / TXD1 /

SCK0 / SCK

I/O

O

I/O

I

SCK0 — Serial clock for SSP0.

SCK — Serial clock for SPI.

P0[16] / RXD1 /

SSEL0 / SSEL

P0[16] — General purpose digital input/output pin.

RXD1 — Receiver input for UART1.

I/O

I

SSEL0 — Slave Select for SSP0.

SSEL — Slave Select for SPI.

P0[17] / CTS1 /

MISO0 / MISO

P0[17] — General purpose digital input/output pin.

CTS1 — Clear to Send input for UART1.

MISO0 — Master In Slave Out for SSP0.

MISO — Master In Slave Out for SPI.

I/O

I

P0[18] / DCD1 /

MOSI0 / MOSI

P0[18] — General purpose digital input/output pin.

DCD1 — Data Carrier Detect input for UART1.

MOSI0 — Master Out Slave In for SSP0.

MOSI — Master Out Slave In for SPI.

I/O

I

P0[19] / DSR1 /

SDA1

P0[19] — General purpose digital input/output pin.

DSR1 — Data Set Ready input for UART1.

I/O

SDA1 — I²C1 data input/output (this pin is not fully compliant with the

I²C-bus specification, see Section 19–4 for details).

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Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P0[20] / DTR1 /

SCL1

58

-

I/O

O

P0[20] — General purpose digital input/output pin.

DTR1 — Data Terminal Ready output for UART1. Can also be configured

to be an RS-485/EIA-485 output enable signal.

I/O

SCL1 — I²C1 clock input/output (this pin is not fully compliant with the

I²C-bus specification, see Section 19–4 for details).

P0[21] / RI1 / RD1

57

-

I/O

I

P0[21] — General purpose digital input/output pin.

RI1 — Ring Indicator input for UART1.

RD1 — CAN1 receiver input.

I

P0[22] / RTS1 / TD1 56

44

I/O

O

P0[22] — General purpose digital input/output pin.

RTS1 — Request to Send output for UART1. Can also be configured to be

an RS-485/EIA-485 output enable signal.

O

TD1 — CAN1 transmitter output.

P0[23] / AD0[0] /

I2SRX_CLK /

CAP3[0]

9

8

-

I/O

P0[23] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I

AD0[0] — A/D converter 0, input 0.

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S bus specification.

I

CAP3[0] — Capture input for Timer 3, channel 0.

P0[24] / AD0[1] /

I2SRX_WS /

CAP3[1]

I/O

P0[24] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I

AD0[1] — A/D converter 0, input 1.

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S bus

specification.

I

CAP3[1] — Capture input for Timer 3, channel 1.

P0[25] / AD0[2] /

I2SRX_SDA /

TXD3

7

I/O

P0[25] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I

AD0[2] — A/D converter 0, input 2.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S bus specification.

O

TXD3 — Transmitter output for UART3.

P0[26] / AD0[3] /

AOUT / RXD3

6

I/O

P0[26] — General purpose digital input/output pin. When configured as an

ADC input or DAC output, the digital section of the pad is disabled.

I

AD0[3] — A/D converter 0, input 3.

AOUT — D/A converter output.

RXD3 — Receiver input for UART3.

O

I

P0[27] / SDA0 /

USB_SDA

25

-

I/O

P0[27] — General purpose digital input/output pin. Open-drain 5 V tolerant

digital I/O pad, compatible with I²C-bus specifications for 100 kHz standard

mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires

an external pull-up to provide output functionality. When power is switched

off, this pin connected to the I²C-bus is floating and does not disturb the

I²C lines. Open-drain configuration applies to all functions on this pin.

I/O

SDA0 — I²C0 data input/output. Open-drain output (for I²C-bus

compliance).

USB_SDA — USB port I²C serial data (OTG transceiver).

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Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P0[28] / SCL0 /

USB_SCL

24

-

I/O

P0[28] — General purpose digital input/output pin. Open-drain 5 V tolerant

digital I/O pad, compatible with I²C-bus specifications for 100 kHz standard

mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires

an external pull-up to provide output functionality. When power is switched

off, this pin connected to the I²C-bus is floating and does not disturb the

I²C lines. Open-drain configuration applies to all functions on this pin.

I/O

SCL0 — I²C0 clock input/output. Open-drain output (for I²C-bus

compliance).

I/O

USB_SCL — USB port I²C serial clock (OTG transceiver).

P0[29] / USB_D+

P0[30] / USB_D−

P1[0] to P1[31]

29

30

22

23

P0[29] — General purpose digital input/output pin. Pad provides digital I/O

and USB functions. It is designed in accordance with the USB

specification, revision 2.0 (Full-speed and Low-speed mode only).

I/O

USB_D+ — USB bidirectional D+ line.

P0[30] — General purpose digital input/output pin. Pad provides digital I/O

and USB functions. It is designed in accordance with the USB

specification, revision 2.0 (Full-speed and Low-speed mode only).

I/O

USB_D− — USB bidirectional D− line.

Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each

bit. The operation of port 1 pins depends upon the pin function selected via

the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not

available.

P1[0] /

ENET_TXD0

95

94

93

92

91

90

89

88

87

86

76

75

74

73

72

71

70

69

-

I/O

O

P1[0] — General purpose digital input/output pin.

ENET_TXD0 — Ethernet transmit data 0.

P1[1] /

ENET_TXD1

I/O

O

P1[1] — General purpose digital input/output pin.

ENET_TXD1 — Ethernet transmit data 1.

P1[4] /

ENET_TX_EN

I/O

O

P1[4] — General purpose digital input/output pin.

ENET_TX_EN — Ethernet transmit data enable.

P1[8] — General purpose digital input/output pin.

ENET_CRS — Ethernet carrier sense.

P1[8] /

ENET_CRS

I/O

I

P1[9] /

ENET_RXD0

I/O

I

P1[9] — General purpose digital input/output pin.

ENET_RXD0 — Ethernet receive data.

P1[10] /

ENET_RXD1

I/O

I

P1[10] — General purpose digital input/output pin.

ENET_RXD1 — Ethernet receive data.

P1[14] /

ENET_RX_ER

I/O

I

P1[14] — General purpose digital input/output pin.

ENET_RX_ER — Ethernet receive error.

P1[15] /

ENET_REF_CLK

I/O

I

P1[15] — General purpose digital input/output pin.

ENET_REF_CLK — Ethernet reference clock.

P1[16] — General purpose digital input/output pin.

ENET_MDC — Ethernet MIIM clock.

P1[16] /

ENET_MDC

I/O

O

P1[17] /

ENET_MDIO

-

I/O

P1[17] — General purpose digital input/output pin.

ENET_MDIO — Ethernet MIIM data input and output.

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Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P1[18] /

USB_UP_LED /

PWM1[1] / CAP1[0]

32

25

I/O

O

P1[18] — General purpose digital input/output pin.

USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled). It is HIGH when the device is

not configured or during global suspend.

O

I

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

CAP1[0] — Capture input for Timer 1, channel 0.

P1[19] — General purpose digital input/output pin.

MCOA0 — Motor control PWM channel 0, output A.

USB_PPWR — Port Power enable signal for USB port.

CAP1[1] — Capture input for Timer 1, channel 1.

P1[20] — General purpose digital input/output pin.

P1[19] / MCOA0 /

USB_PPWR /

CAP1[1]

33

34

26

27

I/O

O

I

P1[20] / MCI0 /

I/O

I

PWM1[2] / SCK0

MCI0 — Motor control PWM channel 0 input. Also Quadrature Encoder

Interface PHA input.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

SCK0 — Serial clock for SSP0.

I/O

O

P1[21] /

35

36

37

-

P1[21] — General purpose digital input/output pin.

MCABORT — Motor control PWM, active low fast abort.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

SSEL0 — Slave Select for SSP0.

MCABORT /

PWM1[3] / SSEL0

O

I/O

O

P1[22] / MCOB0 /

USB_PWRD /

MAT1[0]

28

29

P1[22] — General purpose digital input/output pin.

MCOB0 — Motor control PWM channel 0, output B.

USB_PWRD — Power Status for USB port (host power switch).

MAT1[0] — Match output for Timer 1, channel 0.

P1[23] — General purpose digital input/output pin.

I

O

P1[23] / MCI1 /

I/O

I

PWM1[4] / MISO0

MCI1 — Motor control PWM channel 1 input. Also Quadrature Encoder

Interface PHB input.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

MISO0 — Master In Slave Out for SSP0.

I/O

I

P1[24] / MCI2 /

38

30

P1[24] — General purpose digital input/output pin.

PWM1[5] / MOSI0

MCI2 — Motor control PWM channel 2 input. Also Quadrature Encoder

Interface INDEX input.

O

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

MOSI0 — Master Out Slave in for SSP0.

I/O

O

P1[25] / MCOA1 /

MAT1[1]

39

40

31

32

P1[25] — General purpose digital input/output pin.

MCOA1 — Motor control PWM channel 1, output A.

MAT1[1] — Match output for Timer 1, channel 1.

P1[26] — General purpose digital input/output pin.

MCOB1 — Motor control PWM channel 1, output B.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

CAP0[0] — Capture input for Timer 0, channel 0.

O

P1[26] / MCOB1 /

I/O

O

PWM1[6] / CAP0[0]

O

I

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Chapter 7: LPC17xx Pin configuration

Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P1[27] / CLKOUT / 43

USB_OVRCR /

CAP0[1]

-

I/O

O

I

P1[27] — General purpose digital input/output pin.

CLKOUT — Clock output pin.

USB_OVRCR — USB port Over-Current status.

CAP0[1] — Capture input for Timer 0, channel 1.

P1[28] — General purpose digital input/output pin.

MCOA2 — Motor control PWM channel 2, output A.

PCAP1[0] — Capture input for PWM1, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

P1[29] — General purpose digital input/output pin.

MCOB2 — Motor control PWM channel 2, output B.

PCAP1[1] — Capture input for PWM1, channel 1.

MAT0[1] — Match output for Timer 0, channel 0.

I

P1[28] / MCOA2 /

44

45

21

35

36

18

I/O

O

I

PCAP1[0] / MAT0[0]

O

I/O

O

I

P1[29] / MCOB2 /

PCAP1[1] /

MAT0[1]

O

I/O

P1[30] / V_BUS

AD0[4]

/

P1[30] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I

V_BUS— Monitors the presence of USB bus power.

Note: This signal must be HIGH for USB reset to occur.

AD0[4] — A/D converter 0, input 4.

I

P1[31] / SCK1 /

AD0[5]

20

17

I/O

P1[31] — General purpose digital input/output pin. When configured as an

ADC input, digital section of the pad is disabled.

I/O

I

SCK1 — Serial Clock for SSP1.

AD0[5] — A/D converter 0, input 5.

P2[0] to P2[31]

I/O

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each

bit. The operation of port 2 pins depends upon the pin function selected via

the pin connect block. Pins 14 through 31 of this port are not available.

P2[0] / PWM1[1] /

TXD1

75

74

73

60

59

58

I/O

O

I/O

O

I

P2[0] — General purpose digital input/output pin.

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

TXD1 — Transmitter output for UART1.

P2[1] / PWM1[2] /

RXD1

P2[1] — General purpose digital input/output pin.

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

RXD1 — Receiver input for UART1.

P2[2] / PWM1[3] /

CTS1 /

TRACEDATA[3]

I/O

O

I

P2[2] — General purpose digital input/output pin.

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

CTS1 — Clear to Send input for UART1.

O

I/O

O

I

TRACEDATA[3] — Trace data, bit 3.

P2[3] / PWM1[4] /

DCD1 /

TRACEDATA[2]

70

55

P2[3] — General purpose digital input/output pin.

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

DCD1 — Data Carrier Detect input for UART1.

TRACEDATA[2] — Trace data, bit 2.

O

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Chapter 7: LPC17xx Pin configuration

Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P2[4] / PWM1[5] /

DSR1 /

TRACEDATA[1]

69

54

I/O

O

P2[4] — General purpose digital input/output pin.

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I

DSR1 — Data Set Ready input for UART1.

TRACEDATA[1] — Trace data, bit 1.

O

P2[5] / PWM1[6] /

DTR1 /

TRACEDATA[0]

68

53

I/O

O

P2[5] — General purpose digital input/output pin.

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O

DTR1 — Data Terminal Ready output for UART1. Can also be configured

to be an RS-485/EIA-485 output enable signal.

O

I/O

I

TRACEDATA[0] — Trace data, bit 0.

P2[6] — General purpose digital input/output pin.

PCAP1[0] — Capture input for PWM1, channel 0.

RI1 — Ring Indicator input for UART1.

TRACECLK — Trace Clock.

P2[6] / PCAP1[0] /

RI1 / TRACECLK

67

52

I

O

I/O

I

P2[7] / RD2 /

RTS1

66

65

51

50

P2[7] — General purpose digital input/output pin.

RD2 — CAN2 receiver input.

O

RTS1 — Request to Send output for UART1. Can also be configured to be

an RS-485/EIA-485 output enable signal.

P2[8] / TD2 /

TXD2 / ENET_MDC

I/O

O

P2[8] — General purpose digital input/output pin.

TD2 — CAN2 transmitter output.

O

TXD2 — Transmitter output for UART2.

ENET_MDC — Ethernet MIIM clock.

O

P2[9] /

USB_CONNECT /

RXD2 /

64

53

49

41

I/O

O

P2[9] — General purpose digital input/output pin.

USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor

under software control. Used with the SoftConnect USB feature.

ENET_MDIO

I

RXD2 — Receiver input for UART2.

I/O

ENET_MDIO — Ethernet MIIM data input and output.

P2[10] / EINT0 /

NMI

P2[10] — General purpose digital input/output pin. 5 V tolerant pad with 5

ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

Note: A LOW on this pin while RESET is LOW forces the on-chip

bootloader to take over control of the part after a reset and go into ISP

mode. See Section 32–1.

I

EINT0 — External interrupt 0 input.

NMI — Non-maskable interrupt input.

I

P2[11] / EINT1 /

I2STX_CLK

52

-

I/O

P2[11] — General purpose digital input/output pin. 5 V tolerant pad with 5

ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

I

EINT1 — External interrupt 1 input.

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by

the slave. Corresponds to the signal SCK in the I²S bus specification.

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Table 72. Pin description …continued

Symbol

LQFP

100

LQFP

80

Type Description

P2[12] / EINT2 /

I2STX_WS

51

-

I/O

P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5

ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

I

EINT2 — External interrupt 2 input.

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I²S bus

specification.

P2[13] / EINT3 /

I2STX_SDA

50

-

I/O

P2[13] — General purpose digital input/output pin. 5 V tolerant pad with 5

ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

I

EINT3 — External interrupt 3 input.

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by

the receiver. Corresponds to the signal SD in the I²S bus specification.

P3[0] to P3[31]

I/O

Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each

bit. The operation of port 3 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 24, and 27 through 31 of this port are

not available.

P3[25] / MAT0[0] /

PWM1[2]

27

26

-

I/O

O

P3[25] — General purpose digital input/output pin.

MAT0[0] — Match output for Timer 0, channel 0.

PWM1[2] — Pulse Width Modulator 1, output 2.

P3[26] — General purpose digital input/output pin.

STCLK — System tick timer clock input.

O

P3[26] / STCLK /

MAT0[1] / PWM1[3]

I/O

I

O

MAT0[1] — Match output for Timer 0, channel 1.

PWM1[3] — Pulse Width Modulator 1, output 3.

O

P4[0] to P4[31]

P4[28] /

I/O

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each

bit. The operation of port 4 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 27, 30, and 31 of this port are not

available.

82

65

68

1

I/O

I

P4[28] — General purpose digital input/output pin.

RX_MCLK — I²S receive master clock.

MAT2[0] — Match output for Timer 2, channel 0.

TXD3 — Transmitter output for UART3.

P4[29] — General purpose digital input/output pin.

TX_MCLK — I²S transmit master clock.

MAT2[1] — Match output for Timer 2, channel 1.

RXD3 — Receiver input for UART3.

RX_MCLK /

MAT2[0] / TXD3

O

I/O

I

P4[29] TX_MCLK / 85

MAT2[1] / RXD3

O

I

TDO / SWO

1

O

I

TDO — Test Data out for JTAG interface.

SWO — Serial wire trace output.

TDI

2

3

2

3

TDI — Test Data in for JTAG interface.

TMS — Test Mode Select for JTAG interface.

SWDIO — Serial wire debug data input/output.

TRST — Test Reset for JTAG interface.

TCK — Test Clock for JTAG interface.

SWDCLK — Serial wire clock.

TMS / SWDIO

I

I/O

I

TRST

4

5

4

5

TCK / SWDCLK

I

RTCK

100

-

I/O

RTCK — JTAG interface control signal.

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Chapter 7: LPC17xx Pin configuration

Table 72. Pin description …continued

Symbol

RSTOUT

RESET

LQFP

100

LQFP

80

Type Description

14

11

O

I

RSTOUT — This is a 3.3 V pin. A LOW on this pin indicates that the

LPC17xx is in a Reset state.

17

14

External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0. This is a 5 V tolerant pad with a 20 ns

glitch filter, TTL levels and hysteresis.

XTAL1

XTAL2

RTCX1

RTCX2

V_SS

22^[1]

23^[1]

16^[1]

18^[1]

19^[1]

20^[1]

13^[1]

15^[1]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

O

I

Input to the RTC oscillator circuit.

O

I

Output from the RTC oscillator circuit.

ground: 0 V reference.

31, 41, 24, 33,

55, 72, 43, 57,

83, 97^[1]66, 78^[1]

V_SSA

11^[1]

9^[1]

I

analog ground: 0 V reference. This should be the same voltage as V_SS,

but should be isolated to minimize noise and error.

V_DD(3V3)

V_DD(REG)(3V3)

V_DDA

28, 54, 21, 42,

71, 96^[1]56, 77^[1]

42, 84^[1]34, 67^[1]

3.3 V supply voltage: This is the power supply voltage for I/O other than

pins in the Vbat domain.

3.3 V voltage regulator supply voltage: This is the supply voltage for the

on-chip voltage regulator only.

10^[1]

12^[1]

15^[1]

8^[1]

analog 3.3 V pad supply voltage: This can be connected to the same

supply as V_DD(3V3)but should be isolated to minimize noise and error. This

voltage is used to power the ADC and DAC. Note: this pin should be tied

to 3.3v if the ADC and DAC are not used.

V_REFP

10^[1]

I

ADC positive reference voltage: This should be nominally the same

voltage as V_DDAbut should be isolated to minimize noise and error. The

voltage level on this pin is used as a reference for ADC and DAC. Note:

this pin should be tied to 3.3v if the ADC and DAC are not used.

V_REFN

12^[1]

ADC negative reference voltage: This should be the same voltage as

V_SSbut should be isolated to minimize noise and error. Level on this pin is

used as a reference for ADC and DAC.

V_BAT

n.c.

19^[1]

13

16^[1]

-

I

RTC domain power supply: 3.3 V on this pin supplies the power to the

RTC peripheral.

-

not connected

[1] Pad provides special analog functionality.

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1. How to read this chapter

Table 8–73 shows the functions of the PINSEL registers in the LPC17xx.

Table 73. Summary of PINSEL registers

Register

PINSEL0

PINSEL1

PINSEL2

PINSEL3

PINSEL4

PINSEL5

PINSEL6

PINSEL7

PINSEL8

PINSEL9

Controls

Table

P0[15:0]

Table 8–78

Table 8–79

Table 8–80

Table 8–81

Table 8–82

not used

P0 [31:16]

P1 [15:0] (Ethernet)

P1 [31:16]

P2 [15:0]

P2 [31:16]

P3 [15:0]

not used

P3 [31:16]

P4 [15:0]

Table 8–83

not used

P4 [31:16]

Table 8–84

Table 8–85

PINSEL10 Trace port enable

2. Description

The pin connect block allows most pins of the microcontroller to have more than one

potential function. Configuration registers control the multiplexers to allow connection

between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Selection of a single function on a port pin excludes other peripheral functions available

on the same pin. However, the GPIO input stays connected and may be read by software

or used to contribute to the GPIO interrupt feature.

3. Pin function select register values

The PINSEL registers control the functions of device pins as shown below. Pairs of bits in

these registers correspond to specific device pins.

Table 74. Pin function select register bits

PINSEL0 to

Function

Value after Reset

PINSEL9 Values

00

01

10

11

Primary (default) function, typically GPIO port

First alternate function

00

Second alternate function

Third alternate function

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The direction control bit in the GPIO registers is effective only when the GPIO function is

selected for a pin. For other functions, direction is controlled automatically. Each

derivative typically has a different pinout and therefore a different set of functions possible

for each pin. Details for a specific derivative may be found in the appropriate data sheet.

Multiple connections

Since a particular peripheral function may be allowed on more than one pin, it is in

principle possible to configure more than one pin to perform the same function. If a

peripheral output function is configured to appear on more than one pin, it will in fact be

routed to those pins. If a peripheral input function is configured to appear on more than

one pin for some reason, the peripheral will receive its input from the lowest port number.

For instance, any pin of port 0 will take precedence over any pin of a higher numbered

port, and pin 0 of any port will take precedence over a higher numbered pin of the same

port.

4. Pin mode select register values

The PINMODE registers control the input mode of all ports. This includes the use of the

on-chip pull-up/pull-down resistor feature and a special open drain operating mode. The

on-chip pull-up/pull-down resistor can be selected for every port pin regardless of the

function on this pin with the exception of the I²C pins for the I2C0 interface and the USB

pins (see Section 8–5.10). Three bits are used to control the mode of a port pin, two in a

PINMODE register, and an additional one in a PINMODE_OD register. Bits are reserved

for unused pins as in the PINSEL registers.

Table 75. Pin Mode Select register Bits

PINMODE0 to

PINMODE9 Values

Function

Value after

Reset

00

01

10

11

Pin has an on-chip pull-up resistor enabled.

Repeater mode (see text below).

00

Pin has neither pull-up nor pull-down resistor enabled.

Pin has an on-chip pull-down resistor enabled.

Repeater mode enables the pull-up resistor if the pin is at a logic high and enables the

pull-down resistor if the pin is at a logic low. This causes the pin to retain its last known

state if it is configured as an input and is not driven externally. The state retention is not

applicable to the Deep Power-down mode. Repeater mode may typically be used to

prevent a pin from floating (and potentially using significant power if it floats to an

indeterminate state) if it is temporarily not driven.

The PINMODE_OD registers control the open drain mode for ports. The open drain mode

causes the pin to be pulled low normally if it is configured as an output and the data value

is 0. If the data value is 1, the output drive of the pin is turned off, equivalent to changing

the pin direction. This combination simulates an open drain output.

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Table 76. Open Drain Pin Mode Select register Bits

PINMODE_OD0 to Function

PINMODE_OD4

Values

Value after

Reset

0

1

Pin is in the normal (not open drain) mode.

Pin is in the open drain mode.

00

Function of PINMODE in open drain mode

Normally the value of PINMODE applies to a pin only when it is in the input mode. When a

pin is in the open drain mode, caused by a 1 in the corresponding bit of one of the

PINMODE_OD registers, the input mode still does not apply when the pin is outputting a

0. However, when the pin value is 1, PINMODE applies since this state turns off the pin’s

output driver. For example, this allows for the possibility of configuring a pin to be open

drain with an on-chip pullup. A pullup in this case which is only on when the pin is not

being pulled low by the pin’s own output.

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5. Register description

The Pin Control Module contains 11 registers as shown in Table 8–77 below.

Table 77. Pin Connect Block Register Map

Name

Description

Access Reset

Value^[1]

Address

PINSEL0

Pin function select register 0.

Pin function select register 1.

Pin function select register 2.

Pin function select register 3.

Pin function select register 4

Pin function select register 7

Pin function select register 8

Pin function select register 9

Pin function select register 10

Pin mode select register 0

R/W

0

0x4002 C000

0x4002 C004

0x4002 C008

0x4002 C00C

0x4002 C010

0x4002 C01C

0x4002 C020

0x4002 C024

0x4002 C028

0x4002 C040

0x4002 C044

0x4002 C048

0x4002 C04C

0x4002 C050

0x4002 C054

0x4002 C058

0x4002 C05C

0x4002 C064

0x4002 C068

0x4002 C06C

0x4002 C070

0x4002 C074

0x4002 C078

0x4002 C07C

PINSEL1

PINSEL2

PINSEL3

PINSEL4

PINSEL7

PINSEL8

PINSEL9

PINSEL10

PINMODE0

PINMODE1

PINMODE2

PINMODE3

PINMODE4

PINMODE5

PINMODE6

PINMODE7

PINMODE9

PINMODE_OD0

PINMODE_OD1

PINMODE_OD2

PINMODE_OD3

PINMODE_OD4

I2CPADCFG

Pin mode select register 1

Pin mode select register 2

Pin mode select register 3.

Pin mode select register 4

Pin mode select register 5

Pin mode select register 6

Pin mode select register 7

Pin mode select register 9

Open drain mode control register 0

Open drain mode control register 1

Open drain mode control register 2

Open drain mode control register 3

Open drain mode control register 4

2

I C Pin Configuration register

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

Pin control module register reset values

On external reset, watchdog reset, power-on-reset (POR), and BOD reset, all registers in

this module are reset to '0'.

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5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000)

The PINSEL0 register controls the functions of the lower half of Port 0. The direction

control bit in FIO0DIR register is effective only when the GPIO function is selected for a

pin. For other functions, the direction is controlled automatically.

Table 78. Pin function select register 0 (PINSEL0 - address 0x4002 C000) bit description

PINSEL0 Pin

Function when Function when 01 Function

Function

when 11

Reset

value

name 00

when 10

1:0

P0.0

P0.1

P0.2

P0.3

GPIO Port 0.0

GPIO Port 0.1

GPIO Port 0.2

GPIO Port 0.3

RD1

TXD3

SDA1

00

0

3:2

TD1

RXD3

AD0.7

AD0.6

RD2

SCL1

5:4

TXD0

Reserved

CAP2.0

CAP2.1

MAT2.0

MAT2.1

MAT2.2

MAT2.3

MAT3.0

MAT3.1

Reserved

SCK

7:6

RXD0

9:8

P0.4^[1]GPIO Port 0.4

P0.5^[1]GPIO Port 0.5

I2SRX_CLK

I2SRX_WS

I2SRX_SDA

I2STX_CLK

I2STX_WS

I2STX_SDA

11:10

13:12

15:14

17:16

19:18

21:20

23:22

29:24

31:30

TD2

P0.6

P0.7

P0.8

P0.9

GPIO Port 0.6

GPIO Port 0.7

GPIO Port 0.8

GPIO Port 0.9

SSEL1

SCK1

MISO1

MOSI1

SDA2

SCL2

P0.10 GPIO Port 0.10 TXD2

P0.11

-

GPIO Port 0.11 RXD2

Reserved Reserved

Reserved

SCK0

P0.15 GPIO Port 0.15 TXD1

00

[1] Not available on 80-pin package.

5.2 Pin Function Select Register 1 (PINSEL1 - 0x4002 C004)

The PINSEL1 register controls the functions of the upper half of Port 0. The direction

control bit in the FIO0DIR register is effective only when the GPIO function is selected for

a pin. For other functions the direction is controlled automatically.

Table 79. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description

PINSEL1 Pin name Function when Function

00 when 01

Function

when 10

Function

when 11

Reset

value

1:0

P0.16

GPIO Port 0.16 RXD1

GPIO Port 0.17 CTS1

GPIO Port 0.18 DCD1

GPIO Port 0.19 DSR1

GPIO Port 0.20 DTR1

GPIO Port 0.21 RI1

SSEL0

SSEL

MISO

MOSI

SDA1

SCL1

RD1

00

3:2

P0.17

MISO0

5:4

P0.18

MOSI0

7:6

P0.19^[1]

P0.20^[1]

P0.21^[1]

P0.22

Reserved

I2SRX_CLK

I2SRX_WS

9:8

11:10

13:12

15:14

17:16

19:18

21:20

23:22

25:24

GPIO Port 0.22 RTS1

GPIO Port 0.23 AD0.0

GPIO Port 0.24 AD0.1

GPIO Port 0.25 AD0.2

GPIO Port 0.26 AD0.3

TD1

P0.23^[1]

P0.24^[1]

P0.25

CAP3.0

CAP3.1

I2SRX_SDA TXD3

P0.26

AOUT

RXD3

P0.27^[1][2]GPIO Port 0.27 SDA0

P0.28^[1][2]GPIO Port 0.28 SCL0

USB_SDA

USB_SCL

Reserved

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Table 79. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description

PINSEL1 Pin name Function when Function

00 when 01

Function

when 10

Function

when 11

Reset

value

27:26

29:28

31:30

P0.29

P0.30

-

GPIO Port 0.29 USB_D+

GPIO Port 0.30 USB_D−

Reserved

00

Reserved

[1] Not available on 80-pin package.

[2] Pins P027] and P0[28] are open-drain for I²C-bus compliance.

5.3 Pin Function Select register 2 (PINSEL2 - 0x4002 C008)

The PINSEL2 register controls the functions of the lower half of Port 1, which contains the

Ethernet related pins. The direction control bit in the FIO1DIR register is effective only

when the GPIO function is selected for a pin. For other functions, the direction is

controlled automatically.

Table 80. Pin function select register 2 (PINSEL2 - address 0x4002 C008) bit description

PINSEL2 Pin

name

Function when Function when Function

Function

when 11

Reset

value

00

01

when 10

Reserved

1:0

P1.0

GPIO Port 1.0

GPIO Port 1.1

Reserved

ENET_TXD0

ENET_TXD1

Reserved

00

0

3:2

P1.1

-

7:4

9:8

P1.4

-

GPIO Port 1.4

Reserved

ENET_TX_EN

Reserved

00

0

15:10

17:16

19:18

21:20

27:22

29:28

31:30

P1.8

P1.9

P1.10

-

GPIO Port 1.8

GPIO Port 1.9

ENET_CRS

ENET_RXD0

00

0

GPIO Port 1.10 ENET_RXD1

Reserved Reserved

GPIO Port 1.14 ENET_RX_ER

P1.14

P1.15

00

GPIO Port 1.15 ENET_REF_CLK Reserved

5.4 Pin Function Select Register 3 (PINSEL3 - 0x4002 C00C)

The PINSEL3 register controls the functions of the upper half of Port 1. The direction

control bit in the FIO1DIR register is effective only when the GPIO function is selected for

a pin. For other functions, direction is controlled automatically.

Table 81. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description

PINSEL3 Pin

name

Function when Function when

00 01

Function

when 10

Function

when 11

Reset

value

1:0

P1.16^[1]GPIO Port 1.16 ENET_MDC

P1.17^[1]GPIO Port 1.17 ENET_MDIO

Reserved

PWM1.1

Reserved

CAP1.0

00

3:2

5:4

P1.18

P1.19

P1.20

GPIO Port 1.18 USB_UP_LED

GPIO Port 1.19 MCOA0

GPIO Port 1.20 MCI0

7:6

USB_PPWR CAP1.1

9:8

PWM1.2

PWM1.3

SCK0

11:10

13:12

P1.21^[1]GPIO Port 1.21 MCABORT

SSEL0

P1.22

GPIO Port 1.22 MCOB0

USB_PWRD MAT1.0

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Table 81. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description

PINSEL3 Pin

name

Function when Function when

00 01

Function

when 10

Function

when 11

Reset

value

15:14

17:16

19:18

21:20

23:22

25:24

27:26

29:28

31:30

P1.23

P1.24

P1.25

P1.26

GPIO Port 1.23 MCI1

GPIO Port 1.24 MCI2

GPIO Port 1.25 MCOA1

GPIO Port 1.26 MCOB1

PWM1.4

PWM1.5

Reserved

PWM1.6

MISO0

MOSI0

MAT1.1

CAP0.0

00

P1.27^[1]GPIO Port 1.27 CLKOUT

USB_OVRCR CAP0.1

P1.28

P1.29

P1.30

P1.31

GPIO Port 1.28 MCOA2

GPIO Port 1.29 MCOB2

GPIO Port 1.30 Reserved

GPIO Port 1.31 Reserved

PCAP1.0

PCAP1.1

V_BUS

MAT0.0

MAT0.1

AD0.4

SCK1

AD0.5

[1] Not available on 80-pin package.

5.5 Pin Function Select Register 4 (PINSEL4 - 0x4002 C010)

The PINSEL4 register controls the functions of the lower half of Port 2. The direction

control bit in the FIO2DIR register is effective only when the GPIO function is selected for

a pin. For other functions, direction is controlled automatically.

Table 82. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description

PINSEL4 Pin

name

Function when Function when 01 Function

Functionwhen Reset

00

when 10

11

value

00

0

1:0

P2.0

GPIO Port 2.0

GPIO Port 2.1

GPIO Port 2.2

GPIO Port 2.3

GPIO Port 2.4

GPIO Port 2.5

GPIO Port 2.6

GPIO Port 2.7

GPIO Port 2.8

GPIO Port 2.9

PWM1.1

PWM1.2

PWM1.3

PWM1.4

PWM1.5

PWM1.6

PCAP1.0

RD2

TXD1

Reserved

3:2

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

RXD1

Reserved

5:4

CTS1

Reserved ^[2]

Reserved

7:6

DCD1

9:8

DSR1

11:10

13:12

15:14

17:16

19:18

21:20

23:22

25:24

27:26

31:28

DTR1

RI1

RTS1

TD2

TXD2

ENET_MDC

ENET_MDIO

Reserved

USB_CONNECT

RXD2

GPIO Port 2.10 EINT0

NMI

P2.11^[1]GPIO Port 2.11 EINT1

P2.12^[1]GPIO Port 2.12 EINT2

P2.13^[1]GPIO Port 2.13 EINT3

Reserved

I2STX_CLK

I2STX_WS

I2STX_SDA

Reserved

-

Reserved

[1] Not available on 80-pin package.

[2] These pins support a debug trace function when selected via a development tool or by writing to the

PINSEL10 register. See Section 8–5.8 “Pin Function Select Register 10 (PINSEL10 - 0x4002 C028)” for

details.

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5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C)

The PINSEL7 register controls the functions of the upper half of Port 3. The direction

control bit in the FIO3DIR register is effective only when the GPIO function is selected for

a pin. For other functions, direction is controlled automatically.

Table 83. Pin function select register 7 (PINSEL7 - address 0x4002 C01C) bit description

PINSEL7 Pin

name

Function when Function

Function

when 10

Function

when 11

Reset

value

00

when 01

17:0

-

Reserved

MAT0.0

Reserved

PWM1.2

PWM1.3

Reserved

0

19:18

21:20

31:22

P3.25^[1]GPIO Port 3.25 Reserved

P3.26^[1]GPIO Port 3.26 STCLK

00

0

MAT0.1

-

Reserved

[1] Not available on 80-pin package.

5.7 Pin Function Select Register 9 (PINSEL9 - 0x4002 C024)

The PINSEL9 register controls the functions of the upper half of Port 4. The direction

control bit in the FIO4DIR register is effective only when the GPIO function is selected for

a pin. For other functions, direction is controlled automatically.

Table 84. Pin function select register 9 (PINSEL9 - address 0x4002 C024) bit description

PINSEL9 Pin

name

Function when Function

Function

when 10

Function

when 11

Reset

value

00

when 01

23:0

-

Reserved

MAT2.0

Reserved

TXD3

00

25:24

27:26

31:28

P4.28

P4.29

-

GPIO Port 4.28 RX_MCLK

GPIO Port 4.29 TX_MCLK

MAT2.1

RXD3

Reserved

5.8 Pin Function Select Register 10 (PINSEL10 - 0x4002 C028)

Only bit 3 of this register is used to control the Trace function on pins P2.2 through P2.6.

Table 85. Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description

Bit

Symbol

Value Description

Reset

value

2:0

3

-

Reserved. Software should not write 1 to these bits. NA

GPIO/TRACE

TPIU interface pins control.

TPIU interface is disabled.

0

1

TPIU interface is enabled. TPIU signals are

available on the pins hosting them regardless of the

PINSEL4 content.

31:4

-

Reserved. Software should not write 1 to these bits. NA

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5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040)

This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15.

Table 86. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description

PINMODE0 Symbol

Value Description

Reset

value

1:0

P0.00MODE

Port 0 pin 0 on-chip pull-up/down resistor control.

00

01

10

11

P0.0 pin has a pull-up resistor enabled.

P0.0 pin has repeater mode enabled.

P0.0 pin has neither pull-up nor pull-down.

P0.0 has a pull-down resistor enabled.

Port 0 pin 1 control, see P0.00MODE.

Port 0 pin 2 control, see P0.00MODE.

Port 0 pin 3 control, see P0.00MODE.

Port 0 pin 4 control, see P0.00MODE.

Port 0 pin 5 control, see P0.00MODE.

Port 0 pin 6 control, see P0.00MODE.

Port 0 pin 7 control, see P0.00MODE.

Port 0 pin 8 control, see P0.00MODE.

Port 0 pin 9control, see P0.00MODE.

Port 0 pin 10 control, see P0.00MODE.

Port 0 pin 11 control, see P0.00MODE.

Reserved.

3:2

P0.01MODE

P0.02MODE

P0.03MODE

P0.04MODE^[1]

P0.05MODE^[1]

P0.06MODE

P0.07MODE

P0.08MODE

P0.09MODE

P0.10MODE

P0.11MODE

-

00

NA

00

5:4

7:6

9:8

11:10

13:12

15:14

17:16

19:18

21:20

23:22

29:24

31:30

P0.15MODE

Port 0 pin 15 control, see P0.00MODE.

[1] Not available on 80-pin package.

5.10 Pin Mode select register 1 (PINMODE1 - 0x4002 C044)

This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 26. For

details see Section 8–4 “Pin mode select register values”.

Table 87. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description

PINMODE1 Symbol

Description

Reset

value

1:0

P0.16MODE

Port 1 pin 16 control, see P0.00MODE.

Port 1 pin 17 control, see P0.00MODE.

Port 1 pin 18 control, see P0.00MODE.

Port 1 pin 19 control, see P0.00MODE.

Port 1 pin 20control, see P0.00MODE.

Port 1 pin 21 control, see P0.00MODE.

Port 1 pin 22 control, see P0.00MODE.

Port 1 pin 23 control, see P0.00MODE.

Port 1 pin 24 control, see P0.00MODE.

Port 1 pin 25 control, see P0.00MODE.

00

3:2

P0.17MODE

P0.18MODE

P0.19MODE^[1]

P0.20MODE^[1]

P0.21MODE^[1]

P0.22MODE

P0.23MODE^[1]

P0.24MODE^[1]

P0.25MODE

5:4

7:6

9:8

11:10

13:12

15:14

17:16

19:18

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Table 87. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description

PINMODE1 Symbol

Description

Reset

value

21:20

29:22

31:30

P0.26MODE

Port 1 pin 26 control, see P0.00MODE.

Reserved. ^[2]

00

-

NA

Reserved.

[1] Not available on 80-pin package.

[2] The pin mode cannot be selected for pins P0[27] to P0[30]. Pins P0[27] and P0[28] are dedicated I2C

open-drain pins without pull-up/down. Pins P0[29] and P0[30] are USB specific pins without configurable

pull-up or pull-down resistors. Pins P0[29] and P0[30] also must have the same direction since they operate

as a unit for the USB function, see Section 9–5.1 “GPIO port Direction register FIOxDIR (FIO0DIR to

FIO4DIR- 0x2009 C000 to 0x2009 C080)”.

5.11 Pin Mode select register 2 (PINMODE2 - 0x4002 C048)

This register controls pull-up/pull-down resistor configuration for Port 1 pins 0 to 15. For

details see Section 8–4 “Pin mode select register values”.

Table 88. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description

PINMODE2 Symbol

Description

Reset

value

1:0

P1.00MODE

Port 1 pin 0 control, see P0.00MODE.

Port 1 pin 1 control, see P0.00MODE.

Reserved.

00

NA

00

NA

00

NA

00

3:2

P1.01MODE

-

7:4

9:8

P1.04MODE

-

Port 1 pin 4 control, see P0.00MODE.

Reserved.

15:10

17:16

19:18

21:20

27:22

29:28

31:30

P1.08MODE

P1.09MODE

P1.10MODE

-

Port 1 pin 8 control, see P0.00MODE.

Port 1 pin 9 control, see P0.00MODE.

Port 1 pin 10 control, see P0.00MODE.

Reserved.

P1.14MODE

P1.15MODE

Port 1 pin 14 control, see P0.00MODE.

Port 1 pin 15 control, see P0.00MODE.

5.12 Pin Mode select register 3 (PINMODE3 - 0x4002 C04C)

This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 31. For

details see Section 8–4 “Pin mode select register values”.

Table 89. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description

PINMODE3 Symbol

Description

Reset

value

1:0

P1.16MODE^[1]

Port 1 pin 16 control, see P0.00MODE.

Port 1 pin 17 control, see P0.00MODE.

Port 1 pin 18 control, see P0.00MODE.

Port 1 pin 19 control, see P0.00MODE.

Port 1 pin 20 control, see P0.00MODE.

Port 1 pin 21 control, see P0.00MODE.

Port 1 pin 22 control, see P0.00MODE.

00

3:2

P1.17MODE^[1]

P1.18MODE

P1.19MODE

P1.20MODE

P1.21MODE^[1]

P1.22MODE

5:4

7:6

9:8

11:10

13:12

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Table 89. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description

PINMODE3 Symbol

Description

Reset

value

15:14

17:16

19:18

21:20

23:22

25:24

27:26

29:28

31:30

P1.23MODE

Port 1 pin 23 control, see P0.00MODE.

Port 1 pin 24 control, see P0.00MODE.

Port 1 pin 25 control, see P0.00MODE.

Port 1 pin 26 control, see P0.00MODE.

Port 1 pin 27 control, see P0.00MODE.

Port 1 pin 28 control, see P0.00MODE.

Port 1 pin 29 control, see P0.00MODE.

Port 1 pin 30 control, see P0.00MODE.

Port 1 pin 31 control, see P0.00MODE.

00

P1.24MODE

P1.25MODE

P1.26MODE

P1.27MODE^[1]

P1.28MODE

P1.29MODE

P1.30MODE

P1.31MODE

[1] Not available on 80-pin package.

5.13 Pin Mode select register 4 (PINMODE4 - 0x4002 C050)

This register controls pull-up/pull-down resistor configuration for Port 2 pins 0 to 15. For

details see Section 8–4 “Pin mode select register values”.

Table 90. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description

PINMODE4 Symbol

Description

Reset

value

1:0

P2.00MODE

Port 2 pin 0 control, see P0.00MODE.

Port 2 pin 1 control, see P0.00MODE.

Port 2 pin 2 control, see P0.00MODE.

Port 2 pin 3 control, see P0.00MODE.

Port 2 pin 4 control, see P0.00MODE.

Port 2 pin 5 control, see P0.00MODE.

Port 2 pin 6 control, see P0.00MODE.

Port 2 pin 7 control, see P0.00MODE.

Port 2 pin 8 control, see P0.00MODE.

Port 2 pin 9 control, see P0.00MODE.

Port 2 pin 10 control, see P0.00MODE.

Port 2 pin 11 control, see P0.00MODE.

Port 2 pin 12 control, see P0.00MODE.

Port 2 pin 13 control, see P0.00MODE.

Reserved.

00

NA

3:2

P2.01MODE

P2.02MODE

P2.03MODE

P2.04MODE

P2.05MODE

P2.06MODE

P2.07MODE

P2.08MODE

P2.09MODE

P2.10MODE

P2.11MODE^[1]

P2.12MODE^[1]

P2.13MODE^[1]

-

5:4

7:6

9:8

11:10

13:12

15:14

17:16

19:18

21:20

23:22

25:24

27:26

31:28

[1] Not available on 80-pin package.

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5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C)

This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For

details see Section 8–4 “Pin mode select register values”.

Table 91. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description

PINMODE7 Symbol

Description

Reset

value

17:0

-

Reserved

NA

00

19:18

21:20

31:22

P3.25MODE^[1]

P3.26MODE^[1]

Port 3 pin 25 control, see P0.00MODE.

Port 3 pin 26 control, see P0.00MODE.

Reserved.

00

-

NA

[1] Not available on 80-pin package.

5.15 Pin Mode select register 9 (PINMODE9 - 0x4002 C064)

This register controls pull-up/pull-down resistor configuration for Port 4 pins 16 to 31. For

details see Section 8–4 “Pin mode select register values”.

Table 92. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description

PINMODE9 Symbol

Description

Reset

value

23:0

-

Reserved.

NA

00

25:24

27:26

31:28

P4.28MODE Port 4 pin 28 control, see P0.00MODE.

P4.29MODE Port 4 pin 29 control, see P0.00MODE.

00

-

Reserved.

NA

5.16 Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068)

This register controls the open drain mode for Port 0 pins. For details see Section 8–4 “Pin

mode select register values”.

Table 93. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit

description

PINMODE Symbol

_OD0

Value Description

Reset

value

0

P0.00OD^[3]

Port 0 pin 0 open drain mode control.

0

1

P0.0 pin is in the normal (not open drain) mode.

P0.0 pin is in the open drain mode.

1

2

3

4

5

6

7

8

9

P0.01OD^[3]

P0.02OD

P0.03OD

P0.04OD

P0.05OD

P0.06OD

P0.07OD

P0.08OD

P0.09OD

Port 0 pin 1 open drain mode control, see P0.00OD

Port 0 pin 2 open drain mode control, see P0.00OD

Port 0 pin 3 open drain mode control, see P0.00OD

Port 0 pin 4 open drain mode control, see P0.00OD

Port 0 pin 5 open drain mode control, see P0.00OD

Port 0 pin 6 open drain mode control, see P0.00OD

Port 0 pin 7 open drain mode control, see P0.00OD

Port 0 pin 8 open drain mode control, see P0.00OD

Port 0 pin 9 open drain mode control, see P0.00OD

0

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Table 93. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit

description

PINMODE Symbol

_OD0

Value Description

Reset

value

10

P0.10OD^[3]

Port 0 pin 10 open drain mode control, see P0.00OD

0

11

P0.11OD^[3]

Port 0 pin 11 open drain mode control, see P0.00OD

Reserved.

0

14:12

15

-

NA

0

P0.15OD

P0.16OD

P0.17OD

P0.18OD

P0.19OD^[3]

P0.20OD^[3]

P0.21OD

P0.22OD

P0.23OD

P0.24OD

P0.25OD

P0.26OD

Port 0 pin 15 open drain mode control, see P0.00OD

Port 0 pin 16 open drain mode control, see P0.00OD

Port 0 pin 17 open drain mode control, see P0.00OD

Port 0 pin 18 open drain mode control, see P0.00OD

Port 0 pin 19 open drain mode control, see P0.00OD

Port 0 pin 20open drain mode control, see P0.00OD

Port 0 pin 21 open drain mode control, see P0.00OD

Port 0 pin 22 open drain mode control, see P0.00OD

Port 0 pin 23 open drain mode control, see P0.00OD

Port 0 pin 24open drain mode control, see P0.00OD

Port 0 pin 25 open drain mode control, see P0.00OD

Port 0 pin 26 open drain mode control, see P0.00OD

Reserved.

16

0

17

0

18

0

19

0

20

0

21

0

22

0

23

0

24

0

25

0

26

0

[2]

28:27

29

-

NA

0

P0.29OD

P0.30OD

-

Port 0 pin 29 open drain mode control, see P0.00OD

Port 0 pin 30 open drain mode control, see P0.00OD

Reserved.

30

0

31

NA

[1] Not available on 80-pin package.

[2] Port 0 pins 27 and 28 should be set up using the I2CPADCFG register if they are used for an I²C-bus. Bits

27 and 28 of PINMODE_OD0 do not have any affect on these pins, they are special open drain I²C-bus

compatible pins.

[3] Port 0 bits 1:0, 11:10, and 20:19 may potentially be used for I²C-buses using standard port pins. If so, they

should be configured for open drain mode via the related bits in PINMODE_OD0.

5.17 Open Drain Pin Mode select register 1 (PINMODE_OD1 -

0x4002 C06C)

This register controls the open drain mode for Port 1 pins. For details see Section 8–4 “Pin

mode select register values”.

Table 94. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit

description

PINMODE Symbol

_OD1

Value Description

Reset

value

0

P1.00OD

Port 1 pin 0 open drain mode control.

0

1

P1.0 pin is in the normal (not open drain) mode.

P1.0 pin is in the open drain mode.

1

P1.01OD

-

Port 1 pin 1 open drain mode control, see P1.00OD

Reserved.

0

3:2

4

NA

0

P1.04OD

Port 1 pin 4 open drain mode control, see P1.00OD

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Table 94. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit

description

PINMODE Symbol

_OD1

Value Description

Reset

value

7:5

8

-

Reserved.

NA

0

P1.08OD

P1.09OD

P1.10OD

-

Port 1 pin 8 open drain mode control, see P1.00OD

9

Port 1 pin 9 open drain mode control, see P1.00OD

Port 1 pin 10 open drain mode control, see P1.00OD

Reserved.

0

10

13:11

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

NA

0

P1.14OD

P1.15OD

P1.16OD^[1]

P1.17OD^[1]

P1.18OD

P1.19OD

P1.20OD

P1.21OD^[1]

P1.22OD

P1.23OD

P1.24OD

P1.25OD

P1.26OD

P1.27OD^[1]

P1.28OD

P1.29OD

P1.30OD

P1.31OD

Port 1 pin 14 open drain mode control, see P1.00OD

Port 1 pin 15 open drain mode control, see P1.00OD

Port 1 pin 16 open drain mode control, see P1.00OD

Port 1 pin 17 open drain mode control, see P1.00OD

Port 1 pin 18 open drain mode control, see P1.00OD

Port 1 pin 19 open drain mode control, see P1.00OD

Port 1 pin 20open drain mode control, see P1.00OD

Port 1 pin 21 open drain mode control, see P1.00OD

Port 1 pin 22 open drain mode control, see P1.00OD

Port 1 pin 23 open drain mode control, see P1.00OD

Port 1 pin 24open drain mode control, see P1.00OD

Port 1 pin 25 open drain mode control, see P1.00OD

Port 1 pin 26 open drain mode control, see P1.00OD

Port 1 pin 27 open drain mode control, see P1.00OD

Port 1 pin 28 open drain mode control, see P1.00OD

Port 1 pin 29 open drain mode control, see P1.00OD

Port 1 pin 30 open drain mode control, see P1.00OD

Port 1 pin 31 open drain mode control.

0

[1] Not available on 80-pin package.

5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070)

This register controls the open drain mode for Port 2 pins. For details see Section 8–4 “Pin

mode select register values”.

Table 95. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit

description

PINMODE Symbol

_OD2

Value Description

Reset

value

0

P2.00OD

Port 2 pin 0 open drain mode control.

0

1

P2.0 pin is in the normal (not open drain) mode.

P2.0 pin is in the open drain mode.

1

2

3

4

P2.01OD

P2.02OD

P2.03OD

P2.04OD

Port 2 pin 1 open drain mode control, see P2.00OD

Port 2 pin 2 open drain mode control, see P2.00OD

Port 2 pin 3 open drain mode control, see P2.00OD

Port 2 pin 4 open drain mode control, see P2.00OD

0

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Table 95. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit

description

PINMODE Symbol

_OD2

Value Description

Reset

value

5

P2.05OD

P2.06OD

P2.07OD

P2.08OD

P2.09OD

P2.10OD

P2.11OD^[1]

P2.12OD^[1]

P2.13OD^[1]

-

Port 2 pin 5 open drain mode control, see P2.00OD

0

6

Port 2 pin 6 open drain mode control, see P2.00OD

Port 2 pin 7 open drain mode control, see P2.00OD

Port 2 pin 8 open drain mode control, see P2.00OD

Port 2 pin 9 open drain mode control, see P2.00OD

Port 2 pin 10 open drain mode control, see P2.00OD

Port 2 pin 11 open drain mode control, see P2.00OD

Port 2 pin 12 open drain mode control, see P2.00OD

Port 2 pin 13 open drain mode control, see P2.00OD

Reserved.

0

7

0

8

0

9

0

10

11

12

13

31:14

0

NA

[1] Not available on 80-pin package.

5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074)

This register controls the open drain mode for Port 3 pins. For details see Section 8–4 “Pin

mode select register values”.

Table 96. Open Drain Pin Mode select register 3 (PINMODE_OD3 - address 0x4002 C074) bit

description

PINMODE Symbol

_OD3

Value Description

Reset

value

24:0

25

-

Reserved.

NA

0

P3.25OD^[1]

Port 3 pin 0 open drain mode control.

0

1

P3.25 pin is in the normal (not open drain) mode.

P3.25 pin is in the open drain mode.

Port 3 pin 26 open drain mode control, see P3.25OD

Reserved.

26

P3.26OD^[1]

-

0

31:27

NA

[1] Not available on 80-pin package.

5.20 Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078)

This register controls the open drain mode for Port 4 pins. For details see Section 8–4 “Pin

mode select register values”.

Table 97. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit

description

PINMODE Symbol

_OD4

Value Description

Reset

value

27:0

-

Reserved.

NA

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Table 97. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit

description

PINMODE Symbol

_OD4

Value Description

Reset

value

28

P4.28OD

Port 4 pin 28 open drain mode control.

0

1

P4.28 pin is in the normal (not open drain) mode.

P4.28 pin is in the open drain mode.

Port 4 pin 29 open drain mode control, see P4.28OD

Reserved.

29

P4.28OD

-

0

31:30

NA

5.21 I²C Pin Configuration register (I2CPADCFG - 0x4002 C07C)

The I2CPADCFG register allows configuration of the I²C pins for the I2C0 interface only, in

order to support various I²C-bus operating modes. For use in standard or Fast Mode I²C,

the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode

Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I²C use of these pins, it may

be desirable to turn off I²C filtering and slew rate control by setting SDAI2C0 and SCLI2C0

to 1. See Table 8–98 below.

2

Table 98. I C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit

description

I2CPADCFG Symbol

Value Description

Reset

value

0

SDADRV0

SDAI2C0

Drive mode control for the SDA0 pin, P0.27.

0

1

The SDA0 pin is in the standard drive mode.

The SDA0 pin is in Fast Mode Plus drive mode.

I²C mode control for the SDA0 pin, P0.27.

1

0

1

The SDA0 pin has I²C glitch filtering and slew rate

control enabled.

The SDA0 pin has I²C glitch filtering and slew rate

control disabled.

2

3

SCLDRV0

SCLI2C0

Drive mode control for the SCL0 pin, P0.28.

The SCL0 pin is in the standard drive mode.

The SCL0 pin is in Fast Mode Plus drive mode.

I²C mode control for the SCL0 pin, P0.28.

0

1

0

1

The SCL0 pin has I²C glitch filtering and slew rate

control enabled.

The SCL0 pin has I²C glitch filtering and slew rate

control disabled.

31:4

-

Reserved.

NA

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1. Basic configuration

GPIOs are configured using the following registers:

1. Power: always enabled.

2. Pins: See Section 8–3 for GPIO pins and their modes.

3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see

(Section 4–8.8).

4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (Table 9–113) or IO0/2IntEnF

(Table 9–115). Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

2. Features

2.1 Digital I/O ports

• Accelerated GPIO functions:

– GPIO registers are located on a peripheral AHB bus for fast I/O timing.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte, half-word, and word addressable.

– Entire port value can be written in one instruction.

– GPIO registers are accessible by the GPDMA.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• All GPIO registers support Cortex-M3 bit-banding.

• GPIO registers are accessible by the GPDMA controller to allow DMA of data to or

from GPIOs, synchronized to any DMA request.

• Direction control of individual port bits.

• All I/Os default to input with pullup after reset.

2.2 Interrupt generating digital ports

• Port 0 and Port 2 can provide a single interrupt for any combination of port pins.

• Each port pin can be programmed to generate an interrupt on a rising edge, a falling

edge, or both.

• Edge detection is asynchronous, so it may operate when clocks are not present, such

as during Power-down mode. With this feature, level triggered interrupts are not

needed.

• Each enabled interrupt contributes to a wake-up signal that can be used to bring the

part out of Power-down mode.

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• Registers provide a software view of pending rising edge interrupts, pending falling

edge interrupts, and overall pending GPIO interrupts.

• GPIO0 and GPIO2 interrupts share the same position in the NVIC with External

Interrupt 3.

3. Applications

• General purpose I/O

• Driving LEDs or other indicators

• Controlling off-chip devices

• Sensing digital inputs, detecting edges

• Bringing the part out of Power-down mode

4. Pin description

Table 99. GPIO pin description

Pin Name

Type

Description

P0[30:0]^[1];

P1[31:0]^[2];

P2[13:0];

P3[26:25];

P4[29:28]

Input/

Output

General purpose input/output. These are typically shared with other

peripherals functions and will therefore not all be available in an

application. Packaging options may affect the number of GPIOs

available in a particular device.

Some pins may be limited by requirements of the alternate functions of

the pin. For example, the pins containing the I²C0 functions are

open-drain for any function selected on that pin. Details may be found

in Section 7–1.1.

[1] P0[14:12] are not available.

[2] P1[2], P1[3], P1[7:5], P1[13:11] are not available.

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5. Register description

Due to compatibility requirements with the LPC2300 series ARM7-based products, the

LPC17xx implements portions of five 32-bit General Purpose I/O ports. Details on a

specific GPIO port usage can be found in Section 8–3.

The registers in Table 9–100 represent the enhanced GPIO features available on all of the

GPIO ports. These registers are located on an AHB bus for fast read and write timing.

They can all be accessed in byte, half-word, and word sizes. A mask register allows

access to a group of bits in a single GPIO port independently from other bits in the same

port.

Table 100. GPIO register map (local bus accessible registers - enhanced GPIO features)

Generic

Name

Description

Access Reset

PORTn Register

value^[1]Name & Address

FIODIR

Fast GPIO Port Direction control register. This register

individually controls the direction of each port pin.

R/W

0

FIO0DIR - 0x2009 C000

FIO1DIR - 0x2009 C020

FIO2DIR - 0x2009 C040

FIO3DIR - 0x2009 C060

FIO4DIR - 0x2009 C080

FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to R/W

port (done via writes to FIOPIN, FIOSET, and FIOCLR, and

reads of FIOPIN) alter or return only the bits enabled by zeros

in this register.

FIO0MASK - 0x2009 C010

FIO1MASK - 0x2009 C030

FIO2MASK - 0x2009 C050

FIO3MASK - 0x2009 C070

FIO4MASK - 0x2009 C090

FIOPIN

Fast Port Pin value register using FIOMASK. The current state R/W

of digital port pins can be read from this register, regardless of

pin direction or alternate function selection (as long as pins are

not configured as an input to ADC). The value read is masked

by ANDing with inverted FIOMASK. Writing to this register

places corresponding values in all bits enabled by zeros in

FIOMASK.

FIO0PIN - 0x2009 C014

FIO1PIN - 0x2009 C034

FIO2PIN - 0x2009 C054

FIO3PIN - 0x2009 C074

FIO4PIN - 0x2009 C094

Important: if an FIOPIN register is read, its bit(s) masked with

1 in the FIOMASK register will be read as 0 regardless of the

physical pin state.

FIOSET

FIOCLR

Fast Port Output Set register using FIOMASK. This register

controls the state of output pins. Writing 1s produces highs at

the corresponding port pins. Writing 0s has no effect. Reading

this register returns the current contents of the port output

register. Only bits enabled by 0 in FIOMASK can be altered.

R/W

0

FIO0SET - 0x2009 C018

FIO1SET - 0x2009 C038

FIO2SET - 0x2009 C058

FIO3SET - 0x2009 C078

FIO4SET - 0x2009 C098

Fast Port Output Clear register using FIOMASK. This register WO

controls the state of output pins. Writing 1s produces lows at

the corresponding port pins. Writing 0s has no effect. Only bits

enabled by 0 in FIOMASK can be altered.

FIO0CLR - 0x2009 C01C

FIO1CLR - 0x2009 C03C

FIO2CLR - 0x2009 C05C

FIO3CLR - 0x2009 C07C

FIO4CLR - 0x2009 C09C

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Table 101. GPIO interrupt register map

Generic

Name

Description

Access Reset

PORTn Register

value^[1]Name & Address

IntEnR

IntEnF

IntStatR

IntStatF

IntClr

GPIO Interrupt Enable for Rising edge.

GPIO Interrupt Enable for Falling edge.

GPIO Interrupt Status for Rising edge.

GPIO Interrupt Status for Falling edge.

GPIO Interrupt Clear.

R/W

RO

0

IO0IntEnR - 0x4002 8090

IO2IntEnR - 0x4002 80B0

IO0IntEnR - 0x4002 8094

IO2IntEnR - 0x4002 80B4

IO0IntStatR - 0x4002 8084

IO2IntStatR - 0x4002 80A4

RO

IO0IntStatF - 0x4002 8088

IO2IntStatF - 0x4002 80A8

WO

RO

IO0IntClr - 0x4002 808C

IO2IntClr - 0x4002 80AC

IntStatus

GPIO overall Interrupt Status.

IOIntStatus - 0x4002 8080

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009

C000 to 0x2009 C080)

This word accessible register is used to control the direction of the pins when they are

configured as GPIO port pins. Direction bit for any pin must be set according to the pin

functionality.

Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and

must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both

P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and

P0.30 will be outputs.

Table 102. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to

0x2009 C080) bit description

Bit

Symbol

Value Description

Reset

value

31:0 FIO0DIR

FIO1DIR

Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR

controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.

Controlled pin is input.

0x0

FIO2DIR

FIO3DIR

FIOI4DIR

0

1

Controlled pin is output.

Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port

can also be controlled via several byte and half-word accessible registers listed in

Table 9–103, too. Next to providing the same functions as the FIODIR register, these

additional registers allow easier and faster access to the physical port pins.

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Table 103. Fast GPIO port Direction control byte and half-word accessible register

description

Generic

Register

name

Description

Register

length (bits) value

& access

Reset PORTn Register

Address & Name

FIOxDIR0 Fast GPIO Port x Direction

control register 0. Bit 0 in

8 (byte)

R/W

0x00

FIO0DIR0 - 0x2009 C000

FIO1DIR0 - 0x2009 C020

FIO2DIR0 - 0x2009 C040

FIO3DIR0 - 0x2009 C060

FIO4DIR0 - 0x2009 C080

FIOxDIR0 register corresponds

to pin Px.0 … bit 7 to pin Px.7.

FIOxDIR1 Fast GPIO Port x Direction

control register 1. Bit 0 in

8 (byte)

R/W

FIO0DIR1 - 0x2009 C001

FIO1DIR1 - 0x2009 C021

FIO2DIR1 - 0x2009 C041

FIO3DIR1 - 0x2009 C061

FIO4DIR1 - 0x2009 C081

FIOxDIR1 register corresponds

to pin Px.8 … bit 7 to pin Px.15.

FIO0DIR2 Fast GPIO Port x Direction

control register 2. Bit 0 in

FIOxDIR2 register corresponds

to pin Px.16 … bit 7 to pin

Px.23.

8 (byte)

R/W

FIO0DIR2 - 0x2009 C002

FIO1DIR2 - 0x2009 C022

FIO2DIR2 - 0x2009 C042

FIO3DIR2 - 0x2009 C062

FIO4DIR2 - 0x2009 C082

FIOxDIR3 Fast GPIO Port x Direction

control register 3. Bit 0 in

FIOxDIR3 register corresponds

to pin Px.24 … bit 7 to pin

Px.31.

8 (byte)

R/W

FIO0DIR3 - 0x2009 C003

FIO1DIR3 - 0x2009 C023

FIO2DIR3 - 0x2009 C043

FIO3DIR3 - 0x2009 C063

FIO4DIR3 - 0x2009 C083

FIOxDIRL Fast GPIO Port x Direction

control Lower half-word

16 (half-word) 0x0000 FIO0DIRL - 0x2009 C000

R/W

FIO1DIRL - 0x2009 C020

FIO2DIRL - 0x2009 C040

FIO3DIRL - 0x2009 C060

FIO4DIRL - 0x2009 C080

register. Bit 0 in FIOxDIRL

register corresponds to pin

Px.0 … bit 15 to pin Px.15.

FIOxDIRU Fast GPIO Port x Direction

control Upper half-word

16 (half-word) 0x0000 FIO0DIRU - 0x2009 C002

R/W

FIO1DIRU - 0x2009 C022

FIO2DIRU - 0x2009 C042

FIO3DIRU - 0x2009 C062

FIO4DIRU - 0x2009 C082

register. Bit 0 in FIOxDIRU

register corresponds to Px.16

… bit 15 to Px.31.

5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009

C018 to 0x2009 C098)

This register is used to produce a HIGH level output at the port pins configured as GPIO in

an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.

Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing

1 to the corresponding bit in the FIOxSET has no effect.

Reading the FIOxSET register returns the value of this register, as determined by

previous writes to FIOxSET and FIOxCLR (or FIOxPIN as noted above). This value does

not reflect the effect of any outside world influence on the I/O pins.

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Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of

the FIOxMASK register (see Section 9–5.5).

Table 104. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018

to 0x2009 C098) bit description

Bit

Symbol Value Description

Reset

value

31:0 FIO0SET

FIO1SET

Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin

Px.0, bit 31 in FIOxSET controls pin Px.31.

0x0

FIO2SET

FIO3SET

FIO4SET

0

1

Controlled pin output is unchanged.

Controlled pin output is set to HIGH.

Aside from the 32-bit long and word only accessible FIOxSET register, every fast GPIO

port can also be controlled via several byte and half-word accessible registers listed in

Table 9–105, too. Next to providing the same functions as the FIOxSET register, these

additional registers allow easier and faster access to the physical port pins.

Table 105. Fast GPIO port output Set byte and half-word accessible register description

Generic

Register

name

Description

Register

length (bits) value

& access

Reset PORTn Register

Address & Name

FIOxSET0 Fast GPIO Port x output Set 8 (byte)

register 0. Bit 0 in FIOxSET0 R/W

register corresponds to pin

0x00

FIO0SET0 - 0x2009 C018

FIO1SET0 - 0x2009 C038

FIO2SET0 - 0x2009 C058

FIO3SET0 - 0x2009 C078

FIO4SET0 - 0x2009 C098

Px.0 … bit 7 to pin Px.7.

FIOxSET1 Fast GPIO Port x output Set 8 (byte)

register 1. Bit 0 in FIOxSET1 R/W

register corresponds to pin

FIO0SET1 - 0x2009 C019

FIO1SET1 - 0x2009 C039

FIO2SET1 - 0x2009 C059

FIO3SET1 - 0x2009 C079

FIO4SET1 - 0x2009 C099

Px.8 … bit 7 to pin Px.15.

FIOxSET2 Fast GPIO Port x output Set 8 (byte)

register 2. Bit 0 in FIOxSET2 R/W

register corresponds to pin

FIO0SET2 - 0x2009 C01A

FIO1SET2 - 0x2009 C03A

FIO2SET2 - 0x2009 C05A

FIO3SET2 - 0x2009 C07A

FIO4SET2 - 0x2009 C09A

Px.16 … bit 7 to pin Px.23.

FIOxSET3 Fast GPIO Port x output Set 8 (byte)

register 3. Bit 0 in FIOxSET3 R/W

register corresponds to pin

FIO0SET3 - 0x2009 C01B

FIO1SET3 - 0x2009 C03B

FIO2SET3 - 0x2009 C05B

FIO3SET3 - 0x2009 C07B

FIO4SET3 - 0x2009 C09B

Px.24 … bit 7 to pin Px.31.

FIOxSETL Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETL - 0x2009 C018

Lower half-word register. Bit 0 R/W

in FIOxSETL register

corresponds to pin Px.0 … bit

15 to pin Px.15.

FIO1SETL - 0x2009 C038

FIO2SETL - 0x2009 C058

FIO3SETL - 0x2009 C078

FIO4SETL - 0x2009 C098

FIOxSETU Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETU - 0x2009 C01A

Upper half-word register. Bit 0 R/W

in FIOxSETU register

corresponds to Px.16 … bit

15 to Px.31.

FIO1SETU - 0x2009 C03A

FIO2SETU - 0x2009 C05A

FIO3SETU - 0x2009 C07A

FIO4SETU - 0x2009 C09A

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5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR-

0x2009 C01C to 0x2009 C09C)

This register is used to produce a LOW level output at port pins configured as GPIO in an

OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears

the corresponding bit in the FIOxSET register. Writing 0 has no effect. If any pin is

configured as an input or a secondary function, writing to FIOxCLR has no effect.

Access to a port pin via the FIOxCLR register is conditioned by the corresponding bit of

the FIOxMASK register (see Section 9–5.5).

Table 106. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009

C01C to 0x2009 C09C) bit description

Bit

Symbol Value Description

Reset

value

31:0 FIO0CLR

FIO1CLR

Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin 0x0

Px.0, bit 31 controls pin Px.31.

FIO2CLR

FIO3CLR

FIO4CLR

0

1

Controlled pin output is unchanged.

Controlled pin output is set to LOW.

Aside from the 32-bit long and word only accessible FIOxCLR register, every fast GPIO

port can also be controlled via several byte and half-word accessible registers listed in

Table 9–107, too. Next to providing the same functions as the FIOxCLR register, these

additional registers allow easier and faster access to the physical port pins.

Table 107. Fast GPIO port output Clear byte and half-word accessible register description

Generic

Register

name

Description

Register

length (bits)

& access

Reset PORTn Register

value

Address & Name

FIOxCLR0 Fast GPIO Port x output

Clear register 0. Bit 0 in

FIOxCLR0 register

8 (byte)

WO

0x00

FIO0CLR0 - 0x2009 C01C

FIO1CLR0 - 0x2009 C03C

FIO2CLR0 - 0x2009 C05C

FIO3CLR0 - 0x2009 C07C

FIO4CLR0 - 0x2009 C09C

corresponds to pin Px.0 …

bit 7 to pin Px.7.

FIOxCLR1 Fast GPIO Port x output

Clear register 1. Bit 0 in

FIOxCLR1 register

8 (byte)

WO

0x00

FIO0CLR1 - 0x2009 C01D

FIO1CLR1 - 0x2009 C03D

FIO2CLR1 - 0x2009 C05D

FIO3CLR1 - 0x2009 C07D

FIO4CLR1 - 0x2009 C09D

corresponds to pin Px.8 …

bit 7 to pin Px.15.

FIOxCLR2 Fast GPIO Port x output

Clear register 2. Bit 0 in

FIOxCLR2 register

8 (byte)

WO

FIO0CLR2 - 0x2009 C01E

FIO1CLR2 - 0x2009 C03E

FIO2CLR2 - 0x2009 C05E

FIO3CLR2 - 0x2009 C07E

FIO4CLR2 - 0x2009 C09E

corresponds to pin Px.16 …

bit 7 to pin Px.23.

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Table 107. Fast GPIO port output Clear byte and half-word accessible register description

Generic

Register

name

Description

Register

length (bits)

& access

Reset PORTn Register

value

Address & Name

FIOxCLR3 Fast GPIO Port x output

Clear register 3. Bit 0 in

FIOxCLR3 register

8 (byte)

WO

0x00

FIO0CLR3 - 0x2009 C01F

FIO1CLR3 - 0x2009 C03F

FIO2CLR3 - 0x2009 C05F

FIO3CLR3 - 0x2009 C07F

FIO4CLR3 - 0x2009 C09F

corresponds to pin Px.24 …

bit 7 to pin Px.31.

FIOxCLRL Fast GPIO Port x output

Clear Lower half-word

16 (half-word) 0x0000 FIO0CLRL - 0x2009 C01C

WO

FIO1CLRL - 0x2009 C03C

FIO2CLRL - 0x2009 C05C

FIO3CLRL - 0x2009 C07C

FIO4CLRL - 0x2009 C09C

register. Bit 0 in FIOxCLRL

register corresponds to pin

Px.0 … bit 15 to pin Px.15.

FIOxCLRU Fast GPIO Port x output

Clear Upper half-word

16 (half-word) 0x0000 FIO0CLRU - 0x2009 C01E

WO

FIO1CLRU - 0x2009 C03E

FIO2CLRU - 0x2009 C05E

FIO3CLRU - 0x2009 C07E

FIO4CLRU - 0x2009 C09E

register. Bit 0 in FIOxCLRU

register corresponds to pin

Px.16 … bit 15 to Px.31.

5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009

C014 to 0x2009 C094)

This register provides the value of port pins that are configured to perform only digital

functions. The register will give the logic value of the pin regardless of whether the pin is

configured for input or output, or as GPIO or an alternate digital function. As an example,

a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output

as selectable functions. Any configuration of that pin will allow its current logic state to be

read from the corresponding FIOxPIN register.

If a pin has an analog function as one of its options, the pin state cannot be read if the

analog configuration is selected. Selecting the pin as an A/D input disconnects the digital

features of the pin. In that case, the pin value read in the FIOxPIN register is not valid.

Writing to the FIOxPIN register stores the value in the port output register, bypassing the

need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value.

This feature should be used carefully in an application since it affects the entire port.

Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of

the FIOxMASK register (see Section 9–5.5).

Only pins masked with zeros in the Mask register (see Section 9–5.5) will be correlated to

the current content of the Fast GPIO port pin value register.

Table 108. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to

0x2009 C094) bit description

Bit

Symbol Value Description

Reset

value

31:0 FIO0VAL

FIO1VAL

Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds 0x0

to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31.

FIO2VAL

FIO3VAL

FIO4VAL

0

1

Controlled pin output is set to LOW.

Controlled pin output is set to HIGH.

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Aside from the 32-bit long and word only accessible FIOxPIN register, every fast GPIO

port can also be controlled via several byte and half-word accessible registers listed in

Table 9–109, too. Next to providing the same functions as the FIOxPIN register, these

additional registers allow easier and faster access to the physical port pins.

Table 109. Fast GPIO port Pin value byte and half-word accessible register description

Generic

Register

name

Description

Register

length (bits) value

& access

Reset PORTn Register

Address & Name

FIOxPIN0 Fast GPIO Port x Pin value

register 0. Bit 0 in FIOxPIN0

register corresponds to pin

8 (byte)

R/W

0x00

FIO0PIN0 - 0x2009 C014

FIO1PIN0 - 0x2009 C034

FIO2PIN0 - 0x2009 C054

FIO3PIN0 - 0x2009 C074

FIO4PIN0 - 0x2009 C094

Px.0 … bit 7 to pin Px.7.

FIOxPIN1 Fast GPIO Port x Pin value

register 1. Bit 0 in FIOxPIN1

register corresponds to pin

8 (byte)

R/W

FIO0PIN1 - 0x2009 C015

FIO1PIN1 - 0x2009 C035

FIO2PIN1 - 0x2009 C055

FIO3PIN1 - 0x2009 C075

FIO4PIN1 - 0x2009 C095

Px.8 … bit 7 to pin Px.15.

FIOxPIN2 Fast GPIO Port x Pin value

register 2. Bit 0 in FIOxPIN2

register corresponds to pin

8 (byte)

R/W

FIO0PIN2 - 0x2009 C016

FIO1PIN2 - 0x2009 C036

FIO2PIN2 - 0x2009 C056

FIO3PIN2 - 0x2009 C076

FIO4PIN2 - 0x2009 C096

Px.16 … bit 7 to pin Px.23.

FIOxPIN3 Fast GPIO Port x Pin value

register 3. Bit 0 in FIOxPIN3

register corresponds to pin

8 (byte)

R/W

FIO0PIN3 - 0x2009 C017

FIO1PIN3 - 0x2009 C037

FIO2PIN3 - 0x2009 C057

FIO3PIN3 - 0x2009 C077

FIO4PIN3 - 0x2009 C097

Px.24 … bit 7 to pin Px.31.

FIOxPINL Fast GPIO Port x Pin value

16 (half-word) 0x0000 FIO0PINL - 0x2009 C014

Lower half-word register. Bit 0 R/W

in FIOxPINL register

corresponds to pin Px.0 … bit

15 to pin Px.15.

FIO1PINL - 0x2009 C034

FIO2PINL - 0x2009 C054

FIO3PINL - 0x2009 C074

FIO4PINL - 0x2009 C094

FIOxPINU Fast GPIO Port x Pin value

16 (half-word) 0x0000 FIO0PINU - 0x2009 C016

Upper half-word register. Bit 0 R/W

FIO1PINU - 0x2009 C036

FIO2PINU - 0x2009 C056

FIO3PINU - 0x2009 C076

FIO4PINU - 0x2009 C096

in FIOxPINU register

corresponds to pin Px.16 … bit

15 to Px.31.

5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK -

0x2009 C010 to 0x2009 C090)

This register is used to select port pins that will and will not be affected by write accesses

to the FIOxPIN, FIOxSET or FIOxCLR register. Mask register also filters out port’s content

when the FIOxPIN register is read.

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A zero in this register’s bit enables an access to the corresponding physical pin via a read

or write access. If a bit in this register is one, corresponding pin will not be changed with

write access and if read, will not be reflected in the updated FIOxPIN register. For

software examples, see Section 9–6.

Table 110. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010

to 0x2009 C090) bit description

Bit Symbol

Value Description

Reset

value

31:0 FIO0MASK

FIO1MASK

Fast GPIO physical pin access control.

0x0

0

1

Controlled pin is affected by writes to the port’s FIOxSET,

FIOxCLR, and FIOxPIN register(s). Current state of the pin

can be read from the FIOxPIN register.

FIO2MASK

FIO3MASK

FIO4MASK

Controlled pin is not affected by writes into the port’s

FIOxSET, FIOxCLR and FIOxPIN register(s). When the

FIOxPIN register is read, this bit will not be updated with the

state of the physical pin.

Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO

port can also be controlled via several byte and half-word accessible registers listed in

Table 9–111, too. Next to providing the same functions as the FIOxMASK register, these

additional registers allow easier and faster access to the physical port pins.

Table 111. Fast GPIO port Mask byte and half-word accessible register description

Generic

Register

name

Description

Register

Reset PORTn Register

length (bits) value Address & Name

& access

FIOxMASK0 Fast GPIO Port x Mask

register 0. Bit 0 in

8 (byte)

R/W

0x0

FIO0MASK0 - 0x2009 C010

FIO1MASK0 - 0x2009 C030

FIO2MASK0 - 0x2009 C050

FIO3MASK0 - 0x2009 C070

FIO4MASK0 - 0x2009 C090

FIOxMASK0 register

corresponds to pin Px.0 …

bit 7 to pin Px.7.

FIOxMASK1 Fast GPIO Port x Mask

register 1. Bit 0 in

8 (byte)

R/W

FIO0MASK1 - 0x2009 C011

FIO1MASK1 - 0x2009 C031

FIO2MASK1 - 0x2009 C051

FIO3MASK1 - 0x2009 C071

FIO4MASK1 - 0x2009 C091

FIOxMASK1 register

corresponds to pin Px.8 …

bit 7 to pin Px.15.

FIOxMASK2 Fast GPIO Port x Mask

register 2. Bit 0 in

8 (byte)

R/W

FIO0MASK2 - 0x2009 C012

FIO1MASK2 - 0x2009 C032

FIO2MASK2 - 0x2009 C052

FIO3MASK2 - 0x2009 C072

FIO4MASK2 - 0x2009 C092

FIOxMASK2 register

corresponds to pin Px.16 …

bit 7 to pin Px.23.

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Table 111. Fast GPIO port Mask byte and half-word accessible register description

Generic

Register

name

Description

Register

Reset PORTn Register

length (bits) value Address & Name

& access

FIOxMASK3 Fast GPIO Port x Mask

register 3. Bit 0 in

8 (byte)

R/W

0x0

FIO0MASK3 - 0x2009 C013

FIO1MASK3 - 0x2009 C033

FIO2MASK3 - 0x2009 C053

FIO3MASK3 - 0x2009 C073

FIO4MASK3 - 0x2009 C093

FIOxMASK3 register

corresponds to pin Px.24 …

bit 7 to pin Px.31.

FIOxMASKL Fast GPIO Port x Mask

Lower half-word register.

16

FIO0MASKL - 0x2009 C010

FIO1MASKL - 0x2009 C030

FIO2MASKL - 0x2009 C050

FIO3MASKL - 0x2009 C070

FIO4MASKL - 0x2009 C090

(half-word)

R/W

Bit 0 in FIOxMASKL

register corresponds to pin

Px.0 … bit 15 to pin Px.15.

FIOxMASKU Fast GPIO Port x Mask

Upper half-word register.

Bit 0 in FIOxMASKU

16

FIO0MASKU - 0x2009 C012

FIO1MASKU - 0x2009 C032

FIO2MASKU - 0x2009 C052

FIO3MASKU - 0x2009 C072

FIO4MASKU - 0x2009 C092

(half-word)

R/W

register corresponds to pin

Px.16 … bit 15 to Px.31.

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5.6 GPIO interrupt registers

The following registers configure the pins of Port 0 and Port 2 to generate interrupts.

5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080)

This read-only register indicates the presence of interrupt pending on all of the GPIO ports

that support GPIO interrupts. Only status one bit per port is required.

Table 112. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit

description

Bit

Symbol Value Description

Reset

value

0

P0Int

Port 0 GPIO interrupt pending.

0

1

-

There are no pending interrupts on Port 0.

There is at least one pending interrupt on Port 0.

Reserved. The value read from a reserved bit is not defined.

Port 2 GPIO interrupt pending.

1

2

-

NA

0

P2Int

0

1

-

There are no pending interrupts on Port 2.

There is at least one pending interrupt on Port 2.

Reserved. The value read from a reserved bit is not defined.

31:2

-

NA

5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090)

Each bit in these read-write registers enables the rising edge interrupt for the

corresponding port 0 pin.

Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit

description

Bit

Symbol

Value Description

Reset

value

0

P0.0ER

Enable rising edge interrupt for P0.0.

0

1

Rising edge interrupt is disabled on P0.0.

Rising edge interrupt is enabled on P0.0.

Enable rising edge interrupt for P0.1.

Enable rising edge interrupt for P0.2.

Enable rising edge interrupt for P0.3.

Enable rising edge interrupt for P0.4.

Enable rising edge interrupt for P0.5.

Enable rising edge interrupt for P0.6.

Enable rising edge interrupt for P0.7.

Enable rising edge interrupt for P0.8.

Enable rising edge interrupt for P0.9.

Enable rising edge interrupt for P0.10.

Enable rising edge interrupt for P0.11.

Reserved

1

P0.1ER

P0.2ER

P0.3ER

P0.4ER^[1]

P0.5ER^[1]

P0.6ER

P0.7ER

P0.8ER

P0.9ER

P0.10ER

P0.11ER

-

0

2

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

11

14:12

15

16

0

NA

0

P0.15ER

P0.16ER

Enable rising edge interrupt for P0.15.

Enable rising edge interrupt for P0.16.

0

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Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit

description

Bit

Symbol

Value Description

Reset

value

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

P0.17ER

P0.18ER

P0.19ER^[1]

P0.20ER^[1]

P0.21ER^[1]

P0.22ER

P0.23ER^[1]

P0.24ER^[1]

P0.25ER

P0.26ER

P0.27ER^[1]

P0.28ER^[1]

P0.29ER

P0.30ER

-

Enable rising edge interrupt for P0.17.

0

Enable rising edge interrupt for P0.18.

Enable rising edge interrupt for P0.19.

Enable rising edge interrupt for P0.20.

Enable rising edge interrupt for P0.21.

Enable rising edge interrupt for P0.22.

Enable rising edge interrupt for P0.23.

Enable rising edge interrupt for P0.24.

Enable rising edge interrupt for P0.25.

Enable rising edge interrupt for P0.26.

Enable rising edge interrupt for P0.27.

Enable rising edge interrupt for P0.28.

Enable rising edge interrupt for P0.29.

Enable rising edge interrupt for P0.30.

Reserved.

0

NA

[1] Not available on 80-pin package.

5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0)

Each bit in these read-write registers enables the rising edge interrupt for the

corresponding port 2 pin.

Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit

description

Bit

Symbol

Value Description

Reset

value

0

P2.0ER

Enable rising edge interrupt for P2.0.

0

1

Rising edge interrupt is disabled on P2.0.

Rising edge interrupt is enabled on P2.0.

Enable rising edge interrupt for P2.1.

Enable rising edge interrupt for P2.2.

Enable rising edge interrupt for P2.3.

Enable rising edge interrupt for P2.4.

Enable rising edge interrupt for P2.5.

Enable rising edge interrupt for P2.6.

Enable rising edge interrupt for P2.7.

Enable rising edge interrupt for P2.8.

Enable rising edge interrupt for P2.9.

Enable rising edge interrupt for P2.10.

Enable rising edge interrupt for P2.11.

1

P2.1ER

P2.2ER

P2.3ER

P2.4ER

P2.5ER

P2.6ER

P2.7ER

P2.8ER

P2.9ER

P2.10ER

P2.11ER^[1]

0

2

3

4

5

6

7

8

9

10

11

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Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit

description

Bit

Symbol

Value Description

Reset

value

12

P2.12ER^[1]

P2.13ER^[1]

-

Enable rising edge interrupt for P2.12.

0

13

Enable rising edge interrupt for P2.13.

Reserved.

0

31:14

NA

[1] Not available on 80-pin package.

5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094)

Each bit in these read-write registers enables the falling edge interrupt for the

corresponding GPIO port 0 pin.

Table 115. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)

bit description

Bit

Symbol

Value Description

Reset

value

0

P0.0EF

Enable falling edge interrupt for P0.0

0

1

Falling edge interrupt is disabled on P0.0.

Falling edge interrupt is enabled on P0.0.

Enable falling edge interrupt for P0.1.

Enable falling edge interrupt for P0.2.

Enable falling edge interrupt for P0.3.

Enable falling edge interrupt for P0.4.

Enable falling edge interrupt for P0.5.

Enable falling edge interrupt for P0.6.

Enable falling edge interrupt for P0.7.

Enable falling edge interrupt for P0.8.

Enable falling edge interrupt for P0.9.

Enable falling edge interrupt for P0.10.

Enable falling edge interrupt for P0.11.

Reserved.

1

P0.1EF

0

NA

0

2

P0.2EF

3

P0.3EF

4

P0.4EF^[1]

P0.5EF^[1]

P0.6EF

5

6

7

P0.7EF

8

P0.8EF

9

P0.9EF

10

11

14:12

15

16

17

18

19

20

21

22

23

24

25

26

27

P0.10EF

P0.11EF

-

P0.15EF

P0.16EF

P0.17EF

P0.18EF

P0.19EF^[1]

P0.20EF^[1]

P0.21EF^[1]

P0.22EF

P0.23EF^[1]

P0.24EF^[1]

P0.25EF

P0.26EF

P0.27EF^[1]

Enable falling edge interrupt for P0.15.

Enable falling edge interrupt for P0.16.

Enable falling edge interrupt for P0.17.

Enable falling edge interrupt for P0.18.

Enable falling edge interrupt for P0.19.

Enable falling edge interrupt for P0.20.

Enable falling edge interrupt for P0.21.

Enable falling edge interrupt for P0.22.

Enable falling edge interrupt for P0.23.

Enable falling edge interrupt for P0.24.

Enable falling edge interrupt for P0.25.

Enable falling edge interrupt for P0.26.

Enable falling edge interrupt for P0.27.

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Table 115. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)

bit description

Bit

Symbol

Value Description

Reset

value

28

29

30

31

P0.28EF^[1]

P0.29EF

P0.30EF

-

Enable falling edge interrupt for P0.28.

0

Enable falling edge interrupt for P0.29.

Enable falling edge interrupt for P0.30.

Reserved.

0

NA

[1] Not available on 80-pin package.

5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)

Each bit in these read-write registers enables the falling edge interrupt for the

corresponding GPIO port 2 pin.

Table 116. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit

description

Bit

Symbol

Value Description

Reset

value

0

P2.0EF

Enable falling edge interrupt for P2.0

0

1

Falling edge interrupt is disabled on P2.0.

Falling edge interrupt is enabled on P2.0.

Enable falling edge interrupt for P2.1.

Enable falling edge interrupt for P2.2.

Enable falling edge interrupt for P2.3.

Enable falling edge interrupt for P2.4.

Enable falling edge interrupt for P2.5.

Enable falling edge interrupt for P2.6.

Enable falling edge interrupt for P2.7.

Enable falling edge interrupt for P2.8.

Enable falling edge interrupt for P2.9.

Enable falling edge interrupt for P2.10.

Enable falling edge interrupt for P2.11.

Enable falling edge interrupt for P2.12.

Enable falling edge interrupt for P2.13.

Reserved.

1

P2.1EF

P2.2EF

P2.3EF

P2.4EF

P2.5EF

P2.6EF

P2.7EF

P2.8EF

P2.9EF

P2.10EF

P2.11EF^[1]

P2.12EF^[1]

P2.13EF^[1]

-

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

11

12

13

31:14

0

NA

[1] Not available on 80-pin package.

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5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR -

0x4002 8084)

Each bit in these read-only registers indicates the rising edge interrupt status for port 0.

Table 117. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084)

bit description

Bit

Symbol

Value Description

Reset

value

0

P0.0REI

Status of Rising Edge Interrupt for P0.0

0

1

A rising edge has not been detected on P0.0.

Interrupt has been generated due to a rising edge on P0.0.

Status of Rising Edge Interrupt for P0.1.

Status of Rising Edge Interrupt for P0.2.

Status of Rising Edge Interrupt for P0.3.

Status of Rising Edge Interrupt for P0.4.

Status of Rising Edge Interrupt for P0.5.

Status of Rising Edge Interrupt for P0.6.

Status of Rising Edge Interrupt for P0.7.

Status of Rising Edge Interrupt for P0.8.

Status of Rising Edge Interrupt for P0.9.

Status of Rising Edge Interrupt for P0.10.

Status of Rising Edge Interrupt for P0.11.

Reserved.

1

P0.1REI

P0.2REI

P0.3REI

P0.4REI^[1]

P0.5REI^[1]

P0.6REI

P0.7REI

P0.8REI

P0.9REI

P0.10REI

P0.11REI

-

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

11

14:12

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

NA

0

P0.15REI

P0.16REI

P0.17REI

P0.18REI

P0.19REI^[1]

P0.20REI^[1]

P0.21REI^[1]

P0.22REI

P0.23REI^[1]

P0.24REI^[1]

P0.25REI

P0.26REI

P0.27REI^[1]

P0.28REI^[1]

P0.29REI

P0.30REI

-

Status of Rising Edge Interrupt for P0.15.

Status of Rising Edge Interrupt for P0.16.

Status of Rising Edge Interrupt for P0.17.

Status of Rising Edge Interrupt for P0.18.

Status of Rising Edge Interrupt for P0.19.

Status of Rising Edge Interrupt for P0.20.

Status of Rising Edge Interrupt for P0.21.

Status of Rising Edge Interrupt for P0.22.

Status of Rising Edge Interrupt for P0.23.

Status of Rising Edge Interrupt for P0.24.

Status of Rising Edge Interrupt for P0.25.

Status of Rising Edge Interrupt for P0.26.

Status of Rising Edge Interrupt for P0.27.

Status of Rising Edge Interrupt for P0.28.

Status of Rising Edge Interrupt for P0.29.

Status of Rising Edge Interrupt for P0.30.

Reserved.

0

NA

[1] Not available on 80-pin package.

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Chapter 9: LPC17xx General Purpose Input/Output (GPIO)

5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR -

0x4002 80A4)

Each bit in these read-only registers indicates the rising edge interrupt status for port 2.

Table 118. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4)

bit description

Bit

Symbol

Value Description

Reset

value

0

P2.0REI

Status of Rising Edge Interrupt for P2.0

0

1

A rising edge has not been detected on P2.0.

Interrupt has been generated due to a rising edge on P2.0.

Status of Rising Edge Interrupt for P2.1.

Status of Rising Edge Interrupt for P2.2.

Status of Rising Edge Interrupt for P2.3.

Status of Rising Edge Interrupt for P2.4.

Status of Rising Edge Interrupt for P2.5.

Status of Rising Edge Interrupt for P2.6.

Status of Rising Edge Interrupt for P2.7.

Status of Rising Edge Interrupt for P2.8.

Status of Rising Edge Interrupt for P2.9.

Status of Rising Edge Interrupt for P2.10.

Status of Rising Edge Interrupt for P2.11.

Status of Rising Edge Interrupt for P2.12.

Status of Rising Edge Interrupt for P2.13.

Reserved.

1

P2.1REI

P2.2REI

P2.3REI

P2.4REI

P2.5REI

P2.6REI

P2.7REI

P2.8REI

P2.9REI

P2.10REI

P2.11REI^[1]

P2.12REI^[1]

P2.13REI^[1]

-

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

11

12

13

31:14

0

NA

[1] Not available on 80-pin package.

5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF -

0x4002 8088)

Each bit in these read-only registers indicates the falling edge interrupt status for port 0.

Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088)

bit description

Bit

Symbol

Value Description

Reset

value

0

P0.0FEI

Status of Falling Edge Interrupt for P0.0

0

1

A falling edge has not been detected on P0.0.

Interrupt has been generated due to a falling edge on P0.0.

Status of Falling Edge Interrupt for P0.1.

Status of Falling Edge Interrupt for P0.2.

Status of Falling Edge Interrupt for P0.3.

Status of Falling Edge Interrupt for P0.4.

Status of Falling Edge Interrupt for P0.5.

Status of Falling Edge Interrupt for P0.6.

Status of Falling Edge Interrupt for P0.7.

1

2

3

4

5

6

7

P0.1FEI

P0.2FEI

P0.3FEI

P0.4FEI^[1]

P0.5FEI^[1]

P0.6FEI

P0.7FEI

0

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Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088)

bit description

Bit

Symbol

Value Description

Reset

value

8

P0.8FEI

Status of Falling Edge Interrupt for P0.8.

0

9

P0.9FEI

Status of Falling Edge Interrupt for P0.9.

Status of Falling Edge Interrupt for P0.10.

Status of Falling Edge Interrupt for P0.11.

Reserved.

0

10

11

14:12

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

P0.10FEI

P0.11FEI

-

0

NA

0

P0.15FEI

P0.16FEI

P0.17FEI

P0.18FEI

P0.19FEI^[1]

P0.20FEI^[1]

P0.21FEI^[1]

P0.22FEI

P0.23FEI^[1]

P0.24FEI^[1]

P0.25FEI

P0.26FEI

P0.27FEI^[1]

P0.28FEI^[1]

P0.29FEI

P0.30FEI

-

Status of Falling Edge Interrupt for P0.15.

Status of Falling Edge Interrupt for P0.16.

Status of Falling Edge Interrupt for P0.17.

Status of Falling Edge Interrupt for P0.18.

Status of Falling Edge Interrupt for P0.19.

Status of Falling Edge Interrupt for P0.20.

Status of Falling Edge Interrupt for P0.21.

Status of Falling Edge Interrupt for P0.22.

Status of Falling Edge Interrupt for P0.23.

Status of Falling Edge Interrupt for P0.24.

Status of Falling Edge Interrupt for P0.25.

Status of Falling Edge Interrupt for P0.26.

Status of Falling Edge Interrupt for P0.27.

Status of Falling Edge Interrupt for P0.28.

Status of Falling Edge Interrupt for P0.29.

Status of Falling Edge Interrupt for P0.30.

Reserved.

0

NA

[1] Not available on 80-pin package.

5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF -

0x4002 80A8)

Each bit in these read-only registers indicates the falling edge interrupt status for port 2.

Table 120. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)

bit description

Bit

Symbol

Value Description

Reset

value

0

P2.0FEI

Status of Falling Edge Interrupt for P2.0

0

1

A falling edge has not been detected on P2.0.

Interrupt has been generated due to a falling edge on P2.0.

Status of Falling Edge Interrupt for P2.1.

Status of Falling Edge Interrupt for P2.2.

Status of Falling Edge Interrupt for P2.3.

Status of Falling Edge Interrupt for P2.4.

Status of Falling Edge Interrupt for P2.5.

Status of Falling Edge Interrupt for P2.6.

1

2

3

4

5

6

P2.1FEI

P2.2FEI

P2.3FEI

P2.4FEI

P2.5FEI

P2.6FEI

0

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Table 120. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)

bit description

Bit

Symbol

Value Description

Reset

value

7

P2.7FEI

P2.8FEI

P2.9FEI

P2.10FEI

P2.11FEI^[1]

P2.12FEI^[1]

P2.13FEI^[1]

-

Status of Falling Edge Interrupt for P2.7.

0

8

Status of Falling Edge Interrupt for P2.8.

Status of Falling Edge Interrupt for P2.9.

Status of Falling Edge Interrupt for P2.10.

Status of Falling Edge Interrupt for P2.11.

Status of Falling Edge Interrupt for P2.12.

Status of Falling Edge Interrupt for P2.13.

Reserved.

0

9

0

10

11

12

13

31:14

0

NA

[1] Not available on 80-pin package.

5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)

Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding

port 0 pin.

Table 121. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description

Bit

Symbol

Value Description

Reset

value

0

P0.0CI

Clear GPIO port Interrupts for P0.0

0

1

Corresponding bits in IOxIntStatR and IOxIntStatF are

unchanged.

Corresponding bits in IOxIntStatR and IOxStatF are cleared.

Clear GPIO port Interrupts for P0.1.

Clear GPIO port Interrupts for P0.2.

Clear GPIO port Interrupts for P0.3.

Clear GPIO port Interrupts for P0.4.

Clear GPIO port Interrupts for P0.5.

Clear GPIO port Interrupts for P0.6.

Clear GPIO port Interrupts for P0.7.

Clear GPIO port Interrupts for P0.8.

Clear GPIO port Interrupts for P0.9.

Clear GPIO port Interrupts for P0.10.

Clear GPIO port Interrupts for P0.11.

Reserved.

1

P0.1CI

0

NA

0

2

P0.2CI

3

P0.3CI

4

P0.4CI^[1]

P0.5CI^[1]

P0.6CI

5

6

7

P0.7CI

8

P0.8CI

9

P0.9CI

10

11

14:12

15

16

17

18

19

20

21

22

P0.10CI

P0.11CI

-

P0.15CI

P0.16CI

P0.17CI

P0.18CI

P0.19CI^[1]

P0.20CI^[1]

P0.21CI^[1]

P0.22CI

Clear GPIO port Interrupts for P0.15.

Clear GPIO port Interrupts for P0.16.

Clear GPIO port Interrupts for P0.17.

Clear GPIO port Interrupts for P0.18.

Clear GPIO port Interrupts for P0.19.

Clear GPIO port Interrupts for P0.20.

Clear GPIO port Interrupts for P0.21.

Clear GPIO port Interrupts for P0.22.

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Table 121. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description

Bit

Symbol

Value Description

Reset

value

23

24

25

26

27

28

29

30

31

P0.23CI^[1]

P0.24CI^[1]

P0.25CI

P0.26CI

P0.27CI^[1]

P0.28CI^[1]

P0.29CI

P0.30CI

-

Clear GPIO port Interrupts for P0.23.

0

Clear GPIO port Interrupts for P0.24.

Clear GPIO port Interrupts for P0.25.

Clear GPIO port Interrupts for P0.26.

Clear GPIO port Interrupts for P0.27.

Clear GPIO port Interrupts for P0.28.

Clear GPIO port Interrupts for P0.29.

Clear GPIO port Interrupts for P0.30.

Reserved.

0

NA

[1] Not available on 80-pin package.

5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC)

Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding

port 2 pin.

Table 122. GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) bit description

Bit

Symbol

Value Description

Reset

value

0

P2.0CI

Clear GPIO port Interrupts for P2.0

0

1

Corresponding bits in IOxIntStatR and IOxIntStatF are

unchanged.

Corresponding bits in IOxIntStatR and IOxStatF are cleared.

Clear GPIO port Interrupts for P2.1.

Clear GPIO port Interrupts for P2.2.

Clear GPIO port Interrupts for P2.3.

Clear GPIO port Interrupts for P2.4.

Clear GPIO port Interrupts for P2.5.

Clear GPIO port Interrupts for P2.6.

Clear GPIO port Interrupts for P2.7.

Clear GPIO port Interrupts for P2.8.

Clear GPIO port Interrupts for P2.9.

Clear GPIO port Interrupts for P2.10.

Clear GPIO port Interrupts for P2.11.

Clear GPIO port Interrupts for P2.12.

Clear GPIO port Interrupts for P2.13.

Reserved.

1

P2.1CI

P2.2CI

P2.3CI

P2.4CI

P2.5CI

P2.6CI

P2.7CI

P2.8CI

P2.9CI

P2.10CI

P2.11CI^[1]

P2.12CI^[1]

P2.13CI^[1]

-

0

2

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

11

12

13

31:14

0

NA

[1] Not available on 80-pin package.

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6. GPIO usage notes

6.1 Example: An instantaneous output of 0s and 1s on a GPIO port

Solution 1: using 32-bit (word) accessible fast GPIO registers

FIO0MASK

FIO0PIN

=

0xFFFF00FF ;

0x0000A500;

Solution 2: using 16-bit (half-word) accessible fast GPIO registers

FIO0MASKL

FIO0PINL

=

0x00FF;

0xA500;

Solution 3: using 8-bit (byte) accessible fast GPIO registers

FIO0PIN1

= 0xA5;

6.2 Writing to FIOSET/FIOCLR vs. FIOPIN

Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output

pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used,

only pin/bit(s) written with 1 will be changed, while those written as 0 will remain

unaffected.

Writing to the FIOPIN register enables instantaneous output of a desired value on the

parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs

on that port: zeroes in the value will produce low level pin outputs and ones in the value

will produce high level pin outputs.

A subset of a port’s pins may be changed by using the FIOMASK register to define which

pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that

will be changed, and ones for all others. Solution 2 from Section 9–6.1 above illustrates

output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as

they were before.

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Chapter 10: LPC17xx Ethernet

Rev. 01 — 4 January 2010

User manual

1. Basic configuration

The Ethernet controller is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCENET.

Remark: On reset, the Ethernet block is disabled (PCENET = 0).

2. Clock: see Table 4–38.

3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes

through the PINMODE registers, see Section 8–5.

4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from

Power-down mode, see Section 4–8.8.

5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

6. Initialization: see Section 10–17.2.

2. Introduction

The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media

Access Controller) designed to provide optimized performance through the use of DMA

hardware acceleration. Features include a generous suite of control registers, half or full

duplex operation, flow control, control frames, hardware acceleration for transmit retry,

receive packet filtering and wake-up on LAN activity. Automatic frame transmission and

reception with Scatter-Gather DMA off-loads many operations from the CPU.

The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix,

it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet

is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be

accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum

bandwidth to the Ethernet function.

The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced

Media Independent Interface) protocol and the on-chip MIIM (Media Independent

Interface Management) serial bus, also referred to as MDIO (Management Data

Input/Output).

Table 123. Ethernet acronyms, abbreviations, and definitions

Acronym or

Abbreviation

Definition

AHB

Advanced High-performance bus

Cyclic Redundancy Check

Direct Memory Access

CRC

DMA

Double-word

FCS

64-bit entity

Frame Check Sequence (CRC)

Fragment

A (part of an) Ethernet frame; one or multiple fragments can add up to a single

Ethernet frame.

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Table 123. Ethernet acronyms, abbreviations, and definitions

Acronym or Definition

Abbreviation

Frame

An Ethernet frame consists of destination address, source address, length

type field, payload and frame check sequence.

Half-word

LAN

16-bit entity

Local Area Network

MAC

Media Access Control sublayer

Media Independent Interface

MII management

MII

MIIM

Octet

Packet

An 8-bit data entity, used in lieu of "byte" by IEEE 802.3

A frame that is transported across Ethernet; a packet consists of a preamble,

a start of frame delimiter and an Ethernet frame.

PHY

RMII

Rx

Ethernet Physical Layer

Reduced MII

Receive

TCP/IP

Transmission Control Protocol / Internet Protocol. The most common

high-level protocol used with Ethernet.

Tx

Transmit

VLAN

WoL

Word

Virtual LAN

Wake-up on LAN

32-bit entity

3. Features

• Ethernet standards support:

– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

– Flexible transmit and receive frame options.

– VLAN frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and prefetching.

• Enhanced Ethernet features:

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic FCS insertion (CRC) for transmit.

– Selectable automatic transmit frame padding.

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– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision backoff and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through a standard Reduced MII (RMII) interface.

– PHY register access is available via the Media Independent Interface Management

(MIIM) interface.

4. Architecture and operation

Figure 10–16 shows the internal architecture of the Ethernet block.

TRANSMIT

HOST

FLOW

REGISTERS

CONTROL

register

interface (AHB

slave)

TRANSMIT

DMA

TRANSMIT

RETRY

RMII

MIIM

DMA interface

(AHB master)

RECEIVE

DMA

RECEIVE

BUFFER

RECEIVE

FILTER

ETHERNET

BLOCK

Fig 16. Ethernet block diagram

The block diagram for the Ethernet block consists of:

• The host registers module containing the registers in the software view and handling

AHB accesses to the Ethernet block. The host registers connect to the transmit and

receive data path as well as the MAC.

• The DMA to AHB interface. This provides an AHB master connection that allows the

Ethernet block to access on-chip SRAM for reading of descriptors, writing of status,

and reading and writing data buffers.

• The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.

• The transmit data path, including:

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– The transmit DMA manager which reads descriptors and data from memory and

writes status to memory.

– The transmit retry module handling Ethernet retry and abort situations.

– The transmit flow control module which can insert Ethernet pause frames.

• The receive data path, including:

– The receive DMA manager which reads descriptors from memory and writes data

and status to memory.

– The Ethernet MAC which detects frame types by parsing part of the frame header.

– The receive filter which can filter out certain Ethernet frames by applying different

filtering schemes.

– The receive buffer implementing a delay for receive frames to allow the filter to

filter out certain frames before storing them to memory.

5. DMA engine functions

The Ethernet block is designed to provide optimized performance via DMA hardware

acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load

many data transfers from the CPU.

Descriptors, which are stored in memory, contain information about fragments of incoming

or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller

amount of data. Each descriptor contains a pointer to a memory buffer that holds data

associated with a fragment, the size of the fragment buffer, and details of how the

fragment will be transmitted or received.

Descriptors are stored in arrays in memory, which are located by pointer registers in the

Ethernet block. Other registers determine the size of the arrays, point to the next

descriptor in each array that will be used by the DMA engine, and point to the next

descriptor in each array that will be used by the Ethernet device driver.

6. Overview of DMA operation

The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array

in memory. All or part of an Ethernet frame may be contained in a memory buffer

associated with a descriptor. When transmitting, the transmit DMA engine uses as many

descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and

sends them out in sequence. When receiving, the receive DMA engine also uses as many

descriptors as needed (one or more) to find places to store (scatter) all of the data in the

received frame.

The base address registers for the descriptor array, registers indicating the number of

descriptor array entries, and descriptor array input/output pointers are contained in the

Ethernet block. The descriptor entries and all transmit and receive packet data are stored

in memory which is not a part of the Ethernet block. The descriptor entries tell where

related frame data is stored in memory, certain aspects of how the data is handled, and

the result status of each Ethernet transaction.

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Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved

to memory, causes fragment related status to be saved, and advances the hardware

receive pointer for incoming data. Driver software must handle the disposition of received

data, changing of descriptor data addresses (to avoid unnecessary data movement), and

advancing the software receive pointer. The two pointers create a circular queue in the

descriptor array and allow both the DMA hardware and the driver software to know which

descriptors (if any) are available for their use, including whether the descriptor array is

empty or full.

Similarly, driver software must set up pointers to data that will be transmitted by the

Ethernet MAC, giving instructions for each fragment of data, and advancing the software

transmit pointer for outgoing data. Hardware in the DMA engine reads this information and

sends the data to the Ethernet MAC interface when possible, updating the status and

advancing the hardware transmit pointer.

7. Ethernet Packet

Figure 10–17 illustrates the different fields in an Ethernet packet.

ethernet packet

PREAMBLE

7 bytes

ETHERNET FRAME

start-of-frame

delimiter

1 byte

DESTINATION

ADDRESS

SOURCE

ADDRESS

OPTIONAL LEN

PAYLOAD

FCS

VLAN

TYPE

DesA

oct6

DesA

oct5

DesA

oct4

DesA

oct3

DesA

oct2

DesA

oct1

SrcA

oct6

SrcA

oct5

SrcA

oct4

SrcA

oct3

SrcA

oct2

SrcA

oct1

LSB

oct(0) oct(1) oct(2) oct(3) oct(4) oct(5)

MSB

oct(6) oct(7)

time

Fig 17. Ethernet packet fields

A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame.

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The Ethernet frame consists of the destination address, the source address, an optional

VLAN field, the length/type field, the payload and the frame check sequence.

Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred

starting with the least significant bit.

8. Overview

8.1 Partitioning

The Ethernet block and associated device driver software offer the functionality of the

Media Access Control (MAC) sublayer of the data link layer in the OSI reference model

(see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving

frames to the next higher protocol level, the MAC client layer, typically the Logical Link

Control sublayer. The device driver software implements the interface to the MAC client

layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to

frames in memory and receives results back from the Ethernet block through interrupts.

When a frame is transmitted, the software partially sets up the Ethernet frames by

providing pointers to the destination address field, source address field, the length/type

field, the MAC client data field and optionally the CRC in the frame check sequence field.

Preferably concatenation of frame fields should be done by using the scatter/gather

functionality of the Ethernet core to avoid unnecessary copying of data. The hardware

adds the preamble and start frame delimiter fields and can optionally add the CRC, if

requested by software. When a packet is received the hardware strips the preamble and

start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device

driver, including destination address, source address, length/type field, MAC client data

and frame check sequence (FCS).

Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that

control receive and transmit data streams between the MAC and the AHB interface.

Frames are passed via descriptor arrays located in host memory, so that the hardware

can process many frames without software/CPU support. Frames can consist of multiple

fragments that are accessed with scatter/gather DMA. The DMA managers optimize

memory bandwidth using prefetching and buffering.

A receive filter block is used to identify received frames that are not addressed to this

Ethernet station, so that they can be discarded. The Rx filters include a perfect address

filter and a hash filter.

Wake-on-LAN power management support makes it possible to wake the system up from

a power-down state -a state in which some of the clocks are switched off -when wake-up

frames are received over the LAN. Wake-up frames are recognized by the receive filtering

modules or by a Magic Frame detection technology. System wake-up occurs by triggering

an interrupt.

An interrupt logic block raises and masks interrupts and keeps track of the cause of

interrupts. The interrupt block sends an interrupt request signal to the host system.

Interrupts can be enabled, cleared and set by software.

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Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.

Receive flow control frames are automatically handled by the MAC. Transmit flow control

frames can be initiated by software. In half duplex mode, the flow control module will

generate back pressure by sending out continuous preamble only, interrupted by pauses

to prevent the jabber limit from being exceeded.

The Ethernet block has a standard Reduced Media Independent Interface (RMII) to

connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the

AHB interface through the serial management connection of the MIIM bus, typically

operating at 2.5 MHz.

8.2 Example PHY Devices

Some examples of compatible PHY devices are shown in Table 10–124.

Table 124. Example PHY Devices

Manufacturer

Broadcom

ICS

Part Number(s)

BCM5221

ICS1893

Intel

LXT971A

LSI Logic

Micrel

L80223, L80225, L80227

KS8721

National

SMSC

DP83847, DP83846, DP83843

LAN83C185

9. Pin description

Table 10–125 shows the signals used for connecting the Reduced Media Independent

Interface (RMII) to the external PHY.

Table 125. Ethernet RMII pin descriptions

Pin Name

Type

Output

Input

Pin Description

ENET_TX_EN

ENET_TXD[1:0]

ENET_RXD[1:0]

ENET_RX_ER

ENET_CRS

Transmit data enable

Transmit data, 2 bits

Receive data, 2 bits.

Receive error.

Input

Carrier sense/data valid.

Reference clock

ENET_REF_CLK/ Input

ENET_RX_CLK

Table 10–126 shows the signals used for Media Independent Interface Management

(MIIM) of the external PHY.

Table 126. Ethernet MIIM pin descriptions

Pin Name

Type

Pin Description

MIIM clock.

ENET_MDC

ENET_MDIO

Output

Input/Output

MI data input and output

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10. Registers and software interface

The software interface of the Ethernet block consists of a register view and the format

definitions for the transmit and receive descriptors. These two aspects are addressed in

the next two subsections.

10.1 Register map

Table 10–127 lists the registers, register addresses and other basic information. The total

AHB address space required is 4 kilobytes.

After a hard reset or a soft reset via the RegReset bit of the Command register all bits in

all registers are reset to 0 unless stated otherwise in the following register descriptions.

Some registers will have unused bits which will return a 0 on a read via the AHB interface.

Writing to unused register bits of an otherwise writable register will not have side effects.

The register map consists of registers in the Ethernet MAC and registers around the core

for controlling DMA transfers, flow control and filtering.

Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to

reserved addresses or reserved bits has no effect.

Reading of write-only registers will return a read error on the AHB interface. Writing of

read-only registers will return a write error on the AHB interface.

Table 127. Ethernet register definitions

Name

Description

Access Reset Value Address

MAC registers

MAC1

MAC configuration register 1.

MAC configuration register 2.

Back-to-Back Inter-Packet-Gap register.

Non Back-to-Back Inter-Packet-Gap register.

Collision window / Retry register.

Maximum Frame register.

R/W

WO

RO

0x8000

0x5000 0000

0x5000 0004

0x5000 0008

0x5000 000C

0x5000 0010

0x5000 0014

0x5000 0018

0x5000 001C

0x5000 0020

0x5000 0024

0x5000 0028

0x5000 002C

0x5000 0030

0x5000 0034

0x5000 0040

0x5000 0044

0x5000 0048

MAC2

0

IPGT

0

IPGR

0

CLRT

0x370F

MAXF

0x0600

SUPP

PHY Support register.

0

TEST

Test register.

MCFG

MCMD

MADR

MWTD

MRDD

MIND

MII Mgmt Configuration register.

MII Mgmt Command register.

MII Mgmt Address register.

MII Mgmt Write Data register.

MII Mgmt Read Data register.

MII Mgmt Indicators register.

Station Address 0 register.

Station Address 1 register.

Station Address 2 register.

RO

SA0

R/W

SA1

SA2

Control registers

Command

Command register.

R/W

0

0x5000 0100

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Table 127. Ethernet register definitions

Name

Description

Access Reset Value Address

Status

Status register.

RO

0

0x5000 0104

0x5000 0108

0x5000 010C

0x5000 0110

0x5000 0114

0x5000 0118

0x5000 011C

0x5000 0120

0x5000 0124

0x5000 0128

0x5000 012C

0x5000 0158

0x5000 015C

0x5000 0160

0x5000 0170

0x5000 0174

RxDescriptor

RxStatus

Receive descriptor base address register.

Receive status base address register.

Receive number of descriptors register.

Receive produce index register.

Receive consume index register.

Transmit descriptor base address register.

Transmit status base address register.

Transmit number of descriptors register.

Transmit produce index register.

Transmit consume index register.

Transmit status vector 0 register.

Transmit status vector 1 register.

Receive status vector register.

Flow control counter register.

R/W

RO

RxDescriptorNumber

RxProduceIndex

RxConsumeIndex

TxDescriptor

TxStatus

R/W

RO

TxDescriptorNumber

TxProduceIndex

TxConsumeIndex

TSV0

RO

TSV1

RO

RSV

RO

FlowControlCounter

FlowControlStatus

Rx filter registers

RxFliterCtrl

R/W

RO

Flow control status register.

Receive filter control register.

Receive filter WoL status register.

Receive filter WoL clear register.

Hash filter table LSBs register.

Hash filter table MSBs register.

0

0x5000 0200

0x5000 0204

0x5000 0208

0x5000 0210

0x5000 0214

RxFilterWoLStatus

RxFilterWoLClear

HashFilterL

HashFilterH

Module control registers

IntStatus

Interrupt status register.

Interrupt enable register.

Interrupt clear register.

Interrupt set register.

Power-down register.

RO

0

0x5000 0FE0

0x5000 0FE4

0x5000 0FE8

0x5000 0FEC

0x5000 0FF4

IntEnable

R/W

WO

R/W

IntClear

IntSet

PowerDown

The third column in the table lists the accessibility of the register: read-only, write-only,

read/write.

All AHB register write transactions except for accesses to the interrupt registers are

posted i.e. the AHB transaction will complete before write data is actually committed to the

register. Accesses to the interrupt registers will only be completed by accepting the write

data when the data has been committed to the register.

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11. Ethernet MAC register definitions

This section defines the bits in the individual registers of the Ethernet block register map.

11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000)

The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit

definition is shown in Table 10–128.

Table 128. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description

Bit

Symbol

Function

Reset

value

0

RECEIVE ENABLE

Set this to allow receive frames to be received. Internally the MAC synchronizes

this control bit to the incoming receive stream.

0

1

PASS ALL RECEIVE When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal

FRAMES vs. Control). When disabled, the MAC does not pass valid Control frames.

2

RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control

frames. When disabled, received PAUSE Flow Control frames are ignored.

3

TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be

transmitted. When disabled, Flow Control frames are blocked.

4

LOOPBACK

Setting this bit will cause the MAC Transmit interface to be looped back to the MAC

Receive interface. Clearing this bit results in normal operation.

7:5

8

-

Unused

0x0

0

RESET TX

Setting this bit will put the Transmit Function logic in reset.

9

RESET MCS / TX

Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic

implements flow control.

0

10

11

RESET RX

Setting this bit will put the Ethernet receive logic in reset.

0

RESET MCS / RX

Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic

implements flow control.

0x0

13:12

14

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

0x0

0

SIMULATION RESET Setting this bit will cause a reset to the random number generator within the

Transmit Function.

15

SOFT RESET

Setting this bit will put all modules within the MAC in reset except the Host

Interface.

1

31:16

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

0x0

11.2 MAC Configuration Register 2 (MAC2 - 0x5000 0004)

The MAC configuration register 2 (MAC2) has an address of 0x5000 0004. Its bit

definition is shown in Table 10–129.

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Table 129. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description

Bit

Symbol

Function

Reset

value

0

FULL-DUPLEX

When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled,

the MAC operates in Half-Duplex mode.

0

1

FRAME LENGTH

CHECKING

When enabled (set to ’1’), both transmit and receive frame lengths are compared to

the Length/Type field. If the Length/Type field represents a length then the check is

performed. Mismatches are reported in the StatusInfo word for each received frame.

0

2

3

HUGE FRAME

ENABLE

When enabled (set to ’1’), frames of any length are transmitted and received.

0

DELAYED CRC

This bit determines the number of bytes, if any, of proprietary header information

that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored

by the CRC function) are added. When 0, there is no proprietary header.

4

5

CRC ENABLE

Set this bit to append a CRC to every frame whether padding was required or not.

Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the

MAC contain a CRC.

0

PAD / CRC ENABLE Set this bit to have the MAC pad all short frames. Clear this bit if frames presented

to the MAC have a valid length. This bit is used in conjunction with AUTO PAD

ENABLE and VLAN PAD ENABLE. See Table 10–131 - Pad Operation for details on

the pad function.

6

7

VLAN PAD ENABLE Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid

CRC. Consult Table 10–131 - Pad Operation for more information on the various

padding features.

0

Note: This bit is ignored if PAD / CRC ENABLE is cleared.

AUTO DETECT PAD Set this bit to cause the MAC to automatically detect the type of frame, either tagged

ENABLE

or un-tagged, by comparing the two octets following the source address with

0x8100 (VLAN Protocol ID) and pad accordingly. Table 10–131 - Pad Operation

provides a description of the pad function based on the configuration of this register.

Note: This bit is ignored if PAD / CRC ENABLE is cleared.

8

9

PURE PREAMBLE

ENFORCEMENT

When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure

it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded.

When disabled, no preamble checking is performed.

0

LONG PREAMBLE

ENFORCEMENT

When enabled (set to ’1’), the MAC only allows receive packets which contain

preamble fields less than 12 bytes in length. When disabled, the MAC allows any

length preamble as per the Standard.

11:10

12

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

0x0

0

NO BACKOFF

When enabled (set to ’1’), the MAC will immediately retransmit following a collision

rather than using the Binary Exponential Backoff algorithm as specified in the

Standard.

13

BACK PRESSURE / When enabled (set to ’1’), after the MAC incidentally causes a collision during back

0

NO BACKOFF

pressure, it will immediately retransmit without backoff, reducing the chance of

further collisions and ensuring transmit packets get sent.

14

EXCESS DEFER

When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the

Standard. When disabled, the MAC will abort when the excessive deferral limit is

reached.

0

31:15

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

0x0

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Table 130. Pad operation

Type Auto detect VLAN pad

pad enable enable

Pad/CRC

enable

Action

MAC2 [7]

MAC2 [6]

MAC2 [5]

Any

x

0

x

1

x

0

1

0

1

No pad or CRC check

Pad to 60 bytes, append CRC

Pad to 64 bytes, append CRC

If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to

64 bytes and append CRC.

11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008)

The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0x5000 0008. Its

bit definition is shown in Table 10–131.

Table 131. Back-to-back Inter-packet-gap register (IPGT - address 0x5000 0008) bit description

Bit

Symbol

Function

Reset

value

6:0

BACK-TO-BACK

INTER-PACKET-GAP

This is a programmable field representing the nibble time offset of the minimum

possible period between the end of any transmitted packet to the beginning of the

next. In Full-Duplex mode, the register value should be the desired period in

nibble times minus 3. In Half-Duplex mode, the register value should be the

desired period in nibble times minus 6. In Full-Duplex the recommended setting is

0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or

9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),

which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs

(in 10 Mbps mode).

0x0

31:7

-

Reserved. User software should not write ones to reserved bits. The value read 0x0

from a reserved bit is not defined.

11.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C)

The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of 0x5000 000C.

Its bit definition is shown in Table 10–132.

Table 132. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description

Bit

Symbol

Function

Reset

value

6:0

NON-BACK-TO-BACK

INTER-PACKET-GAP PART2

This is a programmable field representing the Non-Back-to-Back

Inter-Packet-Gap. The recommended value is 0x12 (18d), which

represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in

10 Mbps mode).

0x0

7

-

Reserved. User software should not write ones to reserved bits. The value 0x0

read from a reserved bit is not defined.

14:8 NON-BACK-TO-BACK

INTER-PACKET-GAP PART1

This is a programmable field representing the optional carrierSense

window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is

detected during the timing of IPGR1, the MAC defers to carrier. If,

however, carrier becomes active after IPGR1, the MAC continues timing

IPGR2 and transmits, knowingly causing a collision, thus ensuring fair

access to medium. Its range of values is 0x0 to IPGR2. The recommended

value is 0xC (12d)

0x0

31:15 -

Reserved. User software should not write ones to reserved bits. The value 0x0

read from a reserved bit is not defined.

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11.5 Collision Window / Retry Register (CLRT - 0x5000 0010)

The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit

definition is shown in Table 10–133.

Table 133. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description

Bit

Symbol

Function

Reset

value

3:0

RETRANSMISSION This is a programmable field specifying the number of retransmission attempts

0xF

MAXIMUM

-

following a collision before aborting the packet due to excessive collisions. The

Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.

7:4

Reserved. User software should not write ones to reserved bits. The value read from 0x0

a reserved bit is not defined.

13:8

COLLISION

WINDOW

This is a programmable field representing the slot time or collision window during

which collisions occur in properly configured networks. The default value of 0x37

(55d) represents a 56 byte window following the preamble and SFD.

0x37

31:14

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

11.6 Maximum Frame Register (MAXF - 0x5000 0014)

The Maximum Frame register (MAXF) has an address of 0x5000 0014. Its bit definition is

shown in Table 10–134.

Table 134. Maximum Frame register (MAXF - address 0x5000 0014) bit description

Bit

Symbol

Function

Reset

value

15:0

MAXIMUM FRAME This field resets to the value 0x0600, which represents a maximum receive frame of 0x0600

LENGTH

1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged

frame adds four octets for a total of 1522 octets. If a shorter maximum length

restriction is desired, program this 16-bit field.

31:16

-

Unused

0x0

11.7 PHY Support Register (SUPP - 0x5000 0018)

The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register

provides additional control over the RMII interface. The bit definition of this register is

shown in Table 10–135.

Table 135. PHY Support register (SUPP - address 0x5000 0018) bit description

Bit

Symbol

Function

Reset

value

7:0

8

-

Unused

0x0

0

SPEED

This bit configures the Reduced MII logic for the current operating speed. When set,

100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.

31:9

-

Unused

0x0

Unused bits in the PHY support register should be left as zeroes.

11.8 Test Register (TEST - 0x5000 001C)

The Test register (TEST) has an address of 0x5000 001C. The bit definition of this register

is shown in Table 10–136. These bits are used for testing purposes only.

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Table 136. Test register (TEST - address 0x5000 ) bit description

Bit

Symbol

Function

Reset

value

0

SHORTCUT PAUSE This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.

QUANTA

0

1

TEST PAUSE

This bit causes the MAC Control sublayer to inhibit transmissions, just as if a

PAUSE Receive Control frame with a nonzero pause time parameter was received.

2

TEST

BACKPRESSURE

Setting this bit will cause the MAC to assert backpressure on the link. Backpressure

causes preamble to be transmitted, raising carrier sense. A transmit packet from the

system will be sent during backpressure.

31:3

-

Unused

0x0

11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020)

The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit

definition of this register is shown in Table 10–137.

Table 137. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description

Bit

Symbol

Function

Reset

value

0

SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a

range of PHYs. When set, the MII Management hardware will perform read cycles

from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow

continuous reads of the same PHY.

0

1

SUPPRESS

PREAMBLE

Set this bit to cause the MII Management hardware to perform read/write cycles

without the 32-bit preamble field. Clear this bit to cause normal cycles to be

performed. Some PHYs support suppressed preamble.

0

5:2

CLOCK SELECT

This field is used by the clock divide logic in creating the MII Management Clock

(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs

support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided

by the specified amount. Refer to Table 10–138 below for the definition of values for

this field.

14:6

15

-

Unused

0x0

0

RESET MII MGMT

-

This bit resets the MII Management hardware.

Unused

31:16

0x0

Table 138. Clock select encoding

Clock Select

Bit 5

Bit 4

Bit 3

Bit 2

Maximum AHB

clock supported

Host Clock divided by 4

Host Clock divided by 6

Host Clock divided by 8

Host Clock divided by 10

Host Clock divided by 14

Host Clock divided by 20

Host Clock divided by 28

Host Clock divided by 36

Host Clock divided by 40

Host Clock divided by 44

0

1

0

1

0

1

0

1

0

1

x

0

1

0

1

0

1

0

1

0

10

15

20

25

35

50

70

80^[1]

90^[1]

100^[1]

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Table 138. Clock select encoding

Clock Select

Bit 5

Bit 4

Bit 3

Bit 2

Maximum AHB

clock supported

Host Clock divided by 48

Host Clock divided by 52

Host Clock divided by 56

Host Clock divided by 60

Host Clock divided by 64

1

0

1

0

1

0

1

0

1

120^[1]

130^[1]

140^[1]

150^[1]

160^[1]

[1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device.

11.10 MII Mgmt Command Register (MCMD - 0x5000 0024)

The MII Mgmt Command register (MCMD) has an address of 0x5000 0024. The bit

definition of this register is shown in Table 10–139.

Table 139. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description

Bit

Symbol Function

Reset

value

0

READ

SCAN

-

This bit causes the MII Management hardware to perform a single Read cycle. The Read data is

returned in Register MRDD (MII Mgmt Read Data).

0

1

This bit causes the MII Management hardware to perform Read cycles continuously. This is

useful for monitoring Link Fail for example.

0

31:2

Unused

0x0

11.11 MII Mgmt Address Register (MADR - 0x5000 0028)

The MII Mgmt Address register (MADR) has an address of 0x5000 0028. The bit definition

of this register is shown in Table 10–140.

Table 140. MII Mgmt Address register (MADR - address 0x5000 0028) bit description

Bit

Symbol

Function

Reset

value

4:0

REGISTER

ADDRESS

This field represents the 5-bit Register Address field of Mgmt 0x0

cycles. Up to 32 registers can be accessed.

7:5

-

Unused

0x0

12:8

PHY ADDRESS This field represents the 5-bit PHY Address field of Mgmt

cycles. Up to 31 PHYs can be addressed (0 is reserved).

31:13

-

Unused

0x0

11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C)

The MII Mgmt Write Data register (MWTD) is a write-only register with an address of

0x5000 002C. The bit definition of this register is shown in Table 10–141.

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Table 141. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description

Bit

Symbol

Function

Reset

value

15:0

WRITE

DATA

When written, an MII Mgmt write cycle is performed using the 16-bit 0x0

data and the pre-configured PHY and Register addresses from the

MII Mgmt Address register (MADR).

31:16

-

Unused

0x0

11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030)

The MII Mgmt Read Data register (MRDD) is a read-only register with an address of

0x5000 0030. The bit definition of this register is shown in Table 10–142.

Table 142. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description

Bit

Symbol Function

Reset

value

15:0

31:16

READ

DATA

Following an MII Mgmt Read Cycle, the 16-bit data can be read from

this location.

0x0

-

Unused

0x0

11.14 MII Mgmt Indicators Register (MIND - 0x5000 0034)

The MII Mgmt Indicators register (MIND) is a read-only register with an address of

0x5000 0034. The bit definition of this register is shown in Table 10–143.

Table 143. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description

Bit

Symbol

Function

Reset

value

0

BUSY

When ’1’ is returned - indicates MII Mgmt is currently performing an

MII Mgmt Read or Write cycle.

0

1

SCANNING When ’1’ is returned - indicates a scan operation (continuous MII

Mgmt Read cycles) is in progress.

0

2

NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not

completed and the Read Data is not yet valid.

0

3

MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has

occurred.

0

31:4

-

Unused

0x0

Here are two examples to access PHY via the MII Management Controller.

For PHY Write if scan is not used:

1. Write 0 to MCMD

2. Write PHY address and register address to MADR

3. Write data to MWTD

4. Wait for busy bit to be cleared in MIND

For PHY Read if scan is not used:

1. Write 1 to MCMD

2. Write PHY address and register address to MADR

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3. Wait for busy bit to be cleared in MIND

4. Write 0 to MCMD

5. Read data from MRDD

11.15 Station Address 0 Register (SA0 - 0x5000 0040)

The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of

this register is shown in Table 10–144.

Table 144. Station Address register (SA0 - address 0x5000 0040) bit description

Bit

Symbol

Function

Reset

value

7:0

STATION ADDRESS, This field holds the second octet of the station address.

2nd octet

0x0

15:8

31:16

STATION ADDRESS, This field holds the first octet of the station address.

1st octet

-

Unused

The station address is used for perfect address filtering and for sending pause control

frames. For the ordering of the octets in the packet please refer to Figure 10–17.

11.16 Station Address 1 Register (SA1 - 0x5000 0044)

The Station Address 1 register (SA1) has an address of 0x5000 0044. The bit definition of

this register is shown in Table 10–145.

Table 145. Station Address register (SA1 - address 0x5000 0044) bit description

Bit

Symbol

Function

Reset

value

7:0

STATION ADDRESS, This field holds the fourth octet of the station address.

4th octet

0x0

15:8

31:16

STATION ADDRESS, This field holds the third octet of the station address.

3rd octet

-

Unused

The station address is used for perfect address filtering and for sending pause control

frames. For the ordering of the octets in the packet please refer to Figure 10–17.

11.17 Station Address 2 Register (SA2 - 0x5000 0048)

The Station Address 2 register (SA2) has an address of 0x5000 0048. The bit definition of

this register is shown in Table 10–146.

Table 146. Station Address register (SA2 - address 0x5000 0048) bit description

Bit

Symbol

Function

Reset

value

7:0

STATION ADDRESS, This field holds the sixth octet of the station address.

6th octet

0x0

15:8

31:16

STATION ADDRESS, This field holds the fifth octet of the station address.

5th octet

-

Unused

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The station address is used for perfect address filtering and for sending pause control

frames. For the ordering of the octets in the packet please refer to Figure 10–17.

12. Control register definitions

12.1 Command Register (Command - 0x5000 0100)

The Command register (Command) register has an address of 0x5000 0100. Its bit

definition is shown in Table 10–147.

Table 147. Command register (Command - address 0x5000 0100) bit description

Bit

Symbol

Function

Reset

value

0

1

2

3

RxEnable

TxEnable

-

Enable receive.

Enable transmit.

Unused

0

0x0

0

RegReset

When a ’1’ is written, all datapaths and the host registers are

reset. The MAC needs to be reset separately.

4

5

6

TxReset

RxReset

When a ’1’ is written, the transmit datapath is reset.

When a ’1’ is written, the receive datapath is reset.

0

PassRuntFrame When set to ’1’, passes runt frames smaller than 64 bytes to

memory unless they have a CRC error. If ’0’ runt frames are

filtered out.

7

8

9

PassRxFilter

TxFlowControl

RMII

When set to ’1’, disables receive filtering i.e. all frames

received are written to memory.

0

Enable IEEE 802.3 / clause 31 flow control sending pause

frames in full duplex and continuous preamble in half duplex.

When set to “1”, RMII mode is selected. This bit must be set to

one during Ethernet initialization. See Section 10–17.2.

10

FullDuplex

-

When set to “1”, indicates full duplex operation.

Unused

0

31:11

0x0

All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0.

12.2 Status Register (Status - 0x5000 0104)

The Status register (Status) is a read-only register with an address of 0x5000 0104. Its bit

definition is shown in Table 10–148.

Table 148. Status register (Status - address 0x5000 0104) bit description

Bit

Symbol Function

Reset

value

0

RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive.

0

1

TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0

Unused 0x0

31:2

-

The values represent the status of the two channels/data paths. When the status is 1, the

channel is active, meaning:

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• It is enabled and the Rx/TxEnable bit is set in the Command register or it just got

disabled while still transmitting or receiving a frame.

• Also, for the transmit channel, the transmit queue is not empty

i.e. ProduceIndex != ConsumeIndex.

• Also, for the receive channel, the receive queue is not full

i.e. ProduceIndex != ConsumeIndex - 1.

The status transitions from active to inactive if the channel is disabled by a software reset

of the Rx/TxEnable bit in the Command register and the channel has committed the status

and data of the current frame to memory. The status also transitions to inactive if the

transmit queue is empty or if the receive queue is full and status and data have been

committed to memory.

12.3 Receive Descriptor Base Address Register (RxDescriptor -

0x5000 0108)

The Receive Descriptor base address register (RxDescriptor) has an address of

0x5000 0108. Its bit definition is shown in Table 10–149.

Table 149. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108)

bit description

Bit

Symbol

Function

Reset

value

1:0

-

Fixed to ’00’

-

31:2 RxDescriptor

MSBs of receive descriptor base address.

0x0

The receive descriptor base address is a byte address aligned to a word boundary i.e.

LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of

descriptors.

12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C)

The receive descriptor base address is a byte address aligned to a word boundary i.e.

LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of

descriptors.

Table 150. receive Status Base Address register (RxStatus - address 0x5000 010C) bit

description

Bit

Symbol

Function

Reset

value

2:0

-

Fixed to ’000’

-

31:3 RxStatus

MSBs of receive status base address.

0x0

The receive status base address is a byte address aligned to a double word boundary i.e.

LSB 2:0 are fixed to “000”.

12.5 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110)

The Receive Number of Descriptors register (RxDescriptorNumber) has an address of

0x5000 0110. Its bit definition is shown in Table 10–151.

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Table 151. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit

description

Bit

Symbol

Function

Reset

value

15:0

RxDescriptorNumber

Number of descriptors in the descriptor array for which 0x0

RxDescriptor is the base address. The number of

descriptors is minus one encoded.

31:16

-

Unused

0x0

The receive number of descriptors register defines the number of descriptors in the

descriptor array for which RxDescriptor is the base address. The number of descriptors

should match the number of statuses. The register uses minus one encoding i.e. if the

array has 8 elements, the value in the register should be 7.

12.6 Receive Produce Index Register (RxProduceIndex - 0x5000 0114)

The Receive Produce Index register (RxProduceIndex) is a read-only register with an

address of 0x5000 0114. Its bit definition is shown in Table 10–152.

Table 152. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit

description

Bit

Symbol

Function

Reset

value

15:0

31:16

RxProduceIndex Index of the descriptor that is going to be filled next by the

receive datapath.

0x0

-

Unused

0x0

The receive produce index register defines the descriptor that is going to be filled next by

the hardware receive process. After a frame has been received, hardware increments the

index. The value is wrapped to 0 once the value of RxDescriptorNumber has been

reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any

further frames being received will cause a buffer overrun error.

12.7 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118)

The Receive consume index register (RxConsumeIndex) has an address of 0x5000 0118.

Its bit definition is shown in Table 10–153.

Table 153. Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit

description

Bit

Symbol

Function

Reset

value

15:0

31:16

RxConsumeIndex Index of the descriptor that is going to be processed next by

the receive

-

Unused

0x0

The receive consume register defines the descriptor that is going to be processed next by

the software receive driver. The receive array is empty as long as RxProduceIndex equals

RxConsumeIndex. As soon as the array is not empty, software can process the frame

pointed to by RxConsumeIndex. After a frame has been processed by software, software

should increment the RxConsumeIndex. The value must be wrapped to 0 once the value

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of RxDescriptorNumber has been reached. If the RxProduceIndex equals

RxConsumeIndex - 1, the array is full and any further frames being received will cause a

buffer overrun error.

12.8 Transmit Descriptor Base Address Register (TxDescriptor -

0x5000 011C)

The Transmit Descriptor base address register (TxDescriptor) has an address of

0x5000 011C. Its bit definition is shown in Table 10–154.

Table 154. Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C)

bit description

Bit

Symbol

Function

Reset

value

1:0

-

Fixed to ’00’

-

31:2 TxDescriptor

MSBs of transmit descriptor base address.

0x0

The transmit descriptor base address is a byte address aligned to a word boundary i.e.

LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of

descriptors.

12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120)

The Transmit Status base address register (TxStatus) has an address of 0x5000 0120. Its

bit definition is shown in Table 10–155.

Table 155. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit

description

Bit

Symbol

Function

Reset

value

1:0

-

Fixed to ’00’

-

31:2

TxStatus

MSBs of transmit status base address.

0x0

The transmit status base address is a byte address aligned to a word boundary i.e. LSB

1:0 are fixed to “00”. The register contains the lowest address in the array of statuses.

12.10 Transmit Number of Descriptors Register (TxDescriptorNumber -

0x5000 0124)

The Transmit Number of Descriptors register (TxDescriptorNumber) has an address of

0x5000 0124. Its bit definition is shown in Table 10–156.

Table 156. Transmit Number of Descriptors register (TxDescriptorNumber - address

0x5000 0124) bit description

Bit

Symbol

Function

Reset

value

15:0

TxDescriptorNumber Number of descriptors in the descriptor array for which

TxDescriptor is the base address. The register is minus

one encoded.

31:16

-

Unused

0x0

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The transmit number of descriptors register defines the number of descriptors in the

descriptor array for which TxDescriptor is the base address. The number of descriptors

should match the number of statuses. The register uses minus one encoding i.e. if the

array has 8 elements, the value in the register should be 7.

12.11 Transmit Produce Index Register (TxProduceIndex - 0x5000 0128)

The Transmit Produce Index register (TxProduceIndex) has an address of 0x5000 0128.

Its bit definition is shown in Table 10–157.

Table 157. Transmit Produce Index register (TxProduceIndex - address 0x5000 0128) bit

description

Bit

Symbol

Function

Reset

value

15:0

31:16

TxProduceIndex Index of the descriptor that is going to be filled next by the

transmit software driver.

0x0

-

Unused

0x0

The transmit produce index register defines the descriptor that is going to be filled next by

the software transmit driver. The transmit descriptor array is empty as long as

TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start

transmitting frames as soon as the descriptor array is not empty. After a frame has been

processed by software, it should increment the TxProduceIndex. The value must be

wrapped to 0 once the value of TxDescriptorNumber has been reached. If the

TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software

should stop producing new descriptors until hardware has transmitted some frames and

updated the TxConsumeIndex.

12.12 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C)

The Transmit Consume Index register (TxConsumeIndex) is a read-only register with an

address of 0x5000 012C. Its bit definition is shown in Table 10–158.

Table 158. Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit

description

Bit

Symbol

Function

Reset

value

15:0

31:16

TxConsumeIndex Index of the descriptor that is going to be transmitted next by 0x0

the transmit datapath.

-

Unused

0x0

The transmit consume index register defines the descriptor that is going to be transmitted

next by the hardware transmit process. After a frame has been transmitted hardware

increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has

been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is

empty and the transmit channel will stop transmitting until software produces new

descriptors.

12.13 Transmit Status Vector 0 Register (TSV0 - 0x5000 0158)

The Transmit Status Vector 0 register (TSV0) is a read-only register with an address of

0x5000 0158. The transmit status vector registers store the most recent transmit status

returned by the MAC. Since the status vector consists of more than 4 bytes, status is

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distributed over two registers TSV0 and TSV1. These registers are provided for debug

purposes, because the communication between driver software and the Ethernet block

takes place primarily through the frame descriptors. The status register contents are valid

as long as the internal status of the MAC is valid and should typically only be read when

the transmit and receive processes are halted.

Table 10–159 lists the bit definitions of the TSV0 register.

Table 159. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description

Bit

Symbol

Function

Reset

value

0

CRC error

The attached CRC in the packet did not match the

internally generated CRC.

0

1

Length check error

Indicates the frame length field does not match the actual

number of data items and is not a type field.

2

Length out of range^[1]Indicates that frame type/length field was larger than

1500 bytes.

3

4

5

6

Done

Transmission of packet was completed.

0

Multicast

Broadcast

Packet Defer

Packet’s destination was a multicast address.

Packet’s destination was a broadcast address.

Packet was deferred for at least one attempt, but less than

an excessive defer.

7

8

Excessive Defer

Packet was deferred in excess of 6071 nibble times in

100 Mbps or 24287 bit times in 10 Mbps mode.

0

Excessive Collision

Packet was aborted due to exceeding of maximum allowed

number of collisions.

9

Late Collision

Giant

Collision occurred beyond collision window, 512 bit times.

0

10

Byte count in frame was greater than can be represented

in the transmit byte count field in TSV1.

11

Underrun

Host side caused buffer underrun.

0

27:12 Total bytes

The total number of bytes transferred including collided

attempts.

0x0

28

29

Control frame

Pause

The frame was a control frame.

0

The frame was a control frame with a valid PAUSE

opcode.

30

31

Backpressure

VLAN

Carrier-sense method backpressure was previously

applied.

0

Frame’s length/type field contained 0x8100 which is the

VLAN protocol identifier.

[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or

ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length

out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the

status of the received frame.

12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C)

The Transmit Status Vector 1 register (TSV1) is a read-only register with an address of

0x5000 015C. The transmit status vector registers store the most recent transmit status

returned by the MAC. Since the status vector consists of more than 4 bytes, status is

distributed over two registers TSV0 and TSV1. These registers are provided for debug

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purposes, because the communication between driver software and the Ethernet block

takes place primarily through the frame descriptors. The status register contents are valid

as long as the internal status of the MAC is valid and should typically only be read when

the transmit and receive processes are halted.Table 10–160 lists the bit definitions of the

TSV1 register.

Table 160. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description

Bit

Symbol

Function

Reset

value

15:0

Transmit byte count

The total number of bytes in the frame, not counting the

collided bytes.

0x0

19:16 Transmit collision

count

Number of collisions the current packet incurred during

transmission attempts. The maximum number of collisions

(16) cannot be represented.

0x0

31:20

-

Unused

0x0

12.15 Receive Status Vector Register (RSV - 0x5000 0160)

The Receive status vector register (RSV) is a read-only register with an address of

0x5000 0160. The receive status vector register stores the most recent receive status

returned by the MAC. This register is provided for debug purposes, because the

communication between driver software and the Ethernet block takes place primarily

through the frame descriptors. The status register contents are valid as long as the

internal status of the MAC is valid and should typically only be read when the transmit and

receive processes are halted.

Table 10–161 lists the bit definitions of the RSV register.

Table 161. Receive Status Vector register (RSV - address 0x5000 0160) bit description

Bit

Symbol

Function

Reset

value

15:0

16

Received byte count Indicates length of received frame.

0x0

0

Packet previously

ignored

Indicates that a packet was dropped.

17

18

19

20

21

22

RXDV event

previously seen

Indicates that the last receive event seen was not long

enough to be a valid packet.

0

Carrier event

previously seen

Indicates that at some time since the last receive statistics,

a carrier event was detected.

Receive code

violation

Indicates that received PHY data does not represent a

valid receive code.

CRC error

The attached CRC in the packet did not match the

internally generated CRC.

Length check error

Indicates the frame length field does not match the actual

number of data items and is not a type field.

Length out of range^[1]Indicates that frame type/length field was larger than

1518 bytes.

23

24

25

Receive OK

Multicast

The packet had valid CRC and no symbol errors.

The packet destination was a multicast address.

The packet destination was a broadcast address.

0

Broadcast

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Table 161. Receive Status Vector register (RSV - address 0x5000 0160) bit description

Bit

Symbol

Function

Reset

value

26

Dribble Nibble

Indicates that after the end of packet another 1-7 bits were

received. A single nibble, called dribble nibble, is formed

but not sent out.

0

27

28

Control frame

PAUSE

The frame was a control frame.

0

The frame was a control frame with a valid PAUSE

opcode.

29

30

31

Unsupported Opcode The current frame was recognized as a Control Frame but

contains an unknown opcode.

0

VLAN

Frame’s length/type field contained 0x8100 which is the

VLAN protocol identifier.

0

-

Unused

0x0

[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or

ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length

out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the

status of the received frame.

12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170)

The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170.

Table 10–162 lists the bit definitions of the register.

Table 162. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit

description

Bit

Symbol

Function

Reset

value

15:0

MirrorCounter

In full duplex mode the MirrorCounter specifies the number 0x0

of cycles before re-issuing the Pause control frame.

31:16 PauseTimer

In full-duplex mode the PauseTimer specifies the value

that is inserted into the pause timer field of a pause flow

control frame. In half duplex mode the PauseTimer

specifies the number of backpressure cycles.

0x0

12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174)

The Flow Control Status register (FlowControlStatus) is a read-only register with an

address of 0x5000 8174. Table 10–163 lists the bit definitions of the register.

Table 163. Flow Control Status register (FlowControlStatus - address 0x5000 8174) bit

description

Bit

Symbol

Function

Reset

value

15:0

MirrorCounterCurrent In full duplex mode this register represents the current

value of the datapath’s mirror counter which counts up to

the value specified by the MirrorCounter field in the

FlowControlCounter register. In half duplex mode the

register counts until it reaches the value of the PauseTimer

bits in the FlowControlCounter register.

0x0

31:16

-

Unused

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13. Receive filter register definitions

13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200)

The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200.

Table 10–164 lists the definition of the individual bits in the register.

Table 164. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description

Bit

Symbol

Function

Reset

value

0

1

2

3

AcceptUnicastEn

When set to ’1’, all unicast frames are accepted.

When set to ’1’, all broadcast frames are accepted.

When set to ’1’, all multicast frames are accepted.

0

AcceptBroadcastEn

AcceptMulticastEn

AcceptUnicastHashEn

When set to ’1’, unicast frames that pass the imperfect

hash filter are accepted.

4

5

AcceptMulticastHashEn

AcceptPerfectEn

When set to ’1’, multicast frames that pass the

imperfect hash filter are accepted.

0

When set to ’1’, the frames with a destination address

identical to the

station address are accepted.

11:6

-

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

12

13

MagicPacketEnWoL

RxFilterEnWoL

When set to ’1’, the result of the magic packet filter will

generate a WoL interrupt when there is a match.

0

When set to ’1’, the result of the perfect address

matching filter and the imperfect hash filter will

generate a WoL interrupt when there is a match.

31:14 -

Unused

0x0

13.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204)

The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only

register with an address of 0x5000 0204.

Table 10–165 lists the definition of the individual bits in the register.

Table 165. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit

description

Bit Symbol

Function

Reset

value

0

1

2

3

AcceptUnicastWoL

When the value is ’1’, a unicast frames caused WoL.

When the value is ’1’, a broadcast frame caused WoL.

When the value is ’1’, a multicast frame caused WoL.

0

AcceptBroadcastWoL

AcceptMulticastWoL

AcceptUnicastHashWoL When the value is ’1’, a unicast frame that passes the

imperfect hash filter caused WoL.

4

5

AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the

imperfect hash filter caused WoL.

0

AcceptPerfectWoL

When the value is ’1’, the perfect address matching filter

caused WoL.

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Table 165. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit

description

Bit Symbol

Function

Reset

value

6

7

8

-

Unused

0x0

0

RxFilterWoL

When the value is ’1’, the receive filter caused WoL.

MagicPacketWoL

When the value is ’1’, the magic packet filter caused

WoL.

0

31:9 -

Unused

0x0

The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be

cleared by writing the RxFilterWoLClear register.

13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208)

The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only

register with an address of 0x5000 0208.

Table 10–166 lists the definition of the individual bits in the register.

Table 166. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit

description

Bit Symbol

Function

Reset

value

0

1

2

3

4

5

6

7

8

AcceptUnicastWoLClr

When a ’1’ is written to one of these bits (0 to 5), the

corresponding status bit in the RxFilterWoLStatus

register is cleared.

0

AcceptBroadcastWoLClr

AcceptMulticastWoLClr

AcceptUnicastHashWoLClr

AcceptMulticastHashWoLClr

AcceptPerfectWoLClr

-

0

Unused

0x0

0

RxFilterWoLClr

When a ’1’ is written to one of these bits (7 and/or 8),

the corresponding status bit in the RxFilterWoLStatus

register is cleared.

MagicPacketWoLClr

0

31:9 -

Unused

0x0

The bits in this register are write-only; writing resets the corresponding bits in the

RxFilterWoLStatus register.

13.4 Hash Filter Table LSBs Register (HashFilterL - 0x5000 0210)

The Hash Filter table LSBs register (HashFilterL) has an address of 0x5000 0210.

Table 10–167 lists the bit definitions of the register. Details of Hash filter table use can be

found in Section 10–17.10 “Receive filtering” on page 196.

Table 167. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit

description

Bit

Symbol

Function

Reset

value

31:0

HashFilterL

Bits 31:0 of the imperfect filter hash table for receive

filtering.

0x0

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13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214)

The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214.

Table 10–168 lists the bit definitions of the register. Details of Hash filter table use can be

found in Section 10–17.10 “Receive filtering” on page 196.

Table 168. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description

Bit

Symbol

Function

Reset

value

31:0

HashFilterH

Bits 63:32 of the imperfect filter hash table for receive

filtering.

0x0

14. Module control register definitions

14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0)

The Interrupt Status register (IntStatus) is a read-only register with an address of

0x5000 0FE0. The interrupt status register bit definition is shown in Table 10–169. Note

that all bits are flip-flops with an asynchronous set in order to be able to generate

interrupts if there are wake-up events while clocks are disabled.

Table 169. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description

Bit

Symbol

Function

Reset

value

0

RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The

fatal interrupt should be resolved by a Rx soft-reset. The bit is not

set when there is a nonfatal overrun error.

0

1

2

RxErrorInt

Interrupt trigger on receive errors: AlignmentError, RangeError,

LengthError, SymbolError, CRCError or NoDescriptor or Overrun.

0

RxFinishedInt Interrupt triggered when all receive descriptors have been

processed i.e. on the transition to the situation where

ProduceIndex == ConsumeIndex.

3

4

RxDoneInt

Interrupt triggered when a receive descriptor has been processed

while the Interrupt bit in the Control field of the descriptor was set.

0

TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The

fatal interrupt should be resolved by a Tx soft-reset. The bit is not

set when there is a nonfatal underrun error.

5

6

7

TxErrorInt

Interrupt trigger on transmit errors: LateCollision,

ExcessiveCollision and ExcessiveDefer, NoDescriptor or

Underrun.

0

TxFinishedInt Interrupt triggered when all transmit descriptors have been

processed i.e. on the transition to the situation where

ProduceIndex == ConsumeIndex.

TxDoneInt

Interrupt triggered when a descriptor has been transmitted while

the Interrupt bit in the Control field of the descriptor was set.

11:8

12

-

Unused

0x0

0

SoftInt

Interrupt triggered by software writing a 1 to the SoftintSet bit in

the IntSet register.

13

WakeupInt

-

Interrupt triggered by a Wake-up event detected by the receive

filter.

0

31:14

Unused

0x0

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The interrupt status register is read-only. Setting can be done via the IntSet register. Reset

can be accomplished via the IntClear register.

14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4)

The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt

enable register bit definition is shown in Table 10–170.

Table 170. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description

Bit

Symbol

Function

Reset

value

0

RxOverrunIntEn Enable for interrupt trigger on receive buffer overrun or

descriptor underrun situations.

0

1

2

RxErrorIntEn

Enable for interrupt trigger on receive errors.

0

RxFinishedIntEn Enable for interrupt triggered when all receive descriptors have

been processed i.e. on the transition to the situation where

ProduceIndex == ConsumeIndex.

3

4

RxDoneIntEn

Enable for interrupt triggered when a receive descriptor has

been processed while the Interrupt bit in the Control field of the

descriptor was set.

0

TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor

underrun situations.

5

6

TxErrorIntEn

Enable for interrupt trigger on transmit errors.

0

TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors

have been processed i.e. on the transition to the situation

where ProduceIndex == ConsumeIndex.

7

TxDoneIntEn

Enable for interrupt triggered when a descriptor has been

transmitted while the Interrupt bit in the Control field of the

descriptor was set.

0

11:8

12

-

Unused

0x0

0

SoftIntEn

Enable for interrupt triggered by the SoftInt bit in the IntStatus

register, caused by software writing a 1 to the SoftIntSet bit in

the IntSet register.

13

WakeupIntEn

-

Enable for interrupt triggered by a Wake-up event detected by

the receive filter.

0

31:14

Unused

0x0

14.3 Interrupt Clear Register (IntClear - 0x5000 0FE8)

The Interrupt Clear register (IntClear) is a write-only register with an address of

0x5000 0FE8. The interrupt clear register bit definition is shown in Table 10–171.

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Table 171. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description

Bit

Symbol

Function

Reset

value

0

RxOverrunIntClr

RxErrorIntClr

RxFinishedIntClr

RxDoneIntClr

TxUnderrunIntClr

TxErrorIntClr

TxFinishedIntClr

TxDoneIntClr

-

Writing a ’1’ to one of these bits clears (0 to 7) the

corresponding status bit in interrupt status register

IntStatus.

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

11:8

12

13

Unused

0x0

0

SoftIntClr

Writing a ’1’ to one of these bits (12 and/or 13) clears the

corresponding status bit in interrupt status register

IntStatus.

WakeupIntClr

0

31:14

-

Unused

0x0

The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears

the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.

14.4 Interrupt Set Register (IntSet - 0x5000 0FEC)

The Interrupt Set register (IntSet) is a write-only register with an address of 0x5000 0FEC.

The interrupt set register bit definition is shown in Table 10–172.

Table 172. Interrupt Set register (IntSet - address 0x5000 0FEC) bit description

Bit

Symbol

Function

Reset

value

0

RxOverrunIntSet

RxErrorIntSet

RxFinishedIntSet

RxDoneIntSet

TxUnderrunIntSet

TxErrorIntSet

TxFinishedIntSet

TxDoneIntSet

-

Writing a ’1’ to one of these bits (0 to 7) sets the

corresponding status bit in interrupt status register

IntStatus.

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

11:8

12

13

Unused

0x0

0

SoftIntSet

Writing a ’1’ to one of these bits (12 and/or 13) sets the

corresponding status bit in interrupt status register

IntStatus.

WakeupIntSet

0

31:14

-

Unused

0x0

The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the

corresponding bit in the status register. Writing a 0 will not affect the interrupt status.

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14.5 Power-Down Register (PowerDown - 0x5000 0FF4)

The Power-Down register (PowerDown) is used to block all AHB accesses except

accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The

bit definition of the register is listed in Table 10–173.

Table 173. Power-Down register (PowerDown - address 0x5000 0FF4) bit description

Bit

Symbol

Function

Reset

value

30:0

31

-

Unused

0x0

0

PowerDownMACAHB If true, all AHB accesses will return a read/write error,

except accesses to the Power-Down register.

Setting the bit will return an error on all read and write accesses on the MACAHB interface

except for accesses to the Power-Down register.

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15. Descriptor and status formats

This section defines the descriptor format for the transmit and receive scatter/gather DMA

engines. Each Ethernet frame can consist of one or more fragments. Each fragment

corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for

receive) and gather (for transmit) multiple fragments for a single Ethernet frame.

15.1 Receive descriptors and statuses

Figure 10–18 depicts the layout of the receive descriptors in memory.

RxDescriptor

RxStatus

PACKET

StatusInfo

DATA BUFFER

1

2

3

4

5

CONTROL

PACKET

StatusHashCRC

StatusInfo

CONTROL

PACKET

StatusHashCRC

StatusInfo

DATA BUFFER

CONTROL

PACKET

StatusHashCRC

StatusInfo

CONTROL

PACKET

StatusHashCRC

StatusInfo

DATA BUFFER

CONTROL

StatusHashCRC

PACKET

DATA BUFFER

StatusInfo

RxDescriptorNumber

CONTROL

StatusHashCRC

Fig 18. Receive descriptor memory layout

Receive descriptors are stored in an array in memory. The base address of the array is

stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary.

The number of descriptors in the array is stored in the RxDescriptorNumber register using

a minus one encoding style e.g. if the array has 8 elements the register value should be 7.

Parallel to the descriptors there is an array of statuses. For each element of the descriptor

array there is an associated status field in the status array. The base address of the status

array is stored in the RxStatus register, and must be aligned on an 8 byte address

boundary. During operation (when the receive data path is enabled) the RxDescriptor,

RxStatus and RxDescriptorNumber registers should not be modified.

Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations

that will be used next by hardware and software. Both registers act as counters starting at

0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex

contains the index of the descriptor that is going to be filled with the next frame being

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received. The RxConsumeIndex is programmed by software and is the index of the next

descriptor that the software receive driver is going to process. When RxProduceIndex ==

RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==

RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly

received data would generate an overflow unless the software driver frees up one or more

descriptors.

Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each

status field takes two words (8 bytes) in memory. Each receive descriptor consists of a

pointer to the data buffer for storing receive data (Packet) and a control word (Control).

The Packet field has a zero address offset, the control field has a 4 byte address offset

with respect to the descriptor address as defined in Table 10–174.

Table 174. Receive Descriptor Fields

Symbol

Address Bytes Description

offset

Packet

Control

0x0

0x4

4

Base address of the data buffer for storing receive data.

Control information, see Table 10–175.

The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the

base address of the data buffer. The definition of the control word bits is listed in

Table 10–175.

Table 175. Receive Descriptor Control Word

Bit

Symbol

Description

10:0 Size

Size in bytes of the data buffer. This is the size of the buffer reserved by the

device driver for a frame or frame fragment i.e. the byte size of the buffer

pointed to by the Packet field. The size is -1 encoded e.g. if the buffer is 8

bytes the size field should be equal to 7.

30:11

31

-

Unused

Interrupt

If true generate an RxDone interrupt when the data in this frame or frame

fragment and the associated status information has been committed to

memory.

Table 10–176 lists the fields in the receive status elements from the status array.

Table 176. Receive Status Fields

Symbol

Address Bytes Description

offset

StatusInfo

0x0

4

Receive status return flags, see Table 10–178.

StatusHashCRC 0x4

The concatenation of the destination address hash CRC and

the source address hash CRC.

Each receive status consists of two words. The StatusHashCRC word contains a

concatenation of the two 9-bit hash CRCs calculated from the destination and source

addresses contained in the received frame. After detecting the destination and source

addresses, StatusHashCRC is calculated once, then held for every fragment of the same

frame.

The concatenation of the two CRCs is shown in Table 10–177:

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Table 177. Receive Status HashCRC Word

Bit

Symbol

SAHashCRC Hash CRC calculated from the source address.

Unused

Description

8:0

15:9

-

24:16 DAHashCRC Hash CRC calculated from the destination address.

31:25 - Unused

The StatusInfo word contains flags returned by the MAC and flags generated by the

receive data path reflecting the status of the reception. Table 10–178 lists the bit

definitions in the StatusInfo word.

Table 178. Receive status information word

Bit

Symbol

Description

10:0 RxSize

The size in bytes of the actual data transferred into one fragment buffer. In

other words, this is the size of the frame or fragment as actually written by

the DMA manager for one descriptor. This may be different from the Size

bits of the Control field in the descriptor that indicate the size of the buffer

allocated by the device driver. Size is -1 encoded e.g. if the buffer has

8 bytes the RxSize value will be 7.

17:11 -

Unused

18

ControlFrame Indicates this is a control frame for flow control, either a pause frame or a

frame with an unsupported opcode.

19

20

VLAN

Indicates a VLAN frame.

FailFilter

Indicates this frame has failed the Rx filter. These frames will not normally

pass to memory. But due to the limitation of the size of the buffer, part of

this frame may already be passed to memory. Once the frame is found to

have failed the Rx filter, the remainder of the frame will be discarded

without being passed to the memory. However, if the PassRxFilter bit in

the Command register is set, the whole frame will be passed to memory.

21

22

23

24

25

Multicast

Set when a multicast frame is received.

Broadcast

CRCError

SymbolError

LengthError

Set when a broadcast frame is received.

The received frame had a CRC error.

The PHY reports a bit error over the PHY interface during reception.

The frame length field value in the frame specifies a valid length, but does

not match the actual data length.

26

27

RangeError^[1]The received packet exceeds the maximum packet size.

AlignmentError An alignment error is flagged when dribble bits are detected and also a

CRC error is detected. This is in accordance with IEEE std. 802.3/clause

4.3.2.

28

29

Overrun

Receive overrun. The adapter can not accept the data stream.

NoDescriptor

No new Rx descriptor is available and the frame is too long for the buffer

size in the current receive descriptor.

30

31

LastFlag

Error

When set to 1, indicates this descriptor is for the last fragment of a frame.

If the frame consists of a single fragment, this bit is also set to 1.

An error occurred during reception of this frame. This is a logical OR of

AlignmentError, RangeError, LengthError, SymbolError, CRCError, and

Overrun.

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[1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or

ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"

error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the

received frame.

For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError,

SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise

the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined.

The status of the last fragment in the frame will copy the value for these bits from the

MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and

NoDescriptor bits.

15.2 Transmit descriptors and statuses

Figure 10–19 depicts the layout of the transmit descriptors in memory.

TxDescriptor

TxStatus

PACKET

DATA BUFFER

1

2

3

4

5

StatusInfo

CONTROL

PACKET

CONTROL

PACKET

DATA BUFFER

CONTROL

PACKET

CONTROL

PACKET

DATA BUFFER

CONTROL

PACKET

DATA BUFFER

TxDescriptorNumber

StatusInfo

CONTROL

Fig 19. Transmit descriptor memory layout

Transmit descriptors are stored in an array in memory. The lowest address of the transmit

descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte

address boundary. The number of descriptors in the array is stored in the

TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8

elements the register value should be 7. Parallel to the descriptors there is an array of

statuses. For each element of the descriptor array there is an associated status field in the

status array. The base address of the status array is stored in the TxStatus register, and

must be aligned on a 4 byte address boundary. During operation (when the transmit data

path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should

not be modified.

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Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that

will be used next by hardware and software. Both register act as counters starting at 0 and

wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex

contains the index of the next descriptor that is going to be filled by the software driver.

The TxConsumeIndex contains the index of the next descriptor going to be transmitted by

the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.

When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the

transmit buffer is full and the software driver cannot add new descriptors until the

hardware has transmitted one or more frames to free up descriptors.

Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each

status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a

pointer to the data buffer containing transmit data (Packet) and a control word (Control).

The Packet field has a zero address offset, whereas the control field has a 4 byte address

offset, see Table 10–179.

Table 179. Transmit descriptor fields

Symbol Address offset

Bytes Description

Packet

Control

0x0

0x4

4

Base address of the data buffer containing transmit data.

Control information, see Table 10–180.

The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the

base address of the data buffer. The definition of the control word bits is listed in

Table 10–180.

Table 180. Transmit descriptor control word

Bit

Symbol

Description

10:0 Size

Size in bytes of the data buffer. This is the size of the frame or fragment as it

needs to be fetched by the DMA manager. In most cases it will be equal to the

byte size of the data buffer pointed to by the Packet field of the descriptor. Size

is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7.

25:11

26

-

Unused

Override

Per frame override. If true, bits 30:27 will override the defaults from the MAC

internal registers. If false, bits 30:27 will be ignored and the default values

from the MAC will be used.

27

Huge

If true, enables huge frame, allowing unlimited frame sizes. When false,

prevents transmission of more than the maximum frame length (MAXF[15:0]).

28

29

30

Pad

CRC

Last

If true, pad short frames to 64 bytes.

If true, append a hardware CRC to the frame.

If true, indicates that this is the descriptor for the last fragment in the transmit

frame. If false, the fragment from the next descriptor should be appended.

31

Interrupt

If true, a TxDone interrupt will be generated when the data in this frame or

frame fragment has been sent and the associated status information has been

committed to memory.

Table 10–181 shows the one field transmit status.

Table 181. Transmit status fields

Symbol

Address

offset

Bytes

Description

StatusInfo

0x0

4

Transmit status return flags, see Table 10–182.

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The transmit status consists of one word which is the StatusInfo word. It contains flags

returned by the MAC and flags generated by the transmit data path reflecting the status of

the transmission. Table 10–182 lists the bit definitions in the StatusInfo word.

Table 182. Transmit status information word

Bit

Symbol

Description

20:0

-

Unused

24:21 CollisionCount

The number of collisions this packet incurred, up to the

Retransmission Maximum.

25

26

27

Defer

This packet incurred deferral, because the medium was occupied.

This is not an error unless excessive deferral occurs.

ExcessiveDefer

This packet incurred deferral beyond the maximum deferral limit and

was aborted.

ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was

aborted.

28

29

LateCollision

Underrun

An Out of window Collision was seen, causing packet abort.

A Tx underrun occurred due to the adapter not producing transmit

data.

30

31

NoDescriptor

Error

The transmit stream was interrupted because a descriptor was not

available.

An error occurred during transmission. This is a logical OR of

Underrun, LateCollision, ExcessiveCollision, and ExcessiveDefer.

For multi-fragment frames, the value of the LateCollision, ExcessiveCollision,

ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will

be 0. The status of the last fragment in the frame will copy the value for these bits from the

MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits.

16. Ethernet block functional description

This section defines the functions of the DMA capable 10/100 Ethernet MAC. After

introducing the DMA concepts of the Ethernet block, and a description of the basic

transmit and receive functions, this section elaborates on advanced features such as flow

control, receive filtering, etc.

16.1 Overview

The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet

PHY connected through the RMII interface.

Typically during system start-up, the Ethernet block will be initialized. Software

initialization of the Ethernet block should include initialization of the descriptor and status

arrays as well as the receiver fragment buffers.

Remark: when initializing the Ethernet block, it is important to first configure the PHY and

insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both

ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins

and connected to the EMAC module (selecting the appropriate pins using the PINSEL

registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become

locked and no further functionality will be possible. This will cause JTAG lose

communication with the target, if debug mode is being used.

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To transmit a packet the software driver has to set up the appropriate Control registers

and a descriptor to point to the packet data buffer before transferring the packet to

hardware by incrementing the TxProduceIndex register. After transmission, hardware will

increment TxConsumeIndex and optionally generate an interrupt.

The hardware will receive packets from the PHY and apply filtering as configured by the

software driver. While receiving a packet the hardware will read a descriptor from memory

to find the location of the associated receiver data buffer. Receive data is written in the

data buffer and receive status is returned in the receive descriptor status word. Optionally

an interrupt can be generated to notify software that a packet has been received. Note

that the DMA manager will prefetch and buffer up to three descriptors.

16.2 AHB interface

The registers of the Ethernet block connect to an AHB slave interface to allow access to

the registers from the CPU.

The AHB interface has a 32-bit data path, which supports only word accesses and has an

address aperture of 4 kB. Table 10–127 lists the registers of the Ethernet block.

All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear

and IntEnable registers. AHB write operations are executed in order.

If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses

will return a read or write error except for accesses to the PowerDown register.

Bus Errors

The Ethernet block generates errors for several conditions:

• The AHB interface will return a read error when there is an AHB read access to a

write-only register; likewise a write error is returned when there is an AHB write

access to the read-only register. An AHB read or write error will be returned on AHB

read or write accesses to reserved registers. These errors are propagated back to the

CPU. Registers defined as read-only and write-only are identified in Table 10–127.

• If the PowerDown bit is set all accesses to AHB registers will result in an error

response except for accesses to the PowerDown register.

17. Interrupts

The Ethernet block has a single interrupt request output to the CPU (via the NVIC).

The interrupt service routine must read the IntStatus register to determine the origin of the

interrupt. All interrupt statuses can be set by software writing to the IntSet register;

statuses can be cleared by software writing to the IntClear register.

The transmit and receive data paths can only set interrupt statuses, they cannot clear

statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for

test purposes.

17.1 Direct Memory Access (DMA)

Descriptor arrays

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The Ethernet block includes two DMA managers. The DMA managers make it possible to

transfer frames directly to and from memory with little support from the processor and

without the need to trigger an interrupt for each frame.

The DMA managers work with arrays of frame descriptors and statuses that are stored in

memory. The descriptors and statuses act as an interface between the Ethernet hardware

and the device driver software. There is one descriptor array for receive frames and one

descriptor array for transmit frames. Using buffering for frame descriptors, the memory

traffic and memory bandwidth utilization of descriptors can be kept small.

Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer

containing a frame or a fragment, whereas the second field is a control word related to

that frame or fragment.

The software driver must write the base addresses of the descriptor and status arrays in

the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of

descriptors/statuses in each array must be written in the

TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an

array corresponds to the number of statuses in the associated status array.

Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be

aligned on a 4 byte (32bit)address boundary, while the receive status array must be

aligned on a 8 byte (64bit) address boundary.

Ownership of descriptors

Both device driver software and Ethernet hardware can read and write the descriptor

arrays at the same time in order to produce and consume descriptors. A descriptor is

"owned" either by the device driver or by the Ethernet hardware. Only the owner of a

descriptor reads or writes its value. Typically, the sequence of use and ownership of

descriptors and statuses is as follows: a descriptor is owned and set up by the device

driver; ownership of the descriptor/status is passed by the device driver to the Ethernet

block, which reads the descriptor and writes information to the status field; the Ethernet

block passes ownership of the descriptor back to the device driver, which uses the status

information and then recycles the descriptor to be used for another frame. Software must

pre-allocate the memory used to hold the descriptor arrays.

Software can hand over ownership of descriptors and statuses to the hardware by

incrementing (and wrapping if on the array boundary) the

TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and

status to software by updating the TxConsumeIndex/ RxProduceIndex registers.

After handing over a descriptor to the receive and transmit DMA hardware, device driver

software should not modify the descriptor or reclaim the descriptor by decrementing the

TxProduceIndex/ RxConsumeIndex registers because descriptors may have been

prefetched by the hardware. In this case the device driver software will have to wait until

the frame has been transmitted or the device driver has to soft-reset the transmit and/or

receive data paths which will also reset the descriptor arrays.

Sequential order with wrap-around

When descriptors are read from and statuses are written to the arrays, this is done in

sequential order with wrap-around. Sequential order means that when the Ethernet block

has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is

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the one at the next higher, adjacent memory address. Wrap around means that when the

Ethernet block has finished reading/writing the last descriptor/status of the array (with the

highest memory address), the next descriptor/status it reads/writes is the first

descriptor/status of the array at the base address of the array.

Full and Empty state of descriptor arrays

The descriptor arrays can be empty, partially full or full. A descriptor array is empty when

all descriptors are owned by the producer. A descriptor array is partially full if both

producer and consumer own part of the descriptors and both are busy processing those

descriptors. A descriptor array is full when all descriptors (except one) are owned by the

consumer, so that the producer has no more room to process frames. Ownership of

descriptors is indicated with the use of a consume index and a produce index. The

produce index is the first element of the array owned by the producer. It is also the index

of the array element that is next going to be used by the producer of frames (it may

already be busy using it and subsequent elements). The consume index is the first

element of the array that is owned by the consumer. It is also the number of the array

element next to be consumed by the consumer of frames (it and subsequent elements

may already be in the process of being consumed). If the consume index and the produce

index are equal, the descriptor array is empty and all array elements are owned by the

producer. If the consume index equals the produce index plus one, then the array is full

and all array elements (except the one at the produce index) are owned by the consumer.

With a full descriptor array, still one array element is kept empty, to be able to easily

distinguish the full or empty state by looking at the value of the produce index and

consume index. An array must have at least 2 elements to be able to indicate a full

descriptor array with a produce index of value 0 and a consume index of value 1. The

wrap around of the arrays is taken into account when determining if a descriptor array is

full, so a produce index that indicates the last element in the array and a consume index

that indicates the first element in the array, also means the descriptor array is full. When

the produce index and the consume index are unequal and the consume index is not the

produce index plus one (with wrap around taken into account), then the descriptor array is

partially full and both the consumer and producer own enough descriptors to be able to

operate actively on the descriptor array.

Interrupt bit

The descriptors have an Interrupt bit, which is programmed by software. When the

Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an

interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits

in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the

descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note

that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers

flexible ways of managing the descriptor arrays. For instance, the device driver could add

10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the

descriptor array. This would invoke the interrupt service routine before the transmit

descriptor array is completely exhausted. The device driver could add another batch of

frames to the descriptor array, without interrupting continuous transmission of frames.

Frame fragments

For maximum flexibility in frame storage, frames can be split up into multiple frame

fragments with fragments located in different places in memory. In this case one

descriptor is used for each frame fragment. So, a descriptor can point to a single frame or

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to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit

frames are gathered from multiple fragments in memory and receive frames can be

scattered to multiple fragments in memory.

By stringing together fragments it is possible to create large frames from small memory

areas. Another use of fragments is to be able to locate a frame header and frame payload

in different places and to concatenate them without copy operations in the device driver.

For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the

last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status

words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next

descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor

is a new Ethernet frame.

17.2 Initialization

After reset, the Ethernet software driver needs to initialize the Ethernet block. During

initialization the software needs to:

• Remove the soft reset condition from the MAC

• Configure the PHY via the MIIM interface of the MAC.

Remark: it is important to configure the PHY and insure that reference clocks

(ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK

signals in MII mode) are present at the external pins and connected to the EMAC

module (selecting the appropriate pins using the PINSEL registers) prior to continuing

with Ethernet configuration. Otherwise the CPU can become locked and no further

functionality will be possible. This will cause JTAG lose communication with the target,

if debug mode is being used.

• Select RMII mode

• Configure the transmit and receive DMA engines, including the descriptor arrays

• Configure the host registers (MAC1,MAC2 etc.) in the MAC

• Enable the receive and transmit data paths

Depending on the PHY, the software needs to initialize registers in the PHY via the MII

Management interface. The software can read and write PHY registers by programming

the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the

MWTD register; read data and status information can be read from the MRDD and MIND

registers.

The Ethernet block supports RMII PHYs. During initialization software must select RMII

mode by programming the Command register.

Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be

de-asserted. The phy_ref_clk must be running and internally connected during this

operation.

Transmit and receive DMA engines should be initialized by the device driver by allocating

the descriptor and status arrays in memory. Transmit and receive functions have their own

dedicated descriptor and status arrays. The base addresses of these arrays need to be

programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The

number of descriptors in an array matches the number of statuses in an array.

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Please note that the transmit descriptors, receive descriptors and receive statuses are 8

bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit

statuses need to be aligned on 4 byte boundaries; receive status arrays need to be

aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to

be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding

i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor

array has 4 descriptors the value of the number of descriptors register should be 3.

After setting up the descriptor arrays, frame buffers need to be allocated for the receive

descriptors before enabling the receive data path. The Packet field of the receive

descriptors needs to be filled with the base address of the frame buffer of that descriptor.

Amongst others the Control field in the receive descriptor needs to contain the size of the

data buffer using -1 encoding.

The receive data path has a configurable filtering function for discarding/ignoring specific

Ethernet frames. The filtering function should also be configured during initialization.

After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The

soft reset condition must be removed before the Ethernet block can be enabled.

Enabling of the receive function is located in two places. The receive DMA manager

needs to be enabled and the receive data path of the MAC needs to be enabled. To

prevent overflow in the receive DMA engine the receive DMA engine should be enabled

by setting the RxEnable bit in the Command register before enabling the receive data path

in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register.

The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the

Command register.

Before enabling the data paths, several options can be programmed in the MAC, such as

automatic flow control, transmit to receive loop-back for verification, full/half duplex

modes, etc.

Base addresses of descriptor arrays and descriptor array sizes cannot be modified

without a (soft) reset of the receive and transmit data paths.

17.3 Transmit process

Overview

This section outlines the transmission process.

Device driver sets up descriptors and data

If the descriptor array is full the device driver should wait for the descriptor arrays to

become not full before writing to a descriptor in the descriptor array. If the descriptor array

is not full, the device driver should use the descriptor numbered TxProduceIndex of the

array pointed to by TxDescriptor.

The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be

transmitted. The Size field in the Command field of the descriptor should be set to the

number of bytes in the fragment buffer, -1 encoded. Additional control information can be

indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).

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After writing the descriptor the descriptor needs to be handed over to the hardware by

incrementing (and possibly wrapping) the TxProduceIndex register.

If the transmit data path is disabled, the device driver should not forget to enable the

transmit data path by setting the TxEnable bit in the Command register.

When there is a multi-fragment transmission for fragments other than the last, the Last bit

in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To

trigger an interrupt when the frame has been transmitted and transmission status has

been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have

the hardware add a CRC in the frame sequence control field of this Ethernet frame, set

the CRC bit in the descriptor. This should be done if the CRC has not already been added

by software. To enable automatic padding of small frames to the minimum required frame

size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits

CRC and Pad are both set to 1.

The device driver can set up interrupts using the IntEnable register to wait for a signal of

completion from the hardware or can periodically inspect (poll) the progress of

transmission. It can also add new frames at the end of the descriptor array, while

hardware consumes descriptors at the start of the array.

The device driver can stop the transmit process by resetting the TxEnable bit in the

Command register to 0. The transmission will not stop immediately; frames already being

transmitted will be transmitted completely and the status will be committed to memory

before deactivating the data path. The status of the transmit data path can be monitored

by the device driver reading the TxStatus bit in the Status register.

As soon as the transmit data path is enabled and the corresponding TxConsumeIndex

and TxProduceIndex are not equal i.e. the hardware still needs to process frames from

the descriptor array, the TxStatus bit in the Status register will return to 1 (active).

Tx DMA manager reads the Tx descriptor array

When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at

the address determined by TxDescriptor and TxConsumeIndex. The number of

descriptors requested is determined by the total number of descriptors owned by the

hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes

memory loading. Read data returned from memory is buffered and consumed as needed.

Tx DMA manager transmits data

After reading the descriptor the transmit DMA engine reads the associated frame data

from memory and transmits the frame. After transfer completion, the Tx DMA manager

writes status information back to the StatusInfo and StatusHashCRC words of the status

field. The value of the TxConsumeIndex is only updated after status information has been

committed to memory, which is checked by an internal tag protocol in the memory

interface. The Tx DMA manager continues to transmit frames until the descriptor array is

empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will

return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the

TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled.

The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the

descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments.

The Tx DMA manager gathers all the fragments from the host memory, visiting a string of

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frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.

When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,

this indicates the last fragment of the frame and thus the end of the frame is found.

Update ConsumeIndex

Each time the Tx DMA manager commits a status word to memory it completes the

transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around

into account) to hand the descriptor back to the device driver software. Software can

re-use the descriptor for new transmissions after hardware has handed it back.

The device driver software can keep track of the progress of the DMA manager by reading

the TxConsumeIndex register to see how far along the transmit process is. When the Tx

descriptor array is emptied completely, the TxConsumeIndex register retains its last value.

Write transmission status

After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame

descriptor is updated by the DMA manager.

If the descriptor is for the last fragment of a frame (or for the whole frame if there are no

fragments), then depending on the success or failure of the frame transmission, error

flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set

in the status. The CollisionCount field is set to the number of collisions the frame incurred,

up to the Retransmission Maximum programmed in the Collision window/retry register of

the MAC.

Statuses for all but the last fragment in the frame will be written as soon as the data in the

frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame

fragment other than the last fragment, the error flags are returned via the AHB interface. If

the Ethernet block detects a transmission error during transmission of a (multi-fragment)

frame, all remaining fragments of the frame are still read via the AHB interface. After an

error, the remaining transmit data is discarded by the Ethernet block. If there are errors

during transmission of a multi-fragment frame the error statuses will be repeated until the

last fragment of the frame. Statuses for all but the last fragment in the frame will be written

as soon as the data in the frame has been accepted by the Tx DMA manager. These may

include error information if the error is detected early enough. The status for the last

fragment in the frame will only be written after the transmission has completed on the

Ethernet connection. Thus, the status for the last fragment will always reflect any error

that occurred anywhere in the frame.

The status of the last frame transmission can also be inspected by reading the TSV0 and

TSV1 registers. These registers do not report statuses on a fragment basis and do not

store information of previously sent frames. They are provided primarily for debug

purposes, because the communication between driver software and the Ethernet block

takes place through the frame descriptors. The status registers are valid as long as the

internal status of the MAC is valid and should typically only be read when the transmit and

receive processes are halted.

Transmission error handling

If an error occurs during the transmit process, the Tx DMA manager will report the error

via the transmission StatusInfo word written in the Status array and the IntStatus interrupt

status register.

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The transmission can generate several types of errors: LateCollision, ExcessiveCollision,

ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the

transmission StatusInfo word. In addition to the separate bits in the StatusInfo word,

LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error

bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the

IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer,

or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus

register.

Underrun errors can have three causes:

• The next fragment in a multi-fragment transmission is not available. This is a nonfatal

error. A NoDescriptor status will be returned on the previous fragment and the TxError

bit in IntStatus will be set.

• The transmission fragment data is not available when the Ethernet block has already

started sending the frame. This is a nonfatal error. An Underrun status will be returned

on transfer and the TxError bit in IntStatus will be set.

• The flow of transmission statuses stalls and a new status has to be written while a

previous status still waits to be transferred across the memory interface. This is a fatal

error which can only be resolved by a soft reset of the hardware.

The first and second situations are nonfatal and the device driver has to re-send the frame

or have upper software layers re-send the frame. In the third case the hardware is in an

undefined state and needs to be soft reset by setting the TxReset bit in the Command

register.

After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, the

transmission of the erroneous frame will be aborted, remaining transmission data and

frame fragments will be discarded and transmission will continue with the next frame in

the descriptor array.

Device drivers should catch the transmission errors and take action.

Transmit triggers interrupts

The transmit data path can generate four different interrupt types:

• If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the

TxDoneInt bit in the IntStatus register after sending the fragment and committing the

associated transmission status to memory. Even if a descriptor (fragment) is not the

last in a multi-fragment frame the Interrupt bit in the descriptor can be used to

generate an interrupt.

• If the descriptor array is empty while the Ethernet hardware is enabled the hardware

will set the TxFinishedInt bit of the IntStatus register.

• If the AHB interface does not consume the transmission statuses at a sufficiently high

bandwidth the transmission may underrun in which case the TxUnderrun bit will be set

in the IntStatus register. This is a fatal error which requires a soft reset of the

transmission queue.

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• In the case of a transmission error (LateCollision, ExcessiveCollision, or

ExcessiveDefer) or a multi-fragment frame where the device driver did provide the

initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the

case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus

register.

All of the above interrupts can be enabled and disabled by setting or resetting the

corresponding bits in the IntEnable register. Enabling or disabling does not affect the

IntStatus register contents, only the propagation of the interrupt status to the CPU (via the

NVIC).

The interrupts, either of individual frames or of the whole list, are a good means of

communication between the DMA manager and the device driver, triggering the device

driver to inspect the status words of descriptors that have been processed.

Transmit example

Figure 10–20 illustrates the transmit process in an example transmitting uses a frame

header of 8 bytes and a frame payload of 12 bytes.

TxDescriptor

0x200810EC

TxStatus

0x200811F8

PACKET 0 HEADER (8 bytes)

0x200811F8

0x200810EC

Packet

0x20081314

StatusInfo

0x200810F0

0x200810F4

0x200810F8

0x200811FC

CONTROL

0 0 Control

7

StatusInfo

PACKET 0 PAYLOAD (12 bytes)

Packet

0x20081411

0x20081200

0x20081204

0 0 CONTROL 7

Control

Packet

0x20081419

0x200810FC

0x20081100

0x20081104

0x20081108

1 1 CONTROL 3

Control

TxProduceIndex

TxConsumeIndex

PACKET 1 HEADER (8 bytes)

Packet

0x20081324

TxDescriptorNumber

= 3

CONTROL 7

0 0 Control

descriptor array

fragment buffers

status array

Fig 20. Transmit example memory and registers

After reset the values of the DMA registers will be zero. During initialization the device

driver will allocate the descriptor and status array in memory. In this example, an array of

four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address

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boundary. Since the number of descriptors matches the number of statuses the status

array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address

boundary. The device driver writes the base address of the descriptor array

(0x2008 10EC) to the TxDescriptor register and the base address of the status array

(0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors

and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and

statuses in the arrays need not be initialized, yet.

At this point, the transmit data path may be enabled by setting the TxEnable bit in the

Command register. If the transmit data path is enabled while there are no further frames to

send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load

only the desired interrupts can be enabled by setting the relevant bits in the IntEnable

register.

Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP

protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will

add a header to the frame. The frame header need not be immediately in front of the

payload data in memory. The device driver can program the Tx DMA to collect header and

payload data. To do so, the device driver will program the first descriptor to point at the

frame header; the Last flag in the descriptor will be set to false/0 to indicate a

multi-fragment transmission. The device driver will program the next descriptor to point at

the actual payload data. The maximum size of a payload buffer is 2 kB so a single

descriptor suffices to describe the payload buffer. For the sake of the example though the

payload is distributed across two descriptors. After the first descriptor in the array

describing the header, the second descriptor in the array describes the initial 8 bytes of

the payload; the third descriptor in the array describes the remaining 4 bytes of the frame.

In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last

descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set

in the last fragment of the frame in order to trigger an interrupt after the transmission

completed. The Size field in the descriptor’s Control word is set to the number of bytes in

the fragment buffer, -1 encoded.

Note that in real device drivers, the payload will typically only be split across multiple

descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to

the hardware without the device driver copying it (zero copy device driver).

After setting up the descriptors for the transaction the device driver increments the

TxProduceIndex register by 3 since three descriptors have been programmed. If the

transmit data path was not enabled during initialization the device driver needs to enable

the data path now.

If the transmit data path is enabled the Ethernet block will start transmitting the frame as

soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero

after reset. The Tx DMA will start reading the descriptors from memory. The memory

system will return the descriptors and the Ethernet block will accept them one by one

while reading the transmit data fragments.

As soon as transmission read data is returned from memory, the Ethernet block will try to

start transmission on the Ethernet connection via the RMII interface.

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After transmitting each fragment of the frame the Tx DMA will write the status of the

fragment’s transmission. Statuses for all but the last fragment in the frame will be written

as soon as the data in the frame has been accepted by the Tx DMA manager. The status

for the last fragment in the frame will only be written after the transmission has completed

on the Ethernet connection.

Since the Interrupt bit in the descriptor of the last fragment is set, after committing the

status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,

which triggers the device driver to inspect the status information.

In this example the device driver cannot add new descriptors as long as the Ethernet

block has not incremented the TxConsumeIndex because the descriptor array is full (even

though one descriptor is not programmed yet). Only after the hardware commits the status

for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager

can the device driver program the next (the fourth) descriptor. The fourth descriptor can

already be programmed before completely transmitting the first frame.

In this example the hardware adds the CRC to the frame. If the device driver software

adds the CRC, the CRC trailer can be considered another frame fragment which can be

added by doing another gather DMA.

Each data byte is transmitted across the RMII interface as four 2-bit values. The Ethernet

block adds the preamble, frame delimiter leader, and the CRC trailer if hardware CRC is

enabled. Once transmission on the RMII interface commences the transmission cannot

be interrupted without generating an underrun error, which is why descriptors and data

read commands are issued as soon as possible and pipelined.

Using an RMII PHY, the data communication between the Ethernet block and the PHY is

communicated at 50 MHz. In 10 Mbps mode data will only be transmitted once every 10

clock cycles.

17.4 Receive process

This section outlines the receive process including the activities in the device driver

software.

Device driver sets up descriptors

After initializing the receive descriptor and status arrays to receive frames from the

Ethernet connection, the receive data path should be enabled in the MAC1 register and

the Control register.

During initialization, each Packet pointer in the descriptors is set to point to a data

fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the

descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt

bit allows generation of an interrupt after a fragment buffer has been filled and its status

has been committed to memory.

After the initialization and enabling of the receive data path, all descriptors are owned by

the receive hardware and should not be modified by the software unless hardware hands

over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been

received. The device driver is allowed to modify the descriptors after a (soft) reset of the

receive data path.

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Rx DMA manager reads Rx descriptor arrays

When the RxEnable bit in the Command register is set, the Rx DMA manager reads the

descriptors from memory at the address determined by RxDescriptor and

RxProduceIndex. The Ethernet block will start reading descriptors even before actual

receive data arrives on the RMII interface (descriptor prefetching). The block size of the

descriptors to be read is determined by the total number of descriptors owned by the

hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors

minimizes memory load. Read data returned from memory is buffered and consumed as

needed.

RX DMA manager receives data

After reading the descriptor, the receive DMA engine waits for the MAC to return receive

data from the RMII interface that passes the receive filter. Receive frames that do not

match the filtering criteria are not passed to memory. Once a frame passes the receive

filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA

does not write beyond the size of the buffer. When a frame is received that is larger than a

descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of

consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment

in the frame will return a status where the LastFrag bit is set to 0. Only on the last

fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the

last of a frame, the buffer may not be filled completely. The first receive data of the next

frame will be written to the fragment buffer of the next descriptor.

After receiving a fragment, the Rx DMA manager writes status information back to the

StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in

bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of

the RxProduceIndex is only updated after the fragment data and the fragment status

information has been committed to memory, which is checked by an internal tag protocol

in the memory interface. The Rx DMA manager continues to receive frames until the

descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the

RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the

receive descriptor array is full any new receive data will generate an overflow error and

interrupt.

Update ProduceIndex

Each time the Rx DMA manager commits a data fragment and the associated status word

to memory, it completes the reception of a descriptor and increments the RxProduceIndex

(taking wrap around into account) in order to hand the descriptor back to the device driver

software. Software can re-use the descriptor for new receptions by handing it back to

hardware when the receive data has been processed.

The device driver software can keep track of the progress of the DMA manager by reading

the RxProduceIndex register to see how far along the receive process is. When the Rx

descriptor array is emptied completely, the RxProduceIndex retains its last value.

Write reception status

After the frame has been received from the RMII bus, the StatusInfo and StatusHashCRC

words of the frame descriptor are updated by the DMA manager.

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If the descriptor is for the last fragment of a frame (or for the whole frame if there are no

fragments), then depending on the success or failure of the frame reception, error flags

(Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or

CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually

written to the fragment buffer, -1 encoded. For fragments not being the last in the frame

the RxSize will match the size of the buffer. The hash CRCs of the destination and source

addresses of a packet are calculated once for all the fragments belonging to the same

packet and then stored in every StatusHashCRC word of the statuses associated with the

corresponding fragments. If the reception reports an error, any remaining data in the

receive frame is discarded and the LastFrag bit will be set in the receive status field, so

the error flags in all but the last fragment of a frame will always be 0.

The status of the last received frame can also be inspected by reading the RSV register.

The register does not report statuses on a fragment basis and does not store information

of previously received frames. RSV is provided primarily for debug purposes, because the

communication between driver software and the Ethernet block takes place through the

frame descriptors.

Reception error handling

When an error occurs during the receive process, the Rx DMA manager will report the

error via the receive StatusInfo written in the Status array and the IntStatus interrupt status

register.

The receive process can generate several types of errors: AlignmentError, RangeError,

LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding

bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo,

AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together

into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the

RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError,

LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are

reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the

RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to

be soft reset by setting the RxReset bit in the Command register.

Overrun errors can have three causes:

• In the case of a multi-fragment reception, the next descriptor may be missing. In this

case the NoDescriptor field is set in the status word of the previous descriptor and the

RxError in the IntStatus register is set. This error is nonfatal.

• The data flow on the receiver data interface stalls, corrupting the packet. In this case

the overrun bit in the status word is set and the RxError bit in the IntStatus register is

set. This error is nonfatal.

• The flow of reception statuses stalls and a new status has to be written while a

previous status still waits to be transferred across the memory interface. This error will

corrupt the hardware state and requires the hardware to be soft reset. The error is

detected and sets the Overrun bit in the IntStatus register.

The first overrun situation will result in an incomplete frame with a NoDescriptor status

and the RxError bit in IntStatus set. Software should discard the partially received frame.

In the second overrun situation the frame data will be corrupt which results in the Overrun

status bit being set in the Status word while the IntError interrupt bit is set. In the third case

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receive errors cannot be reported in the receiver Status arrays which corrupts the

hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The

RxReset bit in the Command register should be used to soft reset the hardware.

Device drivers should catch the above receive errors and take action.

Receive triggers interrupts

The receive data path can generate four different interrupt types:

• If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the

RxDoneInt bit in the IntStatus register after receiving a fragment and committing the

associated data and status to memory. Even if a descriptor (fragment) is not the last in

a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an

interrupt.

• If the descriptor array is full while the Ethernet hardware is enabled, the hardware will

set the RxFinishedInt bit of the IntStatus register.

• If the AHB interface does not consume receive statuses at a sufficiently high

bandwidth, the receive status process may overrun, in which case the RxOverrun bit

will be set in the IntStatus register.

• If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or

CRCError), or a multi-fragment frame where the device driver did provide descriptors

for the initial fragments but did not provide the descriptors for the rest of the

fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt

bit of the IntStatus register.

All of the above interrupts can be enabled and disabled by setting or resetting the

corresponding bits in the IntEnable register. Enabling or disabling does not affect the

IntStatus register contents, only the propagation of the interrupt status to the CPU (via the

NVIC).

The interrupts, either of individual frames or of the whole list, are a good means of

communication between the DMA manager and the device driver, triggering the device

driver to inspect the status words of descriptors that have been processed.

Device driver processes receive data

As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the

device driver can read the descriptors that have been handed over to it by the hardware

(RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words

in the status array to check for multi-fragment receptions and receive errors.

The device driver can forward receive data and status to upper software layers. After

processing of data and status, the descriptors, statuses and data buffers may be recycled

and handed back to hardware by incrementing the RxConsumeIndex.

Receive example

Figure 10–21 illustrates the receive process in an example receiving a frame of 19 bytes.

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RxDescriptor

0x200810EC

RxStatus

0x200811F8

FRAGMENT 0 BUFFER(8 bytes)

0x200811F8

0x20081200

StatusInfo

StatusHashCRC

StatusInfo

StatusHashCRC

StatusInfo

StatusHashCRC

StatusInfo

StatusHashCRC

7

0x200810EC

PACKET

0x20081409

7

0x200810F0

1 CONTROL

7

FRAGMENT 1 BUFFER(8 bytes)

FRAGMENT 2 BUFFER(3 bytes)

FRAGMENT 3 BUFFER(8 bytes)

0x200810F4

0x200810F8

2

PACKET

0x20081411

0x20081208

0x20081210

7

1

CONTROL 7

PACKET

0x20081419

0x200810FC

0x20081100

0x20081104

0x20081108

CONTROL

7

PACKET

0x20081325

RxProduceIndex

RxConsumeIndex

CONTROL

RxDescriptorNumber= 3

descriptor array

fragment buffers

status array

Fig 21. Receive Example Memory and Registers

After reset, the values of the DMA registers will be zero. During initialization, the device

driver will allocate the descriptor and status array in memory. In this example, an array of

four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address

boundary. Since the number of descriptors matches the number of statuses, the status

array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address

boundary. The device driver writes the base address of the descriptor array

(0x2008 10EC) in the RxDescriptor register, and the base address of the status array

(0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors

and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and

statuses in the arrays need not be initialized yet.

After allocating the descriptors, a fragment buffer needs to be allocated for each of the

descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base

address of the fragment buffer is stored in the Packet field of the descriptors. The number

of bytes in the fragment buffer is stored in the Size field of the descriptor Control word.

The Interrupt field in the Control word of the descriptor can be set to generate an interrupt

as soon as the descriptor has been filled by the receive process. In this example the

fragment buffers are 8 bytes, so the value of the Size field in the Control word of the

descriptor is set to 7. Note that in this example, the fragment buffers are actually a

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continuous memory space; even when a frame is distributed over multiple fragments it will

typically be in a linear, continuous memory space; when the descriptors wrap at the end of

the descriptor array the frame will not be in a continuous memory space.

The device driver should enable the receive process by writing a 1 to the RxEnable bit of

the Command register, after which the MAC needs to be enabled by writing a 1 to the

‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now

start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts

can be disabled by setting the relevant bits in the IntEnable register.

After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In

this example the number of descriptors is 4. Initially the RxProduceIndex and

RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex

== RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex -

RxProduceIndex - 1 =) 3 descriptors; note the wrapping.

After enabling the receive function in the MAC, data reception will begin starting at the

next frame i.e. if the receive function is enabled while the RMII interface is halfway

through receiving a frame, the frame will be discarded and reception will start at the next

frame. The Ethernet block will strip the preamble and start of frame delimiter from the

frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the

frame to the first fragment buffer.

Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the

frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the

first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA

will continue filling the second fragment buffer. Since this is a multi-fragment receive, the

status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the

RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second

fragment the Rx DMA will continue writing the third fragment. The status of the second

fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing

the three bytes in the third fragment buffer, the end of the frame has been reached and the

status of the third fragment is written. The third fragment’s status will have the LastFrag bit

set to 1 and the RxSize equal to 2 (3, -1 encoded).

The next frame received from the RMII interface will be written to the fourth fragment

buffer i.e. five bytes of the third buffer will be unused.

The Rx DMA manager uses an internal tag protocol in the memory interface to check that

the receive data and status have been committed to memory. After the status of the

fragments are committed to memory, an RxDoneInt interrupt will be triggered, which

activates the device driver to inspect the status information. In this example, all

descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate

an interrupt after committing data and status to memory.

In this example the receive function cannot read new descriptors as long as the device

driver does not increment the RxConsumeIndex, because the descriptor array is full (even

though one descriptor is not programmed yet). Only after the device driver has forwarded

the receive data to application software, and after the device driver has updated the

RxConsumeIndex by incrementing it, will the Ethernet block can continue reading

descriptors and receive data. The device driver will probably increment the

RxConsumeIndex by 3, since the driver will forward the complete frame consisting of

three fragments to the application, and hence free up three descriptors at the same time.

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Each four pairs of bits transferred on the RMII interface are transferred as a byte on the

data write interface after being delayed by 128 or 136 cycles for filtering by the receive

filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and

CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability,

three descriptors are buffered. The value of the RxProduceIndex is only updated after

status information has been committed to memory, which is checked by an internal tag

protocol in the memory interface. The software device driver will process the receive data,

after which the device driver will update the RxConsumeIndex.

17.5 Transmission retry

If a collision on the Ethernet occurs, it usually takes place during the collision window

spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry

the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this

data can be used during the retry. A transmission retry within the first 64 bytes in a frame

is fully transparent to the application and device driver software.

When a collision occurs outside of the 64 byte collision window, a LateCollision error is

triggered, and the transmission is aborted. After a LateCollision error, the remaining data

in the transmit frame will be discarded. The Ethernet block will set the Error and

LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will

be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the

IntStatus register will be propagated to the CPU (via the NVIC). The device driver software

should catch the interrupt and take appropriate actions.

The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure

the maximum number of retries before aborting the transmission.

17.6 Status hash CRC calculations

For each received frame, the Ethernet block is able to detect the destination address and

source address and from them calculate the corresponding hash CRCs. To perform the

computation, the Ethernet block features two internal blocks: one is a controller

synchronized with the beginning and the end of each frame, the second block is the CRC

calculator.

When a new frame is detected, internal signaling notifies the controller.The controller

starts counting the incoming bytes of the frame, which correspond to the destination

address bytes. When the sixth (and last) byte is counted, the controller notifies the

calculator to store the corresponding 32-bit CRC into a first inner register. Then the

controller repeats counting the next incoming bytes, in order to get synchronized with the

source address. When the last byte of the source address is encountered, the controller

again notifies the CRC calculator, which freezes until the next new frame. When the

calculator receives this second notification, it stores the present 32-bit CRC into a second

inner register. Then the CRCs remain frozen in their own registers until new notifications

arise.

The destination address and source address hash CRCs being written in the

StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated

by the CRC calculator.

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17.7 Duplex modes

The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex

mode needs to be configured by the device driver software during initialization.

For a full duplex connection the FullDuplex bit of the Command register needs to be set to

1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for

half duplex the same bits need to be set to 0.

17.8 IEE 802.3/Clause 31 flow control

Overview

For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control

using pause frames. This type of flow control may be used in full-duplex point-to-point

connections. Flow control allows a receiver to stall a transmitter e.g. when the receive

buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the

transmitting side.

Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles.

Receive flow control

In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives

a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is

enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the

RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control

frames. When a pause frame is received on the Rx side of the Ethernet block,

transmission on the Tx side will be interrupted after the currently transmitting frame has

completed, for an amount of time as indicated in the received pause frame. The transmit

data path will stop transmitting data for the number of 512 bit slot times encoded in the

pause-timer field of the received pause control frame.

By default the received pause control frames are not forwarded to the device driver. To

forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE

FRAMES’ bit in the MAC1 configuration register.

Transmit flow control

If case device drivers need to stall the receive data e.g. because software buffers are full,

the Ethernet block can transmit pause control frames. Transmit flow control needs to be

initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by

hardware, such as the DMA managers.

With software flow control, the device driver can detect a situation in which the process of

receiving frames needs to be interrupted by sending out Tx pause frames. Note that due

to Ethernet delays, a few frames can still be received before the flow control takes effect

and the receive stream stops.

Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command

register. When the Ethernet block operates in full duplex mode, this will result in

transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is

written to TxFlowControl bit of the Command register.

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If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the

Command register will start a pause frame transmission. The value inserted into the

pause-timer value field of transmitted pause frames is programmed via the

PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is

de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically

sent to abort flow control and resume transmission.

When flow control be in force for an extended time, a sequence of pause frames must be

transmitted. This is supported with a mirror counter mechanism. To enable mirror

counting, a nonzero value is written to the MirrorCounter[15:0] bits in the

FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is

transmitted. After sending the pause frame, an internal mirror counter is initialized to zero.

The internal mirror counter starts incrementing one every 512 bit-slot times. When the

internal mirror counter reaches the MirrorCounter value, another pause frame is

transmitted with pause-timer value equal to the PauseTimer field from the

FlowControlCounter register, the internal mirror counter is reset to zero and restarts

counting. The register MirrorCounter[15:0] is usually set to a smaller value than register

PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send

a new pause frame before the transmission on the other side can resume. By continuing

to send pause frames before the transmitting side finishes counting the pause timer, the

pause can be extended as long as TxFlowControl is asserted. This continues until

TxFlowControl is de-asserted when a final pause frame having a pause-timer value of

0x0000 is automatically sent to abort flow control and resume transmission. To disable the

mirror counter mechanism, write the value 0 to MirrorCounter field in the

FlowControlCounter register. When using the mirror counter mechanism, account for

time-of-flight delays, frame transmission time, queuing delays, crystal frequency

tolerances, and response time delays by programming the MirrorCounter conservatively,

typically about 80% of the PauseTimer value.

If the software device driver sets the MirrorCounter field of the FlowControlCounter

register to zero, the Ethernet block will only send one pause control frame. After sending

the pause frame an internal pause counter is initialized at zero; the internal pause counter

is incremented by one every 512 bit-slot times. Once the internal pause counter reaches

the value of the PauseTimer register, the TxFlowControl bit in the Command register will

be reset. The software device driver can poll the TxFlowControl bit to detect when the

pause completes.

The value of the internal counter in the flow control module can be read out via the

FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register

will return the value of the internal mirror counter; if the MirrorCounter is zero the

FlowControlStatus register will return the value of the internal pause counter value.

The device driver is allowed to dynamically modify the MirrorCounter register value and

switch between zero MirrorCounter and nonzero MirrorCounter modes.

Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1

configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not

transmit pause control frames, software must not initiate pause frame transmissions, and

the TxFlowControl bit in the Command register should be zero.

Transmit flow control example

Figure 10–22 illustrates the transmit flow control.

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device driver

PauseTimer

clear

MirrorCounter

TxFlowCtl

register

writes

TxFlowCtl

pause control

frame

transmission

pause control

frame

transmission

RMII

normal

frame

normal transimisson

transmit transmission

transmission

MirrorCounter

(1/515 bit

slots)

RMII

receive

pause in effect

normal receive

0

50

100

150

200

250

300

350

400

450

500

Fig 22. Transmit Flow Control

In this example, a frame is received while transmitting another frame (full duplex.) The

device driver detects that some buffer might overrun and enables the transmit flow control

by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter

register, after which it enables the transmit flow control by setting the TxFlowControl bit in

the Command register.

As a response to the enabling of the flow control a pause control frame will be sent after

the currently transmitting frame has been transmitted. When the pause frame

transmission completes the internal mirror counter will start counting bit slots; as soon as

the counter reaches the value in the MirrorCounter field another pause frame is

transmitted. While counting the transmit data path will continue normal transmissions.

As soon as software disables transmit flow control a zero pause control frame is

transmitted to resume the receive process.

17.9 Half-Duplex mode backpressure

When in half-duplex mode, backpressure can be generated to stall receive packets by

sending continuous preamble that basically jams any other transmissions on the Ethernet

medium. When the Ethernet block operates in half duplex mode, asserting

the TxFlowControl bit in the Command register will result in applying continuous preamble

on the Ethernet wire, effectively blocking traffic from any other Ethernet station on the

same segment.

In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent

until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins

transmitting preamble, which raises carrier sense causing all other stations to defer. In the

event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the

collision. The colliding station backs off and then defers to the backpressure. If during

backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame

sent and then the backpressure resumed. If TxFlowControl is asserted for longer than

3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending

preamble for several byte times to avoid the jabber limit.

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17.10 Receive filtering

Features of receive filtering

The Ethernet MAC has several receive packet filtering functions that can be configured

from the software driver:

• Perfect address filter: allows packets with a perfectly matching station address to be

identified and passed to the software driver.

• Hash table filter: allows imperfect filtering of packets based on the station address.

• Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or

broadcast packets.

• Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt.

The filtering functions can be logically combined to create complex filtering functions.

Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a

promiscuous mode allows all packets to be passed to software.

Overview

The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet

destination address in the frame. This capability greatly reduces the load on the host

system, because Ethernet frames that are addressed to other stations would otherwise

need to be inspected and rejected by the device driver software, using up bandwidth,

memory space, and host CPU time. Address filtering can be implemented using the

perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code

which can be used as an index into a 64 entry programmable hash table. Figure 10–23

depicts a functional view of the receive filter.

At the top of the diagram the Ethernet receive frame enters the filters. Each filter is

controlled by signals from control registers; each filter produces a ‘Ready’ output and a

‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering

then it will assert its Ready output; if the filter finds a matching frame it will assert the

Match output along with the Ready output. The results of the filters are combined by logic

functions into a single RxAbort output. If the RxAbort output is asserted, the frame does

not need to be received.

In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The

Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort

signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and

removed from the buffer and not stored to memory at all, not using up receive descriptors,

etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to

reception of a Magic Packet), part of the frame is already written to memory and the

Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the

status word of the frame will be set to indicate that the software device driver can discard

the frame immediately.

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packet

AcceptUnicastEn

AcceptMulticastEn

AcceptMulticastHashEn

AcceptUnicastHashEn

HashFilter

StationAddress

AcceptPerfectEn

IMPERFECT

HASH

FILTER

PERFECT

ADDRESS

FILTER

CRC

OK?

FMatch

RxFilterWoL

RxFilterEnWoL

RxAbort

FReady

Fig 23. Receive filter block diagram

Unicast, broadcast and multicast

Generic filtering based on the type of frame (unicast, multicast or broadcast) can be

programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits

of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and

AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast,

respectively, to be accepted, ignoring the Ethernet destination address in the frame. To

program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1.

Perfect address match

When a frame with a unicast destination address is received, a perfect filter compares the

destination address with the 6 byte station address programmed in the station address

registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1,

and the address matches, the frame is accepted.

Imperfect hash filtering

An imperfect filter is available, based on a hash mechanism. This filter applies a hash

function to the destination address and uses the hash to access a table that indicates if

the frame should be accepted. The advantage of this type of filter is that a small table can

cover any possible address. The disadvantage is that the filtering is imperfect, i.e.

sometimes frames are accepted that should have been discarded.

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• Hash function:

– The standard Ethernet cyclic redundancy check (CRC) function is calculated from

the 6 byte destination address in the Ethernet frame (this CRC is calculated

anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of

the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access

the hash table: it is used as an index in the 64-bit HashFilter register that has been

programmed with accept values. If the selected accept value is 1, the frame is

accepted.

– The device driver can initialize the hash filter table by writing to the registers

HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table

and HashFilterH contains bit 32 through 63 of the table. So, hash value 0

corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to

bit 31 of the HashFilterH register.

• Multicast and unicast

– The imperfect hash filter can be applied to multicast addresses, by setting the

AcceptMulticastHashEn bit in the RxFilter register to 1.

– The same imperfect hash filter that is available for multicast addresses can also be

used for unicast addresses. This is useful to be able to respond to a multitude of

unicast addresses without enabling all unicast addresses. The hash filter can be

applied to unicast addresses by setting the AcceptUnicastHashEn bit in the

RxFilter register to 1.

Enabling and disabling filtering

The filters as defined in the sections above can be bypassed by setting the PassRxFilter

bit in the Command register. When the PassRxFilter bit is set, all receive frames will be

passed to memory. In this case the device driver software has to implement all filtering

functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering

as defined in the next section.

Runt frames

A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the

minimum Ethernet frame size and therefore considered erroneous; they might be collision

fragments. The receive data path automatically filters and discards these runt frames

without writing them to memory and using a receive descriptor.

When a runt frame has a correct CRC there is a possibility that it is intended to be useful.

The device driver can receive the runt frames with correct CRC by setting the

PassRuntFrame bit of the Command register to 1.

17.11 Power management

The Ethernet block supports power management by means of clock switching. All clocks

in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should

not be switched off.

17.12 Wake-up on LAN

Overview

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The Ethernet block supports power management with remote wake-up over LAN. The

host system can be powered down, even including part of the Ethernet block itself, while

the Ethernet block continues to listen to packets on the LAN. Appropriately formed

packets can be received and recognized by the Ethernet block and used to trigger the

host system to wake up from its power-down state.

Wake-up of the system takes effect through an interrupt. When a wake-up event is

detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger

an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This

interrupt should be used by system power management logic to wake up the system.

While in a power-down state the packet that generates a Wake-up on LAN event is lost.

There are two ways in which Ethernet packets can trigger wake-up events: generic

Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for

Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the

triggering packet has a valid CRC. Figure 10–23 shows the generation of the wake-up

signal.

The RxFilterWoLStatus register can be read by the software to inspect the reason for a

Wake-up event. Before going to power-down the power management software should

clear the register by writing the RxFilterWolClear register.

NOTE: when entering in power-down mode, a receive frame might be not entirely stored

into the Rx buffer. In this situation, after turning exiting power-down mode, the next

receive frame is corrupted due to the data of the previous frame being added in front of

the last received frame. Software drivers have to reset the receive data path just after

exiting power-down mode.

The following subsections describe the two Wake-up on LAN mechanisms.

Filtering for WoL

The receive filter functionality can be used to generate Wake-up on LAN events. If the

RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt

bit of the IntStatus register if a frame is received that passes the filter. The interrupt will

only be generated if the CRC of the frame is correct.

Magic Packet WoL

The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet

technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely

intended for wake-up purposes. This packet can be received, analyzed and recognized by

the Ethernet block and used to trigger a wake-up event.

A Magic Packet is a packet that contains in its data portion the station address repeated

16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization

bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the

data portion of the packet. The whole packet must be a well-formed Ethernet frame.

The magic packet detection unit analyzes the Ethernet packets, extracts the packet

address and checks the payload for the Magic Packet pattern. The address from the

packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic

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packet only sets the wake-up interrupt status bit if the packet passes the receive filter as

illustrated in Figure 10–23: the result of the receive filter is ANDed with the magic packet

filter result to produce the result.

Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl

register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the

RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all

packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets

is more strict.

When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register,

the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the

bit writing a 1 to the corresponding bit of the RxFilterWoLClear register.

Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55

0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet):

FF FF FF FF FF FF

11 22 33 44 55 66 11 22 33 44 55 66

17.13 Enabling and disabling receive and transmit

Enabling and disabling reception

After reset, the receive function of the Ethernet block is disabled. The receive function can

be enabled by the device driver setting the RxEnable bit in the Command register and the

“RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order).

The status of the receive data path can be monitored by the device driver by reading the

RxStatus bit of the Status register. Figure 10–24 illustrates the state machine for the

generation of the RxStatus bit.

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ACTIVE

RxStatus = 1

xxxxxxxxxxxxxxxxxx

RxEnable = 0 and not busy receiving

OR

RxEnable = 1

RxProduceIndex = RxConsumeIndex - 1

INACTIVE

RxStatus = 0

reset

Fig 24. Receive Active/Inactive state machine

After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is

set in the Command register, the state machine transitions to the ACTIVE state. As soon

as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the

receive data path is busy receiving a packet while the receive data path gets disabled, the

packet will be received completely, stored to memory along with its status before returning

to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will

return to the INACTIVE state.

For the state machine in Figure 10–24, a soft reset is like a hardware reset assertion, i.e.

after a soft reset the receive data path is inactive until the data path is re-enabled.

Enabling and disabling transmission

After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data

path can be enabled by the device driver setting the TxEnable bit in the Command

register to 1.

The status of the transmit data paths can be monitored by the device driver reading the

TxStatus bit of the Status register. Figure 10–25 illustrates the state machine for the

generation of the TxStatus bit.

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ACTIVE

TxStatus = 1

xxxxxxxxxxxxxxxxxxxxxx

TxEnable = 1

TxEnable = 0 and not busy transmitting

AND

OR

TxProduceIndex <> TxConsumeIndex

TxProduceIndex = TxConsumeIndex

INACTIVE

TxStatus = 0

reset

Fig 25. Transmit Active/Inactive state machine

After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set

in the Command register and the Produce and Consume indices are not equal, the state

machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the

transmit data path has completed all pending transmissions, including committing the

transmission status to memory, the state machine returns to the INACTIVE state. The

state machine will also return to the INACTIVE state if the Produce and Consume indices

are equal again i.e. all frames have been transmitted.

For the state machine in Figure 10–25, a soft reset is like a hardware reset assertion, i.e.

after a soft reset the transmit data path is inactive until the data path is re-enabled.

17.14 Transmission padding and CRC

In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet

block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check

Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’

(ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the

MAC2 configuration register, as well as the Override and Pad bits from the transmit

descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and

‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and

CRC bits from the transmit descriptor Control word.

The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the

MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then

EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable

(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the

descriptor.

If padding is required and enabled, a CRC will always be appended to the padded frames.

A CRC will only be appended to the non-padded frames if ECRCE is set.

If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is

set.

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If EPADEN is 1, then small frames will be padded and a CRC will always be added to the

padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be

padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the

frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if

ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN

frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating

64 or 68 bytes padded frames.

If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the

DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.

17.15 Huge frames and frame length checking

The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to

enable transmission and reception of frames of any length. Huge frame transmission can

be enabled on a per frame basis by setting the Override and Huge bits in the transmit

descriptor Control word.

When enabling huge frames, the Ethernet block will not check frame lengths and report

frame length errors (RangeError and LengthError). If huge frames are enabled, the

received byte count in the RSV register may be invalid because the frame may exceed the

maximum size; the RxSize fields from the receive status arrays will be valid.

Frame lengths are checked by comparing the length/type field of the frame to the actual

number of bytes in the frame. A LengthError is reported by setting the corresponding bit in

the receive StatusInfo word.

The MAXF register allows the device driver to specify the maximum number of bytes in a

frame. The Ethernet block will compare the actual receive frame to the MAXF value and

report a RangeError in the receive StatusInfo word if the frame is larger.

17.16 Statistics counters

Generally, Ethernet applications maintain many counters that track Ethernet traffic

statistics. There are a number of standards specifying such counters, such as IEEE std

802.3 / clause 30. Other standards are RFC 2665 and RFC 2233.

The approach taken here is that by default all counters are implemented in software. With

the help of the StatusInfo field in frame statuses, many of the important statistics events

listed in the standards can be counted by software.

17.17 MAC status vectors

Transmit and receive status information as detected by the MAC are available in registers

TSV0, TSV1 and RSV so that software can poll them. These registers are normally of

limited use because the communication between driver software and the Ethernet block

takes place primarily through frame descriptors. Statistical events can be counted by

software in the device driver. However, for debug purposes the transmit and receive status

vectors are made visible. They are valid as long as the internal status of the MAC is valid

and should typically only be read when the transmit and receive processes are halted.

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Chapter 10: LPC17xx Ethernet

The Ethernet block has a hard reset input which is connected to the chip reset, as well as

several soft resets which can be activated by setting the appropriate bit(s) in registers. All

registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise

specified.

Hard reset

After a hard reset, all registers will be set to their default value.

Soft reset

Parts of the Ethernet block can be soft reset by setting bits in the Command register and

the MAC1 configuration register.The MAC1 register has six different reset bits:

• SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the

MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a

hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware

reset.

• SIMULATION RESET: Resets the random number generator in the Transmit

Function. The value after a hardware reset assertion is 0.

• RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame

logic) and the receive function in the MAC. The value after a hardware reset assertion

is 0.

• RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a

hardware reset assertion is 0.

• RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame

logic) and the transmit function in the MAC. The value after a hardware reset

assertion is 0.

• RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after

a hardware reset assertion is 0.

The above reset bits must be cleared by software.

The Command register has three different reset bits:

• TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the

MAC portions, including all (read-only) registers in the transmit data path, as well as

the TxProduceIndex register in the host registers module. A soft reset of the transmit

data path will abort all AHB transactions of the transmit data path. The reset bit will be

cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear

the TxStatus bit in the Status register.

• RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the

MAC portions, including all (read-only) registers in the receive data path, as well as

the RxConsumeIndex register in the host registers module. A soft reset of the receive

data path will abort all AHB transactions of the receive data path. The reset bit will be

cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear

the RxStatus bit in the Status register.

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• RegReset: Resets all of the data paths and registers in the host registers module,

excluding the registers in the MAC. A soft reset of the registers will also abort all AHB

transactions of the transmit and receive data path. The reset bit will be cleared

autonomously by the Ethernet block.

To do a full soft reset of the Ethernet block, device driver software must:

• Set the ‘SOFT RESET’ bit in the MAC1 register to 1.

• Set the RegReset bit in the Command register, this bit clears automatically.

• Re-initialize the MAC registers (0x000 to 0x0FC).

• Reset the ‘SOFT RESET’ bit in the MAC1 register to 0.

To reset just the transmit data path, the device driver software has to:

• Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.

• Disable the Tx DMA managers by setting the TxEnable bits in the Command register

to 0.

• Set the TxReset bit in the Command register, this bit clears automatically.

• Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0.

To reset just the receive data path, the device driver software has to:

• Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1

configuration register and resetting of the RxEnable bit of the Command register.

• Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.

• Set the RxReset bit in the Command register, this bit clears automatically.

• Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.

17.19 Ethernet errors

The Ethernet block generates errors for the following conditions:

• A reception can cause an error: AlignmentError, RangeError, LengthError,

SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the

receive StatusInfo and in the interrupt status register (IntStatus).

• A transmission can cause an error: LateCollision, ExcessiveCollision,

ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the

transmission StatusInfo and in the interrupt status register (IntStatus).

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18. AHB bandwidth

The Ethernet block is connected to an AHB bus which must carry all of the data and

control information associated with all Ethernet traffic in addition to the CPU accesses

required to operate the Ethernet block and deal with message contents.

18.1 DMA access

Assumptions

By making some assumptions, the bandwidth needed for each type of AHB transfer can

be calculated and added in order to find the overall bandwidth requirement.

The flexibility of the descriptors used in the Ethernet block allows the possibility of defining

memory buffers in a range of sizes. In order to analyze bus bandwidth requirements,

some assumptions must be made about these buffers. The "worst case" is not addressed

since that would involve all descriptors pointing to single byte buffers, with most of the

memory occupied in holding descriptors and very little data. It can easily be shown that

the AHB cannot handle the huge amount of bus traffic that would be caused by such a

degenerate (and illogical) case.

For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame.

Continuous traffic is assumed on both the transmit and receive channels.

This analysis does not reflect the flow of Ethernet traffic over time, which would include

inter-packet gaps in both the transmit and receive channels that reduce the bandwidth

requirements over a larger time frame.

Types of DMA access and their bandwidth requirements

The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz,

transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps.

The Ethernet block initiates DMA accesses for the following cases:

• Tx descriptor read:

– Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for

each use of a descriptor.

– Two word read happens once every 64 bytes (16 words) of transmitted data.

– This gives 1/8th of the data rate, which = 1.5625 Mbps.

• Rx descriptor read:

– Receive descriptors occupy 2 words (8 bytes) of memory and are read once for

each use of a descriptor.

– Two word read happens once every 64 bytes (16 words) of received data.

– This gives 1/8th of the data rate, which = 1.5625 Mbps.

• Tx status write:

– Transmit status occupies 1 word (4 bytes) of memory and is written once for each

use of a descriptor.

– One word write happens once every 64 bytes (16 words) of transmitted data.

– This gives 1/16th of the data rate, which = 0.7813 Mbps.

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• Rx status write:

– Receive status occupies 2 words (8 bytes) of memory and is written once for each

use of a descriptor.

– Two word write happens once every 64 bytes (16 words) of received data.

– This gives 1/8 of the data rate, which = 1.5625 Mbps.

• Tx data read:

– Data transmitted in an Ethernet frame, the size is variable.

– Basic Ethernet rate = 12.5 Mbps.

• Rx data write:

– Data to be received in an Ethernet frame, the size is variable.

– Basic Ethernet rate = 12.5 Mbps.

This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.

18.2 Types of CPU access

• Accesses that mirror each of the DMA access types:

– All or part of status values must be read, and all or part of descriptors need to be

written after each use, transmitted data must be stored in the memory by the CPU,

and eventually received data must be retrieved from the memory by the CPU.

– This gives roughly the same or slightly lower rate as the combined DMA functions,

which = 30.5 Mbps.

• Access to registers in the Ethernet block:

– The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus

registers, and both read and write the RxConsumeIndex and TxProduceIndex

registers.

– 7 word read/writes once every 64 bytes (16 words) of transmitted and received

data.

– This gives 7/16 of the data rate, which = 5.4688 Mbps.

This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.

18.3 Overall bandwidth

Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which

comes to approximately 66.5 MB/s.

The peak bandwidth requirement can be somewhat higher due to the use of small

memory buffers, in order to hold often used addresses (e.g. the station address) for

example. Driver software can determine how to build frames in an efficient manner that

does not overutilize the AHB.

The bandwidth available on the AHB bus depends on the system clock frequency. As an

example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses

related to the Ethernet will be word transfers. The raw AHB bandwidth can be

approximated as 4 bytes per two system clocks, which equals 2 times the system clock

rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization

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for Ethernet traffic during simultaneous transmit and receive operations. This shows that it

is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty

of bandwidth headroom.

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19. CRC calculation

The calculation is used for several purposes:

• Generation the FCS at the end of the Ethernet frame.

• Generation of the hash table index for the hash table filtering.

• Generation of the destination and source address hash CRCs.

The C pseudocode function below calculates the CRC on a frame taking the frame

(without FCS) and the number of bytes in the frame as arguments. The function returns

the CRC as a 32-bit integer.

int crc_calc(char frame_no_fcs[], int frame_len)

{

int

i;

j;

// iterator

// another iterator

char byte; // current byte

int crc; // CRC result

int q0, q1, q2, q3; // temporary variables

crc 0xFFFFFFFF;

for (i 0; frame_len; i++)

byte *frame_no_fcs++;

for (j 0; 2; j++)

if (((crc >> 28)

=

i

<

{

=

j

<

{

^

(byte >> 3))

&

0x00000001)

q0;

{

q3

else

q3

=

0x04C11DB7;

}

{

=

0x00000000;

if (((crc >> 29)

^

(byte >> 2))

&

^

q2

else

q2

=

0x09823B6E;

}

{

=

0x00000000;

}

if (((crc >> 30)

^ (byte >> 1))

q1

else

q1

=

0x130476DC;

}

{

=

0x00000000;

if (((crc >> 31)

^ (byte >> 0))

q0

else

q0

=

0x2608EDB8;

}

{

=

0x00000000;

}

crc

= (crc << 4) ^ q3 ^ q2 ^ q1

byte >>= 4;

}

return crc;

}

For FCS calculation, this function is passed a pointer to the first byte of the frame and the

length of the frame without the FCS.

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For hash filtering, this function is passed a pointer to the destination address part of the

frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits

[28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit

is set the packet is passed, otherwise it is rejected by the hash filter.

For obtaining the destination and source address hash CRCs, this function calculates first

both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are

extracted, concatenated, and written in every StatusHashCRC word of every fragment

status.

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1. How to read this chapter

This chapter describes the USB controller which is present on all LPC17xx devices except

the LPC1767. On some LPC17xx family devices, the USB controller can also be

configured for Host or OTG operation.

2. Basic configuration

The USB controller is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the

USB clock or with the Main PLL (PLL0). See Section 4–6.1.

3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to

PINMODE5 (Section 8–5).

4. Wake-up: Activity on the USB bus port can wake up the microcontroller from

Power-down mode, see Section 4–8.8.

5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

6. Initialization: see Section 11–13.

3. Introduction

The Universal Serial Bus (USB) is a four-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame

(SOF) marker and transactions that transfer data to or from device endpoints. Each device

can have a maximum of 16 logical or 32 physical endpoints. There are four types of

transfers defined for the endpoints. Control transfers are used to configure the device.

Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the

rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no

error correction.

For more information on the Universal Serial Bus, see the USB Implementers Forum

website.

The USB device controller on the LPC17xx enables full-speed (12 Mb/s) data exchange

with a USB host controller.

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Table 183. USB related acronyms, abbreviations, and definitions used in this chapter

Acronym/abbreviation Description

AHB

ATLE

ATX

Advanced High-performance bus

Auto Transfer Length Extraction

Analog Transceiver

DMA Descriptor

DD

DDP

DMA

EOP

EP

DMA Description Pointer

Direct Memory Access

End-Of-Packet

Endpoint

EP_RAM

FS

Endpoint RAM

Full Speed

LED

LS

Light Emitting Diode

Low Speed

MPS

NAK

PLL

Maximum Packet Size

Negative Acknowledge

Phase Locked Loop

Random Access Memory

Start-Of-Frame

RAM

SOF

SIE

Serial Interface Engine

Synchronous RAM

USB Device Communication Area

Universal Serial Bus

SRAM

UDCA

USB

4. Features

• Fully compliant with the USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• Supports DMA transfers on all non-control endpoints.

• Allows dynamic switching between CPU controlled and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

5. Fixed endpoint configuration

Table 11–184 shows the supported endpoint configurations. Endpoints are realized and

configured at run time using the Endpoint realization registers, documented in Section

11–10.4 “Endpoint realization registers”.

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Table 184. Fixed endpoint configuration

Logical

endpoint

Physical

endpoint

Endpoint type

Direction

Packet size (bytes)

Double buffer

0

Control

Interrupt

Bulk

Out

In

8, 16, 32, 64

1 to 64

No

0

1

No

1

2

Out

In

No

1

3

1 to 64

No

2

4

Out

In

8, 16, 32, 64

1 to 1023

1 to 64

Yes

No

2

5

Bulk

3

6

Isochronous

Interrupt

Bulk

Out

In

3

7

4

8

Out

In

4

9

1 to 64

No

5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Out

In

8, 16, 32, 64

1 to 1023

1 to 64

Yes

No

5

Bulk

6

Isochronous

Interrupt

Bulk

Out

In

6

7

Out

In

7

1 to 64

No

8

Out

In

8, 16, 32, 64

1 to 1023

1 to 64

Yes

No

8

Bulk

9

Isochronous

Interrupt

Bulk

Out

In

9

10

11

12

13

14

15

Out

In

1 to 64

No

Out

In

8, 16, 32, 64

1 to 1023

1 to 64

Yes

No

Bulk

Isochronous

Interrupt

Bulk

Out

In

Out

In

1 to 64

No

Out

In

8, 16, 32, 64

Yes

Bulk

Out

In

Bulk

6. Functional description

The architecture of the USB device controller is shown below in Figure 11–26.

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V_BUS

BUS

MASTER

INTERFACE

DMA

ENGINE

USB_CONNECT

DMA interface

(AHB master)

USB_D+

EP_RAM

ACCESS

CONTROL

SERIAL

INTERFACE

ENGINE

REGISTER

INTERFACE

USB_D-

USB_UP_LED

register

EP_RAM

(4K)

interface

(AHB slave)

USB DEVICE

BLOCK

Fig 26. USB device controller block diagram

6.1 Analog transceiver

The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX

sends/receives the bi-directional D+ and D- signals of the USB bus.

6.2 Serial Interface Engine (SIE)

The SIE implements the full USB protocol layer. It is completely hardwired for speed and

needs no firmware intervention. It handles transfer of data between the endpoint buffers in

EP_RAM and the USB bus. The functions of this block include: synchronization pattern

recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,

PID verification/generation, address recognition, and handshake evaluation/generation.

6.3 Endpoint RAM (EP_RAM)

Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for

this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the

EP_RAM. The total EP_RAM space required depends on the number of realized

endpoints, the maximum packet size of the endpoint, and whether the endpoint supports

double buffering.

6.4 EP_RAM access control

The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the

three sources that can access it: the CPU (via the Register Interface), the SIE, and the

DMA Engine.

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6.5 DMA engine and bus master interface

When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB

bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all

endpoints. When transferring data, the DMA Engine functions as a master on the AHB

bus through the bus master interface.

6.6 Register interface

The Register Interface allows the CPU to control the operation of the USB Device

Controller. It also provides a way to write transmit data to the controller and read receive

data from the controller.

6.7 SoftConnect

The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH

through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow

software to finish its initialization sequence before deciding to establish connection to the

USB. Re-initialization of the USB bus connection can also be performed without having to

unplug the cable.

To use the SoftConnect feature, the CONNECT signal should control an external switch

that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the

CONNECT signal by writing to the CON bit using the SIE Set Device Status command.

6.8 GoodLink

Good USB connection indication is provided through GoodLink technology. When the

device is successfully enumerated and configured, the LED indicator will be permanently

ON. During suspend, the LED will be OFF.

This feature provides a user-friendly indicator on the status of the USB device. It is a

useful field diagnostics tool to isolate faulty equipment.

To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED

signal is controlled using the SIE Configure Device command.

7. Operational overview

Transactions on the USB bus transfer data between device endpoints and the host. The

direction of a transaction is defined with respect to the host. OUT transactions transfer

data from the host to the device. IN transactions transfer data from the device to the host.

All transactions are initiated by the host controller.

For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the

USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and

converts it into a parallel data stream. The parallel data is written to the corresponding

endpoint buffer in the EP_RAM.

For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,

converts it into serial data, and transmits it onto the USB bus using the USB ATX.

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Once data has been received or sent, the endpoint buffer can be read or written. How this

is accomplished depends on the endpoint’s type and operating mode. The two operating

modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.

In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the

Register Interface. See Section 11–14 “Slave mode operation” for a detailed description of

this mode.

In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See

Section 11–15 “DMA operation” for a detailed description of this mode.

8. Pin description

Table 185. USB external interface

Name

Direction Description

V_BUS

I

V_BUSstatus input. When this function is not enabled

via its corresponding PINSEL register, it is driven

HIGH internally.

USB_CONNECT

USB_UP_LED

USB_D+

O

SoftConnect control signal.

GoodLink LED control signal.

Positive differential data.

Negative differential data.

O

I/O

USB_D-

9. Clocking and power management

This section describes the clocking and power management features of the USB Device

Controller.

9.1 Power requirements

The USB protocol insists on power management by the device. This becomes very critical

if the device draws power from the bus (bus-powered device). The following constraints

should be met by a bus-powered device:

1. A device in the non-configured state should draw a maximum of 100 mA from the bus.

2. A configured device can draw only up to what is specified in the Max Power field of

the configuration descriptor. The maximum value is 500 mA.

3. A suspended device can draw a maximum of 2.5 mA.

9.2 Clocks

The USB device controller clocks are shown in Table 11–186

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Table 186. USB device controller clock sources

Clock source Description

AHB master clock

AHB slave clock

usbclk

Clock for the AHB master bus interface and DMA

Clock for the AHB slave interface

48 MHz clock from the dedicated USB PLL (PLL1) or the Main PLL (PLL0),

used to recover the 12 MHz clock from the USB bus

9.3 Power management support

To help conserve power, the USB device controller automatically disables the AHB master

clock and usbclk when not in use.

When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the

usbclk input to the device controller is automatically disabled, helping to conserve power.

However, if software wishes to access the device controller registers, usbclk must be

active. To allow access to the device controller registers while in the suspend state, the

USBClkCtrl and USBClkSt registers are provided.

When software wishes to access the device controller registers, it should first ensure

usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the

corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain

enabled until DEV_CLK_EN is cleared by software.

When a DMA transfer occurs, the device controller automatically turns on the AHB master

clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure

that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the

last DMA access, the AHB master clock is automatically disabled to help conserve power.

If desired, software also has the capability of forcing this clock to remain enabled using the

USBClkCtrl register.

Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is

set. When the device controller is not in use, all of the device controller clocks may be

disabled by clearing PCUSB.

The USB_NEED_CLK signal is used to facilitate going into and waking up from chip

Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt

register are asserted.

After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the

DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.

When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put

into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK

can be read from the USBIntSt register.

Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be

asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the

assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode.

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9.4 Remote wake-up

The USB device controller supports software initiated remote wake-up. Remote wake-up

involves resume signaling on the USB bus initiated from the device. This is done by

clearing the SUS bit in the SIE Set Device Status register. Before writing into the register,

all the clocks to the device controller have to be enabled using the USBClkCtrl register.

10. Register description

Table 11–187 shows the USB Device Controller registers directly accessible by the CPU.

The Serial Interface Engine (SIE) has other registers that are indirectly accessible via the

SIE command registers. See Section 11–12 “Serial interface engine command

description” for more info.

Table 187. USB device register map

Name

Description

Access Reset value^[1]Address

Clock control registers

USBClkCtrl

USB Clock Control

USB Clock Status

R/W

RO

0

0x5000 CFF4

0x5000 CFF8

USBClkSt

Device interrupt registers

USBIntSt

USB Interrupt Status

R/W

RO

0x8000 0000 0x400F C1C0

USBDevIntSt

USBDevIntEn

USBDevIntClr

USBDevIntSet

USBDevIntPri

USB Device Interrupt Status

USB Device Interrupt Enable

USB Device Interrupt Clear

USB Device Interrupt Set

USB Device Interrupt Priority

0x10

0x5000 C200

0x5000 C204

0x5000 C208

0x5000 C20C

0x5000 C22C

R/W

WO

0

Endpoint interrupt registers

USBEpIntSt

USBEpIntEn

USBEpIntClr

USBEpIntSet

USBEpIntPri

USB Endpoint Interrupt Status

RO

0

0x5000 C230

0x5000 C234

0x5000 C238

0x5000 C23C

0x5000 C240

USB Endpoint Interrupt Enable

USB Endpoint Interrupt Clear

USB Endpoint Interrupt Set

USB Endpoint Priority

R/W

WO

WO^[2]

Endpoint realization registers

USBReEp

USB Realize Endpoint

R/W

WO^[2]

0x3

0

0x5000 C244

0x5000 C248

0x5000 C24C

USBEpInd

USB Endpoint Index

USB MaxPacketSize

USBMaxPSize

USB transfer registers

USBRxData

R/W

0x8

USB Receive Data

RO

0

0x5000 C218

0x5000 C220

0x5000 C21C

0x5000 C224

0x5000 C228

USBRxPLen

USB Receive Packet Length

USB Transmit Data

RO

USBTxData

WO^[2]

R/W

USBTxPLen

USB Transmit Packet Length

USB Control

USBCtrl

SIE Command registers

USBCmdCode

USBCmdData

USB Command Code

USB Command Data

WO^[2]

RO

0

0x5000 C210

0x5000 C214

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Table 187. USB device register map

Name

Description

Access Reset value^[1]Address

DMA registers

USBDMARSt

USBDMARClr

USBDMARSet

USBUDCAH

USB DMA Request Status

RO

0

0x5000 C250

0x5000 C254

0x5000 C258

0x5000 C280

0x5000 C284

0x5000 C288

0x5000 C28C

0x5000 C290

0x5000 C294

0x5000 C2A0

0x5000 C2A4

0x5000 C2A8

0x5000 C2AC

0x5000 C2B0

0x5000 C2B4

0x5000 C2B8

0x5000 C2BC

0x5000 C2C0

USB DMA Request Clear

WO^[2]

R/W

USB DMA Request Set

USB UDCA Head

USBEpDMASt

USBEpDMAEn

USBEpDMADis

USBDMAIntSt

USBDMAIntEn

USBEoTIntSt

USBEoTIntClr

USBEoTIntSet

USBNDDRIntSt

USBNDDRIntClr

USBNDDRIntSet

USBSysErrIntSt

USBSysErrIntClr

USBSysErrIntSet

USB Endpoint DMA Status

RO

USB Endpoint DMA Enable

WO^[2]

RO

USB Endpoint DMA Disable

USB DMA Interrupt Status

USB DMA Interrupt Enable

R/W

RO

USB End of Transfer Interrupt Status

USB End of Transfer Interrupt Clear

USB End of Transfer Interrupt Set

USB New DD Request Interrupt Status

USB New DD Request Interrupt Clear

USB New DD Request Interrupt Set

USB System Error Interrupt Status

USB System Error Interrupt Clear

USB System Error Interrupt Set

WO^[2]

RO

WO^[2]

RO

WO^[2]

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

[2] Reading WO register will return an invalid value.

10.1 Clock control registers

10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4)

This register controls the clocking of the USB Device Controller. Whenever software

wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN

must be set. The PORTSEL_CLK_EN bit need only be set when accessing the OTGStCtrl

register (see Section 13–8.6) when the USB is used in OTG configuration.

The software does not have to repeat this exercise for every register access, provided that

the corresponding USBClkCtrl bits are already set. Note that this register is functional only

when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device

controller are disabled irrespective of the contents of this register. USBClkCtrl is a

read/write register.

Table 188. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description

Bit

Symbol

Description

Reset value

0

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

1

2

DEV_CLK_EN

-

Device clock enable. Enables the usbclk input to the device controller

0

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

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Table 188. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description

Bit

3

Symbol

Description

Reset value

PORTSEL_CLK_EN

Port select register clock enable.

AHB clock enable

NA

0

4

AHB_CLK_EN

-

31:5

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8)

This register holds the clock availability status. The bits of this register are ORed together

to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software

should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with

the register access. Software does not have to repeat this exercise for every access,

provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register.

Table 189. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description

Bit

Symbol

Description

Reset value

0

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

1

2

DEV_CLK_ON

-

Device clock on. The usbclk input to the device controller is active.

0

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

3

PORTSEL_CLK_ON

Port select register clock on.

AHB clock on.

NA

0

4

AHB_CLK_ON

-

31:5

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

10.2 Device interrupt registers

10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0)

The USB Device Controller has three interrupt lines. This register allows software to

determine their status with a single read operation. All three interrupt lines are ORed

together to a single channel of the vectored interrupt controller. This register also contains

the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write

register.

Table 190. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description

Bit

0

Symbol

Description

Reset value

USB_INT_REQ_LP

USB_INT_REQ_HP

Low priority interrupt line status. This bit is read-only.

High priority interrupt line status. This bit is read-only.

0

1

0

2

USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only.

0

7:3

-

Reserved, user software should not write ones to reserved bits. The value

NA

read from a reserved bit is not defined.

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Table 190. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description

Bit

Symbol

Description

Reset value

8

USB_NEED_CLK

USB need clock indicator. This bit is set to 1 when USB activity or a change

of state on the USB data pins is detected, and it indicates that a PLL supplied

clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets

to zero 5 ms after the last packet has been received/sent, or 2 ms after the

Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from

0 to 1 can wake up the microcontroller if activity on the USB bus is selected

to wake up the part from the Power-down mode (see Section 4–8.8

“Wake-up from Reduced Power Modes” for details). Also see Section 4–5.9

“PLL0 and Power-down mode” and Section 4–8.9 “Power Control for

Peripherals register (PCONP - 0x400F C0C4)” for considerations about the

PLL and invoking the Power-down mode. This bit is read-only.

1

30:9

31

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

1

EN_USB_INTS

Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt

Controller does not see the ORed output of the USB interrupt lines.

10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200)

The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and

1 indicates the presence of the interrupt. USBDevIntSt is a read-only register.

Table 191. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation

Reset value: 0x0000 0000

Bit

31

30

-

29

28

-

27

-

26

-

25

-

24

-

Symbol

Bit

-

23

22

-

21

20

-

19

-

18

-

17

-

16

-

Symbol

Bit

-

15

14

-

13

12

-

11

-

10

-

9

8

Symbol

Bit

-

5

ERR_INT EP_RLZED

7

6

4

3

2

1

0

Symbol

TxENDPKT

Rx

CDFULL

CCEMPTY DEV_STAT EP_SLOW

EP_FAST

FRAME

ENDPKT

Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description

Bit

0

Symbol

FRAME

EP_FAST

Description

Reset value

The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.

0

1

Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set,

the corresponding endpoint interrupt will be routed to this bit.

2

3

EP_SLOW

DEV_STAT

Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is

not set, the corresponding endpoint interrupt will be routed to this bit.

0

Set when USB Bus reset, USB suspend change or Connect change event occurs.

Refer to Section 11–12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on

page 245.

4

5

6

7

CCEMPTY

CDFULL

The command code register (USBCmdCode) is empty (New command can be written). 1

Command data register (USBCmdData) is full (Data can be read now).

0

RxENDPKT The current packet in the endpoint buffer is transferred to the CPU.

TxENDPKT

The number of data bytes transferred to the endpoint buffer equals the number of bytes

programmed in the TxPacket length register (USBTxPLen).

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Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description

Bit

Symbol

Description

Reset value

8

EP_RLZED

Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize

register (USBMaxPSize) is updated and the corresponding operation is completed.

0

9

ERR_INT

Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 11–12.9

“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 247

0

31:10 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204)

Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to

generate an interrupt on one of the interrupt lines when set. By default, the interrupt is

routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME

interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of

USBDevIntPri. USBDevIntEn is a read/write register.

Table 193. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation

Reset value: 0x0000 0000

Bit

31

30

-

29

28

-

27

-

26

-

25

-

24

-

Symbol

Bit

-

23

22

-

21

20

-

19

-

18

-

17

-

16

-

Symbol

Bit

-

15

14

-

13

12

-

11

-

10

-

9

8

Symbol

Bit

-

5

ERR_INT EP_RLZED

7

6

4

3

2

1

0

Symbol

TxENDPKT

Rx

CDFULL

CCEMPTY DEV_STAT EP_SLOW

EP_FAST

FRAME

ENDPKT

Table 194. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description

Bit

31:0 See

USBDevIntEn

Symbol

Value

Description

Reset value

0

1

No interrupt is generated.

0

An interrupt will be generated when the corresponding bit in the Device

Interrupt Status (USBDevIntSt) register (Table 11–191) is set. By default, the

interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either

the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP

interrupt line by changing the value of USBDevIntPri.

bit allocation

table above

10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208)

Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a

zero has no effect.

Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding

endpoint interrupts in USBEpIntSt should be cleared.

USBDevIntClr is a write-only register.

Table 195. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation

Reset value: 0x0000 0000

Bit

31

30

29

28

27

26

25

24

Symbol

-

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Bit

23

22

-

21

20

-

19

-

18

-

17

-

16

-

Symbol

Bit

-

15

14

-

13

12

-

11

-

10

-

9

8

Symbol

Bit

-

5

ERR_INT EP_RLZED

7

6

4

3

2

1

0

Symbol

TxENDPKT

Rx

CDFULL

CCEMPTY DEV_STAT EP_SLOW

EP_FAST

FRAME

ENDPKT

Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description

Bit

31:0 See

USBDevIntClr

Symbol

Value

Description

Reset value

0

1

No effect.

0

The corresponding bit in USBDevIntSt (Section 11–10.2.2) is cleared.

bit allocation

table above

10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C)

Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a

zero has no effect

USBDevIntSet is a write-only register.

Table 197. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation

Reset value: 0x0000 0000

Bit

31

30

-

29

28

-

27

-

26

-

25

-

24

-

Symbol

Bit

-

23

22

-

21

20

-

19

-

18

-

17

-

16

-

Symbol

Bit

-

15

14

-

13

12

-

11

-

10

-

9

8

Symbol

Bit

-

5

ERR_INT EP_RLZED

7

6

4

3

2

1

0

Symbol

TxENDPKT

Rx

CDFULL

CCEMPTY DEV_STAT EP_SLOW

EP_FAST

FRAME

ENDPKT

Table 198. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description

Bit Symbol Value Description

31:0 See

USBDevIntSet

Reset value

0

1

No effect.

0

The corresponding bit in USBDevIntSt (Section 11–10.2.2) is set.

bit allocation

table above

10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C)

Writing one to a bit in this register causes the corresponding interrupt to be routed to the

USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the

USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed

to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no

interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register.

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Table 199. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description

Bit

Symbol

Value Description

Reset

value

0

FRAME

0

1

0

1

FRAME interrupt is routed to USB_INT_REQ_LP.

0

FRAME interrupt is routed to USB_INT_REQ_HP.

EP_FAST interrupt is routed to USB_INT_REQ_LP.

EP_FAST interrupt is routed to USB_INT_REQ_HP.

1

EP_FAST

-

0

31:2

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

10.3 Endpoint interrupt registers

The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are

used in Slave mode operation.

10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230)

Each physical non-isochronous endpoint is represented by a bit in this register to indicate

that it has generated an interrupt. All non-isochronous OUT endpoints generate an

interrupt when they receive a packet without an error. All non-isochronous IN endpoints

generate an interrupt when a packet is successfully transmitted, or when a NAK

handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section

11–12.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 244). A bit set to one in

this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set

depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a

read-only register.

Note that for Isochronous endpoints, handling of packet data is done when the FRAME

interrupt occurs.

Table 200. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation

Reset value: 0x0000 0000

Bit

31

EP15TX

23

30

EP15RX

22

29

EP14TX

21

28

EP14RX

20

27

EP13TX

19

26

EP13RX

18

25

EP12TX

17

24

EP12RX

16

Symbol

Bit

Symbol

Bit

EP11TX

15

EP11RX

14

EP10TX

13

EP10RX

12

EP9TX

11

EP9RX

10

EP8TX

9

EP8RX

8

Symbol

Bit

EP7TX

7

EP7RX

6

EP6TX

5

EP6RX

4

EP5TX

3

EP5RX

2

EP4TX

1

EP4RX

0

Symbol

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description

Bit

0

Symbol

EP0RX

EP0TX

EP1RX

EP1TX

EP2RX

EP2TX

Description

Reset value

Endpoint 0, Data Received Interrupt bit.

Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 1, Data Received Interrupt bit.

Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 2, Data Received Interrupt bit.

Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.

0

1

2

3

4

5

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Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description

Bit

6

Symbol

EP3RX

EP3TX

EP4RX

EP4TX

EP5RX

EP5TX

EP6RX

EP6TX

EP7RX

EP7TX

EP8RX

EP8TX

EP9RX

EP9TX

EP10RX

EP10TX

EP11RX

EP11TX

EP12RX

EP12TX

EP13RX

EP13TX

EP14RX

EP14TX

EP15RX

EP15TX

Description

Reset value

Endpoint 3, Isochronous endpoint.

NA

0

7

Endpoint 3, Isochronous endpoint.

8

Endpoint 4, Data Received Interrupt bit.

Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 5, Data Received Interrupt bit.

Endpoint 5, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 6, Isochronous endpoint.

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

NA

0

Endpoint 6, Isochronous endpoint.

Endpoint 7, Data Received Interrupt bit.

Endpoint 7, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 8, Data Received Interrupt bit.

Endpoint 8, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 9, Isochronous endpoint.

0

NA

0

Endpoint 9, Isochronous endpoint.

Endpoint 10, Data Received Interrupt bit.

Endpoint 10, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 11, Data Received Interrupt bit.

Endpoint 11, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 12, Isochronous endpoint.

0

NA

0

Endpoint 12, Isochronous endpoint.

Endpoint 13, Data Received Interrupt bit.

Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 14, Data Received Interrupt bit.

Endpoint 14, Data Transmitted Interrupt bit or sent a NAK.

Endpoint 15, Data Received Interrupt bit.

Endpoint 15, Data Transmitted Interrupt bit or sent a NAK.

0

10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234)

Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set

when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the

corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated

endpoint. USBEpIntEn is a read/write register.

Table 202. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation

Reset value: 0x0000 0000

Bit

31

EP15TX

23

30

EP15RX

22

29

EP14TX

21

28

EP14RX

20

27

EP13TX

19

26

EP13RX

18

25

EP12TX

17

24

EP12RX

16

Symbol

Bit

Symbol

Bit

EP11TX

15

EP11RX

14

EP10TX

13

EP10RX

12

EP9TX

11

EP9RX

10

EP8TX

9

EP8RX

8

Symbol

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

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Bit

7

6

5

4

3

2

1

0

Symbol

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description

Bit Symbol Value Description

Reset value

31:0 See USBEpIntEn bit

allocation table above

0

The corresponding bit in USBDMARSt is set when an interrupt occurs

for this endpoint.

0

1

The corresponding bit in USBEpIntSt is set when an interrupt

occurs for this endpoint. Implies Slave mode for this endpoint.

10.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238)

Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt

command to be executed (Table 11–247) for the corresponding physical endpoint. Writing

zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the

CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the

CDFULL bit is set, USBCmdData contains the status of the endpoint, and the

corresponding bit in USBEpIntSt is cleared.

Notes:

• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be

set to ensure the corresponding interrupt has been cleared before proceeding.

• While setting multiple bits in USBEpIntClr simultaneously is possible, it is not

recommended; only the status of the endpoint corresponding to the least significant

interrupt bit cleared will be available at the end of the operation.

• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly

invoked using the SIE command registers, but using USBEpIntClr is recommended

because of its ease of use.

Each physical endpoint has its own reserved bit in this register. The bit field definition is

the same as that of USBEpIntSt shown in Table 11–200. USBEpIntClr is a write-only

register.

Table 204. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation

Reset value: 0x0000 0000

Bit

31

EP15TX

23

30

EP15RX

22

29

EP14TX

21

28

EP14RX

20

27

EP13TX

19

26

EP13RX

18

25

EP12TX

17

24

EP12RX

16

Symbol

Bit

Symbol

Bit

EP11TX

15

EP11RX

14

EP10TX

13

EP10RX

12

EP9TX

11

EP9RX

10

EP8TX

9

EP8RX

8

Symbol

Bit

EP7TX

7

EP7RX

6

EP6TX

5

EP6RX

4

EP5TX

3

EP5RX

2

EP4TX

1

EP4RX

0

Symbol

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

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Table 205. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description

Bit Symbol Value Description

Reset value

31:0 See USBEpIntClr bit

allocation table above

0

1

No effect.

0

Clears the corresponding bit in USBEpIntSt, by executing the SIE

Select Endpoint/Clear Interrupt command for this endpoint.

10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C)

Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero

has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write-only

register.

Table 206. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit allocation

Reset value: 0x0000 0000

Bit

31

EP15TX

23

30

EP15RX

22

29

EP14TX

21

28

EP14RX

20

27

EP13TX

19

26

EP13RX

18

25

EP12TX

17

24

EP12RX

16

Symbol

Bit

Symbol

Bit

EP11TX

15

EP11RX

14

EP10TX

13

EP10RX

12

EP9TX

11

EP9RX

10

EP8TX

9

EP8RX

8

Symbol

Bit

EP7TX

7

EP7RX

6

EP6TX

5

EP6RX

4

EP5TX

3

EP5RX

2

EP4TX

1

EP4RX

0

Symbol

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 207. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description

Bit Symbol Value Description

Reset value

31:0 See USBEpIntSet bit

allocation table above

0

1

No effect.

0

Sets the corresponding bit in USBEpIntSt.

10.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240)

This register determines whether an endpoint interrupt is routed to the EP_FAST or

EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed

to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST

or EP_SLOW is possible.

Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed

to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line.

USBEpIntPri is a write-only register.

Table 208. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation

Reset value: 0x0000 0000

Bit

31

EP15TX

23

30

EP15RX

22

29

EP14TX

21

28

E14RX

20

27

EP13TX

19

26

EP13RX

18

25

EP12TX

17

24

EP12RX

16

Symbol

Bit

Symbol

Bit

EP11TX

15

EP11RX

14

EP10TX

13

EP10RX

12

EP9TX

11

EP9RX

10

EP8TX

9

EP8RX

8

Symbol

Bit

EP7TX

7

EP7RX

6

EP6TX

5

EP6RX

4

EP5TX

3

EP5RX

2

EP4TX

1

EP4RX

0

Symbol

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

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Table 209. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description

Bit

Symbol

Value Description

Reset value

31:0 See USBEpIntPri bit

allocation table above

0

The corresponding interrupt is routed to the EP_SLOW bit of

USBDevIntSt

0

1

The corresponding interrupt is routed to the EP_FAST bit of

USBDevIntSt

10.4 Endpoint realization registers

The registers in this group allow realization and configuration of endpoints at run time.

10.4.1 EP RAM requirements

The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM

dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has

space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends

on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by

the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the

MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next

word boundary. Also, each buffer has one word header showing the size of the packet

length received.

The EP_ RAM space (in words) required for the physical endpoint can be expressed as

MaxPacketSize + 3

⎛

⎝

⎞

EPRAMspace =

+ 1 × dbstatus

-------------------------------------------------

⎠

4

where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.

Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is

N

TotalEPRAMspace = 32 +

EPRAMspace(n)

∑

n = 0

where N is the number of realized endpoints. Total EP_RAM space should not exceed

4096 bytes (4 kB, 1 kwords).

10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244)

Writing one to a bit in this register causes the corresponding endpoint to be realized.

Writing zeros causes it to be unrealized. This register returns to its reset state when a bus

reset occurs. USBReEp is a read/write register.

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Table 210. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation

Reset value: 0x0000 0003

Bit

31

EP31

23

30

EP30

22

29

EP29

21

28

EP28

20

27

EP27

19

26

EP26

18

25

EP25

17

24

EP24

16

Symbol

Bit

Symbol

Bit

EP23

15

EP22

14

EP21

13

EP20

12

EP19

11

EP18

10

EP17

9

EP16

8

Symbol

Bit

EP15

7

EP14

6

EP13

5

EP12

4

EP11

3

EP10

2

EP9

1

EP8

0

Symbol

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description

Bit

Symbol

Value

Description

Reset value

0

EP0

0

1

0

1

0

1

Control endpoint EP0 is not realized.

Control endpoint EP0 is realized.

Control endpoint EP1 is not realized.

Control endpoint EP1 is realized.

Endpoint EPxx is not realized.

Endpoint EPxx is realized.

1

EP1

1

0

31:2 EPxx

On reset, only the control endpoints are realized. Other endpoints, if required, are realized

by programming the corresponding bits in USBReEp. To calculate the required EP_RAM

space for the realized endpoints, see Section 11–10.4.1.

Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is

shown below.

Clear EP_RLZED bit in USBDevIntSt;

for every endpoint to be realized,

{

/* OR with the existing value of the Realize Endpoint register */

USBReEp |= (UInt32) ((0x1 << endpt));

/* Load Endpoint index Reg with physical endpoint no.*/

USBEpIn

= (UInt32) endpointnumber;

/* load the max packet size Register */

USBEpMaxPSize MPS;

=

/* check whether the EP_RLZED bit in the Device Interrupt Status register is set

*/

while (!(USBDevIntSt

{

& EP_RLZED))

/* wait until endpoint realization is complete */

}

/* Clear the EP_RLZED bit */

Clear EP_RLZED bit in USBDevIntSt;

}

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The device will not respond to any transactions to unrealized endpoints. The SIE

Configure Device command will only cause realized and enabled endpoints to respond to

transactions. For details see Table 11–242.

10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 C248)

Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is

in fact a register array. Hence before writing, this register is addressed through the

USBEpIn register.

The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize

will set the array element pointed to by USBEpIn. USBEpIn is a write-only register.

Table 212. USB Endpoint Index register (USBEpIn - address 0x5000 C248) bit description

Bit

Symbol

PHY_EP

-

Description

Reset value

4:0

Physical endpoint number (0-31)

0

31:5

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

10.4.4 USB MaxPacketSize register (USBMaxPSize - 0x5000 C24C)

On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other

endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer

addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At the

end, the EP_RLZED bit will be set in USBDevIntSt (Table 11–191). USBMaxPSize array

indexing is shown in Figure 11–27. USBMaxPSize is a read/write register.

Table 213. USB MaxPacketSize register (USBMaxPSize - address 0x5000 C24C) bit description

Bit

Symbol

Description

Reset value

9:0

MPS

The maximum packet size value.

0x008^[1]

31:10 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

[1] Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.

MPS_EP0

ENDPOINT INDEX

MPS_EP31

The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the

USBMaxPSize register.

Fig 27. USB MaxPacketSize register array indexing

10.5 USB transfer registers

The registers in this group are used for transferring data between endpoint buffers and

RAM in Slave mode operation. See Section 11–14 “Slave mode operation”.

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10.5.1 USB Receive Data register (USBRxData - 0x5000 C218)

For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before

reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register

should be set appropriately. On reading this register, data from the selected endpoint

buffer is fetched. The data is in little endian format: the first byte received from the USB

bus will be available in the least significant byte of USBRxData. USBRxData is a read-only

register.

Table 214. USB Receive Data register (USBRxData - address 0x5000 C218) bit description

Bit

Symbol

Description

Reset value

31:0 RX_DATA

Data received.

0x0000 0000

10.5.2 USB Receive Packet Length register (USBRxPLen - 0x5000 C220)

This register contains the number of bytes remaining in the endpoint buffer for the current

packet being read via the USBRxData register, and a bit indicating whether the packet is

valid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the

USBCtrl register should be set appropriately. This register is updated on each read of the

USBRxData register. USBRxPLen is a read-only register.

Table 215. USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description

Bit

Symbol

Value Description

Reset value

9:0

PKT_LNGTH

-

The remaining number of bytes to be read from the currently selected

0

endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be

set in USBDevIntSt.

10

DV

Data valid. This bit is useful for isochronous endpoints. Non-isochronous

endpoints do not raise an interrupt when an erroneous data packet is

received. But invalid data packet can be produced with a bus reset. For

isochronous endpoints, data transfer will happen even if an erroneous

packet is received. In this case DV bit will not be set for the packet.

0

1

-

Data is invalid.

Data is valid.

11

PKT_RDY

The PKT_LNGTH field is valid and the packet is ready for reading.

0

31:12 -

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

10.5.3 USB Transmit Data register (USBTxData - 0x5000 C21C)

For an IN transaction, the CPU writes the endpoint data into this register. Before writing to

this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be

set appropriately, and the packet length should be written to the USBTxPlen register. On

writing this register, the data is written to the selected endpoint buffer. The data is in little

endian format: the first byte sent on the USB bus will be the least significant byte of

USBTxData. USBTxData is a write-only register.

Table 216. USB Transmit Data register (USBTxData - address 0x5000 C21C) bit description

Bit

Symbol

Description

Reset value

31:0 TX_DATA

Transmit Data.

0x0000 0000

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10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224)

This register contains the number of bytes transferred from the CPU to the selected

endpoint buffer. Before writing data to USBTxData, software should first write the packet

length (≤ MaxPacketSize) to this register. After each write to USBTxData, hardware

decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl

register should be set to select the desired endpoint buffer before starting this process.

For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in

packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For

example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of

length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes

in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write-only

register.

Table 217. USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description

Bit

Symbol

Value Description

Reset value

9:0

PKT_LNGTH

-

The remaining number of bytes to be written to the selected endpoint buffer. 0x000

This field is decremented by 4 by hardware after each write to USBTxData.

When this field decrements to 0, the TxENDPKT bit will be set in

USBDevIntSt.

31:10 -

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

10.5.5 USB Control register (USBCtrl - 0x5000 C228)

This register controls the data transfer operation of the USB device. It selects the endpoint

buffer that is accessed by the USBRxData and USBTxData registers, and enables

reading and writing them. USBCtrl is a read/write register.

Table 218. USB Control register (USBCtrl - address 0x5000 C228) bit description

Bit

Symbol

Value Description

Read mode control. Enables reading data from the OUT endpoint buffer

Reset value

0

RD_EN

0

for the endpoint specified in the LOG_ENDPOINT field using the

USBRxData register. This bit is cleared by hardware when the last word

of the current packet is read from USBRxData.

0

1

Read mode is disabled.

Read mode is enabled.

1

WR_EN

Write mode control. Enables writing data to the IN endpoint buffer for the

endpoint specified in the LOG_ENDPOINT field using the USBTxData

register. This bit is cleared by hardware when the number of bytes in

USBTxLen have been sent.

0

1

-

Write mode is disabled.

Write mode is enabled.

Logical Endpoint number.

5:2

LOG_ENDPOINT

-

0x0

NA

31:6

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

10.6 SIE command code registers

The SIE command code registers are used for communicating with the Serial Interface

Engine. See Section 11–12 “Serial interface engine command description” for more

information.

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10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210)

This register is used for sending the command and write data to the SIE. The commands

written here are propagated to the SIE and executed there. After executing the command,

the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See

Section 11–12 for details. USBCmdCode is a write-only register.

Table 219. USB Command Code register (USBCmdCode - address 0x5000 C210) bit description

Bit

Symbol

Value Description

Reset value

7:0

-

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

15:8 CMD_PHASE

The command phase:

Read

0x00

0x01

0x02

0x05

Write

Command

23:16 CMD_CODE/

CMD_WDATA

This is a multi-purpose field. When CMD_PHASE is Command or Read,

this field contains the code for the command (CMD_CODE). When

CMD_PHASE is Write, this field contains the command write data

(CMD_WDATA).

0x00

31:24 -

-

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

10.6.2 USB Command Data register (USBCmdData - 0x5000 C214)

This register contains the data retrieved after executing a SIE command. When the data is

ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 11–191

for details. USBCmdData is a read-only register.

Table 220. USB Command Data register (USBCmdData - address 0x5000 C214) bit description

Bit

Symbol

Description

Reset value

7:0

CMD_RDATA

-

Command Read Data.

0x00

31:8

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

10.7 DMA registers

The registers in this group are used for the DMA mode of operation (see Section 11–15

“DMA operation”)

10.7.1 USB DMA Request Status register (USBDMARSt - 0x5000 C250)

A bit in this register associated with a non-isochronous endpoint is set by hardware when

an endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding

bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when the

corresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves as a

flag for the DMA engine to start the data transfer if the DMA is enabled for the

corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for

control endpoints (EP0 and EP1). USBDMARSt is a read-only register.

Table 221. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit allocation

Reset value: 0x0000 0000

Bit

31

30

29

28

27

26

25

24

Symbol

EP31

EP30

EP29

EP28

EP27

EP26

EP25

EP24

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Bit

23

EP23

15

22

EP22

14

21

EP21

13

20

EP20

12

19

EP19

11

18

EP18

10

17

EP17

9

16

EP16

8

Symbol

Bit

Symbol

Bit

EP15

7

EP14

6

EP13

5

EP12

4

EP11

3

EP10

2

EP9

1

EP8

0

Symbol

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Table 222. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description

Bit

Symbol

Value Description

Reset value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit

0

must be 0).

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit

must be 0).

0

31:2 EPxx

Endpoint xx (2 ≤ xx ≤ 31) DMA request.

DMA not requested by endpoint xx.

DMA requested by endpoint xx.

0

1

[1] DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.

10.7.2 USB DMA Request Clear register (USBDMARClr - 0x5000 C254)

Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt

register. Writing zero has no effect.

This register is intended for initialization prior to enabling the DMA for an endpoint. When

the DMA is enabled for an endpoint, hardware clears the corresponding bit in

USBDMARSt on completion of a packet transfer. Therefore, software should not clear the

bit using this register while the endpoint is enabled for DMA operation.

USBDMARClr is a write-only register.

The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 11–221).

Table 223. USB DMA Request Clear register (USBDMARClr - address 0x5000 C254) bit description

Bit

Symbol

Value Description

Reset value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0

0

bit must be 0).

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit

must be 0).

0

31:2 EPxx

Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request.

No effect.

0

1

Clear the corresponding bit in USBDMARSt.

10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258)

Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.

Writing zero has no effect.

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This register allows software to raise a DMA request. This can be useful when switching

from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA

mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is

not raised by hardware. Software can then use this register to manually start the DMA

transfer.

Software can also use this register to initiate a DMA transfer to proactively fill an IN

endpoint buffer before an IN token packet is received from the host.

USBDMARSet is a write-only register.

The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 11–221).

Table 224. USB DMA Request Set register (USBDMARSet - address 0x5000 C258) bit description

Bit

Symbol Value Description

Reset value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit

must be 0).

0

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must

be 0).

0

31:2 EPxx

Set the endpoint xx (2 ≤ xx ≤ 31) DMA request.

No effect.

0

1

Set the corresponding bit in USBDMARSt.

10.7.4 USB UDCA Head register (USBUDCAH - 0x5000 C280)

The UDCA (USB Device Communication Area) Head register maintains the address

where the UDCA is located in the RAM. Refer to Section 11–15.2 “USB device

communication area” and Section 11–15.4 “The DMA descriptor” for more details on the

UDCA and DMA descriptors. USBUDCAH is a read/write register.

Table 225. USB UDCA Head register (USBUDCAH - address 0x5000 C280) bit description

Bit

Symbol

Description

Reset value

6:0

-

Reserved. Software should not write ones to reserved bits. The UDCA is aligned to 0x00

128-byte boundaries.

31:7 UDCA_ADDR

Start address of the UDCA.

0

10.7.5 USB EP DMA Status register (USBEpDMASt - 0x5000 C284)

Bits in this register indicate whether DMA operation is enabled for the corresponding

endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in

this register. USBEpDMASt is a read-only register.

Table 226. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description

Bit

Symbol

Value Description

Reset value

0

EP0_DMA_ENABLE

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and

0

the EP0_DMA_ENABLE bit must be 0).

1

EP1_DMA_ENABLE

0

Control endpoint IN (DMA cannot be enabled for this endpoint and

the EP1_DMA_ENABLE bit must be 0).

0

31:2 EPxx_DMA_ENABLE

endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit.

The DMA for endpoint EPxx is disabled.

The DMA for endpoint EPxx is enabled.

0

1

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10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288)

Writing one to a bit to this register will enable the DMA operation for the corresponding

endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints

EP0 and EP1. USBEpDMAEn is a write-only register.

Table 227. USB EP DMA Enable register (USBEpDMAEn - address 0x5000 C288) bit description

Bit

Symbol

Value Description

Reset value

0

EP0_DMA_ENABLE

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and

0

the EP0_DMA_ENABLE bit value must be 0).

1

EP1_DMA_ENABLE

0

Control endpoint IN (DMA cannot be enabled for this endpoint and the

EP1_DMA_ENABLE bit must be 0).

0

31:2 EPxx_DMA_ENABLE

Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit.

No effect.

0

1

Enable the DMA operation for endpoint EPxx.

10.7.7 USB EP DMA Disable register (USBEpDMADis - 0x5000 C28C)

Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing

zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register

clears the internal DMA_PROCEED flag. Refer to Section 11–15.5.4 “Optimizing

descriptor fetch” for more information on the DMA_PROCEED flag. If a DMA transfer is in

progress for an endpoint when its corresponding bit is cleared, the transfer is completed

before the DMA is disabled. When an error condition is detected during a DMA transfer,

the corresponding bit is cleared by hardware. USBEpDMADis is a write-only register.

Table 228. USB EP DMA Disable register (USBEpDMADis - address 0x5000 C28C) bit description

Bit

Symbol

Value Description

Reset value

0

EP0_DMA_DISABLE

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and

0

the EP0_DMA_DISABLE bit value must be 0).

1

EP1_DMA_DISABLE

0

Control endpoint IN (DMA cannot be enabled for this endpoint and the

EP1_DMA_DISABLE bit value must be 0).

0

31:2 EPxx_DMA_DISABLE

Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit.

No effect.

0

1

Disable the DMA operation for endpoint EPxx.

10.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290)

Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt

status register are set. USBDMAIntSt is a read-only register.

Table 229. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description

Bit

Symbol

Value Description

End of Transfer Interrupt bit.

Reset value

0

EOT

0

1

All bits in the USBEoTIntSt register are 0.

At least one bit in the USBEoTIntSt is set.

New DD Request Interrupt bit.

1

NDDR

0

1

All bits in the USBNDDRIntSt register are 0.

At least one bit in the USBNDDRIntSt is set.

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Table 229. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description

Bit

Symbol

Value Description

System Error Interrupt bit.

Reset value

2

ERR

0

1

-

All bits in the USBSysErrIntSt register are 0.

At least one bit in the USBSysErrIntSt is set.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294)

Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to

generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn

is a read/write register.

Table 230. USB DMA Interrupt Enable register (USBDMAIntEn - address 0x5000 C294) bit description

Bit

Symbol

Value Description

End of Transfer Interrupt enable bit.

Reset value

0

EOT

0

1

The End of Transfer Interrupt is disabled.

The End of Transfer Interrupt is enabled.

New DD Request Interrupt enable bit.

The New DD Request Interrupt is disabled.

The New DD Request Interrupt is enabled.

System Error Interrupt enable bit.

1

NDDR

ERR

-

0

1

2

0

1

-

The System Error Interrupt is disabled.

The System Error Interrupt is enabled.

31:3

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)

When the DMA transfer completes for the current DMA descriptor, either normally

(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in

this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.

USBEoTIntSt is a read-only register.

Table 231. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description

Bit

Symbol

Value Description

Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.

Reset value

31:0 EPxx

0

1

There is no End of Transfer interrupt request for endpoint xx.

There is an End of Transfer Interrupt request for endpoint xx.

10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4)

Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt

register. Writing zero has no effect. USBEoTIntClr is a write-only register.

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Table 232. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description

Bit

Symbol

Value Description

Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.

No effect.

Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.

Reset value

31:0 EPxx

0

1

10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8)

Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.

Writing zero has no effect. USBEoTIntSet is a write-only register.

Table 233. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description

Bit

Symbol

Value Description

Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.

No effect.

Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.

Reset value

31:0 EPxx

0

1

10.7.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0x5000

C2AC)

A bit in this register is set when a transfer is requested from the USB device and no valid

DD is detected for the corresponding endpoint. USBNDDRIntSt is a read-only register.

Table 234. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description

Bit

Symbol

Value

Description

Reset value

31:0 EPxx

Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.

There is no new DD interrupt request for endpoint xx.

There is a new DD interrupt request for endpoint xx.

0

1

10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000

C2B0)

Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt

register. Writing zero has no effect. USBNDDRIntClr is a write-only register.

Table 235. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description

Bit

Symbol Value Description

Reset value

31:0 EPxx

Clear endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.

No effect.

0

1

Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.

10.7.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0x5000

C2B4)

Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt

register. Writing zero has no effect. USBNDDRIntSet is a write-only register

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Table 236. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description

Bit

Symbol

Value

Description

Reset value

31:0 EPxx

Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.

No effect.

0

1

Set the EPxx new DD interrupt request in the USBNDDRIntSt register.

10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8)

If a system error (AHB bus error) occurs when transferring the data or when fetching or

updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read-only

register.

Table 237. USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description

Bit

Symbol

Value

Description

Reset value

31:0 EPxx

Endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.

There is no System Error Interrupt request for endpoint xx.

There is a System Error Interrupt request for endpoint xx.

0

1

10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC)

Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt

register. Writing zero has no effect. USBSysErrIntClr is a write-only register.

Table 238. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description

Bit

Symbol Value

Description

Reset value

31:0 EPxx

Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.

No effect.

0

1

Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.

10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0)

Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt

register. Writing zero has no effect. USBSysErrIntSet is a write-only register.

Table 239. USB System Error Interrupt Set register (USBSysErrIntSet - address 0x5000 C2C0) bit description

Bit

Symbol

Value

Description

Reset value

31:0 EPxx

Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.

No effect.

0

1

Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.

11. Interrupt handling

This section describes how an interrupt event on any of the endpoints is routed to the

Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event

handling, see Figure 11–28.

All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an

interrupt when they receive a packet without an error. All non-isochronous IN endpoints

generate an interrupt when a packet has been successfully transmitted or when a NAK

signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see

Section 11–12.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.

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The interrupt handling is different for Slave and DMA mode.

Slave mode

If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the

USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For

non-isochronous endpoints, all endpoint interrupt events are divided into two types by the

corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint

interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in

the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the

EP_SLOW bit in USBDevIntSt.

For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.

The USBDevIntSt register holds the status of all endpoint interrupt events as well as the

status of various other interrupts (see Section 11–10.2.2). By default, all interrupts (if

enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt

register to request low priority interrupt handling. However, the USBDevIntPri register can

route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt

register.

Only one of the EP_FAST and FRAME interrupt events can be routed to the

USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both

interrupt events are routed to USB_INT_REQ_LP.

Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for

low priority interrupt handling by software.

The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the USBIntSt

register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set.

DMA mode

If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not

enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is

set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer

is enabled for the corresponding endpoint in the USBEpDMASt register.

Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End

of transfer interrupt, new DD request interrupt, and system error interrupt. These interrupt

events set a bit for each endpoint in the respective registers USBEoTIntSt,

USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints

are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request

interrupts and system error interrupt events are routed to the NDDR and ERR bits

respectively in the USBDMAStInt register.

The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the

USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in

USBIntSt, the interrupt is routed to the NVIC.

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interrupt

event on

EPn

Slave mode

from other

Endpoints

USBEpIntSt

USBDevIntSt

.

FRAME

EP_FAST

.

n

EP_SLOW

USBDevIntPri[0]

USBDevIntPri[1]

.

USBEpIntEn[n]

.

USBEpIntPri[n]

ERR_INT

USBDMARSt

n

USBIntSt

USB_INT_REQ_HP

to NVIC

USB_INT_REQ_LP

USB_INT_REQ_DMA

to DMA engine

EN_USB_INTS

USBEoTIntST

0

DMA Mode

.

31

USBNDDRIntSt

0

USBDMAIntSt

.

EOT

NDDR

ERR

.

31

USBSysErrIntSt

0

.

31

For simplicity, USBDevIntEn and USBDMAIntEn are not shown.

Fig 28. Interrupt event handling

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12. Serial interface engine command description

The functions and registers of the Serial Interface Engine (SIE) are accessed using

commands, which consist of a command code followed by optional data bytes (read or

write action). The USBCmdCode (Table 11–219) and USBCmdData (Table 11–220)

registers are used for these accesses.

A complete access consists of two phases:

1. Command phase: the USBCmdCode register is written with the CMD_PHASE field

set to the value 0x05 (Command), and the CMD_CODE field set to the desired

command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is

set.

2. Data phase (optional): for writes, the USBCmdCode register is written with the

CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with

the desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt

is set. For reads, USBCmdCode register is written with the CMD_PHASE field set to

the value 0x02 (Read), and the CMD_CODE field set with command code the read

corresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set,

indicating the data is available for reading in the USBCmdData register. In the case of

multi-byte registers, the least significant byte is accessed first.

An overview of the available commands is given in Table 11–240.

Here is an example of the Read Current Frame Number command (reading 2 bytes):

USBDevIntClr

USBCmdCode

while (!(USBDevIntSt

USBDevIntClr 0x10;

USBCmdCode 0x00F50200;

while (!(USBDevIntSt

=

0x30;

0x00F50500;

0x10)); // Wait for CCEMPTY.

// Clear both CCEMPTY

// CMD_CODE=0xF5, CMD_PHASE=0x05(Command)

& CDFULL

=

&

=

// Clear CCEMPTY interrupt bit.

// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)

=

&

0x20)); // Wait for CDFULL.

USBDevIntClr

CurFrameNum

=

0x20;

USBCmdData;

0x00F50200;

while (!(USBDevIntSt

Temp USBCmdData;

// Clear CDFULL.

// Read Frame number LSB byte.

// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)

=

USBCmdCode

=

&

0x20)); // Wait for CDFULL.

=

// Read Frame number MSB byte

// Clear CDFULL interrupt bit.

| (Temp << 8);

USBDevIntClr

CurFrameNum

=

0x20;

CurFrameNum

=

Here is an example of the Set Address command (writing 1 byte):

USBDevIntClr

USBCmdCode

while (!(USBDevIntSt

USBDevIntClr 0x10;

USBCmdCode 0x008A0100;

=

0x10;

// Clear CCEMPTY.

// CMD_CODE=0xD0, CMD_PHASE=0x05(Command)

0x10)); // Wait for CCEMPTY.

=

0x00D00500;

&

=

// Clear CCEMPTY.

// CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA),

// CMD_PHASE=0x01(Write)

=

while (!(USBDevIntSt

USBDevIntClr 0x10;

&

0x10)); // Wait for CCEMPTY.

// Clear CCEMPTY.

=

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Table 240. SIE command code table

Command name

Device commands

Set Address

Recipient

Code (Hex)

Data phase

Device

D0

D8

F3

F5

FD

FE

FF

FB

Write 1 byte

Read 1 or 2 bytes

Read 2 bytes

Write 1 byte

Read 1 byte

Configure Device

Set Mode

Read Current Frame Number

Read Test Register

Set Device Status

Get Device Status

Get Error Code

Read Error Status

Endpoint Commands

Select Endpoint

Endpoint 0

00

01

Read 1 byte (optional)

Read 1 byte

Endpoint 1

Endpoint xx

Endpoint 0

xx

Select Endpoint/Clear Interrupt

Set Endpoint Status

40

Endpoint 1

41

Read 1 byte

Endpoint xx

Endpoint 0

xx + 40

40

Read 1 byte

Write 1 byte

Endpoint 1

41

Write 1 byte

Endpoint xx

Selected Endpoint

xx + 40

F2

Write 1 byte

Clear Buffer

Read 1 byte (optional)

None

Validate Buffer

FA

12.1 Set Address (Command: 0xD0, Data: write 1 byte)

The Set Address command is used to set the USB assigned address and enable the

(embedded) function. The address set in the device will take effect after the status stage

of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is

set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default

endpoint).

Table 241. Set Address command bit description

Bit

6:0

7

Symbol

Description

Reset value

DEV_ADDR

DEV_EN

Device address set by the software. After a bus reset this field is set to 0x00.

Device Enable. After a bus reset this bit is set to 1.

0: Device will not respond to any packets.

0x00

0

1: Device will respond to packets for function address DEV_ADDR.

12.2 Configure Device (Command: 0xD8, Data: write 1 byte)

A value of 1 written to the register indicates that the device is configured and all the

enabled non-control endpoints will respond. Control endpoints are always enabled and

respond even if the device is not configured, in the default state.

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Table 242. Configure Device command bit description

Bit

Symbol

Description

Reset value

0

CONF_DEVICE

Device is configured. All enabled non-control endpoints will respond. This bit is

cleared by hardware when a bus reset occurs. When set, the UP_LED signal is

driven LOW if the device is not in the suspended state (SUS=0).

7:1

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

12.3 Set Mode (Command: 0xF3, Data: write 1 byte)

Table 243. Set Mode command bit description

Bit

Symbol

Value Description

Always PLL Clock.

Reset value

0

AP_CLK

0

USB_NEED_CLK is functional; the 48 MHz clock can be stopped when the

device enters suspend state.

1

USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be stopped when the

device enters suspend state.

1

2

3

4

5

6

7

INAK_CI

INAK_CO

INAK_II

INAK_IO^[1]

INAK_BI

INAK_BO^[2]

-

Interrupt on NAK for Control IN endpoint.

0

1

Only successful transactions generate an interrupt.

Both successful and NAKed IN transactions generate interrupts.

Interrupt on NAK for Control OUT endpoint.

0

1

Only successful transactions generate an interrupt.

Both successful and NAKed OUT transactions generate interrupts.

Interrupt on NAK for Interrupt IN endpoint.

0

1

Only successful transactions generate an interrupt.

Both successful and NAKed IN transactions generate interrupts.

Interrupt on NAK for Interrupt OUT endpoints.

0

1

Only successful transactions generate an interrupt.

Both successful and NAKed OUT transactions generate interrupts.

Interrupt on NAK for Bulk IN endpoints.

0

1

Only successful transactions generate an interrupt.

Both successful and NAKed IN transactions generate interrupts.

Interrupt on NAK for Bulk OUT endpoints.

0

1

-

Only successful transactions generate an interrupt.

Both successful and NAKed OUT transactions generate interrupts.

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

[1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.

[2] This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.

12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2

bytes)

Returns the frame number of the last successfully received SOF. The frame number is

eleven bits wide. The frame number returns least significant byte first. In case the user is

only interested in the lower 8 bits of the frame number, only the first byte needs to be read.

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• In case no SOF was received by the device at the beginning of a frame, the frame

number returned is that of the last successfully received SOF.

• In case the SOF frame number contained a CRC error, the frame number returned will

be the corrupted frame number as received by the device.

12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)

The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk

and AHB slave clock) are running.

12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)

The Set Device Status command sets bits in the Device Status Register.

Table 244. Set Device Status command bit description

Bit

Symbol

Value Description

The Connect bit indicates the current connect status of the device. It controls the

Reset value

0

CON

0

CONNECT output pin, used for SoftConnect. Reading the connect bit returns the

current connect status. This bit is cleared by hardware when the V_BUSstatus

input is LOW for more than 3 ms. The 3 ms delay filters out temporary dips in the

V_BUSvoltage.

0

1

Writing a 0 will make the CONNECT pin go HIGH.

Writing a 1 will make the CONNECT pin go LOW.

Connect Change.

1

2

CON_CH

SUS

0

1

This bit is cleared when read.

This bit is set when the device’s pull-up resistor is disconnected because V_BUS

disappeared. The DEV_STAT interrupt is generated when this bit is 1.

Suspend: The Suspend bit represents the current suspend state.

When the device is suspended (SUS = 1) and the CPU writes a 0 into it, the

device will generate a remote wake-up. This will only happen when the device is

connected (CON = 1). When the device is not connected or not suspended,

writing a 0 has no effect. Writing a 1 to this bit has no effect.

0

1

This bit is reset to 0 on any activity.

This bit is set to 1 when the device hasn’t seen any activity on its upstream port

for more than 3 ms.

3

SUS_CH

Suspend (SUS) bit change indicator. The SUS bit can toggle because:

• The device goes into the suspended state.

• The device is disconnected.

0

• The device receives resume signalling on its upstream port.

This bit is cleared when read.

0

1

SUS bit not changed.

SUS bit changed. At the same time a DEV_STAT interrupt is generated.

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Table 244. Set Device Status command bit description

Bit

Symbol

Value Description

Bus Reset bit. On a bus reset, the device will automatically go to the default

state. In the default state:

Reset value

4

RST

0

• Device is unconfigured.

• Will respond to address 0.

• Control endpoint will be in the Stalled state.

• All endpoints are unrealized except control endpoints EP0 and EP1.

• Data toggling is reset for all endpoints.

• All buffers are cleared.

• There is no change to the endpoint interrupt status.

• DEV_STAT interrupt is generated.

Note: Bus resets are ignored when the device is not connected (CON=0).

0

1

This bit is cleared when read.

This bit is set when the device receives a bus reset. A DEV_STAT interrupt is

generated.

7:5

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)

The Get Device Status command returns the Device Status Register. Reading the device

status returns 1 byte of data. The bit field definition is same as the Set Device Status

Register as shown in Table 11–244.

Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared

before executing the Get Device Status command.

12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)

Different error conditions can arise inside the SIE. The Get Error Code command returns

the last error code that occurred. The 4 least significant bits form the error code.

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Table 245. Get Error Code command bit description

Bit

Symbol Value Description

Reset value

3:0

EC

Error Code.

0x0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

-

No Error.

PID Encoding Error.

Unknown PID.

Unexpected Packet - any packet sequence violation from the specification.

Error in Token CRC.

Error in Data CRC.

Time Out Error.

Babble.

Error in End of Packet.

Sent/Received NAK.

Sent Stall.

Buffer Overrun Error.

Sent Empty Packet (ISO Endpoints only).

Bitstuff Error.

Error in Sync.

Wrong Toggle Bit in Data PID, ignored data.

The Error Active bit will be reset once this register is read.

4

EA

-

7:5

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

12.9 Read Error Status (Command: 0xFB, Data: read 1 byte)

This command reads the 8-bit Error register from the USB device. This register records

which error events have recently occurred in the SIE. If any of these bits are set, the

ERR_INT bit of USBDevIntSt is set. The error bits are cleared after reading this register.

Table 246. Read Error Status command bit description

Bit

0

Symbol

PID_ERR

UEPKT

DCRC

Description

Reset value

PID encoding error or Unknown PID or Token CRC.

0

1

Unexpected Packet - any packet sequence violation from the specification.

2

Data CRC error.

3

TIMEOUT

EOP

Time out error.

4

End of packet error.

Buffer Overrun.

5

B_OVRN

BTSTF

6

Bit stuff error.

7

TGL_ERR

Wrong toggle bit in data PID, ignored data.

12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))

The Select Endpoint command initializes an internal pointer to the start of the selected

buffer in EP_RAM. Optionally, this command can be followed by a data read, which

returns some additional information on the packet(s) in the endpoint buffer(s). The

command code of the Select Endpoint command is equal to the physical endpoint

number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.

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Table 247. Select Endpoint command bit description

Bit

Symbol

Value Description

Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s).

For IN endpoints, the FE bit gives the ANDed result of the B_1_FULL and

Reset value

0

FE

0

B_2_FULL bits. For OUT endpoints, the FE bit gives ORed result of the

B_1_FULL and B_2_FULL bits. For single buffered endpoints, this bit simply

reflects the status of B_1_FULL.

0

1

For an IN endpoint, at least one write endpoint buffer is empty.

For an OUT endpoint, at least one endpoint read buffer is full.

Stalled endpoint indicator.

1

2

ST

0

1

The selected endpoint is not stalled.

The selected endpoint is stalled.

STP

SETUP bit: the value of this bit is updated after each successfully received

packet (i.e. an ACKed package on that particular physical endpoint).

0

1

The STP bit is cleared by doing a Select Endpoint/Clear Interrupt on this

endpoint.

The last received packet for the selected endpoint was a SETUP packet.

Packet over-written bit.

3

4

PO

0

1

The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’ command.

The previously received packet was over-written by a SETUP packet.

EPN

EP NAKed bit indicates sending of a NAK. If the host sends an OUT packet to a

filled OUT buffer, the device returns NAK. If the host sends an IN token packet

to an empty IN buffer, the device returns NAK.

0

1

The EPN bit is reset after the device has sent an ACK after an OUT packet or

when the device has seen an ACK after sending an IN packet.

The EPN bit is set when a NAK is sent and the interrupt on NAK feature is

enabled.

5

6

7

B_1_FULL

B_2_FULL

-

The buffer 1 status.

Buffer 1 is empty.

Buffer 1 is full.

0

1

The buffer 2 status.

Buffer 2 is empty.

Buffer 2 is full.

0

1

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1

byte)

Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the

following differences:

• They clear the bit corresponding to the endpoint in the USBEpIntSt register.

• In case of a control OUT endpoint, they clear the STP and PO bits in the

corresponding Select Endpoint Register.

• Reading one byte is obligatory.

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Remark: This command may be invoked by using the USBCmdCode and USBCmdData

registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the

USBEpIntClr register is recommended.

12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte

(optional))

The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The

Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical

endpoint number in hex. Not all bits can be set for all types of endpoints.

Table 248. Set Endpoint Status command bit description

Bit

Symbol

Value Description

Stalled endpoint bit. A Stalled control endpoint is automatically unstalled when it

Reset value

0

ST

0

receives a SETUP token, regardless of the content of the packet. If the endpoint

should stay in its stalled state, the CPU can stall it again by setting this bit. When

a stalled endpoint is unstalled - either by the Set Endpoint Status command or by

receiving a SETUP token - it is also re-initialized. This flushes the buffer: in case

of an OUT buffer it waits for a DATA 0 PID; in case of an IN buffer it writes a DATA

0 PID. There is no change of the interrupt status of the endpoint. When already

unstalled, writing a zero to this bit initializes the endpoint. When an endpoint is

stalled by the Set Endpoint Status command, it is also re-initialized.

0

1

-

The endpoint is unstalled.

The endpoint is stalled.

4:1

5

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

0

DA

Disabled endpoint bit.

0

1

The endpoint is enabled.

The endpoint is disabled.

Rate Feedback Mode.

6

7

RF_MO

0

1

Interrupt endpoint is in the Toggle mode.

Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes

place without data toggle bit.

CND_ST

Conditional Stall bit.

0

1

Unstalls both control endpoints.

Stall both control endpoints, unless the STP bit is set in the Select Endpoint

register. It is defined only for control OUT endpoints.

12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))

When an OUT packet sent by the host has been received successfully, an internal

hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by

returning a NAK. When the device software has read the data, it should free the buffer by

issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the

buffer is cleared, new packets will be accepted.

When bit 0 of the optional data byte is 1, the previously received packet was over-written

by a SETUP packet. The Packet over-written bit is used only in control transfers.

According to the USB specification, a SETUP packet should be accepted irrespective of

the buffer status. The software should always check the status of the PO bit after reading

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the SETUP data. If it is set then it should discard the previously read data, clear the PO bit

by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and

again check the status of the PO bit.

See Section 11–14 “Slave mode operation” for a description of when this command is

used.

Table 249. Clear Buffer command bit description

Bit

Symbol Value Description

Reset value

0

PO

Packet over-written bit. This bit is only applicable to the control endpoint EP0.

0

1

-

The previously received packet is intact.

The previously received packet was over-written by a later SETUP packet.

7:1

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

12.14 Validate Buffer (Command: 0xFA, Data: none)

When the CPU has written data into an IN buffer, software should issue a Validate Buffer

command. This tells hardware that the buffer is ready for sending on the USB bus.

Hardware will send the contents of the buffer when the next IN token packet is received.

Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the

Validate Buffer command and cleared when the data has been sent on the USB bus and

the buffer is empty.

A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet

Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP

packet. For the control endpoint the validated buffer will be invalidated when a SETUP

packet is received.

See Section 11–14 “Slave mode operation” for a description of when this command is

used.

13. USB device controller initialization

The LPC17xx USB device controller initialization includes the following steps:

1. Enable the device controller by setting the PCUSB bit of PCONP.

2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk and

the desired frequency for cclk. For correct operation of synchronization logic in the

device controller, the minimum cclk frequency is 18 MHz. For the procedure for

determining the PLL setting and configuration, see Section 4–5.11 “Procedure for

determining PLL0 settings”.

3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits

in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until

they are set.

4. Enable the USB pin functions by writing to the corresponding PINSEL register.

5. Disable the pull-ups and pull-downs on the V_BUSpin using the corresponding

PINMODE register by putting the pin in the “pin has neither pull-up nor pull-down

resistor enabled” mode. See Section 8–4 “Pin mode select register values”.

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6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the

EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.

7. Enable endpoint interrupts (Slave mode):

– Clear all endpoint interrupts using USBEpIntClr.

– Clear any device interrupts using USBDevIntClr.

– Enable Slave mode for the desired endpoints by setting the corresponding bits in

USBEpIntEn.

– Set the priority of each enabled interrupt using USBEpIntPri.

– Configure the desired interrupt mode using the SIE Set Mode command.

– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,

and possibly EP_FAST).

8. Configure the DMA (DMA mode):

– Disable DMA operation for all endpoints using USBEpDMADis.

– Clear any pending DMA requests using USBDMARClr.

– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and

USBSysErrIntClr.

– Prepare the UDCA in system memory.

– Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0

0000).

– Enable the desired endpoints for DMA operation using USBEpDMAEn.

– Set EOT, DDR, and ERR bits in USBDMAIntEn.

9. Install USB interrupt handler in the NVIC by writing its address to the appropriate

vector table location and enabling the USB interrupt in the NVIC.

10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address

command. A bus reset will also cause this to happen.

11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status

command.

The configuration of the endpoints varies depending on the software application. By

default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional

endpoints are enabled and configured by software after a SET_CONFIGURATION or

SET_INTERFACE device request is received from the host.

14. Slave mode operation

In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the

Register Interface.

14.1 Interrupt generation

In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated

in response to an endpoint interrupt. Endpoint interrupts are enabled using the

USBEpIntEn register, and are observable in the USBEpIntSt register.

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All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a

packet without an error. All non-isochronous IN endpoints generate an interrupt when a

packet is successfully transmitted, or when a NAK handshake is sent on the bus and the

interrupt on NAK feature is enabled.

For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in

USBDevIntSt) occurs.

14.2 Data transfer for OUT endpoints

When the software wants to read the data from an endpoint buffer it should set the

RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the

USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,

and set the PKT_RDY bit (Table 11–215).

Software can now start reading the data from the USBRxData register (Table 11–214).

When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is

set in the USBDevSt register. Software now issues a Clear Buffer (refer to Table 11–249)

command. The endpoint is now ready to accept the next packet. For OUT isochronous

endpoints, the next packet will be received irrespective of whether the buffer has been

cleared. Any data not read from the buffer before the end of the frame is lost. See Section

11–16 “Double buffered endpoint operation” for more details.

If the software clears RD_EN before the entire packet is read, reading is terminated, and

the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the

data will be read from the beginning.

14.3 Data transfer for IN endpoints

When writing data to an endpoint buffer, WR_EN (Section 11–10.5.5 “USB Control

register (USBCtrl - 0x5000 C228)”) is set and software writes to the number of bytes it is

going to send in the packet to the USBTxPLen register (Section 11–10.5.4). It can then

write data continuously in the USBTxData register.

When the number of bytes programmed in USBTxPLen have been written to USBTxData,

the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register.

Software issues a Validate Buffer (Section 11–12.14 “Validate Buffer (Command: 0xFA,

Data: none)”) command. The endpoint is now ready to send the packet. For IN

isochronous endpoints, the data in the buffer will be sent only if the buffer is validated

before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the

next frame. If the software clears WR_EN before the entire packet is written, writing will

start again from the beginning the next time WR_EN is set for this endpoint.

Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.

Interleaved read and write operation is possible.

15. DMA operation

In DMA mode, the DMA transfers data between RAM and the endpoint buffer.

The following sections discuss DMA mode operation. Background information is given in

sections Section 11–15.2 “USB device communication area” and Section 11–15.3

“Triggering the DMA engine”. The fields of the DMA Descriptor are described in Section

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11–15.4 “The DMA descriptor”. The last three sections describe DMA operation: Section

11–15.5 “Non-isochronous endpoint operation”, Section 11–15.6 “Isochronous endpoint

operation”, and Section 11–15.7 “Auto Length Transfer Extraction (ATLE) mode

operation”.

15.1 Transfer terminology

Within this section three types of transfers are mentioned:

1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers

to these simply as transfers. Within this section they are referred to as USB transfers

to distinguish them from DMA transfers. A USB transfer is composed of transactions.

Each transaction is composed of packets.

2. DMA transfers – the transfer of data between an endpoint buffer and system memory

(RAM).

3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of

data between an endpoint buffer and system memory (RAM). A DMA transfer is

composed of one or more packet transfers.

15.2 USB device communication area

The CPU and DMA controller communicate through a common area of memory, called the

USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA

Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP

points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs

for unrealized endpoints and endpoints disabled for DMA operation are ignored and can

be set to a NULL (0x0) value.

The start address of the UDCA is stored in the USBUDCAH register. The UDCA can

reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA

controller.

Figure 11–29 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH)

register and DMA Descriptors.

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UDCA

NULL

0

NULL

Next_DD_pointer

DD-EP2-a

Next_DD_pointer

DD-EP2-b

Next_DD_pointer

DD-EP2-c

1

2

DDP-EP2

NULL

UDCA HEAD

REGISTER

NULL

Next_DD_pointer

DD-EP16-a

Next_DD_pointer

DD-EP16-b

16

31

DDP-EP16

DDP-EP31

Fig 29. UDCA Head register and DMA Descriptors

15.3 Triggering the DMA engine

An endpoint raises a DMA request when Slave mode is disabled by setting the

corresponding bit in the USBEpIntEn register to 0 (Section 11–10.3.2) and an endpoint

interrupt occurs (see Section 11–10.7.1 “USB DMA Request Status register (USBDMARSt

- 0x5000 C250)”).

A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in

USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for

the endpoint.

All endpoints share a single DMA channel to minimize hardware overhead. If more than

one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint

number is processed first.

In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT

endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command

(Section 11–12.3).

15.4 The DMA descriptor

DMA transfers are described by a data structure called the DMA Descriptor (DD).

DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at

word-aligned addresses.

DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints

are five words long.

The parameters associated with a DMA transfer are:

• The start address of the DMA buffer

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• The length of the DMA buffer

• The start address of the next DMA descriptor

• Control information

• Count information (number of bytes transferred)

• Status information

Table 11–250 lists the DMA descriptor fields.

Table 250. DMA descriptor

Word

position

Access

(H/W)

Access

(S/W)

Bit

position

Description

0

1

R

R/W

-

31:0

1:0

2

Next_DD_pointer

R

DMA_mode (00 -Normal; 01 - ATLE)

Next_DD_valid (1 - valid; 0 - invalid)

Reserved

R

-

3

R

R/W

4

Isochronous_endpoint (1 - isochronous; 0 - non-isochronous)

Max_packet_size

R

15:5

31:16

R/W^[1]

DMA_buffer_length

This value is specified in bytes for non-isochronous endpoints and in

number of packets for isochronous endpoints.

2

3

R/W

W

R/W

R/I

31:0

0

DMA_buffer_start_addr

DD_retired (To be initialized to 0)

DD_status (To be initialized to 0000):

0000 - NotServiced

R/I

4:1

0001 - BeingServiced

0010 - NormalCompletion

0011 - DataUnderrun (short packet)

1000 - DataOverrun

1001 - SystemError

W

R/I

W

5

Packet_valid (To be initialized to 0)

LS_byte_extracted (ATLE mode) (To be initialized to 0)

MS_byte_extracted (ATLE mode) (To be initialized to 0)

Message_length_position (ATLE mode)

Reserved

W

6

W

7

R

13:8

15:14

31:16

31:0

-

R/W

R/I

R/W

Present_DMA_count (To be initialized to 0)

Isochronous_packetsize_memory_address

4

[1] Write-only in ATLE mode

Legend: R - Read; W - Write; I - Initialize

15.4.1 Next_DD_pointer

Pointer to the memory location from where the next DMA descriptor will be fetched.

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15.4.2 DMA_mode

Specifies the DMA mode of operation. Two modes have been defined: Normal and

Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes

the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is

extracted from the incoming data. See Section 11–15.7 “Auto Length Transfer Extraction

(ATLE) mode operation” on page 261 for more details.

15.4.3 Next_DD_valid

This bit indicates whether the software has prepared the next DMA descriptor. If set, the

DMA engine fetches the new descriptor when it is finished with the current one.

15.4.4 Isochronous_endpoint

When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence

5 words have to be read when fetching it.

15.4.5 Max_packet_size

The maximum packet size of the endpoint. This parameter is used while transferring the

data for IN endpoints from the memory. It is used for OUT endpoints to detect the short

packet. This is applicable to non-isochronous endpoints only. This field should be set to

the same MPS value that is assigned for the endpoint using the USBMaxPSize register.

15.4.6 DMA_buffer_length

This indicates the depth of the DMA buffer allocated for transferring the data. The DMA

engine will stop using this descriptor when this limit is reached and will look for the next

descriptor.

In Normal mode operation, software sets this value for both IN and OUT endpoints. In

ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints,

hardware sets this value using the extracted length of the data stream.

For isochronous endpoints, DMA_buffer_length is specified in number of packets, for

non-isochronous endpoints in bytes.

15.4.7 DMA_buffer_start_addr

The address where the data is read from or written to. This field is updated each time the

DMA engine finishes transferring a packet.

15.4.8 DD_retired

This bit is set by hardware when the DMA engine finishes the current descriptor. This

happens when the end of the buffer is reached, a short packet is transferred

(non-isochronous endpoints), or an error condition is detected.

15.4.9 DD_status

The status of the DMA transfer is encoded in this field. The following codes are defined:

• NotServiced - No packet has been transferred yet.

• BeingServiced - At least one packet is transferred.

• NormalCompletion - The DD is retired because the end of the buffer is reached and

there were no errors. The DD_retired bit is also set.

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• DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is

terminated because a short packet is received. The DD_retired bit is also set.

• DataOverrun - The end of the DMA buffer is reached in the middle of a packet

transfer. This is an error situation. The DD_retired bit is set. The present DMA count

field is equal to the value of DMA_buffer_length. The packet must be re-transmitted

from the endpoint buffer in another DMA transfer. The corresponding

EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.

• SystemError - The DMA transfer being serviced is terminated because of an error on

the AHB bus. The DD_retired bit is not set in this case. The corresponding

EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen

while updating the DD, the DD fields in RAM may be unreliable.

15.4.10 Packet_valid

This bit is used for isochronous endpoints. It indicates whether the last packet transferred

to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was

received without errors. See Section 11–15.6 “Isochronous endpoint operation” on page

259 for isochronous endpoint operation.

This bit is unnecessary for non-isochronous endpoints because a DMA request is

generated only for packets without errors, and thus Packet_valid will always be set when

the request is generated.

15.4.11 LS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of

the transfer length has been extracted. The extracted size is reflected in the

DMA_buffer_length field, bits 23:16.

15.4.12 MS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of

the transfer size has been extracted. The size extracted is reflected in the

DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and

MS_byte_extracted bits are set.

15.4.13 Present_DMA_count

The number of bytes transferred by the DMA engine. The DMA engine updates this field

after completing each packet transfer.

For isochronous endpoints, Present_DMA_count is the number of packets transferred; for

non-isochronous endpoints, Present_DMA_count is the number of bytes.

15.4.14 Message_length_position

Used in ATLE mode. This field gives the offset of the message length position embedded

in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates

that the message length starts from the first byte of the first packet.

15.4.15 Isochronous_packetsize_memory_address

The memory buffer address where the packet size information along with the frame

number has to be transferred or fetched. See Figure 11–30. This is applicable to

isochronous endpoints only.

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15.5 Non-isochronous endpoint operation

15.5.1 Setting up DMA transfers

Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled

for DMA transfer. These DDs are present in on-chip RAM. The start address of the first

DD is programmed into the DMA Description pointer (DDP) location for the corresponding

endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in

the USBEpDMAEn register (Section 11–10.7.6).The DMA_mode bit field in the descriptor

is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in

Table 11–250.

DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).

15.5.2 Finding DMA Descriptor

When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first

determine whether a new descriptor has to the fetched or not. A new descriptor does not

have to be fetched if the last packet transferred was for the same endpoint and the DD is

not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this

condition (see Section 11–15.5.4 “Optimizing descriptor fetch” on page 258).

If a new descriptor has to be read, the DMA engine will calculate the location of the DDP

for this endpoint and will fetch the start address of the DD from this location. A DD start

address at location zero is considered invalid. In this case the NDDR interrupt is raised.

All other word-aligned addresses are considered valid.

When the DD is fetched, the DD status word (word 3) is read first and the status of the

DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the

DMA engine will read the control word (word 1) of the DD.

If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)

of the DD and load it to the DDP. The new DDP is written to the UDCA area.

The full DD (4 words) will then be fetched from the address in the DDP. The DD will give

the details of the DMA transfer to be done. The DMA engine will load its hardware

resources with the information fetched from the DD (start address, DMA count etc.).

If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR

interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.

15.5.3 Transferring the data

For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and

transferred to on-chip RAM memory locations starting from DMA_buffer_start_addr. For

IN endpoints, the data is fetched from on-chip RAM at DMA_buffer_start_addr and written

to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are updated

after each packet is transferred.

15.5.4 Optimizing descriptor fetch

A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a

new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet

transfer, hardware sets an internal flag called DMA_PROCEED.

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The DMA_PROCEED flag is cleared after the required number of bytes specified in the

DMA_buffer_length field is transferred. It is also cleared when the software writes into the

USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to

to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the

USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation

for any endpoint.

15.5.5 Ending the packet transfer

On completing a packet transfer, the DMA engine writes back the DD with updated status

information to the same memory location from where it was read. The

DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are

updated.

A DD can have the following types of completion:

Normal completion - If the current packet is fully transferred and the

Present_DMA_count field equals the DMA_buffer_length, the DD has completed

normally. The DD will be written back to memory with DD_retired set and DD_status set

to NormalCompletion. The EOT interrupt is raised for this endpoint.

USB transfer end completion - If the current packet is fully transferred and its size is

less than the Max_packet_size field, and the end of the DMA buffer is still not reached,

the USB transfer end completion occurs. The DD will be written back to the memory

with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT

interrupt is raised for this endpoint.

Error completion - If the current packet is partially transferred i.e. the end of the DMA

buffer is reached in the middle of the packet transfer, an error situation occurs. The DD

is written back with DD_retired set and DD_status set to the DataOverrun status code.

The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt

register is cleared. The packet will be re-sent from the endpoint buffer to memory when

the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn

register.

15.5.6 No_Packet DD

For an IN transfer, if the system does not have any data to send for a while, it can respond

to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the

Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a

No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt

corresponding to the endpoint without transferring a packet. The DD is retired with a

status code of NormalCompletion. This can be repeated as often as necessary. The

device will respond to IN token packets on the USB bus with a NAK until a DD with a data

packet is programmed and the DMA transfers the packet into the endpoint buffer.

15.6 Isochronous endpoint operation

For isochronous endpoints, the packet size can vary for each packet. There is one packet

per isochronous endpoint for each frame.

15.6.1 Setting up DMA transfers

Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of

the Isochronous_packetsize_memory_address field. All other fields are initialized the

same as for non-isochronous endpoints.

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For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in

frames rather than bytes.

15.6.2 Finding the DMA Descriptor

Finding the descriptors is done in the same way as that for a non-isochronous endpoint.

A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME

interrupt. On processing the request, the DMA engine will fetch the descriptor and if

Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address

from the fifth word of the DD.

15.6.3 Transferring the Data

The data is transferred to or from the memory location DMA_buffer_start_addr. After the

end of the packet transfer the Present_DMA_count value is incremented by 1.

The isochronous packet size is stored in memory as shown in Figure 11–30. Each word in

the packet size memory shown is divided into fields: Frame_number (bits 31 to 17),

Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet

size memory for a given DD should be DMA_buffer_length words in size – one word for

each packet to transfer.

OUT endpoints

At the completion of each frame, the packet size is written to the address location in

Isochronous_packet_size_memory_address, and

Isochronous_packet_size_memory_address is incremented by 4.

IN endpoints

Only the Packet_length field of the isochronous packet size word is used. For each frame,

an isochronous data packet of size specified by this field is transferred from the USB

device to the host, and Isochronous_packet_size_memory_address is incremented by 4

at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by

the USB device.

15.6.4 DMA descriptor completion

DDs for isochronous endpoints can only end with a status code of NormalCompletion

since there is no short packet on Isochronous endpoints, and the USB transfer continues

indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous

endpoints.

15.6.5 Isochronous OUT Endpoint Operation Example

Assume that an isochronous endpoint is programmed for the transfer of 10 frames and

that the transfer begins when the frame number is 21. After transferring four frames with

packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map

appear as shown in Figure 11–30.

The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35.

The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.

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Next_DD_Pointer

W0

NULL

DMA_buffer_length

Max_packet_size

Isochronous_endpoint

Next_DD_Valid

DMA_mode

W1

W2

0x000A

0x0

1

0

DMA_buffer_start_addr

0x80000000

Present_DMA_Count

ATLE settings

Packet_Valid

DD_Status

DD_Retired

W3

W4

NA

0x0

0

0x0

Isocronous_packetsize_memory_address

0x60000000

after 4 packets

0x0

W0

W1

W2

W3

W4

0x000A0010

0x80000035

FULL

0x4

-

0x1

0

frame_ number Packet_Valid Packet_Length

EMPTY

31

16

15

0

0x60000010

21

22

23

24

1

10

15

8

20

data memory

packet size memory

Fig 30. Isochronous OUT endpoint operation example

15.7 Auto Length Transfer Extraction (ATLE) mode operation

Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are

capable of concatenating small USB transfers (delta transfers) to form a single large USB

transfer. For OUT USB transfers, the device hardware has to break up this concatenated

transfer back into the original delta transfers and transfer them to separate DMA buffers.

This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE)

mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only.

OUT transfers in ATLE mode

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data to be sent

by host driver

data in packets

as seen on USB

data to be stored in

RAM by DMA engine

DMA_buffer_start_addr

of DD1

160 bytes

64 bytes

160 bytes

32 bytes

100 bytes

64 bytes

4 bytes

DMA_buffer_start_addr

of DD2

Fig 31. Data transfer in ATLE mode

Figure 11–31 shows a typical OUT USB transfer in ATLE mode, where the host

concatenates two USB transfers of 160 bytes and 100 bytes, respectively. Given a

MaxPacketSize of 64, the device hardware interprets this USB transfer as four packets of

64 bytes and a short packet of 4 bytes. The third and fourth packets are concatenated.

Note that in Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32,

and 64 and 36 bytes.

It is now the responsibility of the DMA engine to separate these two USB transfers and put

them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1

(DD1) and DMA Descriptor 2 (DD2).

Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the

USB transfer) specified by Message_length_position from the incoming data packets and

writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the

DMA_buffer_length are extracted in the event they are split between two packets, the

flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective

byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the

normal mode.

The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when

preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again

for the next DD.

If DD1 is retired during the transfer of a concatenated packet (such as the third packet in

Figure 11–31), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1

is retired with DD_status set to the DataOverrun status code. This is treated as an error

condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared by

hardware.

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In ATLE mode, the last buffer length to be transferred always ends with a short or empty

packet indicating the end of the USB transfer. If the concatenated transfer lengths are

such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host

will send an empty packet to mark the end of the USB transfer.

IN transfers in ATLE mode

For IN USB transfers from the device to the host, DMA_buffer_length is set by the device

software as in normal mode.

In ATLE mode, the device concatenates data from multiple DDs to form a single USB

transfer. If a DD is retired in the middle of a packet (packet size is less than

MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the

remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s

buffer.

If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer

length for the current DD has completed before the MaxPacketSize packet boundary, then

the available bytes from current DD are sent as a short packet on USB, which marks the

end of the USB transfer for the host.

If the last buffer length completes on a MaxPacketSize packet boundary, the device

software must program the next DD with DMA_buffer_length field 0, so that an empty

packet is sent by the device to mark the end of the USB transfer for the host.

15.7.1 Setting up the DMA transfer

For OUT endpoints, the host hardware needs to set the field Message_length_position in

the DD. This indicates the start location of the message length in the incoming data

packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT

endpoints because this field is updated by the device hardware after the extraction of the

buffer length.

For IN endpoints, descriptors are set in the same way as in normal mode operation.

Since a single packet can be split between two DDs, software should always keep two

DDs ready, except for the last DMA transfer which ends with a short or empty packet.

15.7.2 Finding the DMA Descriptor

DMA descriptors are found in the same way as the normal mode operation.

15.7.3 Transferring the Data

OUT endpoints

If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the

hardware will extract the transfer length from the data stream and program

DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and

MS_byte_extracted bits will be set.

IN endpoints

The DMA transfer proceeds as in normal mode and continues until the number of bytes

transferred equals the DMA_buffer_length.

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15.7.4 Ending the packet transfer

The DMA engine proceeds with the transfer until the number of bytes specified in the field

DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be

generated. If this happens in the middle of the packet, the linked DD will get loaded and

the remaining part of the packet gets transferred to or from the address pointed by the

new DD.

OUT endpoints

If the linked DD is not valid and the packet is partially transferred to memory, the DD ends

with DataOverrun status code set, and the DMA will be disabled for this endpoint.

Otherwise DD_status will be updated with the NormalCompletion status code.

IN endpoints

If the linked DD is not valid and the packet is partially transferred to USB, the DD ends

with a status code of NormalCompletion in the DD_status field. This situation corresponds

to the end of the USB transfer, and the packet will be sent as a short packet. Also, when

the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the

end of the USB transfer.

16. Double buffered endpoint operation

The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to

increase data throughput.

When a double-buffered endpoint is realized, enough space for both endpoint buffers is

automatically allocated in the EP_RAM. See Section 11–10.4.1.

For the following discussion, the endpoint buffer currently accessible to the CPU or DMA

engine for reading or writing is said to be the active buffer.

16.1 Bulk endpoints

For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or

Validate Buffer commands.

The following example illustrates how double buffering works for a Bulk OUT endpoint in

Slave mode:

Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is

B_1.

1. The host sends a data packet to the endpoint. The device hardware puts the packet

into B_1, and generates an endpoint interrupt.

2. Software clears the endpoint interrupt and begins reading the packet data from B_1.

While B_1 is still being read, the host sends a second packet, which device hardware

places in B_2, and generates an endpoint interrupt.

3. Software is still reading from B_1 when the host attempts to send a third packet. Since

both B_1 and B_2 are full, the device hardware responds with a NAK.

4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer

command to free B_1 to receive another packet. B_2 becomes the active buffer.

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5. Software sends the SIE Select Endpoint command to read the Select Endpoint

Register and test the FE bit. Software finds that the active buffer (B_2) has data

(FE=1). Software clears the endpoint interrupt and begins reading the contents of

B_2.

6. The host re-sends the third packet which device hardware places in B_1. An endpoint

interrupt is generated.

7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer

command to free B_2 to receive another packet. B_1 becomes the active buffer.

Software waits for the next endpoint interrupt to occur (it already has been generated

back in step 6).

8. Software responds to the endpoint interrupt by clearing it and begins reading the third

packet from B_1.

9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer

command to free B_1 to receive another packet. B_2 becomes the active buffer.

10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).

11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.

The active buffer is now B_2. The next data packet sent by the host will be placed in

B_2.

The following example illustrates how double buffering works for a Bulk IN endpoint in

Slave mode:

Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is

B_1. The interrupt on NAK feature is enabled.

1. The host requests a data packet by sending an IN token packet. The device responds

with a NAK and generates an endpoint interrupt.

2. Software clears the endpoint interrupt. The device has three packets to send.

Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The

active buffer is switched to B_2.

3. Software sends the SIE Select Endpoint command to read the Select Endpoint

Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the

second packet. Software sends a SIE Validate Buffer command, and the active buffer

is switched to B_1.

4. Software waits for the endpoint interrupt to occur.

5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint

interrupt occurs.

6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and

validates it using the SIE Validate Buffer command. The active buffer is switched to

B_2.

7. The device successfully sends the second packet from B_2 and generates an

endpoint interrupt.

8. Software has no more packets to send, so it simply clears the interrupt.

9. The device successfully sends the third packet from B_1 and generates an endpoint

interrupt.

10. Software has no more packets to send, so it simply clears the interrupt.

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11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by

software will go into B_2.

In DMA mode, switching of the active buffer is handled automatically in hardware. For

Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double

buffering can be accomplished by manually starting a packet transfer using the

USBDMARSet register.

16.2 Isochronous endpoints

For isochronous endpoints, the active data buffer is switched by hardware when the

FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do not

cause the active buffer to be switched.

Double buffering allows the software to make full use of the frame interval writing or

reading a packet to or from the active buffer, while the packet in the other buffer is being

sent or received on the bus.

For an OUT isochronous endpoint, any data not read from the active buffer before the end

of the frame is lost when it switches.

For an IN isochronous endpoint, if the active buffer is not validated before the end of the

frame, an empty packet is sent on the bus when the active buffer is switched, and its

contents will be overwritten when it becomes active again.

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Chapter 12: LPC17xx USB Host controller

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User manual

1. How to read this chapter

The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758,

LPC1756, and LPC1754. On these devices, the USB controller can be configured for

device, Host, or OTG operation.

2. Basic configuration

The USB controller is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the

USB clock or with the Main PLL (PLL0). See Section 4–6.1.

3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to

PINMODE5 (Section 8–5).

4. Wake-up: Activity on the USB bus port can wake up the microcontroller from

Power-down mode, see Section 4–8.8.

5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

6. Initialization: see Section 13–11.

3. Introduction

This section describes the host portion of the USB 2.0 OTG dual role core which

integrates the host controller (OHCI compliant), device controller, and I²C interface. The

I²C interface controls the external OTG ATX.

The USB is a 4 wire bus that supports communication between a host and a number (127

max.) of peripherals. The host controller allocates the USB bandwidth to attached devices

through a token based protocol. The bus supports hot plugging, un-plugging and dynamic

configuration of the devices. All transactions are initiated by the host controller.

The host controller enables data exchange with various USB devices attached to the bus.

It consists of register interface, serial interface engine and DMA controller. The register

interface complies to the OHCI specification.

Table 251. USB (OHCI) related acronyms and abbreviations used in this chapter

Acronym/abbreviation

Description

AHB

ATX

DMA

FS

Advanced High-Performance Bus

Analog Transceiver

Direct Memory Access

Full Speed

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Table 251. USB (OHCI) related acronyms and abbreviations used in this chapter

Acronym/abbreviation

Description

LS

Low Speed

OHCI

USB

Open Host Controller Interface

Universal Serial Bus

3.1 Features

• OHCI compliant.

• OpenHCI specifies the operation and interface of the USB Host Controller and SW

Driver

– USBOperational: Process Lists and generate SOF Tokens.

– USBReset: Forces reset signaling on the bus, SOF disabled.

– USBSuspend: Monitor USB for wake-up activity.

– USBResume: Forces resume signaling on the bus.

• The Host Controller has four USB states visible to the SW Driver.

• HCCA register points to Interrupt and Isochronous Descriptors List.

• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.

3.2 Architecture

The architecture of the USB host controller is shown below in Figure 12–32.

register

interface

(AHB slave)

REGISTER

INTERFACE

ATX

CONTROL

LOGIC/

PORT

HOST

CONTROLLER

USB

port

DMA interface

(AHB master)

BUS

MASTER

INTERFACE

USB

ATX

MUX

USB HOST BLOCK

Fig 32. USB Host controller block diagram

4. Interfaces

The USB interface is controlled by the OTG controller. It has one USB port.

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4.1 Pin description

Table 252. USB Host port pins

Pin name

Direction

Description

Type

USB_D+

I/O

O

I

Positive differential data

Negative differential data

GoodLink LED control signal

Port power enable

USB Connector

Control

USB_D−

USB_UP_LED

USB_PPWR

USB_PWRD

USB_OVRCR

Host power switch

Port power status

I

Over-current status

4.1.1 USB host usage note

The USB block can be configured as USB host. For details on how to connect the USB

port, see the USB OTG chapter, Section 13–7.

The USB device/host/OTG controller is disabled after RESET and must be enabled by

writing a 1 to the PCUSB bit in the PCONP register, see Table 4–46.

4.2 Software interface

The software interface of the USB host block consists of a register view and the format

definitions for the endpoint descriptors. For details on these two aspects see the OHCI

specification. The register map is shown in the next subsection.

4.2.1 Register map

The following registers are located in the AHB clock ‘cclk’ domain. They can be accessed

directly by the processor. All registers are 32-bit wide and aligned in the word address

boundaries.

Table 253. USB Host register address definitions

Name

Address

R/W^[1]Function

Reset value

HcRevision

0x5000 C000

R

BCD representation of the version of the HCI

0x10

specification that is implemented by the Host Controller.

HcControl

0x5000 C004

0x5000 C008

R/W

Defines the operating modes of the HC.

0x0

HcCommandStatus

This register is used to receive the commands from the 0x0

Host Controller Driver (HCD). It also indicates the status

of the HC.

HcInterruptStatus

HcInterruptEnable

0x5000 C00C R/W

Indicates the status on various events that cause

hardware interrupts by setting the appropriate bits.

0x0

0x5000 C010

0x5000 C014

R/W

Controls the bits in the HcInterruptStatus register and

indicates which events will generate a hardware

interrupt.

0x0

HcInterruptDisable

The bits in this register are used to disable

corresponding bits in the HCInterruptStatus register and

in turn disable that event leading to hardware interrupt.

0x0

HcHCCA

0x5000 C018

0x5000 C01C

R/W

R

Contains the physical address of the host controller

communication area.

HcPeriodCurrentED

Contains the physical address of the current isochronous 0x0

or interrupt endpoint descriptor.

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Table 253. USB Host register address definitions …continued

Name

Address

R/W^[1]Function

Reset value

HcControlHeadED

0x5000 C020

R/W

Contains the physical address of the first endpoint

descriptor of the control list.

0x0

HcControlCurrentED

HcBulkHeadED

HcBulkCurrentED

HcDoneHead

0x5000 C024

0x5000 C028

R/W

Contains the physical address of the current endpoint

descriptor of the control list

Contains the physical address of the first endpoint

descriptor of the bulk list.

0x5000 C02C R/W

Contains the physical address of the current endpoint

descriptor of the bulk list.

0x5000 C030

0x5000 C034

R

Contains the physical address of the last transfer

descriptor added to the ‘Done’ queue.

HcFmInterval

R/W

Defines the bit time interval in a frame and the full speed 0x2EDF

maximum packet size which would not cause an

overrun.

HcFmRemaining

HcFmNumber

0x5000 C038

0x5000 C03C

R

A 14-bit counter showing the bit time remaining in the

current frame.

0x0

Contains a 16-bit counter and provides the timing

reference among events happening in the HC and the

HCD.

0x0

HcPeriodicStart

HcLSThreshold

0x5000 C040

0x5000 C044

0x5000 C048

R/W

Contains a programmable 14-bit value which determines 0x0

the earliest time HC should start processing a periodic

list.

Contains 11-bit value which is used by the HC to

determine whether to commit to transfer a maximum of

8-byte LS packet before EOF.

0x628h

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

First of the two registers which describes the

characteristics of the root hub.

0xFF000902

0x60000h

0x5000 C04C R/W

Second of the two registers which describes the

characteristics of the Root Hub.

0x5000 C050

R/W

This register is divided into two parts. The lower D-word 0x0

represents the hub status field and the upper word

represents the hub status change field.

HcRhPortStatus[1]

HcRhPortStatus[2]

0x5000 C054

R/W

Controls and reports the port events on a per-port basis. 0x0

Controls and reports the port events on a per port basis. 0x0

0x5000 C058 R/W

Module_ID/Ver_Rev_ID 0x5000 C0FC

R

IP number, where yy (0x00) is unique version number

and zz (0x00) is a unique revision number.

0x3505yyzz

[1] The R/W column in Table 12–253 lists the accessibility of the register:

a) Registers marked ‘R’ for access will return their current value when read.

b) Registers marked ‘R/W’ allow both read and write.

4.2.2 USB Host Register Definitions

Refer to the OHCI specification document on the Compaq website for register definitions.

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Chapter 13: LPC17xx USB OTG controller

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1. How to read this chapter

The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758,

LPC1756, and LPC1754. On these devices, the USB controller can be configured for

device, Host, or OTG operation.

2. Basic configuration

The USB controller is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

2. Clock: The USB clock can generated using the dedicated USB PLL (PLL1) or with the

Main PLL (PLL0). See Section 4–6.1.

3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to

PINMODE5 (Section 8–5).

4. Wake-up: Activity on the USB bus port can wake up the microcontroller from

Power-down mode (see Section 13–10.2 and Section 4–8.8).

5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

6. Initialization: see Section 13–11.

3. Introduction

This chapter describes the OTG and I²C portions of the USB 2.0 OTG dual role device

controller which integrates the (OHCI) host controller, device controller, and I²C. The I²C

interface that is part of the USB block is intended to control an external OTG transceiver,

and is not the same as the I²C peripherals described in Section 19–1.

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the

capability of existing mobile devices and USB peripherals by adding host functionality for

connection to USB peripherals. The specification and more information on USB OTG can

be found on the USB Implementers Forum web site.

4. Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP and SRP.

• Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

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5. Architecture

The architecture of the USB OTG controller is shown below in the block diagram.

The host, device, OTG, and I²C controllers can be programmed through the register

interface. The OTG controller enables dynamic switching between host and device roles

through the HNP protocol. One port may be connected to an external OTG transceiver to

support an OTG connection. The communication between the register interface and an

external OTG transceiver is handled through an I²C interface and through the external

OTG transceiver interrupt signal.

For USB connections that use the device or host controller only (not OTG), the ports use

an embedded USB Analog Transceiver (ATX).

OTG

TRANSCEIVER

register

interface

I2C

CONTROLLER

(AHB slave)

REGISTER

INTERFACE

USB

port

OTG

CONTROLLER

USB

ATX

CONTROL

LOGIC/

PORT

DEVICE

CONTROLLER

DMA interface

(AHB master)

BUS

MASTER

INTERFACE

MUX

HOST

CONTROLLER

USB OTG BLOCK

EP_RAM

Fig 33. USB OTG controller block diagram

6. Modes of operation

The OTG controller is capable of operating in the following modes:

• Host mode (see Figure 13–34)

• Device mode (see Figure 13–35)

• OTG mode (see Figure 13–36)

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7. Pin configuration

The OTG controller has one USB port.

Table 254. USB OTG port pins

Pin name

USB_D+

Direction

Description

Pin category

I/O

O

Positive differential data

Negative differential data

GoodLink LED control signal

I²C serial clock

USB Connector

Control

USB_D−

USB_UP_LED

USB_SCL

USB_SDA

I/O

External OTG transceiver

I²C serial data

The following figures show different ways to realize connections to an USB device. The

example described here uses an ISP1302 (ST-Ericsson) for the external OTG transceiver

and the USB Host power switch LM3526-L (National Semiconductors).

7.1 Connecting the USB port to an external OTG transceiver

For OTG functionality an external OTG transceiver must be connected to the LPC17xx:

Use the internal USB transceiver for USB signalling and use the external OTG transceiver

for OTG functionality only (see Figure 13–34). This option uses the internal transceiver in

VP/VM mode.

V

DD

VBUS

ID

RSTOUT

RESET_N

ADR/PSW

OE_N/INT_N

SPEED

33 Ω

DP

V

DD

Mini-AB

connector

DM

ISP1302

SUSPEND

V

LPC17xx

SSIO,

SCL

SDA

USB_SCL

USB_SDA

EINTn

V

SSCORE

INT_N

USB_D+

USB_D−

USB_UP_LED

V

DD

Fig 34. USB OTG port configuration

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7.2 Connecting USB as a host

The USB port is connected as host using an embedded USB transceiver. There is no

OTG functionality on the port.

V

DD

USB_UP_LED

V

SS

33 Ω

D+

USB_D+

USB_D−

D−

USB-A

connector

15 kΩ

LPC176x

V

DD

V

USB_PWRD

USB_OVRCR

BUS

USB_PPWR

FLAGA

OUTA

ENA

5 V

LM3526-L

IN

graphicID

Fig 35. USB host port configuration

7.3 Connecting USB as device

The USB port is connected as device. There is no OTG functionality on the USB port.

V

DD

USB_UP_LED

V

DD

USB_CONNECT

LPC176x

V

SS

33 Ω

USB_D+

D+

USB-B

connector

D−

USB_D−

V

BUS

V

BUS

graphicID

Fig 36. USB device port configuration

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8. Register description

The OTG and I²C registers are summarized in the following table.

The Device and Host registers are explained in Table 12–253 and Table 11–187 in the

USB Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits

wide and aligned to word address boundaries.

Table 255. USB OTG and I²C register address definitions

Name

Description

Access Reset value

Address

Interrupt register

USBIntSt

USB Interrupt Status

R/W

0x8000 0100

0x400F C1C0

OTG registers

OTGIntSt

OTG Interrupt Status

OTG Interrupt Enable

OTG Interrupt Set

OTG Interrupt Clear

OTG Status and Control

OTG Timer

RO

0

0x5000 C100

0x5000 C104

0x5000 C108

0x5000 C10C

0x5000 C110

0x5000 C114

OTGIntEn

OTGIntSet

OTGIntClr

OTGStCtrl

OTGTmr

R/W

WO

R/W

0

NA

0

0xFFFF

I²C registers

I2C_RX

I²C Receive

I²C Transmit

I²C Status

I²C Control

I²C Clock High

I²C Clock Low

RO

NA

0x5000 C300

0x5000 C304

0x5000 C308

0x5000 C30C

0x5000 C310

I2C_TX

WO

RO

NA

I2C_STS

0x0A00

0

I2C_CTL

R/W

WO

I2C_CLKHI

I2C_CLKLO

0xB9

Clock control registers

OTGClkCtrl

OTGClkSt

OTG clock controller

OTG clock status

R/W

RO

0

0x5000 CFF4

0x5000 CFF8

8.1 USB Interrupt Status Register (USBIntSt - 0x5000 C1C0)

The USB OTG controller has seven interrupt lines. This register allows software to

determine their status with a single read operation.

The interrupt lines are ORed together to a single channel of the vectored interrupt

controller.

Table 256. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description

Bit

Symbol

Description

Reset

Value

0

1

2

3

4

5

USB_INT_REQ_LP

USB_INT_REQ_HP

USB_INT_REQ_DMA

USB_HOST_INT

USB_ATX_INT

Low priority interrupt line status. This bit is read-only.

High priority interrupt line status. This bit is read-only.

DMA interrupt line status. This bit is read-only.

USB host interrupt line status. This bit is read-only.

External ATX interrupt line status. This bit is read-only.

OTG interrupt line status. This bit is read-only.

0

USB_OTG_INT

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Table 256. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description

Bit

Symbol

Description

Reset

Value

6

7

USB_I2C_INT

-

I²C module interrupt line status. This bit is read-only.

0

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

8

USB_NEED_CLK

-

USB need clock indicator. This bit is read-only.

1

30:9

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

31

EN_USB_INTS

Enable all USB interrupts. When this bit is cleared, the

NVIC does not see the ORed output of the USB interrupt

lines.

1

8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100)

Bits in this register are set by hardware when the interrupt event occurs during the HNP

handoff sequence. See Section 13–9 for more information on when these bits are set.

Table 257. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description

Bit

Symbol

Description

Reset

Value

0

1

TMR

Timer time-out.

Remove pull-up.

0

REMOVE_PU

This bit is set by hardware to indicate that software

needs to disable the D+ pull-up resistor.

2

HNP_FAILURE

HNP failed.

0

This bit is set by hardware to indicate that the HNP

switching has failed.

3

HNP_SUCCESS

-

HNP succeeded.

0

This bit is set by hardware to indicate that the HNP

switching has succeeded.

31:4

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104)

Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate

an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT

interrupt line in the USBIntSt register.

The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.

8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C)

Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.

Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.

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8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C)

Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt

register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in

OTGIntSt.

8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110)

The OTGStCtrl register allows enabling hardware tracking during the HNP hand over

sequence, controlling the OTG timer, monitoring the timer count, and controlling the

functions mapped to port U1 and U2.

Time critical events during the switching sequence are controlled by the OTG timer. The

timer can operate in two modes:

1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section

13–8.7 “OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set in

OTGIntSt, and the timer will be disabled.

2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see

Section 13–8.7 “OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set,

and the timer value is reloaded into the counter. The timer is not disabled in this

mode.

Table 258. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description

Bit

Symbol

Description

Reset

Value

1:0

PORT_FUNC

Controls port function. Bit 0 is set or cleared by hardware

when B_HNP_TRACK or A_HNP_TRACK is set and

HNP succeeds. See Section 13–9. Bit 1 is reserved.

-

3:2

TMR_SCALE

TMR_MODE

Timer scale selection. This field determines the duration 0x0

of each timer count.

00: 10 μs (100 KHz)

01: 100 μs (10 KHz)

10: 1000 μs (1 KHz)

11: Reserved

4

Timer mode selection.

0: monoshot

0

1: free running

5

6

TMR_EN

Timer enable. When set, TMR_CNT increments. When

cleared, TMR_CNT is reset to 0.

0

TMR_RST

Timer reset. Writing one to this bit resets TMR_CNT to 0.

This provides a single bit control for the software to

restart the timer when the timer is enabled.

7

8

9

-

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

0

B_HNP_TRACK

A_HNP_TRACK

Enable HNP tracking for B-device (peripheral), see

Section 13–9. Hardware clears this bit when

HNP_SUCCESS or HNP_FAILURE is set.

Enable HNP tracking for A-device (host), see

Section 13–9. Hardware clears this bit when

HNP_SUCCESS or HNP_FAILURE is set.

0

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Table 258. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description

Bit

Symbol

Description

Reset

Value

10

PU_REMOVED

When the B-device changes its role from peripheral to

host, software sets this bit when it removes the D+

pull-up, see Section 13–9. Hardware clears this bit when

HNP_SUCCESS or HNP_FAILURE is set.

0

15:11

-

Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

NA

31:16 TMR_CNT

Current timer count value.

0x0

8.7 OTG Timer Register (OTGTmr - 0x5000 C114)

Table 259. OTG Timer register (OTGTmr - address 0x5000 C114) bit description

Bit

Symbol

Description

Reset

Value

15:0 TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value. 0xFFFF

31:16 -

Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

NA

8.8 OTG Clock Control Register (OTGClkCtrl - 0x5000 CFF4)

This register controls the clocking of the OTG controller. Whenever software wants to

access the registers, the corresponding clock control bit needs to be set. The software

does not have to repeat this exercise for every register access, provided that the

corresponding OTGClkCtrl bits are already set.

Table 260. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit

description

Bit

Symbol

Value Description

Reset

Value

0

HOST_CLK_EN

Host clock enable

0

1

Disable the Host clock.

Enable the Host clock.

Device clock enable

Disable the Device clock.

Enable the Device clock.

I²C clock enable

1

2

3

DEV_CLK_EN

I2C_CLK_EN

OTG_CLK_EN

0

1

2

0

1

Disable the I C clock.

2

Enable the I C clock.

OTG clock enable

0

1

Disable the OTG clock.

Enable the OTG clock.

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Table 260. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit

description

Bit

Symbol

Value Description

Reset

Value

4

AHB_CLK_EN

AHB master clock enable

0

Disable the AHB clock.

Enable the AHB clock.

1

31:5

-

NA

Reserved, user software should not write ones NA

to reserved bits. The value read from a

reserved bit is not defined.

8.9 OTG Clock Status Register (OTGClkSt - 0x5000 CFF8)

This register holds the clock availability status. When enabling a clock via OTGClkCtrl,

software should poll the corresponding bit in this register. If it is set, then software can go

ahead with the register access. Software does not have to repeat this exercise for every

access, provided that the OTGClkCtrl bits are not disturbed.

Table 261. OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description

Bit

Symbol

Value Description

Reset

Value

0

HOST_CLK_ON

Host clock status.

0

1

Host clock is not available.

Host clock is available.

Device clock status.

1

DEV_CLK_ON

I2C_CLK_ON

OTG_CLK_ON

AHB_CLK_ON

-

0

1

Device clock is not available.

Device clock is available.

I²C clock status.

I²C clock is not available.

I²C clock is available.

OTG clock status.

2

0

1

3

0

1

OTG clock is not available.

OTG clock is available.

AHB master clock status.

AHB clock is not available.

AHB clock is available.

4

0

1

31:5

NA

Reserved, user software should not write ones NA

to reserved bits. The value read from a

reserved bit is not defined.

8.10 I²C Receive Register (I2C_RX - 0x5000 C300)

This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx

FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO

gives unpredictable data results.

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Table 262. I²C Receive register (I2C_RX - address 0x5000 C300) bit description

Bit

Symbol

Description

Reset

Value

7:0

RX Data

Receive data.

-

8.11 I²C Transmit Register (I2C_TX - 0x5000 C300)

This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.

The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure

occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.

I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]

are ignored for master-receive operations. The master-receiver must write a dummy byte

to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is

set or the START bit is set to cause a RESTART condition on a byte written to the TX

FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,

the last byte of a master-receive operation is not acknowledged.

Table 263. I²C Transmit register (I2C_TX - address 0x5000 C300) bit description

Bit

Symbol

Description

Reset

Value

7:0

8

TX Data

START

STOP

-

Transmit data.

-

When 1, issue a START condition before transmitting this byte.

When 1, issue a STOP condition after transmitting this byte.

9

31:10

Reserved. User software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

8.12 I²C Status Register (I2C_STS - 0x5000 C304)

The I2C_STS register provides status information on the TX and RX blocks as well as the

current state of the external buses. Individual bits are enabled as interrupts by the

I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.

Table 264. I²C status register (I2C_STS - address 0x5000 C304) bit description

Bit

Symbol Value Description

Reset

Value

0

TDI

AFI

Transaction Done Interrupt. This flag is set if a transaction

completes successfully. It is cleared by writing a one to bit 0 of

the status register. It is unaffected by slave transactions.

0

1

Transaction has not completed.

Transaction completed.

1

Arbitration Failure Interrupt. When transmitting, if the SDA is low

0

2

when SDAOUT is high, then this I C has lost the arbitration to

another device on the bus. The Arbitration Failure bit is set when

this happens. It is cleared by writing a one to bit 1 of the status

register.

0

1

No arbitration failure on last transmission.

Arbitration failure occurred on last transmission.

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Table 264. I²C status register (I2C_STS - address 0x5000 C304) bit description

Bit

Symbol Value Description

Reset

Value

2

NAI

No Acknowledge Interrupt. After every byte of data is sent, the

0

transmitter expects an acknowledge from the receiver. This bit is

set if the acknowledge is not received. It is cleared when a byte

is written to the master TX FIFO.

0

1

Last transmission received an acknowledge.

Last transmission did not receive an acknowledge.

3

4

5

DRMI

Master Data Request Interrupt. Once a transmission is started,

the transmitter must have data to transmit as long as it isn’t

followed by a stop condition or it will hold SCL low until more

data is available. The Master Data Request bit is set when the

master transmitter is data-starved. If the master TX FIFO is

empty and the last byte did not have a STOP condition flag, then

SCL is held low until the CPU writes another byte to transmit.

This bit is cleared when a byte is written to the master TX FIFO.

0

1

Master transmitter does not need data.

Master transmitter needs data.

DRSI

Slave Data Request Interrupt. Once a transmission is started,

the transmitter must have data to transmit as long as it isn’t

followed by a STOP condition or it will hold SCL low until more

data is available. The Slave Data Request bit is set when the

slave transmitter is data-starved. If the slave TX FIFO is empty

and the last byte transmitted was acknowledged, then SCL is

held low until the CPU writes another byte to transmit. This bit is

cleared when a byte is written to the slave Tx FIFO.

0

1

Slave transmitter does not need data.

Slave transmitter needs data.

Active

Indicates whether the bus is busy. This bit is set when a START

condition has been seen. It is cleared when a STOP condition is

seen..

0

6

7

8

SCL

SDA

RFF

The current value of the SCL signal.

The current value of the SDA signal.

-

Receive FIFO Full (RFF). This bit is set when the RX FIFO is full

and cannot accept any more data. It is cleared when the RX

FIFO is not full. If a byte arrives when the Receive FIFO is full,

the SCL is held low until the CPU reads the RX FIFO and makes

room for it.

0

1

RX FIFO is not full

RX FIFO is full

9

RFE

TFF

Receive FIFO Empty. RFE is set when the RX FIFO is empty

and is cleared when the RX FIFO contains valid data.

1

0

1

RX FIFO contains data.

RX FIFO is empty

10

Transmit FIFO Full. TFF is set when the TX FIFO is full and is

cleared when the TX FIFO is not full.

0

1

TX FIFO is not full.

TX FIFO is full

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Table 264. I²C status register (I2C_STS - address 0x5000 C304) bit description

Bit

Symbol Value Description

Reset

Value

11

TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty

1

and is cleared when the TX FIFO contains valid data.

TX FIFO contains valid data.

0

1

TX FIFO is empty

31:12

-

NA

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

8.13 I²C Control Register (I2C_CTL - 0x5000 C308)

The I2C_CTL register is used to enable interrupts and reset the I²C state machine.

Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set.

Table 265. I²C Control register (I2C_CTL - address 0x5000 C308) bit description

Bit Symbol Value Description

Reset

Value

2

0

1

TDIE

AFIE

Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I C

issued a STOP condition.

0

1

Disable the TDI interrupt.

Enable the TDI interrupt.

Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is

asserted during transmission when trying to set SDA high, but the bus is driven low by

another device.

0

1

Disable the AFI.

Enable the AFI.

2

3

NAIE

Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling

that transmitted byte was not acknowledged.

0

1

Disable the NAI.

Enable the NAI.

DRMIE

Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which

signals that the master transmitter has run out of data, has not issued a STOP, and is

holding the SCL line low.

0

1

Disable the DRMI interrupt.

Enable the DRMI interrupt.

4

5

DRSIE

REFIE

Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which

signals that the slave transmitter has run out of data and the last byte was acknowledged,

so the SCL line is being held low.

0

1

Disable the DRSI interrupt.

Enable the DRSI interrupt.

Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to

indicate that the receive FIFO cannot accept any more data.

0

1

Disable the RFFI.

Enable the RFFI.

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Table 265. I²C Control register (I2C_CTL - address 0x5000 C308) bit description

Bit Symbol Value Description

Reset

Value

6

RFDAIE

Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that

data is available in the receive FIFO (i.e. not empty).

0

1

Disable the DAI.

Enable the DAI.

7

TFFIE

Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt

to indicate that the more data can be written to the transmit FIFO. Note that this is not full.

It is intended help the CPU to write to the I C block only when there is room in the FIFO

0

2

and do this without polling the status register.

0

1

Disable the TFFI.

Enable the TFFI.

8

SRST

Soft reset. This is only needed in unusual circumstances. If a device issues a start

condition without issuing a stop condition. A system timer may be used to reset the I C if

0

2

the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx

FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset

to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are

NOT modified by a soft reset.

0

See the text.

2

1

Reset the I C to idle state. Self clearing.

31:9 -

NA

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

8.14 I²C Clock High Register (I2C_CLKHI - 0x5000 C30C)

The CLK register holds a terminal count for counting 48 MHz clock cycles to create the

high period of the slower I²C serial clock, SCL.

Table 266. I²C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description

Bit

Symbol

Description

Reset

Value

7:0

CDHI

Clock divisor high. This value is the number of 48 MHz

clocks the serial clock (SCL) will be high.

0xB9

8.15 I²C Clock Low Register (I2C_CLKLO - 0x5000 C310)

The CLK register holds a terminal count for counting 48 MHz clock cycles to create the

low period of the slower I²C serial clock, SCL.

Table 267. I²C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description

Bit

Symbol

Description

Reset

Value

7:0

CDLO

Clock divisor low. This value is the number of 48 MHz

clocks the serial clock (SCL) will be low.

0xB9

8.16 Interrupt handling

The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All

OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt

register.

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I²C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL,

to the USB_I2C_INT bit.

For more details on the interrupts created by device controller, see the USB device

chapter. For interrupts created by the host controllers, see the OHCI specification.

The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB

related interrupts to the NVIC controller (see Figure 13–37).

Remark: During the HNP switching between host and device with the OTG stack active,

an action may raise several levels of interrupts. It is advised to let the OTG stack initiate

any actions based on interrupts and ignore device and host level interrupts. This means

that during HNP switching, the OTG stack provides the communication to the host and

device controllers.

USBIntSt

USB_INT_REQ_HP

USB DEVICE

INTERRUPTS

USB_INT_REQ_LP

USB_INT_REQ_DMA

USB_HOST_INT

to NVIC

USB_OTG_INT

USB_I2C_INT

USB HOST

INTERRUPTS

OTGIntSt

TMR

REMOVE_PU

HNP_SUCCESS

HNP_FAILURE

USB_NEED_CLOCK

EN_USB_INTS

USB I2C

INTERRUPTS

Fig 37. USB OTG interrupt handling

9. HNP support

This section describes the hardware support for the Host Negotiation Protocol (HNP)

provided by the OTG controller.

When two dual-role OTG devices are connected to each other, the plug inserted into the

mini-AB receptacle determines the default role of each device. The device with the mini-A

plug inserted becomes the default Host (A-device), and the device with the mini-B plug

inserted becomes the default Peripheral (B-device).

Once connected, the default Host (A-device) and the default Peripheral (B-device) can

switch Host and Peripheral roles using HNP.

The context of the OTG controller operation is shown in Figure 13–38. Each controller

(Host, Device, or OTG) communicates with its software stack through a set of status and

control registers and interrupts. In addition, the OTG software stack communicates with

the external OTG transceiver through the I²C interface and the external transceiver

interrupt signal.

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The OTG software stack is responsible for implementing the HNP state machines as

described in the On-The-Go Supplement to the USB 2.0 Specification.

The OTG controller hardware provides support for some of the state transitions in the

HNP state machines as described in the following subsections.

The USB state machines, the HNP switching, and the communications between the USB

controllers are described in more detail in the following documentation:

• USB OHCI specification

• USB OTG supplement, version 1.2

• USB 2.0 specification

• ISP1302 data sheet and user manual

OHCI

HOST

STACK

CONTROLLER

USB BUS

OTG

CONTROLLER

MUX

OTG

STACK

DEVICE

CONTROLLER

DEVICE

STACK

I2C

ISP1302

CONTROLLER

Fig 38. USB OTG controller with software stack

9.1 B-device: peripheral to host switching

In this case, the default role of the OTG controller is peripheral (B-device), and it switches

roles from Peripheral to Host.

The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP

using a state machine diagram. The OTG software stack is responsible for implementing

all of the states in the Dual-Role B-Device State Diagram.

The OTG controller hardware provides support for the state transitions between the states

b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting

B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device

switching from peripheral to host. The hardware actions after setting this bit are shown in

Figure 13–39.

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idle

B_HNP_TRACK = 0

no

B_HNP_TRACK = 1 ?

bus suspended ?

set HNP_FAILURE,

clear B_HNP_TRACK,

clear PU_REMOVED

no

disconnect device controller from U1

set REMOVE_PU

PU_REMOVED set?

yes

PU_REMOVED set?

reconnect port U1 to the

device controller

yes

bus reset/resume detected?

no

reconnect port U1 to the

device controller

wait 25 μs for bus to settle

yes

bus reset/resume detected?

connect from A-device detected?

no

set HNP_SUCCESS

set PORT_FUNC[0]

drive J on internal host controller port

and SE0 on U1

yes

connect U1 to host controller

clear B_HNP_TRACK

SE0 sent by host?

no

clear PU_REMOVED

Fig 39. Hardware support for B-device switching from peripheral state to host state

Figure 13–40 shows the actions that the OTG software stack should take in response to

the hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The

relationship of the software actions to the Dual-Role B-Device states is also shown.

B-device states are in bold font with a circle around them.

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b_peripheral

when host sends SET_FEATURE

with b_hnp_enable,

set B_HNP_TRACK

no

REMOVE_PU set?

yes

remove D+ pull-up,

set PU_REMOVED

go to

b_wait_acon

b_peripheral

yes

HNP_FAILURE set?

no

add D+ pull-up

no

HNP_SUCCESS set?

yes

go to

b_host

Fig 40. State transitions implemented in software during B-device switching from peripheral to host

Note that only the subset of B-device HNP states and state transitions supported by

hardware are shown. Software is responsible for implementing all of the HNP states.

Figure 13–40 may appear to imply that the interrupt bits such as REMOVE_PU should be

polled, but this is not necessary if the corresponding interrupt is enabled.

Following are code examples that show how the actions in Figure 13–40 are

accomplished. The examples assume that ISP1302 is being used as the external OTG

transceiver.

Remove D+ pull-up

/* Remove D+ pull-up through ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x007; // Send OTG Control (Clear) register address

0x201; // Clear DP_PULLUP bit, send STOP condition

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/* Wait for TDI to be set */

while (!(OTG_I2C_STS TDI));

&

/* Clear TDI */

OTG_I2C_STS TDI;

=

Add D+ pull-up

/* Add D+ pull-up through ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x006; // Send OTG Control (Set) register address

0x201; // Set DP_PULLUP bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS

& TDI));

/* Clear TDI */

OTG_I2C_STS

= TDI;

9.2 A-device: host to peripheral HNP switching

In this case, the role of the OTG controller is host (A-device), and the A-device switches

roles from host to peripheral.

The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP

using a state machine diagram. The OTG software stack is responsible for implementing

all of the states in the Dual-Role A-Device State Diagram.

The OTG controller hardware provides support for the state transitions between a_host,

a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram.

Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching

the A-device from the host state to the device state. The hardware actions after setting

this bit are shown in Figure 13–41.

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idle

A_HNP_TRACK = 0

no

A_HNP_TRACK = 1 ?

set HNP_FAILURE,

clear A_HNP_TRACK

disconnect host controller from U1

no

bus suspended ?

yes

resume detected ?

yes

connnect host controller back to U1

yes

bus reset detected?

no

resume detected?

no

OTG timer expired?

(TMR =1 )

yes

clear A_HNP_TRACK

set HNP_SUCCESS

connect device to U1 by clearing

PORT_FUNC[0]

Fig 41. Hardware support for A-device switching from host state to peripheral state

Figure 13–42 shows the actions that the OTG software stack should take in response to

the hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The

relationship of the software actions to the Dual-Role A-Device states is also shown.

A-device states are shown in bold font with a circle around them.

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a_host

when host sends SET_FEATURE

with a_hnp_enable,

set A_HNP_TRACK

set BDIS_ACON_EN

in external OTG transceiver

load and enable OTG timer

suspend host on port 1

go to

a_suspend

no

TMR set?

HNP_SUCCESS set?

HNP_FAILURE set?

yes

clear BDIS_ACON_EN

bit in external OTG transceiver

stop OTG timer

stop the OTG timer

discharge V

BUS

go to

clear BDIS_ACON_EN

a_peripheral

bit in external OTG transceiver

go to

a_wait_vfall

go to

a_host

Fig 42. State transitions implemented in software during A-device switching from host to peripheral

Note that only the subset of A-device HNP states and state transitions supported by

hardware are shown. Software is responsible for implementing all of the HNP states.

Figure 13–42 may appear to imply that the interrupt bits such as TMR should be polled,

but this is not necessary if the corresponding interrupt is enabled.

Following are code examples that show how the actions in Figure 13–42 are

accomplished. The examples assume that ISP1302 is being used as the external OTG

transceiver.

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Set BDIS_ACON_EN in external OTG transceiver

/* Set BDIS_ACON_EN in ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x004; // Send Mode Control (Set) register address

0x210; // Set BDIS_ACON_EN bit, send STOP condition

1

/* Wait for TDI to be set */

while (!(OTG_I2C_STS

& TDI));

/* Clear TDI */

OTG_I2C_STS

= TDI;

Clear BDIS_ACON_EN in external OTG transceiver

/* Set BDIS_ACON_EN in ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x005; // Send Mode Control (Clear) register address

0x210; // Clear BDIS_ACON_EN bit, send STOP condition

1

/* Wait for TDI to be set */

while (!(OTG_I2C_STS

& TDI));

/* Clear TDI */

OTG_I2C_STS

= TDI;

Discharge V_BUS

/* Clear the VBUS_DRV bit in ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x007; // Send OTG Control (Clear) register address

0x220; // Clear VBUS_DRV bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS

& TDI));

/* Clear TDI */

OTG_I2C_STS

= TDI;

/* Set the VBUS_DISCHRG bit in ISP1302 */

OTG_I2C_TX

=

0x15A; // Send ISP1302 address, R/W=0

0x006; // Send OTG Control (Set) register address

0x240; // Set VBUS_DISCHRG bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS

& TDI));

/* Clear TDI */

OTG_I2C_STS

= TDI;

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Load and enable OTG timer

/* The following assumes that the OTG timer has previously been */

/* configured for

/* and monoshot mode (TMR_MODE

a

time scale of

1

0)

ms (TMR_SCALE

=

“10”)

*/

=

/* Load the timeout value to implement the a_aidl_bdis_tmr timer */

/* the minimum value is 200 ms */

OTG_TIMER 200;

=

/* Enable the timer */

OTG_STAT_CTRL |= TMR_EN;

Stop OTG timer

/* Disable the timer

–

causes TMR_CNT to be reset to

0

*/

OTG_STAT_CTRL &= ~TMR_EN;

/* Clear TMR interrupt */

OTG_INT_CLR

= TMR;

Suspend host on port 1

/* Write to PortSuspendStatus bit to suspend host port

1

–

*/

/* this example demonstrates the low-level action software needs to take. */

/* The host stack code where this is done will be somewhat more involved. */

HC_RH_PORT_STAT1

= PSS;

10. Clocking and power management

The OTG controller clocking is shown in Figure 13–43.

A clock switch controls each clock with the exception of ahb_slave_clk. When the enable

of the clock switch is asserted, its clock output is turned on and its CLK_ON output is

asserted. The CLK_ON signals are observable in the OTGClkSt register.

To conserve power, the clocks to the Device, Host, OTG, and I²C controllers can be

disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl

register. When the entire USB block is not in use, all of its clocks can be disabled by

clearing the PCUSB bit in the PCONP register.

When software wishes to access registers in one of the controllers, it should first ensure

that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the

OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.

Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.

Accessing the register of a controller when its 48 MHz clock is not enabled will result in a

data abort exception.

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ahb_slave_clk

cclk

PCUSB

REGISTER

INTERFACE

ahb_master_clk

AHB_CLK_ON

CLOCK

SWITCH

EN

ahb_need_clk

AHB_CLK_EN

CLOCK

SWITCH

EN

dev_dma_need_clk

dev_need_clk

DEVICE

CONTROLLER

USB CLOCK

DIVIDER

usbclk

(48 MHz)

DEV_CLK_ON

DEV_CLK_EN

CLOCK

SWITCH

EN

host_dma_need_clk

host_need_clk

HOST

CONTROLLER

HOST_CLK_ON

HOST_CLK_EN

CLOCK

SWITCH

OTG

CONTROLLER

USB_NEED_CLK

EN

OTG_CLK_ON

OTG_CLK_EN

CLOCK

SWITCH

EN

I2C

CONTROLLER

I2C_CLK_ON

I2C_CLK_EN

Fig 43. Clocking and power control

10.1 Device clock request signals

The Device controller has two clock request signals, dev_need_clk and

dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and

ahb_master_clk respectively.

The dev_need_clk signal is asserted while the device is not in the suspend state, or if the

device is in the suspend state and activity is detected on the USB bus. The dev_need_clk

signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device

Status register – Section 11–10.6). This signal allows DEV_CLK_EN to be cleared during

normal operation when software does not need to access the Device controller registers –

the Device will continue to function normally and automatically shut off its clock when it is

suspended or disconnected.

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The dev_dma_need_clk signal is asserted on any Device controller DMA access to

memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA

throughput is not affected by any latency associated with re-enabling ahb_master_clk.

2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve

power. This signal allows AHB_CLK_EN to be cleared during normal operation.

10.1.1 Host clock request signals

The Host controller has two clock request signals, host_need_clk and

host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and

ahb_master_clk respectively.

The host_need_clk signal is asserted while the Host controller functional state is not

UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a

disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared

during normal operation when software does not need to access the Host controller

registers – the Host will continue to function normally and automatically shut off its clock

when it goes into the UsbSuspend state.

The host_dma_need_clk signal is asserted on any Host controller DMA access to

memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA

throughput is not affected by any latency associated with re-enabling ahb_master_clk.

2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve

power. This signal allows AHB_CLK_EN to be cleared during normal operation.

10.2 Power-down mode support

The LPC17xx can be configured to wake up from Power-down mode on any USB bus

activity. When the chip is in Power-down mode and the USB interrupt is enabled, the

assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode.

Before Power-down mode can be entered when the USB activity interrupt is enabled,

USB_NEED_CLK must be de-asserted. This is accomplished by clearing all of the

CLK_EN bits in OTGClkCtrl and putting the Host controller into the UsbSuspend

functional state. If it is necessary to wait for either of the dma_need_clk signals or the

dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the

USBIntSt register to determine when they have all been de-asserted.

11. USB OTG controller initialization

The LPC17xx OTG device controller initialization includes the following steps:

1. Enable the device controller by setting the PCUSB bit of PCONP.

2. Configure and enable the USB PLL (PLL1) or Main PLL (PLL0) to provide 48 MHz for

usbclk and the desired frequency for cclk. For correct operation of synchronization

logic in the device controller, the minimum cclk frequency is 18 MHz. For the

procedure for determining the PLL setting and configuration, see Section 4–5.11

“Procedure for determining PLL0 settings” or Section 4–6.9 “Procedure for

determining PLL1 settings”.

3. Enable the desired controller clocks by setting their respective CLK_EN bits in the

USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register

until they are set.

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4. Enable the desired USB pin functions by writing to the corresponding PINSEL

registers.

5. Follow the appropriate steps in Section 11–13 “USB device controller initialization” to

initialize the device controller.

6. Follow the guidelines given in the OpenHCI specification for initializing the host

controller.

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1. Basic configuration

The UART0/2/3 peripherals are configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bits PCUART0/2/3.

Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled

(PCUART2/3 = 0).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_UART0; in the

PCLKSEL1 register (Table 4–41), select PCLK_UART2/3.

3. Baud rate: In register U0/2/3LCR (Table 14–278), set bit DLAB =1. This enables

access to registers DLL (Table 14–272) and DLM (Table 14–273) for setting the baud

rate. Also, if needed, set the fractional baud rate in the fractional divider register

(Table 14–284).

4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR (Table 14–277) to

enable FIFO.

5. Pins: Select UART pins through the PINSEL registers and pin modes through the

PINMODE registers (Section 8–5).

Remark: UART receive pins should not have pull-down resistors enabled.

6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR

(Table 14–278). This enables access to U0/2/3IER (Table 14–274). Interrupts are

enabled in the NVIC using the appropriate Interrupt Set Enable register.

7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA

controller (see Table 31–544).

2. Features

• Data sizes of 5, 6, 7, and 8 bits.

• Parity generation and checking: odd, even mark, space or none.

• One or two stop bits.

• 16 byte Receive and Transmit FIFOs.

• Built-in baud rate generator, including a fractional rate divider for great versatility.

• Supports DMA for both transmit and receive.

• Auto-baud capability

• Break generation and detection.

• Multiprocessor addressing mode.

• IrDA mode to support infrared communication.

• Support for software flow control.

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3. Pin description

Table 268: UARTn Pin description

Type

Description

RXD0, RXD2, RXD3

TXD0, TXD2, TXD3

Input

Serial Input. Serial receive data.

Serial Output. Serial transmit data.

Output

4. Register description

Each UART contains registers as shown in Table 14–269. The Divisor Latch Access Bit

(DLAB) is contained in UnLCR7 and enables access to the Divisor Latches.

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Table 269. UART0/2/3 Register Map

Generic Name

Description

Access Reset

UARTn Register

value^[1]Name & Address

RBR (DLAB =0)

Receiver Buffer Register. Contains the next received

character to be read.

RO

NA

U0RBR - 0x4000 C000

U2RBR - 0x4009 8000

U3RBR - 0x4009 C000

THR (DLAB =0)

DLL (DLAB =1)

DLM (DLAB =1)

IER (DLAB =0)

IIR

Transmit Holding Register. The next character to be

transmitted is written here.

WO

R/W

NA

U0THR - 0x4000 C000

U2THR - 0x4009 8000

U3THR - 0x4009 C000

Divisor Latch LSB. Least significant byte of the baud

rate divisor value. The full divisor is used to generate a

baud rate from the fractional rate divider.

0x01

0x00

0x01

0x00

0x60

0x00

0x10

0x80

0x00

U0DLL - 0x4000 C000

U2DLL - 0x4009 8000

U3DLL - 0x4009 C000

Divisor Latch MSB. Most significant byte of the baud

rate divisor value. The full divisor is used to generate a

baud rate from the fractional rate divider.

U0DLM - 0x4000 C004

U2DLM - 0x4009 8004

U3DLM - 0x4009 C004

Interrupt Enable Register. Contains individual interrupt R/W

enable bits for the 7 potential UART interrupts.

U0IER - 0x4000 C004

U2IER - 0x4009 8004

U3IER - 0x4009 C004

Interrupt ID Register. Identifies which interrupt(s) are

pending.

RO

U0IIR - 0x4000 C008

U2IIR - 0x4009 8008

U3IIR - 0x4009 C008

FCR

FIFO Control Register. Controls UART FIFO usage and WO

modes.

U0FCR - 0x4000 C008

U2FCR - 0x4009 8008

U3FCR - 0x4009 C008

LCR

Line Control Register. Contains controls for frame

formatting and break generation.

R/W

RO

U0LCR - 0x4000 C00C

U2LCR - 0x4009 800C

U3LCR - 0x4009 C00C

LSR

Line Status Register. Contains flags for transmit and

receive status, including line errors.

U0LSR - 0x4000 C014

U2LSR - 0x4009 8014

U3LSR - 0x4009 C014

SCR

Scratch Pad Register. 8-bit temporary storage for

software.

R/W

U0SCR - 0x4000 C01C

U2SCR - 0x4009 801C

U3SCR - 0x4009 C01C

ACR

Auto-baud Control Register. Contains controls for the

auto-baud feature.

U0ACR - 0x4000 C020

U2ACR - 0x4009 8020

U3ACR - 0x4009 C020

ICR

IrDA Control Register. Enables and configures the

IrDA mode.

U0ICR - 0x4000 C024

U12CR - 0x4009 8024

U3ICR - 0x4009 C024

FDR

Fractional Divider Register. Generates a clock input for R/W

the baud rate divider.

U0FDR - 0x4000 C028

U2FDR - 0x4009 8028

U3FDR - 0x4009 C028

TER

Transmit Enable Register. Turns off UART transmitter

for use with software flow control.

R/W

U0TER - 0x4000 C030

U2TER - 0x4009 8030

U3TER - 0x4009 C030

FIFOLVL

FIFO Level register. Provides the current fill levels of the RO

transmit and receive FIFOs.

U0FIFOLVL - 0x4000 C058

U2FIFOLVL - 0x4009 8058

U3FIFOLVL - 0x4009 C058

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -

0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)

The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains

the oldest character received and can be read via the bus interface. The LSB (bit 0)

represents the “oldest” received data bit. If the character received is less than 8 bits, the

unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.

The UnRBR is always read-only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.

the one that will be read in the next read from the RBR), the right approach for fetching the

valid pair of received byte and its status bits is first to read the content of the U0LSR

register, and then to read a byte from the UnRBR.

Table 270: UARTn Receiver Buffer Register (U0RBR - address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR -

04009 C000 when DLAB = 0) bit description

Bit

Symbol

Description

Reset Value

7:0 RBR

The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx Undefined

FIFO.

31:8

-

Reserved, the value read from a reserved bit is not defined.

NA

4.2 UARTn Transmit Holding Register (U0THR - 0x4000 C000, U2THR -

0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)

The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in

the TX FIFO and can be written via the bus interface. The LSB represents the first bit to

transmit.

The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the

UnTHR. The UnTHR is always write-only.

Table 271: UARTn Transmit Holding Register (U0THR - address 0x4000 C000, U2THR - 0x4009 8000, U3THR -

0x4009 C000 when DLAB = 0) bit description

Bit

Symbol

Description

Reset Value

7:0 THR

Writing to the UARTn Transmit Holding Register causes the data to be stored in the

UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and

the transmitter is available.

NA

31:8

-

Reserved, user software should not write ones to reserved bits.

NA

4.3 UARTn Divisor Latch LSB register (U0DLL - 0x4000 C000, U2DLL -

0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn

Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL -

0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1)

The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value

used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce

the baud rate clock, which must be 16× the desired baud rate. The UnDLL and UnDLM

registers together form a 16-bit divisor where UnDLL contains the lower 8 bits of the

divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like

a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in

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UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to

select the right value for U1DLL and U1DLM can be found later in this chapter, see

Section 14–4.12.

Table 272: UARTn Divisor Latch LSB register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL -

0x4009 C000 when DLAB = 1) bit description

Bit

Symbol

Description

Reset Value

7:0 DLLSB

The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the

baud rate of the UARTn.

0x01

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

Table 273: UARTn Divisor Latch MSB register (U0DLM - address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM -

0x4009 C004 when DLAB = 1) bit description

Bit

Symbol

Description

Reset Value

7:0 DLMSB

The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the

baud rate of the UARTn.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

4.4 UARTn Interrupt Enable Register (U0IER - 0x4000 C004, U2IER -

0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0)

The UnIER is used to enable the three UARTn interrupt sources.

Table 274: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -

0x4009 C004 when DLAB = 0) bit description

Bit

Symbol

Value Description

Enables the Receive Data Available interrupt for UARTn. It also controls

Reset Value

0

RBR Interrupt

Enable

0

the Character Receive Time-out interrupt.

0

1

Disable the RDA interrupts.

Enable the RDA interrupts.

1

2

THRE Interrupt

Enable

Enables the THRE interrupt for UARTn. The status of this can be read

from UnLSR[5].

0

1

Disable the THRE interrupts.

Enable the THRE interrupts.

RX Line Status

Interrupt Enable

Enables the UARTn RX line status interrupts. The status of this interrupt

can be read from UnLSR[4:1].

0

1

Disable the RX line status interrupts.

Enable the RX line status interrupts.

7:3

8

-

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

ABEOIntEn

Enables the end of auto-baud interrupt.

Disable end of auto-baud Interrupt.

Enable end of auto-baud Interrupt.

0

1

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Table 274: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER -

0x4009 C004 when DLAB = 0) bit description

Bit

Symbol

Value Description

Enables the auto-baud time-out interrupt.

Reset Value

9

ABTOIntEn

0

1

Disable auto-baud time-out Interrupt.

Enable auto-baud time-out Interrupt.

31:10 -

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -

0x4009 8008, U3IIR - 0x4009 C008)

The UnIIR provides a status code that denotes the priority and source of a pending

interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during

an UnIIR access, the interrupt is recorded for the next UnIIR access.

Table 275: UARTn Interrupt Identification Register (U0IIR - address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR -

0x4009 C008) bit description

Bit

Symbol

Value Description

Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be

Reset Value

0

IntStatus

1

determined by evaluating UnIIR[3:1].

At least one interrupt is pending.

No interrupt is pending.

0

1

3:1

IntId

Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the

UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below

are reserved (000,100,101,111).

0

011 1 - Receive Line Status (RLS).

010 2a - Receive Data Available (RDA).

110 2b - Character Time-out Indicator (CTI).

001 3 - THRE Interrupt

5:4

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

7:6

8

FIFO Enable

ABEOInt

Copies of UnFCR[0].

0

End of auto-baud interrupt. True if auto-baud has finished successfully and

interrupt is enabled.

9

ABTOInt

Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is

enabled.

0

31:10 -

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud

condition. The auto-baud interrupt conditions are cleared by setting the corresponding

Clear bits in the Auto-baud Control Register.

If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus

is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of

interrupt and handling as described in Table 14–276. Given the status of UnIIR[3:0], an

interrupt handler routine can determine the cause of the interrupt and how to clear the

active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the

Interrupt Service Routine.

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The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set

whenever any one of four error conditions occur on the UARTn Rx input: overrun error

(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error

condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared

upon an UnLSR read.

The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI

interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the

trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls

below the trigger level. When the RDA interrupt goes active, the CPU can read a block of

data defined by the trigger level.

The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn

Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in

3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will

clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has

been received that is not a multiple of the trigger level size. For example, if a peripheral

wished to send a 105 character message and the trigger level was 10 characters, the

CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5

CTI interrupts (depending on the service routine) resulting in the transfer of the remaining

5 characters.

Table 276: UARTn Interrupt Handling

U0IIR[3:0] Priority Interrupt

Interrupt Source

Interrupt Reset

value^[1]

Type

0001

-

None

-

0110

Highest RX Line

Status / Error

OE^[2]or PE^[2]or FE^[2]or BI^[2]

UnLSR Read^[2]

0100

1100

Second RX Data

Available

Rx data available or trigger level reached in FIFO

(UnFCR0=1)

UnRBR Read^[3]or UARTn

FIFO drops below trigger level

UnRBR Read^[3]

Second Character

Time-out

Minimum of one character in the Rx FIFO and no

character input or removed during a time period

depending on how many characters are in FIFO and

what the trigger level is set at (3.5 to 4.5 character

times).

indication

The exact time will be:

[(word length) × 7 - 2] × 8 + [(trigger level - number of

characters) × 8 + 1] RCLKs

0010

Third

THRE

THRE^[2]

UnIIR Read (if source of

interrupt) or THR write^[4]

[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2] For details see Section 14–4.8 “UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -

0x4009 8014, U3LSR - 0x4009 C014)”

[3] For details see Section 14–14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -

0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)”

[4] For details see Section 14–4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -

0x4009 8008, U3IIR - 0x4009 C008)” and Section 14–4.2 “UARTn Transmit Holding Register (U0THR -

0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)”

The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated

when the UARTn THR FIFO is empty provided certain initialization conditions have been

met. These initialization conditions are intended to give the UARTn THR FIFO a chance to

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fill up with data to eliminate many THRE interrupts from occurring at system start-up. The

initialization conditions implement a one character delay minus the stop bit whenever

THRE = 1 and there have not been at least two characters in the UnTHR at one time

since the last THRE = 1 event. This delay is provided to give the CPU time to write data to

UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set

immediately if the UARTn THR FIFO has held two or more characters at one time and

currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or

a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).

4.6 UARTn FIFO Control Register (U0FCR - 0x4000 C008, U2FCR -

0x4009 8008, U3FCR - 0x4009 C008)

The write-only UnFCR controls the operation of the UARTn Rx and TX FIFOs.

Table 277: UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR -

0x4007 C008) bit description

Bit

Symbol

Value Description

Reset Value

0

FIFO Enable

0

1

UARTn FIFOs are disabled. Must not be used in the application.

0

Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access.

This bit must be set for proper UART operation. Any transition on this bit will

automatically clear the related UART FIFOs.

1

2

RX FIFO

Reset

0

1

No impact on either of UARTn FIFOs.

0

Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the

pointer logic. This bit is self-clearing.

TX FIFO

Reset

0

1

No impact on either of UARTn FIFOs.

Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the

pointer logic. This bit is self-clearing.

3

DMA Mode

Select

When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA

mode. See Section 14–4.6.1.

5:4

7:6

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

RX Trigger

Level

These two bits determine how many receiver UARTn FIFO characters must be

written before an interrupt or DMA request is activated.

0

00

01

10

11

Trigger level 0 (1 character or 0x01)

Trigger level 1 (4 characters or 0x04)

Trigger level 2 (8 characters or 0x08)

Trigger level 3 (14 characters or 0x0E)

Reserved, user software should not write ones to reserved bits.

31:8

-

NA

4.6.1 DMA Operation

The user can optionally operate the UART transmit and/or receive using DMA. The DMA

mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an

affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.

UART receiver DMA

In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO

level becoming equal to or greater than trigger level, or if a character timeout occurs. See

the description of the RX Trigger Level above. The receiver DMA request is cleared by the

DMA controller.

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UART transmitter DMA

In DMA mode, the transmitter DMA request is asserted on the event of the transmitter

FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA

controller.

4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR -

0x4009 800C, U3LCR - 0x4009 C00C)

The UnLCR determines the format of the data character that is to be transmitted or

received.

Table 278: UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -

0x4009 C00C) bit description

Bit

Symbol

Value Description

Reset Value

1:0

Word Length Select 00

5-bit character length

0

01

10

11

6-bit character length

7-bit character length

8-bit character length

2

Stop Bit Select

Parity Enable

Parity Select

0

1 stop bit.

0

1

2 stop bits (1.5 if UnLCR[1:0]=00).

Disable parity generation and checking.

Enable parity generation and checking.

3

0

1

5:4

00

Odd parity. Number of 1s in the transmitted character and the attached

parity bit will be odd.

01

Even Parity. Number of 1s in the transmitted character and the attached

parity bit will be even.

10

11

0

Forced "1" stick parity.

Forced "0" stick parity.

Disable break transmission.

6

Break Control

0

1

Enable break transmission. Output pin UARTn TXD is forced to logic 0

when UnLCR[6] is active high.

7

Divisor Latch

Access Bit (DLAB)

0

1

Disable access to Divisor Latches.

Enable access to Divisor Latches.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

4.8 UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -

0x4009 8014, U3LSR - 0x4009 C014)

The UnLSR is a read-only register that provides status information on the UARTn TX and

RX blocks.

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Table 279: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)

bit description

Bit

Symbol

Value Description

Reset

Value

0

Receiver Data

Ready (RDR)

UnLSR0 is set when the UnRBR holds an unread character and is cleared when

the UARTn RBR FIFO is empty.

0

1

The UARTn receiver FIFO is empty.

The UARTn receiver FIFO is not empty.

1

2

Overrun Error

(OE)

The overrun error condition is set as soon as it occurs. An UnLSR read clears

UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and

the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be

overwritten and the character in the UARTn RSR will be lost.

0

1

Overrun error status is inactive.

Overrun error status is active.

Parity Error (PE)

When the parity bit of a received character is in the wrong state, a parity error

occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is

dependent on UnFCR[0].

0

Note: A parity error is associated with the character at the top of the UARTn RBR

FIFO.

0

1

Parity error status is inactive.

Parity error status is active.

3

Framing Error

(FE)

When the stop bit of a received character is a logic 0, a framing error occurs. An

UnLSR read clears UnLSR[3]. The time of the framing error detection is

dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to

resynchronize to the data and assume that the bad stop bit is actually an early

start bit. However, it cannot be assumed that the next received byte will be correct

even if there is no Framing Error.

0

Note: A framing error is associated with the character at the top of the UARTn

RBR FIFO.

0

1

Framing error status is inactive.

Framing error status is active.

4

Break Interrupt

(BI)

When RXDn is held in the spacing state (all zeroes) for one full character

transmission (start, data, parity, stop), a break interrupt occurs. Once the break

condition has been detected, the receiver goes idle until RXDn goes to marking

state (all ones). An UnLSR read clears this status bit. The time of break detection

is dependent on UnFCR[0].

0

Note: The break interrupt is associated with the character at the top of the UARTn

RBR FIFO.

0

1

Break interrupt status is inactive.

Break interrupt status is active.

5

6

Transmitter

Holding Register

Empty (THRE))

THRE is set immediately upon detection of an empty UARTn THR and is cleared

on a UnTHR write.

1

0

1

UnTHR contains valid data.

UnTHR is empty.

Transmitter

Empty (TEMT)

TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when

either the UnTSR or the UnTHR contain valid data.

0

1

UnTHR and/or the UnTSR contains valid data.

UnTHR and the UnTSR are empty.

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Table 279: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)

bit description

Bit

Symbol

Value Description

Reset

Value

7

Error in RX FIFO

(RXFE)

UnLSR[7] is set when a character with a Rx error such as framing error, parity

error or break interrupt, is loaded into the UnRBR. This bit is cleared when the

UnLSR register is read and there are no subsequent errors in the UARTn FIFO.

0

1

UnRBR contains no UARTn RX errors or UnFCR[0]=0.

UARTn RBR contains at least one UARTn RX error.

Reserved, the value read from a reserved bit is not defined.

31:8

-

NA

4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR -

0x4009 801C U3SCR - 0x4009 C01C)

The UnSCR has no effect on the UARTn operation. This register can be written and/or

read at user’s discretion. There is no provision in the interrupt interface that would indicate

to the host that a read or write of the UnSCR has occurred.

Table 280: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -

0x4009 C01C) bit description

Bit

Symbol Description

Reset Value

0x00

7:0

Pad

-

A readable, writable byte.

31:8

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

4.10 UARTn Auto-baud Control Register (U0ACR - 0x4000 C020, U2ACR -

0x4009 8020, U3ACR - 0x4009 C020)

The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the

incoming clock/data rate for the baud rate generation and can be read and written at

user’s discretion.

Table 281: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -

0x4009 C020) bit description

Bit

Symbol

Value Description

This bit is automatically cleared after auto-baud completion.

Reset value

0

Start

0

1

Auto-baud stop (auto-baud is not running).

Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is

automatically cleared after auto-baud completion.

1

Mode

Auto-baud mode select bit.

0

1

0

1

Mode 0.

Mode 1.

2

AutoRestart

-

No restart.

0

Restart in case of time-out (counter restarts at next UARTn Rx falling edge)

0

7:3

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

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Table 281: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -

0x4009 C020) bit description

Bit

Symbol

Value Description

End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will

Reset value

8

ABEOIntClr

0

clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.

9

ABTOIntClr

Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will

clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.

0

31:10 -

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

14.4.10.1 Auto-baud

The UARTn auto-baud function can be used to measure the incoming baud-rate based on

the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit

time of the receive data stream and set the divisor latch registers UnDLM and UnDLL

accordingly.

Remark: the fractional rate divider is not connected during auto-baud operations, and

therefore should not be used when the auto-baud feature is needed.

Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing

the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the

bit will return the status of auto-baud (pending/finished).

Two auto-baud measuring modes are available which can be selected by the UnACR

Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the

UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significant

bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent

rising edge of the UARTn Rx pin (the length of the start bit).

The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement

if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate

measurement will restart at the next falling edge of the UARTn Rx pin.

The auto-baud function can generate two interrupts.

• The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn

is set and the auto-baud rate measurement counter overflows).

• The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn

is set and the auto-baud has completed successfully).

The auto-baud interrupts have to be cleared by setting the corresponding UnACR

ABTOIntClr and ABEOIntEn bits.

Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during

auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it

is going to impact the measuring of UARTn Rx pin baud-rate, but the value of the UnFDR

register is not going to be modified after rate measurement. Also, when auto-baud is used,

any write to UnDLM and UnDLL registers should be done before UnACR register write.

The minimum and the maximum baud rates supported by UARTn are function of pclk,

number of data bits, stop bits and parity bits.

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(1)

2 × PCLK

PCLK

------------------------

-----------------------------------------------------------------------------------------------------------

= ratemax

ratemin =

≤ UARTn

≤

baudrate

15

16 × (2 + databits + paritybits + stopbits)

16 × 2

14.4.10.2 Auto-baud modes

When the software is expecting an “AT” command, it configures the UARTn with the

expected character format and sets the UnACR Start bit. The initial values in the divisor

latches UnDLM and UnDLM don‘t care. Because of the “A” or “a” ASCII coding

(”A" = 0x41, “a” = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expected

character are delimited by two falling edges. When the UnACR Start bit is set, the

auto-baud protocol will execute the following phases:

1. On UnACR Start bit setting, the baud rate measurement counter is reset and the

UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate.

2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate

measuring counter will start counting pclk cycles optionally pre-scaled by the

fractional baud-rate generator.

3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with

the frequency of the (fractional baud-rate pre-scaled) UARTn input clock,

guaranteeing the start bit is stored in the UnRSR.

4. During the receipt of the start bit (and the character LSB for mode = 0) the rate

counter will continue incrementing with the pre-scaled UARTn input clock (pclk).

5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If

Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin.

6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched to

normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt

UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the

remaining bits of the “A/a” character.

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'A' (0x41) or 'a' (0x61)

start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7 parity stop

UARTn RX

start bit

LSB of 'A' or 'a'

U0ACR start

rate counter

16xbaud_rate

16 cycles

a. Mode 0 (start bit and LSB are used for auto-baud)

'A' (0x41) or 'a' (0x61)

start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7 parity stop

UARTn RX

start bit

LSB of 'A' or 'a'

U1ACR start

rate counter

16xbaud_rate

16 cycles

b. Mode 1 (only start bit is used for auto-baud)

Fig 44. Auto-baud a) mode 0 and b) mode 1 waveform

4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009

8024, U3ICR - 0x4009 C024)

The IrDA Control Register enables and configures the IrDA mode on each UART. The

value of UnICR should not be changed while transmitting or receiving data, or data loss or

corruption may occur.

Table 282: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit

description

Bit

Symbol

Value Description

Reset value

0

IrDAEn

0

1

IrDA mode on UARTn is disabled, UARTn acts as a standard UART.

0

IrDA mode on UARTn is enabled.

1

IrDAInv

When 1, the serial input is inverted. This has no effect on the serial output.

When 0, the serial input is not inverted.

0

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Table 282: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit

description

Bit

2

Symbol

FixPulseEn

PulseDiv

-

Value Description

When 1, enabled IrDA fixed pulse width mode.

Reset value

0

5:3

31:6

Configures the pulse when FixPulseEn = 1. See text below for details.

NA

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width

mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits

should be set so that the resulting pulse width is at least 1.63 µs. Table 14–283 shows the

possible pulse widths.

Table 283: IrDA Pulse Width

FixPulseEn PulseDiv

IrDA Transmitter Pulse width (µs)

3 / (16 × baud rate)

2 × T_PCLK

0

1

x

0

1

2

3

4

5

6

7

4 × T_PCLK

8 × T_PCLK

16 × T_PCLK

32 × T_PCLK

64 × T_PCLK

128 × T_PCLK

256 × T_PCLK

4.12 UARTn Fractional Divider Register (U0FDR - 0x4000 C028, U2FDR -

0x4009 8028, U3FDR - 0x4009 C028)

The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for

the baud rate generation and can be read and written at the user’s discretion. This

pre-scaler takes the APB clock and generates an output clock according to the specified

fractional requirements.

Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of

the DLL register must be greater than 2.

Table 284: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR -

0x4009 C028) bit description

Bit

Function

Value Description

Reset value

3:0

DIVADDVAL

0

Baud-rate generation pre-scaler divisor value. If this field is 0, fractional

0

baud-rate generator will not impact the UARTn baudrate.

7:4

MULVAL

-

1

Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for

UARTn to operate properly, regardless of whether the fractional baud-rate

generator is used or not.

1

0

31:8

NA

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

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This register controls the clock pre-scaler for the baud rate generation. The reset value of

the register keeps the fractional capabilities of UART0/2/3 disabled making sure that

UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this

feature.

UART0/2/3 baud rate can be calculated as (n = 0/2/3):

(2)

PCLK

UARTn_baudrate

=

----------------------------------------------------------------------------------------------------------------------------------

DivAddVal

⎛

⎞

16 × (256 × UnDLM + UnDLL) × 1 +

----------------------------

⎝

⎠

MulVal

Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard

UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3

fractional baud rate generator specific parameters.

The value of MULVAL and DIVADDVAL should comply to the following conditions:

1. 1 ≤ MULVAL ≤ 15

2. 0 ≤ DIVADDVAL ≤ 14

3. DIVADDVAL < MULVAL

The value of the U0/2/3FDR should not be modified while transmitting/receiving data or

data may be lost or corrupted.

If the U0/2/3FDR register value does not comply to these two requests, then the fractional

divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,

and the clock will not be divided.

4.12.1 Baud rate calculation

UARTn can operate with or without using the Fractional Divider. In real-life applications it

is likely that the desired baud rate can be achieved using several different Fractional

Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,

MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a

relative error of less than 1.1% from the desired one.

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Calculating UART

baudrate (BR)

PCLK,

BR

DL _est= PCLK/(16 x BR)

DL_estis an

integer?

True

DIVADDVAL = 0

MULVAL = 1

False

FR _est= 1.5

Pick another FR_estfrom

the range [1.1, 1.9]

DL _est= Int(PCLK/(16 x BR x FR _est))

FR_est= PCLK/(16 x BR x DL _est

)

False

1.1 < FR _est< 1.9?

True

DIVADDVAL = table(FR _est

)

MULVAL = table(FR

)

est

DLM = DL_est[15:8]

DLL = DL_est[7:0]

End

Fig 45. Algorithm for setting UART dividers

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Table 285. Fractional Divider setting look-up table

FR

DivAddVal/ FR

MulVal

DivAddVal/ FR

MulVal

DivAddVal/ FR

MulVal

DivAddVal/

MulVal

1.000

1.067

1.071

1.077

1.083

1.091

1.100

1.111

1.125

1.133

1.143

1.154

1.167

1.182

1.200

1.214

1.222

1.231

0/1

1.250

1/4

1.500

1/2

1.750

3/4

1/15

1/14

1/13

1/12

1/11

1/10

1/9

1.267

1.273

1.286

1.300

1.308

1.333

1.357

1.364

1.375

1.385

1.400

1.417

1.429

1.444

1.455

1.462

1.467

4/15

3/11

2/7

1.533

1.538

1.545

1.556

1.571

1.583

1.600

1.615

1.625

1.636

1.643

1.667

1.692

1.700

1.714

1.727

1.733

8/15

7/13

6/11

5/9

1.769

1.778

1.786

1.800

1.818

1.833

1.846

1.857

1.867

1.875

1.889

1.900

1.909

1.917

1.923

1.929

1.933

10/13

7/9

11/14

4/5

3/10

4/13

1/3

4/7

9/11

5/6

7/12

3/5

5/14

4/11

3/8

11/13

6/7

1/8

8/13

5/8

2/15

1/7

13/15

7/8

5/13

2/5

7/11

9/14

2/3

2/13

1/6

8/9

5/12

3/7

9/10

10/11

11/12

12/13

13/14

14/15

2/11

1/5

9/13

7/10

5/7

4/9

3/14

2/9

5/11

6/13

7/15

8/11

11/15

3/13

4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600

According to the provided algorithm DL_est= PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)

= 96. Since this DL_estis an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and

DLL = 96.

4.12.1.2 Example 2: PCLK = 12 MHz, BR = 115200

According to the provided algorithm DL_est= PCLK/(16 x BR) = 12 MHz / (16 x 115200) =

6.51. This DL_estis not an integer number and the next step is to estimate the FR

parameter. Using an initial estimate of FR_est= 1.5 a new DL_est= 4 is calculated and FR_est

is recalculated as FR_est= 1.628. Since FRest = 1.628 is within the specified range of 1.1

and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up

table.

The closest value for FRest = 1.628 in the look-up Table 14–285 is FR = 1.625. It is

equivalent to DIVADDVAL = 5 and MULVAL = 8.

Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,

DIVADDVAL = 5, and MULVAL = 8. According to Equation 14–2 the UART rate is 115384.

This rate has a relative error of 0.16% from the originally specified 115200.

4.13 UARTn Transmit Enable Register (U0TER - 0x4000 C030, U2TER -

0x4009 8030, U3TER - 0x4009 C030)

The UnTER register enables implementation of software flow control. When TXEn=1,

UARTn transmitter will keep sending data as long as they are available. As soon as TXEn

becomes 0, UARTn transmission will stop.

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Table 14–286 describes how to use TXEn bit in order to achieve software flow control.

Table 286: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER -

0x4009 C030) bit description

Bit Symbol Description

Reset Value

6:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

7

TXEN

When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as

soon as any preceding data has been sent. If this bit is cleared to 0 while a character is

being sent, the transmission of that character is completed, but no further characters are

sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters

from the THR or TX FIFO into the transmit shift register. Software implementing

software-handshaking can clear this bit when it receives an XOFF character (DC3). Software

can set this bit again when it receives an XON (DC1) character.

1

4.14 UARTn FIFO Level register (U0FIFOLVL - 0x4000 C058, U2FIFOLVL -

0x4009 8058, U3FIFOLVL - 0x4009 C058)

UnFIFOLVL register is a read-only register that allows software to read the current FIFO

level status. Both the transmit and receive FIFO levels are present in this register.

Table 287. UARTn FIFO Level register (U0FIFOLVL - 0x4000 C058, U2FIFOLVL - 0x4009 8058, U3FIFOLVL - 0x4009

C058) bit description

Bit

Symbol

Description

Reset value

3:0

RXFIFILVL

Reflects the current level of the UART receiver FIFO.

0 = empty, 0xF = FIFO full.

0x00

7:4

-

Reserved. The value read from a reserved bit is not defined.

NA

11:8 TXFIFOLVL Reflects the current level of the UART transmitter FIFO.

0 = empty, 0xF = FIFO full.

0x00

31:12 -

Reserved. The value read from a reserved bit is not defined.

NA

5. Architecture

The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram.

The APB interface provides a communications link between the CPU or host and the

UART.

The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input.

The UARTn RX Shift Register (UnRSR) accepts valid characters via RXDn. After a valid

character is assembled in the UnRSR, it is passed to the UARTn RX Buffer Register FIFO

to await access by the CPU or host via the generic host interface.

The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers

the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register

(UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via the

serial output pin, TXDn.

The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by

the UARTn TX block. The UnBRG clock input source is the APB clock (PCLK). The main

clock is divided down per the divisor specified in the UnDLL and UnDLM registers. This

divided down clock is a 16x oversample clock, NBAUDOUT.

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The interrupt interface contains registers UnIER and UnIIR. The interrupt interface

receives several one clock wide enables from the UnTX and UnRX blocks.

Status information from the UnTX and UnRX is stored in the UnLSR. Control information

for the UnTX and UnRX is stored in the UnLCR.

Transmitter

Holding

Register

Transmitter

Shift

Register

Un_TXD

Transmitter

FIFO

Transmitter

DMA

Interface

TX_DMA_REQ

TX_DMA_CLR

Baud Rate Generator

Fractional

Rate

Main

Divider

PCLK

Divider

(DLM, DLL)

FIFO Control

& Status

Interrupt

Control &

Status

Line Control

& Status

UARTn interrupt

Un_OE

RS485, IrDA,

& Auto-baud

Receiver

Buffer

Register

Receiver

Shift

Register

Un_RXD

Receiver

FIFO

Receiver

DMA

Interface

RX_DMA_REQ

RX_DMA_CLR

Fig 46. UART0, 2 and 3 block diagram

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1. Basic configuration

The UART1 peripheral is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bits PCUART1.

Remark: On reset, UART1 is enabled (PCUART1 = 1).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_UART1.

3. Baud rate: In register U1LCR (Table 15–298), set bit DLAB =1. This enables access

to registers DLL (Table 15–292) and DLM (Table 15–293) for setting the baud rate.

Also, if needed, set the fractional baud rate in the fractional divider register

(Table 15–305).

4. UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR (Table 15–297) to enable

FIFO.

5. Pins: Select UART pins through PINSEL registers and pin modes through the

PINMODE registers (Section 8–5).

Remark: UART receive pins should not have pull-down resistors enabled.

6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR

(Table 15–298). This enables access to U1IER (Table 15–294). Interrupts are enabled

in the NVIC using the appropriate Interrupt Set Enable register.

7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller

(see Table 31–544).

2. Features

• Full modem control handshaking available

• Data sizes of 5, 6, 7, and 8 bits.

• Parity generation and checking: odd, even mark, space or none.

• One or two stop bits.

• 16 byte Receive and Transmit FIFOs.

• Built-in baud rate generator, including a fractional rate divider for great versatility.

• Supports DMA for both transmit and receive.

• Auto-baud capability

• Break generation and detection.

• Multiprocessor addressing mode.

• RS-485 support.

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3. Pin description

Table 288: UART1 Pin Description

RXD1 Input

TXD1 Output Serial Output. Serial transmit data.

Type Description

Serial Input. Serial receive data.

CTS1 Input

Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via

TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value

of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a

priority level 4 interrupt, if enabled (U1IER[3] = 1).

Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked by

reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR)

indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt is

enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTS1

is also used in the auto-cts mode to control the transmitter.

DCD1 Input

DSR1 Input

Data Carrier Detect. Active low signal indicates if the external modem has established a communication

link with the UART1 and data may be exchanged. In normal operation of the modem interface

(U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is

stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications

link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of

this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a

priority level 4 interrupt, if enabled (U1IER[3] = 1).

DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with

external modem. The complement value of this signal is stored in U1MCR[0].

The DTR pin can also be used as an RS-485/EIA-485 output enable signal.

RI1

Input

Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the

modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is

stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4

interrupt, if enabled (U1IER[3] = 1).

RTS1 Output Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external

modem. The complement value of this signal is stored in U1MCR[1].

In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic.

Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready to

receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is set to

the inactive (high) level either as a result of a system reset or during loop-back mode operations or by

clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO threshold

logic.

The RTS pin can also be used as an RS-485/EIA-485 output enable signal.

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4. Register description

UART1 contains registers organized as shown in Table 15–289. The Divisor Latch Access

Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.

Table 289: UART1 register map

Name

Description

Access Reset

Value^[1]

Address

U1RBR

Receiver Buffer Register. Contains the next received character to

be read.

RO

NA

0x4001 0000

(when DLAB=0)

(when DLAB =0)

U1THR

Transmit Holding Register. The next character to be transmitted is WO

written here.

NA

0x4001 0000

(when DLAB=0)

(when DLAB =0)

U1DLL

Divisor Latch LSB. Least significant byte of the baud rate divisor

value. The full divisor is used to generate a baud rate from the

fractional rate divider.

R/W

0x01

0x4001 0000

(when DLAB=1)

(when DLAB =1)

U1DLM

Divisor Latch MSB. Most significant byte of the baud rate divisor

value. The full divisor is used to generate a baud rate from the

fractional rate divider.

R/W

0x00

0x4001 0004

(when DLAB=1)

(when DLAB =1)

U1IER

Interrupt Enable Register. Contains individual interrupt enable bits R/W

for the 7 potential UART1 interrupts.

0x4001 0004

(when DLAB=0)

(when DLAB =0)

U1IIR

Interrupt ID Register. Identifies which interrupt(s) are pending.

FIFO Control Register. Controls UART1 FIFO usage and modes.

RO

0x01

0x00

0x4001 0008

0x4001 000C

U1FCR

WO

R/W

U1LCR

Line Control Register. Contains controls for frame formatting and

break generation.

U1MCR

U1LSR

Modem Control Register. Contains controls for flow control

handshaking and loopback mode.

R/W

0x00

0x60

0x4001 0010

0x4001 0014

Line Status Register. Contains flags for transmit and receive status, RO

including line errors.

U1MSR

U1SCR

U1ACR

Modem Status Register. Contains handshake signal status flags.

Scratch Pad Register. 8-bit temporary storage for software.

RO

0x00

0x4001 0018

0x4001 001C

0x4001 0020

R/W

Auto-baud Control Register. Contains controls for the auto-baud

feature.

U1FDR

Fractional Divider Register. Generates a clock input for the baud

rate divider.

R/W

0x10

0x80

0x00

0x4001 0028

0x4001 0030

0x4001 004C

0x4001 0050

U1TER

Transmit Enable Register. Turns off UART transmitter for use with R/W

software flow control.

U1RS485CTRL

U1ADRMATCH

RS-485/EIA-485 Control. Contains controls to configure various

aspects of RS-485/EIA-485 modes.

R/W

RS-485/EIA-485 address match. Contains the address match value R/W

for RS-485/EIA-485 mode.

U1RS485DLY

U1FIFOLVL

RS-485/EIA-485 direction control delay.

R/W

RO

0x00

0x4001 0054

0x4001 0058

FIFO Level register. Provides the current fill levels of the transmit

and receive FIFOs.

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when

DLAB = 0)

The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains

the oldest character received and can be read via the bus interface. The LSB (bit 0)

represents the “oldest” received data bit. If the character received is less than 8 bits, the

unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the

U1RBR. The U1RBR is always read-only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.

the one that will be read in the next read from the RBR), the right approach for fetching the

valid pair of received byte and its status bits is first to read the content of the U1LSR

register, and then to read a byte from the U1RBR.

Table 290: UART1 Receiver Buffer Register (U1RBR - address 0x4001 0000 when DLAB = 0) bit description

Bit

Symbol Description

Reset Value

7:0

RBR

The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX

undefined

FIFO.

31:8

-

Reserved, the value read from a reserved bit is not defined.

NA

4.2 UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when

DLAB = 0)

The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest

character in the TX FIFO and can be written via the bus interface. The LSB represents the

first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the

U1THR. The U1THR is write-only.

Table 291: UART1 Transmitter Holding Register (U1THR - address 0x4001 0000 when DLAB = 0) bit description

Bit

Symbol Description

Reset Value

7:0

THR

Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 NA

transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the

transmitter is available.

31:8

-

Reserved, user software should not write ones to reserved bits.

NA

4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000

and U1DLM - 0x4001 0004, when DLAB = 1)

The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value

used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce

the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM

registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the

divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like

a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in

U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to

select the right value for U1DLL and U1DLM can be found later in this chapter, see

Section 15–4.16.

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Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description

Bit

Symbol Description

Reset Value

7:0

DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the

baud rate of the UART1.

0x01

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

Table 293: UART1 Divisor Latch MSB Register (U1DLM - address 0x4001 0004 when DLAB = 1) bit description

Bit

Symbol Description

Reset Value

7:0

DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the

baud rate of the UART1.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

4.4 UART1 Interrupt Enable Register (U1IER - 0x4001 0004, when

DLAB = 0)

The U1IER is used to enable the four UART1 interrupt sources.

Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description

Bit

Symbol

Value Description

Reset

Value

0

RBR

Interrupt

Enable

enables the Receive Data Available interrupt for UART1. It also controls the Character

0

Receive Time-out interrupt.

Disable the RDA interrupts.

Enable the RDA interrupts.

0

1

2

3

THRE

Interrupt

Enable

enables the THRE interrupt for UART1. The status of this interrupt can be read from

U1LSR[5].

0

1

Disable the THRE interrupts.

Enable the THRE interrupts.

RX Line

Interrupt

Enable

enables the UART1 RX line status interrupts. The status of this interrupt can be read

from U1LSR[4:1].

0

1

Disable the RX line status interrupts.

Enable the RX line status interrupts.

Modem

Status

Interrupt

Enable

enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. 0

Disable the modem interrupt.

0

1

Enable the modem interrupt.

6:4

7

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

CTS

Interrupt

Enable

If auto-cts mode is enabled this bit enables/disables the modem status interrupt

generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition

will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set.

0

In normal operation a CTS1 signal transition will generate a Modem Status Interrupt

unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER

register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both

the U1IER[3] and U1IER[7] bits are set.

0

1

Disable the CTS interrupt.

Enable the CTS interrupt.

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Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description

Bit

Symbol

Value Description

Reset

Value

8

ABEOIntEn

Enables the end of auto-baud interrupt.

0

1

Disable end of auto-baud Interrupt.

Enable end of auto-baud Interrupt.

Enables the auto-baud time-out interrupt.

Disable auto-baud time-out Interrupt.

Enable auto-baud time-out Interrupt.

9

ABTOIntEn

0

1

31:10 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

4.5 UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)

The U1IIR provides a status code that denotes the priority and source of a pending

interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during

an U1IIR access, the interrupt is recorded for the next U1IIR access.

Table 295: UART1 Interrupt Identification Register (U1IIR - address 0x4001 0008) bit description

Bit

Symbol

Value Description

Reset

Value

0

IntStatus

Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be

1

determined by evaluating U1IIR[3:1].

At least one interrupt is pending.

No interrupt is pending.

0

1

3:1

IntId

Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the

UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below

are reserved (100,101,111).

0

011

1 - Receive Line Status (RLS).

010 2a - Receive Data Available (RDA).

110 2b - Character Time-out Indicator (CTI).

001 3 - THRE Interrupt.

000 4 - Modem Interrupt.

5:4

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

7:6

8

FIFO Enable

ABEOInt

Copies of U1FCR[0].

0

End of auto-baud interrupt. True if auto-baud has finished successfully and

interrupt is enabled.

9

ABTOInt

Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is

enabled.

0

31:10 -

Reserved, the value read from a reserved bit is not defined.

NA

Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud

condition. The auto-baud interrupt conditions are cleared by setting the corresponding

Clear bits in the Auto-baud Control Register.

If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus

is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of

interrupt and handling as described in Table 15–296. Given the status of U1IIR[3:0], an

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interrupt handler routine can determine the cause of the interrupt and how to clear the

active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the

Interrupt Service Routine.

The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set

whenever any one of four error conditions occur on the UART1RX input: overrun error

(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error

condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared

upon an U1LSR read.

The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI

interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the

trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below

the trigger level. When the RDA interrupt goes active, the CPU can read a block of data

defined by the trigger level.

The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1

Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in

3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will

clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has

been received that is not a multiple of the trigger level size. For example, if a peripheral

wished to send a 105 character message and the trigger level was 10 characters, the

CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5

CTI interrupts (depending on the service routine) resulting in the transfer of the remaining

5 characters.

Table 296: UART1 Interrupt Handling

U1IIR[3:0] Priority Interrupt Interrupt Source

Interrupt Reset

value^[1]

Type

0001

-

None

-

0110

Highest RX Line

Status /

OE^[2]or PE^[2]or FE^[2]or BI^[2]

U1LSR Read^[2]

Error

0100

1100

Second RX Data Rx data available or trigger level reached in FIFO

Available (U1FCR0=1)

U1RBR Read^[3]or UART1

FIFO drops below trigger level

U1RBR Read^[3]

Second Character Minimum of one character in the RX FIFO and no

Time-out character input or removed during a time period depending

indication on how many characters are in FIFO and what the trigger

level is set at (3.5 to 4.5 character times).

The exact time will be:

[(word length) × 7 - 2] × 8 + [(trigger level - number of

characters) × 8 + 1] RCLKs

0010

0000

Third

THRE

THRE^[2]

U1IIR Read^[4](if source of

interrupt) or THR write

Fourth Modem

Status

CTS or DSR or RI or DCD

MSR Read

[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2] For details see Section 15–4.10 “UART1 Line Status Register (U1LSR - 0x4001 0014)”

[3] For details see Section 15–4.1 “UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)”

[4] For details see Section 15–4.5 “UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)” and Section

15–4.2 “UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)”

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The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated

when the UART1 THR FIFO is empty provided certain initialization conditions have been

met. These initialization conditions are intended to give the UART1 THR FIFO a chance to

fill up with data to eliminate many THRE interrupts from occurring at system start-up. The

initialization conditions implement a one character delay minus the stop bit whenever

THRE = 1 and there have not been at least two characters in the U1THR at one time since

the last THRE = 1 event. This delay is provided to give the CPU time to write data to

U1THR without a THRE interrupt to decode and service. A THRE interrupt is set

immediately if the UART1 THR FIFO has held two or more characters at one time and

currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or

a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).

It is the lowest priority interrupt and is activated whenever there is any state change on

modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem

input RI will generate a modem interrupt. The source of the modem interrupt can be

determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.

4.6 UART1 FIFO Control Register (U1FCR - 0x4001 0008)

The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs.

Table 297: UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description

Bit

Symbol

Value Description

Reset Value

0

FIFO Enable

0

1

UART1 FIFOs are disabled. Must not be used in the application.

0

Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access.

This bit must be set for proper UART1 operation. Any transition on this bit will

automatically clear the UART1 FIFOs.

1

2

RX FIFO

Reset

0

1

No impact on either of UART1 FIFOs.

0

Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the

pointer logic. This bit is self-clearing.

TX FIFO

Reset

0

1

No impact on either of UART1 FIFOs.

Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the

pointer logic. This bit is self-clearing.

3

DMA Mode

Select

When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA

mode. See Section 15–4.6.1.

5:4

7:6

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

RX Trigger

Level

These two bits determine how many receiver UART1 FIFO characters must be

written before an interrupt is activated.

0

00 Trigger level 0 (1 character or 0x01).

01 Trigger level 1 (4 characters or 0x04).

10 Trigger level 2 (8 characters or 0x08).

11 Trigger level 3 (14 characters or 0x0E).

Reserved, user software should not write ones to reserved bits.

31:8

-

NA

4.6.1 DMA Operation

The user can optionally operate the UART transmit and/or receive using DMA. The DMA

mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an

affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.

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UART receiver DMA

In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO

level becoming equal to or greater than trigger level, or if a character timeout occurs. See

the description of the RX Trigger Level above. The receiver DMA request is cleared by the

DMA controller.

UART transmitter DMA

In DMA mode, the transmitter DMA request is asserted on the event of the transmitter

FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA

controller.

4.7 UART1 Line Control Register (U1LCR - 0x4001 000C)

The U1LCR determines the format of the data character that is to be transmitted or

received.

Table 298: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description

Bit

Symbol

Value Description

Reset Value

1:0

Word Length

Select

00

01

10

11

0

5-bit character length.

0

6-bit character length.

7-bit character length.

8-bit character length.

2

Stop Bit Select

Parity Enable

Parity Select

1 stop bit.

0

1

2 stop bits (1.5 if U1LCR[1:0]=00).

Disable parity generation and checking.

Enable parity generation and checking.

3

0

1

5:4

00

Odd parity. Number of 1s in the transmitted character and the attached

parity bit will be odd.

01

Even Parity. Number of 1s in the transmitted character and the attached

parity bit will be even.

10

11

0

Forced "1" stick parity.

Forced "0" stick parity.

Disable break transmission.

6

Break Control

0

1

Enable break transmission. Output pin UART1 TXD is forced to logic 0

when U1LCR[6] is active high.

7

Divisor Latch

Access Bit (DLAB)

0

1

Disable access to Divisor Latches.

Enable access to Divisor Latches.

31:8

-

Reserved, user software should not write ones to reserved bits. The value NA

read from a reserved bit is not defined.

4.8 UART1 Modem Control Register (U1MCR - 0x4001 0010)

The U1MCR enables the modem loopback mode and controls the modem output signals.

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Table 299: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description

Bit

Symbol

DTR Control

RTS Control

-

Value Description

Reset

value

0

Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode

is active.

0

1

Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is

active.

3-2

4

NA

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

Loopback

Mode Select

The modem loopback mode provides a mechanism to perform diagnostic loopback

testing. Serial data from the transmitter is connected internally to serial input of the

receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in

marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected

externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4

modem outputs are connected to the 4 modem inputs. As a result of these

connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the

U1MCR rather than the 4 modem inputs in normal mode. This permits modem status

interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR.

0

Disable modem loopback mode.

Enable modem loopback mode.

1

5

6

-

NA

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

0

RTSen

0

1

0

1

Disable auto-rts flow control.

Enable auto-rts flow control.

Disable auto-cts flow control.

Enable auto-cts flow control.

7

CTSen

-

0

31:8

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

4.9 Auto-flow control

If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1

output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will

only start transmitting if the CTS1 input signal is asserted.

15.4.9.1 Auto-RTS

The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control

originates in the U1RBR module and is linked to the programmed receiver FIFO trigger

level. If auto-RTS is enabled, the data-flow is controlled as follows:

When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted

(to a high value). It is possible that the sending UART sends an additional byte after the

trigger level is reached (assuming the sending UART has another byte to send) because it

might not recognize the de-assertion of RTS1 until after it has begun sending the

additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO

has reached the previous trigger level. The re-assertion of RTS1 signals to the sending

UART to continue transmitting data.

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If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If

Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of

RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,

the value of the RTS Control bit is read-only for software.

Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to

0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the

receive FIFO contains 8 bytes (Table 15–297 on page 323). The RTS1 output will be

reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.

UART1 Rx

RTS1 pin

start

byte N

stop start

bits0..7

stop

start bits0..7

stop

UART1 Rx

FIFO read

UART1 Rx

FIFO level

N-1

N

N-1

N-2

N-1

N-2

M+2

M+1

M

M-1

Fig 47. Auto-RTS Functional Timing

15.4.9.2 Auto-CTS

The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the

transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data

byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the

transmitter from sending the following byte, CTS1 must be released before the middle of

the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1

signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,

Delta CTS bit in the U1MSR will be set though. Table 15–300 lists the conditions for

generating a Modem Status interrupt.

Table 300: Modem status interrupt generation

Enable Modem Status CTSen CTS Interrupt

Delta CTS Delta DCD or Trailing Edge RI ModemStatus

Interrupt (U1ER[3])

(U1MCR[7]) Enable (U1IER[7]) (U1MSR[0]) or Delta DSR (U1MSR[3] or

U1MSR[2] or U1MSR[1])

Interrupt

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

x

1

0

1

0

x

1

No

Yes

No

Yes

No

Yes

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The auto-CTS function reduces interrupts to the host system. When flow control is

enabled, a CTS1 state change does not trigger host interrupts because the device

automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any

data present in the transmit FIFO and a receiver overrun error can result. Figure 15–48

illustrates the Auto-CTS functional timing.

UART1 TX

CTS1 pin

start

bits0..7

stop

start bits0..7

stop

start

bits0..7 stop

Fig 48. Auto-CTS Functional Timing

While starting transmission of the initial character the CTS1 signal is asserted.

Transmission will stall as soon as the pending transmission has completed. The UART will

continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets

de-asserted transmission resumes and a start bit is sent followed by the data bits of the

next character.

4.10 UART1 Line Status Register (U1LSR - 0x4001 0014)

The U1LSR is a read-only register that provides status information on the UART1 TX and

RX blocks.

Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description

Bit

Symbol

Value Description

Reset

Value

0

Receiver Data

Ready (RDR)

U1LSR[0] is set when the U1RBR holds an unread character and is cleared when

the UART1 RBR FIFO is empty.

0

1

The UART1 receiver FIFO is empty.

The UART1 receiver FIFO is not empty.

1

2

Overrun Error

(OE)

The overrun error condition is set as soon as it occurs. An U1LSR read clears

U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled

and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be

overwritten and the character in the UART1 RSR will be lost.

0

1

Overrun error status is inactive.

Overrun error status is active.

Parity Error (PE)

When the parity bit of a received character is in the wrong state, a parity error

occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is

dependent on U1FCR[0].

0

Note: A parity error is associated with the character at the top of the UART1 RBR

FIFO.

0

1

Parity error status is inactive.

Parity error status is active.

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Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description

Bit

Symbol

Value Description

Reset

Value

3

Framing Error

(FE)

When the stop bit of a received character is a logic 0, a framing error occurs. An

0

U1LSR read clears U1LSR[3]. The time of the framing error detection is

dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to

resynchronize to the data and assume that the bad stop bit is actually an early

start bit. However, it cannot be assumed that the next received byte will be correct

even if there is no Framing Error.

Note: A framing error is associated with the character at the top of the UART1

RBR FIFO.

0

1

Framing error status is inactive.

Framing error status is active.

4

Break Interrupt

(BI)

When RXD1 is held in the spacing state (all zeroes) for one full character

transmission (start, data, parity, stop), a break interrupt occurs. Once the break

condition has been detected, the receiver goes idle until RXD1 goes to marking

state (all ones). An U1LSR read clears this status bit. The time of break detection

is dependent on U1FCR[0].

0

Note: The break interrupt is associated with the character at the top of the UART1

RBR FIFO.

0

1

Break interrupt status is inactive.

Break interrupt status is active.

5

6

7

Transmitter

Holding Register

Empty (THRE)

THRE is set immediately upon detection of an empty UART1 THR and is cleared

on a U1THR write.

1

0

1

U1THR contains valid data.

U1THR is empty.

Transmitter

Empty (TEMT)

TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when

either the U1TSR or the U1THR contain valid data.

0

1

U1THR and/or the U1TSR contains valid data.

U1THR and the U1TSR are empty.

Error in RX FIFO

(RXFE)

U1LSR[7] is set when a character with a RX error such as framing error, parity

error or break interrupt, is loaded into the U1RBR. This bit is cleared when the

U1LSR register is read and there are no subsequent errors in the UART1 FIFO.

0

1

U1RBR contains no UART1 RX errors or U1FCR[0]=0.

UART1 RBR contains at least one UART1 RX error.

Reserved, the value read from a reserved bit is not defined.

31:8

-

NA

4.11 UART1 Modem Status Register (U1MSR - 0x4001 0018)

The U1MSR is a read-only register that provides status information on the modem input

signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct

effect on UART1 operation, they facilitate software implementation of modem signal

operations.

Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description

Bit

Symbol

Value Description

Set upon state change of input CTS. Cleared on an U1MSR read.

Reset Value

0

Delta CTS

0

1

No change detected on modem input, CTS.

State change detected on modem input, CTS.

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Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description

Bit

Symbol

Value Description

Set upon state change of input DSR. Cleared on an U1MSR read.

Reset Value

1

Delta DSR

0

1

No change detected on modem input, DSR.

State change detected on modem input, DSR.

Set upon low to high transition of input RI. Cleared on an U1MSR read.

No change detected on modem input, RI.

2

3

Trailing Edge RI

Delta DCD

0

1

Low-to-high transition detected on RI.

Set upon state change of input DCD. Cleared on an U1MSR read.

No change detected on modem input, DCD.

0

1

State change detected on modem input, DCD.

4

CTS

DSR

RI

Clear To Send State. Complement of input signal CTS. This bit is

connected to U1MCR[1] in modem loopback mode.

0

5

Data Set Ready State. Complement of input signal DSR. This bit is

connected to U1MCR[0] in modem loopback mode.

0

6

Ring Indicator State. Complement of input RI. This bit is connected to

U1MCR[2] in modem loopback mode.

0

7

DCD

-

Data Carrier Detect State. Complement of input DCD. This bit is connected

to U1MCR[3] in modem loopback mode.

0

31:8

Reserved, the value read from a reserved bit is not defined.

NA

4.12 UART1 Scratch Pad Register (U1SCR - 0x4001 001C)

The U1SCR has no effect on the UART1 operation. This register can be written and/or

read at user’s discretion. There is no provision in the interrupt interface that would indicate

to the host that a read or write of the U1SCR has occurred.

Table 303: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description

Bit

Symbol Description

Pad A readable, writable byte.

Reset Value

7:0

0x00

4.13 UART1 Auto-baud Control Register (U1ACR - 0x4001 0020)

The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the

incoming clock/data rate for the baud rate generation and can be read and written at

user’s discretion.

Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description

Bit

Symbol

Value Description

This bit is automatically cleared after auto-baud completion.

Reset value

0

Start

0

1

Auto-baud stop (auto-baud is not running).

Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is

automatically cleared after auto-baud completion.

1

Mode

Auto-baud mode select bit.

Mode 0.

0

1

Mode 1.

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Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description

Bit

Symbol

Value Description

Reset value

2

AutoRestart

0

No restart

0

1

Restart in case of time-out (counter restarts at next UART1 Rx falling edge)

7:3

8

-

NA

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

ABEOIntClr

End of auto-baud interrupt clear bit (write-only accessible).

Writing a 0 has no impact.

0

1

Writing a 1 will clear the corresponding interrupt in the U1IIR.

Auto-baud time-out interrupt clear bit (write-only accessible).

Writing a 0 has no impact.

9

ABTOIntClr

0

1

Writing a 1 will clear the corresponding interrupt in the U1IIR.

31:10 -

NA

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

4.14 Auto-baud

The UART1 auto-baud function can be used to measure the incoming baud-rate based on

the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit

time of the receive data stream and set the divisor latch registers U1DLM and U1DLL

accordingly.

Remark: the fractional rate divider is not connected during auto-baud operations, and

therefore should not be used when the auto-baud feature is needed.

Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing

the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the

bit will return the status of auto-baud (pending/finished).

Two auto-baud measuring modes are available which can be selected by the U1ACR

Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the

UART1 Rx pin (the falling edge of the start bit and the falling edge of the least significant

bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent

rising edge of the UART1 Rx pin (the length of the start bit).

The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement

if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate

measurement will restart at the next falling edge of the UART1 Rx pin.

The auto-baud function can generate two interrupts.

• The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn

is set and the auto-baud rate measurement counter overflows).

• The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn

is set and the auto-baud has completed successfully).

The auto-baud interrupts have to be cleared by setting the corresponding U1ACR

ABTOIntClr and ABEOIntEn bits.

Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during

auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it

is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR

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register is not going to be modified after rate measurement. Also, when auto-baud is used,

any write to U1DLM and U1DLL registers should be done before U1ACR register write.

The minimum and the maximum baud rates supported by UART1 are function of pclk,

number of data bits, stop bits and parity bits.

(3)

2 × PCLK

PCLK

------------------------

-----------------------------------------------------------------------------------------------------------

= ratemax

ratemin =

≤ UART1

≤

baudrate

15

16 × (2 + databits + paritybits + stopbits)

16 × 2

4.15 Auto-baud modes

When the software is expecting an “AT” command, it configures the UART1 with the

expected character format and sets the U1ACR Start bit. The initial values in the divisor

latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding

(”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected

character are delimited by two falling edges. When the U1ACR Start bit is set, the

auto-baud protocol will execute the following phases:

1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the

UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.

2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate

measuring counter will start counting pclk cycles optionally pre-scaled by the

fractional baud-rate generator.

3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with

the frequency of the (fractional baud-rate pre-scaled) UART1 input clock,

guaranteeing the start bit is stored in the U1RSR.

4. During the receipt of the start bit (and the character LSB for mode = 0) the rate

counter will continue incrementing with the pre-scaled UART1 input clock (pclk).

5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If

Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.

6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to

normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt

U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the

remaining bits of the “A/a” character.

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'A' (0x41) or 'a' (0x61)

start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7 parity stop

UARTn RX

start bit

LSB of 'A' or 'a'

U0ACR start

rate counter

16xbaud_rate

16 cycles

a. Mode 0 (start bit and LSB are used for auto-baud)

'A' (0x41) or 'a' (0x61)

start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7 parity stop

UARTn RX

start bit

LSB of 'A' or 'a'

U1ACR start

rate counter

16xbaud_rate

16 cycles

b. Mode 1 (only start bit is used for auto-baud)

Fig 49. Auto-baud a) mode 0 and b) mode 1 waveform

4.16 UART1 Fractional Divider Register (U1FDR - 0x4001 0028)

The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the

baud rate generation and can be read and written at the user’s discretion. This pre-scaler

takes the APB clock and generates an output clock according to the specified fractional

requirements.

Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of

the DLL register must be greater than 2.

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Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description

Bit

Function

Value Description

Reset value

3:0

DIVADDVAL

0

Baud-rate generation pre-scaler divisor value. If this field is 0, fractional

0

baud-rate generator will not impact the UARTn baudrate.

7:4

MULVAL

-

1

Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for

UARTn to operate properly, regardless of whether the fractional baud-rate

generator is used or not.

1

0

31:8

NA

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

This register controls the clock pre-scaler for the baud rate generation. The reset value of

the register keeps the fractional capabilities of UART1 disabled making sure that UART1

is fully software and hardware compatible with UARTs not equipped with this feature.

UART1 baud rate can be calculated as (n = 1):

(4)

PCLK

UART1_baudrate

=

----------------------------------------------------------------------------------------------------------------------------------

DivAddVal

⎛

⎞

16 × (256 × U1DLM + U1DLL) × 1 +

----------------------------

⎝

⎠

MulVal

Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud

rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate

generator specific parameters.

The value of MULVAL and DIVADDVAL should comply to the following conditions:

1. 1 ≤ MULVAL ≤ 15

2. 0 ≤ DIVADDVAL ≤ 14

3. DIVADDVAL < MULVAL

The value of the U1FDR should not be modified while transmitting/receiving data or data

may be lost or corrupted.

If the U1FDR register value does not comply to these two requests, then the fractional

divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,

and the clock will not be divided.

4.16.1 Baud rate calculation

UART1 can operate with or without using the Fractional Divider. In real-life applications it

is likely that the desired baud rate can be achieved using several different Fractional

Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,

MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a

relative error of less than 1.1% from the desired one.

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Calculating UART

baudrate (BR)

PCLK,

BR

DL _est= PCLK/(16 x BR)

DL_estis an

integer?

True

DIVADDVAL = 0

MULVAL = 1

False

FR _est= 1.5

Pick another FR_estfrom

the range [1.1, 1.9]

DL _est= Int(PCLK/(16 x BR x FR _est))

FR_est= PCLK/(16 x BR x DL _est

)

False

1.1 < FR _est< 1.9?

True

DIVADDVAL = table(FR _est

)

MULVAL = table(FR

)

est

DLM = DL_est[15:8]

DLL = DL_est[7:0]

End

Fig 50. Algorithm for setting UART dividers

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Table 306. Fractional Divider setting look-up table

FR

DivAddVal/ FR

MulVal

DivAddVal/ FR

MulVal

DivAddVal/ FR

MulVal

DivAddVal/

MulVal

1.000

1.067

1.071

1.077

1.083

1.091

1.100

1.111

1.125

1.133

1.143

1.154

1.167

1.182

1.200

1.214

1.222

1.231

0/1

1.250

1/4

1.500

1/2

1.750

1.769

1.778

1.786

1.800

1.818

1.833

1.846

1.857

1.867

1.875

1.889

1.900

1.909

1.917

1.923

1.929

1.933

3/4

1/15

1/14

1/13

1/12

1/11

1/10

1/9

1.267

1.273

1.286

1.300

1.308

1.333

1.357

1.364

1.375

1.385

1.400

1.417

1.429

1.444

1.455

1.462

1.467

4/15

3/11

2/7

1.533

1.538

1.545

1.556

1.571

1.583

1.600

1.615

1.625

1.636

1.643

1.667

1.692

1.700

1.714

1.727

1.733

8/15

7/13

6/11

5/9

10/13

7/9

11/14

4/5

3/10

4/13

1/3

4/7

9/11

5/6

7/12

3/5

5/14

4/11

3/8

11/13

6/7

1/8

8/13

5/8

2/15

1/7

13/15

7/8

5/13

2/5

7/11

9/14

2/3

2/13

1/6

8/9

5/12

3/7

9/10

10/11

11/12

12/13

13/14

14/15

2/11

1/5

9/13

7/10

5/7

4/9

3/14

2/9

5/11

6/13

7/15

8/11

11/15

3/13

4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600

According to the provided algorithm DL_est= PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)

= 96. Since this DL_estis an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and

DLL = 96.

4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200

According to the provided algorithm DL_est= PCLK/(16 x BR) = 12 MHz / (16 x 115200) =

6.51. This DL_estis not an integer number and the next step is to estimate the FR

parameter. Using an initial estimate of FR_est= 1.5 a new DL_est= 4 is calculated and FR_est

is recalculated as FR_est= 1.628. Since FRest = 1.628 is within the specified range of 1.1

and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up

table.

The closest value for FRest = 1.628 in the look-up Table 15–306 is FR = 1.625. It is

equivalent to DIVADDVAL = 5 and MULVAL = 8.

Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,

DIVADDVAL = 5, and MULVAL = 8. According to Equation 15–4 the UART rate is 115384.

This rate has a relative error of 0.16% from the originally specified 115200.

4.17 UART1 Transmit Enable Register (U1TER - 0x4001 0030)

In addition to being equipped with full hardware flow control (auto-cts and auto-rts

mechanisms described above), U1TER enables implementation of software flow control,

too. When TxEn=1, UART1 transmitter will keep sending data as long as they are

available. As soon as TxEn becomes 0, UART1 transmission will stop.

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Although Table 15–307 describes how to use TxEn bit in order to achieve hardware flow

control, it is strongly suggested to let UART1 hardware implemented auto flow control

features take care of this, and limit the scope of TxEn to software flow control.

U1TER enables implementation of software and hardware flow control. When TXEn=1,

UART1 transmitter will keep sending data as long as they are available. As soon as TXEn

becomes 0, UART1 transmission will stop.

Table 15–307 describes how to use TXEn bit in order to achieve software flow control.

Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description

Bit

Symbol Description

Reset Value

6:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

NA

reserved bit is not defined.

7

TXEN

When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as

soon as any preceding data has been sent. If this bit cleared to 0 while a character is being

sent, the transmission of that character is completed, but no further characters are sent until

this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the

THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects

that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software

handshaking, when it receives an XOFF character (DC3). Software can set this bit again

when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1)

character.

1

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C)

The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485

mode.

Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description

Bit

Symbol Value Description

Reset value

0

NMMEN

0

1

RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.

0

RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an

address is detected when a received byte causes the UART to set the parity error

and generate an interrupt.

1

2

3

4

RXDIS

AADEN

SEL

0

1

0

1

0

1

0

1

The receiver is enabled.

0

The receiver is disabled.

Auto Address Detect (AAD) is disabled.

Auto Address Detect (AAD) is enabled.

If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0

If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.

DCTRL

Disable Auto Direction Control.

Enable Auto Direction Control.

0

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Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description

Bit

Symbol Value Description

OINV

Reset value

5

This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0

0

1

-

The direction control pin will be driven to logic ‘0’ when the transmitter has data to

be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.

The direction control pin will be driven to logic ‘1’ when the transmitter has data to

be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.

31:6

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH -

0x4001 0050)

The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485

mode.

Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description

Bit

Symbol

Description

Reset value

7:0

ADRMATCH

-

Contains the address match value.

0x00

31:8

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054)

The user may program the 8-bit RS485DLY register with a delay between the last stop bit

leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of

the baud clock. Any delay time from 0 to 255 bit times may be programmed.

Table 310. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description

Bit

Symbol

Description

Reset value

7:0

DLY

Contains the direction control (RTS or DTR) delay value. This register works in

conjunction with an 8-bit counter.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

4.21 RS-485/EIA-485 modes of operation

The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.

The addressable slave is one of multiple slaves controlled by a single master.

The UART master transmitter will identify an address character by setting the parity (9th)

bit to ‘1’. For data characters, the parity bit is set to ‘0’.

Each UART slave receiver can be assigned a unique address. The slave can be

programmed to either manually or automatically reject data following an address which is

not theirs.

RS-485/EIA-485 Normal Multidrop Mode (NMM)

Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected

when a received byte causes the UART to set the parity error and generate an interrupt.

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If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be

ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit

= ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated.

The processor can then read the address byte and decide whether or not to enable the

receiver to accept the following data.

While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be

accepted and stored in the RXFIFO regardless of whether they are data or address. When

an address character is received a parity error interrupt will be generated and the

processor can decide whether or not to disable the receiver.

RS-485/EIA-485 Auto Address Detection (AAD) mode

When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are

set, the UART is in auto address detect mode.

In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit

value programmed into the RS485ADRMATCH register.

If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if

it is either a data byte OR an address byte which fails to match the RS485ADRMATCH

value.

When a matching address character is detected it will be pushed onto the RXFIFO along

with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be

cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt.

While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be

accepted and stored in the RXFIFO until an address byte which does not match the

RS485ADRMATCH value is received. When this occurs, the receiver will be automatically

disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address

character will not be stored in the RXFIFO.

RS-485/EIA-485 Auto Direction Control

RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically

control the state of either the RTS pin or the DTR pin as a direction control output signal.

Setting RS485CTRL bit 4 = ‘1’ enables this feature.

Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use

the DTR pin when RS485CTRL bit 3 = ‘1’.

When Auto Direction Control is enabled, the selected pin will be asserted (driven low)

when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once

the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register.

The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or

DTR) with the exception of loopback mode.

RS485/EIA-485 driver delay time

The driver delay time is the delay between the last stop bit leaving the TXFIFO and the

de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY

register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit

times may be programmed.

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RS485/EIA-485 output inversion

The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by

programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control

pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction

control pin will be driven to logic 0 after the last bit of data has been transmitted.

4.22 UART1 FIFO Level register (U1FIFOLVL - 0x4001 0058)

U1FIFOLVL register is a read-only register that allows software to read the current FIFO

level status. Both the transmit and receive FIFO levels are present in this register.

Table 311. UART1 FIFO Level register (U1FIFOLVL - address 0x4001 0058) bit description

Bit

Symbol

Description

Reset value

3:0

RXFIFILVL

Reflects the current level of the UART1 receiver FIFO.

0 = empty, 0xF = FIFO full.

0x00

7:4

-

Reserved. The value read from a reserved bit is not defined.

NA

11:8 TXFIFOLVL Reflects the current level of the UART1 transmitter FIFO.

0 = empty, 0xF = FIFO full.

0x00

31:12 -

Reserved, the value read from a reserved bit is not defined.

NA

5. Architecture

The architecture of the UART1 is shown below in the block diagram.

The APB interface provides a communications link between the CPU or host and the

UART1.

The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.

The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid

character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO

to await access by the CPU or host via the generic host interface.

The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers

the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register

(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the

serial output pin, TXD1.

The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by

the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main

clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This

divided down clock is a 16x oversample clock, NBAUDOUT.

The modem interface contains registers U1MCR and U1MSR. This interface is

responsible for handshaking between a modem peripheral and the UART1.

The interrupt interface contains registers U1IER and U1IIR. The interrupt interface

receives several one clock wide enables from the U1TX and U1RX blocks.

Status information from the U1TX and U1RX is stored in the U1LSR. Control information

for the U1TX and U1RX is stored in the U1LCR.

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Transmitter

Holding

Register

Transmitter

Shift

Register

U1_TXD

Transmitter

FIFO

Transmitter

DMA

Interface

TX_DMA_REQ

TX_DMA_CLR

Baud Rate Generator

Fractional

Rate

Main

Divider

PCLK

Divider

(DLM, DLL)

UART1 interrupt

FIFO Control

& Status

U1_CTS

Interrupt

Control &

Status

U1_RTS

U1_DSR

U1_DTR

U1_DCD

U1_RI

Line Control

& Status

Modem

Control

&

RS485, IrDA,

& Auto-baud

U1_OE

Status

Receiver

Buffer

Register

Receiver

Shift

Register

U1_RXD

Receiver

FIFO

Receiver

DMA

Interface

RX_DMA_REQ

RX_DMA_CLR

Fig 51. UART1 block diagram

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User manual

1. Basic configuration

The CAN1/2 peripherals are configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bits PCAN1/2.

Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_CAN1,

PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be

the same value.

Remark: If CAN baud rates above 100 kbit/s (see Table 16–323) are needed, do not

select the IRC as the clock source (see Table 4–17).

3. Wake-up: CAN controllers are able to wake up the microcontroller from Power-down

mode, see Section 4–8.8.

4. Pins: Select CAN1/2 pins through the PINSEL registers and their pin modes through

the PINMODE registers (Section 8–5).

5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers

(Table 16–322). Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

6. CAN controller initialization: see CANMOD register (Section 16–7.1).

2. CAN controllers

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The CAN Controller is designed to provide a full

implementation of the CAN-Protocol according to the CAN Specification Version 2.0B.

Microcontrollers with this on-chip CAN controller are used to build powerful local networks

by supporting distributed real-time control with a very high level of security. The

applications are automotive, industrial environments, and high speed networks as well as

low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced

diagnostic and supervisory capabilities.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

various applications.

The CAN module consists of two elements: the controller and the Acceptance Filter. All

registers and the RAM are accessed as 32-bit words.

3. Features

3.1 General CAN features

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Multi-master architecture with non destructive bit-wise arbitration.

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• Bus access priority determined by the message identifier (11-bit or 29-bit).

• Guaranteed latency time for high priority messages.

• Programmable transfer rate (up to 1 Mbit/s).

• Multicast and broadcast message facility.

• Data length from 0 up to 8 bytes.

• Powerful error handling capability.

• Non-return-to-zero (NRZ) encoding/decoding with bit stuffing.

3.2 CAN controller features

• 2 CAN controllers and buses.

• Supports 11-bit identifier as well as 29-bit identifier.

• Double Receive Buffer and Triple Transmit Buffer.

• Programmable Error Warning Limit and Error Counters with read/write access.

• Arbitration Lost Capture and Error Code Capture with detailed bit position.

• Single Shot Transmission (no re-transmission).

• Listen Only Mode (no acknowledge, no active error flags).

• Reception of "own" messages (Self Reception Request).

3.3 Acceptance filter features

• Fast hardware implemented search algorithm supporting a large number of CAN

identifiers.

• Global Acceptance Filter recognizes 11-bit and 29-bit Rx Identifiers for all CAN buses.

• Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

4. Pin description

Table 312. CAN Pin descriptions

Pin Name

RD1, RD2

TD1, TD2

Type

Description

Input

Serial Inputs. From CAN transceivers.

Serial Outputs. To CAN transceivers.

Output

5. CAN controller architecture

The CAN Controller is a complete serial interface with both Transmit and Receive Buffers

but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a

separate block (Acceptance Filter). Except for message buffering and acceptance filtering

the functionality is similar to the PeliCAN concept.

The CAN Controller Block includes interfaces to the following blocks:

• APB Interface

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• Acceptance Filter

• Nested Vectored Interrupt Controller (NVIC)

• CAN Transceiver

• Common Status Registers

INTERFACE

MANAGEMENT

LOGIC

CAN CORE

BLOCK

APB BUS

NVIC

TX

RX

ERROR

MANAGEMENT

LOGIC

CAN

TRANSCEIVER

TRANSMIT

BUFFERS 1,2

AND 3

BIT

TIMING

LOGIC

COMMON

STATUS

REGISTER

BIT

STREAM

PROCESSOR

RECEIVE

BUFFERS 1

AND 2

ACCEPTANCE

FILTER

Fig 52. CAN controller block diagram

5.1 APB Interface Block (AIB)

The APB Interface Block provides access to all CAN Controller registers.

5.2 Interface Management Logic (IML)

The Interface Management Logic interprets commands from the CPU, controls internal

addressing of the CAN Registers and provides interrupts and status information to the

CPU.

5.3 Transmit Buffers (TXB)

The TXB represents a Triple Transmit Buffer, which is the interface between the Interface

Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is

able to store a complete message which can be transmitted over the CAN network. This

buffer is written by the CPU and read out by the BSP.

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31

24 23

16 15

8 7

0

TX

Frame info

unused TX DLC

. . .

unused

TX Priority

ID.28 ... ID.18

TFS

Descriptor

Field

0

TID

TDA

TDB

TX Data 4

TX Data 8

TX Data 3

TX Data 7

TX Data 2

TX Data 6

TX Data 1

TX Data 5

Data Field

Standard Frame Format (11-bit Identifier)

31

24 23

16 15

8 7

0

TX

Frame info

unused TX DLC

unused

TX Priority

ID.00

TFS

TID

Descriptor

Field

0 0 0 ID.28

TX Data 4

...

TX Data 3

TX Data 7

TX Data 2

TX Data 6

TX Data 1

TX Data 5

TDA

TDB

Data Field

TX Data 8

Extended Frame Format (29-bit Identifier)

Fig 53. Transmit buffer layout for standard and extended frame format configurations

5.4 Receive Buffer (RXB)

The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is

located between the CAN Controller Core Block and APB Interface Block and stores all

received messages from the CAN Bus line. With the help of this Double Receive Buffer

concept the CPU is able to process one message while another message is being

received.

The global layout of the Receive Buffer is very similar to the Transmit Buffer described

earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length

Code have the same meaning as described for the Transmit Buffer. In addition, the

Receive Buffer includes an ID Index field (see Section 16–7.9.1 “ID index field”).

The received Data Length Code represents the real transmitted Data Length Code, which

may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum

number of received data bytes is 8. This should be taken into account by reading a

message from the Receive Buffer. If there is not enough space for a new message within

the Receive Buffer, the CAN Controller generates a Data Overrun condition when this

message becomes valid and the acceptance test was positive. A message that is partly

written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This

situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if

enabled.

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31

24 23

16 15

10

9

8

7

0

RX

Frame info

unused RX DLC

unused

RX Data 3

RX Data 7

unused

ID Index

RFS

Descriptor

Field

ID.28 ... ID.18

RX Data 1

RID

RDA

RDB

RX Data 4

RX Data 8

RX Data 2

RX Data 6

Data Field

RX Data 5

BPM=bypass

message

Standard Frame Format (11-bit Identifier)

31

24 23

16 15

10

9

8

7

0

RX

Frame info

ID.28

unused RX DLC

unused

ID Index

ID.00

RFS

RID

Descriptor

Field

unused

...

RX Data 4

RX Data 8

RX Data 3

RX Data 7

RX Data 2

RX Data 6

RX Data 1

RX Data 5

RDA

RDB

Data Field

Extended Frame Format (29-bit Identifier)

Fig 54. Receive buffer layout for standard and extended frame format configurations

5.5 Error Management Logic (EML)

The EML is responsible for the error confinement. It gets error announcements from the

BSP and then informs the BSP and IML about error statistics.

5.6 Bit Timing Logic (BTL)

The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit

timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant"

Bus line transition at the beginning of a message (hard synchronization) and

re-synchronizes on further transitions during the reception of a message (soft

synchronization). The BTL also provides programmable time segments to compensate for

the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the

sample point and the number of samples to be taken within a bit time.

5.7 Bit Stream Processor (BSP)

The Bit Stream Processor is a sequencer, controlling the data stream between the

Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection,

arbitration, stuffing and error handling on the CAN Bus.

5.8 CAN controller self-tests

The CAN controller supports two different options for self-tests:

• Global Self-Test (setting the self reception request bit in normal Operating Mode)

• Local Self-Test (setting the self reception request bit in Self Test Mode)

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Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self

Reception Request, the transmitted message is also received and stored in the receive

buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the

CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.

Global self test

A Global Self-Test can for example be used to verify the chosen configuration of the CAN

Controller in a given CAN system. As shown in Figure 16–55, at least one other CAN

node, which is acknowledging each CAN message has to be connected to the CAN bus.

TX Buffer

CAN Bus

TX Buffer

Transceiver

LPC17xx

ack

RX Buffer

Fig 55. Global Self-Test (high-speed CAN Bus example)

Initiating a Global Self-Test is similar to a normal CAN transmission. In this case the

transmission of a CAN message(s) is initiated by setting Self Reception Request bit

(SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the

CAN Controller Command register (CANCMR).

Local self test

The Local Self-Test perfectly fits for single node tests. In this case an acknowledge from

other nodes is not needed. As shown in the Figure below, a CAN transceiver with an

appropriate CAN bus termination has to be connected to the LPC17xx. The CAN

Controller has to be put into the 'Self Test Mode' by setting the STM bit in the CAN

Controller Mode register (CANMOD). Hint: Setting the Self Test Mode bit (STM) is

possible only when the CAN Controller is in Reset Mode.

TX Buffer

Transceiver

LPC17xx

RX Buffer

Fig 56. Local self test (high-speed CAN Bus example)

A message transmission is initiated by setting Self Reception Request bit (SRR) in

conjunction with the selected Message Buffer(s) (STB3, STB2, STB1).

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6. Memory map of the CAN block

The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows:

Table 313. Memory map of the CAN block

Address Range

Used for

0x4003 8000 - 0x4003 87FF

0x4003 C000 - 0x4003 C017

0x4004 0000 - 0x4004 000B

0x4004 4000 - 0x4004 405F

0x4004 8000 - 0x4004 805F

0x400F C110 - 0x400F C114

Acceptance Filter RAM.

Acceptance Filter Registers.

Central CAN Registers.

CAN Controller 1 Registers.

CAN Controller 2 Registers.

CAN Wake and Sleep Registers.

7. CAN controller registers

CAN block implements the registers shown in Table 16–314 and Table 16–315. More

detailed descriptions follow.

Table 314. CAN acceptance filter and central CAN registers

Name

Description

Access

R/W

RO

Reset Value

Address

AFMR

SFF_sa

Acceptance Filter Register

1

0

0x4003 C000

0x4003 C004

0x4003 C008

0x4003 C00C

0x4003 C010

0x4003 C014

0x4003 C018

0x4003 C01C

Standard Frame Individual Start Address Register

SFF_GRP_sa Standard Frame Group Start Address Register

EFF_sa Extended Frame Start Address Register

EFF_GRP_sa Extended Frame Group Start Address Register

ENDofTable

LUTerrAd

LUTerr

End of AF Tables register

LUT Error Address register

LUT Error Register

RO

CANTxSR

CANRxSR

CANMSR

CAN Central Transmit Status Register

CAN Central Receive Status Register

CAN Central Miscellaneous Register

RO

0x0003 0300 0x4004 0000

RO

0

0x4004 0004

0x4004 0008

RO

Table 315. CAN1 and CAN2 controller register map

Generic Description

Name

Access Reset

value

CAN1 & 2 Register Name

& Address

MOD

CMR

GSR

ICR

Controls the operating mode of the CAN Controller.

Command bits that affect the state of the CAN Controller

Global Controller Status and Error Counters

R/W

1

CAN1MOD - 0x4004 4000

CAN2MOD - 0x4004 8000

CAN1CMR - 0x4004 4004

CAN2CMR - 0x4004 8004

CAN1GSR - 0x4004 4008

CAN2GSR - 0x4004 8008

CAN1ICR - 0x4004 400C

CAN2ICR - 0x4004 800C

CAN1IER - 0x4004 4010

CAN2IER - 0x4004 8010

WO

0

RO^[1]

0x3C

Interrupt status, Arbitration Lost Capture, Error Code Capture RO

0

IER

Interrupt Enable

R/W

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Table 315. CAN1 and CAN2 controller register map

Generic Description

Name

Access Reset

value

CAN1 & 2 Register Name

& Address

BTR

EWL

SR

Bus Timing

R/W^[2]

RO

0x1C0000 CAN1BTR - 0x4004 4014

CAN2BTR - 0x4004 8014

Error Warning Limit

0x60

CAN1EWL - 0x4004 4018

CAN2EWL - 0x4004 8018

Status Register

0x3C3C3C CAN1SR - 0x4004 401C

CAN2SR - 0x4004 801C

RFS

RID

Receive frame status

R/W^[2]

R/W

0

CAN1RFS - 0x4004 4020

CAN2RFS - 0x4004 8020

CAN1RID - 0x4004 4024

CAN2RID - 0x4004 8024

CAN1RDA - 0x4004 4028

CAN2RDA - 0x4004 8028

CAN1RDB - 0x4004 402C

CAN2RDB - 0x4004 802C

CAN1TFI1 - 0x4004 4030

CAN2TFI1 - 0x4004 8030

CAN1TID1 - 0x4004 4034

CAN2TID1 - 0x4004 8034

CAN1TDA1 - 0x4004 4038

CAN2TDA1 - 0x4004 8038

CAN1TDB1- 0x4004 403C

CAN2TDB1 - 0x4004 803C

CAN1TFI2 - 0x4004 4040

CAN2TFI2 - 0x4004 8040

CAN1TID2 - 0x4004 4044

CAN2TID2 - 0x4004 8044

CAN1TDA2 - 0x4004 4048

CAN2TDA2 - 0x4004 8048

CAN1TDB2 - 0x4004 404C

CAN2TDB2 - 0x4004 804C

CAN1TFI3 - 0x4004 4050

CAN2TFI3 - 0x4004 8050

CAN1TID3 - 0x4004 4054

CAN2TID3 - 0x4004 8054

CAN1TDA3 - 0x4004 4058

CAN2TDA3 - 0x4004 8058

CAN1TDB3 - 0x4004 405C

CAN2TDB3 - 0x4004 805C

Received Identifier

RDA

RDB

TFI1

TID1

TDA1

TDB1

TFI2

TID2

TDA2

TDB2

TFI3

TID3

TDA3

TDB3

Received data bytes 1-4

Received data bytes 5-8

Transmit frame info (Tx Buffer 1)

Transmit Identifier (Tx Buffer 1)

Transmit data bytes 1-4 (Tx Buffer 1)

Transmit data bytes 5-8 (Tx Buffer 1)

Transmit frame info (Tx Buffer 2)

Transmit Identifier (Tx Buffer 2)

Transmit data bytes 1-4 (Tx Buffer 2)

Transmit data bytes 5-8 (Tx Buffer 2)

Transmit frame info (Tx Buffer 3)

Transmit Identifier (Tx Buffer 3)

Transmit data bytes 1-4 (Tx Buffer 3)

Transmit data bytes 5-8 (Tx Buffer 3)

R/W

[1] The error counters can only be written when RM in CANMOD is 1.

[2] These registers can only be written when RM in CANMOD is 1.

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The internal registers of each CAN Controller appear to the CPU as on-chip memory

mapped peripheral registers. Because the CAN Controller can operate in different modes

(Operating/Reset, see also Section 16–7.1 “CAN Mode register (CAN1MOD -

0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different

internal address definitions. Note that write access to some registers is only allowed in

Reset Mode.

Table 316. CAN1 and CAN2 controller register summary

Generic Operating Mode

Reset Mode

Read

Name

Read

Write

MOD

CMR

GSR

ICR

Mode

0x00

Command

0x00

Command

Global Status and Error Counters

Interrupt and Capture

Interrupt Enable

Bus Timing

-

Global Status and Error Counters Error Counters only

Interrupt and Capture

-

IER

Interrupt Enable Interrupt Enable

Interrupt Enable

Bus Timing

Error Warning Limit

-

BTR

EWL

SR

-

Bus Timing

Error Warning Limit

Status

Error Warning Limit

Status

-

RFS

RID

Rx Info and Index

Rx Identifier

Rx Data

-

Rx Info and Index

Rx Identifier

Rx Data

Rx Info and Index

Rx Identifier

Rx Data

-

RDA

RDB

TFI1

TID1

TDA1

TDB1

-

Rx Info and Index

Tx Info1

-

Rx Info and Index

Tx Info

Rx Info and Index

Tx Info

Tx Identifier

Tx Data

Tx Identifier

Tx Data

Tx Identifier

Tx Data

Table 317. CAN Wake and Sleep registers

Name

Description

Access Reset Value Address

CANSLEEPCLR

Allows clearing the current CAN channel sleep state as well as R/W

reading that state.

0

0x400F C110

CANWAKEFLAGS Allows reading the wake-up state of the CAN channels.

R/W

0

0x400F C114

In the following register tables, the column “Reset Value” shows how a hardware reset

affects each bit or field, while the column “RM Set” indicates how each bit or field is

affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that

while hardware reset sets RM, in this case the setting noted in the “Reset Value” column

prevails over that shown in the “RM Set” column, in the few bits where they differ. In both

columns, X indicates the bit or field is unchanged.

7.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD -

0x4004 8000)

The contents of the Mode Register are used to change the behavior of the CAN

Controller. Bits may be set or reset by the CPU that uses the Mode Register as a

read/write memory.

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Table 318. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description

Bit

Symbol Value

Function

Reset RM

Value Set

0

RM^[1][6]

Reset Mode.

1

0 (normal)

The CAN Controller is in the Operating Mode, and certain registers can not

be written.

1 (reset)

CAN operation is disabled, writable registers can be written and the current

transmission/reception of a message is aborted.

1

2

LOM^[3][2]

Listen Only Mode.

0

x

[6]

0 (normal)

The CAN controller acknowledges a successfully received message on the

CAN bus. The error counters are stopped at the current value.

1 (listen only) The controller gives no acknowledgment, even if a message is successfully

received. Messages cannot be sent, and the controller operates in “error

passive” mode. This mode is intended for software bit rate detection and

“hot plugging”.

STM^[3][6]

Self Test Mode.

0

x

0 (normal)

1 (self test)

A transmitted message must be acknowledged to be considered successful.

The controller will consider a Tx message successful even if there is no

acknowledgment received.

In this mode a full node test is possible without any other active node on the

bus using the SRR bit in CANxCMR.

3

4

TPM^[4]

Transmit Priority Mode.

0

x

0 (CAN ID)

The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.

1 (local prio)

The transmit priority for 3 Transmit Buffers depends on the contents of the

Tx Priority register within the Transmit Buffer.

SM^[5]

Sleep Mode.

0

0 (wake-up)

1 (sleep)

Normal operation.

The CAN controller enters Sleep Mode if no CAN interrupt is pending and

there is no bus activity. See the Sleep Mode description Section 16–8.2 on

page 369.

5

RPM

Receive Polarity Mode.

0

x

0 (low active) RD input is active Low (dominant bit = 0).

1 (high active) RD input is active High (dominant bit = 1) -- reverse polarity.

6

7

-

Reserved, user software should not write ones to reserved bits.

0

x

TM

Test Mode.

0 (disabled)

1 (enabled)

Normal operation.

The TD pin will reflect the bit, detected on RD pin, with the next positive

edge of the system clock.

31:8

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

[1] During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit

is set '0' the CAN Controller will wait for:

- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated

reset.

- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the

Bus-On mode.

[2] This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can

be used e.g. for software driven bit rate detection and "hot plugging".

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[3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.

[4] Transmit Priority Mode is explained in more detail in Section 16–5.3 “Transmit Buffers (TXB)”.

[5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts

is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN

Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping

CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits

(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only

when Bus-Free is detected again.

[6] The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.

7.2 CAN Command Register (CAN1CMR - 0x4004 x004, CAN2CMR -

0x4004 8004)

Writing to this write-only register initiates an action within the transfer layer of the CAN

Controller. Reading this register yields zeroes.

At least one internal clock cycle is needed for processing between two commands.

Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit

description

Bit

Symbol Value

Function

Reset RM

Value Set

0^[1][2]TR

Transmission Request.

No transmission request.

0

0 (absent)

1 (present)

The message, previously written to the CANxTFI, CANxTID, and

optionally the CANxTDA and CANxTDB registers, is queued for

transmission from the selected Transmit Buffer. If at two or all three of

STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit

Buffer will be selected based on the chosen priority scheme (for details

see Section 16–5.3 “Transmit Buffers (TXB)”)

1^[1][3]AT

Abort Transmission.

0

0 (no action)

1 (present)

Do not abort the transmission.

if not already in progress, a pending Transmission Request for the

selected Transmit Buffer is cancelled.

2^[4]

RRB

Release Receive Buffer.

0 (no action)

1 (released)

Do not release the receive buffer.

The information in the Receive Buffer (consisting of CANxRFS,

CANxRID, and if applicable the CANxRDA and CANxRDB registers) is

released, and becomes eligible for replacement by the next received

frame. If the next received frame is not available, writing this command

clears the RBS bit in the Status Register(s).

3^[5]

CDO

Clear Data Overrun.

0

0 (no action)

1 (clear)

Do not clear the data overrun bit.

The Data Overrun bit in Status Register(s) is cleared.

Self Reception Request.

4^[1][6]SRR

0 (absent)

1 (present)

No self reception request.

The message, previously written to the CANxTFS, CANxTID, and

optionally the CANxTDA and CANxTDB registers, is queued for

transmission from the selected Transmit Buffer and received

simultaneously. This differs from the TR bit above in that the receiver is

not disabled during the transmission, so that it receives the message if its

Identifier is recognized by the Acceptance Filter.

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Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit

description

Bit

Symbol Value

Function

Reset RM

Value Set

5

STB1

Select Tx Buffer 1.

0

0 (not selected)

Tx Buffer 1 is not selected for transmission.

Tx Buffer 1 is selected for transmission.

Select Tx Buffer 2.

1 (selected)

6

STB2

STB3

-

0

0 (not selected)

1 (selected)

Tx Buffer 2 is not selected for transmission.

Tx Buffer 2 is selected for transmission.

Select Tx Buffer 3.

7

0

0 (not selected)

1 (selected)

Tx Buffer 3 is not selected for transmission.

Tx Buffer 3 is selected for transmission.

Reserved, user software should not write ones to reserved bits.

31:8

NA

[1] - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in

case of an error or arbitration lost (single shot transmission).

- Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.

No re-transmission will be performed in case of an error or arbitration lost.

- Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The

moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically.

- Setting TR and SRR simultaneously will ignore the set SRR bit.

[2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the

bits. The requested transmission may only be cancelled by setting the Abort Transmission bit.

[3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a

more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either

transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit

Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated.

[4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'.

This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is

reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated.

[5] This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun

Status bit is set no further Data Overrun Interrupt is generated.

[6] Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding

identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16–7.1 “CAN Mode

register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”).

7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR -

0x4004 8008)

The content of the Global Status Register reflects the status of the CAN Controller. This

register is read-only, except that the Error Counters can be written when the RM bit in the

CANMOD register is 1. Bits not listed read as 0 and should be written as 0.

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Table 320. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit

description

Bit

Symbol Value

Function

Reset RM

Value Set

0

RBS^[1]

Receive Buffer Status.

0

1

0

1

0 (empty)

No message is available.

1 (full)

At least one complete message is received by the Double Receive Buffer

and available in the CANxRFS, CANxRID, and if applicable the CANxRDA

and CANxRDB registers. This bit is cleared by the Release Receive Buffer

command in CANxCMR, if no subsequent received message is available.

1

2

DOS^[2]

Data Overrun Status.

0 (absent)

1 (overrun)

No data overrun has occurred since the last Clear Data Overrun command

was given/written to CANxCMR (or since Reset).

A message was lost because the preceding message to this CAN controller

was not read and released quickly enough (there was not enough space for

a new message in the Double Receive Buffer).

TBS

Transmit Buffer Status.

0 (locked)

At least one of the Transmit Buffers is not available for the CPU, i.e. at least

one previously queued message for this CAN controller has not yet been

sent, and therefore software should not write to the CANxTFI, CANxTID,

CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).

1 (released)

All three Transmit Buffers are available for the CPU. No transmit message is

pending for this CAN controller (in any of the 3 Tx buffers), and software may

write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.

3

TCS^[3]

Transmit Complete Status.

1

x

0 (incomplete) At least one requested transmission has not been successfully completed

yet.

1 (complete)

All requested transmission(s) has (have) been successfully completed.

Receive Status.

4

5

6

RS^[4]

TS^[4]

ES^[5]

1

0

0 (idle)

The CAN controller is idle.

1 (receive)

The CAN controller is receiving a message.

Transmit Status.

0 (idle)

The CAN controller is idle.

1 (transmit)

The CAN controller is sending a message.

Error Status.

0 (ok)

Both error counters are below the Error Warning Limit.

1 (error)

One or both of the Transmit and Receive Error Counters has reached the

limit set in the Error Warning Limit register.

7

BS^[6]

Bus Status.

0

0 (Bus-On)

1 (Bus-Off)

The CAN Controller is involved in bus activities

The CAN controller is currently not involved/prohibited from bus activity

because the Transmit Error Counter reached its limiting value of 255.

15:8

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

23:16 RXERR

31:24 TXERR

-

The current value of the Rx Error Counter (an 8-bit value).

The current value of the Tx Error Counter (an 8-bit value).

0

X

[1] After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.

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[2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is

signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an

error), no overrun condition is signalled.

[3] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit

is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are

transmitted successfully.

[4] If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to

become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this

will take 128 times of 11 consecutive recessive bits.

[5] Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is

set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if

enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 16–7.7 “CAN Error Warning

Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)”.

[6] Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and

the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN

Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error

Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error

Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the

Bus-Off recovery.

RX error counter

The RX Error Counter Register, which is part of the Status Register, reflects the current

value of the Receive Error Counter. After hardware reset this register is initialized to 0. In

Operating Mode this register appears to the CPU as a read-only memory. A write access

to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error

Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no

effect.The Rx Error Counter is determined as follows:

RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000

Note that a CPU-forced content change of the RX Error Counter is possible only if the

Reset Mode was entered previously. An Error Status change (Status Register), an Error

Warning or an Error Passive Interrupt forced by the new register content will not occur

until the Reset Mode is cancelled again.

TX error counter

The TX Error Counter Register, which is part of the Status Register, reflects the current

value of the Transmit Error Counter. In Operating Mode this register appears to the CPU

as a read-only memory. After hardware reset this register is initialized to 0. A write access

to this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error

Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences

of the Bus-Free signal). Reading the TX Error Counter during this time gives information

about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in

the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence

of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error

counter is determined as follows:

TX Error Counter = (CANxGSR AND 0xFF000000) / 0x01000000

Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a

CPU-forced content change of the TX Error Counter is possible only if the Reset Mode

was entered previously. An Error or Bus Status change (Status Register), an Error

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Warning, or an Error Passive Interrupt forced by the new register content will not occur

until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX

Counter content is interpreted and the Bus Off event is performed in the same way as if it

was forced by a bus error event. That means, that the Reset Mode is entered again, the

TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status

and Interrupt Register bits are set. Clearing of Reset Mode now will perform the protocol

defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal).

If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus

Off keeps active and TXERR is frozen.

7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C,

CAN2ICR - 0x4004 800C)

Bits in this register indicate information about events on the CAN bus. This register is

read-only.

The Interrupt flags of the Interrupt and Capture Register allow the identification of an

interrupt source. When one or more bits are set, a CAN interrupt will be indicated to the

CPU. After this register is read from the CPU all interrupt bits are reset except of the

Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory.

Bits 1 through 10 clear when they are read.

Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in

CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur.

Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in

CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either

of these bytes is captured, its value will remain the same until it is read, at which time it is

released to capture a new value.

The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read

from CANxICR, regardless of whether part or all of the register is read. This means that

software should always read CANxICR as a word, and process and deal with all bits of the

register as appropriate for the application.

Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)

bit description

Bit

Symbol Value

Function

Reset RM

Value Set

0

RI^[1]

TI1

EI

0 (reset) Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE

0

X

1 (set)

bit in CANxIER are both 1, indicating that a new message was received and

stored in the Receive Buffer.

1

2

0 (reset) Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to

1 (set)

1 (whenever a message out of TXB1 was successfully transmitted or aborted),

indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.

0 (reset) Error Warning Interrupt. This bit is set on every change (set or clear) of either the

1 (set)

Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the

Interrupt Enable Register at the time of the change.

3

4

DOI

0 (reset) Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0

1 (set) to 1 and the DOIE bit in CANxIER is 1.

0

WUI^[2]

0 (reset) Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity

1 (set)

is detected and the WUIE bit in CANxIER is 1.

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Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)

bit description

Bit

Symbol Value

Function

Reset RM

Value Set

5

EPI

0 (reset) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the

0

1 (set)

CAN controller switches between Error Passive and Error Active mode in either

direction.

This is the case when the CAN Controller has reached the Error Passive Status

(at least one error counter exceeds the CAN protocol defined level of 127) or if

the CAN Controller is in Error Passive Status and enters the Error Active Status

again.

6

ALI

0 (reset) Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the

0

1 (set)

CAN controller loses arbitration while attempting to transmit. In this case the

CAN node becomes a receiver.

7

8

BEI

IDI

0 (reset) Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN

1 (set) controller detects an error on the bus.

0

X

0

0 (reset) ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN

1 (set)

Identifier has been received (a message was successfully transmitted or

aborted). This bit is set whenever a message was successfully transmitted or

aborted and the IDIE bit is set in the IER register.

9

TI2

TI3

0 (reset) Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to

0

1 (set)

1 (whenever a message out of TXB2 was successfully transmitted or aborted),

indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.

10

0 (reset) Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to

1 (set)

1 (whenever a message out of TXB3 was successfully transmitted or aborted),

indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.

15:11 -

-

Reserved, user software should not write ones to reserved bits.

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Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)

bit description

Bit

Symbol Value

Function

Reset RM

Value Set

20:16 ERRBIT

4:0^[3]

Error Code Capture: when the CAN controller detects a bus error, the location of

the error within the frame is captured in this field. The value reflects an internal

state variable, and as a result is not very linear:

0

X

00011

00010

00110

00100

00101

00111

01111

01110

01100

01101

01001

01011

01010

01000

11000

11001

11011

11010

10010

10001

10110

10011

10111

11100

Start of Frame

ID28 ... ID21

ID20 ... ID18

SRTR Bit

IDE bit

ID17 ... 13

ID12 ... ID5

ID4 ... ID0

RTR Bit

Reserved Bit 1

Reserved Bit 0

Data Length Code

Data Field

CRC Sequence

CRC Delimiter

Acknowledge Slot

Acknowledge Delimiter

End of Frame

Intermission

Active Error Flag

Passive Error Flag

Tolerate Dominant Bits

Error Delimiter

Overload flag

21

ERRDIR

When the CAN controller detects a bus error, the direction of the current bit is

captured in this bit.

0

X

0

1

Error occurred during transmitting.

Error occurred during receiving.

23:22 ERRC1:0

When the CAN controller detects a bus error, the type of error is captured in this

field:

00

01

10

11

Bit error

Form error

Stuff error

Other error

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Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)

bit description

Bit

Symbol Value

Function

Reset RM

Value Set

31:24 ALCBIT^[4]

-

Each time arbitration is lost while trying to send on the CAN, the bit number

within the frame is captured into this field. After the content of ALCBIT is read,

the ALI bit is cleared and a new Arbitration Lost interrupt can occur.

0

X

00

...

arbitration lost in the first bit (MS) of identifier

11

12

13

...

arbitration lost in SRTS bit (RTR bit for standard frame messages)

arbitration lost in IDE bit

arbitration lost in 12th bit of identifier (extended frame only)

30

31

arbitration lost in last bit of identifier (extended frame only)

arbitration lost in RTR bit (extended frame only)

[1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command

“Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive

Buffer after the release command, RI is set again. Otherwise RI remains cleared.

[2] A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is

involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the

according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.

[3] Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time,

the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The

content within this register is fixed until the user software has read out its content once. From now on, the

capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.

[4] On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current

bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content

within this register is fixed until the user application has read out its contents once. From now on, the

capture mechanism is activated again.

7.5 CAN Interrupt Enable Register (CAN1IER - 0x4004 4010, CAN2IER -

0x4004 8010)

This read/write register controls whether various events on the CAN controller will result in

an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the

CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt is

disabled; if a bit in the CANxIER register is 1 the corresponding source is enabled to

trigger an interrupt.

Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit

description

Bit

Symbol Function

Reset RM

Value Set

0

RIE

Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller

0

X

requests the respective interrupt.

1

TIE1

Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted

out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission

command), the CAN Controller requests the respective interrupt.

0

X

2

EIE

Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the

CAN Controller requests the respective interrupt.

0

X

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Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit

description

Bit

Symbol Function

Reset RM

Value Set

3

DOIE

WUIE

EPIE

ALIE

BEIE

IDIE

Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the

CAN Controller requests the respective interrupt.

0

X

4

Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt

is requested.

5

Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error

active to error passive or vice versa, the respective interrupt is requested.

6

Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective

interrupt is requested.

7

Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the

respective interrupt.

8

ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller

requests the respective interrupt.

9

TIE2

Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted

out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission

command), the CAN Controller requests the respective interrupt.

10

TIE3

Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted

out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission

command), the CAN Controller requests the respective interrupt.

0

X

31:11 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR -

0x4004 8014)

This register controls how various CAN timings are derived from the APB clock. It defines

the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW).

Furthermore, it defines the length of the bit period, the location of the sample point and the

number of samples to be taken at each sample point. It can be read at any time but can

only be written if the RM bit in CANmod is 1.

Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit

description

Bit

Symbol Value Function

Reset RM

Value Set

9:0

BRP

Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the

CAN clock.

0

X

13:10 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

15:14 SJW

The Synchronization Jump Width is (this value plus one) CAN clocks.

0

X

19:16 TESG1

The delay from the nominal Sync point to the sample point is (this value plus one)

CAN clocks.

1100

22:20 TESG2

The delay from the sample point to the next nominal sync point is (this value plus one) 001

CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3)

CAN clocks.

X

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Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit

description

Bit

Symbol Value Function

Reset RM

Value Set

23

SAM

Sampling

0

1

The bus is sampled once (recommended for high speed buses)

0

X

The bus is sampled 3 times (recommended for low to medium speed buses to filter

spikes on the bus-line)

31:24 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

Baud rate prescaler

The period of the CAN system clock t_SCLis programmable and determines the individual

bit timing. The CAN system clock t_SCLis calculated using the following equation:

(5)

t_SCL= t_{CANsuppliedCLK}× (BRP + 1)

Synchronization jump width

To compensate for phase shifts between clock oscillators of different bus controllers, any

bus controller must re-synchronize on any relevant signal edge of the current

transmission. The synchronization jump width t_SJWdefines the maximum number of clock

cycles a certain bit period may be shortened or lengthened by one re-synchronization:

(6)

t_SJW= t_SCL× (SJW + 1)

Time segment 1 and time segment 2

Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period

and the location of the sample point:

(7)

t_SYNCSEG= t_SCL

(8)

t_TSEG1= t_SCL× (TSEG1 + 1)

(9)

t_TSEG2= t_SCL× (TSEG2 + 1)

7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018,

CAN2EWL - 0x4004 8018)

This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read

at any time but can only be written if the RM bit in CANmod is 1.

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Table 324. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018)

bit description

Bit

Symbol Function

Reset

Value

RM

Set

7:0

EWL

-

During CAN operation, this value is compared to both the Tx and Rx Error Counters. If 96₁₀= 0x60 X

either of these counter matches this value, the Error Status (ES) bit in CANSR is set.

31:8

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

Note that a content change of the Error Warning Limit Register is possible only if the

Reset Mode was entered previously. An Error Status change (Status Register) and an

Error Warning Interrupt forced by the new register content will not occur until the Reset

Mode is cancelled again.

7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR -

0x4004 801C)

This read-only register contains three status bytes in which the bits not related to

transmission are identical to the corresponding bits in the Global Status Register, while

those relating to transmission reflect the status of each of the 3 Tx Buffers.

Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description

Bit

Symbol Value

Function

Reset RM

Value Set

0

1

2

RBS

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

Transmit Buffer Status 1.

0

1

0

1

DOS

TBS1^[1]

0(locked)

Software cannot access the Tx Buffer 1 nor write to the corresponding

CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a

message is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 1 and its CANxTFI,

CANxTID, CANxTDA, and CANxTDB registers.

3

TCS1^[2]

Transmission Complete Status.

1

x

0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 1 has been successfully

completed.

4

5

RS

Receive Status. This bit is identical to the RS bit in the GSR.

Transmit Status 1.

1

0

TS1

0(idle)

There is no transmission from Tx Buffer 1.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 1.

Error Status. This bit is identical to the ES bit in the CANxGSR.

Bus Status. This bit is identical to the BS bit in the CANxGSR.

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

6

7

8

9

ES

0

BS

RBS

DOS

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Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description

Bit

Symbol Value

Function

Reset RM

Value Set

10

TBS2^[1]

Transmit Buffer Status 2.

1

x

0(locked)

Software cannot access the Tx Buffer 2 nor write to the corresponding

CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a

message is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 2 and its CANxTFI,

CANxTID, CANxTDA, and CANxTDB registers.

11

TCS2^[2]

Transmission Complete Status.

0(incomplete) The previously requested transmission for Tx Buffer 2 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 2 has been successfully

completed.

12

13

RS

Receive Status. This bit is identical to the RS bit in the GSR.

Transmit Status 2.

1

0

TS2

0(idle)

There is no transmission from Tx Buffer 2.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 2.

Error Status. This bit is identical to the ES bit in the CANxGSR.

Bus Status. This bit is identical to the BS bit in the CANxGSR.

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

Transmit Buffer Status 3.

14

15

16

17

18

ES

0

1

0

1

BS

RBS

DOS

TBS3^[1]

0(locked)

Software cannot access the Tx Buffer 3 nor write to the corresponding

CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a

message is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 3 and its CANxTFI,

CANxTID, CANxTDA, and CANxTDB registers.

19

TCS3^[2]

Transmission Complete Status.

1

x

0(incomplete) The previously requested transmission for Tx Buffer 3 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 3 has been successfully

completed.

20

21

RS

Receive Status. This bit is identical to the RS bit in the GSR.

Transmit Status 3.

1

0

TS3

0(idle)

There is no transmission from Tx Buffer 3.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 3.

Error Status. This bit is identical to the ES bit in the CANxGSR.

Bus Status. This bit is identical to the BS bit in the CANxGSR.

Reserved, the value read from a reserved bit is not defined.

22

ES

BS

-

0

23

0

31:24

NA

[1] If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is

lost without this being signalled.

[2] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit

is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully.

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7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020,

CAN2RFS - 0x4004 8020)

This register defines the characteristics of the current received message. It is read-only in

normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1.

Table 326. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020)

bit description

Bit

Symbol Function

Reset RM

Value Set

9:0

ID Index If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry

at which the Acceptance Filter matched the received Identifier. Disabled entries in the

Standard tables are included in this numbering, but will not be matched. See Section 16–17

“Examples of acceptance filter tables and ID index values” on page 391 for examples of ID

Index values.

0

X

10

BP

If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field

(above) is meaningless.

0

X

15:11 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

19:16 DLC

The field contains the Data Length Code (DLC) field of the current received message. When

RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB

registers as follows:

0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes

With RTR = 1, this value indicates the number of data bytes requested to be sent back, with

the same encoding.

29:20 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

30

RTR

This bit contains the Remote Transmission Request bit of the current received message. 0

indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA

and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC

value identifies the number of data bytes requested to be sent using the same Identifier.

X

31

FF

A 0 in this bit indicates that the current received message included an 11-bit Identifier, while

a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described

below.

0

7.9.1 ID index field

The ID Index is a 10-bit field in the Info Register that contains the table position of the ID

Look-up Table if the currently received message was accepted. The software can use this

index to simplify message transfers from the Receive Buffer into the Shared Message

Memory. Whenever bit 10 (BP) of the ID Index in the CANRFS register is 1, the current

CAN message was received in acceptance filter bypass mode.

7.10 CAN Receive Identifier register (CAN1RID - 0x4004 4024, CAN2RID -

0x4004 8024)

This register contains the Identifier field of the current received message. It is read-only in

normal operation but can be written for testing purposes if the RM bit in CANmod is 1. It

has two different formats depending on the FF bit in CANRFS. See Table 16–314 for

details on specific CAN channel register address.

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Table 327. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit

description

Bit

Symbol Function

Reset Value RM Set

10:0 ID

The 11-bit Identifier field of the current received message. In CAN 2.0A, these

bits are called ID10-0, while in CAN 2.0B they’re called ID29-18.

0

X

31:11 -

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

Table 328. RX Identifier register when FF = 1

Bit Symbol Function

Reset Value RM Set

28:0 ID

The 29-bit Identifier field of the current received message. In CAN 2.0B these bits

are called ID29-0.

0

X

31:29 -

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

7.11 CAN Receive Data register A (CAN1RDA - 0x4004 4028, CAN2RDA -

0x4004 8028)

This register contains the first 1-4 Data bytes of the current received message. It is

read-only in normal operation, but can be written for testing purposes if the RM bit in

CANMOD is 1. See Table 16–314 for details on specific CAN channel register address.

Table 329. CAN Receive Data register A (CAN1RDA - address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit

description

Bit

Symbol Function

Reset Value RM Set

7:0

Data 1

If the DLC field in CANRFS ≥ 0001, this contains the first Data byte of the current

0

X

received message.

15:8 Data 2

23:16 Data 3

31:24 Data 4

If the DLC field in CANRFS ≥ 0010, this contains the first Data byte of the current

received message.

If the DLC field in CANRFS ≥ 0011, this contains the first Data byte of the current

received message.

If the DLC field in CANRFS ≥ 0100, this contains the first Data byte of the current

received message.

7.12 CAN Receive Data register B (CAN1RDB - 0x4004 402C, CAN2RDB -

0x4004 802C)

This register contains the 5th through 8th Data bytes of the current received message. It is

read-only in normal operation, but can be written for testing purposes if the RM bit in

CANMOD is 1. See Table 16–314 for details on specific CAN channel register address.

Table 330. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit

description

Bit

Symbol Function

Data 5 If the DLC field in CANRFS ≥ 0101, this contains the first Data byte of the current

received message.

Reset Value RM Set

7:0

0

X

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Table 330. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit

description

Bit

Symbol Function

Reset Value RM Set

15:8 Data 6

23:16 Data 7

31:24 Data 8

If the DLC field in CANRFS ≥ 0110, this contains the first Data byte of the current

0

X

received message.

If the DLC field in CANRFS ≥ 0111, this contains the first Data byte of the current

received message.

If the DLC field in CANRFS ≥ 1000, this contains the first Data byte of the current

received message.

7.13 CAN Transmit Frame Information register (CAN1TFI[1/2/3] -

0x4004 40[30/ 40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50])

When the corresponding TBS bit in CANSR is 1, software can write to one of these

registers to define the format of the next transmit message for that Tx buffer. Bits not listed

read as 0 and should be written as 0.

The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be

set to the values expected in the Receive Buffer for an easy comparison, when using the

Self Reception facility (self test), otherwise they are not defined.

The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4

words and is able to store one complete CAN message as shown in Figure 16–53.

The buffer layout is subdivided into Descriptor and Data Field where the first word of the

Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data

Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows

the definition of a certain priority for each transmit message. Depending on the chosen

Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier

for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to

be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes.

Table 331. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] -

0x4004 80[30/40/50]) bit description

Bit

Symbol Function

Reset RM

Value Set

7:0

PRIO

If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx

x

Buffers contend for the right to send their messages based on this field. The buffer with the

lowest TX Priority value wins the prioritization and is sent first.

15:8

-

Reserved.

0

19:16 DLC

Data Length Code. This value is sent in the DLC field of the next transmit message. In

addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit

message, from the CANxTDA and CANxTDB registers:

0

X

0000-0111 = 0-7 bytes

1xxx = 8 bytes

29:20 -

Reserved.

0

30

RTR

This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of

data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers.

If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.

X

31

FF

If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame

format), while if it’s 1, the message will be sent with a 29-bit Identifier (extended frame

format).

0

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Automatic transmit priority detection

To allow uninterrupted streams of transmit messages, the CAN Controller provides

Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selected

Transmit Priority Mode, internal prioritization is based on the CAN Identifier or a user

defined "local priority". If more than one message is enabled for transmission (TR=1) the

internal transmit message queue is organized such as that the transmit buffer with the

lowest CAN Identifier (TID) or the lowest "local priority" (TX Priority) wins the prioritization

and is sent first. The result of the internal scheduling process is taken into account short

before a new CAN message is sent on the bus. This is also true after the occurrence of a

transmission error and right before a re-transmission.

Tx DLC

The number of bytes in the Data Field of a message is coded with the Data Length Code

(DLC). At the start of a Remote Frame transmission the DLC is not considered due to the

RTR bit being '1 ' (remote). This forces the number of transmitted/received data bytes to

be 0. Nevertheless, the DLC must be specified correctly to avoid bus errors, if two CAN

Controllers start a Remote Frame transmission with the same identifier simultaneously.

For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 is

selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in

DLC. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows:

(10)

DataByteCount = DLC

7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] -

0x4004 40[34/44/54], CAN2TID[1/2/3] - 0x4004 80[34/44/54])

When the corresponding TBS bit in CANxSR is 1, software can write to one of these

registers to define the Identifier field of the next transmit message. Bits not listed read as 0

and should be written as 0. The register assumes two different formats depending on the

FF bit in CANTFI.

In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 to

ID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits

(ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during

the arbitration process. The Identifier acts as the message's name, used in a receiver for

acceptance filtering, and also determines the bus access priority during the arbitration

process.

Table 332. CAN Transfer Identifier register (CAN1TID[1/2/3] - address 0x4004 40[34/44/54], CAN2TID[1/2/3] - address

0x4004 80[34/44/54]) bit description

Bit

Symbol Function

Reset Value RM Set

10:0 ID

31:11 -

The 11-bit Identifier to be sent in the next transmit message.

0

X

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

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Table 333. Transfer Identifier register when FF = 1

Bit

Symbol Function

Reset Value RM Set

28:0 ID

31:29 -

The 29-bit Identifier to be sent in the next transmit message.

0

X

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58],

CAN2TDA[1/2/3] - 0x4004 80[38/48/58])

When the corresponding TBS bit in CANSR is 1, software can write to one of these

registers to define the first 1 - 4 data bytes of the next transmit message. The Data Length

Code defines the number of transferred data bytes. The first bit transmitted is the most

significant bit of TX Data Byte 1.

Table 334. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address

0x4004 80[38/48/58]) bit description

Bit

Symbol Function

Reset Value RM Set

7:0

Data 1

If RTR = 0 and DLC ≥ 0001 in the corresponding CANxTFI, this byte is sent as

0

X

the first Data byte of the next transmit message.

15;8 Data 2

23:16 Data 3

31:24 Data 4

If RTR = 0 and DLC ≥ 0010 in the corresponding CANxTFI, this byte is sent as

the 2nd Data byte of the next transmit message.

If RTR = 0 and DLC ≥ 0011 in the corresponding CANxTFI, this byte is sent as

the 3rd Data byte of the next transmit message.

If RTR = 0 and DLC ≥ 0100 in the corresponding CANxTFI, this byte is sent as

the 4th Data byte of the next transmit message.

7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] - 0x4004 40[3C/4C/5C],

CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C])

When the corresponding TBS bit in CANSR is 1, software can write to one of these

registers to define the 5th through 8th data bytes of the next transmit message. The Data

Length Code defines the number of transferred data bytes. The first bit transmitted is the

most significant bit of TX Data Byte 1.

Table 335. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address

0x4004 80[3C/4C/5C]) bit description

Bit

Symbol Function

Data 5

Reset Value RM Set

7:0

If RTR = 0 and DLC ≥ 0101 in the corresponding CANTFI, this byte is sent as the

0

X

5th Data byte of the next transmit message.

15;8 Data 6

23:16 Data 7

31:24 Data 8

If RTR = 0 and DLC ≥ 0110 in the corresponding CANTFI, this byte is sent as the

6th Data byte of the next transmit message.

If RTR = 0 and DLC ≥ 0111 in the corresponding CANTFI, this byte is sent as the

7th Data byte of the next transmit message.

If RTR = 0 and DLC ≥ 1000 in the corresponding CANTFI, this byte is sent as the

8th Data byte of the next transmit message.

7.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110)

This register provides the current sleep state of the two CAN channels and provides a

means to restore the clocks to that channel following wake-up. Refer to Section 16–8.2

“Sleep mode” for more information on the CAN sleep feature.

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Table 336. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description

Bit

Symbol

Function

Reset Value

0

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

1

CAN1SLEEP Sleep status and control for CAN channel 1.

Read: when 1, indicates that CAN channel 1 is in the sleep mode.

Write: writing a 1 causes clocks to be restored to CAN channel 1.

CAN2SLEEP Sleep status and control for CAN channel 2.

0

2

Read: when 1, indicates that CAN channel 2 is in the sleep mode.

Write: writing a 1 causes clocks to be restored to CAN channel 2.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114)

This register provides the wake-up status for the two CAN channels and allows clearing

wake-up events. Refer to Section 16–8.2 “Sleep mode” for more information on the CAN

sleep feature.

Table 337. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description

Bit

Symbol

Function

Reset Value

0

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

1

Wake-up status for CAN channel 1.

CAN1WAKE

0

Read: when 1, indicates that a falling edge has occurred on the receive data line of

CAN channel 1.

Write: writing a 1 clears this bit.

2

CAN2WAKE Wake-up status for CAN channel 2.

Read: when 1, indicates that a falling edge has occurred on the receive data line of

0

CAN channel 2.

Write: writing a 1 clears this bit.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

8. CAN controller operation

8.1 Error handling

The CAN Controllers count and handle transmit and receive errors as specified in CAN

Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected

error and are decremented when operation is error-free. If the Transmit Error counter

contains 255 and another error occurs, the CAN Controller is forced into a state called

Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in

CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the

CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive

Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit

Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive

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recessive bits). Software can monitor this countdown by reading the Tx Error Counter.

When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and

sets EI in CANxSR if EIE in IER is 1.

The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the

Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is

1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software

clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive

recessive bits) is needed before operation resumes.

8.2 Sleep mode

The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no

CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set

SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN

Interrupt Enable register to enable an interrupt on any wake-up condition.

The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the

CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)

software clearing SM in the CAN Mode register. A sleeping CAN Controller that wakes up

in response to bus activity is not able to receive an initial message until after it detects

Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is

active when software sets SM, the wake-up is immediate.

Upon wake-up, software needs to do the following things:

1. Write a 1 to the relevant bit(s) in the CANSLEEPCLR register.

2. Write a 0 to the SM bit in the CAN1MOD and/or CAN2MOD register.

3. Write a 1 to the relevant bit(s) in the CANWAKEFLAGS register. Failure to perform

this step will prevent subsequent entry into Power-down mode.

If the LPC17xx is in Deep Sleep or Power-down mode, CAN activity will wake up the

device if the CAN activity interrupt is enabled. See Section 4–8 “Power control”.

8.3 Interrupts

Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”.

The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each

Receive and Transmit interrupt request from each controller is assigned its own channel in

the NVIC, and can have its own interrupt service routine. The “other status” interrupts from

all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one

NVIC channel.

8.4 Transmit priority

If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the

right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,

they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both

cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have

the same smallest value, the lowest-numbered buffer sends first.

The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it

sends each message.

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9. Centralized CAN registers

For easy and fast access, all CAN Controller Status bits from each CAN Controller Status

register are bundled together. Each defined byte of the following registers contains one

particular status bit from each of the CAN controllers, in its LS bits.

All Status registers are read-only and allow byte, half word and word access.

9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000)

Table 338. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description

Bit

0

Symbol Description

Reset Value

TS1

TS2

-

When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).

0

1

When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)

0

7:2

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

8

9

TBS1

TBS2

When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in

CAN1GSR).

1

When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in

CAN2GSR).

1

15:10 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

1

16

TCS1

When 1, all requested transmissions have been completed successfully by the CAN1

controller (same as TCS in CAN1GSR).

17:16 TCS2

31:18 -

When 1, all requested transmissions have been completed successfully by the CAN2

controller (same as TCS in CAN2GSR).

1

Reserved, the value read from a reserved bit is not defined.

NA

9.2 Central Receive Status Register (CANRxSR - 0x4004 0004)

Table 339. Central Receive Status Register (CANRxSR - address 0x4004 0004) bit description

Bit

0

Symbol Description

Reset Value

RS1

RS2

-

When 1, CAN1 is receiving a message (same as RS in CAN1GSR).

0

1

When 1, CAN2 is receiving a message (same as RS in CAN2GSR).

0

7:2

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

8

9

RB1

RB2

When 1, a received message is available in the CAN1 controller (same as RBS in

CAN1GSR).

0

When 1, a received message is available in the CAN2 controller (same as RBS in

CAN2GSR).

0

15:10 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

16

DOS1

When 1, a message was lost because the preceding message to CAN1 controller was not

read out quickly enough (same as DOS in CAN1GSR).

17:16 DOS2

31:18 -

When 1, a message was lost because the preceding message to CAN2 controller was not

read out quickly enough (same as DOS in CAN2GSR).

0

Reserved, the value read from a reserved bit is not defined.

NA

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9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008)

Table 340. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description

Bit

Symbol Description

Reset Value

0

E1

E2

-

When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the

CAN1EWL register (same as ES in CAN1GSR)

0

1

When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the

CAN2EWL register (same as ES in CAN2GSR)

0

7:2

8

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

BS1

BS2

When 1, the CAN1 controller is currently involved in bus activities (same as BS in

CAN1GSR).

9

When 1, the CAN2 controller is currently involved in bus activities (same as BS in

CAN2GSR).

0

31:10 -

Reserved, the value read from a reserved bit is not defined.

NA

10. Global acceptance filter

This block provides lookup for received Identifiers (called Acceptance Filtering in CAN

terminology) for all the CAN Controllers. It includes a 512 × 32 (2 kB) RAM in which

software maintains one to five tables of Identifiers. This RAM can contain up to 1024

Standard Identifiers or 512 Extended Identifiers, or a mixture of both types.

11. Acceptance filter modes

The Acceptance Filter can be put into different modes by setting the according AccOff,

AccBP, and eFCAN bits in the Acceptance Filter Mode Register (Section 16–14.1

“Acceptance Filter Mode Register (AFMR - 0x4003 C000)”). During each mode the

access to the Configuration Register and the ID Look-up table is handled differently.

Table 341. Acceptance filter modes and access control

Acceptance Bit

Bit

Acceptance ID Look-up Acceptanc CAN controller

filter mode AccOff AccBP filter state

table

RAM^[1]

e filter

config.

registers

message receive

interrupt

Off Mode

1

X

0

1

0

reset &

halted

r/w access

from CPU

r/w access

from CPU

no messages

accepted

Bypass

Mode

reset &

halted

r/w access

from CPU

r/w access

from CPU

all messages

accepted

Operating

Mode and

FullCAN

Mode

running

read-only

access from hardware

from CPU^[2]Acceptance acceptance filtering

filter only

[1] The whole ID Look-up Table RAM is only word accessible.

[2] During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable or

enable Messages.

A write access to all section configuration registers is only possible during the Acceptance

Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes.

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11.1 Acceptance filter Off mode

The Acceptance Filter Off Mode is typically used during initialization. During this mode an

unconditional access to all registers and to the Look-up Table RAM is possible. With the

Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in

the Receive Buffers of active CAN Controllers.

11.2 Acceptance filter Bypass mode

The Acceptance Filter Bypass Mode can be used for example to change the acceptance

filter configuration during a running system, e.g. change of identifiers in the ID-Look-up

Table memory. During this re-configuration, software acceptance filtering has to be used.

It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI).

In this mode all CAN message are accepted and stored in the Receive Buffers of active

CAN Controllers.

11.3 Acceptance filter Operating mode

The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the

Configuration Register is set and the eFCAN = 0.

11.4 FullCAN mode

The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the

Configuration Register is set and the eFCAN = 1. More details on FullCAN mode are

available in Section 16–16 “FullCAN mode”.

12. Sections of the ID look-up table RAM

Four 12-bit section configuration registers (SFF_sa, SFF_GRP_sa, EFF_sa,

EFF_GRP_sa) are used to define the boundaries of the different identifier sections in the

ID-Look-up Table Memory. The fifth 12-bit section configuration register, the End of Table

address register (ENDofTable) is used to define the end of all identifier sections. The End

of Table address is also used to assign the start address of the section where FullCAN

Message Objects, if enabled are stored.

Table 342. Section configuration register settings

ID-Look up Table Section

Register

Value

Section

status

FullCAN (Standard Frame Format) Identifier Section SFF_sa

= 0x000

> 0x000

disabled

enabled

disabled

enabled

Explicit Standard Frame Format Identifier Section

Group of Standard Frame Format Identifier Section

Explicit Extended Frame Format Identifier Section

SFF_GRP_sa = SFF_sa

> SFF_sa

EFF_sa

= SFF_GRP_sa disabled

> SFF_GRP_sa enabled

EFF_GRP_sa = EFF_sa

> EFF_sa

disabled

enabled

Group of Extended Frame Format Identifier Section ENDofTable

= EFF_GRP_sa disabled

> EFF_GRP_sa enabled

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13. ID look-up table RAM

The Whole ID Look-up Table RAM is only word accessible. A write access is only possible

during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all

Acceptance Filter Modes.

If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in

Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the

first table contains Standard identifiers for which reception is to be handled in this mode.

The next table contains individual Standard Identifiers and the third contains ranges of

Standard Identifiers, for which messages are to be received via the CAN Controllers. The

tables of FullCAN and individual Standard Identifiers must be arranged in ascending

numerical order, one per halfword, two per word. Since each CAN bus has its own

address map, each entry also contains the number of the CAN Controller (001-010) to

which it applies.

16

0

31

15

26

10

29

13

DIS

ABLE USED

NOT

CONTROLLER #

IDENTIFIER

Fig 57. Entry in FullCAN and individual standard identifier tables

The table of Standard Identifier Ranges contains paired upper and lower (inclusive)

bounds, one pair per word. These must also be arranged in ascending numerical order.

31

29

26

16

10

0

CONTROLLER

LOWER IDENTIFIER

BOUND

CONTROLLER

#

UPPER IDENTIFIER

BOUND

#

Fig 58. Entry in standard identifier range table

The disable bits in Standard entries provide a means to turn response, to particular CAN

Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter

function is enabled, only the disable bits in Acceptance Filter RAM can be changed by

software. Response to a range of Standard addresses can be enabled by writing 32 zero

bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in

RAM. Only the disable bits are actually changed. Disabled entries must maintain the

ascending sequence of Identifiers.

If Extended (29-bit) Identifiers are used in the application, at least one of the other two

tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers

and one for ranges of Extended Identifiers. The table of individual Extended Identifiers

must be arranged in ascending numerical order.

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31

29 28

0

CONTROLLER #

IDENTIFIER

Fig 59. Entry in either extended identifier table

The table of ranges of Extended Identifiers must contain an even number of entries, of the

same form as in the individual Extended Identifier table. Like the Individual Extended

table, the Extended Range must be arranged in ascending numerical order. The first and

second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of

Extended addresses, such that any received address that falls in the inclusive range is

received (accepted). Software must maintain the table to consist of such word pairs.

There is no facility to receive messages to Extended identifiers using the FullCAN

method.

Five address registers point to the boundaries between the tables in Acceptance Filter

RAM: FullCAN Standard addresses, Standard Individual addresses, Standard address

ranges, Extended Individual addresses, and Extended address ranges. These tables

must be consecutive in memory. The start of each of the latter four tables is implicitly the

end of the preceding table. The end of the Extended range table is given in an End of

Tables register. If the start address of a table equals the start of the next table or the End

Of Tables register, that table is empty.

When the Receive side of a CAN controller has received a complete Identifier, it signals

the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads

the Controller number, the size of the Identifier, and the Identifier itself from the Controller.

It then proceeds to search its RAM to determine whether the message should be received

or ignored.

If FullCAN mode is enabled and the CAN controller signals that the current message

contains a Standard identifier, the Acceptance Filter first searches the table of identifiers

for which reception is to be done in FullCAN mode. Otherwise, or if the AF doesn’t find a

match in the FullCAN table, it searches its individual Identifier table for the size of Identifier

signalled by the CAN controller. If it finds an equal match, the AF signals the CAN

controller to retain the message, and provides it with an ID Index value to store in its

Receive Frame Status register.

If the Acceptance Filter does not find a match in the appropriate individual Identifier table,

it then searches the Identifier Range table for the size of Identifier signalled by the CAN

controller. If the AF finds a match to a range in the table, it similarly signals the CAN

controller to retain the message, and provides it with an ID Index value to store in its

Receive Frame Status register. If the Acceptance Filter does not find a match in either the

individual or Range table for the size of Identifier received, it signals the CAN controller to

discard/ignore the received message.

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14. Acceptance filter registers

14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000)

The AccBP and AccOff bits of the acceptance filter mode register are used for putting the

acceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register can

be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages.

Table 343. Acceptance Filter Mode Register (AFMR - address 0x4003 C000) bit description

Bit

Symbol Value Description

Reset Value

0

AccOff^[2]

1

if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN

buses are ignored.

1

2

AccBP^[1]

1

All Rx messages are accepted on enabled CAN controllers. Software must set this

bit before modifying the contents of any of the registers described below, and

before modifying the contents of Lookup Table RAM in any way other than setting

or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff

are 0, the Acceptance filter operates to screen received CAN Identifiers.

0

eFCAN^[3]

0

1

Software must read all messages for all enabled IDs on all enabled CAN buses,

from the receiving CAN controllers.

0

The Acceptance Filter itself will take care of receiving and storing messages for

selected Standard ID values on selected CAN buses. See Section 16–16 “FullCAN

mode” on page 380.

31:3

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

[1] Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register,

the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state

machine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, and

acceptance filtering can be done by software.

[2] Acceptance Filter Off mode (AccOff): After power-up or hardware reset, the Acceptance filter will be in Off

mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of

the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or by

software, will force the acceptance filter into Off mode.

[3] FullCAN Mode Enhancements: A FullCAN mode for received CAN messages can be enabled by setting the

eFCAN bit in the acceptance filter mode register.

14.2 Section configuration registers

The 10-bit section configuration registers are used for the ID look-up table RAM to

indicate the boundaries of the different sections for explicit and group of CAN identifiers

for 11-bit CAN and 29-bit CAN identifiers, respectively. The 10-bit wide section

configuration registers allow the use of a 512x32 (2 kB) look-up table RAM. The whole ID

Look-up Table RAM is only word accessible. All five section configuration registers contain

APB addresses for the acceptance filter RAM and do not include the APB base address.

A write access to all section configuration registers is only possible during the Acceptance

filter off and Bypass modes. Read access is allowed in all acceptance filter modes.

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14.3 Standard Frame Individual Start Address register (SFF_sa -

0x4003 C004)

Table 344. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

10:2 SFF_sa^[1]The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the

table is empty, write the same value in this register and the SFF_GRP_sa register

described below. For compatibility with possible future devices, write zeroes in bits 31:11

and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size

of the table of Standard IDs which the Acceptance Filter will search and (if found)

automatically store received messages in Acceptance Filter RAM.

0

31:11 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

[1] Write access to the look-up table section configuration registers are possible only during the Acceptance

filter bypass mode or the Acceptance filter off mode.

14.4 Standard Frame Group Start Address register (SFF_GRP_sa -

0x4003 C008)

Table 345. Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

11:2 SFF_GRP_sa^[1]The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If

the table is empty, write the same value in this register and the EFF_sa register

described below. The largest value that should be written to this register is 0x800,

when only the Standard Individual table is used, and the last word (address 0x7FC)

in AF Lookup Table RAM is used. For compatibility with possible future devices,

please write zeroes in bits 31:12 and 1:0 of this register.

0

31:12 -

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

[1] Write access to the look-up table section configuration registers are possible only during the Acceptance

filter bypass mode or the Acceptance filter off mode.

14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C)

Table 346. Extended Frame Start Address register (EFF_sa - address 0x4003 C00C) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

10:2 EFF_sa^[1]The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the

table is empty, write the same value in this register and the EFF_GRP_sa register

described below. The largest value that should be written to this register is 0x800, when

both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table

RAM is used. For compatibility with possible future devices, please write zeroes in bits

31:11 and 1:0 of this register.

0

31:11 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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[1] Write access to the look-up table section configuration registers are possible only during the Acceptance

filter bypass mode or the Acceptance filter off mode.

14.6 Extended Frame Group Start Address register (EFF_GRP_sa -

0x4003 C010)

Table 347. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

11:2 Eff_GRP_sa^[1]The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If

the table is empty, write the same value in this register and the ENDofTable register

described below. The largest value that should be written to this register is 0x800,

when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM

is used. For compatibility with possible future devices, please write zeroes in bits

31:12 and 1:0 of this register.

0

31:12 -

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

[1] Write access to the look-up table section configuration registers are possible only during the Acceptance

filter bypass mode or the Acceptance filter off mode.

14.7 End of AF Tables register (ENDofTable - 0x4003 C014)

Table 348. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

11:2 EndofTable^[1]The address above the last active address in the last active AF table. For compatibility

with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.

0

If the eFCAN bit in the AFMR is 0, the largest value that should be written to this

register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM

to be used.

If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance

Filter RAM, into which the Acceptance Filter will automatically receive messages for

selected IDs on selected CAN buses. In this case, the maximum value that should be

written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes

of message storage between this address and the end of Acceptance Filter RAM, for

each Standard ID that is specified between the start of Acceptance Filter RAM, and the

next active AF table.

31:12 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

[1] Write access to the look-up table section configuration registers are possible only during the Acceptance

filter bypass mode or the Acceptance filter off mode.

14.8 Status registers

The look-up table error status registers, the error addresses, and the flag register provide

information if a programming error in the look-up table RAM during the ID screening was

encountered. The look-up table error address and flag register have only read access. If

an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides the

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information under which address during an ID screening an error in the look-up table was

encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table

interrupt.

14.9 LUT Error Address register (LUTerrAd - 0x4003 C018)

Table 349. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description

Bit

Symbol

Description

Reset Value

1:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

10:2 LUTerrAd It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup

Table RAM, at which the Acceptance Filter encountered an error in the content of the

tables.

0

31:11 -

Reserved, the value read from a reserved bit is not defined.

NA

14.10 LUT Error register (LUTerr - 0x4003 C01C)

Table 350. LUT Error register (LUTerr - address 0x4003 C01C) bit description

Bit

Symbol Description

LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of

Reset Value

0

the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This

condition is ORed with the “other CAN” interrupts from the CAN controllers, to produce the

request that is connected to the NVIC.

31:1

-

Reserved, the value read from a reserved bit is not defined.

NA

14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020)

A write access to the Global FullCAN Interrupt Enable register is only possible when the

Acceptance Filter is in the off mode.

Table 351. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description

Bit

0

Symbol Description

Reset Value

FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.

0

31:1

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and

FCANIC1 - 0x4003 C028)

For detailed description on these two registers, see Section 16–16.2 “FullCAN interrupts”.

Table 352. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description

Bit

0

Symbol

Description

Reset Value

IntPnd0

FullCan Interrupt Pending bit 0.

FullCan Interrupt Pending bit x.

FullCan Interrupt Pending bit 31.

0

...

IntPndx (0<x<31)

IntPnd31

31

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Table 353. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description

Bit

0

Symbol

Description

Reset Value

IntPnd32

FullCan Interrupt Pending bit 32.

FullCan Interrupt Pending bit x.

FullCan Interrupt Pending bit 63.

0

...

IntPndx (32<x<63)

IntPnd63

31

15. Configuration and search algorithm

The CAN Identifier Look-up Table Memory can contain explicit identifiers and groups of

CAN identifiers for Standard and Extended CAN Frame Formats. They are organized as a

sorted list or table with an increasing order of the Source CAN Channel (SCC) together

with CAN Identifier in each section.

SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1

matches CAN2.

Every CAN identifier is linked to an ID Index number. In case of a CAN Identifier match,

the matching ID Index is stored in the Identifier Index of the Frame Status Register

(CANRFS) of the according CAN Controller.

15.1 Acceptance filter search algorithm

The identifier screening process of the acceptance filter starts in the following order:

1. FullCAN (Standard Frame Format) Identifier Section

2. Explicit Standard Frame Format Identifier Section

3. Group of Standard Frame Format Identifier Section

4. Explicit Extended Frame Format Identifier Section

5. Group of Extended Frame Format Identifier Section

Note: Only activated sections will take part in the screening process.

In cases where equal message identifiers of same frame format are defined in more than

one section, the first match will end the screening process for this identifier.

For example, if the same Source CAN Channel in conjunction with the identifier is defined

in the FullCAN, the Explicit Standard Frame Format and the Group of Standard Frame

Format Identifier Sections, the screening will already be finished with the match in the

FullCAN section.

In the example of Figure 16–60, Identifiers with their Source CAN Channel have been

defined in the FullCAN, Explicit and Group of Standard Frame Format Identifier Sections.

This example corresponds part with 6 CAN controllers.

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Message

disable bit

0

Index 0, 1

Index 2, 3

Index 4, 5

Index 6, 7

SCC = 1

SCC = 2

ID = 0x5A

SCC = 1

...

FullCAN

Explicit

Standard

Frame

Format

Identifier

Section

0

...

SCC = 3

SCC = 5

SCC = 6

0

SCC = 4

SCC = 6

Explicit

Standard

Frame

Format

Identifier

Section

0

Index 8, 9

Index 10, 11

Index 12, 13

SCC = 1

SCC = 2

SCC = 4

ID = 0x5A

SCC = 1

SCC = 3

SCC = 5

...

Group of

Standard

Frame

Format

Identifier

Section

0

Index 14

Index 15

SCC = 1

SCC = 2

ID = 0x5A

...

SCC = 1

SCC = 2

ID = 0x5FA

...

Fig 60. ID Look-up table example explaining the search algorithm

The identifier 0x5A of the CAN Controller 1 with the Source CAN Channel SCC = 1, is

defined in all three sections. With this configuration incoming CAN messages on CAN

Controller 1 with a 0x5A identifier will find a match in the FullCAN section.

It is possible to disable the ‘0x5A identifier’ in the FullCAN section. With that, the

screening process would be finished with the match in the Explicit Identifier Section.

The first group in the Group Identifier Section has been defined in that way, that incoming

CAN messages with identifiers of 0x5A up to 0x5F are accepted on CAN Controller 1 with

the Source CAN Channel SCC = 1. As stated above, the identifier 0x5A would find a

match already in the FullCAN or in the Explicit Identifier section if enabled. The rest of the

defined identifiers of this group (0x5B to 0x5F) will find a match in this Group Identifier

Section.

This way the user can switch dynamically between different filter modes for same

identifiers.

16. FullCAN mode

The FullCAN mode is based on capabilities provided by the CAN Gateway module used in

the LPC2000 family of products. This block uses the Acceptance Filter to provide filtering

for both CAN channels.

The concept of the CAN Gateway block is mainly based on a BasicCAN functionality. This

concept fits perfectly in systems where a gateway is used to transfer messages or

message data between different CAN channels. A BasicCAN device is generating a

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receive interrupt whenever a CAN message is accepted and received. Software has to

move the received message out of the receive buffer from the according CAN controller

into the user RAM.

To cover dashboard like applications where the controller typically receives data from

several CAN channels for further processing, the CAN Gateway block was extended by a

so-called FullCAN receive function. This additional feature uses an internal message

handler to move received FullCAN messages from the receive buffer of the according

CAN controller into the FullCAN message object data space of Look-up Table RAM.

When FullCAN mode is enabled, the Acceptance Filter itself takes care of receiving and

storing messages for selected Standard ID values on selected CAN buses, in the style of

“FullCAN” controllers.

In order to set this bit and use this mode, two other conditions must be met with respect to

the contents of Acceptance Filter RAM and the pointers into it:

• The Standard Frame Individual Start Address Register (SFF_sa) must be greater than

or equal to the number of IDs for which automatic receive storage is to be done, times

two. SFF_sa must be rounded up to a multiple of 4 if necessary.

• The EndOfTable register must be less than or equal to 0x800 minus 6 times the

SFF_sa value, to allow 12 bytes of message storage for each ID for which automatic

receive storage will be done.

When these conditions are met and eFCAN is set:

• The area between the start of Acceptance Filter RAM and the SFF_sa address, is

used for a table of individual Standard IDs and CAN Controller/bus identification,

sorted in ascending order and in the same format as in the Individual Standard ID

table (see Figure 16–57 “Entry in FullCAN and individual standard identifier tables” on

page 373). Entries can be marked as “disabled” as in the other Standard tables. If

there are an odd number of “FullCAN” ID’s, at least one entry in this table must be so

marked.

• The first (SFF_sa)/2 IDindex values are assigned to these automatically-stored ID’s.

That is, IDindex values stored in the Rx Frame Status Register, for IDs not handled in

this way, are increased by (SFF_sa)/2 compared to the values they would have when

eFCAN is 0.

• When a Standard ID is received, the Acceptance Filter searches this table before the

Standard Individual and Group tables.

• When a message is received for a controller and ID in this table, the Acceptance filter

reads the received message out of the CAN controller and stores it in Acceptance

Filter RAM, starting at (EndOfTable) + its IDindex*12.

• The format of such messages is shown in Table 16–354.

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16.1 FullCAN message layout

Table 354. Format of automatically stored Rx messages

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Address

0

F

R

T

0000

SEM 0000

[1:0]

DLC

00000

ID.28 ... ID.18

R

+4

+8

Rx Data 4

Rx Data 8

Rx Data 3

Rx Data 7

Rx Data 2

Rx Data 6

Rx Data 1

Rx Data 5

The FF, RTR, and DLC fields are as described in Table 16–326.

Since the FullCAN message object section of the Look-up table RAM can be accessed

both by the Acceptance Filter and the CPU, there is a method for insuring that no CPU

reads from FullCAN message object occurs while the Acceptance Filter hardware is

writing to that object.

For this purpose the Acceptance Filter uses a 3-state semaphore, encoded with the two

semaphore bits SEM1 and SEM0 (see Table 16–354 “Format of automatically stored Rx

messages”) for each message object. This mechanism provides the CPU with information

about the current state of the Acceptance Filter activity in the FullCAN message object

section.

The semaphore operates in the following manner:

Table 355. FullCAN semaphore operation

SEM1

SEM0

activity

0

1

0

1

0

Acceptance Filter is updating the content

Acceptance Filter has finished updating the content

CPU is in process of reading from the Acceptance Filter

Prior to writing the first data byte into a message object, the Acceptance Filter will write

the FrameInfo byte into the according buffer location with SEM[1:0] = 01.

After having written the last data byte into the message object, the Acceptance Filter will

update the semaphore bits by setting SEM[1:0] = 11.

Before reading a message object, the CPU should read SEM[1:0] to determine the current

state of the Acceptance Filter activity therein. If SEM[1:0] = 01, then the Acceptance Filter

is currently active in this message object. If SEM[1:0] = 11, then the message object is

available to be read.

Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00.

When the CPU is finished reading, it can check SEM[1:0] again. At the time of this final

check, if SEM[1:0] = 01 or 11, then the Acceptance Filter has updated the message object

during the time when the CPU reads were taking place, and the CPU should discard the

data. If, on the other hand, SEM[1:0] = 00 as expected, then valid data has been

successfully read by the CPU.

Figure 16–61 shows how software should use the SEM field to ensure that all three words

read from the message are all from the same received message.

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START

read 1st word

SEM == 01?

this message has not been

received since last check

SEM == 11?

clear SEM, write back 1st word

read 2nd and 3rd words

read 1st word

SEM == 00?

most recently read 1st, 2nd, and

3rd words are from the same

message

Fig 61. Semaphore procedure for reading an auto-stored message

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16.2 FullCAN interrupts

The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a

maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM

is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to

participate in the interrupt scheme. It is still possible to define more than 64 FullCAN

objects. The only difference is, that the remaining FullCAN objects will not provide a

FullCAN interrupt.

The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)

FullCAN receive interrupts. As soon as a FullCAN message is received, the according

interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global

FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the

Vectored Interrupt Controller.

Application Software has to solve the following:

1. Index/Object number calculation based on the bit position in the FCANIC Interrupt

Register for more than one pending interrupt.

2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.

The software that covers the interrupt priority handling has to assign a receive interrupt

priority to every FullCAN object. If more than one interrupt is pending, then the software

has to decide, which received FullCAN object has to be served next.

To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so

that it is possible to enable or disable FullCAN interrupts for each object individually. The

new Message Lost flag (MsgLstx) is introduced to indicate whether more than one

FullCAN message has been received since last time this message object was read by the

CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table

RAM.

16.2.1 FullCAN message interrupt enable bit

In Figure 16–62 8 FullCAN Identifiers with their Source CAN Channel are defined in the

FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used

to enable for each FullCAN message an Interrupt.

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Message

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3

2

0

1

0

1

0

9

8

7

6

5 4

3

2

1

9

8

7

6

5

4

3

2

0

1

9

8

7

6

5

4

3

2

1

0

Index 0, 1

SCC

11-bit CAN ID

SCC

11-bit CAN ID

FullCAN

Explicit

0

Index 2, 3

Index 4, 5

SCC

11-bit CAN ID

SCC

11-bit CAN ID

Standard

Frame

Format

Identifier

0

Index 6, 7

SCC

11-bit CAN ID

SCC

11-bit CAN ID

Section

New:

FullCAN

Message

Interrupt

FullCAN

Message

Interrupt

enable bit

Fig 62. FullCAN section example of the ID look-up table

16.2.2 Message lost bit and CAN channel number

Figure 16–63 is the detailed layout structure of one FullCAN message stored in the

FullCAN message object section of the Look-up Table.

New:

FullCAN

Message

lost bit

New:

CAN

Source

Channel

31

24 23

16 15

10

9

8

7

0

APB

Base +

S

E

M

0

R

E

M

1

F

un-

ID.2

8

ID.1

8

T

R

unused

............................

Msg_ObjAddr + 0

RX DLC

RX Data 3

RX Data 7

SCC

used

Msg_ObjAddr + 4

Msg_ObjAddr + 8

RX Data 4

RX Data 8

RX Data 2

RX Data 6

RX Data 1

RX Data 5

Fig 63. FullCAN message object layout

The new message lost bit (MsgLst) is introduced to indicate whether more than one

FullCAN message has been received since last time this message object was read. For

more information the CAN Source Channel (SCC) of the received FullCAN message is

added to Message Object.

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16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)

The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN

message and if the interrupt of the according FullCAN Object is enabled (enable bit

FCANIntxEn) is set).

During the last write access from the data storage of a FullCAN message object the

interrupt pending bit of a FullCAN object (IntPndx) gets asserted.

16.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)

Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of

a message object are cleared by Software (ARM CPU).

16.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)

The Message Lost bit of a FullCAN message object gets asserted in case of an accepted

FullCAN message and when the FullCAN Interrupt of the same object is asserted already.

During the first write access from the data storage of a FullCAN message object the

Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit

is set already.

16.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to

0)

The Message Lost bit of a FullCAN message object gets cleared when the FullCAN

Interrupt of the same object is not asserted.

During the first write access from the data storage of a FullCAN message object the

Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit

is not set.

16.3 Set and clear mechanism of the FullCAN interrupt

Special precaution is needed for the built-in set and clear mechanism of the FullCAN

Interrupts. The following text illustrates how the already existing Semaphore Bits (see

Section 16–16.1 “FullCAN message layout” for more details) and how the new introduced

features (IntPndx, MsgLstx) will behave.

16.3.1 Scenario 1: Normal case, no message lost

Figure 16–64 below shows a typical “normal” scenario in which an accepted FullCAN

message is stored in the FullCAN Message Object Section. After storage the message is

read out by Software (ARM CPU).

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semaphore

bits

01

11

00

IntPndx

Write

ID, SEM

write write write

read clear

SEM SEM

read read read

look-up

table

D1

D2 SEM

D1

D2 SEM

access

MsgLostx

ARM

processor

access

message

handler

access

Fig 64. Normal case, no messages lost

16.3.2 Scenario 2: Message lost

In this scenario a first FullCAN Message is stored and read out by Software (1^stObject

write and read). In a second course a second message is stored (2^ndObject write) but not

read out before a third message gets stored (3^rdObject write). Since the FullCAN Interrupt

of that Object (IntPndx) is already asserted, the Message Lost Signal gets asserted.

semaphore

bits

01

11

00

01

11

IntPndx

look-up

table

access

write

ID,

SEM

write

ID,

SEM

write

ID,

write write write

read clear

SEM SEM

read read read

write write write

D1

D2 SEM

D1

D2 SEM

D1

D2 SEM

D1

D2 SEM

SEM

1st Object

write

2nd Object

write

3rd Object

write

1st Object

read

MsgLostx

message

handler

access

ARM

processor

access

Fig 65. Message lost

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16.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits

This scenario is a special case in which the lost message is indicated by the existing

semaphore bits. The scenario is entered, if during a Software read of a message object

another new message gets stored by the message handler. In this case, the FullCAN

Interrupt bit gets set for a second time with the 2^ndObject write.

01

11

00

01

11

00

semaphore

bits

IntPndx

look-up

table

access

write

ID,

SEM

write

ID,

SEM

read clear

SEM SEM

read read read

D1 D2 SEM

read read read

write write write

clear

SEM

write write write

D1

D2 SEM

D1

D2 SEM

D1

D2 SEM

1st Object

write

2nd Object

write

2nd Object

read

1st Object read

Interrupt Service

Routine

MsgLostx

message

handler

access

ARM

processor

access

Fig 66. Message gets overwritten

16.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and

Message Lost

This scenario is a sub-case to Scenario 3 in which the lost message is indicated by the

existing semaphore bits and by Message Lost.

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01

11

00

01

11

00

semaphore

bits

IntPndx

write

ID,

write

ID,

clear

SEM

write write write

D1 D2 SEM

read clear

SEM SEM

write write write

read read read

D1 D2 SEM

read read read

D1 D2 SEM

look-up

table

D1

D2 SEM

SEM

access

1st Object

write

2nd Object

write

2nd Object

read

1st Object read

Interrupt Service

Routine

MsgLostx

message

handler

access

ARM

processor

access

Fig 67. Message overwritten indicated by semaphore bits and message lost

16.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost

This scenario is a sub-case to Scenario 3 in which the lost message is indicated by

Message Lost.

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01

11

01

11

00

01

11

semaphore

bits

IntPndx

write

ID,

SEM

write

ID,

SEM

write

ID,

SEM

look-up

table

access

write write write read

write write write

clear read read read

write write write

D1

D2 SEM SEM

D1

D2 SEM

SEM

D1 D2 SEM

D1

D2 SEM

1st Object

write

2nd Object

write

3rd Object

write

1st Object

read

Interrupt Service

Routine

MsgLostx

message

handler

access

ARM

processor

access

Fig 68. Message overwritten indicated by message lost

16.3.6 Scenario 4: Clearing Message Lost bit

This scenario is a special case in which the lost message bit of an object gets set during

an overwrite of a none read message object (2^ndObject write). The subsequent read out

of that object by Software (1^stObject read) clears the pending Interrupt. The 3^rdObject

write clears the Message Lost bit. Every “write ID, SEM” clears Message Lost bit if no

pending Interrupt of that object is set.

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01

11

01

11

00

11

semaphore

bits

IntPndx

write

ID,

SEM

write

ID,

SEM

write

ID,

SEM

write write write

D1 D2 SEM

write write write

read clear

SEM SEM

read read

write write write

D1 D2 SEM

read

D1

look-up

table

D1

D2 SEM

access

1st Object

write

2nd Object

write

3rd Object

write

1st Object

read

MsgLostx

message

handler

access

ARM

processor

access

Fig 69. Clearing message lost

17. Examples of acceptance filter tables and ID index values

17.1 Example 1: only one section is used

SFF_sa

SFF_GRP_sa

EFF_sa

<

ENDofTable

OR

EFF_GRP_sa

The start address of a section is lower than the end address of all programmed CAN

identifiers.

17.2 Example 2: all sections are used

SFF_sa

SFF_GRP_sa

EFF_sa

<

SFF_GRP_sa

EFF_sa

EFF_GRP_sa

ENDofTable

AND

EFF_GRP_sa

In cases of a section not being used, the start address has to be set onto the value of the

next section start address.

17.3 Example 3: more than one but not all sections are used

If the SFF group is not used, the start address of the SFF Group Section (SFF_GRP_sa

register) has to be set to the same value of the next section start address, in this case the

start address of the Explicit SFF Section (SFF_sa register).

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In cases where explicit identifiers as well as groups of the identifiers are programmed, a

CAN identifier search has to start in the explicit identifier section first. If no match is found,

it continues the search in the group of identifier section. By this order it can be guaranteed

that in case where an explicit identifier match is found, the succeeding software can

directly proceed on this certain message whereas in case of a group of identifier match

the succeeding software needs more steps to identify the message.

17.4 Configuration example 4

Suppose that the five Acceptance Filter address registers contain the values shown in the

third column below. In this case each table contains the decimal number of words and

entries shown in the next two columns, and the ID Index field of the CANRFS register can

return the decimal values shown in the column ID Indexes for CAN messages whose

Identifiers match the entries in that table.

Table 356. Example of Acceptance Filter Tables and ID index Values

Table

Register

Value

0x040

0x060

0x070

0x100

0x110

# Words

8₁₀

# Entire

16₁₀

ID Indexes

0-15₁₀

Standard Individual

Standard Group

Extended Individual

Extended Group

SFF_sa

SFF_GRP_sa

EFF_sa

4₁₀

16-19₁₀

20-55₁₀

56-57₁₀

8₁₀

16₁₀

EFF_GRP_sa

ENDofTable

8₁₀

16₁₀

17.5 Configuration example 5

Figure 16–70 below is a more detailed and graphic example of the address registers,

table layout, and ID Index values. It shows:

• A Standard Individual table starting at the start of Acceptance Filter RAM and

containing 26 Identifiers, followed by:

• A Standard Group table containing 12 ranges of Identifiers, followed by:

• An Extended Individual table containing 3 Identifiers, followed by:

• An Extended Group table containing 2 ranges of Identifiers.

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000 d := 000 h := 0 0000 0000 b

SFF_sa

look-up table RAM

column_lower column_upper

ID index #

APB base +

address

0

1

2

0

2

1

3

00d = 00h

04d = 04h

3

22

23

24

25

22

24

23

25

44d = 2Ch

48d = 30h

2 6

26 d

52d = 34h

SFF_GRP_sa 52 d := 034 h := 0 0011 0100 b

lower_boundary 3 4 upper_boundary

lower_boundary 35 upper_boundary

84d = 54h

88d = 58h

34 d

35 d

92d = 5Ch

lower_boundary 36 upper_boundary 36 d

EFF_sa

100 d := 064 h := 0 0110 0100 b

38

39

38 d

39 d

100d = 64h

104d = 68h

EFF_GRP_sa

112 d := 070 h := 0 0111 0000 b

41 d

42 d

lower_boundary 41

112d = 70h

116d = 74h

upper_boundary

lower_boundary 42

upper_boundary

120d = 78h

124d = 7Ch

ENDofTable 128 d := 080 h := 0 1000 0000 b

Fig 70. Detailed example of acceptance filter tables and ID index values

17.6 Configuration example 6

The Table below shows which sections and therefore which types of CAN identifiers are

used and activated. The ID-Look-up Table configuration of this example is shown in

Figure 16–71.

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Table 357. Used ID-Look-up Table sections

ID-Look-up Table Section

FullCAN

Status

not activated

activated

Explicit Standard Frame Format

Group of Standard Frame Format

Explicit Extended Frame Format

Group of Extended Frame Format

Explicit standard frame format identifier section (11-bit CAN ID):

The start address of the Explicit Standard Frame Format section is defined in the SFF_sa

register with the value of 0x00. The end of this section is defined in the SFF_GRP_sa

register. In the Explicit Standard Frame Format section of the ID Look-up Table two CAN

Identifiers with their Source CAN Channels (SCC) share one 32-bit word. Not used or

disabled CAN Identifiers can be marked by setting the message disable bit.

Group of standard frame format identifier section (11-bit CAN ID):

The start address of the Group of Standard Frame Format section is defined with the

SFF_GRP_sa register with the value of 0x10. The end of this section is defined with the

EFF_sa register. In the Group of Standard Frame Format section two CAN Identifiers with

the same Source CAN Channel (SCC) share one 32-bit word and represent a range of

CAN Identifiers to be accepted. Bit 31 down to 16 represents the lower boundary and bit

15 down to 0 represents the upper boundary of the range of CAN Identifiers. All Identifiers

within this range (including the boundary identifiers) will be accepted. A whole group can

be disabled and not used by the acceptance filter by setting the message disable bit in the

upper and lower boundary identifier. To provide memory space for four Groups of

Standard Frame Format identifiers, the EFF_sa register value is set to 0x20. The identifier

group with the Index 9 of this section is not used and therefore disabled.

Explicit extended frame format identifier section (29-bit CAN ID, Figure 16–71)

The start address of the Explicit Extended Frame Format section is defined with the

EFF_sa register with the value of 0x20. The end of this section is defined with the

EFF_GRP_sa register. In the explicit Extended Frame Format section only one CAN

Identifier with its Source CAN Channel (SCC) is programmed per address line. To provide

memory space for four Explicit Extended Frame Format identifiers, the EFF_GRP_sa

register value is set to 0x30.

Group of extended frame format identifier section (29-bit CAN ID, Figure 16–71)

The start address of the Group of Extended Frame Format is defined with the

EFF_GRP_sa register with the value of 0x30. The end of this section is defined with the

End of Table address register (ENDofTable). In the Group of Extended Frame Format

section the boundaries are programmed with a pair of address lines; the first is the lower

boundary, the second the upper boundary. To provide memory space for two Groups of

Extended Frame Format Identifiers, the ENDofTable register value is set to 0x40.

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Message

disable bit

Index

MSB

ID28

MSB

ID28

LSB

ID18

SFF_sa

= 0x00

LSB

ID18

0

1

0

1

SCC

0

SCC

12

1

Explicit

Standard

Frame

...Format

Identifier

Section

MSB

ID28

MSB

ID28

LSB

ID18

LSB

ID18

2

3

MSB

ID28

MSB

ID28

LSB

ID18

LSB

ID18

4

5

Disabled, 7

8

MSB

ID28

LSB

ID18

LSB

ID18

MSB

ID28

6

8

MSB

ID28

LSB

ID18

MSB

ID28

LSB

ID18

SFF_GRP_sa

0

1

Group 8

= 0x10

Group of

Standard

Frame

Format

...

Identifier

MSB

ID28

LSB

ID18

MSB

ID28

LSB

ID18

Disabled

Group 9

Disabled, 9

MSB

ID28

LSB

ID18

MSB

ID28

LSB

ID18

1

0

1

0

Group 10

SCC

10

11

10

11

MSB

ID28

LSB

ID18

MSB

ID28

LSB

Section

Group 11

ID18

MSB

ID28

LSB

ID0

EFF_sa

= 0x20

Explicit

Extended

Frame

Format

Identifier

Section

LSB

ID0

MSB

ID28

SCC

13

LSB

ID0

MSB

ID28

14

LSB

ID0

MSB

ID28

15

EFF_GRP_sa

= 0x30

LSB

ID0

MSB

ID28

16

Group of

Extended

Frame

Format

Identifier

Section

Group 16

Group 17

LSB

ID0

MSB

ID28

16

MSB

ID28

LSB

ID0

17

LSB

ID0

MSB

ID28

17

ENDofTable

= 0x40

Fig 71. ID Look-up table configuration example (no FullCAN)

17.7 Configuration example 7

The Table below shows which sections and therefore which types of CAN identifiers are

used and activated. The ID-Look-up Table configuration of this example is shown in

Figure 16–72.

This example uses a typical configuration in which FullCAN as well as Explicit Standard

Frame Format messages are defined. As described in Section 16–15.1 “Acceptance filter

search algorithm”, acceptance filtering takes place in a certain order. With the enabled

FullCAN section, the identifier screening process of the acceptance filter starts always in

the FullCAN section first, before it continues with the rest of enabled sections.e disabled.

Table 358. Used ID-Look-up Table sections

ID-Look-up Table Section

FullCAN

Status

activated and enabled

activated

Explicit Standard Frame Format

Group of Standard Frame Format

Explicit Extended Frame Format

Group of Extended Frame Format

not activated

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FullCAN explicit standard frame format identifier section (11-bit CAN ID)

The start address of the FullCAN Explicit Standard Frame Format Identifier section is

(automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the

FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.

In this section two CAN Identifiers with their Source CAN Channels (SCC) share one

32-bit word. Not used or disabled CAN Identifiers can be marked by setting the message

disable bit. The FullCAN Object data for each defined identifier can be found in the

FullCAN Message Object section. In case of an identifier match during the acceptance

filter process, the received FullCAN message object data is moved from the Receive

Buffer of the appropriate CAN Controller into the FullCAN Message Object section. To

provide memory space for eight FullCAN, Explicit Standard Frame Format identifiers, the

SFF_sa register value is set to 0x10. The identifier with the Index 1 of this section is not

used and therefore disabled.

Explicit standard frame format identifier section (11-bit CAN ID)

The start address of the Explicit Standard Frame Format section is defined in the SFF_sa

register with the value of 0x10. The end of this section is defined in the End of Table

address register (ENDofTable). In the explicit Standard Frame Format section of the ID

Look-up Table two CAN Identifiers with their Source CAN Channel (SCC) share one 32-bit

word. Not used or disabled CAN Identifiers can be marked by setting the message disable

bit. To provide memory space for eight Explicit Standard Frame Format identifiers, the

ENDofTable register value is set to 0x20.

FullCAN message object data section

The start address of the FullCAN Message Object Data section is defined with the

ENDofTable register. The number of enabled FullCAN identifiers is limited to the available

memory space in the FullCAN Message Object Data section. Each defined FullCAN

Message needs three address lines for the Message Data in the FullCAN Message Object

Data section. The FullCAN Message Object section is organized in that way, that each

Index number of the FullCAN Identifier section corresponds to a Message Object Number

in the FullCAN Message Object section.

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FullCAN

Interrupt

Enable bit

FullCAN

Interrupt

Enable bit

Message

Disable bit

Message

Disable bit

Index

MSB

ID28

LSB

MSB

ID28

LSB

0

1

0

1

0

1

0

FullCAN

Explicit

0

2

Disabled, 1

SCC

ID18

MSB

ID28

LSB

ID18

LSB

ID18

MSB

ID28

Standard

Frame

...Format

Identifier

Section

3

5

MSB

ID28

LSB

ID18

MSB

ID28

MSB

ID28

LSB

ID18

4

MSB

ID28

LSB

ID18

LSB

ID18

6

7

SFF_sa

= 0x10

MSB

ID28

MSB

ID28

LSB

ID18

LSB

ID18

LSB

ID18

LSB

ID18

LSB

ID18

LSB

ID18

8

9

SCC

Explicit

Standard

Frame

...Format

Identifier

Section

MSB

ID28

MSB

ID28

10

12

14

11

13

15

MSB

ID28

MSB

ID28

SCC

MSB

ID28

LSB

ID18

MSB

ID28

LSB

ID18

ENDofTable =

SFF_GRP_sa =

EFF_sa =

FF RTR SEM DLC CAN-ID

RXDATA 4, 3, 2, 1

Message Object

Data 0

FullCAN

Message

Object

section

Section

EFF_GRP_sa =

0x20

RXDATA 8, 7, 6, 5

No Message Data, disabled.

FF RTR SEM DLC CAN-ID

RXDATA 4, 3, 2, 1

Message Object

Data 1

Message Object

Data 2

RXDATA 8, 7, 6, 5

Fig 72. ID Look-up table configuration example (FullCAN activated and enabled)

17.8 Look-up table programming guidelines

All identifier sections of the ID Look-up Table have to be programmed in such a way, that

each active section is organized as a sorted list or table with an increasing order of the

Source CAN Channel (SCC) together with CAN Identifier in each section.

SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1

matches CAN2.

In cases, where a syntax error in the ID Look-up Table is encountered, the Look-up Table

address of the incorrect line is made available in the Look-up Table Error Address

Register (LUTerrAd).

The reporting process in the Look-up Table Error Address Register (LUTerrAd) is a

“run-time” process. Only those address lines with syntax error are reported, which were

passed through the acceptance filtering process.

The following general rules for programming the Look-up Table apply:

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• Each section has to be organized as a sorted list or table with an increasing order of

the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no

exception for disabled identifiers).

• The upper and lower bound in a Group of Identifiers definition has to be from the

same Source CAN Channel.

• To disable a Group of Identifiers the message disable bit has to be set for both, the

upper and lower bound.

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Chapter 17: LPC17xx SPI

Rev. 01 — 4 January 2010

User manual

1. Basic configuration

The SPI is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCSPI.

Remark: On reset, the SPI is enabled (PCSPI = 1).

2. Clock: In the PCLKSEL0 register (Table 4–40), set bit PCLK_SPI. In master mode,

the clock must be an even number greater than or equal to 8 (see Section 17–7.4).

3. Pins: The SPI pins are configured using both PINSEL0 (Table 8–78) and PINSEL1

(Table 8–79), as well as the PINMODE (Section 8–4) register. PINSEL0[31:30] is

used to configure the SPI CLK pin. PINSEL1[1:0], PINSEL1[3:2] and PINSEL1[5:4]

are used to configure the pins SSEL, MISO and MOSI, respectively.

4. Interrupts: The SPI interrupt flag is enabled using the S0SPINT[0] bit

(Section 17–7.7). The SPI interrupt flag must be enabled in the NVIC, see Table 6–50.

Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is

included as a legacy peripheral. Only one of these peripherals can be used at the any one

time.

2. Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex Communication.

• SPI master or slave.

• Maximum data bit rate of one eighth of the peripheral clock rate.

• 8 to 16 bits per transfer.

3. SPI overview

SPI is a full duplex serial interface. It can handle multiple masters and slaves being

connected to a given bus. Only a single master and a single slave can communicate on

the interface during a given data transfer. During a data transfer the master always sends

8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.

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4. Pin description

Table 359. SPI pin description

Type

Pin Description

Name

SCK

Input/

Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of

Output data across the SPI interface. The SPI is always driven by the master and

received by the slave. The clock is programmable to be active high or active

low. The SPI is only active during a data transfer. Any other time, it is either in its

inactive state, or tri-stated.

SSEL Input

Slave Select. The SPI slave select signal (SSEL) is an active low signal that

indicates which slave is currently selected to participate in a data transfer. Each

slave has its own unique slave select signal input. The SSEL must be low before

data transactions begin and normally stays low for the duration of the

transaction. If the SSEL signal goes high any time during a data transfer, the

transfer is considered to be aborted. In this event, the slave returns to idle, and

any data that was received is thrown away. There are no other indications of this

exception. This signal is not directly driven by the master. It could be driven by a

simple general purpose I/O under software control.

MISO Input/

Master In Slave Out. The SPI Master In Slave Out signal (MISO) is a

Output unidirectional signal used to transfer serial data from an SPI slave to an SPI

master. When a device is a slave, serial data is output on this pin. When a

device is a master, serial data is input on this pin. When a slave device is not

selected, the slave drives the signal high-impedance.

MOSI Input/

Master Out Slave In. The SPI Master Out Slave In signal (MOSI) is a

Output unidirectional signal used to transfer serial data from an SPI master to an SPI

slave. When a device is a master, serial data is output on this pin. When a

device is a slave, serial data is input on this pin.

5. SPI data transfers

Figure 17–73 is a timing diagram that illustrates the four different data transfer formats

that are available with the SPI port. This timing diagram illustrates a single 8-bit data

transfer. The first thing you should notice in this timing diagram is that it is divided into

three horizontal parts. The first part describes the SCK and SSEL signals. The second

part describes the MOSI and MISO signals when the Clock Phase control bit (CPHA) in

the SPI Control Register is 0. The third part describes the MOSI and MISO signals when

the CPHA variable is 1.

In the first part of the timing diagram, note two points. First, the SPI is illustrated with the

Clock Polarity control bit (CPOL) in the SPI Control Register set to both 0 and 1. The

second point to note is the activation and de-activation of the SSEL signal. When

CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not

guaranteed when CPHA = 1 (the signal can remain active).

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SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

CPHA = 0

1

2

3

4

5

6

7

8

Cycle # CPHA = 0

MOSI (CPHA = 0)

MISO (CPHA = 0)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

CPHA = 1

1

2

3

4

5

6

7

8

Cycle # CPHA = 1

MOSI (CPHA = 1)

MISO (CPHA = 1)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

Fig 73. SPI data transfer format (CPHA = 0 and CPHA = 1)

The data and clock phase relationships are summarized in Table 17–360.

Table 360. SPI Data To Clock Phase Relationship

CPOL and CPHA

settings

When the first data bit is

driven

When all other data When data is

bits are driven

sampled

CPOL = 0, CPHA = 0 Prior to first SCK rising edge SCK falling edge

CPOL = 0, CPHA = 1 First SCK rising edge SCK rising edge

CPOL = 1, CPHA = 0 Prior to first SCK falling edge SCK rising edge

CPOL = 1, CPHA = 1 First SCK falling edge SCK falling edge

SCK rising edge

SCK falling edge

SCK rising edge

The definition of when a transfer starts and stops is dependent on whether a device is a

master or a slave, and the setting of the CPHA variable.

When a device is a master, the start of a transfer is indicated by the master having a byte

of data that is ready to be transmitted. At this point, the master can activate the clock, and

begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.

When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal

goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is

set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on

the last clock edge where data is sampled.

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6. SPI peripheral details

6.1 General information

There are five control and status registers for the SPI port. They are described in detail in

Section 17–7 “Register description” on page 404.

The SPI Control Register (S0SPCR) contains a number of programmable bits used to

control the function of the SPI block. The settings for this register must be set up prior to a

given data transfer taking place.

The SPI Status Register (S0SPSR) contains read-only bits that are used to monitor the

status of the SPI interface, including normal functions, and exception conditions. The

primary purpose of this register is to detect completion of a data transfer. This is indicated

by the SPI Interrupt Flag (SPIF) in the S0SPINT register. The remaining bits in the register

are exception condition indicators. These exceptions will be described later in this section.

The SPI Data Register (S0SPDR) is used to provide the transmit and receive data bytes.

An internal shift register in the SPI block logic is used for the actual transmission and

reception of the serial data. Data is written to the SPI Data Register for the transmit case.

There is no buffer between the data register and the internal shift register. A write to the

data register goes directly into the internal shift register. Therefore, data should only be

written to this register when a transmit is not currently in progress. Read data is buffered.

When a transfer is complete, the receive data is transferred to a single byte data buffer,

where it is later read. A read of the SPI Data Register returns the value of the read data

buffer.

The SPI Clock Counter Register (S0SPCCR) controls the clock rate when the SPI block is

in master mode. This needs to be set prior to a transfer taking place, when the SPI block

is a master. This register has no function when the SPI block is a slave.

Prior to use, SPI configurations such as the master/slave settings, clock polarity, clock

rate, etc. must be set up in the SPI Control Register and SPI Clock Counter Register.

The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI

option is not implemented in this design. When a device is set up to be a slave, its I/Os are

only active when it is selected by the SSEL signal being active.

6.2 Master operation

The following sequence can be followed to set up the SPI prior to its first use as a master.

This is typically done during program initialization.

1. Set the SPI Clock Counter Register to the desired clock rate.

2. Set the SPI Control Register to the desired settings for master mode.

The following sequence describes how one should process a data transfer with the SPI

block when it is set up to be the master. This process assumes that any prior data transfer

has already completed.

1. Optionally, verify the SPI setup before starting the transfer.

2. Write the data to transmitted to the SPI Data Register. This write starts the SPI data

transfer.

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3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set

after the last cycle of the SPI data transfer.

4. Read the SPI Status Register.

5. Read the received data from the SPI Data Register (optional).

6. Go to step 2 if more data is to be transmitted.

Note: A read or write of the SPI Data Register is required in order to clear the SPIF status

bit. Therefore, if the optional read of the SPI Data Register does not take place, a write to

this register is required in order to clear the SPIF status bit.

6.3 Slave operation

The following sequence can be followed to set up the SPI prior to its first use as a slave.

This is typically done during program initialization.

1. Set the SPI Control Register to the desired settings for slave mode.

The following sequence describes how one should process a data transfer with the SPI

block when it is set up to be a slave. This process assumes that any prior data transfer

has already completed. It is required that the system clock driving the SPI logic be at least

8X faster than the SPI.

1. Optionally, verify the SPI setup before starting the transfer.

2. Write the data to transmitted to the SPI Data Register (optional). Note that this can

only be done when a slave SPI transfer is not in progress.

3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set

after the last sampling clock edge of the SPI data transfer.

4. Read the SPI Status Register.

5. Read the received data from the SPI Data Register (optional).

6. Go to step 2 if more data is to be transferred.

Note: A read or write of the SPI Data Register is required in order to clear the SPIF status

bit. Therefore, at least one of the optional reads or writes of the SPI Data Register must

take place, in order to clear the SPIF status bit.

6.4 Exception conditions

Read Overrun

A read overrun occurs when the SPI block internal read buffer contains data that has not

been read by the processor, and a new transfer has completed. The read buffer

containing valid data is indicated by the SPIF bit in the SPI Interrupt Register being active.

When a transfer completes, the SPI block needs to move the received data to the read

buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and

the read overrun (ROVR) bit in the SPI Status Register will be activated.

Write Collision

As stated previously, there is no write buffer between the SPI block bus interface, and the

internal shift register. As a result, data must not be written to the SPI Data Register when

a SPI data transfer is currently in progress. The time frame where data cannot be written

to the SPI Data Register is from when the transfer starts, until after the SPI Status

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Register has been read when the SPIF status is active. If the SPI Data Register is written

in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI

Status Register will be activated.

Mode Fault

If the SSEL signal goes active when the SPI block is a master, this indicates another

master has selected the device to be a slave. This condition is known as a mode fault.

When a mode fault is detected, the mode fault (MODF) bit in the SPI Status Register will

be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed

to be a slave.

If the SSEL function is assigned to its related pin in the relevant Pin Function Select

Register, the SSEL signal must always be inactive when the SPI controller is a master.

Slave Abort

A slave transfer is considered to be aborted if the SSEL signal goes inactive before the

transfer is complete. In the event of a slave abort, the transmit and receive data for the

transfer that was in progress are lost, and the slave abort (ABRT) bit in the SPI Status

Register will be activated.

7. Register description

The SPI contains 5 registers as shown in Table 17–361. All registers are byte, half word

and word accessible.

Table 361. SPI register map

Name

Description

Access Reset

Value^[1]

Address

S0SPCR

S0SPSR

S0SPDR

SPI Control Register. This register controls the

operation of the SPI.

R/W

0x00

0x4002 0000

0x4002 0004

0x4002 0008

SPI Status Register. This register shows the

status of the SPI.

RO

SPI Data Register. This bi-directional register

provides the transmit and receive data for the

SPI. Transmit data is provided to the SPI0 by

writing to this register. Data received by the SPI0

can be read from this register.

R/W

S0SPCCR SPI Clock Counter Register. This register

controls the frequency of a master’s SCK0.

R/W

0x00

0x4002 000C

0x4002 001C

S0SPINT SPI Interrupt Flag. This register contains the

interrupt flag for the SPI interface.

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

7.1 SPI Control Register (S0SPCR - 0x4002 0000)

The S0SPCR register controls the operation of SPI0 as per the configuration bits setting

shown in Table 17–362.

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Table 362: SPI Control Register (S0SPCR - address 0x4002 0000) bit description

Bit

1:0

2

Symbol

Value Description

Reset

Value

-

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

BitEnable

0

1

The SPI controller sends and receives 8 bits of data per

transfer.

0

The SPI controller sends and receives the number of bits

selected by bits 11:8.

3

CPHA

Clock phase control determines the relationship between the

data and the clock on SPI transfers, and controls when a slave

transfer is defined as starting and ending.

0

1

Data is sampled on the first clock edge of SCK. A transfer starts

and ends with activation and deactivation of the SSEL signal.

Data is sampled on the second clock edge of the SCK. A

transfer starts with the first clock edge, and ends with the last

sampling edge when the SSEL signal is active.

4

5

6

CPOL

MSTR

LSBF

Clock polarity control.

0

1

SCK is active high.

SCK is active low.

Master mode select.

0

1

The SPI operates in Slave mode.

The SPI operates in Master mode.

LSB First controls which direction each byte is shifted when

transferred.

0

1

SPI data is transferred MSB (bit 7) first.

SPI data is transferred LSB (bit 0) first.

Serial peripheral interrupt enable.

SPI interrupts are inhibited.

7

SPIE

0

1

A hardware interrupt is generated each time the SPIF or MODF

bits are activated.

11:8 BITS

When bit 2 of this register is 1, this field controls the number of 0000

bits per transfer:

1000 8 bits per transfer

1001 9 bits per transfer

1010 10 bits per transfer

1011 11 bits per transfer

1100 12 bits per transfer

1101 13 bits per transfer

1110 14 bits per transfer

1111 15 bits per transfer

0000 16 bits per transfer

31:12 -

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

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7.2 SPI Status Register (S0SPSR - 0x4002 0004)

The S0SPSR register controls the operation of SPI0 as per the configuration bits setting

shown in Table 17–363.

Table 363: SPI Status Register (S0SPSR - address 0x4002 0004) bit description

Bit

2:0

3

Symbol Description

Reset

Value

-

Reserved, user software should not write ones to reserved bits. The

NA

value read from a reserved bit is not defined.

ABRT

MODF

Slave abort. When 1, this bit indicates that a slave abort has occurred.

This bit is cleared by reading this register.

0

4

Mode fault. when 1, this bit indicates that a Mode fault error has

occurred. This bit is cleared by reading this register, then writing the

SPI0 control register.

0

5

6

ROVR

WCOL

Read overrun. When 1, this bit indicates that a read overrun has

occurred. This bit is cleared by reading this register.

0

Write collision. When 1, this bit indicates that a write collision has

occurred. This bit is cleared by reading this register, then accessing the

SPI Data Register.

7

SPIF

SPI transfer complete flag. When 1, this bit indicates when a SPI data

transfer is complete. When a master, this bit is set at the end of the last

cycle of the transfer. When a slave, this bit is set on the last data

sampling edge of the SCK. This bit is cleared by first reading this

register, then accessing the SPI Data Register.

0

Note: this is not the SPI interrupt flag. This flag is found in the SPINT

register.

31:8

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

7.3 SPI Data Register (S0SPDR - 0x4002 0008)

This bi-directional data register provides the transmit and receive data for the SPI.

Transmit data is provided to the SPI by writing to this register. Data received by the SPI

can be read from this register. When used as a master, a write to this register will start an

SPI data transfer. Writes to this register will be blocked when a data transfer starts, or

when the SPIF status bit is set, and the SPI Status Register has not been read.

Table 364: SPI Data Register (S0SPDR - address 0x4002 0008) bit description

Bit

Symbol

Description

Reset

Value

7:0

DataLow SPI Bi-directional data port.

0x00

15:8 DataHigh If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all 0x00

of these bits contain the additional transmit and receive bits. When less

than 16 bits are selected, the more significant among these bits read

as zeroes.

31:16 -

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

7.4 SPI Clock Counter Register (S0SPCCR - 0x4002 000C)

This register controls the frequency of a master’s SCK. The register indicates the number

of SPI peripheral clock cycles that make up an SPI clock.

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In Master mode, this register must be an even number greater than or equal to 8.

Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be

calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the

PCLKSEL0 register contents for PCLK_SPI as described in Section 4–7.3.

In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI

peripheral clock selected in Section 4–7.3. The content of the S0SPCCR register is not

relevant.

Table 365: SPI Clock Counter Register (S0SPCCR - address 0x4002 000C) bit description

Bit

Symbol Description

Reset

Value

7:0

Counter SPI0 Clock counter setting.

0x00

NA

31:8

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

7.5 SPI Test Control Register (SPTCR - 0x4002 0010)

Note that the bits in this register are intended for functional verification only. This register

should not be used for normal operation.

Table 366: SPI Test Control Register (SPTCR - address 0x4002 0010) bit description

Bit

Symbol Description

Reset

Value

0

-

Reserved, user software should not write ones to reserved bits. The

NA

value read from a reserved bit is not defined.

7:1

Test

SPI test mode. When 0, the SPI operates normally. When 1, SCK will

always be on, independent of master mode select, and data availability

setting.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

7.6 SPI Test Status Register (SPTSR - 0x4002 0014)

Note: The bits in this register are intended for functional verification only. This register

should not be used for normal operation.

This register is a replication of the SPI Status Register. The difference between the

registers is that a read of this register will not start the sequence of events required to

clear these status bits. A write to this register will set an interrupt if the write data for the

respective bit is a 1.

Table 367: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description

Bit

Symbol Description

Reset

Value

2:0

-

Reserved, user software should not write ones to reserved bits. The

NA

value read from a reserved bit is not defined.

3

4

5

ABRT

MODF

ROVR

Slave abort.

Mode fault.

0

Read overrun.

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Table 367: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description

Bit

Symbol Description

Reset

Value

6

WCOL

SPIF

-

Write collision.

0

7

SPI transfer complete flag.

0

31:8

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

7.7 SPI Interrupt Register (S0SPINT - 0x4002 001C)

This register contains the interrupt flag for the SPI0 interface.

Table 368: SPI Interrupt Register (S0SPINT - address 0x4002 001C) bit description

Bit

Symbol Description

Reset

Value

0

SPIF

SPI interrupt flag. Set by the SPI interface to generate an interrupt.

0

Cleared by writing a 1 to this bit.

Note: this bit will be set once when SPIE = 1 and at least one of SPIF

and WCOL bits is 1. However, only when the SPI Interrupt bit is set and

SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be

processed by interrupt handling software.

7:1

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

31:8

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

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8. Architecture

The block diagram of the SPI solution implemented in SPI0 interface is shown in the

Figure 17–74.

MOSI_IN

MOSI_OUT

MISO_IN

MISO_OUT

SPI SHIFT REGISTER

SCK_IN

SCK_OUT

SS_IN

SPI CLOCK

GENERATOR &

DETECTOR

SPI Interrupt

SPI REGISTER

INTERFACE

APB Bus

SPI STATE CONTROL

SCK_OUT_EN

MOSI_OUT_EN

MISO_OUT_EN

OUTPUT

ENABLE

LOGIC

Fig 74. SPI block diagram

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1. Basic configuration

The two SSP interfaces, SSP0 and SSP1 are configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCSSP0 to enable SSP0 and bit

PCSSP1 to enable SSP1.

Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).

2. Clock: In PCLKSEL0 select PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see

Section 4–7.3. In master mode, the clock must be scaled down (see Section 18–6.5).

3. Pins: Select the SSP pins through the PINSEL registers (Section 8–5) and pin modes

through the PINMODE registers (Section 8–4).

4. Interrupts: Interrupts are enabled in the SSP0IMSC register for SSP0 and SSP1IMSC

register for SSP1 Table 18–376. Interrupts are enabled in the NVIC using the

appropriate Interrupt Set Enable register, see Table 6–50.

5. Initialization: There are two control registers for each of the SSP ports to be

configured: SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1.

See Section 18–6.1 and Section 18–6.2.

6. DMA: The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA

controller (see Section 18–6.10). For GPDMA system connections, see

Table 31–544.

Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is

included as a legacy peripheral. Only one of these peripherals can be used at the any one

time.

2. Features

• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire

buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8 frame FIFOs for both transmit and receive.

• 4 to 16 bit data frame.

• DMA transfers supported by GPDMA.

3. Description

The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,

4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.

Only a single master and a single slave can communicate on the bus during a given data

transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data

flowing from the master to the slave and from the slave to the master. In practice it is often

the case that only one of these data flows carries meaningful data.

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The LPC17xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.

4. Pin descriptions

Table 369. SSP pin descriptions

Interface pin

name/function

Type

Pin Description

Name

SPI

SSI

Microwire

SCK0/1 I/O

SSEL0/1 I/O

SCK CLK

SK

Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer

of data. It is driven by the master and received by the slave. When the SPI

interface is used, the clock is programmable to be active-high or active-low,

otherwise it is always active-high. SCK1 only switches during a data transfer.

Any other time, the SSPn interface either holds it in its inactive state, or does

not drive it (leaves it in high-impedance state).

SSEL FS

CS

Frame Sync/Slave Select. When the SSPn interface is a bus master, it

drives this signal to an active state before the start of serial data, and then

releases it to an inactive state after the serial data has been sent. The active

state of this signal can be high or low depending upon the selected bus and

mode. When the SSPn is a bus slave, this signal qualifies the presence of

data from the Master, according to the protocol in use.

When there is just one bus master and one bus slave, the Frame Sync or

Slave Select signal from the Master can be connected directly to the slave's

corresponding input. When there is more than one slave on the bus, further

qualification of their Frame Select/Slave Select inputs will typically be

necessary to prevent more than one slave from responding to a transfer.

MISO0/1 I/O

MOSI0/1 I/O

MISO DR(M) SI(M)

DX(S) SO(S)

Master In Slave Out. The MISO signal transfers serial data from the slave to

the master. When the SSPn is a slave, serial data is output on this signal.

When the SSPn is a master, it clocks in serial data from this signal. When the

SSPn is a slave and is not selected by FS/SSEL, it does not drive this signal

(leaves it in high-impedance state).

MOSI DX(M) SO(M)

DR(S) SI(S)

Master Out Slave In. The MOSI signal transfers serial data from the master

to the slave. When the SSPn is a master, it outputs serial data on this signal.

When the SSPn is a slave, it clocks in serial data from this signal.

5. Bus description

5.1 Texas Instruments synchronous serial frame format

Figure 18–75 shows the 4-wire Texas Instruments synchronous serial frame format

supported by the SSP module.

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CLK

FS

DX/DR

MSB

LSB

4 to 16 bits

a. Single frame transfer

CLK

FS

DX/DR

MSB

LSB

MSB

LSB

4 to 16 bits

b. Continuous/back-to-back frames transfer

Fig 75. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two

Frames Transfer

For device configured as a master in this mode, CLK and FS are forced LOW, and the

transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the

transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be

transmitted is also transferred from the transmit FIFO to the serial shift register of the

transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is

shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR

pin by the off-chip serial slave device.

Both the SSP and the off-chip serial slave device then clock each data bit into their serial

shifter on the falling edge of each CLK. The received data is transferred from the serial

shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

5.2 SPI frame format

The SPI interface is a four-wire interface where the SSEL signal behaves as a slave

select. The main feature of the SPI format is that the inactive state and phase of the SCK

signal are programmable through the CPOL and CPHA bits within the SSPCR0 control

register.

5.2.1 Clock Polarity (CPOL) and Phase (CPHA) control

When the CPOL clock polarity control bit is 0, it produces a steady state low value on the

SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on

the CLK pin when data is not being transferred.

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The CPHA control bit selects the clock edge that captures data and allows it to change

state. It has the most impact on the first bit transmitted by either allowing or not allowing a

clock transition before the first data capture edge. When the CPHA phase control bit is 0,

data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,

data is captured on the second clock edge transition.

5.2.2 SPI format with CPOL=0,CPHA=0

Single and continuous transmission signal sequences for SPI format with CPOL = 0,

CPHA = 0 are shown in Figure 18–76.

SCK

SSEL

MSB

LSB

MOSI

MISO

Q

4 to 16 bits

a. Single transfer with CPOL=0 and CPHA=0

SCK

SSEL

MOSI

MISO

MSB

LSB

MSB

LSB

Q

4 to 16 bits

b. Continuous transfer with CPOL=0 and CPHA=0

Fig 76. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)

In this configuration, during idle periods:

• The CLK signal is forced LOW.

• SSEL is forced HIGH.

• The transmit MOSI/MISO pad is in high impedance.

If the SSP is enabled and there is valid data within the transmit FIFO, the start of

transmission is signified by the SSEL master signal being driven LOW. This causes slave

data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.

One half SCK period later, valid master data is transferred to the MOSI pin. Now that both

the master and slave data have been set, the SCK master clock pin goes HIGH after one

further half SCK period.

The data is now captured on the rising and propagated on the falling edges of the SCK

signal.

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In the case of a single word transmission, after all bits of the data word have been

transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last

bit has been captured.

However, in the case of continuous back-to-back transmissions, the SSEL signal must be

pulsed HIGH between each data word transfer. This is because the slave select pin

freezes the data in its serial peripheral register and does not allow it to be altered if the

CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave

device between each data transfer to enable the serial peripheral data write. On

completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK

period after the last bit has been captured.

5.2.3 SPI format with CPOL=0,CPHA=1

The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in

Figure 18–77, which covers both single and continuous transfers.

SCK

SSEL

MSB

LSB

MOSI

MISO

Q

4 to 16 bits

Fig 77. SPI frame format with CPOL=0 and CPHA=1

In this configuration, during idle periods:

• The CLK signal is forced LOW.

• SSEL is forced HIGH.

• The transmit MOSI/MISO pad is in high impedance.

If the SSP is enabled and there is valid data within the transmit FIFO, the start of

transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin

is enabled. After a further one half SCK period, both master and slave valid data is

enabled onto their respective transmission lines. At the same time, the SCK is enabled

with a rising edge transition.

Data is then captured on the falling edges and propagated on the rising edges of the SCK

signal.

In the case of a single word transfer, after all bits have been transferred, the SSEL line is

returned to its idle HIGH state one SCK period after the last bit has been captured.

For continuous back-to-back transfers, the SSEL pin is held LOW between successive

data words and termination is the same as that of the single word transfer.

5.2.4 SPI format with CPOL = 1,CPHA = 0

Single and continuous transmission signal sequences for SPI format with CPOL=1,

CPHA=0 are shown in Figure 18–78.

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SCK

SSEL

MSB

LSB

MOSI

MISO

LSB

Q

4 to 16 bits

a. Single transfer with CPOL=1 and CPHA=0

SCK

SSEL

MOSI

MISO

MSB

LSB

MSB

LSB

Q

4 to 16 bits

b. Continuous transfer with CPOL=1 and CPHA=0

Fig 78. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)

In this configuration, during idle periods:

• The CLK signal is forced HIGH.

• SSEL is forced HIGH.

• The transmit MOSI/MISO pad is in high impedance.

If the SSP is enabled and there is valid data within the transmit FIFO, the start of

transmission is signified by the SSEL master signal being driven LOW, which causes

slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI

pin is enabled.

One half period later, valid master data is transferred to the MOSI line. Now that both the

master and slave data have been set, the SCK master clock pin becomes LOW after one

further half SCK period. This means that data is captured on the falling edges and be

propagated on the rising edges of the SCK signal.

In the case of a single word transmission, after all bits of the data word are transferred, the

SSEL line is returned to its idle HIGH state one SCK period after the last bit has been

captured.

However, in the case of continuous back-to-back transmissions, the SSEL signal must be

pulsed HIGH between each data word transfer. This is because the slave select pin

freezes the data in its serial peripheral register and does not allow it to be altered if the

CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave

device between each data transfer to enable the serial peripheral data write. On

completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK

period after the last bit has been captured.

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5.2.5 SPI format with CPOL = 1,CPHA = 1

The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in

Figure 18–79, which covers both single and continuous transfers.

SCK

SSEL

MSB

LSB

MOSI

MISO

Q

4 to 16 bits

Fig 79. SPI Frame Format with CPOL = 1 and CPHA = 1

In this configuration, during idle periods:

• The CLK signal is forced HIGH.

• SSEL is forced HIGH.

• The transmit MOSI/MISO pad is in high impedance.

If the SSP is enabled and there is valid data within the transmit FIFO, the start of

transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is

enabled. After a further one half SCK period, both master and slave data are enabled onto

their respective transmission lines. At the same time, the SCK is enabled with a falling

edge transition. Data is then captured on the rising edges and propagated on the falling

edges of the SCK signal.

After all bits have been transferred, in the case of a single word transmission, the SSEL

line is returned to its idle HIGH state one SCK period after the last bit has been captured.

For continuous back-to-back transmissions, the SSEL pins remains in its active LOW

state, until the final bit of the last word has been captured, and then returns to its idle state

as described above. In general, for continuous back-to-back transfers the SSEL pin is

held LOW between successive data words and termination is the same as that of the

single word transfer.

5.3 National Semiconductor Microwire frame format

Figure 18–80 shows the Microwire frame format for a single frame. Figure 18–81 shows

the same format when back-to-back frames are transmitted.

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SK

CS

MSB

LSB

SO

SI

8-bit control

MSB

LSB

0

4 to 16 bits

output data

Fig 80. Microwire frame format (single transfer)

Microwire format is very similar to SPI format, except that transmission is half-duplex

instead of full-duplex, using a master-slave message passing technique. Each serial

transmission begins with an 8-bit control word that is transmitted from the SSP to the

off-chip slave device. During this transmission, no incoming data is received by the SSP.

After the message has been sent, the off-chip slave decodes it and, after waiting one

serial clock after the last bit of the 8-bit control message has been sent, responds with the

required data. The returned data is 4 to 16 bits in length, making the total frame length

anywhere from 13 to 25 bits.

In this configuration, during idle periods:

• The SK signal is forced LOW.

• CS is forced HIGH.

• The transmit data line SO is arbitrarily forced LOW.

A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge

of CS causes the value contained in the bottom entry of the transmit FIFO to be

transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control

frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame

transmission. The SI pin remains tristated during this transmission.

The off-chip serial slave device latches each control bit into its serial shifter on the rising

edge of each SK. After the last bit is latched by the slave device, the control byte is

decoded during a one clock wait-state, and the slave responds by transmitting data back

to the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turn

latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the

CS signal is pulled HIGH one clock period after the last bit has been latched in the receive

serial shifter, that causes the data to be transferred to the receive FIFO.

Note: The off-chip slave device can tristate the receive line either on the falling edge of

SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.

For continuous transfers, data transmission begins and ends in the same manner as a

single transfer. However, the CS line is continuously asserted (held LOW) and

transmission of data occurs back to back. The control byte of the next frame follows

directly after the LSB of the received data from the current frame. Each of the received

values is transferred from the receive shifter on the falling edge SK, after the LSB of the

frame has been latched into the SSP.

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SK

CS

SO

LSB

MSB

LSB

8-bit control

SI

MSB

LSB

MSB

LSB

0

4 to 16 bits

output data

4 to 16 bits

output data

Fig 81. Microwire frame format (continuos transfers)

5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire

mode

In the Microwire mode, the SSP slave samples the first bit of receive data on the rising

edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure

that the CS signal has sufficient setup and hold margins with respect to the rising edge of

SK.

Figure 18–82 illustrates these setup and hold time requirements. With respect to the SK

rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS

must have a setup of at least two times the period of SK on which the SSP operates. With

respect to the SK rising edge previous to this edge, CS must have a hold of at least one

SK period.

t_SETUP=2*t_SK

t_HOLD= t_SK

SK

CS

SI

Fig 82. Microwire frame format setup and hold details

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6. Register description

The register addresses of the SSP controllers addresses are shown in Table 18–370.

Table 370. SSP Register Map

Generic Description

Name

Access Reset

SSPn Register

Value^[1]Name & Address

CR0

Control Register 0. Selects the

R/W

0

SSP0CR0 - 0x4008 8000

serial clock rate, bus type, and data

size.

SSP1CR0 - 0x4003 0000

CR1

DR

Control Register 1. Selects

master/slave and other modes.

R/W

0

SSP0CR1 - 0x4008 8004

SSP1CR1 - 0x4003 0004

Data Register. Writes fill the

transmit FIFO, and reads empty

the receive FIFO.

SSP0DR - 0x4008 8008

SSP1DR - 0x4003 0008

SR

Status Register

RO

SSP0SR - 0x4008 800C

SSP1SR - 0x4003 000C

CPSR

IMSC

RIS

Clock Prescale Register

R/W

0

SSP0CPSR - 0x4008 8010

SSP1CPSR - 0x4003 0010

Interrupt Mask Set and Clear

Register

SSP0IMSC - 0x4008 8014

SSP1IMSC - 0x4003 0014

Raw Interrupt Status Register

Masked Interrupt Status Register

SSPICR Interrupt Clear Register

SSP0RIS - 0x4008 8018

SSP1RIS - 0x4003 0018

MIS

0

SSP0MIS - 0x4008 801C

SSP1MIS - 0x4003 001C

ICR

NA

0

SSP0ICR - 0x4008 8020

SSP1ICR - 0x4003 0020

DMACR DMA Control Register

SSP0DMACR - 0x4008 8024

SSP1DMACR - 0x4003 0024

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 SSPn Control Register 0 (SSP0CR0 - 0x4008 8000, SSP1CR0 - 0x4003

0000)

This register controls the basic operation of the SSP controller.

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Table 371: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 -

0x4003 0000) bit description

Bit

Symbol Value Description

Reset

Value

3:0

DSS

Data Size Select. This field controls the number of bits

0000

transferred in each frame. Values 0000-0010 are not supported

and should not be used.

0011 4-bit transfer

0100 5-bit transfer

0101 6-bit transfer

0110 7-bit transfer

0111 8-bit transfer

1000 9-bit transfer

1001 10-bit transfer

1010 11-bit transfer

1011 12-bit transfer

1100 13-bit transfer

1101 14-bit transfer

1110 15-bit transfer

1111 16-bit transfer

Frame Format.

5:4

FRF

00

01

10

11

SPI

TI

Microwire

This combination is not supported and should not be used.

Clock Out Polarity. This bit is only used in SPI mode.

SSP controller maintains the bus clock low between frames.

SSP controller maintains the bus clock high between frames.

Clock Out Phase. This bit is only used in SPI mode.

6

7

CPOL

CPHA

0

1

0

1

SSP controller captures serial data on the first clock transition of

the frame, that is, the transition away from the inter-frame state

of the clock line.

SSP controller captures serial data on the second clock transition

of the frame, that is, the transition back to the inter-frame state of

the clock line.

15:8 SCR

Serial Clock Rate. The number of prescaler-output clocks per bit 0x00

on the bus, minus one. Given that CPSDVSR is the prescale

divider, and the APB clock PCLK clocks the prescaler, the bit

frequency is PCLK / (CPSDVSR × [SCR+1]).

31:8

-

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

6.2 SSPn Control Register 1 (SSP0CR1 - 0x4008 8004, SSP1CR1 -

0x4003 0004)

This register controls certain aspects of the operation of the SSP controller.

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Table 372: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 -

0x4003 0004) bit description

Bit

Symbol Value Description

Reset

Value

0

LBM

SSE

Loop Back Mode.

0

1

During normal operation.

Serial input is taken from the serial output (MOSI or MISO) rather

than the serial input pin (MISO or MOSI respectively).

1

2

SSP Enable.

0

1

The SSP controller is disabled.

The SSP controller will interact with other devices on the serial

bus. Software should write the appropriate control information to

the other SSP registers and interrupt controller registers, before

setting this bit.

MS

Master/Slave Mode.This bit can only be written when the SSE bit

is 0.

0

1

The SSP controller acts as a master on the bus, driving the

SCLK, MOSI, and SSEL lines and receiving the MISO line.

The SSP controller acts as a slave on the bus, driving MISO line

and receiving SCLK, MOSI, and SSEL lines.

3

SOD

-

Slave Output Disable. This bit is relevant only in slave mode

(MS = 1). If it is 1, this blocks this SSP controller from driving the

transmit data line (MISO).

31:4

Reserved, user software should not write ones to reserved bits. NA

The value read from a reserved bit is not defined.

6.3 SSPn Data Register (SSP0DR - 0x4008 8008, SSP1DR - 0x4003 0008)

Software can write data to be transmitted to this register, and read data that has been

received.

Table 373: SSPn Data Register (SSP0DR - address 0x4008 8008, SSP1DR - 0x4003 0008) bit

description

Bit

Symbol Description

Reset

Value

15:0 DATA

Write: software can write data to be sent in a future frame to this

register whenever the TNF bit in the Status register is 1, indicating that

the Tx FIFO is not full. If the Tx FIFO was previously empty and the

SSP controller is not busy on the bus, transmission of the data will

begin immediately. Otherwise the data written to this register will be

sent as soon as all previous data has been sent (and received). If the

data length is less than 16 bits, software must right-justify the data

written to this register.

0x0000

Read: software can read data from this register whenever the RNE bit

in the Status register is 1, indicating that the Rx FIFO is not empty.

When software reads this register, the SSP controller returns data from

the least recent frame in the Rx FIFO. If the data length is less than 16

bits, the data is right-justified in this field with higher order bits filled with

0s.

31:16 -

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

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6.4 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR -

0x4003 000C)

This read-only register reflects the current status of the SSP controller.

Table 374: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C)

bit description

Bit

Symbol Description

Reset

Value

0

1

2

TFE

TNF

RNE

Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1

Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.

1

0

Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if

not.

3

4

RFF

BSY

Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.

0

Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently

sending/receiving a frame and/or the Tx FIFO is not empty.

31:5

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.5 SSPn Clock Prescale Register (SSP0CPSR - 0x4008 8010, SSP1CPSR

- 0x4003 0010)

This register controls the factor by which the Prescaler divides the SSP peripheral clock

SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in

SSPnCR0, to determine the bit clock.

Table 375: SSPn Clock Prescale Register (SSP0CPSR - address 0x4008 8010, SSP1CPSR -

0x4003 0010) bit description

Bit

Symbol

Description

Reset

Value

7:0

CPSDVSR This even value between 2 and 254, by which SSP_PCLK is divided

to yield the prescaler output clock. Bit 0 always reads as 0.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The NA

value read from a reserved bit is not defined.

Important: the SSPnCPSR value must be properly initialized or the SSP controller will not

be able to transmit data correctly.

In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the

SSP peripheral clock selected in Section 4–7.3. The content of the SSPnCPSR register is

not relevant.

In master mode, CPSDVSR_min= 2 or larger (even numbers only).

6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4008 8014,

SSP1IMSC - 0x4003 0014)

This register controls whether each of the four possible interrupt conditions in the SSP

controller are enabled. Note that ARM uses the word “masked” in the opposite sense from

classic computer terminology, in which “masked” meant “disabled”. ARM uses the word

“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.

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Table 376: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014,

SSP1IMSC - 0x4003 0014) bit description

Bit

Symbol Description

Reset

Value

0

RORIM Software should set this bit to enable interrupt when a Receive Overrun

occurs, that is, when the Rx FIFO is full and another frame is completely

received. The ARM spec implies that the preceding frame data is

overwritten by the new frame data when this occurs.

0

1

RTIM

Software should set this bit to enable interrupt when a Receive Timeout

condition occurs. A Receive Timeout occurs when the Rx FIFO is not

empty, and no has not been read for a "timeout period".

0

2

RXIM

TXIM

-

Software should set this bit to enable interrupt when the Rx FIFO is at

least half full.

0

3

Software should set this bit to enable interrupt when the Tx FIFO is at

least half empty.

0

31:4

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0x4008 8018,

SSP1RIS - 0x4003 0018)

This read-only register contains a 1 for each interrupt condition that is asserted,

regardless of whether or not the interrupt is enabled in the SSPnIMSC.

Table 377: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS -

0x4003 0018) bit description

Bit

Symbol Description

Reset

Value

0

RORRIS This bit is 1 if another frame was completely received while the RxFIFO

was full. The ARM spec implies that the preceding frame data is

overwritten by the new frame data when this occurs.

0

1

RTRIS

This bit is 1 if the Rx FIFO is not empty, and has not been read for a

"timeout period".

0

2

RXRIS

TXRIS

-

This bit is 1 if the Rx FIFO is at least half full.

This bit is 1 if the Tx FIFO is at least half empty.

0

3

1

31:4

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C,

SSP1MIS - 0x4003 001C)

This read-only register contains a 1 for each interrupt condition that is asserted and

enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine

should read this register to determine the cause(s) of the interrupt.

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Table 378: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS

- 0x4003 001C) bit description

Bit

Symbol

Description

Reset

Value

0

RORMIS This bit is 1 if another frame was completely received while the RxFIFO

was full, and this interrupt is enabled.

0

1

RTMIS

RXMIS

TXMIS

-

This bit is 1 if the Rx FIFO is not empty, has not been read for a

"timeout period", and this interrupt is enabled.

0

2

This bit is 1 if the Rx FIFO is at least half full, and this interrupt is

enabled.

0

3

This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is

enabled.

0

31:4

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.9 SSPn Interrupt Clear Register (SSP0ICR - 0x4008 8020, SSP1ICR -

0x4003 0020)

Software can write one or more one(s) to this write-only register, to clear the

corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt

conditions can be cleared by writing or reading the appropriate FIFO, or disabled by

clearing the corresponding bit in SSPnIMSC.

Table 379: SSPn interrupt Clear Register (SSP0ICR - address 0x4008 8020, SSP1ICR -

0x4003 0020) bit description

Bit

Symbol Description

Reset

Value

0

RORIC Writing a 1 to this bit clears the “frame was received when RxFIFO was NA

full” interrupt.

1

RTIC

Writing a 1 to this bit clears the "Rx FIFO was not empty and has not

been read for a timeout period" interrupt.

NA

31:2

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

6.10 SSPn DMA Control Register (SSP0DMACR - 0x4008 8024,

SSP1DMACR - 0x4003 0024)

The SSPnDMACR register is the DMA control register. It is a read/write register.

Table 380: SSPn DMA Control Register (SSP0DMACR - address 0x4008 8024, SSP1DMACR -

0x4003 0024) bit description

Bit

Symbol

Description

Reset

Value

0

Receive DMA Enable When this bit is set to one 1, DMA for the receive FIFO is

(RXDMAE) enabled, otherwise receive DMA is disabled.

0

1

Transmit DMA Enable When this bit is set to one 1, DMA for the transmit FIFO is

0

(TXDMAE)

enabled, otherwise transmit DMA is disabled

31:2

-

Reserved, user software should not write ones to reserved NA

bits. The value read from a reserved bit is not defined.

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Chapter 19: LPC17xx I2C0/1/2 interface

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1. Basic configuration

The I²C0/1/2 interfaces are configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCI2C0/1/2.

Remark: On reset, all I²C interfaces are enabled (PCI2C0/1/2 = 1).

2. Clock: In PCLKSEL0 select PCLK_I2C0; in PCLKSEL1 select PCLK_I2C1 or

PCLK_I2C2 (see Section 4–7.3).

3. Pins: Select I²C0, I²C1, or I²C2 pins through the PINSEL registers. Select the pin

modes for the port pins with I²C1 or I²C2 functions through the PINMODE registers

(no pull-up, no pull-down resistors) and the PINMODE_OD registers (open drain)

(See Section 8–5).

Remark: I²C0 pins SDA0 and SCL0 are open-drain outputs and fully I²C-bus

compliant (see Table 7–72). I²C0 can be further configured through the I2CPADCFG

register to support Fast Mode Plus (See Table 8–98).

Remark: I²C0 is not available in the 80-pin package.

Remark: I²C1 and I²C2 pins are not fully I²C-bus compliant open-drain pins but can

be configured to be open-drain via the PINMODE and PINMODE_OD registers. The

non-compliance is in the I²C-bus ability to turn off power to the device without pulling

down the I²C-bus itself.

4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.

5. Initialization: see Section 19–9.8.1 and Section 19–10.1.

2. Features

• Standard I²C compliant bus interfaces may be configured as Master, Slave, or

Master/Slave.

• Arbitration is handled between simultaneously transmitting masters without corruption

of serial data on the bus.

• Programmable clock allows adjustment of I²C transfer rates.

• Data transfer is bidirectional between masters and slaves.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization is used as a handshake mechanism to suspend and

resume serial transfer.

• Supports Fast Mode Plus (I²C0 only).

• Optional recognition of up to 4 distinct slave addresses.

• Monitor mode allows observing all I²C-bus traffic, regardless of slave address, without

affecting the actual I²C-bus traffic.

• The I²C-bus can be used for test and diagnostic purposes.

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• I²C0 is a standard I²C compliant bus interface with open-drain pins. This interface

supports functions described in the I²C specification for speeds up to 1 MHz. This

includes multi-master operation and allows powering off this device in a working

system while leaving the I²C-bus functional.

• I²C1 and I²C2 use standard I/O pins and are intended for use with a single-master

I²C-bus and do not support powering off of this device while leaving the I²C-bus

functional, and do not support multi-master I²C implementations.

3. Applications

Interfaces to external I²C standard parts, such as serial RAMs, LCDs, tone generators,

other microcontrollers, etc.

4. Description

A typical I²C-bus configuration is shown in Figure 19–83. Depending on the state of the

direction bit (R/W), two types of data transfers are possible on the I²C-bus:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted

by the master is the slave address. Next follows a number of data bytes. The slave

returns an acknowledge bit after each received byte, unless the slave device is unable

to accept more data.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave

address) is transmitted by the master. The slave then returns an acknowledge bit.

Next follows the data bytes transmitted by the slave to the master. The master returns

an acknowledge bit after all received bytes other than the last byte. At the end of the

last received byte, a “not acknowledge” is returned. The master device generates all

of the serial clock pulses and the START and STOP conditions. A transfer is ended

with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the I²C-bus will not be

released.

The LPC17xx I²C interfaces are byte oriented and have four operating modes: master

transmitter mode, master receiver mode, slave transmitter mode and slave receiver

mode.

I²C0 complies with the entire I²C specification, supporting the ability to have the LPC17xx

powered off and not interfere with other powered devices on the same I²C-bus. I²C1 and

I²C2 do not support the ability to have the power to the LPC17xx turned off without

interfering with other powered devices on the same I²C-bus.

Since I²C1 and I²C2 use standard port pins, internal pull-ups could (in theory) be enabled

in order to pull I²C-bus signals high when they are not driven low. However, these internal

pull-ups are far weaker than what would normally be used for I²C, so this practice is not

recommended. Refer to the “I²C-bus specification and user manual” for information on

proper pull-up values for a specific case.

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pull-up

resistor

pull-up

resistor

SDA

SCL

I ²C bus

SCL

SDA

OTHER DEVICE WITH

I ²C INTERFACE

OTHER DEVICE WITH

I C INTERFACE

LPCXXXX

2

Fig 83. I²C-bus configuration

4.1 I²C FAST Mode Plus

Fast Mode Plus is a 1 Mbit/sec transfer rate to communicate with the I²C products which

the NXP Semiconductors is now providing.

In order to use Fast Mode Plus, the I²C0 pins must be configured, then rates above 400

kHz and up to 1 Mhz may be selected, see Table 19–395. To configure the pins for Fast

Mode Plus, the SDADRV0 and SCLDRV0 bits in the I2CPADCFG register must be set,

see Section 8–5.21.

5. Pin description

Table 381. I²C Pin Description

Type

Description

SDA0^[1]

SCL0^[1]

SDA1

SCL1

SDA2

SCL2

Input/Output

I²C0 Serial Data

I²C0 Serial Clock

I²C1 Serial Data

I²C1 Serial Clock

I²C2 Serial Data

I²C2 Serial Clock

[1] I²C0 is only available in 100-pin LPC17xx devices. The SDA0 and SCL0 pins are open-drain pins to comply

with I²C specifications. The pins must be configured in the I2CPADCFG register for Fast Mode Plus.

The three I²C interfaces are identical except for the pin I/O characteristics. I²C0 complies

with the entire I²C specification, supporting the ability to turn power off to the device

without causing a problem with other devices on the same I²C-bus (see "The I²C-bus

specification" description under the heading "Fast Mode", and notes for the table titled

"Characteristics of the SDA and SCL I/O stages for F/S-mode I²C-bus devices"). This is

sometimes a useful capability, but intrinsically limits alternate uses for the same pins if the

I²C interface is not used. Seldom is this capability needed on multiple I²C interfaces within

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the same microcontroller. Therefore, I²C1 and I²C2 are implemented using standard port

pins, and do not support the ability to turn power off to the device while leaving the I²C-bus

functioning between other devices. Standard I/Os also change I²C-bus pull-up

characteristics and do not support multi-master I²C implementations. This difference

should be considered during system design while assigning uses for the I²C interfaces.

The pins associated with I²C1 and I²C2 should be switched to the open drain mode when

the pins are used for I²C communications.

6. I²C operating modes

In a given application, the I²C block may operate as a master, a slave, or both. In the slave

mode, the I²C hardware looks for any one of its four slave addresses and the General Call

address. If one of these addresses is detected, an interrupt is requested. If the processor

wishes to become the bus master, the hardware waits until the bus is free before the

master mode is entered so that a possible slave operation is not interrupted. If bus

arbitration is lost in the master mode, the I²C block switches to the slave mode

immediately and can detect any of its own configured slave addresses in the same serial

transfer.

6.1 Master Transmitter mode

In this mode data is transmitted from master to slave. Before the master transmitter mode

can be entered, the I2CONSET register must be initialized as shown in Table 19–382.

I2EN must be set to 1 to enable the I²C function. If the AA bit is 0, the I²C interface will not

acknowledge any address when another device is master of the bus, so it can not enter

slave mode. The STA, STO and SI bits must be 0. The SI bit is cleared by writing 1 to the

SIC bit in the I2CONCLR register. THe STA bit should be cleared after writing the slave

address.

Table 382. I2C0CONSET and I2C1CONSET used to configure Master mode

Bit

7

-

6

5

4

3

2

1

-

0

-

Symbol

Value

I2EN

1

STA

0

STO

0

SI

0

AA

0

-

The first byte transmitted contains the slave address of the receiving device (7 bits) and

the data direction bit. In this mode the data direction bit (R/W) should be 0 which means

Write. The first byte transmitted contains the slave address and Write bit. Data is

transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

START and STOP conditions are output to indicate the beginning and the end of a serial

transfer.

The I²C interface will enter master transmitter mode when software sets the STA bit. The

I²C logic will send the START condition as soon as the bus is free. After the START

condition is transmitted, the SI bit is set, and the status code in the I2STAT register is

0x08. This status code is used to vector to a state service routine which will load the slave

address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by

writing a 1 to the SIC bit in the I2CONCLR register.

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When the slave address and R/W bit have been transmitted and an acknowledgment bit

has been received, the SI bit is set again, and the possible status codes now are 0x18,

0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled

(by setting AA to 1). The appropriate actions to be taken for each of these status codes

are shown in Table 19–399 to Table 19–402.

A/A

S

SLAVE ADDRESS

RW=0

A

DATA

A

DATA

P

n bytes data transmitted

A = Acknowledge (SDA low)

from Master to Slave

from Slave to Master

A = Not acknowledge (SDA high)

S = START condition

P = STOP condition

Fig 84. Format in the Master Transmitter mode

6.2 Master Receiver mode

In the master receiver mode, data is received from a slave transmitter. The transfer is

initiated in the same way as in the master transmitter mode. When the START condition

has been transmitted, the interrupt service routine must load the slave address and the

data direction bit to the I²C Data register (I2DAT), and then clear the SI bit. In this case,

the data direction bit (R/W) should be 1 to indicate a read.

When the slave address and data direction bit have been transmitted and an

acknowledge bit has been received, the SI bit is set, and the Status Register will show the

status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For

slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to

Table 19–400.

When the LPC17xx needs to acknowledge a received byte, the AA bit needs to be set

accordingly prior to clearing the SI bit and initiating the byte read. When the LPC17xx

needs to not acknowledge a received byte, the AA bit needs to be cleared prior to clearing

the SI bit and initiating the byte read.

Note that the last received byte is always followed by a "Not Acknowledge" from the

LPC17xx so that the master can signal the slave that the reading sequence is finished and

that it needs to issue a STOP or repeated START Command. Once the "Not Acknowledge

has been sent and the SI bit is set, the LPC17xx can send either a STOP (STO bit is set)

or a repeated START (STA bit is set). Then the SI bit is cleared to initiate the requested

operation.

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A

S

SLAVE ADDRESS

RW=1

A

DATA

A

DATA

P

n bytes data received

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

from Master to Slave

from Slave to Master

P = STOP condition

Fig 85. Format of Master Receiver mode

After a repeated START condition, I²C may switch to the master transmitter mode.

S

SLA

R

A

DATA

A

DATA

A

Sr

SLA

W

A

DATA

A

P

n bytes data transmitted

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

From master to slave

From slave to master

P = STOP condition

SLA = Slave Address

Sr = Repeated START condition

Fig 86. A Master Receiver switches to Master Transmitter after sending repeated START

6.3 Slave Receiver mode

In the slave receiver mode, data bytes are received from a master transmitter. To initialize

the slave receiver mode, write any of the Slave Address registers (I2ADR0-3) and Slave

Mask registers (I2MASK0-3) and write the I²C Control Set register (I2CONSET) as shown

in Table 19–383.

Table 383. I2C0CONSET and I2C1CONSET used to configure Slave mode

Bit

7

-

6

5

4

3

2

1

-

0

-

Symbol

Value

I2EN

1

STA

0

STO

0

SI

0

AA

1

-

I2EN must be set to 1 to enable the I²C function. AA bit must be set to 1 to acknowledge

any of its own slave addresses or the General Call address. The STA, STO and SI bits are

set to 0.

After I2ADR and I2CONSET are initialized, the I²C interface waits until it is addressed by

its any of its own slave addresses or General Call address followed by the data direction

bit. If the direction bit is 0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it

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enters slave transmitter mode. After the address and direction bit have been received, the

SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to

Table 19–401 for the status codes and actions.

A/A

S

SLAVE ADDRESS

RW=0

A

DATA

A

DATA

P/Sr

n bytes data received

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

from Master to Slave

from Slave to Master

P = STOP condition

Sr = Repeated START condition

Fig 87. Format of Slave Receiver mode

6.4 Slave Transmitter mode

The first byte is received and handled as in the slave receiver mode. However, in this

mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via

SDA while the serial clock is input through SCL. START and STOP conditions are

recognized as the beginning and end of a serial transfer. In a given application, I²C may

operate as a master and as a slave. In the slave mode, the I²C hardware looks for any of

its own slave addresses and the General Call address. If one of these addresses is

detected, an interrupt is requested. When the microcontrollers wishes to become the bus

master, the hardware waits until the bus is free before the master mode is entered so that

a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the

I²C interface switches to the slave mode immediately and can detect any of its own slave

addresses in the same serial transfer.

A

S

SLAVE ADDRESS

RW=1

A

DATA

A

DATA

P

n bytes data transmitted

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

S = START condition

from Master to Slave

from Slave to Master

P = STOP condition

Fig 88. Format of Slave Transmitter mode

7. I²C implementation and operation

Figure 19–89 shows how the on-chip I²C-bus interface is implemented, and the following

text describes the individual blocks.

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7.1 Input filters and output stages

Input signals are synchronized with the internal clock, and spikes shorter than three

clocks are filtered out.

The output for I²C is a special pad designed to conform to the I²C specification.

8

ADDRESS REGISTERS

I2CnADDR0 to I2CnADDR3

MATCHALL

I2CnMMCTRL[3]

MASK REGISTERS

MASK and COMPARE

I2CnMASK0 to I2CnMASK3

INPUT

FILTER

I2CnDATABUFFER

SDA

SHIFT REGISTER

OUTPUT

STAGE

ACK

I2CnDAT

8

MONITOR MODE

REGISTER

I2CnMMCTRL

BIT COUNTER/

ARBITRATION and

SYNC LOGIC

PCLK

INPUT

FILTER

TIMING and

CONTROL

LOGIC

SCL

OUTPUT

STAGE

SERIAL CLOCK

GENERATOR

interrupt

CONTROL REGISTER and

SCL DUTY CYLE REGISTERS

I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL

16

status

bus

STATUS

DECODER

STATUS REGISTER

I2CnSTAT

8

Fig 89. I²C serial interface block diagram

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7.2 Address Registers, I2ADR0 to I2ADR3

These registers may be loaded with the 7-bit slave address (7 most significant bits) to

which the I²C block will respond when programmed as a slave transmitter or receiver. The

LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave

addresses are enabled, the actual address received may be read from the I2DAT register

at the state where the “own slave address” has just been received.

Remark: in the remainder of this chapter, when the phrase “own slave address” is used, it

refers to any of the four configured slave addresses after address masking.

7.3 Address mask registers, I2MASK0 to I2MASK3

The four mask registers each contain seven active bits (7:1). Any bit in these registers

which is set to ‘1’ will cause an automatic compare on the corresponding bit of the

received address when it is compared to the I2ADRn register associated with that mask

register. In other words, bits in an I2ADRn register which are masked are not taken into

account in determining an address match.

When an address-match interrupt occurs, the processor will have to read the data register

(I2DAT) to determine which received address actually caused the match.

7.4 Comparator

The comparator compares the received 7-bit slave address with any of the four configured

slave addresses in I2ADR0 through I2ADR3 after masking. It also compares the first

received 8-bit byte with the General Call address (0x00). If an a match is found, the

appropriate status bits are set and an interrupt is requested.

7.5 Shift register, I2DAT

This 8-bit register contains a byte of serial data to be transmitted or a byte which has just

been received. Data in I2DAT is always shifted from right to left; the first bit to be

transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received

data is located at the MSB of I2DAT. While data is being shifted out, data on the bus is

simultaneously being shifted in; I2DAT always contains the last byte present on the bus.

Thus, in the event of lost arbitration, the transition from master transmitter to slave

receiver is made with the correct data in I2DAT.

7.6 Arbitration and synchronization logic

In the master transmitter mode, the arbitration logic checks that every transmitted logic 1

actually appears as a logic 1 on the I²C-bus. If another device on the bus overrules a logic

1 and pulls the SDA line low, arbitration is lost, and the I²C block immediately changes

from master transmitter to slave receiver. The I²C block will continue to output clock

pulses (on SCL) until transmission of the current serial byte is complete.

Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode

can only occur while the I²C block is returning a “not acknowledge: (logic 1) to the bus.

Arbitration is lost when another device on the bus pulls this signal low. Since this can

occur only at the end of a serial byte, the I²C block generates no further clock pulses.

Figure 19–90 shows the arbitration procedure.

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(1)

1

(1)

2

(2)

3

(3)

SDA line

SCL line

4

8

9

ACK

(1) Another device transmits serial data.

(2) Another device overrules a logic (dotted line) transmitted this I²C master by pulling the SDA line

low. Arbitration is lost, and this I²C enters Slave Receiver mode.

(3) This I²C is in Slave Receiver mode but still generates clock pulses until the current byte has been

transmitted. This I²C will not generate clock pulses for the next byte. Data on SDA originates from

the new master once it has won arbitration.

Fig 90. Arbitration procedure

The synchronization logic will synchronize the serial clock generator with the clock pulses

on the SCL line from another device. If two or more master devices generate clock pulses,

the “mark” duration is determined by the device that generates the shortest “marks,” and

the “space” duration is determined by the device that generates the longest “spaces”.

Figure 19–91 shows the synchronization procedure.

SDA line

(1)

(3)

(1)

SCL line

(2)

high

low

period

(1) Another device pulls the SCL line low before this I²C has timed a complete high time. The other

device effectively determines the (shorter) HIGH period.

(2) Another device continues to pull the SCL line low after this I²C has timed a complete low time and

released SCL. The I²C clock generator is forced to wait until SCL goes HIGH. The other device

effectively determines the (longer) LOW period.

(3) The SCL line is released , and the clock generator begins timing the HIGH time.

Fig 91. Serial clock synchronization

A slave may stretch the space duration to slow down the bus master. The space duration

may also be stretched for handshaking purposes. This can be done after each bit or after

a complete byte transfer. the I²C block will stretch the SCL space duration after a byte has

been transmitted or received and the acknowledge bit has been transferred. The serial

interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is

cleared.

7.7 Serial clock generator

This programmable clock pulse generator provides the SCL clock pulses when the I²C

block is in the master transmitter or master receiver mode. It is switched off when the I²C

block is in a slave mode. The I²C output clock frequency and duty cycle is programmable

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via the I²C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH

registers for details. The output clock pulses have a duty cycle as programmed unless the

bus is synchronizing with other SCL clock sources as described above.

7.8 Timing and control

The timing and control logic generates the timing and control signals for serial byte

handling. This logic block provides the shift pulses for I2DAT, enables the comparator,

generates and detects START and STOP conditions, receives and transmits acknowledge

bits, controls the master and slave modes, contains interrupt request logic, and monitors

the I²C-bus status.

7.9 Control register, I2CONSET and I2CONCLR

The I²C control register contains bits used to control the following I²C block functions: start

and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,

and acknowledgment.

The contents of the I²C control register may be read as I2CONSET. Writing to I2CONSET

will set bits in the I²C control register that correspond to ones in the value written.

Conversely, writing to I2CONCLR will clear bits in the I²C control register that correspond

to ones in the value written.

7.10 Status decoder and status register

The status decoder takes all of the internal status bits and compresses them into a 5-bit

code. This code is unique for each I²C-bus status. The 5-bit code may be used to

generate vector addresses for fast processing of the various service routines. Each

service routine processes a particular bus status. There are 26 possible bus states if all

four modes of the I²C block are used. The 5-bit status code is latched into the five most

significant bits of the status register when the serial interrupt flag is set (by hardware) and

remains stable until the interrupt flag is cleared by software. The three least significant bits

of the status register are always zero. If the status code is used as a vector to service

routines, then the routines are displaced by eight address locations. Eight bytes of code is

sufficient for most of the service routines (see the software example in this section).

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8. Register description

Each I²C interface contains 16 registers as shown in Table 19–384 below.

Remark: In the LPC17xx, the following registers have been added to support response to

multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To 3,

MMCTRL, and I2DATA_BUFFER.

Table 384. I²C register map

Generic

Name

Description

Access Reset I²Cn Name & Address

value^[1]

I2CONSET I²C Control Set Register. When a one is written to R/W

a bit of this register, the corresponding bit in the I²C

control register is set. Writing a zero has no effect on

the corresponding bit in the I²C control register.

0x00

I2C0CONSET - 0x4001 C000

I2C1CONSET - 0x4005 C000

I2C2CONSET - 0x400A 0000

I2STAT

I²C Status Register. During I²C operation, this

register provides detailed status codes that allow

software to determine the next action needed.

RO

0xF8

0x00

I2C0STAT - 0x4001 C004

I2C1STAT - 0x4005 C004

I2C2STAT - 0x400A 0004

I2C0DAT - 0x4001 C008

I2C1DAT - 0x4005 C008

I2C2DAT - 0x400A 0008

I2DAT

I²C Data Register. During master or slave transmit R/W

mode, data to be transmitted is written to this

register. During master or slave receive mode, data

that has been received may be read from this

register.

I2ADR0

I²C Slave Address Register 0. Contains the 7-bit

slave address for operation of the I²C interface in

slave mode, and is not used in master mode. The

least significant bit determines whether a slave

responds to the General Call address.

R/W

0x00

I2C0ADR0 - 0x4001 C00C

I2C1ADR0 - 0x4005 C00C

I2C2ADR0 - 0x400A 000C

I2SCLH

I2SCLL

SCH Duty Cycle Register High Half Word.

R/W

0x04

I2C0SCLH - 0x4001 C010

I2C1SCLH - 0x4005 C010

I2C2SCLH - 0x400A 0010

I2C0SCLL - 0x4001 C014

I2C1SCLL - 0x4005 C014

I2C2SCLL - 0x400A 0014

Determines the high time of the I²C clock.

SCL Duty Cycle Register Low Half Word.

Determines the low time of the I²C clock. I2nSCLL

and I2nSCLH together determine the clock

frequency generated by an I²C master and certain

times used in slave mode.

I2CONCLR I²C Control Clear Register. When a one is written WO

to a bit of this register, the corresponding bit in the

I²C control register is cleared. Writing a zero has no

effect on the corresponding bit in the I²C control

register.

NA

I2C0CONCLR - 0x4001 C018

I2C1CONCLR - 0x4005 C018

I2C2CONCLR - 0x400A 0018

MMCTRL

Monitor mode control register.

R/W

0x00

I2C0MMCTRL - 0x4001 C01C

I2C1MMCTRL - 0x4005 C01C

I2C2MMCTRL - 0x400A 001C

I2C0ADR1 - 0x4001 C020

I2C1ADR1 - 0x4005 C020

I2C2ADR1 - 0x400A 0020

I2ADR1

I²C Slave Address Register 1. Contains the 7-bit

slave address for operation of the I²C interface in

slave mode, and is not used in master mode. The

least significant bit determines whether a slave

responds to the General Call address.

R/W

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Table 384. I²C register map

Generic

Name

Description

Access Reset I²Cn Name & Address

value^[1]

I2ADR2

I²C Slave Address Register 2. Contains the 7-bit

slave address for operation of the I²C interface in

slave mode, and is not used in master mode. The

least significant bit determines whether a slave

responds to the General Call address.

R/W

0x00

I2C0ADR2 - 0x4001 C024

I2C1ADR2 - 0x4005 C024

I2C2ADR2 - 0x400A 0024

I2ADR3

I²C Slave Address Register 3. Contains the 7-bit

slave address for operation of the I²C interface in

slave mode, and is not used in master mode. The

least significant bit determines whether a slave

responds to the General Call address.

R/W

0x00

I2C0ADR3 - 0x4001 C028

I2C1ADR3 - 0x4005 C028

I2C2ADR3 - 0x400A 0028

I2DATA_

BUFFER

Data buffer register. The contents of the 8 MSBs of RO

the I2DAT shift register will be transferred to the

I2DATA_BUFFER automatically after every 9 bits (8

bits of data plus ACK or NACK) has been received

on the bus.

I²C Slave address mask register 0. This mask

register is associated with I2ADR0 to determine an

address match. The mask register has no effect

when comparing to the General Call address

(‘0000000’).

I²C Slave address mask register 1. This mask

register is associated with I2ADR0 to determine an

address match. The mask register has no effect

when comparing to the General Call address

(‘0000000’).

I²C Slave address mask register 2. This mask

register is associated with I2ADR0 to determine an

address match. The mask register has no effect

when comparing to the General Call address

(‘0000000’).

I2C0DATA_ BUFFER - 0x4001 C02C

I2C1DATA_ BUFFER - 0x4005 C02C

I2C2DATA_ BUFFER - 0x400A 002C

I2MASK0

I2MASK1

I2MASK2

I2MASK3

R/W

I2C0MASK0 - 0x4001 C030

I2C1MASK0 - 0x4005 C030

I2C2MASK0 - 0x400A 0030

I2C0MASK1 - 0x4001 C034

I2C1MASK1 - 0x4005 C034

I2C2MASK1 - 0x400A 0034

I2C0MASK2 - 0x4001 C038

I2C1MASK2 - 0x4005 C038

I2C2MASK2 - 0x400A 0038

I²C Slave address mask register 3. This mask

register is associated with I2ADR0 to determine an

address match. The mask register has no effect

when comparing to the General Call address

(‘0000000’).

I2C0MASK3 - 0x4001 C03C

I2C1MASK3 - 0x4005 C03C

I2C2MASK3 - 0x400A 003C

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

8.1 I²C Control Set register (I2CONSET: I²C0, I2C0CONSET -

0x4001 C000; I²C1, I2C1CONSET - 0x4005 C000; I²C2, I2C2CONSET -

0x400A 0000)

The I2CONSET registers control setting of bits in the I2CON register that controls

operation of the I²C interface. Writing a one to a bit of this register causes the

corresponding bit in the I²C control register to be set. Writing a zero has no effect.

Reading this register provides the current values of the control and flag bits.

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Table 385. I²C Control Set register (I2CONSET: I²C0, I2C0CONSET - address 0x4001 C000,

I²C1, I2C1CONSET - address 0x4005 C000, I²C2, I2C2CONSET - address

0x400A 0000) bit description

Bit

Symbol Description

Reset

value

1:0

-

Reserved. User software should not write ones to reserved bits. The

NA

value read from a reserved bit is not defined.

Assert acknowledge flag.

I²C interrupt flag.

2

AA

SI

0

3

0

4

STO

STA

I2EN

-

STOP flag.

0

5

START flag.

I²C interface enable.

0

6

0

31:7

Reserved. User software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

I2EN I²C Interface Enable. When I2EN is 1, the I²C interface is enabled. I2EN can be

cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I²C

interface is disabled.

When I2EN is “0”, the SDA and SCL input signals are ignored, the I²C block is in the “not

addressed” slave state, and the STO bit is forced to “0”.

I2EN should not be used to temporarily release the I²C-bus since, when I2EN is reset, the

I²C-bus status is lost. The AA flag should be used instead.

STA is the START flag. Setting this bit causes the I²C interface to enter master mode and

transmit a START condition or transmit a repeated START condition if it is already in

master mode.

When STA is 1 and the I²C interface is not already in master mode, it enters master mode,

checks the bus and generates a START condition if the bus is free. If the bus is not free, it

waits for a STOP condition (which will free the bus) and generates a START condition

after a delay of a half clock period of the internal clock generator. If the I²C interface is

already in master mode and data has been transmitted or received, it transmits a repeated

START condition. STA may be set at any time, including when the I²C interface is in an

addressed slave mode.

STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is

0, no START condition or repeated START condition will be generated.

If STA and STO are both set, then a STOP condition is transmitted on the I²C-bus if it the

interface is in master mode, and transmits a START condition thereafter. If the I²C

interface is in slave mode, an internal STOP condition is generated, but is not transmitted

on the bus.

STO is the STOP flag. Setting this bit causes the I²C interface to transmit a STOP

condition in master mode, or recover from an error condition in slave mode. When STO is

1 in master mode, a STOP condition is transmitted on the I²C-bus. When the bus detects

the STOP condition, STO is cleared automatically.

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In slave mode, setting this bit can recover from an error condition. In this case, no STOP

condition is transmitted to the bus. The hardware behaves as if a STOP condition has

been received and it switches to “not addressed” slave receiver mode. The STO flag is

cleared by hardware automatically.

SI is the I²C Interrupt Flag. This bit is set when the I²C state changes. However, entering

state F8 does not set SI since there is nothing for an interrupt service routine to do in that

case.

While SI is set, the low period of the serial clock on the SCL line is stretched, and the

serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.

SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register. The SI bit

should be cleared only after the required bit(s) has (have) been set and the value in I2DAT

has been loaded or read.

AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)

will be returned during the acknowledge clock pulse on the SCL line on the following

situations:

1. A matching address defined by registers I2ADR0 through I2ADR3, masked by

I2MASK0 though I2MASK3, has been received.

2. The General Call address has been received while the General Call bit (GC) in I2ADR

is set.

3. A data byte has been received while the I²C is in the master receiver mode.

4. A data byte has been received while the I²C is in the addressed slave receiver mode

The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA

is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge

clock pulse on the SCL line on the following situations:

1. A data byte has been received while the I²C is in the master receiver mode.

2. A data byte has been received while the I²C is in the addressed slave receiver mode.

8.2 I²C Control Clear register (I2CONCLR: I²C0, I2C0CONCLR -

0x4001 C018; I²C1, I2C1CONCLR - 0x4005 C018; I²C2, I2C2CONCLR -

0x400A 0018)

The I2CONCLR registers control clearing of bits in the I2CON register that controls

operation of the I²C interface. Writing a one to a bit of this register causes the

corresponding bit in the I²C control register to be cleared. Writing a zero has no effect.

I2CONCLR is a write-only register. The value of the related bits can be read from the

I2CONSET register.

Table 386. I²C Control Clear register (I2CONCLR: I²C0, I2C0CONCLR - 0x4001 C018; I²C1,

I2C1CONCLR - 0x4005 C018; I²C2, I2C2CONCLR - 0x400A 0018) bit description

Bit

Symbol Description

1:0

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

Assert acknowledge Clear bit.

I²C interrupt Clear bit.

2

3

AAC

SIC

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Table 386. I²C Control Clear register (I2CONCLR: I²C0, I2C0CONCLR - 0x4001 C018; I²C1,

I2C1CONCLR - 0x4005 C018; I²C2, I2C2CONCLR - 0x400A 0018) bit description

Bit

Symbol Description

4

-

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

5

STAC

I2ENC

-

START flag Clear bit.

I²C interface Disable bit.

6

31:7

Reserved. User software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the

I2CONSET register. Writing 0 has no effect.

SIC is the I²C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET

register. Writing 0 has no effect.

STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the

I2CONSET register. Writing 0 has no effect.

I2ENC is the I²C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the

I2CONSET register. Writing 0 has no effect.

8.3 I²C Status register (I2STAT: I²C0, I2C0STAT - 0x4001 C004; I²C1,

I2C1STAT - 0x4005 C004; I²C2, I2C2STAT - 0x400A 0004)

Each I²C Status register reflects the condition of the corresponding I²C interface. The I²C

Status register is read-only.

Table 387. I²C Status register (I2STAT: I²C0, I2C0STAT - 0x4001 C004; I²C1, I2C1STAT -

0x4005 C004; I²C2, I2C2STAT - 0x400A 0004) bit description

Bit

Symbol Description

Reset

value

2:0

-

These bits are unused and are always 0.

0

7:3

Status

-

These bits give the actual status information about the I²C interface.

0x1F

NA

31:8

Reserved. The value read from a reserved bit is not defined.

The three least significant bits are always 0. Taken as a byte, the status register contents

represent a status code. There are 26 possible status codes. When the status code is

0xF8, there is no relevant information available and the SI bit is not set. All other 25 status

codes correspond to defined I²C states. When any of these states entered, the SI bit will

be set. For a complete list of status codes, refer to tables from Table 19–399 to

Table 19–402.

8.4 I²C Data register (I2DAT: I²C0, I2C0DAT - 0x4001 C008; I²C1, I2C1DAT -

0x4005 C008; I²C2, I2C2DAT - 0x400A 0008)

This register contains the data to be transmitted or the data just received. The CPU can

read and write to this register only while it is not in the process of shifting a byte, when the

SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is

always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a

byte has been received, the first bit of received data is located at the MSB of I2DAT.

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Table 388. I²C Data register (I2DAT: I²C0, I2C0DAT - 0x4001 C008; I²C1, I2C1DAT -

0x4005 C008; I²C2, I2C2DAT - 0x400A 0008) bit description

Bit

Symbol Description

Reset

value

7:0

Data

-

This register holds data values that have been received or are to be

transmitted.

0

31:8

Reserved. User software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

8.5 I²C Monitor mode control register (I2MMCTRL: I²C0, I2C0MMCTRL -

0x4001 C01C; I²C1, I2C1MMCTRL- 0x4005 C01C; I²C2, I2C2MMCTRL-

0x400A 001C)

This register controls the Monitor mode which allows the I²C module to monitor traffic on

the I²C-bus without actually participating in traffic or interfering with the I²C-bus.

Table 389. I²C Monitor mode control register (I2MMCTRL: I²C0, I2C0MMCTRL - 0x4001 C01C;

I²C1, I2C1MMCTRL- 0x4005 C01C; I²C2, I2C2MMCTRL- 0x400A 001C) bit

description

Bit

Symbol

Value Description

Reset

value

0

MM_ENA

Monitor mode enable.

0

1

Monitor mode disabled.

The I²C module will enter monitor mode. In this mode the

SDA output will be put in high impedance mode. This

prevents the I²C module from outputting data of any kind

(including ACK) onto the I²C data bus.

Depending on the state of the ENA_SCL bit, the output may

be also forced high, preventing the module from having

control over the I²C clock line.

1

ENA_SCL

SCL output enable.

0

1

When this bit is cleared to ‘0’, the SCL output will be forced

high when the module is in monitor mode. As described

above, this will prevent the module from having any control

over the I²C clock line.

When this bit is set, the I²C module may exercise the same

control over the clock line that it would in normal operation.

This means that, acting as a slave peripheral, the I²C

module can “stretch” the clock line (hold it low) until it has

had time to respond to an I²C interrupt.^[1]

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Table 389. I²C Monitor mode control register (I2MMCTRL: I²C0, I2C0MMCTRL - 0x4001 C01C;

I²C1, I2C1MMCTRL- 0x4005 C01C; I²C2, I2C2MMCTRL- 0x400A 001C) bit

description

Bit

Symbol

Value Description

Reset

value

2

MATCH_ALL

Select interrupt register match.

0

1

When this bit is cleared, an interrupt will only be generated

when a match occurs to one of the (up-to) four address

registers, I2ADR0 through I2ADR3. That is, the module will

respond as a normal slave as far as address-recognition is

concerned.

When this bit is set to ‘1’ and the I²C is in monitor mode, an

interrupt will be generated on ANY address received. This

will enable the part to monitor all traffic on the bus.

31:3

-

Reserved. User software should not write ones to reserved NA

bits. The value read from a reserved bit is not defined.

[1] When the ENA_SCL bit is cleared and the I²C no longer has the ability to stretch the clock, interrupt

response time becomes important. To give the part more time to respond to an I²C interrupt under these

conditions, an I2DATA_BUFFER register is used (Section 19–8.6) to hold received data for a full 9-bit word

transmission time.

Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if

the module is NOT in monitor mode).

8.5.1 Interrupt in Monitor mode

All interrupts will occur as normal when the module is in monitor mode. This means that

the first interrupt will occur when an address-match is detected (any address received if

the MATCH_ALL bit is set, otherwise an address matching one of the four address

registers).

Subsequent to an address-match detection, interrupts will be generated after each data

byte is received for a slave-write transfer, or after each byte that the module believes it

has transmitted for a slave-read transfer. In this second case, the data register will actually

contain data transmitted by some other slave on the bus which was actually addressed by

the master.

Following all of these interrupts, the processor may read the data register to see what was

actually transmitted on the bus.

8.5.2 Loss of arbitration in Monitor mode

In monitor mode, the I²C module will not be able to respond to a request for information by

the bus master or issue an ACK. Some other slave on the bus will respond instead.

Software should be aware of the fact that the module is in monitor mode and should not

respond to any loss of arbitration state that is detected.

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8.6 I²C Data buffer register (I2DATA_BUFFER: I²C0, I2CDATA_BUFFER -

0x4001 C02C; I²C1, I2C1DATA_BUFFER- 0x4005 C02C; I²C2,

I2C2DATA_BUFFER- 0x400A 002C)

In monitor mode, the I²C module may lose the ability to stretch the clock if the ENA_SCL

bit is not set. This means that the processor will have a limited amount of time to read the

contents of the data received on the bus. If the processor reads the I2DAT shift register, as

it ordinarily would, it could have only one bit-time to respond to the interrupt before the

received data is overwritten by new data.

To give the processor more time to respond, a new 8-bit, read-only I2DATA_BUFFER

register will be added. The contents of the 8 MSBs of the I2DAT shift register will be

transferred to the I2DATA_BUFFER automatically after every 9 bits (8 bits of data plus

ACK or NACK) has been received on the bus. This means that the processor will have 9

bit transmission times to respond to the interrupt and read the data before it is overwritten.

The processor will still have the ability to read I2DAT directly, as usual, and the behavior of

I2DAT will not be altered in any way.

Although the I2DATA_BUFFER register is primarily intended for use in monitor mode with

the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of

operation.

Table 390. I²C Data buffer register (I2DATA_BUFFER: I²C0, I2CDATA_BUFFER -

0x4001 C02C; I²C1, I2C1DATA_BUFFER- 0x4005 C02C; I²C2, I2C2DATA_BUFFER-

0x400A 002C) bit description

Bit

Symbol Description

Reset

value

7:0

Data

-

This register holds contents of the 8 MSBs of the I2DAT shift register.

Reserved. The value read from a reserved bit is not defined.

0

31:8

NA

8.7 I²C Slave Address registers (I2ADR0 to 3: I²C0, I2C0ADR[0, 1, 2, 3]-

0x4001 C0[0C, 20, 24, 28]; I²C1, I2C1ADR[0, 1, 2, 3] - address

0x4005 C0[0C, 20, 24, 28]; I²C2, I2C2ADR[0, 1, 2, 3] - address

0x400A 00[0C, 20, 24, 28])

These registers are readable and writable and are only used when an I²C interface is set

to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the

General Call bit. When this bit is set, the General Call address (0x00) is recognized.

If these registers contain 0x00, the I²C will not acknowledge any address on the bus. All

four registers will be cleared to this disabled state on reset.

Table 391. I²C Slave Address registers (I2ADR0 to 3: I²C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C,

20, 24, 28]; I²C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I²C2,

I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description

Bit

Symbol

Description

Reset

value

0

GC

General Call enable bit.

0

7:1

31:8

Address

-

The I²C device address for slave mode.

0x00

NA

Reserved. User software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

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8.8 I²C Mask registers (I2MASK0 to 3: I²C0, I2C0MASK[0, 1, 2, 3] -

0x4001 C0[30, 34, 38, 3C]; I²C1, I2C1MASK[0, 1, 2, 3] - address

0x4005 C0[30, 34, 38, 3C]; I²C2, I2C2MASK[0, 1, 2, 3] - address

0x400A 00[30, 34, 38, 3C])

The four mask registers each contain seven active bits (7:1). Any bit in these registers

which is set to ‘1’ will cause an automatic compare on the corresponding bit of the

received address when it is compared to the I2ADRn register associated with that mask

register. In other words, bits in an I2ADRn register which are masked are not taken into

account in determining an address match.

The mask register has no effect on comparison to the General Call address (“0000000”).

When an address-match interrupt occurs, the processor will have to read the data register

(I2DAT) to determine which received address actually caused the match.

Table 392. I²C Mask registers (I2MASK0 to 3: I²C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34,

38, 3C]; I²C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I²C2,

I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit description

Bit

Symbol Description

Reset

value

0

-

Reserved. User software should not write ones to reserved bits. This bit

0

reads always back as 0.

7:1

MASK

-

Mask bits.

0x00

0

31:8

Reserved. User software should not write ones to reserved bits. These

bits read always back as zeroes.

8.9 I²C SCL HIGH duty cycle register (I2SCLH: I²C0, I2C0SCLH -

0x4001 C010; I²C1, I2C1SCLH - 0x4005 C010; I²C2, I2C2SCLH -

0x400A 0010)

Table 393. I²C SCL HIGH Duty Cycle register (I2SCLH: I²C0, I2C0SCLH - address

0x4001 C010; I²C1, I2C1SCLH - address 0x4005 C010; I²C2, I2C2SCLH -

0x400A 0010) bit description

Bit

Symbol Description

Reset value

0x0004

NA

15:0 SCLH

31:16 -

Count for SCL HIGH time period selection.

Reserved. The value read from a reserved bit is not defined.

8.10 I²C SCL Low duty cycle register (I2SCLL: I²C0 - I2C0SCLL:

0x4001 C014; I²C1 - I2C1SCLL: 0x4005 C014; I²C2 - I2C2SCLL:

0x400A 0014)

Table 394. I²C SCL Low duty cycle register (I2SCLL: I²C0 - I2C0SCLL: 0x4001 C014; I²C1 -

I2C1SCLL: 0x4005 C014; I²C2 - I2C2SCLL: 0x400A 0014) bit description

Bit

Symbol Description

Reset value

0x0004

NA

15:0 SCLL

31:16 -

Count for SCL low time period selection.

Reserved. The value read from a reserved bit is not defined.

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8.11 Selecting the appropriate I²C data rate and duty cycle

Software must set values for the registers I2SCLH and I2SCLL to select the appropriate

data rate and duty cycle. I2SCLH defines the number of PCLK_I2C cycles for the SCL

HIGH time, I2SCLL defines the number of PCLK_I2C cycles for the SCL low time. The

frequency is determined by the following formula (PCLK_I2C is the frequency of the

peripheral bus APB):

(11)

PCLKI2C

I2CSCLH + I2CSCLL

2

I C_bitfrequency

=

--------------------------------------------------------

The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate

I²C data rate range. Each register value must be greater than or equal to 4. Table 19–395

gives some examples of I²C-bus rates based on PCLK_I2C frequency and I2SCLL and

I2SCLH values.

Table 395. Example I²C clock rates

I2SCLL + I2SCLH values at PCLK_I2C (MHz)

I²C Rate

6

8

10

12

16

20

30

40

50

60

70

80

90

100

100 kHz

(Standard)

60

80

100

120

160

200

300

400

500

600

700

800

900 1000

400 kHz

(Fast Mode)

15

-

20

8

25

10

30

12

40

16

50

20

75

30

100

40

125

50

150

60

175

70

200

80

225

90

250

100

1 MHz (Fast

Mode Plus)

I2SCLL and I2SCLH values should not necessarily be the same. Software can set

different duty cycles on SCL by setting these two registers. For example, the I²C-bus

specification defines the SCL low time and high time at different values for a Fast Mode

and Fast Mode Plus I²C.

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9. Details of I²C operating modes

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave Receiver

• Slave Transmitter

Data transfers in each mode of operation are shown in Figure 19–92, Figure 19–93,

Figure 19–94, Figure 19–95, and Figure 19–96. Table 19–396 lists abbreviations used in

these figures when describing the I²C operating modes.

Table 396. Abbreviations used to describe an I²C operation

Abbreviation

Explanation

S

START condition

SLA

R

7-bit slave address

Read bit (HIGH level at SDA)

Write bit (LOW level at SDA)

Acknowledge bit (LOW level at SDA)

Not acknowledge bit (HIGH level at SDA)

8-bit data byte

W

A

Data

P

STOP condition

Sr

Repeated START condition

In Figure 19–92 to Figure 19–96, circles are used to indicate when the serial interrupt flag

is set. The numbers in the circles show the status code held in the I2STAT register. At

these points, a service routine must be executed to continue or complete the serial

transfer. These service routines are not critical since the serial transfer is suspended until

the serial interrupt flag is cleared by software.

When a serial interrupt routine is entered, the status code in I2STAT is used to branch to

the appropriate service routine. For each status code, the required software action and

details of the following serial transfer are given in tables from Table 19–399 to

Table 19–403.

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9.1 Master Transmitter mode

In the master transmitter mode, a number of data bytes are transmitted to a slave receiver

(see Figure 19–92). Before the master transmitter mode can be entered, I2CON must be

initialized as follows:

Table 397. I2CONSET used to initialize Master Transmitter mode

Bit

7

-

6

5

4

3

2

1

-

0

-

Symbol

Value

I2EN

1

STA

0

STO

0

SI

0

AA

x

-

The I²C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be

set to logic 1 to enable the I²C block. If the AA bit is reset, the I²C block will not

acknowledge its own slave address or the General Call address in the event of another

device becoming master of the bus. In other words, if AA is reset, the I²C interface cannot

enter a slave mode. STA, STO, and SI must be reset.

The master transmitter mode may now be entered by setting the STA bit. The I²C logic will

now test the I²C-bus and generate a START condition as soon as the bus becomes free.

When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status

code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt

service routine to enter the appropriate state service routine that loads I2DAT with the

slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset

before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an

acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a

number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the

master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).

The appropriate action to be taken for each of these status codes is detailed in

Table 19–399. After a repeated START condition (state 0x10). The I²C block may switch

to the master receiver mode by loading I2DAT with SLA+R).

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MT

successful

transmission

S

SLA

W

A

DATA

A

P

to a Slave

Receiver

18H

28H

08H

next transfer

started with a

Repeated Start

condition

S

SLA

W

R

10H

Not

Acknowledge

received after

the Slave

address

A

P

20H

to Master

receive

mode,

entry

Not

Acknowledge

received after a

Data byte

A

P

= MR

30H

arbitration lost

in Slave

address or

Data byte

other Master

continues

other Master

continues

A OR A

38H

A OR A

38H

arbitration lost

and

addressed as

Slave

other Master

continues

A

to corresponding

states in Slave mode

68H 78H B0H

from Master to Slave

from Slave to Master

any number of data bytes and their associated Acknowledge bits

DATA

n

this number (contained in I2STA) corresponds to a defined state of the

I²C bus

Fig 92. Format and states in the Master Transmitter mode

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9.2 Master Receiver mode

In the master receiver mode, a number of data bytes are received from a slave transmitter

(see Figure 19–93). The transfer is initialized as in the master transmitter mode. When the

START condition has been transmitted, the interrupt service routine must load I2DAT with

the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then

be cleared before the serial transfer can continue.

When the slave address and the data direction bit have been transmitted and an

acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a

number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the

master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The

appropriate action to be taken for each of these status codes is detailed in Table 19–400.

After a repeated START condition (state 0x10), the I²C block may switch to the master

transmitter mode by loading I2DAT with SLA+W.

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MR

successful

transmission to

a Slave

A

S

SLA

R

A

DATA

A

DATA

P

transmitter

08H

40H

50H

58H

next transfer

started with a

Repeated Start

condition

S

SLA

R

10H

Not Acknowledge

received after the

Slave address

A

P

W

48H

to Master

transmit

mode, entry

= MT

arbitration lost in

Slave address or

Acknowledge bit

other Master

continues

other Master

continues

A OR A

38H

A

38H

arbitration lost

and addressed

as Slave

other Master

continues

A

to corresponding

states in Slave

mode

68H 78H B0H

from Master to Slave

from Slave to Master

any number of data bytes and their associated

Acknowledge bits

DATA

n

A

this number (contained in I2STA) corresponds to a defined state of

the I²C bus

Fig 93. Format and states in the Master Receiver mode

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9.3 Slave Receiver mode

In the slave receiver mode, a number of data bytes are received from a master transmitter

(see Figure 19–94). To initiate the slave receiver mode, I2CON register, the I2ADR

registers, and the I2MASK registers must be configured.

The values on the four I2ADR registers combined with the values on the four I2MASK

registers determines which address(es) the I²C block will respond to when slave functions

are enabled. See sections 7.2, 7.3, 8.7, and 8.8 for details.

Table 398. I2CONSET used to initialize Slave Receiver mode

Bit

7

-

6

5

4

3

2

1

-

0

-

Symbol

Value

I2EN

1

STA

0

STO

0

SI

0

AA

1

-

The I²C-bus rate settings do not affect the I²C block in the slave mode. I2EN must be set

to logic 1 to enable the I²C block. The AA bit must be set to enable the I²C block to

acknowledge its own slave address or the General Call address. STA, STO, and SI must

be reset.

When the I2ADR, I2MASK, and I2CON registers have been initialized, the I²C block waits

until it is addressed by its own slave address followed by the data direction bit which must

be “0” (W) for the I²C block to operate in the slave receiver mode. After its own slave

address and the W bit have been received, the serial interrupt flag (SI) is set and a valid

status code can be read from I2STAT. This status code is used to vector to a state service

routine. The appropriate action to be taken for each of these status codes is detailed in

Table 19–401. The slave receiver mode may also be entered if arbitration is lost while the

I²C block is in the master mode (see status 0x68 and 0x78).

If the AA bit is reset during a transfer, the I²C block will return a not acknowledge (logic 1)

to SDA after the next received data byte. While AA is reset, the I²C block does not

respond to its own slave address or a General Call address. However, the I²C-bus is still

monitored and address recognition may be resumed at any time by setting AA. This

means that the AA bit may be used to temporarily isolate the I²C block from the I²C-bus.

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reception of the own

Slave address and one

or more Data bytes all

are acknowledged

S

SLA

R

A

DATA

A

DATA

A

P OR S

A0H

60H

80H

last data byte

received is Not

acknowledged

A

P OR S

88H

arbitration lost as

Master and addressed

as Slave

A

68H

reception of the

General Call address

and one or more Data

bytes

A

GENERAL CALL

A

DATA

A

DATA

P OR S

A0H

70h

90h

last data byte is Not

acknowledged

A

P OR S

98h

arbitration lost as

Master and addressed

as Slave by General

Call

A

78h

from Master to Slave

from Slave to Master

DATA

n

A

any number of data bytes and their associated Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of the²IC

bus

Fig 94. Format and states in the Slave Receiver mode

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9.4 Slave Transmitter mode

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver

(see Figure 19–95). Data transfer is initialized as in the slave receiver mode. When I2ADR

and I2CON have been initialized, the I²C block waits until it is addressed by its own slave

address followed by the data direction bit which must be “1” (R) for the I²C block to

operate in the slave transmitter mode. After its own slave address and the R bit have been

received, the serial interrupt flag (SI) is set and a valid status code can be read from

I2STAT. This status code is used to vector to a state service routine, and the appropriate

action to be taken for each of these status codes is detailed in Table 19–402. The slave

transmitter mode may also be entered if arbitration is lost while the I²C block is in the

master mode (see state 0xB0).

If the AA bit is reset during a transfer, the I²C block will transmit the last byte of the transfer

and enter state 0xC0 or 0xC8. The I²C block is switched to the not addressed slave mode

and will ignore the master receiver if it continues the transfer. Thus the master receiver

receives all 1s as serial data. While AA is reset, the I²C block does not respond to its own

slave address or a General Call address. However, the I²C-bus is still monitored, and

address recognition may be resumed at any time by setting AA. This means that the AA

bit may be used to temporarily isolate the I²C block from the I²C-bus.

reception of the own

Slave address and

one or more Data

bytes all are

A

S

SLA

R

A

DATA

A

DATA

P OR S

acknowledged

A8H

B8H

C0H

arbitration lost as

Master and

A

addressed as Slave

B0H

last data byte

transmitted. Switched

to Not Addressed

Slave (AA bit in

A

ALL ONES P OR S

I2CON = “0”)

C8H

from Master to Slave

from Slave to Master

any number of data bytes and their associated

Acknowledge bits

DATA

n

A

this number (contained in I2STA) corresponds to a defined state of

the I²C bus

Fig 95. Format and states in the Slave Transmitter mode

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9.5 Detailed state tables

The following tables show detailed state information for the four I²C operating modes.

Table 399. Master Transmitter mode

I2CSTAT Status of the

Status

Code

Application software response

Next action taken by I²C hardware

I²C-bus and

hardware

To/From I2DAT

To I2CON

STA STO SI

AA

0x08

0x10

A START condition

has been transmitted. STA

Load SLA+W; clear

X

0

X

SLA+W will be transmitted; ACK bit will

be received.

A repeated START

condition has been

transmitted.

Load SLA+W or

X

0

X

As above.

Load SLA+R; Clear

STA

SLA+W will be transmitted; the I²C block

will be switched to MST/REC mode.

0x18

0x20

0x28

0x30

SLA+W has been

transmitted; ACK has

been received.

Load data byte or

0

X

Data byte will be transmitted; ACK bit will

be received.

No I2DAT action or

1

0

1

0

X

Repeated START will be transmitted.

STOP condition will be transmitted; STO

flag will be reset.

No I2DAT action

Load data byte or

1

0

1

0

X

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

SLA+W has been

transmitted; NOT

ACK has been

received.

Data byte will be transmitted; ACK bit will

be received.

No I2DAT action or

1

0

1

0

X

Repeated START will be transmitted.

STOP condition will be transmitted; STO

flag will be reset.

No I2DAT action

Load data byte or

1

0

1

0

X

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

Data byte in I2DAT

has been transmitted;

ACK has been

received.

Data byte will be transmitted; ACK bit will

be received.

No I2DAT action or

1

0

1

0

X

Repeated START will be transmitted.

STOP condition will be transmitted; STO

flag will be reset.

No I2DAT action

Load data byte or

1

0

1

0

X

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

Data byte in I2DAT

has been transmitted;

NOT ACK has been

received.

Data byte will be transmitted; ACK bit will

be received.

No I2DAT action or

1

0

1

0

X

Repeated START will be transmitted.

STOP condition will be transmitted; STO

flag will be reset.

No I2DAT action

1

0

X

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

0x38

Arbitration lost in

SLA+R/W or Data

bytes.

No I2DAT action or

No I2DAT action

0

1

0

X

I²C-bus will be released; not addressed

slave will be entered.

A START condition will be transmitted

when the bus becomes free.

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Table 400. Master Receiver mode

I2CSTAT Status of the

Status

Code

Application software response

Next action taken by I²C hardware

I²C-bus and

hardware

To/From I2DAT

To I2CON

STA STO SI

AA

0x08

0x10

A START condition

has been transmitted.

Load SLA+R

X

0

X

SLA+R will be transmitted; ACK bit will be

received.

A repeated START

condition has been

transmitted.

Load SLA+R or

Load SLA+W

X

0

X

As above.

SLA+W will be transmitted; the I²C block

will be switched to MST/TRX mode.

0x38

0x40

0x48

Arbitration lost in

NOT ACK bit.

No I2DAT action or

No I2DAT action

No I2DAT action or

No I2DAT action

No I2DAT action or

No I2DAT action

0

1

0

1

0

1

0

1

0

X

0

I²C-bus will be released; the I²C block will

enter a slave mode.

A START condition will be transmitted

when the bus becomes free.

SLA+R has been

transmitted; ACK has

been received.

Data byte will be received; NOT ACK bit

will be returned.

1

Data byte will be received; ACK bit will be

returned.

SLA+R has been

transmitted; NOT

ACK has been

received.

X

Repeated START condition will be

transmitted.

STOP condition will be transmitted; STO

flag will be reset.

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

0x50

0x58

Data byte has been

received; ACK has

been returned.

Read data byte or

Read data byte

0

1

0

1

0

1

0

Data byte will be received; NOT ACK bit

will be returned.

1

Data byte will be received; ACK bit will be

returned.

Data byte has been

received; NOT ACK

has been returned.

Read data byte or

Read data byte

X

Repeated START condition will be

transmitted.

STOP condition will be transmitted; STO

flag will be reset.

STOP condition followed by a START

condition will be transmitted; STO flag will

be reset.

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Table 401. Slave Receiver mode

I2CSTAT Status of the I²C-bus

Application software response

To/From I2DAT To I2CON

STA STO SI

Next action taken by I²C hardware

Status

Code

and hardware

AA

0x60

0x68

0x70

0x78

Own SLA+W has been

received; ACK has been or

returned.

No I2DAT action

X

0

Data byte will be received and NOT ACK

will be returned.

No I2DAT action X

1

0

1

0

1

0

1

Data byte will be received and ACK will be

returned.

Arbitration lost in

No I2DAT action

or

X

Data byte will be received and NOT ACK

will be returned.

SLA+R/W as master;

Own SLA+W has been

received, ACK returned.

No I2DAT action X

Data byte will be received and ACK will be

returned.

General Call address

(0x00) has been

received; ACK has been

returned.

No I2DAT action

or

X

Data byte will be received and NOT ACK

will be returned.

No I2DAT action X

Data byte will be received and ACK will be

returned.

Arbitration lost in

No I2DAT action

or

X

Data byte will be received and NOT ACK

will be returned.

SLA+R/W as master;

General Call address

has been received, ACK

has been returned.

No I2DAT action X

Data byte will be received and ACK will be

returned.

0x80

0x88

Previously addressed

with own SLA address;

DATA has been received;

ACK has been returned.

Read data byte

or

X

0

1

0

Data byte will be received and NOT ACK

will be returned.

Read data byte

Data byte will be received and ACK will be

returned.

Previously addressed

with own SLA; DATA

byte has been received;

NOT ACK has been

returned.

Read data byte

or

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address.

Read data byte

or

0

1

0

1

0

1

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1.

Read data byte

or

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address. A START condition will be

transmitted when the bus becomes free.

Read data byte

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1. A START condition will

be transmitted when the bus becomes

free.

0x90

Previously addressed

with General Call; DATA or

byte has been received;

Read data byte

X

0

1

Data byte will be received and NOT ACK

will be returned.

Read data byte

Data byte will be received and ACK will be

returned.

ACK has been returned.

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Table 401. Slave Receiver mode

I2CSTAT Status of the I²C-bus

Application software response

To/From I2DAT To I2CON

STA STO SI

Next action taken by I²C hardware

Status

Code

and hardware

AA

0x98

Previously addressed

Read data byte

0

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address.

with General Call; DATA or

byte has been received;

NOT ACK has been

Read data byte

or

0

1

0

1

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

returned.

I2ADR[0] = logic 1.

Read data byte

or

1

0

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address. A START condition will be

transmitted when the bus becomes free.

Read data byte

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1. A START condition will

be transmitted when the bus becomes

free.

0xA0

A STOP condition or

repeated START

condition has been

received while still

addressed as Slave

Receiver or Slave

Transmitter.

No STDAT

action or

0

1

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address.

No STDAT

action or

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1.

No STDAT

action or

1

0

1

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address. A START condition will be

transmitted when the bus becomes free.

No STDAT

action

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1. A START condition will

be transmitted when the bus becomes

free.

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Table 402. Slave Transmitter mode

I2CSTAT Status of the I²C-bus Application software response

Next action taken by I²C hardware

Status

Code

and hardware

To/From I2DAT

To I2CON

STA STO SI

AA

0xA8

0xB0

Own SLA+R has been Load data byte or

received; ACK has

X

0

Last data byte will be transmitted and ACK

bit will be received.

been returned.

Load data byte

1

0

1

Data byte will be transmitted; ACK will be

received.

Arbitration lost in

Load data byte or

Load data byte

Last data byte will be transmitted and ACK

bit will be received.

SLA+R/W as master;

Own SLA+R has been

received, ACK has

been returned.

Data byte will be transmitted; ACK bit will

be received.

0xB8

0xC0

Data byte in I2DAT has Load data byte or

been transmitted; ACK

X

0

1

0

Last data byte will be transmitted and ACK

bit will be received.

has been received.

Load data byte

Data byte will be transmitted; ACK bit will

be received.

Data byte in I2DAT has No I2DAT action

been transmitted; NOT or

ACK has been

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address.

received.

No I2DAT action

or

0

1

0

1

0

1

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1.

No I2DAT action

or

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address. A START condition will be

transmitted when the bus becomes free.

No I2DAT action

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1. A START condition will

be transmitted when the bus becomes free.

0xC8

Last data byte in

I2DAT has been

transmitted (AA = 0);

ACK has been

received.

No I2DAT action

or

0

1

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address.

No I2DAT action

or

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR[0] = logic 1.

No I2DAT action

or

1

0

Switched to not addressed SLV mode; no

recognition of own SLA or General Call

address. A START condition will be

transmitted when the bus becomes free.

No I2DAT action

01

Switched to not addressed SLV mode;

Own SLA will be recognized; General Call

address will be recognized if

I2ADR.0 = logic 1. A START condition will

be transmitted when the bus becomes free.

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9.6 Miscellaneous states

There are two I2STAT codes that do not correspond to a defined I²C hardware state (see

Table 19–403). These are discussed below.

9.6.1 I2STAT = 0xF8

This status code indicates that no relevant information is available because the serial

interrupt flag, SI, is not yet set. This occurs between other states and when the I²C block

is not involved in a serial transfer.

9.6.2 I2STAT = 0x00

This status code indicates that a bus error has occurred during an I²C serial transfer. A

bus error is caused when a START or STOP condition occurs at an illegal position in the

format frame. Examples of such illegal positions are during the serial transfer of an

address byte, a data byte, or an acknowledge bit. A bus error may also be caused when

external interference disturbs the internal I²C block signals. When a bus error occurs, SI is

set. To recover from a bus error, the STO flag must be set and SI must be cleared. This

causes the I²C block to enter the “not addressed” slave mode (a defined state) and to

clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are

released (a STOP condition is not transmitted).

Table 403. Miscellaneous States

Status

Code

(I2CSTAT)

Status of the I²C-bus Application software response

and hardware

Next action taken by I²C hardware

To/From I2DAT

To I2CON

STA STO SI

AA

0xF8

0x00

No relevant state

information available;

SI = 0.

No I2DAT action

No I2CON action

Wait or proceed current transfer.

Bus error during MST No I2DAT action

or selected slave

modes, due to an

0

1

0

X

Only the internal hardware is affected in

the MST or addressed SLV modes. In all

cases, the bus is released and the I²C

block is switched to the not addressed

SLV mode. STO is reset.

illegal START or

STOP condition. State

0x00 can also occur

when interference

causes the I²C block

to enter an undefined

state.

9.7 Some special cases

The I²C hardware has facilities to handle the following special cases that may occur

during a serial transfer:

9.7.1 Simultaneous repeated START conditions from two masters

A repeated START condition may be generated in the master transmitter or master

receiver modes. A special case occurs if another master simultaneously generates a

repeated START condition (see Figure 19–96). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

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If the I²C hardware detects a repeated START condition on the I²C-bus before generating

a repeated START condition itself, it will release the bus, and no interrupt request is

generated. If another master frees the bus by generating a STOP condition, the I²C block

will transmit a normal START condition (state 0x08), and a retry of the total serial data

transfer can commence.

9.7.2 Data transfer after loss of arbitration

Arbitration may be lost in the master transmitter and master receiver modes (see

Figure 19–90). Loss of arbitration is indicated by the following states in I2STAT; 0x38,

0x68, 0x78, and 0xB0 (see Figure 19–92 and Figure 19–93).

If the STA flag in I2CON is set by the routines which service these states, then, if the bus

is free again, a START condition (state 0x08) is transmitted without intervention by the

CPU, and a retry of the total serial transfer can commence.

9.7.3 Forced access to the I²C-bus

In some applications, it may be possible for an uncontrolled source to cause a bus

hang-up. In such situations, the problem may be caused by interference, temporary

interruption of the bus or a temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superfluous START or masks a STOP condition,

then the I²C-bus stays busy indefinitely. If the STA flag is set and bus access is not

obtained within a reasonable amount of time, then a forced access to the I²C-bus is

possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP

condition is transmitted. The I²C hardware behaves as if a STOP condition was received

and is able to transmit a START condition. The STO flag is cleared by hardware

Figure 19–97.

9.7.4 I²C-bus obstructed by a LOW level on SCL or SDA

An I²C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on

the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial

transfer is possible, and the problem must be resolved by the device that is pulling the

SCL bus line LOW.

Typically, the SDA line may be obstructed by another device on the bus that has become

out of synchronization with the current bus master by either missing a clock, or by sensing

a noise pulse as a clock. In this case, the problem can be solved by transmitting additional

clock pulses on the SCL line Figure 19–98. The I²C interface does not include a dedicated

timeout timer to detect an obstructed bus, but this can be implemented using another

timer in the system. When detected, software can force clocks (up to 9 may be required)

on SCL until SDA is released by the offending device. At that point, the slave may still be

out of synchronization, so a START should be generated to insure that all I²C peripherals

are synchronized.

9.7.5 Bus error

A bus error occurs when a START or STOP condition is detected at an illegal position in

the format frame. Examples of illegal positions are during the serial transfer of an address

byte, a data bit, or an acknowledge bit.

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The I²C hardware only reacts to a bus error when it is involved in a serial transfer either as

a master or an addressed slave. When a bus error is detected, the I²C block immediately

switches to the not addressed slave mode, releases the SDA and SCL lines, sets the

interrupt flag, and loads the status register with 0x00. This status code may be used to

vector to a state service routine which either attempts the aborted serial transfer again or

simply recovers from the error condition as shown in Table 19–403.

OTHER MASTER

CONTINUES

S

SLA

W

A

DATA

A

S

P

S

SLA

08H

18H

28H

other Master sends

repeated START earlier

retry

Fig 96. Simultaneous repeated START conditions from two masters

time limit

STA flag

STO flag

SDA line

SCL line

start

condition

Fig 97. Forced access to a busy I²C-bus

STA flag

(2)

(3)

(1)

SDA line

SCL line

start

condition

(1) Unsuccessful attempt to send a START condition.

(2) SDA line is released.

(3) Successful attempt to send a START condition. State 08H is entered.

Fig 98. Recovering from a bus obstruction caused by a LOW level on SDA

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9.8 I²C state service routines

This section provides examples of operations that must be performed by various I²C state

service routines. This includes:

• Initialization of the I²C block after a Reset.

• I²C Interrupt Service

• The 26 state service routines providing support for all four I²C operating modes.

9.8.1 Initialization

In the initialization example, the I²C block is enabled for both master and slave modes.

For each mode, a buffer is used for transmission and reception. The initialization routine

performs the following functions:

• The I2ADR registers and I2MASK registers are loaded with values to configure the

part’s own slave address(es) and the General Call bit (GC)

• The I²C interrupt enable and interrupt priority bits are set

• The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON

and the serial clock frequency (for master modes) is defined by loading the I2SCLH

and I2SCLL registers. The master routines must be started in the main program.

The I²C hardware now begins checking the I²C-bus for its own slave address and General

Call. If the General Call or the own slave address is detected, an interrupt is requested

and I2STAT is loaded with the appropriate state information.

9.8.2 I²C interrupt service

When the I²C interrupt is entered, I2STAT contains a status code which identifies one of

the 26 state services to be executed.

9.8.3 The state service routines

Each state routine is part of the I²C interrupt routine and handles one of the 26 states.

9.8.4 Adapting state services to an application

The state service examples show the typical actions that must be performed in response

to the 26 I²C state codes. If one or more of the four I²C operating modes are not used, the

associated state services can be omitted, as long as care is taken that the those states

can never occur.

In an application, it may be desirable to implement some kind of timeout during I²C

operations, in order to trap an inoperative bus or a lost service routine.

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10. Software example

10.1 Initialization routine

Example to initialize I²C Interface as a Slave and/or Master.

1. Load the I2ADR registers and I2MASK registers with values to configure the own

Slave Address, enable General Call recognition if needed.

2. Enable I²C interrupt.

3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For

Master only functions, write 0x40 to I2CONSET.

10.2 Start Master Transmit function

Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then

initiating a START.

1. Initialize Master data counter.

2. Set up the Slave Address to which data will be transmitted, and add the Write bit.

3. Write 0x20 to I2CONSET to set the STA bit.

4. Set up data to be transmitted in Master Transmit buffer.

5. Initialize the Master data counter to match the length of the message being sent.

6. Exit

10.3 Start Master Receive function

Begin a Master Receive operation by setting up the buffer, pointer, and data count, then

initiating a START.

1. Initialize Master data counter.

2. Set up the Slave Address to which data will be transmitted, and add the Read bit.

3. Write 0x20 to I2CONSET to set the STA bit.

4. Set up the Master Receive buffer.

5. Initialize the Master data counter to match the length of the message to be received.

6. Exit

10.4 I²C interrupt routine

Determine the I²C state and which state routine will be used to handle it.

1. Read the I²C status from I2STA.

2. Use the status value to branch to one of 26 possible state routines.

10.5 Non mode specific states

10.5.1 State: 0x00

Bus Error. Enter not addressed Slave mode and release bus.

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1. Write 0x14 to I2CONSET to set the STO and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.5.2 Master States

State 0x08 and State 0x10 are for both Master Transmit and Master Receive modes. The

R/W bit decides whether the next state is within Master Transmit mode or Master Receive

mode.

10.5.3 State: 0x08

A START condition has been transmitted. The Slave Address + R/W bit will now be

transmitted.

1. Write Slave Address with R/W bit to I2DAT.

2. Write 0x04 to I2CONSET to set the AA bit.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Set up Master Transmit mode data buffer.

5. Set up Master Receive mode data buffer.

6. Initialize Master data counter.

7. Exit

10.5.4 State: 0x10

A repeated START condition has been transmitted. The Slave Address + R/W bit will now

be transmitted.

1. Write Slave Address with R/W bit to I2DAT.

2. Write 0x04 to I2CONSET to set the AA bit.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Set up Master Transmit mode data buffer.

5. Set up Master Receive mode data buffer.

6. Initialize Master data counter.

7. Exit

10.6 Master Transmitter states

10.6.1 State: 0x18

Previous state was State 0x08 or State 0x10, Slave Address + Write has been transmitted,

ACK has been received. The first data byte will be transmitted.

1. Load I2DAT with first data byte from Master Transmit buffer.

2. Write 0x04 to I2CONSET to set the AA bit.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Increment Master Transmit buffer pointer.

5. Exit

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10.6.2 State: 0x20

Slave Address + Write has been transmitted, NOT ACK has been received. A STOP

condition will be transmitted.

1. Write 0x14 to I2CONSET to set the STO and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.6.3 State: 0x28

Data has been transmitted, ACK has been received. If the transmitted data was the last

data byte then transmit a STOP condition, otherwise transmit the next data byte.

1. Decrement the Master data counter, skip to step 5 if not the last data byte.

2. Write 0x14 to I2CONSET to set the STO and AA bits.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Exit

5. Load I2DAT with next data byte from Master Transmit buffer.

6. Write 0x04 to I2CONSET to set the AA bit.

7. Write 0x08 to I2CONCLR to clear the SI flag.

8. Increment Master Transmit buffer pointer

9. Exit

10.6.4 State: 0x30

Data has been transmitted, NOT ACK received. A STOP condition will be transmitted.

1. Write 0x14 to I2CONSET to set the STO and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.6.5 State: 0x38

Arbitration has been lost during Slave Address + Write or data. The bus has been

released and not addressed Slave mode is entered. A new START condition will be

transmitted when the bus is free again.

1. Write 0x24 to I2CONSET to set the STA and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.7 Master Receive states

10.7.1 State: 0x40

Previous state was State 08 or State 10. Slave Address + Read has been transmitted,

ACK has been received. Data will be received and ACK returned.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

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3. Exit

10.7.2 State: 0x48

Slave Address + Read has been transmitted, NOT ACK has been received. A STOP

condition will be transmitted.

1. Write 0x14 to I2CONSET to set the STO and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.7.3 State: 0x50

Data has been received, ACK has been returned. Data will be read from I2DAT. Additional

data will be received. If this is the last data byte then NOT ACK will be returned, otherwise

ACK will be returned.

1. Read data byte from I2DAT into Master Receive buffer.

2. Decrement the Master data counter, skip to step 5 if not the last data byte.

3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.

4. Exit

5. Write 0x04 to I2CONSET to set the AA bit.

6. Write 0x08 to I2CONCLR to clear the SI flag.

7. Increment Master Receive buffer pointer

8. Exit

10.7.4 State: 0x58

Data has been received, NOT ACK has been returned. Data will be read from I2DAT. A

STOP condition will be transmitted.

1. Read data byte from I2DAT into Master Receive buffer.

2. Write 0x14 to I2CONSET to set the STO and AA bits.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Exit

10.8 Slave Receiver states

10.8.1 State: 0x60

Own Slave Address + Write has been received, ACK has been returned. Data will be

received and ACK returned.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit

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10.8.2 State: 0x68

Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address

+ Write has been received, ACK has been returned. Data will be received and ACK will be

returned. STA is set to restart Master mode after the bus is free again.

1. Write 0x24 to I2CONSET to set the STA and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit.

10.8.3 State: 0x70

General Call has been received, ACK has been returned. Data will be received and ACK

returned.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit

10.8.4 State: 0x78

Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has

been received and ACK has been returned. Data will be received and ACK returned. STA

is set to restart Master mode after the bus is free again.

1. Write 0x24 to I2CONSET to set the STA and AA bits.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Set up Slave Receive mode data buffer.

4. Initialize Slave data counter.

5. Exit

10.8.5 State: 0x80

Previously addressed with own Slave Address. Data has been received and ACK has

been returned. Additional data will be read.

1. Read data byte from I2DAT into the Slave Receive buffer.

2. Decrement the Slave data counter, skip to step 5 if not the last data byte.

3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.

4. Exit.

5. Write 0x04 to I2CONSET to set the AA bit.

6. Write 0x08 to I2CONCLR to clear the SI flag.

7. Increment Slave Receive buffer pointer.

8. Exit

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10.8.6 State: 0x88

Previously addressed with own Slave Address. Data has been received and NOT ACK

has been returned. Received data will not be saved. Not addressed Slave mode is

entered.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.8.7 State: 0x90

Previously addressed with General Call. Data has been received, ACK has been returned.

Received data will be saved. Only the first data byte will be received with ACK. Additional

data will be received with NOT ACK.

1. Read data byte from I2DAT into the Slave Receive buffer.

2. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.

3. Exit

10.8.8 State: 0x98

Previously addressed with General Call. Data has been received, NOT ACK has been

returned. Received data will not be saved. Not addressed Slave mode is entered.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.8.9 State: 0xA0

A STOP condition or repeated START has been received, while still addressed as a

Slave. Data will not be saved. Not addressed Slave mode is entered.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

10.9 Slave Transmitter states

10.9.1 State: 0xA8

Own Slave Address + Read has been received, ACK has been returned. Data will be

transmitted, ACK bit will be received.

1. Load I2DAT from Slave Transmit buffer with first data byte.

2. Write 0x04 to I2CONSET to set the AA bit.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Set up Slave Transmit mode data buffer.

5. Increment Slave Transmit buffer pointer.

6. Exit

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10.9.2 State: 0xB0

Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read

has been received, ACK has been returned. Data will be transmitted, ACK bit will be

received. STA is set to restart Master mode after the bus is free again.

1. Load I2DAT from Slave Transmit buffer with first data byte.

2. Write 0x24 to I2CONSET to set the STA and AA bits.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Set up Slave Transmit mode data buffer.

5. Increment Slave Transmit buffer pointer.

6. Exit

10.9.3 State: 0xB8

Data has been transmitted, ACK has been received. Data will be transmitted, ACK bit will

be received.

1. Load I2DAT from Slave Transmit buffer with data byte.

2. Write 0x04 to I2CONSET to set the AA bit.

3. Write 0x08 to I2CONCLR to clear the SI flag.

4. Increment Slave Transmit buffer pointer.

5. Exit

10.9.4 State: 0xC0

Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is

entered.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit.

10.9.5 State: 0xC8

The last data byte has been transmitted, ACK has been received. Not addressed Slave

mode is entered.

1. Write 0x04 to I2CONSET to set the AA bit.

2. Write 0x08 to I2CONCLR to clear the SI flag.

3. Exit

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1. Basic configuration

The I²S interface is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCI2S.

Remark: On reset, the I²S interface is disabled (PCI2S = 0).

2. Clock: In PCLKSEL1 select PCLK_I2S, see Table 4–41.

3. Pins: Select I²S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to

PINMODE4 (see Section 8–5).

4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.

5. DMA: The I²S interface supports two DMA requests, see Table 20–411 and

Table 20–412, and Table 31–544.

2. Features

The I²S bus provides a standard communication interface for digital audio applications.

The I²S bus specification defines a 3-wire serial bus, having one data, one clock, and one

word select signal. The basic I²S connection has one master, which is always the master,

and one slave. The I²S interface on the LPC17xx provides a separate transmit and

receive channel, each of which can operate as either a master or a slave.

• The I²S input can operate in both master and slave mode.

The I²S output can operate in both master and slave mode, independent of the I²S

input.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• Versatile clocking includes independent transmit and receive fractional rate

generators, and an ability to use a single clock input or output for a 4-wire mode.

• The sampling frequency (fs) can range (in practice) from 16 to 96 kHz. (16, 22.05, 32,

44.1, 48, or 96 kHz) for audio applications.

• Separate Master Clock outputs for both transmit and receive channels support a clock

up to 512 times the I²S sampling frequency.

• Word Select period in master mode is configurable (separately for I²S input and I²S

output).

• Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for

receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the General Purpose DMA block.

• Controls include reset, stop and mute options separately for I²S input and I²S output.

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3. Description

The I²S performs serial data out via the transmit channel and serial data in via the receive

channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio

data, both for stereo and mono modes. Configuration, data access and control is

performed by a APB register set. Data streams are buffered by FIFOs with a depth of

8 words.

The I²S receive and transmit stage can operate independently in either slave or master

mode. Within the I²S module the difference between these modes lies in the word select

(WS) signal which determines the timing of data transmissions. Data words start on the

next falling edge of the transmitting clock after a WS change. In stereo mode when WS is

low left data is transmitted and right data when WS is high. In mono mode the same data

is transmitted twice, once when WS is low and again when WS is high.

• In master mode, word select is generated internally with a 9-bit counter. The half

period count value of this counter can be set in the control register.

• In slave mode, word select is input from the relevant bus pin.

• When an I²S bus is active, the word select, receive clock and transmit clock signals

are sent continuously by the bus master, while data is sent continuously by the

transmitter.

• Disabling the I²S can be done with the stop or mute control bits separately for the

transmit and receive.

• The stop bit will disable accesses by the transmit channel or the receive channel to

the FIFOs and will place the transmit channel in mute mode.

• The mute control bit will place the transmit channel in mute mode. In mute mode, the

transmit channel FIFO operates normally, but the output is discarded and replaced by

zeroes. This bit does not affect the receive channel, data reception can occur

normally.

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4. Pin descriptions

Table 404. Pin descriptions

Pin Name

Type

Description

I2SRX_CLK

Input/

Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is

Output driven by the master and received by the slave. Corresponds to the signal SCK in the I²S bus

specification.

I2SRX_WS

Input/

Receive Word Select. Selects the channel from which data is to be received. It is driven by the

Output master and received by the slave. Corresponds to the signal WS in the I²S bus specification.

WS = 0 indicates that data is being received by channel 1 (left channel).

WS = 1 indicates that data is being received by channel 2 (right channel).

I2SRX_SDA Input/

Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by the

Output receiver. Corresponds to the signal SD in the I²S bus specification.

Output Optional master clock output for the I²S receive function.

RX_MCLK

I2STX_CLK

Input/

Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit channel. It

Output is driven by the master and received by the slave. Corresponds to the signal SCK in the I²S bus

specification.

I2STX_WS

Input/

Transmit Word Select. Selects the channel to which data is being sent. It is driven by the master

Output and received by the slave. Corresponds to the signal WS in the I²S bus specification.

WS = 0 indicates that data is being sent to channel 1 (left channel).

WS = 1 indicates that data is being sent to channel 2 (right channel).

I2STX_SDA

TX_MCLK

Input/

Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the receiver.

Output Corresponds to the signal SD in the I²S bus specification.

Output Optional master clock output for the I²S transmit function.

SCK: serial clock

WS: word select

SD: serial data

TRANSMITTER

(MASTER)

RECEIVER

(SLAVE)

TRANSMITTER

(SLAVE)

RECEIVER

(MASTER)

WS: word select

SD: serial data

CONTROLLER

(MASTER)

SCK

WS

SD

TRANSMITTER

(SLAVE)

RECEIVER

(SLAVE)

SCK

WS

SD

MSB

LSB

MSB

word n-1

right channel

word n

left channel

word n+1

right channel

Fig 99. Simple I²S configurations and bus timing

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5. Register description

Table 20–405 shows the registers associated with the I²S interface and a summary of

their functions. Following the table are details for each register.

Table 405. I²S register map

Name

Description

Access Reset

Value^[1]

Address

I2SDAO

I2SDAI

Digital Audio Output Register. Contains control bits for the I²S transmit R/W

channel.

0x87E1 0x400A 8000

0x07E1 0x400A 8004

Digital Audio Input Register. Contains control bits for the I²S receive

channel.

R/W

I2STXFIFO

I2SRXFIFO

I2SSTATE

Transmit FIFO. Access register for the 8 × 32-bit transmitter FIFO.

Receive FIFO. Access register for the 8 × 32-bit receiver FIFO.

Status Feedback Register. Contains status information about the I²S

WO

RO

0

0x400A 8008

0x400A 800C

0x400A 8010

0

0x7

interface.

I2SDMA1

I2SDMA2

I2SIRQ

DMA Configuration Register 1. Contains control information for DMA

request 1.

R/W

0

0x400A 8014

0x400A 8018

0x400A 801C

0x400A 8020

0x400A 8024

0x400A 8028

DMA Configuration Register 2. Contains control information for DMA

request 2.

Interrupt Request Control Register. Contains bits that control how the

I²S interrupt request is generated.

Transmit MCLK divider. This register determines the I²S TX MCLK rate R/W

by specifying the value to divide PCLK by in order to produce MCLK.

Receive MCLK divider. This register determines the I²S RX MCLK rate R/W

by specifying the value to divide PCLK by in order to produce MCLK.

I2STXRATE

I2SRXRATE

I2STXBITRATE Transmit bit rate divider. This register determines the I²S transmit bit

rate by specifying the value to divide TX_MCLK by in order to produce

the transmit bit clock.

R/W

I2SRXBITRATE Receive bit rate divider. This register determines the I²S receive bit rate R/W

by specifying the value to divide RX_MCLK by in order to produce the

receive bit clock.

0

0x400A 802C

I2STXMODE

I2SRXMODE

Transmit mode control.

Receive mode control.

R/W

0

0x400A 8030

0x400A 8034

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

5.1 Digital Audio Output register (I2SDAO - 0x400A 8000)

The I2SDAO register controls the operation of the I²S transmit channel. The function of

bits in DAO are shown in Table 20–406.

Table 406: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

wordwidth

Selects the number of bytes in data as follows:

01

00 8-bit data

01 16-bit data

10 Reserved, do not use this setting

11 32-bit data

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Table 406: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description

Bit

Symbol

Value Description

Reset

Value

2

3

4

5

mono

stop

When 1, data is of monaural format. When 0, the data is in stereo format.

0

1

When 1, disables accesses on FIFOs, places the transmit channel in mute mode.

When 1, asynchronously resets the transmit channel and FIFO.

reset

ws_sel

When 0, the interface is in master mode. When 1, the interface is in slave mode. See

Section 20–7 for a summary of useful combinations for this bit with I2STXMODE.

14:6 ws_halfperiod

15 mute

31:16 -

Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.

When 1, the transmit channel sends only zeroes.

0x1F

1

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

5.2 Digital Audio Input register (I2SDAI - 0x400A 8004)

The I2SDAI register controls the operation of the I²S receive channel. The function of bits

in DAI are shown in Table 20–407.

Table 407: Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

wordwidth

Selects the number of bytes in data as follows:

01

00 8-bit data

01 16-bit data

10 Reserved, do not use this setting

11 32-bit data

2

3

4

5

mono

stop

When 1, data is of monaural format. When 0, the data is in stereo format.

When 1, disables accesses on FIFOs, places the transmit channel in mute mode.

When 1, asynchronously reset the transmit channel and FIFO.

0

1

reset

ws_sel

When 0, the interface is in master mode. When 1, the interface is in slave mode. See

Section 20–7 for a summary of useful combinations for this bit with I2SRXMODE.

14:6

ws_halfperiod

-

Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.

0x1F

31:15

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)

The I2STXFIFO register provides access to the transmit FIFO. The function of bits in

I2STXFIFO are shown in Table 20–408.

Table 408: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description

Bit

Symbol

Description

Reset Value

31:0 I2STXFIFO

8 × 32-bit transmit FIFO.

Level = 0

5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)

The I2SRXFIFO register provides access to the receive FIFO. The function of bits in

I2SRXFIFO are shown in Table 20–409.

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Table 409: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description

Bit

Symbol

Description

Reset Value

31:0 I2SRXFIFO

8 × 32-bit transmit FIFO.

level = 0

5.5 Status Feedback register (I2SSTATE - 0x400A 8010)

The I2SSTATE register provides status information about the I²S interface. The meaning

of bits in I2SSTATE are shown in Table 20–410.

Table 410: Status Feedback register (I2SSTATE - address 0x400A 8010) bit description

Bit

Symbol

Description

Reset

Value

0

irq

This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by

comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the I2SIRQ

register.

1

2

dmareq1

dmareq2

This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by

comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the

I2SDMA1 register.

This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by

comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the

I2SDMA2 register.

7:3

Unused

rx_level

-

Unused.

0

11:8

15:12

Reflects the current level of the Receive FIFO.

Reserved, user software should not write ones to reserved bits. The value read from a reserved NA

bit is not defined.

19:16 tx_level

31:20

Reflects the current level of the Transmit FIFO.

0

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved NA

bit is not defined.

5.6 DMA Configuration Register 1 (I2SDMA1 - 0x400A 8014)

The I2SDMA1 register controls the operation of DMA request 1. The function of bits in

I2SDMA1 are shown in Table 20–411. Refer to the General Purpose DMA Controller

chapter for details of DMA operation.

Table 411: DMA Configuration register 1 (I2SDMA1 - address 0x400A 8014) bit description

Bit

Symbol

Description

Reset

Value

0

rx_dma1_enable

When 1, enables DMA1 for I²S receive.

When 1, enables DMA1 for I²S transmit.

0

1

tx_dma1_enable

-

7:2

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

11:8

rx_depth_dma1

-

Set the FIFO level that triggers a receive DMA request on DMA1.

0

15:12

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

19:16 tx_depth_dma1

Set the FIFO level that triggers a transmit DMA request on DMA1.

0

31:20

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

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5.7 DMA Configuration Register 2 (I2SDMA2 - 0x400A 8018)

The I2SDMA2 register controls the operation of DMA request 2. The function of bits in

I2SDMA2 are shown in Table 20–406.

Table 412: DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description

Bit

Symbol

Description

Reset

Value

0

rx_dma2_enable

tx_dma2_enable

Unused

When 1, enables DMA1 for I²S receive.

When 1, enables DMA1 for I²S transmit.

Unused.

0

1

7:2

11:8

15:12

rx_depth_dma2

-

Set the FIFO level that triggers a receive DMA request on DMA2.

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

19:16 tx_depth_dma2

31:20

Set the FIFO level that triggers a transmit DMA request on DMA2.

0

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

5.8 Interrupt Request Control register (I2SIRQ - 0x400A 801C)

The I2SIRQ register controls the operation of the I²S interrupt request. The function of bits

in I2SIRQ are shown in Table 20–406.

Table 413: Interrupt Request Control register (I2SIRQ - address 0x400A 801C) bit description

Bit

Symbol

Description

Reset

Value

0

rx_Irq_enable

tx_Irq_enable

Unused

When 1, enables I²S receive interrupt.

When 1, enables I²S transmit interrupt.

Unused.

0

1

7:2

11:8

15:12

rx_depth_irq

-

Set the FIFO level on which to create an irq request.

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

19:16 tx_depth_irq

Set the FIFO level on which to create an irq request.

0

31:20

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

5.9 Transmit Clock Rate register (I2STXRATE - 0x400A 8020)

The MCLK rate for the I²S transmitter is determined by the values in the I2STXRATE

register. The required I2STXRATE setting depends on the desired audio sample rate

desired, the format (stereo/mono) used, and the data size.

The transmitter MCLK rate is generated using a fractional rate generator, dividing down

the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be

chosen to produce a frequency twice that desired for the transmitter MCLK, which must be

an integer multiple of the transmitter bit clock rate. Fractional rate generators have some

aspects that the user should be aware of when choosing settings. These are discussed in

Section 20–5.9.1. The equation for the fractional rate generator is:

I2STXMCLK = PCLK_I2S * (X/Y) /2

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Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be

greater than or equal to X.

Table 414: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description

Bit

Symbol

Description

Reset

Value

7:0

Y_divider I²S transmit MCLK rate denominator. This value is used to divide PCLK to produce the

transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of

0 stops the clock.

0

15:8

X_divider I²S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the

transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide

range of possibilities. Note: the resulting ratio X/Y is divided by 2.

0

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

5.9.1 Notes on fractional rate generators

The nature of a fractional rate generator is that there will be some output jitter with some

divide settings. This is because the fractional rate generator is a fully digital function, so

output clock transitions are synchronous with the source clock, whereas a theoretical

perfect fractional rate may have edges that are not related to the source clock. So, output

jitter will not be greater than plus or minus one source clock between consecutive clock

edges.

For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for

every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no

way to distribute the output clocks in a perfectly even fashion, so some clocks will be

longer than others. The output is divided by 2 in order to square it up, which also helps

with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a

slightly different length than their neighbors. It is possible to avoid jitter entirely by

choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.

5.10 Receive Clock Rate register (I2SRXRATE - 0x400A 8024)

The MCLK rate for the I²S receiver is determined by the values in the I2SRXRATE

register. The required I2SRXRATE setting depends on the peripheral clock rate

(PCLK_I2S) and the desired MCLK rate (such as 256 fs).

The receiver MCLK rate is generated using a fractional rate generator, dividing down the

frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be

chosen to produce a frequency twice that desired for the receiver MCLK, which must be

an integer multiple of the receiver bit clock rate. Fractional rate generators have some

aspects that the user should be aware of when choosing settings. These are discussed in

Section 20–5.9.1. The equation for the fractional rate generator is:

I2SRXMCLK = PCLK_I2S * (X/Y) /2

Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be

greater than or equal to X.

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Table 415: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description

Bit

Symbol

Description

Reset

Value

7:0

Y_divider I²S receive MCLK rate denominator. This value is used to divide PCLK to produce the

receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of

0 stops the clock.

0

15:8

X_divider I²S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the

receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide

range of possibilities. Note: the resulting ratio X/Y is divided by 2.

0

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

5.11 Transmit Clock Bit Rate register (I2STXBITRATE - 0x400A 8028)

The bit rate for the I²S transmitter is determined by the value of the I2STXBITRATE

register. The value depends on the audio sample rate desired, and the data size and

format (stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data

requires a bit rate of 48,000×16×2 = 1.536 MHz.

Table 416: Transmit Clock Rate register (I2TXBITRATE - address 0x400A 8028) bit description

Bit

Symbol

Description

Reset

Value

5:0

tx_bitrate I²S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit

clock.

0

31:6

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

5.12 Receive Clock Bit Rate register (I2SRXBITRATE - 0x400A 802C)

The bit rate for the I²S receiver is determined by the value of the I2SRXBITRATE register.

The value depends on the audio sample rate, as well as the data size and format used.

The calculation is the same as for I2SRXBITRATE.

Table 417: Receive Clock Rate register (I2SRXBITRATE - address 0x400A 802C) bit description

Bit

Symbol

Description

Reset

Value

5:0

rx_bitrate I²S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit

clock.

0

31:6

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

5.13 Transmit Mode Control register (I2STXMODE - 0x400A 8030)

The Transmit Mode Control register contains additional controls for transmit clock source,

enabling the 4-pin mode, and how MCLK is used. See Section 20–7 for a summary of

useful mode combinations.

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Table 418: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

TXCLKSEL

Clock source selection for the transmit bit clock divider.

0

00

01

10

11

Select the TX fractional rate divider clock output as the source

Reserved

Select the RX_MCLK signal as the TX_MCLK clock source

Reserved

2

3

TX4PIN

Transmit 4-pin mode selection. When 1, enables 4-pin mode.

0

TXMCENA

Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1,

output of TX_MCLK is enabled.

31:4

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

5.14 Receive Mode Control register (I2SRXMODE - 0x400A 8034)

The Receive Mode Control register contains additional controls for receive clock source,

enabling the 4-pin mode, and how MCLK is used. See Section 20–7 for a summary of

useful mode combinations.

Table 419: Receive Mode Control register (I2SRXMODE - 0x400A 8034) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

RXCLKSEL

Clock source selection for the receive bit clock divider.

0

00

01

10

11

Select the RX fractional rate divider clock output as the source

Reserved

Select the TX_MCLK signal as the RX_MCLK clock source

Reserved

2

3

RX4PIN

Receive 4-pin mode selection. When 1, enables 4-pin mode.

0

RXMCENA

Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1,

output of RX_MCLK is enabled.

31:4

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

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6. I²S transmit and receive interfaces

The I²S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio

information. Some details of I²S implementation are:

• When the FIFO is empty, the transmit channel will repeat transmitting the same data

until new data is written to the FIFO.

• When mute is true, the data value 0 is transmitted.

• When mono is false, two successive data words are respectively left and right data.

• Data word length is determined by the wordwidth value in the configuration register.

There is a separate wordwidth value for the receive channel and the transmit channel.

– 0: word is considered to contain four 8-bit data words.

– 1: word is considered to contain two 16-bit data words.

– 3: word is considered to contain one 32-bit data word.

• When the transmit FIFO contains insufficient data the transmit channel will repeat

transmitting the last data until new data is available. This can occur when the

microprocessor or the DMA at some time is unable to provide new data fast enough.

Because of this delay in new data there is a need to fill the gap, which is

accomplished by continuing to transmit the last sample. The data is not muted as this

would produce an noticeable and undesirable effect in the sound.

• The transmit channel and the receive channel only handle 32-bit aligned words, data

chunks must be clipped or extended to a multiple of 32 bits.

When switching between data width or modes the I²S must be reset via the reset bit in the

control register in order to ensure correct synchronization. It is advisable to set the stop bit

also until sufficient data has been written in the transmit FIFO. Note that when stopped

data output is muted.

All data accesses to FIFOs are 32 bits. Figure 20–112 shows the possible data

sequences.

A data sample in the FIFO consists of:

• 1×32 bits in 8-bit or 16-bit stereo modes.

• 1×32 bits in mono modes.

• 2×32 bits, first left data, second right data, in 32-bit stereo modes.

Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to

the transmit clock domain after the rising edge of WS. On the next falling edge of WS the

left data will be loaded in the shift register and transmitted and on the following rising edge

of WS the right data is loaded and transmitted.

The receive channel will start receiving data after a change of WS. When word select

becomes low it expects this data to be left data, when WS is high received data is

expected to be right data. Reception will stop when the bit counter has reached the limit

set by wordwidth. On the next change of WS the received data will be stored in the

appropriate hold register. When complete data is available it will be written into the receive

FIFO.

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7. I²S operating modes

The clocking and WS usage of the I²S interface is configurable. In addition to master and

slave modes, which are independently configurable for the transmitter and the receiver,

several different clock sources are possible, including variations that share the clock

and/or WS between the transmitter and receiver. This last option allows using I²S with

fewer pins, typically four.

Many configurations are possible that are not considered useful, the following tables and

figures give details of the configurations that are most likely to be useful.

Table 420: I²S transmit modes

I2SDAO I2STXMODE Description

[5]

[3:0]

0

0 0 0 0

Typical transmitter master mode. See Figure 20–100.

The I²S transmit function operates as a master.

The transmit clock source is the fractional rate divider.

The WS used is the internally generated TX_WS.

The TX_MCLK pin is not enabled for output.

0

0 0 1 0

0 1 0 0

1 0 0 0

Transmitter master mode sharing the receiver reference clock. See Figure 20–101.

The I²S transmit function operates as a master.

The transmit clock source is RX_REF.

The WS used is the internally generated TX_WS.

The TX_MCLK pin is not enabled for output.

4-wire transmitter master mode sharing the receiver bit clock and WS. See Figure 20–102.

The I²S transmit function operates as a master.

The transmit clock source is the RX bit clock.

The WS used is the internally generated RX_WS.

The TX_MCLK pin is not enabled for output.

Transmitter master mode with TX_MCLK output. See Figure 20–100.

The I²S transmit function operates as a master.

The transmit clock source is the fractional rate divider.

The WS used is the internally generated TX_WS.

The TX_MCLK pin is enabled for output.

1

0 0 0 0

0 0 1 0

0 1 0 0

Typical transmitter slave mode. See Figure 20–103.

The I²S transmit function operates as a slave.

The transmit clock source is the TX_CLK pin.

The WS used is the TX_WS pin.

Transmitter slave mode sharing the receiver reference clock. See Figure 20–104.

The I²S transmit function operates as a slave.

The transmit clock source is RX_REF.

The WS used is the TX_WS pin.

4-wire transmitter slave mode sharing the receiver bit clock and WS. See Figure 20–105.

The I²S transmit function operates as a slave.

The transmit clock source is the RX bit clock.

The WS used is RX_WS ref.

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I2STXMODE[3]

(Pin OE)

I2STX_MCLK

I2STX_CLK

I2STX_SDA

I2STX_RATE[15:8]

I2STX_RATE[7:0]

I2STXBITRATE[5:0]

I²S

peripheral

block

X

Y

I2S_PCLK

TX_REF

TX bit clock

8-bit

÷N

÷2

(1 to 64)

Fractional

Rate Divider

I2STX_WS

(transmit)

TX_WS ref

Fig 100. Typical transmitter master mode, with or without MCLK output

I2STX_CLK

I2STX_SDA

I2STX_WS

I2STXBITRATE[5:0]

I²S

peripheral

block

RX_REF

TX bit clock

÷N

(1 to 64)

(transmit)

TX_WS ref

Fig 101. Transmitter master mode sharing the receiver reference clock

I2STX_CLK

I²S

peripheral

block

I2STX_SDA

I2STX_WS

RX bit clock

(transmit)

RX_WS ref

Fig 102. 4-wire transmitter master mode sharing the receiver bit clock and WS

I2STX_CLK

I2STX_SDA

I2STX_WS

I2STXBITRATE[5:0]

I²S

peripheral

block

TX_REF

TX bit clock

÷N

(1 to 64)

(transmit)

Fig 103. Typical transmitter slave mode

I2STXBITRATE[5:0]

I²S

peripheral

block

I2STX_SDA

I2STX_WS

RX_REF

TX bit clock

÷N

(1 to 64)

(transmit)

Fig 104. Transmitter slave mode sharing the receiver reference clock

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I²S

peripheral

block

I2STX_SDA

I2STX_WS

RX bit clock

(transmit)

RX_WS ref

Fig 105. 4-wire transmitter slave mode sharing the receiver bit clock and WS

Table 421: I²S receive modes

I2SDAI I2SRXMODE Description

[5]

[3:0]

0

0 0 0 0

Typical receiver master mode. See Figure 20–106.

The I²S receive function operates as a master.

The receive clock source is the fractional rate divider.

The WS used is the internally generated RX_WS.

The RX_MCLK pin is not enabled for output.

0

0 0 1 0

0 1 0 0

1 0 0 0

Receiver master mode sharing the transmitter reference clock. See Figure 20–107.

The I²S receive function operates as a master.

The receive clock source is TX_REF.

The WS used is the internally generated RX_WS.

The RX_MCLK pin is not enabled for output.

4-wire receiver master mode sharing the transmitter bit clock and WS. See Figure 20–108.

The I²S receive function operates as a master.

The receive clock source is the TX bit clock.

The WS used is the internally generated TX_WS.

The RX_MCLK pin is not enabled for output.

Receiver master mode with RX_MCLK output. See Figure 20–106.

The I²S receive function operates as a master.

The receive clock source is the fractional rate divider.

The WS used is the internally generated RX_WS.

The RX_MCLK pin is enabled for output.

1

0 0 0 0

0 0 1 0

0 1 0 0

Typical receiver slave mode. See Figure 20–109.

The I²S receive function operates as a slave.

The receive clock source is the RX_CLK pin.

The WS used is the RX_WS pin.

Receiver slave mode sharing the transmitter reference clock. See Figure 20–110.

The I²S receive function operates as a slave.

The receive clock source is TX_REF.

The WS used is the RX_WS pin.

This is a 4-wire receiver slave mode sharing the transmitter bit clock and WS. See Figure 20–111.

The I²S receive function operates as a slave.

The receive clock source is the TX bit clock.

The WS used is TX_WS ref.

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I2SRXMODE[3]

(Pin OE)

I2SRX_MCLK

I2SRX_CLK

I2SRX_SDA

I2SRX_RATE[15:8]

I2SRX_RATE[7:0]

I2SRXBITRATE[5:0]

I²S

peripheral

block

X

Y

I2S_PCLK

RX_REF

RX bit clock

8-bit

÷N

÷2

(1 to 64)

Fractional

Rate Divider

I2SRX_WS

(receive)

RX_WS ref

Fig 106. Typical receiver master mode, with or without MCLK output

I2SRX_CLK

I2SRX_SDA

I2SRX_WS

I2SRXBITRATE[5:0]

I²S

peripheral

block

TX_REF

RX bit clock

÷N

(1 to 64)

(receive)

RX_WS ref

Fig 107. Receiver master mode sharing the transmitter reference clock

I2SRX_CLK

I²S

peripheral

block

I2SRX_SDA

I2SRX_WS

TX bit clock

(receive)

TX_WS ref

Fig 108. 4-wire receiver master mode sharing the transmitter bit clock and WS

I2SRX_CLK

I2SRX_SDA

I2SRX_WS

I2SRXBITRATE[5:0]

I²S

peripheral

block

RX_REF

RX bit clock

÷N

(1 to 64)

(receive)

Fig 109. Typical receiver slave mode

I2SRXBITRATE[5:0]

RX bit clock

I²S

peripheral

block

I2SRX_SDA

I2SRX_WS

TX_REF

÷N

(1 to 64)

(receive)

Fig 110. Receiver slave mode sharing the transmitter reference clock

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I²S

peripheral

block

I2SRX_SDA

I2SRX_WS

TX bit clock

(receive)

TX_WS ref

Fig 111. 4-wire receiver slave mode sharing the transmitter bit clock and WS

8. FIFO controller

Handling of data for transmission and reception is performed via the FIFO controller which

can generate two DMA requests and an interrupt request. The controller consists of a set

of comparators which compare FIFO levels with depth settings contained in registers. The

current status of the level comparators can be seen in the APB status register.

Table 422. Conditions for FIFO level comparison

Level Comparison

dmareq_tx_1

dmareq_rx_1

dmareq_tx_2

dmareq_rx_2

irq_tx

Condition

tx_depth_dma1 >= tx_level

rx_depth_dma1 <= rx_level

tx_depth_dma2 >= tx_level

rx_depth_dma2 <= rx_level

tx_depth_irq >= tx_level

rx_depth_irq <= rx_level

irq_rx

System signaling occurs when a level detection is true and enabled.

Table 423. DMA and interrupt request generation

System Signaling

irq

Condition

(irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable)

dmareq[0]

(dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &

rx_dma1_enable )

dmareq[1]

( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &

rx_dma2_enable )

Table 424. Status feedback in the I2SSTATE register

Status Feedback

irq

Status

irq_rx | irq_tx

dmareq1

dmareq2

(dmareq_tx_1 | dmareq_rx_1)

(dmareq_rx_2 | dmareq_tx_2)

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Mono 8-bit data mode

N + 3

7

N + 2

N + 1

LEFT

N

0

7

0

7

0

7

0

Stereo 8-bit data mode

LEFT + 1

7

RIGHT + 1

RIGHT

0

7

Mono 16-bit data mode

15

N + 1

LEFT

N

15

0

Stereo 16-bit data mode

15

RIGHT

0

Mono 32-bit data mode

31

N

Stereo 32-bit data mode

31

LEFT

N

0

RIGHT

N + 1

31

Fig 112. FIFO contents for various I²S modes

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User manual

1. Basic configuration

The Timer 0, 1, 2, and 3 peripherals are configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bits PCTIM0/1/2/3.

Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled

(PCTIM2/3 = 0).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_TIMER0/1; in

the PCLKSEL1 register (Table 4–41), select PCLK_TIMER2/3.

3. Pins: Select timer pins through the PINSEL registers. Select the pin modes for the

port pins with timer functions through the PINMODE registers (Section 8–5).

4. Interrupts: See register T0/1/2/3MCR (Table 21–430) and T0/1/2/3CCR

(Table 21–431) for match and capture events. Interrupts are enabled in the NVIC

using the appropriate Interrupt Set Enable register.

5. DMA: Up to two match conditions can be used to generate timed DMA requests, see

Table 31–544.

2. Features

Remark: The four Timer/Counters are identical except for the peripheral base address. A

minimum of two Capture inputs and two Match outputs are pinned out for all four timers,

with a choice of multiple pins for each. Timer 2 brings out all four Match outputs.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Counter or Timer operation

• Up to two 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set low on match.

– Set high on match.

– Toggle on match.

– Do nothing on match.

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3. Applications

• Interval Timer for counting internal events.

• Pulse Width Demodulator via Capture inputs.

• Free running timer.

4. Description

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally-supplied clock, and can optionally generate interrupts or perform other actions

at specified timer values, based on four match registers. It also includes four capture

inputs to trap the timer value when an input signal transitions, optionally generating an

interrupt.

5. Pin description

Table 21–425 gives a brief summary of each of the Timer/Counter related pins.

Table 425. Timer/Counter pin description

Type

Description

CAP0[1:0] Input

CAP1[1:0]

CAP2[1:0]

Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers

with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be

selected from a number of pins. When more than one pin is selected for a Capture input on a single

TIMER0/1 channel, the pin with the lowest Port number is used

CAP3[1:0]

Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock.

For more details see Section 21–6.3.

MAT0[1:0] Output External Match Output - When a match register (MR3:0) equals the timer counter (TC) this output can

MAT1[1:0]

MAT2[3:0]

MAT3[1:0]

either toggle, go low, go high, or do nothing. The External Match Register (EMR) controls the

functionality of this output. Match Output functionality can be selected on a number of pins in parallel.

5.1 Multiple CAP and MAT pins

Software can select from multiple pins for the CAP or MAT functions in the Pin Select

registers, which are described in Section 8–5. When more than one pin is selected for a

MAT output, all such pins are driven identically. When more than one pin is selected for a

CAP input, the pin with the lowest Port number is used. Note that match conditions may

be used internally without the use of a device pin.

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6. Register description

Each Timer/Counter contains the registers shown in Table 21–426 ("Reset Value" refers to

the data stored in used bits only; it does not include reserved bits content). More detailed

descriptions follow.

Table 426. TIMER/COUNTER0-3 register map

Generic Description

Name

Access Reset

TIMERn Register/

Value^[1]Name & Address

IR

Interrupt Register. The IR can be written to clear interrupts. The IR R/W

can be read to identify which of eight possible interrupt sources are

pending.

0

T0IR - 0x4000 4000

T1IR - 0x4000 8000

T2IR - 0x4009 0000

T3IR - 0x4009 4000

TCR

TC

Timer Control Register. The TCR is used to control the Timer

Counter functions. The Timer Counter can be disabled or reset

through the TCR.

R/W

T0TCR - 0x4000 4004

T1TCR - 0x4000 8004

T2TCR - 0x4009 0004

T3TCR - 0x4009 4004

Timer Counter. The 32-bit TC is incremented every PR+1 cycles of R/W

PCLK. The TC is controlled through the TCR.

T0TC - 0x4000 4008

T1TC - 0x4000 8008

T2TC - 0x4009 0008

T3TC - 0x4009 4008

PR

Prescale Register. When the Prescale Counter (below) is equal to R/W

this value, the next clock increments the TC and clears the PC.

T0PR - 0x4000 400C

T1PR - 0x4000 800C

T2PR - 0x4009 000C

T3PR - 0x4009 400C

PC

Prescale Counter. The 32-bit PC is a counter which is incremented R/W

to the value stored in PR. When the value in PR is reached, the TC

is incremented and the PC is cleared. The PC is observable and

controllable through the bus interface.

T0PC - 0x4000 4010

T1PC - 0x4000 8010

T2PC - 0x4009 0010

T3PC - 0x4009 4010

MCR

MR0

MR1

MR2

MR3

CCR

Match Control Register. The MCR is used to control if an interrupt is R/W

generated and if the TC is reset when a Match occurs.

T0MCR - 0x4000 4014

T1MCR - 0x4000 8014

T2MCR - 0x4009 0014

T3MCR - 0x4009 4014

Match Register 0. MR0 can be enabled through the MCR to reset

the TC, stop both the TC and PC, and/or generate an interrupt

every time MR0 matches the TC.

R/W

T0MR0 - 0x4000 4018

T1MR0 - 0x4000 8018

T2MR0 - 0x4009 0018

T3MR0 - 0x4009 4018

Match Register 1. See MR0 description.

Match Register 2. See MR0 description.

Match Register 3. See MR0 description.

T0MR1 - 0x4000 401C

T1MR1 - 0x4000 801C

T2MR1 - 0x4009 001C

T3MR1 - 0x4009 401C

T0MR2 - 0x4000 4020

T1MR2 - 0x4000 8020

T2MR2 - 0x4009 0020

T3MR2 - 0x4009 4020

T0MR3 - 0x4000 4024

T1MR3 - 0x4000 8024

T2MR3 - 0x4009 0024

T3MR3 - 0x4009 4024

Capture Control Register. The CCR controls which edges of the

capture inputs are used to load the Capture Registers and whether

or not an interrupt is generated when a capture takes place.

T0CCR - 0x4000 4028

T1CCR - 0x4000 8028

T2CCR - 0x4009 0028

T3CCR - 0x4009 4028

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Table 426. TIMER/COUNTER0-3 register map

Generic Description

Name

Access Reset

TIMERn Register/

Value^[1]Name & Address

CR0

Capture Register 0. CR0 is loaded with the value of TC when there RO

is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input.

0

T0CR0 - 0x4000 402C

T1CR0 - 0x4000 802C

T2CR0 - 0x4009 002C

T3CR0 - 0x4009 402C

CR1

Capture Register 1. See CR0 description.

RO

T0CR1 - 0x4000 4030

T1CR1 - 0x4000 8030

T2CR1 - 0x4009 0030

T3CR1 - 0x4009 4030

EMR

CTCR

External Match Register. The EMR controls the external match pins R/W

MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).

T0EMR - 0x4000 403C

T1EMR - 0x4000 803C

T2EMR - 0x4009 003C

T3EMR - 0x4009 403C

Count Control Register. The CTCR selects between Timer and

Counter mode, and in Counter mode selects the signal and edge(s)

for counting.

R/W

T0CTCR - 0x4000 4070

T1CTCR - 0x4000 8070

T2CTCR - 0x4009 0070

T3CTCR - 0x4009 4070

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000, 0x4000 8000,

0x4009 0000, 0x4009 4000)

The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture

interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.

Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the

interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match

also clears any corresponding DMA request.

Table 427. Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit

description

Bit

Symbol

Description

Reset

Value

0

MR0 Interrupt Interrupt flag for match channel 0.

MR1 Interrupt Interrupt flag for match channel 1.

MR2 Interrupt Interrupt flag for match channel 2.

MR3 Interrupt Interrupt flag for match channel 3.

CR0 Interrupt Interrupt flag for capture channel 0 event.

CR1 Interrupt Interrupt flag for capture channel 1 event.

0

-

1

2

3

4

5

31:6

-

Reserved

6.2 Timer Control Register (T[0/1/2/3]CR - 0x4000 4004, 0x4000 8004,

0x4009 0004, 0x4009 4004)

The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.

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Table 428. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004,

0x4009 4004) bit description

Bit

Symbol

Description

Reset

Value

0

Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When 1,

the counters are disabled.

0

1

Counter Reset

When one, the Timer Counter and the Prescale Counter are synchronously reset on the

next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.

0

31:2

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.3 Count Control Register (T[0/1/2/3]CTCR - 0x4000 4070, 0x4000 8070,

0x4009 0070, 0x4009 4070)

The Count Control Register (CTCR) is used to select between Timer and Counter mode,

and in Counter mode to select the pin and edge(s) for counting.

When Counter Mode is chosen as a mode of operation, the CAP input (selected by the

CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two

consecutive samples of this CAP input, one of the following four events is recognized:

rising edge, falling edge, either of edges or no changes in the level of the selected CAP

input. Only if the identified event occurs and the event corresponds to the one selected by

bits 1:0 in the CTCR register, will the Timer Counter register be incremented.

Effective processing of the externally supplied clock to the counter has some limitations.

Since two successive rising edges of the PCLK clock are used to identify only one edge

on the CAP selected input, the frequency of the CAP input can not exceed one quarter of

the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in

this case can not be shorter than 1/(2 PCLK).

Table 429. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,

0x4009 4070) bit description

Bit

Symbol Value Description

Reset

Value

1:0

Counter/

Timer

This field selects which rising PCLK edges can increment the Timer’s Prescale Counter 00

(PC), or clear the PC and increment the Timer Counter (TC).

Mode

00

Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale

Register. The Prescale Counter is incremented on every rising PCLK edge.

01

10

11

Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.

Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.

Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

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Table 429. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,

0x4009 4070) bit description

Bit

Symbol Value Description

Reset

Value

3:2

Count

Input

When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for

clocking.

00

Select

00

01

10

11

CAPn.0 for TIMERn

CAPn.1 for TIMERn

Reserved

Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits

for that input in the Capture Control Register (TnCCR) must be programmed as 000.

However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the

same timer.

31:4

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.4 Timer Counter registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008,

0x4009 0008, 0x4009 4008)

The 32-bit Timer Counter register is incremented when the prescale counter reaches its

terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will

count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.

This event does not cause an interrupt, but a match register can be used to detect an

overflow if needed.

6.5 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C,

0x4009 000C, 0x4009 400C)

The 32-bit Prescale register specifies the maximum value for the Prescale Counter.

6.6 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010,

0x4009 0010, 0x4009 4010)

The 32-bit Prescale Counter controls division of PCLK by some constant value before it is

applied to the Timer Counter. This allows control of the relationship of the resolution of the

timer versus the maximum time before the timer overflows. The Prescale Counter is

incremented on every PCLK. When it reaches the value stored in the Prescale register,

the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.

This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 pclks

when PR = 1, etc.

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6.7 Match Registers (MR0 - MR3)

The Match register values are continuously compared to the Timer Counter value. When

the two values are equal, actions can be triggered automatically. The action possibilities

are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are

controlled by the settings in the MCR register.

6.8 Match Control Register (T[0/1/2/3]MCR - 0x4000 4014, 0x4000 8014,

0x4009 0014, 0x4009 4014)

The Match Control Register is used to control what operations are performed when one of

the Match Registers matches the Timer Counter. The function of each of the bits is shown

in Table 21–430.

Table 430. Match Control Register (T[0/1/2/3]MCR - addresses 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014)

bit description

Bit

Symbol Value Description

Reset

Value

0

MR0I

1

0

1

0

1

Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.

This interrupt is disabled

0

1

2

MR0R

MR0S

Reset on MR0: the TC will be reset if MR0 matches it.

Feature disabled.

Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches

the TC.

0

1

0

1

0

1

Feature disabled.

3

4

5

MR1I

Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.

This interrupt is disabled

0

MR1R

MR1S

Reset on MR1: the TC will be reset if MR1 matches it.

Feature disabled.

Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches

the TC.

0

1

0

1

0

1

Feature disabled.

6

7

8

MR2I

Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.

This interrupt is disabled

0

MR2R

MR2S

Reset on MR2: the TC will be reset if MR2 matches it.

Feature disabled.

Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches

the TC.

0

1

0

1

0

1

Feature disabled.

9

MR3I

Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.

This interrupt is disabled

0

10

11

MR3R

MR3S

Reset on MR3: the TC will be reset if MR3 matches it.

Feature disabled.

Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches

the TC.

0

Feature disabled.

31:12 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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6.9 Capture Registers (CR0 - CR1)

Each Capture register is associated with a device pin and may be loaded with the Timer

Counter value when a specified event occurs on that pin. The settings in the Capture

Control Register register determine whether the capture function is enabled, and whether

a capture event happens on the rising edge of the associated pin, the falling edge, or on

both edges.

6.10 Capture Control Register (T[0/1/2/3]CCR - 0x4000 4028, 0x4000 8028,

0x4009 0028, 0x4009 4028)

The Capture Control Register is used to control whether one of the four Capture Registers

is loaded with the value in the Timer Counter when the capture event occurs, and whether

an interrupt is generated by the capture event. Setting both the rising and falling bits at the

same time is a valid configuration, resulting in a capture event for both edges. In the

description below, "n" represents the Timer number, 0 or 1.

Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for

that input in this register should be programmed as 000, but capture and/or interrupt can

be selected for the other 3 CAP inputs.

Table 431. Capture Control Register (T[0/1/2/3]CCR - addresses 0x4000 4028, 0x4000 8020, 0x4009 0028,

0x4009 4028) bit description

Bit

Symbol Value Description

Reset

Value

0

CAP0RE 1

Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to be

0

loaded with the contents of TC.

0

This feature is disabled.

1

CAP0FE 1

Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to be

loaded with the contents of TC.

0

This feature is disabled.

2

3

CAP0I

1

0

Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt.

This feature is disabled.

0

CAP1RE 1

Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to be

loaded with the contents of TC.

0

This feature is disabled.

4

CAP1FE 1

Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to be

loaded with the contents of TC.

0

This feature is disabled.

5

CAP1I

-

1

0

Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt.

This feature is disabled.

0

31:6

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C,

0x4009 003C, 0x4009 403C)

The External Match Register provides both control and status of the external match pins.

In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a

Match number, 0 through 3.

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Chapter 21: LPC17xx Timer 0/1/2/3

Match events for Match 0 and Match 1 in each timer can cause a DMA request, see

Section 21–6.12.

Table 432. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C,

0x4009 403C) bit description

Bit

Symbol Description

Reset

Value

0

EM0

EM1

EM2

EM3

External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go

low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a

MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).

0

1

2

3

External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go

low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a

MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).

External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go

low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a

MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).

External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go

low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a

MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).

5:4

7:6

9:8

EMC0

EMC1

EMC2

External Match Control 0. Determines the functionality of External Match 0. Table 21–433 shows 00

the encoding of these bits.

External Match Control 1. Determines the functionality of External Match 1. Table 21–433 shows 00

the encoding of these bits.

External Match Control 2. Determines the functionality of External Match 2. Table 21–433 shows 00

the encoding of these bits.

11:10 EMC3

15:12 -

External Match Control 3. Determines the functionality of External Match 3. Table 21–433 shows 00

the encoding of these bits.

Reserved, user software should not write ones to reserved bits. The value read from a reserved

bit is not defined.

NA

Table 433. External Match Control

EMR[11:10], EMR[9:8], Function

EMR[7:6], or EMR[5:4]

00

01

10

11

Do Nothing.

Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).

Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).

Toggle the corresponding External Match bit/output.

6.12 DMA operation

DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of

each timer. In order to have an effect, the GPDMA must be configured and the relevant

timer DMA request selected as a DMA source via the DMAREQSEL register, see

Section 31–5.15.

When a timer is initially set up to generate a DMA request, the request may already be

asserted before a match condition occurs. An initial DMA request may be avoided by

having software write a one to the interrupt flag location, as if clearing a timer interrupt.

See Section 21–6.1. A DMA request will be cleared automatically when it is acted upon by

the GPDMA controller.

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Chapter 21: LPC17xx Timer 0/1/2/3

7. Example timer operation

Figure 21–113 shows a timer configured to reset the count and generate an interrupt on

match. The prescaler is set to 2 and the match register set to 6. At the end of the timer

cycle where the match occurs, the timer count is reset. This gives a full length cycle to the

match value. The interrupt indicating that a match occurred is generated in the next clock

after the timer reached the match value.

Figure 21–114 shows a timer configured to stop and generate an interrupt on match. The

prescaler is again set to 2 and the match register set to 6. In the next clock after the timer

reaches the match value, the timer enable bit in TCR is cleared, and the interrupt

indicating that a match occurred is generated.

PCLK

prescale

counter

2

4

0

1

5

2

0

1

6

2

0

1

0

2

0

1

timer

counter

1

timer counter

reset

interrupt

Fig 113. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.

PCLK

prescale counter

timer counter

2

4

0

1

5

1

2

0

6

TCR[0]

(counter enable)

0

interrupt

Fig 114. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled

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Chapter 21: LPC17xx Timer 0/1/2/3

8. Architecture

The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in

Figure 21–115.

MATCH REGISTER 0

MATCH REGISTER 1

MATCH REGISTER 2

MATCH REGISTER 3

MATCH CONTROL REGISTER

EXTERNAL MATCH REGISTER

INTERRUPT REGISTER

CONTROL

MAT[3:0]

=

INTERRUPT

CAP[3:0]

=

DMA REQUEST[1:0]

=

DMA CLEAR[1:0]

STOP ON MATCH

RESET ON MATCH

LOAD[3:0]

=

CAPTURE CONTROL REGISTER

CSN

CAPTURE REGISTER 0

CAPTURE REGISTER 1

RESERVED

TIMER COUNTER

CE

RESERVED

TCI

PCLK

PRESCALE COUNTER

MAXVAL

reset

enable

TIMER CONTROL REGISTER

PRESCALE REGISTER

Fig 115. Timer block diagram

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Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT)

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1. Features

• 32-bit counter running from PCLK. Counter can be free-running, or be reset by a

generated interrupt.

• 32-bit compare value.

• 32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

2. Description

The Repetitive Interrupt Timer provides a versatile means of generating interrupts at

specified time intervals, without using a standard timer. It is intended for repeating

interrupts that aren’t related to Operating System interrupts. However, it could be used as

an alternative to the Cortex-M3 System Tick Timer (Section 23–1) if there are different

system requirements.

3. Register description

Table 434. Repetitive Interrupt Timer register map

Name

Description

Access Reset value^[1]Address

RICOMPVAL

RIMASK

Compare register

R/W

0xFFFF FFFF 0x400B 0000

Mask register. This register holds the 32-bit mask value. A ‘1’

written to any bit will force a compare on the corresponding bit of

the counter and compare register.

0

0x400B 0004

RICTRL

Control register.

32-bit counter

R/W

0xC

0

0x400B 0008

0x400B 000C

RICOUNTER

[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.

3.1 RI Compare Value register (RICOMPVAL - 0x400B 0000)

Table 435. RI Compare Value register (RICOMPVAL - address 0x400B 0000) bit description

Bit

Symbol

Description

Reset value

31:0 RICOMP Compare register. Holds the compare value which is compared to the counter.

0xFFFF FFFF

3.2 RI Mask register (RIMASK - 0x400B 0004)

Table 436. RI Compare Value register (RICOMPVAL - address 0x400B 0004) bit description

Bit

Symbol

Description

Reset value

31:0 RIMASK Mask register. This register holds the 32-bit mask value. A ‘1’ written to any bit will force a

compare on the corresponding bit of the counter and compare register.

0

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3.3 RI Control register (RICTRL - 0x400B 0008)

Table 437. RI Control register (RICTRL - address 0x400B 0008) bit description

Bit

Symbol

Value Description

Reset

value

0

RITINT

Interrupt flag

0

1

This bit is set to 1 by hardware whenever the counter value equals the masked

compare value specified by the contents of RICOMPVAL and RIMASK registers.

Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.

The counter value does not equal the masked compare value.

Timer enable clear

0

1

RITENCLR

The timer will be cleared to 0 whenever the counter value equals the masked compare

value specified by the contents of RICOMPVAL and RIMASK registers. This will occur

on the same clock that sets the interrupt flag.

0

The timer will not be cleared to 0.

Timer enable for debug

2

3

RITENBR

RITEN

1

0

The timer is halted when the processor is halted for debugging.

Debug has no effect on the timer operation.

Timer enable.

1

Timer enabled.

Remark: This can be overruled by a debug halt if enabled in bit 2.

Timer disabled.

0

-

31:4

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

3.4 RI Counter register (RICOUNTER - 0x400B 000C)

Table 438. RI Counter register (RICOUNTER - address 0x400B 000C) bit description

Bit Symbol Description

Reset

value

31:0 RICOUNTER 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or

debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any

value in software.

0

4. RI timer operation

Following reset, the counter begins counting up from 00000000h. Whenever the counter

value equals the value programmed into the RICOMPVAL register the interrupt flag will be

set. Any bit or combination of bits can be removed from this comparison (i.e. forced to

compare) by writing a ‘1’ to the corresponding bit(s) in the RIMASK register. If the

enable_clr bit is low (default state), a valid comparison ONLY causes the interrupt flag to

be set. It has no effect on the count sequence. Counting continues as usual. When the

counter reaches FFFFFFFFh it rolls-over to 00000000h on the next clock and continues

counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to

be reset to zero. Counting will resume from there on the next clock edge.

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Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2).

Counting will also be halted when the processor is halted for debugging provided the

Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are

set on reset.

The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit –

RICTRL(0).

Software can load the counter to any value at any time by writing to RICOUNTER.

The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register

can all be read by software at any time.

RESET

CNT_ENA

PBUS

RESET

ENA

CLR

32-bit COUNTER

SET

ENABLE_TIMER

3

PBUS

ENABLE_BREAK

BREAK

2

32

PBUS

ENABLE_CLK

PBUS

CLR

RESET

32

SET_INT

COMPARATOR

EQ

S

32

0

INTR

C

PBUS

write '1' to

clear

PBUS

CLR

32

RESET

PBUS

RESET

CTRL

register

PBUS

SET

COMPARE REGISTER

CLR

MASK REGISTER

PBUS

OperatingSystemTimer

Fig 116. RI timer block diagram

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Chapter 23: LPC17xx System Tick Timer

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1. Basic configuration

The System Tick Timer is configured using the following registers:

1. Clock Source: Select either the internal CCLK or external STCLK (P3.26) clock as the

source in the STCTRL register.

2. Pins: If STCLK (P3.26) was selected as clock source enable the STCLK pin function

in the PINMODE register (Section 8–5).

3. Interrupt: The System Tick Timer Interrupt is enabled in the NVIC using the

appropriate Interrupt Set Enable register.

2. Features

• Times intervals of 10 milliseconds

• Dedicated exception vector

• Can be clocked internally by the CPU clock or by a clock input from a pin (STCLK)

3. Description

The System Tick Timer is an integral part of the Cortex-M3. The System Tick Timer is

intended to generate a fixed 10 millisecond interrupt for use by an operating system or

other system management software.

Since the System Tick Timer is a part of the Cortex-M3, it facilitates porting of software by

providing a standard timer that is available on Cortex-M3 based devices.

Refer to the Cortex-M3 User Guide appended to this manual (Section 34–4.4) for details

of System Tick Timer operation.

4. Operation

The System Tick Timer is a 24-bit timer that counts down to zero and generates an

interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts.

The System Tick Timer may be clocked either from the CPU clock or from the external pin

STCLK. The STCLK function shares pin P3.26 with other functions, and must be selected

for use as the System Tick Timer clock. In order to generate recurring interrupts at a

specific interval, the STRELOAD register must be initialized with the correct value for the

desired interval. A default value is provided in the STCALIB register and may be changed

by software. The default value gives a 10 millisecond interrupt rate if the CPU clock is set

to 100 MHz.

The block diagram of the System Tick Timer is shown below in the Figure 23–117.

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STCALIB

STRELOAD

load data

STCURR

24-bit down counter

private

peripheral

bus

cclk

clock

STCLK pin

under- count

flow enable

D

Q

load

ENABLE

CLKSOURCE

STCTRL

COUNTFLAG TICKINT

System Tick

interrupt

Fig 117. System Tick Timer block diagram

5. Register description

Table 439. System Tick Timer register map

Name

Description

Access Reset value^[1]Address

STCTRL

STRELOAD

STCURR

STCALIB

System Timer Control and status register

System Timer Reload value register

System Timer Current value register

System Timer Calibration value register

R/W

0x4

0

0xE000 E010

0xE000 E014

0xE000 E018

0

0x000F 423F 0xE000 E01C

[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.

5.1 System Timer Control and status register (STCTRL - 0xE000 E010)

The STCTRL register contains control information for the System Tick Timer, and provides

a status flag.

Table 440. System Timer Control and status register (STCTRL - 0xE000 E010) bit description

Bit

Symbol

Description

Reset value

0

ENABLE

System Tick counter enable. When 1, the counter is enabled. When 0,

the counter is disabled.

0

1

2

TICKINT

System Tick interrupt enable. When 1, the System Tick interrupt is

enabled. When 0, the System Tick interrupt is disabled. When enabled,

the interrupt is generated when the System Tick counter counts down to

0.

0

1

CLKSOURCE

System Tick clock source selection. When 1, the CPU clock is selected.

When 0, the external clock pin (STCLK) is selected.

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Table 440. System Timer Control and status register (STCTRL - 0xE000 E010) bit description

Bit

Symbol

Description

Reset value

15:3

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

16

COUNTFLAG

-

System Tick counter flag. This flag is set when the System Tick counter

counts down to 0, and is cleared by reading this register.

0

31:17

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

5.2 System Timer Reload value register (STRELOAD - 0xE000 E014)

The STRELOAD register is set to the value that will be loaded into the System Tick Timer

whenever it counts down to zero. This register is loaded by software as part of timer

initialization. The STCALIB register may be read and used as the value for STRELOAD if

the CPU or external clock is running at the frequency intended for use with the STCALIB

value.

Table 441. System Timer Reload value register (STRELOAD - 0xE000 E014) bit description

Bit

Symbol

Description

Reset value

23:0

RELOAD

This is the value that is loaded into the System Tick counter when it

counts down to 0.

0

31:24

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

5.3 System Timer Current value register (STCURR - 0xE000 E018)

The STCURR register returns the current count from the System Tick counter when it is

read by software.

Table 442. System Timer Current value register (STCURR - 0xE000 E018) bit description

Bit

Symbol

Description

Reset value

23:0

CURRENT

Reading this register returns the current value of the System Tick

counter. Writing any value clears the System Tick counter and the

COUNTFLAG bit in STCTRL.

0

31:24

-

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

NA

5.4 System Timer Calibration value register (STCALIB - 0xE000 E01C)

The STCALIB register contains a value that is initialized by the Boot Code to a factory

programmed value that is appropriate for generating an interrupt every 10 milliseconds if

the System Tick Timer is clocked at a frequency of 100 MHz. This is the intended use of

the System Tick Timer by ARM. It can be used to generate interrupts at other frequencies

by selecting the correct reload value.

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Table 443. System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description

Bit

Symbol

Value Description

Reset value

23:0

TENMS

Reload value to get a 10 millisecond System Tick underflow rate when running 0x0F 423F

at 100 MHz. This value initialized at reset with a factory supplied value selected

for the LPC17xx. The provided values of TENMS, SKEW, and NOREF are

applicable only when using a CPU clock or external STCLK source of 100 MHz.

29:24

30

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

SKEW

Indicates whether the TENMS value will generate a precise 10 millisecond time,

or an approximation. This bit is initialized at reset with a factory supplied value

selected for the LPC17xx. See the description of TENMS above.

0

When 0, the value of TENMS is considered to be precise. When 1, the value of

TENMS is not considered to be precise.

31

NOREF

Indicates whether an external reference clock is available. This bit is initialized

at reset with a factory supplied value selected for the LPC17xx. See the

description of TENMS above.

0

When 0, a separate reference clock is available. When 1, a separate reference

clock is not available.

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Chapter 23: LPC17xx System Tick Timer

6. Example timer calculations

The following examples illustrate selecting System Tick Timer values for different system

configurations. All of the examples calculate an interrupt interval of 10 milliseconds, as the

System Tick Timer is intended to be used.

Example 1)

This example is for the System Tick Timer running from the CPU clock (cclk), which is

100 MHz.

STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.

RELOAD = (cclk / 100) - 1 = 1,000,000 - 1 = 999,999 = 0xF423F

In this case, there is no rounding error, so the result is as accurate as cclk.

Example 2)

This example is for the System Tick Timer running from the CPU clock (cclk), which is

80 MHz.

STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.

RELOAD = (cclk / 100) - 1 = 800,000 - 1 = 799,999 = 0xC34FF

In this case, there is no rounding error, so the result is as accurate as cclk.

Example 3)

This example is for the CPU clock (cclk) is taken from the Internal RC Oscillator (IRC),

factory trimmed to 4 MHz.

STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source.

RELOAD = (F_IRC/ 100) - 1 = 40,000 - 1 = 39,999 = 0x9C3F

In this case, there is no rounding error, so the result is as accurate as the IRC.

Example 4)

This example is for the System Tick Timer running from an external clock source (the

STCLK pin), which in this case happens to be 32.768 kHz.

STCTRL = 3. This enables the timer and its interrupt, and selects the STCLK pin as the

clock source. STCLK must be selected as the function of the relevant pin. See

Section 8–5.6.

RELOAD = (cclk / 100) - 1 = 327.6 - 1 = 327 (rounded up) = 0x0147

In this case, there is rounding error, so the interrupt rate will drift slightly relative to the

input frequency.

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Chapter 24: LPC17xx Pulse Width Modulator (PWM)

Rev. 01 — 4 January 2010

User manual

1. Basic configuration

The PWM is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCPWM1.

Remark: On reset, the PWM is enabled (PCPWM1 = 1).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_PWM1.

3. Pins: Select PWM pins through the PINSEL registers. Select pin modes for port pins

with PWM1 functions through the PINMODE registers (Section 8–5).

4. Interrupts: See registers PWM1MCR (Table 24–450) and PWM1CCR (Table 24–451)

for match and capture events. Interrupts are enabled in the NVIC using the

appropriate Interrupt Set Enable register.

2. Features

• Counter or Timer operation (may use the peripheral clock or one of the capture inputs

as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must "release" new match values before they can

become effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Two 32-bit capture channels take a snapshot of the timer value when an input signal

transitions. A capture event may also optionally generate an interrupt.

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Chapter 24: LPC17xx Pulse Width Modulator (PWM)

3. Description

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC17xx. The Timer is designed to count

cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other

actions when specified timer values occur, based on seven match registers. The PWM

function is in addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

Figure 24–118 shows the block diagram of the PWM. The portions that have been added

to the standard timer block are on the right hand side and at the top of the diagram.

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Chapter 24: LPC17xx Pulse Width Modulator (PWM)

SHADOW REGISTER 0

LOAD ENABLE

MATCH REGISTER 0

MATCH REGISTER 1

SHADOW REGISTER 1

LOAD ENABLE

SHADOW REGISTER 2

LOAD ENABLE

MATCH REGISTER 2

MATCH REGISTER 3

MATCH REGISTER 4

MATCH REGISTER 5

MATCH REGISTER 6

SHADOW REGISTER 3

LOAD ENABLE

SHADOW REGISTER 4

LOAD ENABLE

SHADOW REGISTER 5

LOAD ENABLE

Match 0

Match 1

PWM1

S

R

Q

SHADOW REGISTER 6

LOAD ENABLE

PWMENA1

EN

PWMSEL2

PWM2

Q

S

R

MUX

Match0

PWMENA2

Match 2

EN

LOAD ENABLE REGISTER CLEAR

PWMSEL3

MATCH CONTROL REGISTER

PWM3

Q

MUX

S

R

PWMENA3

Match 3

EN

INTERRUPT REGISTER

CONTROL

PWMSEL4

PWM4

Q

MUX

S

R

=

PWMENA4

Match 4

EN

=

M[6:0]

INTERRUPT

CAPTURE[1:0]

=

PWMSEL5

=

PWM5

Q

MUX

S

R

=

STOP ON MATCH

RESET ON MATCH

LOAD[1:0]

=

Match 5

PWMENA5

EN

=

PWMSEL6

CAPTURE CONTROL REGISTER

PWM6

Q

S

R

MUX

CSN

CAPTURE REGISTER 0

CAPTURE REGISTER 1

Match 6

PWMENA6

TIMER COUNTER

CE

EN

RESERVED

TCI

PRESCALE COUNTER

PWMENA1..6 PWMSEL2..6

PWM CONTROL REGISTER

MAXVAL

reset

enable

TIMER CONTROL REGISTER

PRESCALE REGISTER

Fig 118. PWM block diagram

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4. Sample waveform with rules for single and double edge control

A sample of how PWM values relate to waveform outputs is shown in Figure 24–119.

PWM output logic is shown in Figure 24–118 that allows selection of either single or

double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The

match register selections for various PWM outputs is shown in Table 24–444. This

implementation supports up to N-1 single edge PWM outputs or (N-1)/2 double edge

PWM outputs, where N is the number of match registers that are implemented. PWM

types can be mixed if desired.

PWM2

PWM4

PWM5

1

27

41

53

65

78

100

(counter is reset)

The waveforms below show a single PWM cycle and demonstrate PWM outputs under the

following conditions:

The timer is configured for PWM mode (counter resets to 1).

Match 0 is configured to reset the timer/counter when a match event occurs.

All PWM related Match registers are configured for toggle on match.

Control bits PWMSEL2 and PWMSEL4 are set.

The Match register values are as follows:

MR0 = 100 (PWM rate)

MR1 = 41, MR2 = 78 (PWM2 output)

MR3 = 53, MR4 = 27 (PWM4 output)

MR5 = 65 (PWM5 output)

Fig 119. Sample PWM waveforms

Table 444. Set and reset inputs for PWM Flip-Flops

PWM Channel

Single Edge PWM (PWMSELn = 0) Double Edge PWM (PWMSELn = 1)

Set by

Reset by

Match 1

Match 2

Match 3

Match 4

Match 5

Match 6

Set by

Reset by

Match 1^[1]

Match 2

1

2

3

4

5

6

Match 0

Match 0^[1]

Match 1

Match 2^[2]

Match 3

Match 4^[2]

Match 5

Match 3^[2]

Match 4

Match 5^[2]

Match 6

[1] Identical to single edge mode in this case since Match 0 is the neighboring match register. Essentially,

PWM1 cannot be a double edged output.

[2] It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it

would reduce the number of double edge PWM outputs that are possible. Using PWM 2, PWM4, and

PWM6 for double edge PWM outputs provides the most pairings.

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4.1 Rules for Single Edge Controlled PWM Outputs

1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle

unless their match value is equal to 0.

2. Each PWM output will go low when its match value is reached. If no match occurs (i.e.

the match value is greater than the PWM rate), the PWM output remains continuously

high.

4.2 Rules for Double Edge Controlled PWM Outputs

Five rules are used to determine the next value of a PWM output when a new cycle is

about to begin:

1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time

point which is coincident with the beginning of the next PWM cycle), except as noted

in rule 3.

2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0

value) have the same effect, except as noted in rule 3. For example, a request for a

falling edge at the beginning of the PWM cycle has the same effect as a request for a

falling edge at the end of a PWM cycle.

3. When match values are changing, if one of the "old" match values is equal to the

PWM rate, it is used again once if the neither of the new match values are equal to 0

or the PWM rate, and there was no old match value equal to 0.

4. If both a set and a clear of a PWM output are requested at the same time, clear takes

precedence. This can occur when the set and clear match values are the same as in,

or when the set or clear value equals 0 and the other value equals the PWM rate.

5. If a match value is out of range (i.e. greater than the PWM rate value), no match event

occurs and that match channel has no effect on the output. This means that the PWM

output will remain always in one state, allowing always low, always high, or

"no change" outputs.

5. Pin description

Table 24–445 gives a brief summary of each of PWM related pins.

Table 445. Pin summary

Type

Description

PWM1[1]

PWM1[2]

PWM1[3]

PWM1[4]

PWM1[5]

PWM1[6]

PCAP1[1:0]

Output

Input

Output from PWM channel 1.

Output from PWM channel 2.

Output from PWM channel 3.

Output from PWM channel 4.

Output from PWM channel 5.

Output from PWM channel 6.

Capture Inputs. A transition on a capture pin can be configured to load

the corresponding Capture Register with the value of the Timer

Counter and optionally generate an interrupt. The PWM brings out 2

capture inputs.

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6. Register description

The PWM1 function includes registers as shown in Table 24–446 below.

Table 446. PWM1 register map

Generic Description

Name

Access Reset

PWMn Register

Value^[1]Name & Address

IR

Interrupt Register. The IR can be written to clear interrupts. The IR can be R/W

read to identify which of eight possible interrupt sources are pending.

0

PWM1IR -

0x4001 8000

PWM1TCR -

0x4001 8004

PWM1TC -

TCR

TC

PR

PC

Timer Control Register. The TCR is used to control the Timer Counter

functions. The Timer Counter can be disabled or reset through the TCR.

R/W

Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. R/W

The TC is controlled through the TCR.

0x4001 8008

PWM1PR -

0x4001 800C

PWM1PC -

0x4001 8010

Prescale Register. The TC is incremented every PR+1 cycles of PCLK.

R/W

Prescale Counter. The 32-bit PC is a counter which is incremented to the R/W

value stored in PR. When the value in PR is reached, the TC is

incremented. The PC is observable and controllable through the bus

interface.

MCR

MR0

Match Control Register. The MCR is used to control if an interrupt is

generated and if the TC is reset when a Match occurs.

R/W

0

PWM1MCR -

0x4001 8014

PWM1MR0 -

0x4001 8018

Match Register 0. MR0 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC sets any PWM output

that is in single-edge mode, and sets PWM1 if it’s in double-edge mode.

MR1

MR2

MR3

CCR

Match Register 1. MR1 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM1 in either

edge mode, and sets PWM2 if it’s in double-edge mode.

0

PWM1MR1 -

0x4001 801C

Match Register 2. MR2 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM2 in either

edge mode, and sets PWM3 if it’s in double-edge mode.

PWM1MR2 -

0x4001 8020

Match Register 3. MR3 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM3 in either

edge mode, and sets PWM4 if it’s in double-edge mode.

PWM1MR3 -

0x4001 8024

Capture Control Register. The CCR controls which edges of the capture

inputs are used to load the Capture Registers and whether or not an

interrupt is generated when a capture takes place.

R/W

PWM1CCR -

0x4001 8028

CR0

CR1

CR2

CR3

Capture Register 0. CR0 is loaded with the value of the TC when there is RO

an event on the CAPn.0 input.

0

PWM1CR0 -

0x4001 802C

PWM1CR1 -

0x4001 8030

PWM1CR2 -

0x4001 8034

PWM1CR3 -

0x4001 8038

Capture Register 1. See CR0 description.

Capture Register 2. See CR0 description.

Capture Register 3. See CR0 description.

RO

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Table 446. PWM1 register map

Generic Description

Name

Access Reset

PWMn Register

Value^[1]Name & Address

MR4

MR5

MR6

Match Register 4. MR4 can be enabled in the MCR to reset the TC, stop R/W

0

PWM1MR4 -

0x4001 8040

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM4 in either

edge mode, and sets PWM5 if it’s in double-edge mode.

Match Register 5. MR5 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM5 in either

edge mode, and sets PWM6 if it’s in double-edge mode.

PWM1MR5 -

0x4001 8044

Match Register 6. MR6 can be enabled in the MCR to reset the TC, stop R/W

both the TC and PC, and/or generate an interrupt when it matches the TC.

In addition, a match between this value and the TC clears PWM6 in either

edge mode.

PWM1MR6 -

0x4001 8048

PCR

LER

PWM Control Register. Enables PWM outputs and selects PWM channel R/W

types as either single edge or double edge controlled.

0

PWM1PCR -

0x4001 804C

PWM1LER -

0x4001 8050

PWM1CTCR -

0x4001 8070

Load Enable Register. Enables use of new PWM match values.

R/W

CTCR

Count Control Register. The CTCR selects between Timer and Counter

mode, and in Counter mode selects the signal and edge(s) for counting.

R/W

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 PWM Interrupt Register (PWM1IR - 0x4001 8000)

The PWM Interrupt Register consists of 11 bits (Table 24–447), 7 for the match interrupts

and 4 reserved for the future use. If an interrupt is generated then the corresponding bit in

the PWMIR will be high. Otherwise, the bit will be low. Writing a logic 1 to the

corresponding IR bit will reset the interrupt. Writing a 0 has no effect.

Table 447: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description

Bit

Symbol

Description

Reset

Value

0

1

2

3

4

PWMMR0 Interrupt Interrupt flag for PWM match channel 0.

PWMMR1 Interrupt Interrupt flag for PWM match channel 1.

PWMMR2 Interrupt Interrupt flag for PWM match channel 2.

PWMMR3 Interrupt Interrupt flag for PWM match channel 3.

0

PWMCAP0

Interrupt

Interrupt flag for capture input 0

5

PWMCAP1

Interrupt

Interrupt flag for capture input 1.

0

7:6

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

8

PWMMR4 Interrupt Interrupt flag for PWM match channel 4.

PWMMR5 Interrupt Interrupt flag for PWM match channel 5.

PWMMR6 Interrupt Interrupt flag for PWM match channel 6.

0

9

10

31:11

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

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6.2 PWM Timer Control Register (PWM1TCR 0x4001 8004)

The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM

Timer Counter. The function of each of the bits is shown in Table 24–448.

Table 448: PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description

Bit

Symbol

Value Description

Reset

Value

0

Counter Enable

1

0

1

The PWM Timer Counter and PWM Prescale Counter are enabled for counting.

0

The counters are disabled.

1

Counter Reset

The PWM Timer Counter and the PWM Prescale Counter are synchronously reset

on the next positive edge of PCLK. The counters remain reset until this bit is

returned to zero.

0

1

Clear reset.

2

3

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

0

PWM Enable

PWM mode is enabled (counter resets to 1). PWM mode causes the shadow

registers to operate in connection with the Match registers. A program write to a

Match register will not have an effect on the Match result until the corresponding bit

in PWMLER has been set, followed by the occurrence of a PWM Match 0 event.

Note that the PWM Match register that determines the PWM rate (PWM Match

Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a

Match event will not occur to cause shadow register contents to become effective.

0

Timer mode is enabled (counter resets to 0).

31:4

-

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

6.3 PWM Count Control Register (PWM1CTCR - 0x4001 8070)

The Count Control Register (CTCR) is used to select between Timer and Counter mode,

and in Counter mode to select the pin and edge(s) for counting. The function of each of

the bits is shown in Table 24–449.

Table 449: PWM Count control Register (PWM1CTCR - address 0x4001 8004) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

Counter/

Timer Mode

00

01

10

11

Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale 00

Register.

Counter Mode: the TC is incremented on rising edges of the PCAP input selected by

bits 3:2.

Counter Mode: the TC is incremented on falling edges of the PCAP input selected by

bits 3:2.

Counter Mode: the TC is incremented on both edges of the PCAP input selected by

bits 3:2.

3:2

Count Input

Select

When bits 1:0 of this register are not 00, these bits select which PCAP pin which

carries the signal used to increment the TC.

00

01

PCAP1.0

PCAP1.1 (Other combinations are reserved)

31:4

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

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6.4 PWM Match Control Register (PWM1MCR - 0x4001 8014)

The PWM Match Control Registers are used to control what operations are performed

when one of the PWM Match Registers matches the PWM Timer Counter. The function of

each of the bits is shown in Table 24–450.

Table 450: Match Control Register (PWM1MCR - address 0x4000 4014) bit description

Bit

Symbol

Value Description

Reset

Value

0

PWMMR0I

1

Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in

0

the PWMTC.

0

1

0

1

This interrupt is disabled.

1

2

PWMMR0R

PWMMR0S

Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.

This feature is disabled.

0

Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR0 matches the PWMTC.

0

1

This feature is disabled

3

PWMMR1I

Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in

the PWMTC.

0

1

0

1

This interrupt is disabled.

4

5

PWMMR1R

PWMMR1S

Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.

This feature is disabled.

0

Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR1 matches the PWMTC.

0

1

This feature is disabled.

6

PWMMR2I

Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in

the PWMTC.

0

1

0

1

This interrupt is disabled.

7

8

PWMMR2R

PWMMR2S

Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.

This feature is disabled.

0

Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR2 matches the PWMTC.

0

1

This feature is disabled

9

PWMMR3I

Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in

the PWMTC.

0

1

0

1

This interrupt is disabled.

10

11

PWMMR3R

PWMMR3S

Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.

This feature is disabled

0

Stop on PWMMR3: The PWMTC and PWMPC will be stopped and PWMTCR[0] will

be set to 0 if PWMMR3 matches the PWMTC.

0

1

This feature is disabled

12

13

PWMMR4I

PWMMR4R

Interrupt on PWMMR4: An interrupt is generated when PWMMR4 matches the value

in the PWMTC.

0

1

0

This interrupt is disabled.

Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.

This feature is disabled.

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Table 450: Match Control Register (PWM1MCR - address 0x4000 4014) bit description

Bit

Symbol

Value Description

Reset

Value

14

PWMMR4S

1

Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

0

set to 0 if PWMMR4 matches the PWMTC.

0

1

This feature is disabled

15

PWMMR5I

Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value

in the PWMTC.

0

1

0

1

This interrupt is disabled.

16

17

PWMMR5R

PWMMR5S

Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.

This feature is disabled.

0

Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR5 matches the PWMTC.

0

1

This feature is disabled

18

PWMMR6I

Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in

the PWMTC.

0

1

0

1

This interrupt is disabled.

19

20

PWMMR6R

PWMMR6S

Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.

This feature is disabled.

0

Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR6 matches the PWMTC.

31:21 -

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

6.5 PWM Capture Control Register (PWM1CCR - 0x4001 8028)

The Capture Control Register is used to control whether one of the four Capture Registers

is loaded with the value in the Timer Counter when a capture event occurs, and whether

an interrupt is generated by the capture event. Setting both the rising and falling bits at the

same time is a valid configuration, resulting in a capture event for both edges. In the

descriptions below, “n” represents the Timer number, 0 or 1.

Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for

that input in this register should be programmed as 000, but capture and/or interrupt can

be selected for the other 3 CAP inputs.

Table 451: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description

Bit

Symbol

Value Description

Reset

Value

0

Capture on

CAPn.0 rising

edge

0

1

This feature is disabled.

0

A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be

loaded with the contents of the TC.

1

2

Capture on

CAPn.0 falling

edge

0

1

This feature is disabled.

A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with

the contents of TC.

Interrupt on

CAPn.0 event

0

1

This feature is disabled.

A CR0 load due to a CAPn.0 event will generate an interrupt.

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Table 451: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description

Bit

Symbol

Value Description

Reset

Value

3

Capture on

CAPn.1rising

edge

0

1

This feature is disabled.

0

A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be

loaded with the contents of the TC.

4

Capture on

CAPn.1falling

edge

0

1

This feature is disabled.

A synchronously sampled falling edge on CAPn.1 will cause CR1 to be loaded with

the contents of TC.

5

Interrupt on

CAPn.1 event

0

1

This feature is disabled.

A CR1 load due to a CAPn.1 event will generate an interrupt.

31:6

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

6.6 PWM Control Register (PWM1PCR - 0x4001 804C)

The PWM Control Register is used to enable and select the type of each PWM channel.

The function of each of the bits are shown in Table 24–452.

Table 452: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

2

Unused

Unused, always zero.

NA

0

PWMSEL2

1

0

1

0

1

0

1

0

1

0

Selects double edge controlled mode for the PWM2 output.

Selects single edge controlled mode for PWM2.

3

4

5

6

PWMSEL3

PWMSEL4

PWMSEL5

PWMSEL6

Selects double edge controlled mode for the PWM3 output.

Selects single edge controlled mode for PWM3.

0

Selects double edge controlled mode for the PWM4 output.

Selects single edge controlled mode for PWM4.

Selects double edge controlled mode for the PWM5 output.

Selects single edge controlled mode for PWM5.

Selects double edge controlled mode for the PWM6 output.

Selects single edge controlled mode for PWM6.

8:7

9

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

PWMENA1

1

0

1

0

1

0

1

0

1

0

The PWM1 output enabled.

The PWM1 output disabled.

The PWM2 output enabled.

The PWM2 output disabled.

The PWM3 output enabled.

The PWM3 output disabled.

The PWM4 output enabled.

The PWM4 output disabled.

The PWM5 output enabled.

The PWM5 output disabled.

0

10

11

12

13

PWMENA2

PWMENA3

PWMENA4

PWMENA5

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Table 452: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description

Bit

Symbol

Value Description

Reset

Value

14

PWMENA6

1

0

The PWM6 output enabled.

0

The PWM6 output disabled.

Unused, always zero.

31:15 Unused

NA

6.7 PWM Latch Enable Register (PWM1LER - 0x4001 8050)

The PWM Latch Enable Registers are used to control the update of the PWM Match

registers when they are used for PWM generation. When software writes to the location of

a PWM Match register while the Timer is in PWM mode, the value is captured, but not

used immediately.

When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the

contents of shadow registers will be transferred to the shadow registers if the

corresponding bit in the Latch Enable Register has been set. At that point, the new values

will take effect and determine the course of the next PWM cycle. Once the transfer of new

values has taken place, all bits of the LER are automatically cleared. Until the

corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value

written to the PWM Match registers has no effect on PWM operation.

For example, if PWM2 is configured for double edge operation and is currently running, a

typical sequence of events for changing the timing would be:

• Write a new value to the PWM Match1 register.

• Write a new value to the PWM Match2 register.

• Write to the PWMLER, setting bits 1 and 2 at the same time.

• The altered values will become effective at the next reset of the timer (when a PWM

Match 0 event occurs).

The order of writing the two PWM Match registers is not important, since neither value will

be used until after the write to LER. This insures that both values go into effect at the

same time, if that is required. A single value may be altered in the same way if needed.

The function of each of the bits in the LER is shown in Table 24–453.

Table 453: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description

Bit

Symbol

Description

Reset

Value

0

Enable PWM

Match 0 Latch

Writing a one to this bit allows the last value written to the PWM Match 0 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

0

1

2

3

Enable PWM

Match 1 Latch

Writing a one to this bit allows the last value written to the PWM Match 1 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

Enable PWM

Match 2 Latch

Writing a one to this bit allows the last value written to the PWM Match 2 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

Enable PWM

Match 3 Latch

Writing a one to this bit allows the last value written to the PWM Match 3 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

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Table 453: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description

Bit

Symbol

Description

Reset

Value

4

Enable PWM

Match 4 Latch

Writing a one to this bit allows the last value written to the PWM Match 4 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

0

5

Enable PWM

Match 5 Latch

Writing a one to this bit allows the last value written to the PWM Match 5 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

0

6

Enable PWM

Match 6 Latch

Writing a one to this bit allows the last value written to the PWM Match 6 register to be

become effective when the timer is next reset by a PWM Match event. See Section 24–6.4

“PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

0

31:7

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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Rev. 01 — 4 January 2010

User manual

1. Introduction

The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control

applications, but can be used in many other applications that need timing, counting,

capture, and comparison.

2. Description

The MCPWM contains three independent channels, each including:

• a 32-bit Timer/Counter (TC)

• a 32-bit Limit register (LIM)

• a 32-bit Match register (MAT)

• a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter

• a 32-bit capture register (CAP)

• two modulated outputs (MCOA and MCOB) with opposite polarities

• a period interrupt, a pulse-width interrupt, and a capture interrupt

Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort

input can force all of the channels into “A passive” state and cause an interrupt.

3. Pin description

Table 25–454 lists the MCPWM pins.

Table 454. Pin summary

Type

Description

MCOA0, MCOA1, MCOA2

MCOB0, MCOB1, MCOB2

MCABORT

O

I

Output A for channels 0, 1, 2

Output B for channels 0, 1, 2

Low-active Fast Abort

Input for channels 0, 1, 2

MCI0, MCI1, MCI2

I

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4. Block Diagram

PCLK

MCI0-2

Clock

TC0

Event

selection

Clock

selection

Event

selection

Clock

selection

Event

selection

TC1

TC2

selection

MCCNTCON

MCCAPCON

cntl

RT0

RT1

RT2

MAT0

(write)

MAT1

(write)

MAT2

(write)

mux

ACMODE

MAT0

(oper)

MAT1

(oper)

MAT2

(oper)

=

LIM0

LIM1

LIM2

(write)

LIM0

(oper)

LIM1

(oper)

LIM2

(oper)

=

CAP0

CAP1

CAP2

interrupt

logic

MCABORT

MCINTEN MCINTF

mux

ACMODE

DT1

ACMODE

DT0

DT2

channel

output

control

channel

output

control

channel

output

control

dead-time

counter

dead-time

counter

dead-time

counter

MCCON

A0

B0

A1

B1

A2

B2

MCCON

MCCP

MCABORT

global output control

MCOA1 MCOB1

MCOA0 MCOB0

MCOA2 MCOB2

Fig 120. MCPWM Block Diagram

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5. Configuring other modules for MCPWM use

Configure the following registers in other modules before using the Motor Control PWM:

1. Power: in the PCONP register (Table 4–46), set bit PCMCPWM.

Remark: On reset the MCPWM is disabled (PCMCPWM = 0).

2. Peripheral clock: in the PCLKSEL1 register (Table 4–40) select PCLK_MCPWM.

3. Pins: select MCPWM functions through the PINSEL registers. Select modes for these

pins through the PINMODE registers (Section 8–5).

4. Interrupts: See Section 25–7.3 for motor control PWM related interrupts. Interrupts

can be enabled in the NVIC using the appropriate Interrupt Set Enable register.

6. General Operation

Section 25–8 includes detailed descriptions of the various modes of MCPWM operation,

but a quick preview here will provide background for the register descriptions below.

The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can

control something off-chip, like one set of coils in a motor. Each channel includes a

Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by

an input pin (counter mode).

Each channel has a Limit register that is compared to the TC value, and when a match

occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to

0, while in “centered mode” a match switches the TC into a state in which it decrements on

each processor clock or input pin transition until it reaches 0, at which time it starts

counting up again.

Each channel also includes a Match register that holds a smaller value than the Limit

register. In edge-aligned mode the channel’s outputs are switched whenever the TC

matches either the Match or Limit register, while in center-aligned mode they are switched

only when it matches the Match register.

So the Limit register controls the period of the outputs, while the Match register controls

how much of each period the outputs spend in each state. Having a small value in the

Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the

MCPWM to control devices that operate at high speed.

The “downside” of small values in the Limit register is that they reduce the resolution of

the duty cycle controlled by the Match register. If you have 8 in the Limit register, the

Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or

100%. In general, the resolution of each step in the Match value is 1 divided by the Limit

value.

This trade-off between resolution and period/frequency is inherent in the design of pulse

width modulators.

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7. Register description

“Control” registers and “interrupt” registers have separate read, set, and clear addresses.

Reading such a register’s read address(e.g. MCCON) yields the state of the register bits.

Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones

to the clear address (e.g. MCCON_CLR) clears register bit(s).

The Capture registers (MCCAP) are read-only, and the write-only MCCAP_CLR address

can be used to clear one or more of them. All the other MCPWM registers (MCTIM,

MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers.

Table 455. Motor Control Pulse Width Modulator (MCPWM) register map

Name

Description

Access

RO

Reset value

Address

MCCON

PWM Control read address

PWM Control set address

PWM Control clear address

Capture Control read address

Capture Control set address

Event Control clear address

Timer Counter register, channel 0

Timer Counter register, channel 1

Timer Counter register, channel 2

Limit register, channel 0

0

-

0x400B 8000

0x400B 8004

0x400B 8008

0x400B 800C

0x400B 8010

0x400B 8014

0x400B 8018

0x400B 801C

0x400B 8020

MCCON_SET

MCCON_CLR

MCCAPCON

MCCAPCON_SET

MCCAPCON_CLR

MCTC0

WO

RO

-

0

-

WO

R/W

RO

-

0

MCTC1

MCTC2

MCLIM0

0xFFFF FFFF 0x400B 8024

0xFFFF FFFF 0x400B 8028

0xFFFF FFFF 0x400B 802C

0xFFFF FFFF 0x400B 8030

0xFFFF FFFF 0x400B 8034

0xFFFF FFFF 0x400B 8038

0x3FFF FFFF 0x400B 803C

MCLIM1

Limit register, channel 1

MCLIM2

Limit register, channel 2

MCMAT0

Match register, channel 0

Match register, channel 1

Match register, channel 2

Dead time register

MCMAT1

MCMAT2

MCDT

MCCP

Commutation Pattern register

Capture register, channel 0

Capture register, channel 1

Capture register, channel 2

Interrupt Enable read address

Interrupt Enable set address

Interrupt Enable clear address

Count Control read address

Count Control set address

Count Control clear address

Interrupt flags read address

Interrupt flags set address

Interrupt flags clear address

Capture clear address

0

-

0x400B 8040

0x400B 8044

0x400B 8048

0x400B 804C

0x400B 8050

0x400B 8054

0x400B 8058

0x400B 805C

0x400B 8060

0x400B 8064

0x400B 8068

0x400B 806C

0x400B 8070

0x400B 8074

MCCAP0

MCCAP1

RO

MCCAP2

RO

MCINTEN

RO

MCINTEN_SET

MCINTEN_CLR

MCCNTCON

MCCNTCON_SET

MCCNTCON_CLR

MCINTF

WO

RO

-

0

-

WO

RO

-

0

-

MCINTF_SET

MCINTF_CLR

MCCAP_CLR

WO

-

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7.1 MCPWM Control register

7.1.1 MCPWM Control read address (MCCON - 0x400B 8000)

The MCCON register controls the operation of all channels of the PWM. This address is

read-only, but the underlying register can be modified by writing to addresses

MCCON_SET and MCCON_CLR.

Table 456. MCPWM Control read address (MCCON - 0x400B 8000) bit description

Bit

Symbol

Value Description

Reset

value

0

RUN0

Stops/starts timer channel 0.

Stop.

0

1

Run.

1

2

3

4

CENTER0

POLA0

DTE0

Edge/center aligned operation for channel 0.

Edge-aligned.

0

1

Center-aligned.

Selects polarity of the MCOA0 and MCOB0 pins.

Passive state is LOW, active state is HIGH.

Passive state is HIGH, active state is LOW.

Controls the dead-time feature for channel 0.

Dead-time disabled.

0

1

0

1

Dead-time enabled.

DISUP0

Enable/disable updates of functional registers for channel 0 (see Section 25–8.2).

0

Functional registers are updated from the write registers at the end of each PWM

cycle.

1

-

Functional registers remain the same as long as the timer is running.

7:5

8

-

Reserved.

RUN1

Stops/starts timer channel 1.

0

1

Stop.

Run.

9

CENTER1

POLA1

DTE1

Edge/center aligned operation for channel 1.

Edge-aligned.

0

1

Center-aligned.

10

11

12

Selects polarity of the MCOA1 and MCOB1 pins.

Passive state is LOW, active state is HIGH.

Passive state is HIGH, active state is LOW.

Controls the dead-time feature for channel 1.

Dead-time disabled.

0

1

0

1

Dead-time enabled.

DISUP1

Enable/disable updates of functional registers for channel 1 (see Section 25–8.2).

0

Functional registers are updated from the write registers at the end of each PWM

cycle.

1

-

Functional registers remain the same as long as the timer is running.

Reserved.

15:13

-

0

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Table 456. MCPWM Control read address (MCCON - 0x400B 8000) bit description

Bit

Symbol

Value Description

Reset

value

16

RUN2

Stops/starts timer channel 2.

Stop.

0

1

Run.

17

18

19

20

CENTER2

POLA2

DTE2

Edge/center aligned operation for channel 2.

Edge-aligned.

0

1

Center-aligned.

Selects polarity of the MCOA2 and MCOB2 pins.

Passive state is LOW, active state is HIGH.

Passive state is HIGH, active state is LOW.

Controls the dead-time feature for channel 1.

Dead-time disabled.

0

1

0

1

Dead-time enabled.

DISUP2

Enable/disable updates of functional registers for channel 2 (see Section 25–8.2).

0

Functional registers are updated from the write registers at the end of each PWM

cycle.

1

-

Functional registers remain the same as long as the timer is running.

Reserved.

28:21

29

-

INVBDC

Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set

to 1 only in 3-phase DC mode.

0

1

The MCOB outputs have opposite polarity from the MCOA outputs (aside from

dead time).

The MCOB outputs have the same basic polarity as the MCOA outputs. (see

Section 25–8.6)

30

31

ACMODE

DCMODE

3-phase AC mode select (see Section 25–8.7).

0

1

3-phase AC-mode off: Each PWM channel uses its own timer-counter and period

register.

3-phase AC-mode on: All PWM channels use the timer-counter and period register

of channel 0.

3-phase DC mode select (see Section 25–8.6).

0

1

3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)

3-phase DC mode on: The internal MCOA0 output is routed through the MCCP (i.e.

a mask) register to all six PWM outputs.

7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004)

Writing ones to this write-only address sets the corresponding bits in MCCON.

Table 457. MCPWM Control set address (MCCON_SET - 0x400B 8004) bit description

Bit

Description

31:0

Writing ones to this address sets the corresponding bits in the MCCON register. See Table 25–456.

7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)

Writing ones to this write-only address clears the corresponding bits in MCCON.

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Table 458. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description

Bit

Description

31:0

Writing ones to this address clears the corresponding bits in the MCCON register. See Table 25–456.

7.2 MCPWM Capture Control register

7.2.1 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C)

The MCCAPCON register controls detection of events on the MCI0-2 inputs for all

MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on

any or all of the three channels. This address is read-only, but the underlying register can

be modified by writing to addresses MCCAPCON_SET and MCCAPCON_CLR.

Table 459. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description

Bit

Symbol

Description

Reset

Value

0

CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.

CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.

CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.

CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.

CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.

CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.

CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.

CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.

CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.

CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.

CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.

CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.

CAP2MCI0_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.

CAP2MCI0_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.

CAP2MCI1_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.

CAP2MCI1_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.

CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.

CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

RT0

If this bit is 1, TC0 is reset by a channel 0 capture event.

If this bit is 1, TC1 is reset by a channel 1 capture event.

If this bit is 1, TC2 is reset by a channel 2 capture event.

RT1

RT2

HNFCAP0

Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in

Section 25–8.4.

22

23

HNFCAP1

HNFCAP2

Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in

Section 25–8.4.

0

-

Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in

Section 25–8.4.

31:24 -

Reserved.

7.2.2 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010)

Writing ones to this write-only address sets the corresponding bits in MCCAPCON.

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Table 460. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description

Bit

Description

31:0

Writing ones to this address sets the corresponding bits in the MCCAPCON register. See Table 25–459.

7.2.3 MCPWM Capture control clear address (MCCAPCON_CLR - 0x400B 8014)

Writing ones to this write-only address clears the corresponding bits in MCCAPCON.

Table 461. MCPWM Capture control clear register (MCCAPCON_CLR - address 0x400B 8014) bit description

Bit

Description

31:0

Writing ones to this address clears the corresponding bits in the MCCAPCON register. See Table 25–459.

7.3 MCPWM Interrupt registers

The Motor Control PWM module includes the following interrupt sources:

Table 462. Motor Control PWM interrupts

Symbol

Description

ILIM0/1/2

IMAT0/1/2

ICAP0/1/2

ABORT

Limit interrupts for channels 0, 1, 2.

Match interrupts for channels 0, 1, 2.

Capture interrupts for channels 0, 1, 2.

Fast abort interrupt

All MCPWM interrupt registers contain one bit for each source as shown in Table 25–463.

Table 463. Interrupt sources bit allocation table

Bit

31

30

29

28

27

-

26

25

24

Symbol

Bit

-

18

-

23

22

21

20

19

-

17

16

Symbol

Bit

-

12

-

9

-

8

15

14

13

11

-

10

Symbol

Bit

ABORT

-

6

-

5

ICAP2

2

IMAT2

1

ILIM2

0

7

4

3

Symbol

-

ICAP1

IMAT1

ILIM1

-

ICAP0

IMAT0

ILIM0

7.3.1 MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050)

The MCINTEN register controls which of the MCPWM interrupts are enabled. This

address is read-only, but the underlying register can be modified by writing to addresses

MCINTEN_SET and MCINTEN_CLR.

Table 464. MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) bit description

Bit

Value Description

Reset

value

31:0

See Table 25–463 for the bit allocation.

0

1

0

Interrupt enabled.

Interrupt disabled.

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7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054)

Writing ones to this write-only address sets the corresponding bits in MCINTEN, thus

enabling interrupts.

Table 465. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit description

Bit

Description

31:0

Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling interrupts. See Table 25–463.

7.3.3 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058)

Writing ones to this write-only address clears the corresponding bits in MCINTEN, thus

disabling interrupts.

Table 466. PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit description

Bit

Description

31:0

Writing ones to this address clears the corresponding bits in MCINTEN, thus disabling interrupts. See

Table 25–463.

7.3.4 MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068)

The MCINTF register includes all MCPWM interrupt flags, which are set when the

corresponding hardware event occurs, or when ones are written to the MCINTF_SET

address. When corresponding bits in this register and MCINTEN are both 1, the MCPWM

asserts its interrupt request to the Interrupt Controller module. This address is read-only,

but the bits in the underlying register can be modified by writing ones to addresses

MCINTF_SET and MCINTF_CLR.

Table 467. MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068) bit description

Bit

Value Description

Reset

value

31:0

See Table 25–463 for the bit allocation.

0

1

0

If the corresponding bit in MCINTEN is 1, the MCPWM module is asserting its interrupt request to

the Interrupt Controller.

This interrupt source is not contributing to the MCPWM interrupt request.

7.3.5 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C)

Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus

possibly simulating hardware interrupt(s).

Table 468. MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit description

Bit

Description

31:0

Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF register, thus possibly

simulating hardware interrupt(s). See Table 25–463.

7.3.6 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070)

Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus

clearing the corresponding interrupt request(s). This is typically done in interrupt service

routines.

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Table 469. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit description

Bit

Description

31:0

Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF register, thus clearing the

corresponding interrupt request(s). See Table 25–463.

7.4 MCPWM Count Control register

7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C)

The MCCNTCON register controls whether the MCPWM channels are in timer or counter

mode, and in counter mode whether the counter advances on rising and/or falling edges

on any or all of the three MCI inputs. If timer mode is selected, the counter advances

based on the PCLK clock.

This address is read-only. To set or clear the register bits, write ones to the

MCCNTCON_SET or MCCNTCON_CLR address.

Table 470. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description

Bit

Symbol

Value Description

Reset

Value

0

TC0MCI0_RE

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

If MODE0 is 1, counter 0 advances on a rising edge on MCI0.

0

A rising edge on MCI0 does not affect counter 0.

1

TC0MCI0_FE

TC0MCI1_RE

TC0MCI1_FE

TC0MCI2_RE

TC0MCI2_FE

TC1MCI0_RE

TC1MCI0_FE

TC1MCI1_RE

TC1MCI1_FE

TC1MCI2_RE

TC1MCI2_FE

TC2MCI0_RE

If MODE0 is 1, counter 0 advances on a falling edge on MCI0.

A falling edge on MCI0 does not affect counter 0.

2

If MODE0 is 1, counter 0 advances on a rising edge on MCI1.

A rising edge on MCI1 does not affect counter 0.

3

If MODE0 is 1, counter 0 advances on a falling edge on MCI1.

A falling edge on MCI1 does not affect counter 0.

4

If MODE0 is 1, counter 0 advances on a rising edge on MCI2.

A rising edge on MCI0 does not affect counter 0.

5

If MODE0 is 1, counter 0 advances on a falling edge on MCI2.

A falling edge on MCI0 does not affect counter 0.

6

If MODE1 is 1, counter 1 advances on a rising edge on MCI0.

A rising edge on MCI0 does not affect counter 1.

7

If MODE1 is 1, counter 1 advances on a falling edge on MCI0.

A falling edge on MCI0 does not affect counter 1.

8

If MODE1 is 1, counter 1 advances on a rising edge on MCI1.

A rising edge on MCI1 does not affect counter 1.

9

If MODE1 is 1, counter 1 advances on a falling edge on MCI1.

A falling edge on MCI0 does not affect counter 1.

10

11

12

If MODE1 is 1, counter 1 advances on a rising edge on MCI2.

A rising edge on MCI2 does not affect counter 1.

If MODE1 is 1, counter 1 advances on a falling edge on MCI2.

A falling edge on MCI2 does not affect counter 1.

If MODE2 is 1, counter 2 advances on a rising edge on MCI0.

A rising edge on MCI0 does not affect counter 2.

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Table 470. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description

Bit

Symbol

Value Description

Reset

Value

13

TC2MCI0_FE

1

0

1

0

1

0

1

0

1

0

-

If MODE2 is 1, counter 2 advances on a falling edge on MCI0.

0

A falling edge on MCI0 does not affect counter 2.

If MODE2 is 1, counter 2 advances on a rising edge on MCI1.

A rising edge on MCI1 does not affect counter 2.

If MODE2 is 1, counter 2 advances on a falling edge on MCI1.

A falling edge on MCI1 does not affect counter 2.

If MODE2 is 1, counter 2 advances on a rising edge on MCI2.

A rising edge on MCI2 does not affect counter 2.

If MODE2 is 1, counter 2 advances on a falling edge on MCI2.

A falling edge on MCI2 does not affect counter 2.

Reserved.

14

15

16

17

TC2MCI1_RE

TC2MCI1_FE

TC2MCI2_RE

TC2MCI2_FE

28:18 -

-

29

30

31

CNTR0

1

0

1

0

1

0

Channel 0 is in counter mode.

0

Channel 0 is in timer mode.

CNTR1

CNTR2

Channel 1 is in counter mode.

0

Channel 1 is in timer mode.

Channel 2 is in counter mode.

Channel 2 is in timer mode.

7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)

Writing one(s) to this write-only address sets the corresponding bit(s) in MCCNTCON.

Table 471. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description

Bit

Description

31:0

Writing one(s) to this write-only address sets the corresponding bit(s) in the MCCNTCON register. See

Table 25–470.

7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)

Writing one(s) to this write-only address clears the corresponding bit(s) in MCCNTCON.

Table 472. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description

Bit

Description

31:0

Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See

Table 25–470.

7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018,

0x400B 801C, 0x400B 8020)

These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each

value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by

MCCNTCON. The timer/counter counts up from 0 until it reaches the value in its

corresponding MCPER register (or is stopped by writing to MCCON_CLR).

A TC register can be read at any time. In order to write to the TC register, its channel must

be stopped. If not, the write will not take place, no exception is generated.

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Table 473. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description

Bit

Symbol

Description

Reset value

31:0

MCTC0/1/2

Timer/Counter values for channels 0, 1, 2.

0

7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028,

0x400B 802C)

These registers hold the limiting values for timer/counters 0-2. When a timer/counter

reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts

over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which

time it begins counting up again.

If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, the match

between TC and LIM switches the channel’s A output from “active” to “passive” state. If

the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously

switches the channel’s B output from “passive” to “active” state.

If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s

deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B

output switches from “passive” to “active” state.

In center-aligned mode, matches between a channel’s TC and LIM registers have no

effect on its A and B outputs.

Writing to either a Limit or a Match (7.7) register loads a “write” register, and if the channel

is stopped it also loads an “operating” register that is compared to the TC. If the channel is

running and its “disable update” bit in MCCON is 0, the operating registers are loaded

from the write registers: 1) in edge-aligned mode, when the TC matches the operating

Limit register; 2) in center-aligned mode, when the TC counts back down to 0. If the

channel is running and the “disable update” bit is 1, the operating registers are not loaded

from the write registers until software stops the channel.

Reading an MCLIM address always returns the operating value.

Table 474. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description

Bit

Symbol

Description

Reset value

31:0

MCLIM0/1/2

Limit values for TC0, 1, 2.

0xFFFF FFFF

Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by

its Limit register, and the pulse width at the start of the period is determined by its Match

register. If it suits your way of thinking, consider the Limit register to be the “Period register”

and the Match register to be the “Pulse Width register”.

7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034,

0x400B 8038)

These registers also have “write” and “operating” versions as described above for the

Limit registers, and the operating registers are also compared to the channels’ TCs. See

7.6 above for details of reading and writing both Limit and Match registers.

The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have

any effect on its channel’s operation, it must contain a smaller value than the

corresponding Limit register.

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Table 475. MCPWM Match 0-2 registers (MCMAT0-2 - addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit

description

Bit

Symbol

Description

Reset value

31:0

MCMAT0/1/2

Match values for TC0, 1, 2.

0xFFFF FFFF

7.7.1 Match register in Edge-Aligned mode

If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, a match

between TC and MAT switches the channel’s B output from “active” to “passive” state. If

the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously

switches the channel’s A output from “passive” to “active” state.

If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s

deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A

output switches from “passive” to “active” state.

7.7.2 Match register in Center-Aligned mode

If the channel’s CENTER bit in MCCON is 1 selecting center-aligned mode, a match

between TC and MAT while the TC is incrementing switches the channel’s B output from

“active” to “passive” state, and a match while the TC is decrementing switches the A

output from “active” to “passive”. If the channel’s CENTER bit in MCCON is 1 but the DTE

bit is 0, a match simultaneously switches the channel’s other output in the opposite

direction.

If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers

the channel’s deadtime counter to begin counting -- when the deadtime counter expires,

the channel’s B output switches from “passive” to “active” if the TC was counting up at the

time of the match, and the channel’s A output switches from “passive” to “active” if the TC

was counting down at the time of the match.

7.7.3 0 and 100% duty cycle

To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register

with a higher value than you write to its Limit register. The match never occurs.

To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write

0 to its Match register.

7.8 MCPWM Dead-time register (MCDT - 0x400B 803C)

This register holds the dead-time values for the three channels. If a channel’s DTE bit in

MCCON is 1 to enable its dead-time counter, the counter counts down from this value

whenever one its channel’s outputs changes from “active” to “passive” state. When the

dead-time counter reaches 0, the channel changes its other output from “passive” to

“active” state.

The motivation for the dead-time feature is that power transistors, like those driven by the

A and B outputs in a motor-control application, take longer to fully turn off than they take to

start to turn on. If the A and B transistors are ever turned on at the same time, a wasteful

and damaging current will flow between the power rails through the transistors. In such

applications, the dead-time register should be programmed with the number of PCLK

periods that is greater than or equal to the transistors’ maximum turn-off time minus their

minimum turn-on time.

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Table 476. MCPWM Dead-time register (MCDT - address 0x400B 803C) bit description

Bit

Symbol

DT0

DT1

DT2

-

Description

Reset value

0x3FF

9:0

Dead time for channel 0.^[1]

Dead time for channel 1.^[2]

Dead time for channel 2.^[2]

reserved

19:10

29:20

31:30

0x3FF

[1] If ACMODE is 1 selecting AC-mode, this field controls the dead time for all three channels.

[2] If ACMODE is 0.

7.9 MCPWM Commutation Pattern register (MCCP - 0x400B 8040)

This register is used in DC mode only. The internal MCOA0 signal is routed to any or all of

the six output pins under the control of the bits in this register. Like the Match and Limit

registers, this register has “write” and “operational” versions. See 7.6 and 8.2 for more

about this subject.

Table 477. MCPWM Commutation Pattern register (MCCP - address 0x400B 8040) bit description

Bit

0

Symbol

CCPA0

CCPB0

CCPA1

CCPB1

CCPA2

CCPB2

-

Description

Reset value

0 = MCOA0 passive, 1 = internal MCOA0.

0 = MCOB0 passive, 1 = MCOB0 tracks internal MCOA0.

0 = MCOA1 passive, 1 = MCOA1 tracks internal MCOA0.

0 = MCOB1 passive, 1 = MCOB1 tracks internal MCOA0.

0 = MCOA2 passive, 1 = MCOA2 tracks internal MCOA0.

0 = MCOB2 passive, 1 = MCOB2 tracks internal MCOA0.

Reserved.

0

1

2

3

4

5

31:6

7.10 MCPWM Capture Registers

7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048,

0x400B 804C)

The MCCAPCON register (Table 25–459) allows software to select any edge(s) on any of

the MCI0-2 inputs as a capture event for each channel. When a channel’s capture event

occurs, the current TC value for that channel is stored in its read-only Capture register.

These addresses are read-only, but the underlying registers can be cleared by writing to

the CAP_CLR address

Table 478. MCPWM Capture read addresses (MCCAP0/1/2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description

Bit

Symbol

Description

Reset value

31:0

CAP0/1/2

TC value at a capture event for channels 0, 1, 2.

0x0000 0000

7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8074)

Writing ones to this write-only address clears the selected CAP register(s).

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Table 479. MCPWM Capture clear address (CAP_CLR - 0x400B 8074) bit description

Bit

0

Symbol

CAP_CLR0

CAP_CLR1

CAP_CLR2

-

Description

Writing a 1 to this bit clears the MCCAP0 register.

Writing a 1 to this bit clears the MCCAP1 register.

Writing a 1 to this bit clears the MCCAP2 register.

Reserved

1

2

31:3

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8. PWM operation

8.1 Pulse-width modulation

Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors

to switch a controlled point between two power rails. Most of the time the two outputs have

opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to

delay both signals’ transitions from “passive” to “active” state so that the transistors are

never both turned on simultaneously. In a more general view, the states of each output

pair can be thought of “high”, “low”, and “floating” or “up”, “down”, and “center-off”.

Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable.

After Reset, the three A outputs are passive/low, and the B outputs are active/high.

The MCPWM can perform edge-aligned and center-aligned pulse-width modulation.

Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by

its Limit register, and the pulse width at the start of the period is determined by its Match

register. If it suits your way of thinking, consider the Limit register to be the “Period register”

and the Match register to be the “Pulse Width register”.

Edge-aligned PWM without dead-time

In this mode the timer TC counts up from 0 to the value in the LIM register. As shown in

Figure 25–121, the MCO state is “A passive” until the TC matches the Match register, at

which point it changes to “A active”. When the TC matches the Limit register, the MCO

state changes back to “A passive”, and the TC is reset and starts counting up again.

active

passive

active

passive

MCOB

MCOA

passive

active

passive

active

POLA = 0

0

MAT

LIM

timer reset

MAT

LIM

timer reset

Fig 121. Edge-aligned PWM waveform without dead time, POLA = 0

Center-aligned PWM without dead-time

In this mode the timer TC counts up from 0 to the value in the LIM register, then counts

back down to 0 and repeats. As shown in Figure 25–122, while the timer counts up, the

MCO state is “A passive” until the TC matches the Match register, at which point it

changes to “A active”. When the TC matches the Limit register it starts counting down.

When the TC matches the Match register on the way down, the MCO state changes back

to “A passive”.

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active

passive

active

LIM

passive

MCOB

MCOA

passive

active

POLA = 0

0

MAT

LIM

Fig 122. Center-aligned PWM waveform without dead time, POLA = 0

Dead-time counter

When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the

passive-to-active transitions of both MCO outputs. The dead-time counter starts counting

down, from the channel’s DT value (in the MCDT register) to 0, whenever the channel’s A

or B output changes from active to passive. The transition of the other output from passive

to active is delayed until the dead-time counter reaches 0. During the dead time, the

MCOA and MCOB output levels are both passive. Figure 25–123 shows operation in edge

aligned mode with dead time, and Figure 25–124 shows center-aligned operation with

dead time.

active

passive

MCOB

DT

active

passive

MCOA

POLA = 0

DT

0

MAT

LIM

timer reset

MAT

LIM

timer reset

Fig 123. Edge-aligned PWM waveform with dead time, POLA = 0

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active

passive

MCOB

DT

active

passive

POLA = 0

MCOA

DT

LIM

DT

0

MAT

LIM

Fig 124. Center-aligned waveform with dead time, POLA = 0

8.2 Shadow registers and simultaneous updates

The Limit, Match, and Commutation Pattern registers (MCLIM, MCMAT, and MCCP) are

implemented as register pairs, each consisting of a write register and an operational

register. Software writes into the write registers. The operational registers control the

actual operation of each channel and are loaded with the current value in the write

registers when the TC starts counting up from 0.

Updating of the functional registers can be disabled by setting a channel’s DISUP bit in

the MCCON register. If the DISUP bits are set, the functional registers are not updated

until software stops the channel.

If a channel is not running when software writes to its LIM or MAT register, the functional

register is updated immediately.

Software can write to a TC register only when its channel is stopped.

8.3 Fast Abort (ABORT)

The MCPWM has an external input MCABORT. When this input goes low, all six MCO

outputs assume their “A passive” states, and the Abort interrupt is generated if enabled.

The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or

the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT

input goes high.

In order to clear an ABORT flag, a 1 must be written to bit 15 of the MCINTF_CLR

register. This will remove the interrupt request. The interrupt can also be disabled by

writing a 1 to bit 15 of the MCINTEN_CLR register.

8.4 Capture events

Each PWM channel can take a snapshot of its TC when an input signal transitions. Any

channel may use any combination of rising and/or falling edges on any or all of the MCI0-2

inputs as a capture event, under control of the MCCAPCON register. Rising or falling

edges on the inputs are detected synchronously with respect to PCLK.

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If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a

selected edge on an MCI pin starts the dead-time counter for that channel, and the

capture event actions described below are delayed until the dead-time counter reaches 0.

This function is targeted specifically for performing three-phase brushless DC motor

control with Hall sensors.

A capture event on a channel (possibly delayed by HNF) causes the following:

• The current value of the TC is stored in the Capture register (CAP).

• If the channel’s capture event interrupt is enabled (see Table 25–464), the capture

event interrupt flag is set.

• If the channel’s RT bit is set in the MCCAPCON register, enabling reset on a capture

event, the input event has the same effect as matching the channel’s TC to its LIM

register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned

mode as described in 7.6 and 8.1.

8.5 External event counting (Counter mode)

If a channel’s MODE bit is 1 in MCCNTCON, its TC is incremented by rising and/or falling

edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM

functions and capture functions are unaffected.

8.6 Three-phase DC mode

The three-phase DC mode is selected by setting the DCMODE bit in the MCCON register.

In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.

Each MCO output is masked by a bit in the current Commutation Pattern register MCCP. If

a bit in the MCCP register is 0, its output pin has the logic level for the passive state of

output MCOA0. The polarity of the off state is determined by the POLA0 bit.

All MCO outputs that have 1 bits in the MCCP register are controlled by the internal

MCOA0 signal.

The three MCOB output pins are inverted when the INVBDC bit is 1 in the MCCON

register. This feature accommodates bridge-drivers that have active-low inputs for the

low-side switches.

The MCCP register is implemented as a shadow register pair, so that changes to the

active commutation pattern occur at the beginning of a new PWM cycle. See 7.6 and 8.2

for more about writing and reading such registers.

Figure 25–125 shows sample waveforms of the MCO outputs in three-phase DC mode.

Bits 1 and 3 in the MCCP register (corresponding to outputs MCOB1 and MCOB0) are set

to 0 so that these outputs are masked and in the off state. Their logic level is determined

by the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is

set to 0 (logic level not inverted) so that the B output have the same polarity as the A

outputs. Note that this mode differs from other modes in that the MCOB outputs are not

the opposite of the MCOA outputs.

In the situation shown in Figure 25–125, bits 0, 2, 4, and 5 in the MCCP register are set to

1. That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0

signal.

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MCOB2

CCPB2 = 1, on-state

CCPA2 = 1, on-state

MCOA2

MCOB1

CCPB1 = 0, off-state

CCPA1 = 1, on-state

CCPB0 = 0, off-state

MCOA1

MCOB0

MCOA0

CCPA0 = 1, on-state

POLA0 = 0, INVBDC = 0

Fig 125. Three-phase DC mode sample waveforms

8.7 Three phase AC mode

The three-phase AC-mode is selected by setting the ACMODE bit in the MCCON register.

In this mode, the value of channel 0’s TC is routed to all channels for comparison with

their MAT registers. (The LIM1-2 registers are not used.)

Each channel controls its MCO output by comparing its MAT value to TC0.

Figure 25–126 shows sample waveforms for the six MCO outputs in three-phase AC

mode. The POLA bits are set to 0 for all three channels, so that for all MCO outputs the

active levels are high and the passive levels are low. Each channel has a different MAT

value which is compared to the MCTC0 value. In this mode the period value is identical for

all three channels and is determined by MCLIM0. The dead-time mode is disabled.

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MCOB2

POLA2 = 0

MCOA2

MCOB1

MAT2

POLA1 = 0

MCOA1

MCOB0

MCOA0

MAT1

POLA0 = 0

0

MAT0

LIM0

timer reset

LIM0

timer reset

Fig 126. Three-phase AC mode sample waveforms, edge aligned PWM mode

8.8 Interrupts

The MCPWM includes 10 possible interrupt sources:

• When any channel’s TC matches its Match register.

• When any channel’s TC matches its Limit register.

• When any channel captures the value of its TC into its Capture register, because a

selected edge occurs on any of MCI0-2.

• When all three channels’ outputs are forced to “A passive” state because the

MCABORT pin goes low.

Section 25–7.3 “MCPWM Interrupt registers” explains how to enable these interrupts, and

Section 25–7.2 “MCPWM Capture Control register” describes how to map edges on the

MCI0-2 inputs to “capture events” on the three channels.

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Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)

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User manual

1. Basic configuration

The QEI is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCQEI.

Remark: On reset, the QEI is disabled (PCQEI = 0).

2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_QEI.

3. Pins: Select QEI pins through the PINSEL registers. Select pin modes for port pins

with QEI functions through the PINMODE registers (Section 8–5).

4. Interrupts: See Section 26–6.4. The QEI interrupt is enabled in the NVIC using the

appropriate Interrupt Set Enable register.

2. Features

This Quadrature Encoder Interface (QEI) has the following features:

• tracks encoder position.

• increments/ decrements depending on direction.

• programmable for 2X or 4X position counting.

• velocity capture using built-in timer.

• velocity compare function with less than interrupt.

• uses 32-bit registers for position and velocity.

• three position compare registers with interrupts.

• index counter for revolution counting.

• index compare register with interrupts.

• can combine index and position interrupts to produce an interrupt for whole and partial

revolution displacement.

• digital filter with programmable delays for encoder input signals.

• can accept decoded signal inputs (clock and direction).

3. Introduction

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, you can track the position, direction of rotation, and

velocity. In addition, a third channel, or index signal, can be used to reset the position

counter. This quadrature encoder interface module decodes the digital pulses from a

quadrature encoder wheel to integrate position over time and determine direction of

rotation. In addition, it can capture the velocity of the encoder wheel.

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VELOCITY

TIMER

velocity interrupt

(TIM_Int)

VELOCITY

RELOAD

low velocity interrupt

(LVEL_Int)

VELOCITY

COMPARE

RST

VELOCITY

CAPTURE

index

RST

CLK

Ph A

VELOCITY

COUNTER

DIGITAL

FILTER

QUAD

DECODER

Ph B

PCLK

encoder clock interrupt

(ENCLK_Int)

position 0 interrupt

(POS0_Int)

POSITION

COMPARE 0

CLK

DIR

INX

POSITION

COUNTER

position 1 interrupt

(POS1_Int)

POSITION

COMPARE 1

direction interrupt

(DIR_Int)

INDEX

COUNTER

INDEX

COMPARE

revolution interrupt

(REV_Int)

index interrupt

(INX_Int)

ERR

phase error interrupt

(ERR_Int)

002aad520

Fig 127.Encoder interface block diagram

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4. Functional description

The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel

to integrate position over time and determine direction of rotation. In addition, it can

capture the velocity of the encoder wheel.

4.1 Input signals

The QEI module supports two modes of signal operation: quadrature phase mode and

clock/direction mode. In quadrature phase mode, the encoder produces two clocks that

are 90 degrees out of phase; the edge relationship is used to determine the direction of

rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps

and a direction signal to indicate the direction of rotation.).

This mode is determined by the SigMode bit of the QEI Control (QEICON) register (See

Table 26–485). When the SigMode bit = 1, the quadrature decoder is bypassed and the

PhA pin functions as the direction signal and PhB pin functions as the clock signal for the

counters, etc. When the SigMode bit = 0, the PhA pin and PhB pins are decoded by the

quadrature decoder. In this mode the quadrature decoder produces the direction and

clock signals for the counters, etc. In both modes the direction signal is subject to the

effects of the direction invert (DIRINV) bit.

4.1.1 Quadrature input signals

When edges on PhA lead edges on PhB, the position counter is incremented. When

edges on PhB lead edges on PhA, the position counter is decremented. When a rising

and falling edge pair is seen on one of the phases without any edges on the other, the

direction of rotation has changed.

Table 480. Encoder states

Phase A

Phase B

state

1

0

1

0

1

2

3

4

Table 481. Encoder state transitions^[1]

from state

to state

Direction

1

2

3

4

3

2

1

2

3

4

1

3

2

1

4

positive

negative

[1] All other state transitions are illegal and should set the ERR bit.

Interchanging of the PhA and PhB input signals are compensated by complementing the

DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit.

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Table 482. Encoder direction

DIR bit

DIRINV bit

direction

forward

reverse

forward

0

1

0

1

0

1

Figure 26–128 shows how quadrature encoder signals equate to direction and count.

PhA

PhB

direction

position

-1 -1 -1 -1 -1 -1 -1 -1 -1

+1 +1 +1 +1 +1 +1 +1 +1

-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

Fig 128.Quadrature Encoder Basic Operation

4.1.2 Digital input filtering

All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of

sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF). In order for

a transition to be accepted, the input signal must remain in new state for the programmed

number of sample clocks.

4.2 Position capture

The capture mode for the position integrator can be set to update the position counter on

every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating

the position counter on every PhA and PhB provides more positional resolution at the cost

of less range in the positional counter.

The position integrator and velocity capture can be independently enabled. Alternatively,

the phase signals can be interpreted as a clock and direction signal as output by some

encoders.

The position counter is automatically reset on one of two conditions. Incrementing past

the maximum position value (QEIMAXPOS) will reset the position counter to zero. If the

reset on index bit (RESPI) is set, sensing the index pulse will reset the position counter to

zero.

4.3 Velocity capture

The velocity capture has a programmable timer and a capture register. It counts the

number of phase edges (using the same configuration as for the position integrator) in a

given time period. When the velocity timer (QEITIME) overflows the contents of the

velocity counter (QEIVEL) are transferred to the capture (QEICAP) register. The velocity

counter is then cleared. The velocity timer is loaded with the contents of the velocity

reload register (QEILOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The

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number of edges counted in a given time period is directly proportional to the velocity of

the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of

the velocity timer, except that the setting the RESV bit will not generate a velocity

interrupt.

The following equation converts the velocity counter value into an RPM value:

RPM

= (PCLK * QEICAP * 60) ÷ (QEILOAD * PPR * Edges)

where:

• PCLK is the peripheral clock rate for the QEI block. See Section 4–7.3 for more on

the possibilities for PCLK).

• QEICAP is the captured velocity counter value for the last velocity timer period.

• QEILOAD is the velocity timer reload value.

• PPR is the number of pulses per revolution of the physical encoder used in the

application

• Edges is 2 or 4, based on the capture mode set in the QEICON register (2 for

CapMode set to 0 and 4 for CapMode set to 1)

For example, consider a motor running at 600 RPM. A 2048 pulse per revolution

quadrature encoder is attached to the motor, producing 8192 phase edges per revolution

(PPR * Edges). This results in 81,920 pulses per second (the motor turns 10 times per

second at 600 RPM and there are 8092 edges per revolution). If the timer were clocked at

10,000 Hz, and the QEILOAD was 2,500 (corresponding to ¼ of a second), it would count

20,480 pulses per update. Using the above equation:

RPM = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 RPM

Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per

second, or 102,400 every ¼ of a second. Again, the above equation gives:

RPM = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 RPM

These are simple examples, real-world values will have a higher rate for PCLK, and

probably a larger value for QEILOAD as well.

4.4 Velocity compare

In addition to velocity capture, the velocity measurement system includes a

programmable velocity compare register. After every velocity capture event the contents

of the velocity capture register (QEICAP) is compared with the contents of the velocity

compare register (VELCOMP). If the captured velocity is less than the compare value an

interrupt is asserted provided that the velocity compare interrupt enable bit is set. This can

be used to determine if a motor shaft is either stalled or moving too slow.

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5. Pin description

Table 483. QEI pin description

Pin name

I/O

Description

MCI0 ^[1]

MCI1 ^[1]

MCI2 ^[1]

I

Used as the Phase A (PhA) input to the Quadrature Encoder Interface.

Used as the Phase B (PhB) input to the Quadrature Encoder Interface.

Used as the Index (IDX) input to the Quadrature Encoder Interface.

[1] The Quadrature Encoder Interface uses the same pin functions as the Motor Control PWM feedback inputs

and are connected when the Motor Control PWM function is selected on these pins. If used as part of motor

control, the QEI is an alternative to feedback directly to the MCPWM.

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6. Register description

6.1 Register summary

Table 484. QEI Register summary

Name

Description

Access

Reset

value

Address

Control registers

QEICON

Control register

WO

R/W

RO

0

0x400B C000

0x400B C008

0x400B C004

QEICONF

Configuration register

Encoder status register

QEISTAT

Position, index, and timer registers

QEIPOS

Position register

RO

0

0x400B C00C

0x400B C010

0x400B C014

0x400B C018

0x400B C01C

0x400B C020

0x400B C024

0x400B C028

0x400B C02C

0x400B C030

0x400B C034

0x400B C038

0x400B C03C

QEIMAXPOS

CMPOS0

CMPOS1

CMPOS2

INXCNT

Maximum position register

position compare register 0

position compare register 1

position compare register 2

Index count register

R/W

RO

INXCMP

QEILOAD

QEITIME

QEIVEL

Index compare register

Velocity timer reload register

Velocity timer register

R/W

RO

Velocity counter register

Velocity capture register

Velocity compare register

Digital filter register

RO

QEICAP

RO

VELCOMP

FILTER

R/W

Interrupt registers

QEIINTSTAT

QEISET

Interrupt status register

RO

WO

RO

0

0x400B CFE0

0x400B CFEC

0x400B CFE8

0x400B CFE4

0x400B CFDC

0x400B CFD8

Interrupt status set register

Interrupt status clear register

Interrupt enable register

QEICLR

QEIIE

QEIIES

Interrupt enable set register

Interrupt enable clear register

WO

QEIIEC

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6.2 Control registers

6.2.1 QEI Control register (QEICON - 0x400B C000)

This register contains bits which control the operation of the position and velocity counters

of the QEI module.

Table 485: QEI Control register (QEICON - address 0x400B C000) bit description

Bit

Symbol

RESP

RESPI

RESV

RESI

-

Description

Reset

value

0

Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when

the position counter is cleared.

0

1

Reset position counter on index. When set = 1, resets the position counter to all zeros when an

index pulse occurs. Autoclears when the position counter is cleared.

2

Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity

timer. Autoclears when the velocity counter is cleared.

3

Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the

index counter is cleared.

31:4

reserved

6.2.2 QEI Configuration register (QEICONF - 0x400B C008)

This register contains the configuration of the QEI module.

Table 486: QEI Configuration register (QEICONF - address 0x400B C008) bit description

Bit

Symbol

Description

Reset

value

0

1

DIRINV

Direction invert. When = 1, complements the DIR bit.

0

SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA

functions as the direction signal and PhB functions as the clock signal.

2

CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB

edges are counted (4X), increasing resolution but decreasing range.

0

3

INVINX

-

Invert Index. When set, inverts the sense of the index input.

reserved

0

31:4

6.2.3 QEI Status register (QEISTAT - 0x400B C004)

This register provides the status of the encoder interface.

Table 487: QEI Interrupt Status register (QEISTAT - address 0x400B C004) bit description

Bit

Symbol

Description

Reset

value

0

DIR

-

Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See

Table 26–482.

31:1

reserved

0

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6.3 Position, index and timer registers

6.3.1 QEI Position register (QEIPOS - 0x400B C00C)

This register contains the current value of the encoder position. Increments or decrements

when encoder counts occur, depending on the direction of rotation.

Table 488: QEI Position register (QEIPOS - address 0x400B C00C) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

6.3.2 QEI Maximum Position register (QEIMAXPOS - 0x400B C010)

This register contains the maximum value of the encoder position. In forward rotation the

position register resets to zero when the position register exceeds this value. In reverse

rotation the position register resets to this value when the position register decrements

from zero.

Table 489: QEI Maximum Position register (QEIMAXPOS - address 0x400B C010) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current maximum position value.

0

6.3.3 QEI Position Compare register 0 (CMPOS0 - 0x400B C014)

This register contains a position compare value. This value is compared against the

current value of the position register. Interrupts can be enabled to interrupt when the

compare value is equal to the current value of the position register.

Table 490: QEI Position Compare register 0 (CMPOS0 - address 0x400B C014) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

6.3.4 QEI Position Compare register 1 (CMPOS1 - 0x400B C018)

This register contains a position compare value. This value is compared against the

current value of the position register. Interrupts can be enabled to interrupt when the

compare value is equal to the current value of the position register.

Table 491: QEI Position Compare register 1 (CMPOS1 - address 0x400B C018) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

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6.3.5 QEI Position Compare register 2 (CMPOS2 - 0x400B C01C)

This register contains a position compare value. This value is compared against the

current value of the position register. Interrupts can be enabled to interrupt when the

compare value is equal to the current value of the position register.

Table 492: QEI Position Compare register 2 (CMPOS2 - address 0x400B C01C) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

6.3.6 QEI Index Count register (INXCNT - 0x400B C020)

This register contains the current value of the encoder position. Increments or decrements

when encoder counts occur, depending on the direction of rotation.

Table 493: QEI Index Count register (CMPOS - address 0x400B C020) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

6.3.7 QEI Index Compare register (INXCMP - 0x400B C024)

This register contains an index compare value. This value is compared against the current

value of the index count register. Interrupts can be enabled to interrupt when the compare

value is equal to the current value of the index count register.

Table 494: QEI Index Compare register (CMPOS - address 0x400B C024) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current position value.

0

6.3.8 QEI Timer Reload register (QEILOAD - 0x400B C028)

This register contains the reload value of the velocity timer. When the timer (QEITIME)

overflows or the RESV bit is asserted, this value is loaded into the timer (QEITIME).

Table 495: QEI Timer Load register (QEILOAD - address 0x400B C028) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current velocity timer load value.

0

6.3.9 QEI Timer register (QEITIME - 0x400B C02C)

This register contains the current value of the velocity timer. When this timer overflows the

value of velocity counter (QEIVEL) is stored in the velocity capture register (QEICAP), the

velocity counter is reset to zero, the timer is reloaded with the value stored in the velocity

reload register (QEILOAD), and the velocity interrupt (TIM_Int) is asserted.

Table 496: QEI Timer register (QEITIME - address 0x400B C02C) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current velocity timer value.

0

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6.3.10 QEI Velocity register (QEIVEL - 0x400B C030)

This register contains the running count of velocity pulses for the current time period.

When the velocity timer (QEITIME) overflows the contents of this register is captured in

the velocity capture register (QEICAP). After capture, this register is set to zero. This

register is also reset when the velocity reset bit (RESV) is asserted.

Table 497: QEI Velocity register (QEIVEL - address 0x400B C030) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current velocity pulse count.

0

6.3.11 QEI Velocity Capture register (QEICAP - 0x400B C034)

This register contains the most recently measured velocity of the encoder. This

corresponds to the number of velocity pulses counted in the previous velocity timer

period.The current velocity count is latched into this register when the velocity timer

overflows.

Table 498: QEI Velocity Capture register (QEICAP - address 0x400B C034) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current velocity pulse count.

0

6.3.12 QEI Velocity Compare register (VELCOMP - 0x400B C038)

This register contains a velocity compare value. This value is compared against the

captured velocity in the velocity capture register. If the capture velocity is less than the

value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if

enabled.

Table 499: QEI Velocity Compare register (VELCOMP - address 0x400B C038) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Current velocity pulse count.

0

6.3.13 QEI Digital Filter register (FILTER - 0x400B C03C)

This register contains the sampling count for the digital filter. A sampling count of zero

bypasses the filter.

Table 500: QEI Digital Filter register (FILTER - address 0x400B C03C) bit description

Bit

Symbol

Description

Reset

value

31:0

-

Digital filter sampling delay

0x0

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6.4 Interrupt registers

6.4.1 QEI Interrupt Status register (QEIINTSTAT)

This register provides the status of the encoder interface and the current set of interrupt

sources that are asserted to the controller. Bits set to 1 indicate the latched events that

have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0

to a bit position clears the corresponding interrupt.

Table 501: QEI Interrupt Status register (QEIINTSTAT - address 0x400B CFE0) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

10

INX_Int

Indicates that an index pulse was detected.

0

TIM_Int

Indicates that a velocity timer overflow occurred

VELC_Int

DIR_Int

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

ERR_Int

ENCLK_Int

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that an encoder phase error was detected.

Indicates that and encoder clock pulse was detected.

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

0

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

0

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

6.4.2 QEI Interrupt Set register (QEISET - 0x400B CFEC)

Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status

register (QEISTAT).

Table 502: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

INX_Int

Indicates that an index pulse was detected.

0

TIM_Int

Indicates that a velocity timer overflow occurred

VELC_Int

DIR_Int

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

ERR_Int

ENCLK_Int

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that an encoder phase error was detected.

Indicates that and encoder clock pulse was detected.

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

0

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Table 502: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description

Bit

Symbol

Description

Reset

value

10

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

0

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

6.4.3 QEI Interrupt Clear register (QEICLR - 0x400B CFE8)

Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status

register (QEISTAT).

Table 503: QEI Interrupt Clear register (QEICLR - 0x400B CFE8) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

10

INX_Int

Indicates that an index pulse was detected.

0

TIM_Int

Indicates that a velocity timer overflow occurred

VELC_Int

DIR_Int

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

ERR_Int

ENCLK_Int

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that an encoder phase error was detected.

Indicates that and encoder clock pulse was detected.

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

0

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

0

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

6.4.4 QEI Interrupt Enable register (QEIIE - 0x400B CFE4)

This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a

0 bit disables the corresponding interrupt.

Table 504: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

INX_Int

TIM_Int

VELC_Int

DIR_Int

Indicates that an index pulse was detected.

0

Indicates that a velocity timer overflow occurred

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

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Table 504: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description

Bit

Symbol

Description

Reset

value

4

ERR_Int

Indicates that an encoder phase error was detected.

0

5

ENCLK_Int

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that and encoder clock pulse was detected.

6

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

7

8

9

10

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

0

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

6.4.5 QEI Interrupt Enable Set register (QEIIES - 0x400B CFDC)

Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable

register (QEIIE).

Table 505: QEI Interrupt Enable Set register (QEIIES - address 0x400B CFDC) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

10

INX_EN

Indicates that an index pulse was detected.

0

TIM_EN

Indicates that a velocity timer overflow occurred

VELC_EN

DIR_EN

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

ERR_EN

ENCLK_EN

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that an encoder phase error was detected.

Indicates that and encoder clock pulse was detected.

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

0

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

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6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8)

Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable

register (QEIIE).

Table 506: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description

Bit

Symbol

Description

Reset

value

0

1

2

3

4

5

6

7

8

9

10

INX_EN

Indicates that an index pulse was detected.

0

TIM_EN

Indicates that a velocity timer overflow occurred

VELC_EN

DIR_EN

Indicates that captured velocity is less than compare velocity.

Indicates that a change of direction was detected.

ERR_EN

ENCLK_EN

POS0_Int

POS1_Int

POS2_Int

REV_Int

Indicates that an encoder phase error was detected.

Indicates that and encoder clock pulse was detected.

Indicates that the position 0 compare value is equal to the current position.

Indicates that the position 1compare value is equal to the current position.

Indicates that the position 2 compare value is equal to the current position.

Indicates that the index compare value is equal to the current index count.

POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set

and the REV_Int is set.

11

POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set

and the REV_Int is set.

0

12

POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set

and the REV_Int is set.

31:13

-

reserved

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1. Basic configuration

The RTC is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bits PCRTC.

Remark: On reset, the RTC is enabled. See Section 27–7 for power saving options.

2. Clock: The RTC uses the 1 Hz clock output from the RTC oscillator as the only clock

source. The peripheral clock rate for accessing registers is CCLK/8.

3. Interrupts: See Section 27–6.1 for RTC interrupt handling. Interrupts are enabled in

the NVIC using the appropriate Interrupt Set Enable register.

2. Features

• Measures the passage of time to maintain a calendar and clock. Provides seconds,

minutes, hours, day of month, month, year, day of week, and day of year.

• Ultra-low power design to support battery powered systems. Less than 1 microamp

required for battery operation. Uses power from the CPU power supply when it is

present.

• 20 bytes of Battery-backed storage and RTC operation when power is removed from

the CPU.

• Dedicated 32 kHz ultra low power oscillator.

• Dedicated battery power supply pin.

• RTC power supply is isolated from the rest of the chip.

• Calibration counter allows adjustment to better than ±1 sec/day with 1 sec resolution.

• Periodic interrupts can be generated from increments of any field of the time registers

and selected fractional second values.

• Alarm interrupt can be generated for a specific date/time.

3. Description

The Real Time Clock (RTC) is a set of counters for measuring time when system power is

on, and optionally when it is off. It uses very little power when its registers are not being

accessed by the CPU, especially reduced power modes. On the LPC17xx, the RTC is

clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The

RTC is powered by its own power supply pin, VBAT, which can be connected to a battery,

externally tied to a 3V supply, or left floating.

The RTC power domain is shown in conceptual form in Figure 27–129. A detailed view of

the time keeping portion of the RTC is shown in Figure 27–130.

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4. Architecture

V_DD(REG)(3v3)pin

to main regulator

RTC power domain

Ultra-low

Power

selector

Backup

Registers

power

regulator

V_BATpin

RTCX1

RTC power

Ultra-low

power

oscillator

1 Hz clock

Real Time Clock

Functional Block

RTC Alarm

& Interrupt

RTCX2

Fig 129. RTC domain conceptual diagram

Alarm Registers

second

minute

hour

day

month

year

Alarm out

and Alarm

Interrupts

alarm compare

1 Hz

Clock

Counter

Increment

Interrupts

second

minute

hour

day

LSB LSB

day of

week

Time Registers

out

set

day of

year

sign

Calibration

bit

calibration compare register

calibration compare

match

calibration

control

logic

counter

reset

calibration counter

Fig 130. RTC functional block diagram

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5. Pin description

Table 507. RTC pin description

Name

Type

Description

RTCX1

RTCX2

I

Input to the RTC oscillator circuit.

O

Output from the RTC oscillator circuit.

Remark: If the RTC is not used, the RTCX1/2 pins can be left floating.

V_BAT

I

RTC power supply: Typically connected to an external 3V battery. If this pin is not

powered, the RTC is still powered internally if V_DD(REG)(3V3)is present.

6. Register description

The RTC includes a number of registers, shown in Table 27–508. Detailed descriptions of

the registers follow. In these descriptions, for most of the registers the Reset Value column

shows "NC", meaning that these registers are Not Changed by a Reset. Software must

initialize these registers between power-on and setting the RTC into operation. The

registers are split into five sections by functionality.

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Table 508. Real-Time Clock register map

Name Description

Access

Reset

Value^[1]

Address

Miscellaneous registers (see Section 27–6.2)

ILR

Interrupt Location Register

Clock Control Register

R/W

0

0x4002 4000

0x4002 4008

0x4002 400C

0x4002 4010

0x4002 405C

0x4002 4058

CCR

NC

0

CIIR

Counter Increment Interrupt Register

Alarm Mask Register

AMR

0

RTC_AUX

RTC_AUXEN

RTC Auxiliary control register

RTC Auxiliary Enable register

0x8

0

Consolidated time registers (see Section 27–6.3)

CTIME0

CTIME1

CTIME2

Consolidated Time Register 0

Consolidated Time Register 1

Consolidated Time Register 2

RO

NC

0x4002 4014

0x4002 4018

0x4002 401C

Time counter registers (see Section 27–6.4)

SEC

Seconds Counter

Minutes Register

R/W

NC

0x4002 4020

0x4002 4024

0x4002 4028

0x4002 402C

0x4002 4030

0x4002 4034

0x4002 4038

0x4002 403C

0x4002 4040

MIN

HOUR

DOM

Hours Register

Day of Month Register

Day of Week Register

Day of Year Register

Months Register

DOW

DOY

MONTH

YEAR

CALIBRATION

Years Register

Calibration Value Register

General purpose registers (see Section 27–6.6)

GPREG0

GPREG1

GPREG2

GPREG3

GPREG4

General Purpose Register 0

General Purpose Register 1

General Purpose Register 2

General Purpose Register 3

General Purpose Register 4

R/W

NC

0x4002 4044

0x4002 4048

0x4002 404C

0x4002 4050

0x4002 4054

Alarm register group (see Section 27–6.7)

ALSEC

ALMIN

Alarm value for Seconds

Alarm value for Minutes

Alarm value for Hours

R/W

NC

0x4002 4060

0x4002 4064

0x4002 4068

0x4002 406C

0x4002 4070

0x4002 4074

0x4002 4078

0x4002 407C

ALHOUR

ALDOM

ALDOW

ALDOY

ALMON

ALYEAR

Alarm value for Day of Month

Alarm value for Day of Week

Alarm value for Day of Year

Alarm value for Months

Alarm value for Year

[1] Reset values apply only to a power-up of the RTC block, other types of reset have no effect on this block.

Since the RTC is powered whenever either of the V_DD(REG)(3V3), or V_BATsupplies are present, power-up

reset occurs only when both supplies were absent and then one is turned on. Most registers are not

affected by power-up of the RTC and must be initialized by software if the RTC is enabled. The Reset Value

reflects the data stored in used bits only. It does not include reserved bits content.

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6.1 RTC interrupts

Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter

Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register

(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR

separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the

time counters. If CIIR is enabled for a particular counter, then every time the counter is

incremented an interrupt is generated. The alarm registers allow the user to specify a date

and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm

compares. If all non-masked alarm registers match the value in their corresponding time

counter, then an interrupt is generated.

The RTC interrupt can bring the microcontroller out of Power-down mode when the RTC

is operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is

enabled for wake-up and its selected event occurs, the oscillator wake-up cycle

associated with the XTAL1/2 pins is started. For details on the RTC based wake-up

process see Section 4–8.8 “Wake-up from Reduced Power Modes” on page 63 and

Section 4–9 “Wake-up timer” on page 66.

6.2 Miscellaneous register group

6.2.1 Interrupt Location Register (ILR - 0x4002 4000)

The Interrupt Location Register is a 2-bit register that specifies which blocks are

generating an interrupt (see Table 27–509). Writing a one to the appropriate bit clears the

corresponding interrupt. Writing a zero has no effect. This allows the programmer to read

this register and write back the same value to clear only the interrupt that is detected by

the read.

Table 509. Interrupt Location Register (ILR - address 0x4002 4000) bit description

Bit

Symbol

Description

Reset

value

0

RTCCIF

When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit

location clears the counter increment interrupt.

0

1

RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the

alarm interrupt.

0

31:21 -

Reserved, user software should not write ones to reserved bits. The value read from a reserved NA

bit is not defined.

6.2.2 Clock Control Register (CCR - 0x4002 4008)

The clock register is a 4-bit register that controls the operation of the clock divide circuit.

Each bit of the clock register is described in Table 27–510. All NC bits in this register

should be initialized when the RTC is first turned on.

Table 510. Clock Control Register (CCR - address 0x4002 4008) bit description

Bit

Symbol

Value Description

Reset

value

0

CLKEN

Clock Enable.

NC

1

0

The time counters are enabled.

The time counters are disabled so that they may be initialized.

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Table 510. Clock Control Register (CCR - address 0x4002 4008) bit description

Bit

Symbol

Value Description

Reset

value

1

CTCRST

CTC Reset.

0

1

0

When one, the elements in the internal oscillator divider are reset, and remain reset until

CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the

32.768 kHz crystal. The state of the divider is not visible to software.

No effect.

3:2

4

-

Internal test mode controls. These bits must be 0 for normal RTC operation.

Calibration counter enable.

NC

CCALEN

1

0

The calibration counter is disabled and reset to zero.

The calibration counter is enabled and counting, using the 1 Hz clock. When the

calibration counter is equal to the value of the CALIBRATION register, the counter resets

and repeats counting up to the value of the CALIBRATION register. See

Section 27–6.4.2 and Section 27–6.5.

31:5

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.2.3 Counter Increment Interrupt Register (CIIR - 0x4002 400C)

The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt

every time a counter is incremented. This interrupt remains valid until cleared by writing a

1 to bit 0 of the Interrupt Location Register (ILR[0]).

Table 511. Counter Increment Interrupt Register (CIIR - address 0x4002 400C) bit description

Bit

Symbol

Description

Reset

value

0

IMSEC

IMMIN

When 1, an increment of the Second value generates an interrupt.

When 1, an increment of the Minute value generates an interrupt.

0

1

2

IMHOUR When 1, an increment of the Hour value generates an interrupt.

3

IMDOM

IMDOW

IMDOY

IMMON

When 1, an increment of the Day of Month value generates an interrupt.

When 1, an increment of the Day of Week value generates an interrupt.

When 1, an increment of the Day of Year value generates an interrupt.

When 1, an increment of the Month value generates an interrupt.

4

5

6

7

IMYEAR When 1, an increment of the Year value generates an interrupt.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved NA

bit is not defined.

6.2.4 Alarm Mask Register (AMR - 0x4002 4010)

The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.

Table 27–512 shows the relationship between the bits in the AMR and the alarms. For the

alarm function, every non-masked alarm register must match the corresponding time

counter for an interrupt to be generated. The interrupt is generated only when the counter

comparison first changes from no match to match. The interrupt is removed when a one is

written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are

set, then the alarm is disabled.

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Table 512. Alarm Mask Register (AMR - address 0x4002 4010) bit description

Bit

Symbol

Description

Reset

value

0

AMRSEC

AMRMIN

When 1, the Second value is not compared for the alarm.

When 1, the Minutes value is not compared for the alarm.

0

1

0

2

AMRHOUR When 1, the Hour value is not compared for the alarm.

AMRDOM When 1, the Day of Month value is not compared for the alarm.

AMRDOW When 1, the Day of Week value is not compared for the alarm.

0

3

0

4

0

5

AMRDOY

When 1, the Day of Year value is not compared for the alarm.

0

6

AMRMON When 1, the Month value is not compared for the alarm.

AMRYEAR When 1, the Year value is not compared for the alarm.

0

7

0

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.2.5 RTC Auxiliary control register (RTC_AUX - 0x4002 405C)

The RTC Auxiliary Control register contains added interrupt flags for functions that are not

part of the Real Time Clock itself (the part recording the passage of time and generating

other time related functions). On the LPC17xx, the only added interrupt flag is for failure of

the RTC oscillator.

Table 513. RTC Auxiliary control register (RTC_AUX - address 0x4002 405C) bit description

Bit

3:0

4

Symbol

Description

Reset

value

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

RTC_OSCF RTC Oscillator Fail detect flag.

Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An

1

interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the

RTC interrupt is enabled in the NVIC.

Write: writing a 1 to this bit clears the flag.

31:5

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

6.2.6 RTC Auxiliary Enable register (RTC_AUXEN - 0x4002 4058)

The RTC Auxiliary Enable Register controls whether additional interrupt sources

represented in the RTC Auxiliary control register are enabled.

Table 514. RTC Auxiliary Enable register (RTC_AUXEN - address 0x4002 4058) bit description

Bit

3:0

4

Symbol

Description

Reset

value

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

RTC_OSCFEN Oscillator Fail Detect interrupt enable.

When 0: the RTC Oscillator Fail detect interrupt is disabled.

0

When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 27–6.2.5.

31:5

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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6.3 Consolidated time registers

The values of the Time Counters can optionally be read in a consolidated format which

allows the programmer to read all time counters with only three read operations. The

various registers are packed into 32-bit values as shown in Table 27–515, Table 27–516,

and Table 27–517. The least significant bit of each register is read back at bit 0, 8, 16, or

24.

The Consolidated Time Registers are read-only. To write new values to the Time

Counters, the Time Counter addresses should be used.

6.3.1 Consolidated Time Register 0 (CTIME0 - 0x4002 4014)

The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes,

Hours, and Day of Week.

Table 515. Consolidated Time register 0 (CTIME0 - address 0x4002 4014) bit description

Bit

Symbol

Description

Reset

value

5:0

7:6

Seconds

-

Seconds value in the range of 0 to 59

NC

NA

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

13:8

Minutes

-

Minutes value in the range of 0 to 59

NC

NA

15:14

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

20:16

23:21

Hours

-

Hours value in the range of 0 to 23

NC

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

26:24

31:27

Day Of Week Day of week value in the range of 0 to 6

NA

NC

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

6.3.2 Consolidated Time Register 1 (CTIME1 - 0x4002 4018)

The Consolidate Time Register 1 contains the Day of Month, Month, and Year values.

Table 516. Consolidated Time register 1 (CTIME1 - address 0x4002 4018) bit description

Bit

4:0

7:5

Symbol

Description

Reset

value

Day of Month Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and

whether it is a leap year).

NC

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

11:8

Month

-

Month value in the range of 1 to 12.

NC

NA

15:12

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

27:16

31:28

Year

-

Year value in the range of 0 to 4095.

NC

NA

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

6.3.3 Consolidated Time Register 2 (CTIME2 - 0x4002 401C)

The Consolidate Time Register 2 contains just the Day of Year value.

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Table 517. Consolidated Time register 2 (CTIME2 - address 0x4002 401C) bit description

Bit

Symbol

Description

Reset

value

11:0

Day of Year

-

Day of year value in the range of 1 to 365 (366 for leap years).

NC

NA

31:12

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

6.4 Time Counter Group

The time value consists of the eight counters shown in Table 27–518 and Table 27–519.

These counters can be read or written at the locations shown in Table 27–519.

Table 518. Time Counter relationships and values

Counter

Second

Size

6

Enabled by

1 Hz Clock

Second

Minimum value

Maximum value

0

1

0

1

0

59

Minute

6

59

Hour

5

Minute

23

Day of Month

Day of Week

Day of Year

Month

5

Hour

28, 29, 30 or 31

3

Hour

6

9

Hour

365 or 366 (for leap year)

4

Day of Month

Month or day of Year

12

Year

12

4095

Table 519. Time Counter registers

Name

SEC

Size Description

Access Address

6

5

Seconds value in the range of 0 to 59

Minutes value in the range of 0 to 59

Hours value in the range of 0 to 23

R/W

0x4002 4020

0x4002 4024

0x4002 4028

0x4002 402C

MIN

HOUR

DOM

Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the

month and whether it is a leap year).^[1]

DOW

3

Day of week value in the range of 0 to 6^[1]

Day of year value in the range of 1 to 365 (366 for leap years)^[1]

Month value in the range of 1 to 12

R/W

0x4002 4030

0x4002 4034

0x4002 4038

0x4002 403C

DOY

9

MONTH

YEAR

4

12

Year value in the range of 0 to 4095

[1] These values are simply incremented at the appropriate intervals and reset at the defined overflow point.

They are not calculated and must be correctly initialized in order to be meaningful.

6.4.1 Leap year calculation

The RTC does a simple bit comparison to see if the two lowest order bits of the year

counter are zero. If true, then the RTC considers that year a leap year. The RTC considers

all years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901

through the year 2099, but fails for the year 2100, which is not a leap year. The only effect

of leap year on the RTC is to alter the length of the month of February for the month, day

of month, and year counters.

6.4.2 Calibration register (CALIBRATION - address 0x4002 4040)

The following register is used to calibrate the time counter.

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Table 520. Calibration register (CALIBRATION - address 0x4002 4040) bit description

Bit

16:0

17

Symbol Value Description

Reset

value

CALVAL

CALDIR

-

If enabled, the calibration counter counts up to this value. The maximum value is 131, NC

072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.

Calibration direction

NC

1

0

Backward calibration. When CALVAL is equal to the calibration counter, the RTC

timers will stop incrementing for 1 second.

Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers

will jump by 2 seconds.

31:12

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

6.5 Calibration procedure

The calibration logic can periodically adjust the time counter either by not incrementing

the counter, or by incrementing the counter by 2 instead of 1. This allows calibrating the

RTC oscillator under some typical voltage and temperature conditions without the need to

externally trim the RTC oscillator.

A recommended method for determining the calibration value is to use the CLKOUT

feature to unintrusively observe the RTC oscillator frequency under the conditions it is to

be trimmed for, and calculating the number of clocks that will be seen before the time is off

by one second. That value is used to determine CALVAL.

If the RTC oscillator is trimmed externally, the same method of unintrusively observing the

RTC oscillator frequency may be helpful in that process.

Backward calibration

Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and

CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL ≥ 1 and

select CALDIR = 1.

• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.

• When the calibration counter reaches CALVAL, a calibration match occurs and all

RTC timers will be stopped for one clock cycle so that the timers will not increment in

the next cycle.

• If an alarm match event occurs in the same cycle as the calibration match, the alarm

interrupt will be delayed by one cycle to avoid a double alarm interrupt.

Forward calibration

Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and

CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL ≥ 1 and

select CALDIR = 0.

• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.

• When the calibration counter reaches CALVAL, a calibration match occurs and the

RTC timers are incremented by 2.

• When the calibration event occurs, the LSB of the ALSEC register is forced to be one

so that the alarm interrupt will not be missed when skipping a second.

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6.6 General purpose registers

6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses

0x4002 4044 to 0x4002 4054)

These registers can be used to store important information when the main power supply is

off. The value in these registers is not affected by chip reset.

Table 521. General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044

to 0x4002 4054) bit description

Bit

Symbol

Description

Reset

value

31:0

GP0 to GP4 General purpose storage.

N/A

6.7 Alarm register group

The alarm registers are shown in Table 27–522. The values in these registers are

compared with the time counters. If all the unmasked (See Section 27–6.2.4 “Alarm Mask

Register (AMR - 0x4002 4010)” on page 560) alarm registers match their corresponding

time counters then an interrupt is generated. The interrupt is cleared when a 1 is written to

bit 1 of the Interrupt Location Register (ILR[1]).

Table 522. Alarm registers

Name

Size Description

Access

R/W

Address

ALSEC

ALMIN

6

Alarm value for Seconds

0x4002 4060

0x4002 4064

0x4002 4068

0x4002 406C

0x4002 4070

0x4002 4074

0x4002 4078

0x4002 407C

6

Alarm value for Minutes

Alarm value for Hours

ALHOUR

ALDOM

ALDOW

ALDOY

ALMON

ALYEAR

5

Alarm value for Day of Month

Alarm value for Day of Week

Alarm value for Day of Year

Alarm value for Months

Alarm value for Years

3

9

4

12

7. RTC usage notes

If the RTC is used, V_BATmay be connected to an independent power supply (typically an

external battery), or left floating. The RTC domain will always be internally powered if

V

_DD(REG)(3V3)is present, even if there is no power applied to V_BAT. As long as power is

available on either V_DD(REG)(3V3)or V_BAT, the RTC will lose its time value and backup

register contents. If both V_DD(REG)(3V3)and V_BATare not present, all RTC information will

be lost. RTC incrementation will stop or be unpredictable if the clock source is lost,

interrupted, or altered.

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Chapter 28: LPC17xx Watchdog Timer (WDT)

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1. Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate Watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_WDCLK× 256 × 4) to (T_WDCLK× 2³²× 4) in multiples of

T_WDCLK× 4.

• The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the APB peripheral clock (PCLK, see Table 4–40), or the RTC oscillator. This

gives a wide range of potential timing choices for Watchdog operation under different

power reduction conditions. For increased reliability, it also provides the ability to run

the Watchdog timer from an entirely internal source that is not dependent on an

external crystal and its associated components and wiring.

• The Watchdog timer can be configured to run in Deep Sleep mode when using the

IRC as the clock source.

2. Applications

The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the Watchdog will generate a system

reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined

amount of time.

For interaction of the on-chip watchdog and other peripherals, especially the reset and

boot-up procedures, please read Section 3–4 “Reset” on page 18 of this document.

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Chapter 28: LPC17xx Watchdog Timer (WDT)

3. Description

The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is

fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value

from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF

to be loaded in the counter. Hence the minimum Watchdog interval is (T_WDCLK× 256 × 4)

and the maximum Watchdog interval is (T_WDCLK× 2³²× 4) in multiples of (T_WDCLK× 4).

The Watchdog should be used in the following manner:

• Set the Watchdog timer constant reload value in WDTC register.

• Setup the Watchdog timer operating mode in WDMOD register.

• Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.

• The Watchdog should be fed again before the Watchdog counter underflows to

prevent reset/interrupt.

When the Watchdog is in the reset mode and the counter underflows, the CPU will be

reset, loading the stack pointer and program counter from the vector table as in the case

of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if

the Watchdog has caused the reset condition. The WDTOF flag must be cleared by

software.

The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB

accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.

There is some synchronization logic between these two clock domains. When the

WDMOD and WDTC registers are updated by APB operations, the new value will take

effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog

timer is counting on WDCLK, the synchronization logic will first lock the value of the

counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV

register by the CPU.

4. Register description

The Watchdog contains 4 registers as shown in Table 28–523 below.

Table 523. Watchdog register map

Name

Description

Access Reset

Address

Value^[1]

WDMOD

WDTC

Watchdog mode register. This register contains the basic mode and

status of the Watchdog Timer.

R/W

0

0x4000 0000

0x4000 0004

0x4000 0008

0x4000 000C

0x4000 0010

Watchdog timer constant register. This register determines the time-out

value.

0xFF

NA

WDFEED

WDTV

Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this WO

register reloads the Watchdog timer with the value contained in WDTC.

Watchdog timer value register. This register reads out the current value of RO

the Watchdog timer.

0xFF

0

WDCLKSEL Watchdog clock source selection register.

R/W

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 28: LPC17xx Watchdog Timer (WDT)

4.1 Watchdog Mode register (WDMOD - 0x4000 0000)

The WDMOD register controls the operation of the Watchdog as per the combination of

WDEN and RESET bits. Note that a watchdog feed must be performed before any

changes to the WDMOD register take effect.

Table 524: Watchdog Mode register (WDMOD - address 0x4000 0000) bit description

Bit

0

Symbol

Description

Reset Value

WDEN

WDEN Watchdog enable bit (set-only). When 1, the watchdog timer is running.

0

1

WDRESET WDRESET Watchdog reset enable bit (set -only). When 1, a watchdog timeout will

cause a chip reset.

2

WDTOF

WDTOF Watchdog time-out flag. Set when the watchdog timer times out, cleared by

software.

0 (Only after

external reset)

3

WDINT

-

WDINT Watchdog interrupt flag (read-only, not clearable by software).

0

31:4

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both

flags are cleared by an external reset or a Watchdog timer underflow.

WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is

cleared by software.

WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is

cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be

disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. the

intent of the watchdog interrupt is to allow debugging watchdog activity without resetting

the device when the watchdog overflows.

Watchdog reset or interrupt will occur any time the watchdog is running and has an

operating clock source. Any clock source works in Sleep mode, and the IRC works in

Deep Sleep mode. If a watchdog interrupt occurs in Sleep or Deep Sleep mode, it will

wake up the device.

Table 525. Watchdog operating modes selection

WDEN

WDRESET Mode of Operation

0

1

X (0 or 1)

0

Debug/Operate without the Watchdog running.

Watchdog interrupt mode: debug with the Watchdog interrupt but no WDRESET enabled.

When this mode is selected, a watchdog counter underflow will set the WDINT flag and the

Watchdog interrupt request will be generated.

1

Watchdog reset mode: operate with the Watchdog interrupt and WDRESET enabled.

When this mode is selected, a watchdog counter underflow will reset the microcontroller. Although

the Watchdog interrupt is also enabled in this case (WDEN = 1) it will not be recognized since the

watchdog reset will clear the WDINT flag.

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4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004)

The WDTC register determines the time-out value. Every time a feed sequence occurs

the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB

set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the

WDTC. Thus the minimum time-out interval is T_WDCLK× 256 × 4.

Table 526: Watchdog Constant register (WDTC - address 0x4000 0004) bit description

Bit

Symbol

Description

Reset Value

31:0

Count

Watchdog time-out interval.

0x0000 00FF

4.3 Watchdog Feed register (WDFEED - 0x4000 0008)

Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the

WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD

register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the

Watchdog. A valid feed sequence must be completed after setting WDEN before the

Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed

errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing

0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.

The reset will be generated during the second PCLK following an incorrect access to a

Watchdog register during a feed sequence.

Interrupts should be disabled during the feed sequence. An abort condition will occur if an

interrupt happens during the feed sequence.

Table 527: Watchdog Feed register (WDFEED - address 0x4000 0008) bit description

Bit

Symbol Description

Reset

Value

7:0

Feed

-

Feed value should be 0xAA followed by 0x55.

NA

31:8

Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

4.4 Watchdog Timer Value register (WDTV - 0x4000 000C)

The WDTV register is used to read the current value of Watchdog timer.

When reading the value of the 32-bit timer, the lock and synchronization procedure takes

up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual

value of the timer when it's being read by the CPU.

Table 528: Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description

Bit

Symbol Description

Counter timer value.

Reset Value

31:0 Count

0x0000 00FF

4.5 Watchdog Timer Clock Source Selection register (WDCLKSEL -

0x4000 0010)

This register allows selecting the clock source for the Watchdog timer. The possibilities are the

Internal RC oscillator (IRC) or the APB peripheral clock (pclk). The function of bits in WDCLKSEL

are shown in Table 28–529. The clock source selection can be locked by software, so that it

cannot be modified. On reset, the clock source selection bits are always unlocked.

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When the IRC is chosen as the watchdog clock source, the watchdog timer can remain

running in deep sleep mode, and can reset or wake up the device from that mode.

Table 529: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description

Bit

Symbol

Value Description

Reset

Value

1:0

WDSEL

These bits select the clock source for the Watchdog timer as described below.

0

Warning: Improper setting of this value may result in incorrect operation of the

Watchdog timer, which could adversely affect system operation. If the WDLOCK bit in

this register is set, the WDSEL bit cannot be modified.

00

01

10

11

-

Selects the Internal RC oscillator (irc_clk) as the Watchdog clock source (default).

Selects the APB peripheral clock (watchdog pclk) as the Watchdog clock source.

Selects the RTC oscillator (rtc_clk) as the Watchdog clock source.

Reserved, this setting should not be used.

30:2

31

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

WDLOCK

0

1

This bit is set to 0 on any reset. It cannot be cleared by software.

0

Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register

cannot be modified.

5. Block diagram

The block diagram of the Watchdog is shown below in the Figure 28–131. The

synchronization logic (PCLK - WDCLK) is not shown in the block diagram.

feed sequence

WDTC

feed ok

WDFEED

feed error

RTC oscillator

wdclk

÷ 4

32-BIT DOWN COUNTER

underflow

pclk

internal RC oscillator

enable

count

WDCLKSEL

WDTV

SHADOW BIT

WMOD register

WDINT WDTOF WDRESET WDEN

reset

interrupt

Fig 131. Watchdog block diagram

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1. Basic configuration

The ADC is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set the PCADC bit.

Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,

and then enable the ADC in the AD0CR register (bit PDN Table 29–532). To disable

the ADC, first clear the PDN bit, and then clear the PCADC bit.

2. Clock: In the PCLKSEL0 register (Table 4–40), select PCLK_ADC. To scale the clock

for the ADC, see bits CLKDIV in Table 29–532.

3. Pins: Enable ADC0 pins through PINSEL registers. Select the pin modes for the port

pins with ADC0 functions through the PINMODE registers (Section 8–5).

4. Interrupts: To enable interrupts in the ADC, see Table 29–536. Interrupts are enabled

in the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC

interrupt in the NVIC using the appropriate Interrupt Set Enable register.

5. DMA: See Section 29–6.4. For GPDMA system connections, see Table 31–544.

2. Features

• 12-bit successive approximation analog to digital converter.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range V_REFNto V_REFP(typically 3 V; not to exceed V_DDAvoltage level).

• 12-bit conversion rate of 200 kHz.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

3. Description

Basic clocking for the A/D converters is provided by the APB clock. A programmable

divider is included in each converter to scale this clock to the clock (maximum 13 MHz)

needed by the successive approximation process. A fully accurate conversion requires 65

of these clocks.

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4. Pin description

Table 29–530 gives a brief summary of each of ADC related pins.

Table 530. ADC pin description

Type

Description

AD0.7 to AD0.0

Input

Analog Inputs. The ADC cell can measure the voltage on any of these input signals.

Digital signals are disconnected from the ADC input pins when the ADC function is

selected on that pin in the Pin Select register.

Warning: if the ADC is used, signal levels on analog input pins must not be above the

level of V_DDAat any time. Otherwise, A/D converter readings will be invalid. If the A/D

converter is not used in an application then the pins associated with A/D inputs can be

used as 5 V tolerant digital IO pins.

V

_REFP, V_REFN

Reference

Power

Voltage References. These pins provide a voltage reference level for the ADC and

DAC. Note: V_REFPshould be tied to VDD(3V3) and V_REFNshould be tied to V_SSif

the ADC and DAC are not used.

V_DDA, V_SSA

Analog Power and Ground. These should typically be the same voltages as V_DDand

V_SS, but should be isolated to minimize noise and error. Note: V_DDAshould be tied to

VDD(3V3) and V_SSAshould be tied to V_SSif the ADC and DAC are not used.

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5. Register description

The A/D Converter registers are shown in Table 29–531.

Table 531. ADC registers

Generic

Name

Description

Access Reset AD0 Name &

value^[1]Address

ADCR

A/D Control Register. The ADCR register must be written to select the

operating mode before A/D conversion can occur.

R/W

1

AD0CR -

0x4003 4000

ADGDR

A/D Global Data Register. This register contains the ADC’s DONE bit and R/W

the result of the most recent A/D conversion.

NA

AD0GDR -

0x4003 4004

ADINTEN A/D Interrupt Enable Register. This register contains enable bits that allow R/W

the DONE flag of each A/D channel to be included or excluded from

contributing to the generation of an A/D interrupt.

0x100 AD0INTEN -

0x4003 400C

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADSTAT

ADTRM

A/D Channel 0 Data Register. This register contains the result of the most RO

recent conversion completed on channel 0.

NA

0

AD0DR0 -

0x4003 4010

A/D Channel 1 Data Register. This register contains the result of the most RO

recent conversion completed on channel 1.

AD0DR1 -

0x4003 4014

A/D Channel 2 Data Register. This register contains the result of the most RO

recent conversion completed on channel 2.

AD0DR2 -

0x4003 4018

A/D Channel 3 Data Register. This register contains the result of the most RO

recent conversion completed on channel 3.

AD0DR3 -

0x4003 401C

A/D Channel 4 Data Register. This register contains the result of the most RO

recent conversion completed on channel 4.

AD0DR4 -

0x4003 4020

A/D Channel 5 Data Register. This register contains the result of the most RO

recent conversion completed on channel 5.

AD0DR5 -

0x4003 4024

A/D Channel 6 Data Register. This register contains the result of the most RO

recent conversion completed on channel 6.

AD0DR6 -

0x4003 4028

A/D Channel 7 Data Register. This register contains the result of the most RO

recent conversion completed on channel 7.

AD0DR7 -

0x4003 402C

A/D Status Register. This register contains DONE and OVERRUN flags

for all of the A/D channels, as well as the A/D interrupt/DMA flag.

RO

AD0STAT -

0x4003 4030

ADC trim register.

R/W

0

AD0TRM -

0x4003 4034

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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5.1 A/D Control Register (AD0CR - 0x4003 4000)

Table 532: A/D Control Register (AD0CR - address 0x4003 4000) bit description

Bit

Symbol Value Description

Reset

value

7:0

SEL

Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0

0x01

selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of

these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is

allowed. All zeroes is equivalent to 0x01.

15:8

16

CLKDIV

The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for

the A/D converter, which should be less than or equal to 13 MHz. Typically, software

should program the smallest value in this field that yields a clock of 13 MHz or slightly

less, but in certain cases (such as a high-impedance analog source) a slower clock may

be desirable.

0

BURST

1

0

The AD converter does repeated conversions at up to 200 kHz, scanning (if necessary)

through the pins selected by bits set to ones in the SEL field. The first conversion after the

start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits

(pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the

conversion that’s in progress when this bit is cleared will be completed.

0

Remark: START bits must be 000 when BURST = 1 or conversions will not start.

Conversions are software controlled and require 65 clocks.

20:17

21

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

PDN

1

0

The A/D converter is operational.

The A/D converter is in power-down mode.

23:22

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

0

26:24 START

When the BURST bit is 0, these bits control whether and when an A/D conversion is

started:

000

001

010

011

No start (this value should be used when clearing PDN to 0).

Start conversion now.

Start conversion when the edge selected by bit 27 occurs on the P2.10 / EINT0 / NMI pin.

Start conversion when the edge selected by bit 27 occurs on the P1.27 / CLKOUT /

USB_OVRCRn / CAP0.1 pin.

100

101

110

111

Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does

not require that the MAT0.1 function appear on a device pin.

Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not

possible to cause the MAT0.3 function to appear on a device pin.

Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does

not require that the MAT1.0 function appear on a device pin.

Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does

not require that the MAT1.1 function appear on a device pin.

27

EDGE

-

This bit is significant only when the START field contains 010-111. In these cases:

Start conversion on a falling edge on the selected CAP/MAT signal.

Start conversion on a rising edge on the selected CAP/MAT signal.

0

1

0

31:28

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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5.2 A/D Global Data Register (AD0GDR - 0x4003 4004)

The A/D Global Data Register holds the result of the most recent A/D conversion that has

completed, and also includes copies of the status flags that go with that conversion.

Results of ADC conversion can be read in one of two ways. One is to use the A/D Global

Data Register to read all data from the ADC. Another is to use the A/D Channel Data

Registers. It is important to use one method consistently because the DONE and

OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D

Channel Data Registers, potentially causing erroneous interrupts or DMA activity.

Table 533: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description

Bit

Symbol

Description

Reset

value

3:0

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

15:4

RESULT

When DONE is 1, this field contains a binary fraction representing the voltage on

the AD0[n] pin selected by the SEL field, as it falls within the range of V_REFPto

V_REFN. Zero in the field indicates that the voltage on the input pin was less than,

equal to, or close to that on V_REFN, while 0x3FF indicates that the voltage on the

NA

input was close to, equal to, or greater than that on V_REFP

.

23:16

26:24

29:27

30

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

CHN

These bits contain the channel from which the RESULT bits were converted (e.g.

000 identifies channel 0, 001 channel 1...).

NA

-

Reserved, user software should not write ones to reserved bits. The value read from NA

a reserved bit is not defined.

OVERRUN

This bit is 1 in burst mode if the results of one or more conversions was (were) lost

and overwritten before the conversion that produced the result in the RESULT bits.

This bit is cleared by reading this register.

0

31

DONE

This bit is set to 1 when an A/D conversion completes. It is cleared when this

register is read and when the ADCR is written. If the ADCR is written while a

conversion is still in progress, this bit is set and a new conversion is started.

0

5.3 A/D Interrupt Enable register (AD0INTEN - 0x4003 400C)

This register allows control over which A/D channels generate an interrupt when a

conversion is complete. For example, it may be desirable to use some A/D channels to

monitor sensors by continuously performing conversions on them. The most recent

results are read by the application program whenever they are needed. In this case, an

interrupt is not desirable at the end of each conversion for some A/D channels.

Table 534: A/D Status register (AD0INTEN - address 0x4003 400C) bit description

Bit

Symbol

Value Description

Reset

value

0

ADINTEN0

0

1

0

1

0

1

Completion of a conversion on ADC channel 0 will not generate an interrupt.

0

Completion of a conversion on ADC channel 0 will generate an interrupt.

Completion of a conversion on ADC channel 1 will not generate an interrupt.

Completion of a conversion on ADC channel 1 will generate an interrupt.

Completion of a conversion on ADC channel 2 will not generate an interrupt.

Completion of a conversion on ADC channel 2 will generate an interrupt.

1

2

ADINTEN1

ADINTEN2

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Table 534: A/D Status register (AD0INTEN - address 0x4003 400C) bit description

Bit

Symbol

Value Description

Reset

value

3

ADINTEN3

0

1

0

1

0

1

0

1

0

1

0

Completion of a conversion on ADC channel 3 will not generate an interrupt.

0

1

Completion of a conversion on ADC channel 3 will generate an interrupt.

Completion of a conversion on ADC channel 4 will not generate an interrupt.

Completion of a conversion on ADC channel 4 will generate an interrupt.

Completion of a conversion on ADC channel 5 will not generate an interrupt.

Completion of a conversion on ADC channel 5 will generate an interrupt.

Completion of a conversion on ADC channel 6 will not generate an interrupt.

Completion of a conversion on ADC channel 6 will generate an interrupt.

Completion of a conversion on ADC channel 7 will not generate an interrupt.

Completion of a conversion on ADC channel 7 will generate an interrupt.

4

5

6

7

8

ADINTEN4

ADINTEN5

ADINTEN6

ADINTEN7

ADGINTEN

Only the individual ADC channels enabled by ADINTEN7:0 will generate

interrupts.

1

Only the global DONE flag in ADDR is enabled to generate an interrupt.

31:17

-

Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined.

NA

5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to

0x4003 402C)

The A/D Data Registers hold the result of the last conversion for each A/D channel, when

an A/D conversion is complete. They also include the flags that indicate when a

conversion has been completed and when a conversion overrun has occurred.

Results of ADC conversion can be read in one of two ways. One is to use the A/D Global

Data Register to read all data from the ADC. Another is to use the A/D Channel Data

Registers. It is important to use one method consistently because the DONE and

OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D

Channel Data Registers, potentially causing erroneous interrupts or DMA activity.

Table 535: A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description

Bit

Symbol

Description

Reset

value

3:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

15:4

RESULT

When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] NA

pin, as it falls within the range of V_REFPto V_REFN. Zero in the field indicates that the voltage on

the input pin was less than, equal to, or close to that on V_REFN, while 0x3FF indicates that the

voltage on the input was close to, equal to, or greater than that on V_REFP

.

29:16

30

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and

overwritten before the conversion that produced the result in the RESULT bits.This bit is

cleared by reading this register.

31

DONE

This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA

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5.5 A/D Status register (ADSTAT - 0x4003 4030)

The A/D Status register allows checking the status of all A/D channels simultaneously.

The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel

are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found

in ADSTAT.

Table 536: A/D Status register (AD0STAT - address 0x4003 4030) bit description

Bit

Symbol

Description

Reset

value

0

DONE0

This bit mirrors the DONE status flag from the result register for A/D channel 0.

This bit mirrors the DONE status flag from the result register for A/D channel 1.

This bit mirrors the DONE status flag from the result register for A/D channel 2.

This bit mirrors the DONE status flag from the result register for A/D channel 3.

This bit mirrors the DONE status flag from the result register for A/D channel 4.

This bit mirrors the DONE status flag from the result register for A/D channel 5.

This bit mirrors the DONE status flag from the result register for A/D channel 6.

This bit mirrors the DONE status flag from the result register for A/D channel 7.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.

This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.

0

1

DONE1

2

DONE2

3

DONE3

4

DONE4

5

DONE5

6

DONE6

7

DONE7

8

OVERRUN0

OVERRUN1

OVERRUN2

OVERRUN3

OVERRUN4

OVERRUN5

OVERRUN6

OVERRUN7

ADINT

9

10

11

12

13

14

15

16

This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done

flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.

31:17

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

5.6 A/D Trim register (ADTRIM - 0x4003 4034)

This register will be set by the bootcode on start-up. It contains the trim values for the DAC

and the ADC. The offset trim values for the ADC can be overwritten by the user. All 12 bits

are visible when this register is read.

Table 537: A/D Trim register (ADTRM - address 0x4003 4034) bit description

Bit

Symbol

Description

Reset

value

3:0

7:4

-

reserved.

NA

ADCOFFS Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. 0

11:8 TRIM

written-to by boot code. Can not be overwritten by the user. These bits are locked after boot

0

code write.

31:12 -

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

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Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)

6. Operation

Once an ADC conversion is started, it cannot be interrupted. A new software write to

launch a new conversion or a new edge-trigger event will be ignored while the previous

conversion is in progress.

6.1 Hardware-triggered conversion

If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will

start a conversion when a transition occurs on a selected pin or Timer Match signal. The

choices include conversion on a specified edge of any of 4 Match signals, or conversion

on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad

or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection

logic.

6.2 Interrupts

An interrupt request is asserted to the NVIC when the DONE bit is 1. Software can use the

Interrupt Enable bit for the A/D Converter in the NVIC to control whether this assertion

results in an interrupt. DONE is negated when the ADDR is read.

6.3 Accuracy vs. digital receiver

The ADC function must be selected via the PINSEL registers in order to get accurate

voltage readings on the monitored pin. The PINMODE should also be set to the mode for

which neither pull-up nor pull-down resistor is enabled. For a pin hosting an ADC input, it

is not possible to have a have a digital function selected and yet get valid ADC readings.

An inside circuit disconnects ADC hardware from the associated pin whenever a digital

function is selected on that pin.

6.4 DMA control

A DMA transfer request is generated from the ADC interrupt request line. To generate a

DMA transfer the same conditions must be met as the conditions for generating an

interrupt (see Section 29–6.2 and Section 29–5.3).

Remark: If the DMA is used, the ADC interrupt must be disabled in the NVIC.

For DMA transfers, only burst requests are supported. The burst size can be set to one in

the DMA channel control register (see Section 31–5.20). If the number of ADC channels is

not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are

1, 4, 8 - see Section 31–5.20), set the burst size to one.

The DMA transfer size determines when a DMA interrupt is generated. The transfer size

can be set to the number of ADC channels being converted (see Section 31–5.20).

Non-contiguous channels can be transferred by the DMA using the scatter/gather linked

lists (see Section 31–5.19).

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Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)

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1. Basic configuration

The DAC is configured using the following registers:

1. Power: The DAC is always connected to V_DDA. Register access is determined by

PINSEL and PINMODE settings (see below).

2. Clock: In the PCLKSEL0 register (Table 4–40), select PCLK_DAC.

3. Pins: Enable the DAC pin through the PINSEL registers. Select pin mode for port pin

with DAC through the PINMODE registers (Section 8–5). This must be done before

accessing any DAC registers.

4. DMA: The DAC can be connected to the GPDMA controller (see Section 30–4.2). For

GPDMA connections, see Table 31–544.

2. Features

• 10-bit digital to analog converter

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable speed vs. power

• Maximum update rate of 1 MHz.

3. Pin description

Table 30–538 gives a brief summary of each of DAC related pins.

Table 538. D/A Pin Description

Type

Description

AOUT

Output

Analog Output. After the selected settling time after the DACR is written with a new value,

the voltage on this pin (with respect to V_SSA) is VALUE × ((V_REFP- V_REFN)/1024) + V_REFN

.

V_REFP, V_REFNReference Voltage References. These pins provide a voltage reference level for the ADC and DAC.

Note: V_REFPshould be tied to VDD(3V3) and V_REFNshould be tied to V_SSif the ADC and

DAC are not used.

V_DDA, V_SSA

Power

Analog Power and Ground. These should typically be the same voltages as V_DDand V_SS,

but should be isolated to minimize noise and error. Note: V_DDAshould be tied to VDD(3V3)

and V_SSAshould be tied to V_SSif the ADC and DAC are not used.

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Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)

4. Register description

The DAC registers are shown in Table 30–539. Note that the DAC does not have a control

bit in the PCONP register. To enable the DAC, its output must be selected to appear on

the related pin, P0.26, by configuring the PINSEL1 register. See Section 8–5.2 “Pin

Function Select Register 1 (PINSEL1 - 0x4002 C004)”. the DAC must be enabled in this

manner prior to accessing any DAC registers.

Table 539. DAC registers

Name

Description

Access Reset Address

value^[1]

DACR

D/A Converter Register. This register contains the digital value to be R/W

converted to analog and a power control bit.

0

0x4008 C000

DACCTRL

DAC Control register. This register controls DMA and timer operation. R/W

0

0x4008 C004

0x4008 C008

DACCNTVAL

DAC Counter Value register. This register contains the reload value for R/W

the DAC DMA/Interrupt timer.

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 D/A Converter Register (DACR - 0x4008 C000)

This read/write register includes the digital value to be converted to analog, and a bit that

trades off performance vs. power. Bits 5:0 are reserved for future, higher-resolution D/A

converters.

Table 540: D/A Converter Register (DACR - address 0x4008 C000) bit description

Bit

Symbol Value Description

Reset

Value

5:0

-

Reserved, user software should not write ones to reserved bits. The value read from a

NA

reserved bit is not defined.

15:6 VALUE

After the selected settling time after this field is written with a new VALUE, the voltage on

0

the AOUT pin (with respect to V_SSA) is VALUE × ((V_REFP- V_REFN)/1024) + V_REFN

.

16

BIAS^[1]

0

1

The settling time of the DAC is 1 μs max, and the maximum current is 700 μA. This allows

a maximum update rate of 1 MHz.

0

The settling time of the DAC is 2.5 μs and the maximum current is 350 μA. This allows a

maximum update rate of 400 kHz.

31:17

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

[1] The settling times noted in the description of the BIAS bit are valid for a capacitance load on the AOUT pin

not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than

the specified time. One or more graph(s) of load impedance vs. settling time will be included in the final data

sheet.

4.2 D/A Converter Control register (DACCTRL - 0x4008 C004)

This read/write register enables the DMA operation and controls the DMA timer.

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Table 541. D/A Control register (DACCTRL - address 0x4008 C004) bit description

Bit

Symbol

Value Description

Reset

Value

0

INT_DMA_REQ 0

1

This bit is cleared on any write to the DACR register.

This bit is set by hardware when the timer times out.

DACR double-buffering is disabled.

0

1

DBLBUF_ENA

0

1

0

When this bit and the CNT_ENA bit are both set, the double-buffering feature in the

DACR register will be enabled. Writes to the DACR register are written to a

pre-buffer and then transferred to the DACR on the next time-out of the counter.

2

CNT_ENA

DMA_ENA

-

0

1

0

1

Time-out counter operation is disabled.

0

Time-out counter operation is enabled.

3

DMA access is disabled.

0

DMA Burst Request Input 7 is enabled for the DAC (see Table 31–544).

31:4

Reserved, user software should not write ones to reserved bits. The value read

from a reserved bit is not defined.

NA

4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008)

This read/write register contains the reload value for the Interrupt/DMA counter.

Table 542: D/A Converter register (DACR - address 0x4008 C000) bit description

Bit Symbol Description

15:0 VALUE 16-bit reload value for the DAC interrupt/DMA timer.

Reset Value

0

5. Operation

5.1 DMA counter

When the counter enable bit CNT_ENA in DACCTRL is set, a 16-bit counter will begin

counting down, at the rate selected by PCLK_DAC (see Table 4–40), from the value

programmed into the DACCNTVAL register. The counter is decremented Each time the

counter reaches zero, the counter will be reloaded by the value of DACCNTVAL and the

DMA request bit INT_DMA_REQ will be set in hardware.

Note that the contents of the DACCTRL and DACCNTVAL registers are read and write

accessible, but the timer itself is not accessible for either read or write.

If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed

to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC

DMA requests are blocked.

5.2 Double buffering

Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set

in DACCTRL. In this case, any write to the DACR register will only load the pre-buffer,

which shares its register address with the DACR register. The DACR itself will be loaded

from the pre-buffer whenever the counter reaches zero and the DMA request is set. At the

same time the counter is reloaded with the COUNTVAL register value.

Reading the DACR register will only return the contents of the DACR register itself, not the

contents of the pre-buffer register.

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Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)

If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DACR address

will go directly to the DACR register.

pbus

CNTVAL

pbus

pbus_wr_toDACR

pbus

16

LD

PRE-BUFFER

EN

LD

DMA_ena

cnt_ena

3

2

COUNTER

pbus

dblbuf_ena

16

1

0

zero

set_intrpt

pbus_wr_to_DACR

S

C

intrptDMA_req

set_intrpt

1

0

ena_cnt_and_dblbuf

MUX

LD

pbus_wr_to_DACR

DACR

pbus

DAC value

Fig 132. DAC control with DMA interrupt and timer

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Chapter 31: LPC17xx General Purpose DMA (GPDMA)

controller

Rev. 01 — 4 January 2010

User manual

1. Basic configuration

The GPDMA is configured using the following registers:

1. Power: In the PCONP register (Table 4–46), set bit PCGPDMA.

Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).

2. Clock: see Table 4–38.

3. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set

Enable register.

4. Programming: see Section 31–6.

2. Introduction

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA

transfers for a single source and destination. For example, a bi-directional port requires

one stream for transmit and one for receives. The source and destination areas can each

be either a memory region or a peripheral.

3. Features

• Eight DMA channels. Each channel can support an unidirectional transfer.

• 16 DMA request lines.

• Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers are

supported.

• GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals.

DMA can also be triggered by a timer match condition. Memory-to-memory transfers

and transfers to or from GPIO are also supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• One AHB bus master for transferring data. The interface transfers data when a DMA

request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

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Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

• DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot

access the flash memory).

4. Functional description

This section describes the major functional blocks of the DMA Controller.

4.1 DMA controller functional description

The DMA Controller enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master. Figure 31–133 shows a block diagram of the

DMA Controller.

GPDMA

CONTROL

LOGIC AND

REGISTERS

AHB SLAVE

INTERFACE

AHB BUS

DMA

requests

DMA

REQUEST

AND

RESPONSE

INTERFACE

CHANNEL

LOGIC AND

REGISTERS

AHB

MASTER

INTERFACE

DMA

responses

AHB BUS

DMA

Interrupts

INTERRUPT

REQUEST

Fig 133. DMA controller block diagram

The functions of the DMA Controller are described in the following sections.

4.1.1 AHB slave interface

All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide.

8-bit and 16-bit accesses are not supported and will result in an exception.

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4.1.2 Control logic and register bank

The register block stores data written or to be read across the AHB interface.

4.1.3 DMA request and response interface

See Section 31–4.2 for information on the DMA request and response interface.

4.1.4 Channel logic and channel register bank

The channel logic and channel register bank contains registers and logic required for each

DMA channel.

4.1.5 Interrupt request

The interrupt request generates the interrupt to the ARM processor.

4.1.6 AHB master interface

The DMA Controller contains one AHB master interface. The AHB master is capable of

dealing with all types of AHB transactions, including:

• Split, retry, and error responses from slaves. If a peripheral performs a split or retry,

the DMA Controller stalls and waits until the transaction can complete.

• Locked transfers for source and destination of each stream.

• Setting of protection bits for transfers on each stream.

4.1.6.1 Bus and transfer widths

The physical width of the AHB bus is 32 bits. Source and destination transfers can be of

differing widths and can be the same width or narrower than the physical bus width. The

DMA Controller packs or unpacks data as appropriate.

4.1.6.2 Endian behavior

The DMA Controller can cope with both little-endian and big-endian addressing.

Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit

quantities. This means that when performing mixed-endian activity, where the endianness

of the source and destination are different, byte swapping of the data within the 32-bit data

bus is observed.

Note: If byte swapping is not required, then use of different endianness between the

source and destination addresses must be avoided. Table 31–543 shows endian behavior

for different source and destination combinations.

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Table 543. Endian behavior

Source

endian

Destination Source

Source data Destination Destination data

endian

width

transfer

no/byte lane

Little

Big

Little

8

1/[7:0]

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

21

43

65

87

12

34

56

78

1/[7:0]

21212121

43434343

65656565

87878787

43214321

87658765

2/[15:8]

3/[23:16]

4/[31:24]

1/[7:0]

2/[15:8]

3/[23:16]

4/[31:24]

1/[15:0]

2/[31:16]

Little

Big

8

16

32

8

2/[15:8]

3/[23:16]

4/[31:24]

1/[7:0]

8

1/[31:0]

87654321

2/[15:8]

3/[23:16]

4/[31:24]

1/[7:0]

16

32

8

1/[7:0]

21212121

43434343

65656565

87878787

43214321

87658765

1/[15:8]

2/[23:16]

2/[31:24]

1/[7:0]

2/[15:8]

3/[23:16]

4/[31:24]

1/[15:0]

2/[31:16]

16

32

8

1/[15:8]

2/[23:16]

2/[31:24]

1/[7:0]

1/[31:0]

87654321

1/[15:8]

2/[23:16]

2/[31:24]

1/[7:0]

21212121

43434343

65656565

87878787

43214321

1/[15:8]

1/[23:16]

1/[31:24]

1/[7:0]

2/[15:8]

3/[23:16]

4/[31:24]

1/[15:0]

2/[31:16]

16

32

8

58765

876

1/[15:8]

1/[23:16]

1/[31:24]

1/[7:0]

1/[31:0]

87654321

1/[15:8]

1/[23:16]

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

12121212

34343434

56565656

78787878

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…continued

Table 543. Endian behavior

Source

endian

Destination Source

Source data Destination Destination data

endian

width

transfer

no/byte lane

Big

8

16

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

12

34

56

78

12

34

56

78

12

34

56

78

12

34

56

78

12

34

56

78

12

34

56

78

12

34

56

78

12

34

56

78

1/[15:0]

12341234

56785678

2/[31:16]

Big

8

32

8

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

1/[31:0]

12345678

16

32

1/[31:24]

1/[23:16]

2/[15:8]

2/[7:0]

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

12121212

34343434

56565656

78787878

12341234

56785678

16

32

8

1/[31:24]

1/[23:16]

2/[15:8]

2/[7:0]

1/[15:0]

2/[31:16]

1/[31:24]

1/[23:16]

2/[15:8]

2/[7:0]

1/[31:0]

12345678

1/[31:24]

1/[23:16]

1/[15:8]

1/[7:0]

1/[31:24]

2/[23:16]

3/[15:8]

4/[7:0]

12121212

34343434

56565656

78787878

12341234

56785678

16

32

1/[31:24]

1/[23:16]

1/[15:8]

1/[7:0]

1/[15:0]

2/[31:16]

1/[31:24]

1/[23:16]

1/[15:8]

1/[7:0]

1/[31:0]

12345678

4.1.6.3 Error conditions

An error during a DMA transfer is flagged directly by the peripheral by asserting an Error

response on the AHB bus during the transfer. The DMA Controller automatically disables

the DMA stream after the current transfer has completed, and can optionally generate an

error interrupt to the CPU. This error interrupt can be masked.

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4.1.7 Channel hardware

Each stream is supported by a dedicated hardware channel, including source and

destination controllers, as well as a FIFO. This enables better latency than a DMA

controller with only a single hardware channel shared between several DMA streams and

simplifies the control logic.

4.1.8 DMA request priority

DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7

has the lowest priority.

If the DMA Controller is transferring data for the lower priority channel and then the higher

priority channel goes active, it completes the number of transfers delegated to the master

interface by the lower priority channel before switching over to transfer data for the higher

priority channel. Transfers delegated to the master interface are staged in the DMA

channel FIFO, so the amount of data that needs to transfer could be as large as a 4

words.

It is recommended that memory-to-memory transactions use the lowest priority channel.

4.1.9 Interrupt generation

A combined interrupt output is generated as an OR function of the individual interrupt

requests of the DMA Controller and is connected to the interrupt controller.

4.2 DMA system connections

4.2.1 DMA request signals

The DMA request signals are used by peripherals to request a data transfer. The DMA

request signals indicate whether a single or burst transfer of data is required. The DMA

available request signals are:

DMACBREQ[15:0] — Burst request signals. These cause a programmed burst number

of data to be transferred.

DMACSREQ[15:0] — Single transfer request signals. These cause a single data to be

transferred. The DMA controller transfers a single transfer to or from the peripheral.

DMACLBREQ[15:0] — Last burst request signals.

DMACLSREQ[15:0] — Last single transfer request signals.

Note that peripherals on this device do not support “last” request types, and many do not

support both single and burst request types. See Section 31–4.2.3.

4.2.2 DMA response signals

The DMA response signals indicate whether the transfer initiated by the DMA request

signal has completed. The response signals can also be used to indicate whether a

complete packet has been transferred. The DMA response signals from the DMA

controller are:

DMACCLR[15:0] — DMA clear or acknowledge signals. The DMACCLR signal is used by

the DMA controller to acknowledge a DMA request from the peripheral.

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DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the

DMA controller to indicate to the peripheral that the DMA transfer is complete.

4.2.3 DMA request connections

The connection of the GPDMA to the supported peripheral devices depends on the DMA

functions implemented in those peripherals. Table 31–544 shows the DMA Request

numbers used by the supported peripherals. UART and timer DMA requests on channels

8 through 15 are chosen via the DMAREQSEL register, see Section 31–5.15.

Table 544. DMA Connections

Peripheral Function DMA Single Request DMA Burst Request DMA Request Signal

Input (DMACSREQ) Input (DMACBREQ)

SSP0 Tx

0

1

2

3

4

-

0

Dedicated DMA requests

ADC interrupt request ^[1]

Dedicated DMA request

Dedicated DMA requests

SSP0 Rx

1

SSP1 Tx

2

SSP1 Rx

3

ADC

4

I²S channel 0

I²S channel 1

DAC

5

-

6

-

7

UART0 Tx / MAT0.0

UART0 Rx / MAT0.1

UART1 Tx / MAT1.0

UART1 Rx / MAT1.1

UART2 Tx / MAT2.0

UART2 Rx / MAT2.1

UART3 Tx / MAT3.0

UART3 Rx / MAT3.1

-

8

-

9

-

10

11

12

13

14

15

-

[1] Generates an interrupt and/or DMA request depending on software setup.

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5. Register description

The DMA Controller supports 8 channels. Each channel has registers specific to the

operation of that channel. Other registers controls aspects of how source peripherals

relate to the DMA Controller. There are also global DMA control and status registers.

The DMA Controller registers are shown in Table 31–545.

Table 545. GPDMA register map

Name

Description

Access Reset Address

state

General registers

DMACIntStat

DMA Interrupt Status Register

RO

0

-

0x5000 4000

0x5000 4004

0x5000 4008

0x5000 400C

0x5000 4010

0x5000 4014

0x5000 4018

0x5000 401C

0x5000 4020

0x5000 4024

0x5000 4028

0x5000 402C

0x5000 4030

0x5000 4034

0x400F C1C4

DMACIntTCStat

DMACIntTCClear

DMACIntErrStat

DMACIntErrClr

DMACRawIntTCStat

DMACRawIntErrStat

DMACEnbldChns

DMACSoftBReq

DMACSoftSReq

DMACSoftLBReq

DMACSoftLSReq

DMACConfig

DMA Interrupt Terminal Count Request Status Register RO

DMA Interrupt Terminal Count Request Clear Register

DMA Interrupt Error Status Register

WO

RO

0

-

DMA Interrupt Error Clear Register

WO

RO

DMA Raw Interrupt Terminal Count Status Register

DMA Raw Error Interrupt Status Register

DMA Enabled Channel Register

0

RO

DMA Software Burst Request Register

DMA Software Single Request Register

DMA Software Last Burst Request Register

DMA Software Last Single Request Register

DMA Configuration Register

R/W

DMACSync

DMA Synchronization Register

DMAREQSEL

Selects between UART and timer DMA requests on

channels 8 through 15

Channel 0 registers

DMACC0SrcAddr

DMACC0DestAddr

DMACC0LLI

DMA Channel 0 Source Address Register

DMA Channel 0 Destination Address Register

DMA Channel 0 Linked List Item Register

DMA Channel 0 Control Register

R/W

0

0x5000 4100

0x5000 4104

0x5000 4108

0x5000 410C

0x5000 4110

0

DMACC0Control

DMACC0Config

Channel 1 registers

DMACC1SrcAddr

DMACC1DestAddr

DMACC1LLI

0

DMA Channel 0 Configuration Register

0 ^[1]

DMA Channel 1 Source Address Register

DMA Channel 1 Destination Address Register

DMA Channel 1 Linked List Item Register

DMA Channel 1 Control Register

R/W

0

0x5000 4120

0x5000 4124

0x5000 4128

0x5000 412C

0x5000 4130

0

DMACC1Control

DMACC1Config

Channel 2 registers

DMACC2SrcAddr

DMACC2DestAddr

DMACC2LLI

0

DMA Channel 1 Configuration Register

0 ^[1]

DMA Channel 2 Source Address Register

DMA Channel 2 Destination Address Register

DMA Channel 2 Linked List Item Register

DMA Channel 2 Control Register

R/W

0

0x5000 4140

0x5000 4144

0x5000 4148

0x5000 414C

DMACC2Control

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Table 545. GPDMA register map

Name

Description

Access Reset Address

state

DMACC2Config

Channel 3 registers

DMACC3SrcAddr

DMACC3DestAddr

DMACC3LLI

DMA Channel 2 Configuration Register

R/W

0 ^[1]

0x5000 4150

DMA Channel 3 Source Address Register

DMA Channel 3 Destination Address Register

DMA Channel 3 Linked List Item Register

DMA Channel 3 Control Register

R/W

0

0x5000 4160

0x5000 4164

0x5000 4168

0x5000 416C

0x5000 4170

0

DMACC3Control

DMACC3Config

Channel 4 registers

DMACC4SrcAddr

DMACC4DestAddr

DMACC4LLI

0

DMA Channel 3 Configuration Register

0 ^[1]

DMA Channel 4 Source Address Register

DMA Channel 4 Destination Address Register

DMA Channel 4 Linked List Item Register

DMA Channel 4 Control Register

R/W

0

0x5000 4180

0x5000 4184

0x5000 4188

0x5000 418C

0x5000 4190

0

DMACC4Control

DMACC4Config

Channel 5 registers

DMACC5SrcAddr

DMACC5DestAddr

DMACC5LLI

0

DMA Channel 4 Configuration Register

0 ^[1]

DMA Channel 5 Source Address Register

DMA Channel 5 Destination Address Register

DMA Channel 5 Linked List Item Register

DMA Channel 5 Control Register

R/W

0

0x5000 41A0

0x5000 41A4

0x5000 41A8

0x5000 41AC

0x5000 41B0

0

DMACC5Control

DMACC5Config

Channel 6 registers

DMACC6SrcAddr

DMACC6DestAddr

DMACC6LLI

0

DMA Channel 5 Configuration Register

0 ^[1]

DMA Channel 6 Source Address Register

DMA Channel 6 Destination Address Register

DMA Channel 6 Linked List Item Register

DMA Channel 6 Control Register

R/W

0

0x5000 41C0

0x5000 41C4

0x5000 41C8

0x5000 41CC

0x5000 41D0

0

DMACC6Control

DMACC6Config

Channel 7 registers

DMACC7SrcAddr

DMACC7DestAddr

DMACC7LLI

0

DMA Channel 6 Configuration Register

0 ^[1]

DMA Channel 7 Source Address Register

DMA Channel 7 Destination Address Register

DMA Channel 7 Linked List Item Register

DMA Channel 7 Control Register

R/W

0

0x5000 41E0

0x5000 41E4

0x5000 41E8

0x5000 41EC

0x5000 41F0

0

DMACC7Control

DMACC7Config

0

DMA Channel 7 Configuration Register

0 ^[1]

[1] Bit 17 of this register is a read-only status flag.

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5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000)

The DMACIntStat Register is read-only and shows the status of the interrupts after

masking. A 1 bit indicates that a specific DMA channel interrupt request is active. The

request can be generated from either the error or terminal count interrupt requests.

Table 31–546 shows the bit assignments of the DMACIntStat Register.

Table 546. DMA Interrupt Status register (DMACIntStat - 0x5000 4000)

Bit

Name

Function

7:0

IntStat

Status of DMA channel interrupts after masking. Each bit represents one channel:

0 - the corresponding channel has no active interrupt request.

1 - the corresponding channel does have an active interrupt request.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.2 DMA Interrupt Terminal Count Request Status register

(DMACIntTCStat - 0x5000 4004)

The DMACIntTCStat Register is read-only and indicates the status of the terminal count

after masking. Table 31–547 shows the bit assignments of the DMACIntTCStat Register.

Table 547. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004)

Bit

Name

Function

7:0

IntTCStat

Terminal count interrupt request status for DMA channels. Each bit represents one

channel:

0 - the corresponding channel has no active terminal count interrupt request.

1 - the corresponding channel does have an active terminal count interrupt request.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.3 DMA Interrupt Terminal Count Request Clear register

(DMACIntTCClear - 0x5000 4008)

The DMACIntTCClear Register is write-only and clears one or more terminal count

interrupt requests. When writing to this register, each data bit that contains a 1 causes the

corresponding bit in the status register (DMACIntTCStat) to be cleared. Data bits that are

0 have no effect. Table 31–548 shows the bit assignments of the DMACIntTCClear

Register.

Table 548. DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008)

Bit

Name

Function

7:0

IntTCClear

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels.

Each bit represents one channel:

0 - writing 0 has no effect.

1 - clears the corresponding channel terminal count interrupt.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.4 DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)

The DMACIntErrStat Register is read-only and indicates the status of the error request

after masking. Table 31–549 shows the bit assignments of the DMACIntErrStat Register.

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Table 549. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)

Bit

Name

Function

7:0

IntErrStat

Interrupt error status for DMA channels. Each bit represents one channel:

0 - the corresponding channel has no active error interrupt request.

1 - the corresponding channel does have an active error interrupt request.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.5 DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)

The DMACIntErrClr Register is write-only and clears the error interrupt requests. When

writing to this register, each data bit that is 1 causes the corresponding bit in the status

register to be cleared. Data bits that are 0 have no effect on the corresponding bit in the

register. Table 31–550 shows the bit assignments of the DMACIntErrClr Register.

Table 550. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)

Bit

Name

Function

7:0

IntErrClr

Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit

represents one channel:

0 - writing 0 has no effect.

1 - clears the corresponding channel error interrupt.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.6 DMA Raw Interrupt Terminal Count Status register

(DMACRawIntTCStat - 0x5000 4014)

The DMACRawIntTCStat Register is read-only and indicates which DMA channel is

requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the

DMACIntTCStat Register contains the same information after masking.) A 1 bit indicates

that the terminal count interrupt request is active prior to masking. Table 31–551 shows

the bit assignments of the DMACRawIntTCStat Register.

Table 551. DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014)

Bit

Name

Function

7:0

RawIntTCStat

Status of the terminal count interrupt for DMA channels prior to masking. Each bit

represents one channel:

0 - the corresponding channel has no active terminal count interrupt request.

1 - the corresponding channel does have an active terminal count interrupt request.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.7 DMA Raw Error Interrupt Status register (DMACRawIntErrStat -

0x5000 4018)

The DMACRawIntErrStat Register is read-only and indicates which DMA channel is

requesting an error interrupt prior to masking. (Note: the DMACIntErrStat Register

contains the same information after masking.) A 1 bit indicates that the error interrupt

request is active prior to masking. Table 31–552 shows the bit assignments of register of

the DMACRawIntErrStat Register.

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Table 552. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018)

Bit

Name

Function

7:0

RawIntErrStat

Status of the error interrupt for DMA channels prior to masking. Each bit represents

one channel:

0 - the corresponding channel has no active error interrupt request.

1 - the corresponding channel does have an active error interrupt request.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.8 DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)

The DMACEnbldChns Register is read-only and indicates which DMA channels are

enabled, as indicated by the Enable bit in the DMACCxConfig Register. A 1 bit indicates

that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer.

Table 31–553 shows the bit assignments of the DMACEnbldChns Register.

Table 553. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)

Bit

Name

Function

7:0

EnabledChannels

Enable status for DMA channels. Each bit represents one channel:

0 - DMA channel is disabled.

1 - DMA channel is enabled.

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.9 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)

The DMACSoftBReq Register is read/write and enables DMA burst requests to be

generated by software. A DMA request can be generated for each source by writing a 1 to

the corresponding register bit. A register bit is cleared when the transaction has

completed. Reading the register indicates which sources are requesting DMA burst

transfers. A request can be generated from either a peripheral or the software request

register. Each bit is cleared when the related transaction has completed. Table 31–554

shows the bit assignments of the DMACSoftBReq Register.

Table 554. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)

Bit

Name

Function

15:0

SoftBReq

Software burst request flags for each of 16 possible sources. Each bit represents one

DMA request line or peripheral function (refer to Table 31–544 for peripheral

hardware connections to the DMA controller):

0 - writing 0 has no effect.

1 - writing 1 generates a DMA burst request for the corresponding request line.

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

Note: It is recommended that software and hardware peripheral requests are not used at

the same time.

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5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000

4024)

The DMACSoftSReq Register is read/write and enables DMA single transfer requests to

be generated by software. A DMA request can be generated for each source by writing a

1 to the corresponding register bit. A register bit is cleared when the transaction has

completed. Reading the register indicates which sources are requesting single DMA

transfers. A request can be generated from either a peripheral or the software request

register. Table 31–555 shows the bit assignments of the DMACSoftSReq Register.

Table 555. DMA Software Single Request register (DMACSoftSReq - 0x5000 4024)

Bit

Name

Function

15:0

SoftSReq

Software single transfer request flags for each of 16 possible sources. Each bit

represents one DMA request line or peripheral function:

0 - writing 0 has no effect.

1 - writing 1 generates a DMA single transfer request for the corresponding request

line.

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.11 DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000

4028)

The DMACSoftLBReq Register is read/write and enables DMA last burst requests to be

generated by software. A DMA request can be generated for each source by writing a 1 to

the corresponding register bit. A register bit is cleared when the transaction has

completed. Reading the register indicates which sources are requesting last burst DMA

transfers. A request can be generated from either a peripheral or the software request

register. Table 31–556 shows the bit assignments of the DMACSoftLBReq Register.

Table 556. DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028)

Bit

Name

Function

15:0

SoftLBReq

Software last burst request flags for each of 16 possible sources. Each bit represents

one DMA request line or peripheral function:

0 - writing 0 has no effect.

1 - writing 1 generates a DMA last burst request for the corresponding request line.

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.12 DMA Software Last Single Request register (DMACSoftLSReq -

0x5000 402C)

The DMACSoftLSReq Register is read/write and enables DMA last single requests to be

generated by software. A DMA request can be generated for each source by writing a 1 to

the corresponding register bit. A register bit is cleared when the transaction has

completed. Reading the register indicates which sources are requesting last single DMA

transfers. A request can be generated from either a peripheral or the software request

register. Table 31–557 shows the bit assignments of the DMACSoftLSReq Register.

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Table 557. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C)

Bit

Name

Function

15:0

SoftLSReq

Software last single transfer request flags for each of 16 possible sources. Each bit

represents one DMA request line or peripheral function:

0 - writing 0 has no effect.

1 - writing 1 generates a DMA last single transfer request for the corresponding

request line.

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.13 DMA Configuration register (DMACConfig - 0x5000 4030)

The DMACConfig Register is read/write and configures the operation of the DMA

Controller. The endianness of the AHB master interface can be altered by writing to the M

bit of this register. The AHB master interface is set to little-endian mode on reset.

Table 31–558 shows the bit assignments of the DMACConfig Register.

Table 558. DMA Configuration register (DMACConfig - 0x5000 4030)

Bit

Name

Function

0

E

DMA Controller enable:

0 = disabled (default). Disabling the DMA Controller reduces power consumption.

1 = enabled.

1

M

-

AHB Master endianness configuration:

0 = little-endian mode (default).

1 = big-endian mode.

31:2

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.14 DMA Synchronization register (DMACSync - 0x5000 4034)

The DMACSync Register is read/write and enables or disables synchronization logic for

the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],

DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables

the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the

synchronization logic for a particular group of DMA requests. This register is reset to 0,

synchronization logic enabled. Table 31–559 shows the bit assignments of the

DMACSync Register.

Table 559. DMA Synchronization register (DMACSync - 0x5000 4034)

Bit

Name

Function

15:0

DMACSync

Controls the synchronization logic for DMA request signals. Each bit represents one

set of DMA request lines as described in the preceding text:

0 - synchronization logic for the corresponding DMA request signals are disabled.

1 - synchronization logic for the corresponding request line signals are enabled.

31:16

-

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

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5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4)

DMAReqSel is a read/write register that allows selecting between UART or Timer DMA

requests for DMA inputs 8 through 15. Table 31–560 shows the bit assignments of the

DMAReqSel Register.

Table 560. DMA Request Select register (DMAReqSel - 0x400F C1C4)

Bit

Name

Function

0

DMASEL08

Selects the DMA request for GPDMA input 8:

0 - UART0 TX is selected.

1 - Timer 0 match 0 is selected.

Selects the DMA request for GPDMA input 9:

0 - UART0 RX is selected.

1

DMASEL09

DMASEL10

DMASEL11

DMASEL12

DMASEL13

DMASEL14

DMASEL15

-

1 - Timer 0 match 1 is selected.

Selects the DMA request for GPDMA input 10:

0 - UART1 TX is selected.

2

1 - Timer 1match 0 is selected.

Selects the DMA request for GPDMA input 11:

0 - UART1 RX is selected.

3

1 - Timer 1match 1 is selected.

Selects the DMA request for GPDMA input 12:

0 - UART2 TX is selected.

4

1 - Timer 2 match 0 is selected.

Selects the DMA request for GPDMA input 13:

0 - UART2 RX is selected.

5

1 - Timer 2 match 1 is selected.

Selects the DMA request for GPDMA input 14:

0 - UART3 TX is selected.

6

1 - Timer 3 match 0 is selected.

Selects the DMA request for GPDMA input 15:

0 - UART3 RX is selected.

7

1 - Timer 3 match 1 is selected.

31:8

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

5.16 DMA Channel registers

The channel registers are used to program the eight DMA channels. These registers

consist of:

• Eight DMACCxSrcAddr Registers.

• Eight DMACCxDestAddr Registers.

• Eight DMACCxLLI Registers.

• Eight DMACCxControl Registers.

• Eight DMACCxConfig Registers.

When performing scatter/gather DMA, the first four of these are automatically updated.

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5.17 DMA Channel Source Address registers (DMACCxSrcAddr -

0x5000 41x0)

The eight read/write DMACCxSrcAddr Registers (DMACC0SrcAddr to DMACC7SrcAddr)

contain the current source address (byte-aligned) of the data to be transferred. Each

register is programmed directly by software before the appropriate channel is enabled.

When the DMA channel is enabled this register is updated:

• As the source address is incremented.

• By following the linked list when a complete packet of data has been transferred.

Reading the register when the channel is active does not provide useful information. This

is because by the time software has processed the value read, the address may have

progressed. It is intended to be read-only when the channel has stopped, in which case it

shows the source address of the last item read.

Note: The source and destination addresses must be aligned to the source and

destination widths.

Table 31–561 shows the bit assignments of the DMACCxSrcAddr Registers.

Table 561. DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0)

Bit

Name

Function

31:0

SrcAddr

DMA source address. Reading this register will return the current source address.

5.18 DMA Channel Destination Address registers (DMACCxDestAddr -

0x5000 41x4)

The eight read/write DMACCxDestAddr Registers (DMACC0DestAddr to

DMACC7DestAddr) contain the current destination address (byte-aligned) of the data to

be transferred. Each register is programmed directly by software before the channel is

enabled. When the DMA channel is enabled the register is updated as the destination

address is incremented and by following the linked list when a complete packet of data

has been transferred. Reading the register when the channel is active does not provide

useful information. This is because by the time that software has processed the value

read, the address may have progressed. It is intended to be read-only when a channel

has stopped, in which case it shows the destination address of the last item read.

Table 31–562 shows the bit assignments of the DMACCxDestAddr Register.

Table 562. DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4)

Bit

Name

Function

31:0

DestAddr

DMA Destination address. Reading this register will return the current destination

address.

5.19 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)

The eight read/write DMACCxLLI Registers (DMACC0LLI to DMACC7LLI) contain a

word-aligned address of the next Linked List Item (LLI). If the LLI is 0, then the current LLI

is the last in the chain, and the DMA channel is disabled when all DMA transfers

associated with it are completed. Programming this register when the DMA channel is

enabled may have unpredictable side effects. Table 31–563 shows the bit assignments of

the DMACCxLLI Register.

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Table 563. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)

Bit

Name

Function

1:0

-

Reserved, and must be written as 0.

31:2

LLI

Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.

5.20 DMA channel control registers (DMACCxControl - 0x5000 41xC)

The eight read/write DMACCxControl Registers (DMACC0Control to DMACC7Control)

contain DMA channel control information such as the transfer size, burst size, and transfer

width. Each register is programmed directly by software before the DMA channel is

enabled. When the channel is enabled the register is updated by following the linked list

when a complete packet of data has been transferred. Reading the register while the

channel is active does not give useful information. This is because by the time software

has processed the value read, the channel may have advanced. It is intended to be

read-only when a channel has stopped. Table 31–564 shows the bit assignments of the

DMACCxControl Register.

5.20.1 Protection and access information

AHB access information is provided to the source and/or destination peripherals when a

transfer occurs, although on the LPC17xx this has no effect. The transfer information is

provided by programming the DMA channel (the Prot bits of the DMACCxControl

Register, and the Lock bit of the DMACCxConfig Register). These bits are programmed

by software, and can be used by peripherals. Three bits of information are provided, and

are used as shown in Table 31–564.

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Table 564. DMA channel control registers (DMACCxControl - 0x5000 41xC)

Bit Name Function

11:0 TransferSize Transfer size. This field sets the size of the transfer. The transfer size value must be set before the

channel is enabled. Transfer size is updated as data transfers are completed.

A read from this field indicates the number of transfers completed on the destination bus. Reading

the register when the channel is active does not give useful information because by the time that the

software has processed the value read, the channel might have progressed. It is intended to be used

only when a channel is enabled and then disabled.

14:12 SBSize

Source burst size. Indicates the number of transfers that make up a source burst. This value must be

set to the burst size of the source peripheral, or if the source is memory, to the memory boundary

size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes

active in the source peripheral.

000 - 1

001 - 4

010 - 8

011 - 16

100 - 32

101 - 64

110 - 128

111 - 256

17:15 DBSize

Destination burst size. Indicates the number of transfers that make up a destination burst transfer

request. This value must be set to the burst size of the destination peripheral or, if the destination is

memory, to the memory boundary size. The burst size is the amount of data that is transferred when

the DMACBREQ signal goes active in the destination peripheral.

000 - 1

001 - 4

010 - 8

011 - 16

100 - 32

101 - 64

110 - 128

111 - 256

20:18 SWidth

23:21 DWidth

25:24 -

Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and

destination widths can be different from each other. The hardware automatically packs and unpacks

the data as required.

000 - Byte (8-bit)

001 - Halfword (16-bit)

010 - Word (32-bit)

011 to 111 - Reserved

Destination transfer width. Transfers wider than the AHB master bus width are not supported. The

source and destination widths can be different from each other. The hardware automatically packs

and unpacks the data as required.

000 - Byte (8-bit)

001 - Halfword (16-bit)

010 - Word (32-bit)

011 to 111 - Reserved

Reserved, and must be written as 0.

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Table 564. DMA channel control registers (DMACCxControl - 0x5000 41xC) …continued

Bit

Name

Function

26

SI

Source increment:

0 - the source address is not incremented after each transfer.

1 - the source address is incremented after each transfer.

Destination increment:

27

28

DI

0 - the destination address is not incremented after each transfer.

1 - the destination address is incremented after each transfer.

Prot1

This is provided to the peripheral during a DMA bus access and indicates that the access is in user

mode or privileged mode. This information is not used in the LPC17xx.

0 - access is in user mode.

1 - access is in privileged mode.

29

30

31

Prot2

Prot3

I

This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the

access is bufferable or not bufferable. This information is not used in the LPC17xx.

0 - access is not bufferable.

1 - access is bufferable.

This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the

access is cacheable or not cacheable. This information is not used in the LPC17xx.

0 - access is not cacheable.

1 - access is cacheable.

Terminal count interrupt enable bit.

0 - the terminal count interrupt is disabled.

1 - the terminal count interrupt is enabled.

5.21 DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)

The eight DMACCxConfig Registers (DMACC0Config to DMACC7Config) are read/write

with the exception of bit[17] which is read-only. Used these to configure the DMA channel.

The registers are not updated when a new LLI is requested. Table 31–565 shows the bit

assignments of the DMACCxConfig Register.

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Table 565. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)

Bit

Name

Function

0

E

Channel enable. Reading this bit indicates whether a channel is currently enabled or

disabled:

0 = channel disabled.

1 = channel enabled.

The Channel Enable bit status can also be found by reading the DMACEnbldChns

Register.

A channel is enabled by setting this bit.

A channel can be disabled by clearing the Enable bit. This causes the current AHB

transfer (if one is in progress) to complete and the channel is then disabled. Any data

in the FIFO of the relevant channel is lost. Restarting the channel by setting the

Channel Enable bit has unpredictable effects, the channel must be fully re-initialized.

The channel is also disabled, and Channel Enable bit cleared, when the last LLI is

reached, the DMA transfer is completed, or if a channel error is encountered.

If a channel must be disabled without losing data in the FIFO, the Halt bit must be set

so that further DMA requests are ignored. The Active bit must then be polled until it

reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable

bit can be cleared.

5:1

SrcPeripheral

DestPeripheral

TransferType

Source peripheral. This value selects the DMA source request peripheral. This field is

ignored if the source of the transfer is from memory. See Table 31–544 for peripheral

identification.

10:6

13:11

Destination peripheral. This value selects the DMA destination request peripheral.

This field is ignored if the destination of the transfer is to memory. See Table 31–544

for peripheral identification.

This value indicates the type of transfer. The transfer type can be

memory-to-memory, memory-to-peripheral, peripheral-to-memory, or

peripheral-to-peripheral.

Refer to Table 31–566 for the encoding of this field.

14

15

16

17

IE

ITC

L

Interrupt error mask. When cleared, this bit masks out the error interrupt of the

relevant channel.

Terminal count interrupt mask. When cleared, this bit masks out the terminal count

interrupt of the relevant channel.

Lock. When set, this bit enables locked transfers. This information is not used in the

LPC17xx.

A

Active:

0 = there is no data in the FIFO of the channel.

1 = the channel FIFO has data.

This value can be used with the Halt and Channel Enable bits to cleanly disable a

DMA channel. This is a read-only bit.

18

H

Halt:

0 = enable DMA requests.

1 = ignore further source DMA requests.

The contents of the channel FIFO are drained.

This value can be used with the Active and Channel Enable bits to cleanly disable a

DMA channel.

31:19

Reserved

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

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5.21.1 Lock control

The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig

Register. When a burst occurs, the AHB arbiter will not de-grant the master during the

burst until the lock is de-asserted. The DMA Controller can be locked for a a single burst

such as a long source fetch burst or a long destination drain burst. The DMA Controller

does not usually assert the lock continuously for a source fetch burst followed by a

destination drain burst.

There are situations when the DMA Controller asserts the lock for source transfers

followed by destination transfers. This is possible when internal conditions in the DMA

Controller permit it to perform a source fetch followed by a destination drain back-to-back.

5.21.2 Transfer type

Table 31–566 lists the bit values of the transfer type bits identified in Table 31–565.

Table 566. Transfer type bits

Bit value

000

Transfer type

Controller

DMA

-

Memory to memory

001

Memory to peripheral

010

Peripheral to memory

011

Source peripheral to destination peripheral

Reserved, do not use these combinations

100 to 111

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6. Using the DMA controller

6.1 Programming the DMA controller

All accesses to the DMA Controller internal register must be word (32-bit) reads and

writes.

6.1.1 Enabling the DMA controller

To enable the DMA controller set the Enable bit in the DMACConfig register.

6.1.2 Disabling the DMA controller

To disable the DMA controller:

• Read the DMACEnbldChns register and ensure that all the DMA channels have been

disabled. If any channels are active, see Disabling a DMA channel.

• Disable the DMA controller by writing 0 to the DMA Enable bit in the DMACConfig

register.

6.1.3 Enabling a DMA channel

To enable the DMA channel set the channel enable bit in the relevant DMA channel

configuration register. Note that the channel must be fully initialized before it is enabled.

6.1.4 Disabling a DMA channel

A DMA channel can be disabled in three ways:

• By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost

if this method is used.

• By using the active and halt bits in conjunction with the channel enable bit.

• By waiting until the transfer completes. This automatically clears the channel.

Disabling a DMA channel and losing data in the FIFO

Clear the relevant channel enable bit in the relevant channel configuration register. The

current AHB transfer (if one is in progress) completes and the channel is disabled. Any

data in the FIFO is lost.

Disabling the DMA channel without losing data in the FIFO

• Set the halt bit in the relevant channel configuration register. This causes any future

DMA request to be ignored.

• Poll the active bit in the relevant channel configuration register until it reaches 0. This

bit indicates whether there is any data in the channel that has to be transferred.

• Clear the channel enable bit in the relevant channel configuration register

6.1.5 Setting up a new DMA transfer

To set up a new DMA transfer:

If the channel is not set aside for the DMA transaction:

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1. Read the DMACEnbldChns controller register and find out which channels are

inactive.

2. Choose an inactive channel that has the required priority.

3. Program the DMA controller

6.1.6 Halting a DMA channel

Set the halt bit in the relevant DMA channel configuration register. The current source

request is serviced. Any further source DMA request is ignored until the halt bit is cleared.

6.1.7 Programming a DMA channel

1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest

priority and DMA channel 7 the lowest priority.

2. Clear any pending interrupts on the channel to be used by writing to the

DMACIntTCClear and DMACIntErrClear register. The previous channel operation

might have left interrupt active.

3. Write the source address into the DMACCxSrcAddr register.

4. Write the destination address into the DMACCxDestAddr register.

5. Write the address of the next LLI into the DMACCxLLI register. If the transfer

comprises of a single packet of data then 0 must be written into this register.

6. Write the control information into the DMACCxControl register.

7. Write the channel configuration information into the DMACCxConfig register. If the

enable bit is set then the DMA channel is automatically enabled.

6.2 Flow control

The device that controls the length of the packet is known as the flow controller. On the

LPC17xx, the flow controller is always the DMA Controller, and the packet length is

programmed by software before the DMA channel is enabled.

When the DMA transfer is completed:

1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that

the transfer has finished.

2. A TC interrupt is generated, if enabled.

3. The DMA Controller moves on to the next LLI.

The following sections describe the DMA Controller data flow sequences for the four

allowed transfer types:

• Memory-to-peripheral.

• Peripheral-to-memory.

• Memory-to-memory.

• Peripheral-to-peripheral.

Table 31–567 indicates the request signals used for each type of transfer.

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Table 567. DMA request signal usage

Transfer direction

Request generator

Peripheral

Flow controller

DMA Controller

Memory-to-peripheral

Peripheral-to-memory

Peripheral

Memory-to-memory

DMA Controller

Source peripheral to destination peripheral

Source peripheral and destination peripheral

6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow

For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence

occurs:

1. Program and enable the DMA channel.

2. Wait for a DMA request.

3. The DMA Controller starts transferring data when:

– The DMA request goes active.

– The DMA stream has the highest pending priority.

– The DMA Controller is the bus master of the AHB bus.

4. If an error occurs while transferring the data, an error interrupt is generated and

disables the DMA stream, and the flow sequence ends.

5. Decrement the transfer count.

6. If the transfer has completed (indicated by the transfer count reaching 0):

– The DMA Controller responds with a DMA acknowledge.

– The terminal count interrupt is generated (this interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,

DMACCxDestAddr, DMACCxLLI, and DMACCxControl registers and go to back to

step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow

sequence ends.

6.2.2 Peripheral-to-peripheral DMA flow

For a peripheral-to-peripheral DMA flow, the following sequence occurs:

1. Program and enable the DMA channel.

2. Wait for a source DMA request.

3. The DMA Controller starts transferring data when:

– The DMA request goes active.

– The DMA stream has the highest pending priority.

– The DMA Controller is the bus master of the AHB bus.

4. If an error occurs while transferring the data an error interrupt is generated, the DMA

stream is disabled, and the flow sequence ends.

5. Decrement the transfer count.

6. If the transfer has completed (indicated by the transfer count reaching 0):

– The DMA Controller responds with a DMA acknowledge to the source peripheral.

– Further source DMA requests are ignored.

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7. When the destination DMA request goes active and there is data in the DMA

Controller FIFO, transfer data into the destination peripheral.

8. If an error occurs while transferring the data, an error interrupt is generated, the DMA

stream is disabled, and the flow sequence ends.

9. If the transfer has completed it is indicated by the transfer count reaching 0. The

following happens:

– The DMA Controller responds with a DMA acknowledge to the destination

peripheral.

– The terminal count interrupt is generated (this interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,

DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back

to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow

sequence ends.

6.2.3 Memory-to-memory DMA flow

For a memory-to-memory DMA flow the following sequence occurs:

1. Program and enable the DMA channel.

2. Transfer data whenever the DMA channel has the highest pending priority and the

DMA Controller gains mastership of the AHB bus.

3. If an error occurs while transferring the data, generate an error interrupt and disable

the DMA stream.

4. Decrement the transfer count.

5. If the count has reached zero:

– Generate a terminal count interrupt (the interrupt can be masked).

– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,

DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back

to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow

sequence ends.

Note: Memory-to-memory transfers should be programmed with a low channel priority,

otherwise other DMA channels cannot access the bus until the memory-to-memory

transfer has finished, or other AHB masters cannot perform any transaction.

6.3 Interrupt requests

Interrupt requests can be generated when an AHB error is encountered or at the end of a

transfer (terminal count), after all the data corresponding to the current LLI has been

transferred to the destination. The interrupts can be masked by programming bits in the

relevant DMACCxControl and DMACCxConfig Channel Registers. The interrupt requests

from all DMA channels can be found in the DMACRawIntTCStat and DMACRawIntErrStat

registers. The masked versions of the DMA interrupt data is contained in the

DMACIntTCStat and DMACIntErrStat registers. The DMACIntStat register then combines

the DMACIntTCStat and DMACIntErrStat requests into a single register to enable the

source of an interrupt to be found quickly. Writing to the DMACIntTCClear or the

DMACIntErrClr Registers with a bit set to 1 enables selective clearing of interrupts.

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6.3.1 Hardware interrupt sequence flow

When a DMA interrupt request occurs, the Interrupt Service Routine needs to:

1. Read the DMACIntTCStat Register to determine whether the interrupt was generated

due to the end of the transfer (terminal count). A 1 bit indicates that the transfer

completed. If more than one request is active, it is recommended that the highest

priority channels be checked first.

2. Read the DMACIntErrStat Register to determine whether the interrupt was generated

due to an error occurring. A 1 bit indicates that an error occurred.

3. Service the interrupt request.

4. For a terminal count interrupt, write a 1 to the relevant bit of the DMACIntTCClr

Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr

Register to clear the interrupt request.

6.4 Address generation

Address generation can be either incrementing or non-incrementing (address wrapping is

not supported).

Some devices, especially memories, disallow burst accesses across certain address

boundaries. The DMA controller assumes that this is the case with any source or

destination area, which is configured for incrementing addressing. This boundary is

assumed to be aligned with the specified burst size. For example, if the channel is set for

16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is

address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,

instead of a burst, that transfer is split into separate AHB transactions.

6.4.1 Word-aligned transfers across a boundary

The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a

destination for which address incrementing is enabled. The start address for the current

burst is 0x0C000024, the next boundary (calculated from the burst size and transfer

width) is 0x0C000040.

The transfer will be split into two AHB transactions:

• a 7-transfer burst starting at address 0x0C000024

• a 9-transfer burst starting at address 0x0C000040.

6.5 Scatter/gather

Scatter/gather is supported through the use of linked lists. This means that the source and

destination areas do not have to occupy contiguous areas in memory. Where

scatter/gather is not required, the DMACCxLLI Register must be set to 0.

The source and destination data areas are defined by a series of linked lists. Each Linked

List Item (LLI) controls the transfer of one block of data, and then optionally loads another

LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed

into the DMA Controller.

The data to be transferred described by an LLI (referred to as the packet of data) usually

requires one or more DMA bursts (to each of the source and destination).

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6.5.1 Linked list items

A Linked List Item (LLI) consists of four words. These words are organized in the following

order:

1. DMACCxSrcAddr.

2. DMACCxDestAddr.

3. DMACCxLLI.

4. DMACCxControl.

Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked

list item.

6.5.1.1 Programming the DMA controller for scatter/gather DMA

To program the DMA Controller for scatter/gather DMA:

1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains

four words:

– Source address.

– Destination address.

– Pointer to next LLI.

– Control word.

The last LLI has its linked list word pointer set to 0.

2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest

priority and DMA channel 7 the lowest priority.

3. Write the first linked list item, previously written to memory, to the relevant channel in

the DMA Controller.

4. Write the channel configuration information to the channel Configuration Register and

set the Channel Enable bit. The DMA Controller then transfers the first and then

subsequent packets of data as each linked list item is loaded.

5. An interrupt can be generated at the end of each LLI depending on the Terminal

Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at

the end of the relevant LLI. The interrupt request must then be serviced and the

relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.

6.5.1.2 Example of scatter/gather DMA

See Figure 31–134 for an example of an LLI. A section of memory is to be transferred to a

peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand

side of the figure. In this example, the LLIs describing the transfer are to be stored

contiguously from address 0x2002 0000, but they could be located anywhere. The right

side of the figure shows the memory containing the data to be transferred.

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Linked List Array

Source address = 0x 2002 A200

LLI1

0x2002 0000

Destination address = peripheral

Next LLI address = 0x2002 0010

Control information = length 3072

Source address = 0x 2002 B200

Destination address = peripheral

Next LLI address = 0x2002 0020

Control information = length 3072

Source address = 0x 2002 C200

Destination address = peripheral

Next LLI address = 0x2002 0030

Control information = length 3072

0x2002 A200

3072 bytes of data

LLI2

0x2002 0010

0x2002 ADFF

0x2002 B200

LLI3

0x2002 0020

0x2002 BDFF

0x2002 C200

0x2002 CDFF

LLI8

0x2002 0070

Source address

= 0x 2003 1200

Destination address = peripheral

Next LLI address = 0 (end of list)

Control information = length 3072

0x2003 1200

0x2003 1DFF

3072 bytes of data

Fig 134. LLI example

The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which

is the data stored from address 0x2002 A200 to 0x2002 ADFF:

• Source start address 0x2002 A200.

• Destination address set to the destination peripheral address.

• Transfer width, word (32-bit).

• Transfer size, 3072 bytes (0XC00).

• Source and destination burst sizes, 16 transfers.

• Next LLI address, 0x2002 0010.

The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:

• Source start address 0x2002 B200.

• Destination address set to the destination peripheral address.

• Transfer width, word (32-bit).

• Transfer size, 3072 bytes (0xC00).

• Source and destination burst sizes, 16 transfers.

• Next LLI address, 0x2002 0020.

A chain of descriptors is built up, each one pointing to the next in the series. To initialize

the DMA stream, the first LLI, 0x2002 0000, is programmed into the DMA Controller.

When the first packet of data has been transferred the next LLI is automatically loaded.

The final LLI is stored at 0x2002 0070 and contains:

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• Source start address 0x2003 1200.

• Destination address set to the destination peripheral address.

• Transfer width, word (32-bit).

• Transfer size, 3072 bytes (0xC00).

• Source and destination burst sizes, 16 transfers.

• Next LLI address, 0x0.

Because the next LLI address is set to zero, this is the last descriptor, and the DMA

channel is disabled after transferring the last item of data. The channel is probably set to

generate an interrupt at this point to indicate to the ARM processor that the channel can

be reprogrammed.

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programming

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1. Introduction

The boot loader controls initial operation after reset and also provides the tools for

programming the flash memory. This could be initial programming of a blank device,

erasure and re-programming of a previously programmed device, or programming of the

flash memory by the application program in a running system.

2. Features

• In-System Programming: In-System programming (ISP) is programming or

reprogramming the on-chip flash memory, using the boot loader software and UART0

serial port. This can be done when the part resides in the end-user board.

• In Application Programming: In-Application (IAP) programming is performing erase

and write operation on the on-chip flash memory, as directed by the end-user

application code.

• Flash signature generation: built-in hardware can generate a signature for a range of

flash addresses, or for the entire flash memory.

3. Description

The flash boot loader code is executed every time the part is powered on or reset. The

loader can execute the ISP command handler or the user application code. A LOW level

after reset at pin P2.10 is considered an external hardware request to start the ISP

command handler. Assuming that power supply pins are on their nominal levels when the

rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled

and the decision on whether to continue with user code or ISP handler is made. If P2.10 is

sampled low and the watchdog overflow flag is set, the external hardware request to start

the ISP command handler is ignored. If there is no request for the ISP command handler

execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.

If a valid user program is found then the execution control is transferred to it. If a valid user

program is not found, the auto-baud routine is invoked.

Pin P2.10 is used as a hardware request signal for ISP and therefore requires special

attention. Since P2.10 is in high impedance mode after reset, it is important that the user

provides external hardware (a pull-up resistor or other device) to put the pin in a defined

state. Otherwise unintended entry into ISP mode may occur.

When ISP mode is entered after a power on reset, the IRC and PLL are used to generate

the CCLK of 14.748 MHz. The baud rates that can easily be obtained in this case are:

9600 baud, 19200 baud, 38400 baud, 57600 baud, 115200 baud, and 230400 baud. This

may not be the case when ISP is invoked by the user application (see Section 32–8.9

“Re-invoke ISP” on page 633).

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A hardware flash signature generation capability is built into the flash memory. this feature

can be used to create a signature that can then be used to verify flash contents. Details of

flash signature generation are in Section 32–10.

3.1 Memory map after any reset

When a user program begins execution after reset, the interrupt vectors are set to point to

the beginning of flash memory.

Fig 135. Map of lower memory

3.1.1 Criterion for Valid User Code

The reserved Cortex-M3 exception vector location 7 (offset 0x 001C in the vector table)

should contain the 2’s complement of the check-sum of table entries 0 through 6. This

causes the checksum of the first 8 table entries to be 0. The boot loader code checksums

the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is

transferred to the user code.

If the signature is not valid, the auto-baud routine synchronizes with the host via serial port

0. The host should send a “?” (0x3F) as a synchronization character and wait for a

response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.

The auto-baud routine measures the bit time of the received synchronization character in

terms of its own frequency and programs the baud rate generator of the serial port. It also

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sends an ASCII string ("Synchronized<CR><LF>") to the host. In response to this the host

should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at

the received characters to verify synchronization. If synchronization is verified then

"OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal

frequency (in kHz) at which the part is running. For example, if the part is running at 10

MHz, the response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is

sent to the host after receiving the crystal frequency. If synchronization is not verified then

the auto-baud routine waits again for a synchronization character. For auto-baud to work

correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal

to 10 MHz.

For more details on Reset, PLL and startup/boot code interaction see Section 4–5.1.1

“PLL0 and startup/boot code interaction”.

Once the crystal frequency is received the part is initialized and the ISP command handler

is invoked. For safety reasons an "Unlock" command is required before executing the

commands resulting in flash erase/write operations and the "Go" command. The rest of

the commands can be executed without the unlock command. The Unlock command is

required to be executed once per ISP session. The Unlock command is explained in

Section 32–7 “ISP commands” on page 620.

3.2 Communication protocol

All ISP commands should be sent as single ASCII strings. Strings should be terminated

with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and

<LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated ASCII

strings. Data is sent and received in UU-encoded format.

3.2.1 ISP command format

"Command Parameter_0 Parameter_1 … Parameter_n<CR><LF>" "Data" (Data only for

Write commands).

3.2.2 ISP response format

"Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> …

Response_n<CR><LF>" "Data" (Data only for Read commands).

3.2.3 ISP data format

The data stream is in UU-encoded format. The UU-encode algorithm converts 3 bytes of

binary data in to 4 bytes of printable ASCII character set. It is more efficient than Hex

format which converts 1 byte of binary data in to 2 bytes of ASCII hex. The sender should

send the check-sum after transmitting 20 UU-encoded lines. The length of any

UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes.

The receiver should compare it with the check-sum of the received bytes. If the

check-sum matches then the receiver should respond with "OK<CR><LF>" to continue

further transmission. If the check-sum does not match the receiver should respond with

"RESEND<CR><LF>". In response the sender should retransmit the bytes.

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3.2.4 ISP flow control

A software XON/XOFF flow control scheme is used to prevent data loss due to buffer

overrun. When the data arrives rapidly, the ASCII control character DC3 (0x13) is sent to

stop the flow of data. Data flow is resumed by sending the ASCII control character DC1

(0x11). The host should also support the same flow control scheme.

3.2.5 ISP command abort

Commands can be aborted by sending the ASCII control character "ESC" (0x1B). This

feature is not documented as a command under "ISP Commands" section. Once the

escape code is received the ISP command handler waits for a new command.

3.2.6 Interrupts during IAP

The on-chip flash memory is not accessible during erase/write operations. When the user

application code starts executing the interrupt vectors from the user flash area are active.

The user should either disable interrupts, or ensure that user interrupt vectors are active in

RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP

call. The IAP code does not use or disable interrupts.

3.2.7 RAM used by ISP command handler

ISP commands use on-chip RAM from 0x1000 0118 to 0x1000 01FF. The user could use

this area, but the contents may be lost upon reset. Flash programming commands use the

top 32 bytes of on-chip RAM. The stack is located at RAM top - 32. The maximum stack

usage is 256 bytes and it grows downwards.

3.2.8 RAM used by IAP command handler

Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stack

usage in the user allocated stack space is 128 bytes and it grows downwards.

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4. Boot process flowchart

RESET

INITIALIZE

no

CRP1/2/3ENABLED?

ENABLE DEBUG

yes

WATCHDOG

FLAG SET?

A

no

yes

USER CODE

VALID?

no

CRP3ENABLED?

yes

EXECUTE INTERNAL

USER CODE

Enter ISP

MODE?

(P2.10=LOW)

no

USER CODE VALID?

no

yes

A

RUN AUTO-BAUD

no

AUTO-BAUD

SUCCESSFUL?

yes

RUN ISP COMMAND

HANDLER²

RECEIVE CRYSTAL

FREQUENCY¹

(1) For details on handling the crystal frequency, see Section 32–8.9 “Re-invoke ISP” on page 633

(2) For details on available ISP commands based on the CRP settings see Section 32–6 “Code Read Protection (CRP)”

Fig 136. Boot process flowchart

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5. Sector numbers

Some IAP and ISP commands operate on "sectors" and specify sector numbers. The

following table indicate the correspondence between sector numbers and memory

addresses for LPC17xx devices containing 32, 64, 128, 256 and 512 kB of flash

respectively. IAP and ISP routines are located in the Boot ROM.

Table 568. Sectors in a LPC17xx device

Sector

Number

Sector

Size [kB]

Start Address

End Address

32 kB

Part

64 kB

Part

128 kB

Part

256 kB

Part

512 kB

Part

0

4

0X0000 0000

0X0000 1000

0X0000 2000

0X0000 3000

0X0000 4000

0X0000 5000

0X0000 6000

0X0000 7000

0x0000 8000

0x0000 9000

0x0000 A000

0x0000 B000

0x0000 C000

0x0000 D000

0x0000 E000

0x0000 F000

0x0001 0000

0x0001 8000

0x0002 0000

0x0002 8000

0x0003 0000

0x0003 8000

0x0004 0000

0x0004 8000

0x0005 0000

0x0005 8000

0x0006 0000

0x0006 8000

0x0007 0000

0x0007 8000

0X0000 0FFF

0X0000 1FFF

0X0000 2FFF

0X0000 3FFF

0X0000 4FFF

0X0000 5FFF

0X0000 6FFF

0X0000 7FFF

0X0000 8FFF

0X0000 9FFF

0X0000 AFFF

0X0000 BFFF

0X0000 CFFF

0X0000 DFFF

0X0000 EFFF

0X0000 FFFF

0x0001 7FFF

0x0001 FFFF

0x0002 7FFF

0x0002 FFFF

0x0003 7FFF

0x0003 FFFF

0x0004 7FFF

0x0004 FFFF

0x0005 7FFF

0x0005 FFFF

0x0006 7FFF

0x0006 FFFF

0x0007 7FFF

0x0007 FFFF

x

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

4

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0X0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

23 (0x17)

24 (0x18)

25 (0x19)

26 (0x1A)

27 (0x1B)

28 (0x1C)

29 (0x1D)

4

32

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6. Code Read Protection (CRP)

Code Read Protection is a mechanism that allows user to enable different levels of

security in the system so that access to the on-chip flash and use of the ISP can be

restricted. When needed, CRP is invoked by programming a specific pattern in flash

location at 0x000002FC. IAP commands are not affected by the code read protection.

Important: Any CRP change becomes effective only after the device has gone

through a power cycle.

Table 569. Code Read Protection options

Name Pattern

programmed in

Description

0x000002FC

CRP1 0x12345678

Access to chip via the JTAG pins is disabled. This mode allows partial

flash update using the following ISP commands and restrictions:

• Write to RAM command can not access RAM below 0x10000200.

This is due to use of the RAM by the ISP code, see

Section 32–3.2.7.

• Read Memory command: disabled.

• Copy RAM to Flash command: cannot write to Sector 0.

• Go command: disabled.

• Erase sector(s) command: can erase any individual sector except

sector 0 only, or can erase all sectors at once.

• Compare command: disabled

This mode is useful when CRP is required and flash field updates are

needed but all sectors can not be erased. The compare command is

disabled, so in the case of partial flash updates the secondary loader

should implement a checksum mechanism to verify the integrity of the

flash.

CRP2 0x87654321

CRP3 0x43218765

This is similar to CRP1 with the following additions:

• Write to RAM command: disabled.

• Copy RAM to Flash: disabled.

• Erase command: only allows erase of all sectors.

This is similar to CRP2, but ISP entry by pulling P2.10 LOW is

disabled if a valid user code is present in flash sector 0.

This mode effectively disables ISP override using the P2.10 pin. It is

up to the user’s application to provide for flash updates by using IAP

calls or by invoking ISP with UART0.

Caution: If CRP3 is selected, no future factory testing can be

performed on the device.

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Table 570. Code Read Protection hardware/software interaction

CRP option

User Code

Valid

P2.10 pin at

reset

JTAG enabled LPC17xx

enters ISP

partial flash

update in ISP

mode

None

CRP1

CRP2

CRP3

No

X

Yes

No

Yes

No

Yes

NA

Yes

NA

Yes

No

Yes

No

High

Low

x

Yes

No

Yes

No

High

Low

x

Yes

No

Yes

No

High

Low

x

NA

No

Yes

No

Yes

x

NA

If any CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported

or restricted ISP command will be terminated with return code

CODE_READ_PROTECTION_ENABLED.

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7. ISP commands

The following commands are accepted by the ISP command handler. Detailed status

codes are supported for each command. The command handler sends the return code

INVALID_COMMAND when an undefined command is received. Commands and return

codes are in ASCII format.

CMD_SUCCESS is sent by ISP command handler only when received ISP command has

been completely executed and the new ISP command can be given by the host.

Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"

commands.

Table 571. ISP command summary

ISP Command

Unlock

Usage

Described in

Table 32–572

Table 32–573

Table 32–575

Table 32–576

Table 32–577

Table 32–578

U <Unlock Code>

Set Baud Rate

Echo

B <Baud Rate> <stop bit>

A <setting>

Write to RAM

Read Memory

W <start address> <number of bytes>

R <address> <number of bytes>

P <start sector number> <end sector number>

Prepare sector(s) for

write operation

Copy RAM to Flash

Go

C <flash address> <RAM address> <number of bytes> Table 32–579

G <address> <Mode>

Table 32–580

Table 32–581

Table 32–582

Table 32–583

Table 32–585

Table 32–586

Table 32–587

Erase sector(s)

Blank check sector(s)

Read Part ID

E <start sector number> <end sector number>

I <start sector number> <end sector number>

J

Read Boot Code version K

Read serial number

Compare

N

M <address1> <address2> <number of bytes>

7.1 Unlock <Unlock code>

Table 572. ISP Unlock command

Command

Input

U

Unlock code: 23130₁₀

CMD_SUCCESS |

INVALID_CODE |

PARAM_ERROR

Return Code

Description

Example

This command is used to unlock Flash Write, Erase, and Go commands.

"U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands.

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7.2 Set Baud Rate <Baud Rate> <stop bit>

Table 573. ISP Set Baud Rate command

Command

B

Input

Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400

Stop bit: 1 | 2

Return Code

CMD_SUCCESS |

INVALID_BAUD_RATE |

INVALID_STOP_BIT |

PARAM_ERROR

Description

Example

This command is used to change the baud rate. The new baud rate is effective

after the command handler sends the CMD_SUCCESS return code.

"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.

Table 574. Correlation between possible ISP baudrates and CCLK frequency (in MHz)

ISP Baudrate .vs.

CCLK Frequency

9600

19200

38400

57600

115200

230400

10.0000

11.0592

12.2880

14.7456^[1]

15.3600

18.4320

19.6608

24.5760

25.0000

+

[1] ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz

7.3 Echo <setting>

Table 575. ISP Echo command

Command

Input

A

Setting: ON = 1 | OFF = 0

CMD_SUCCESS |

PARAM_ERROR

Return Code

Description

Example

The default setting for echo command is ON. When ON the ISP command handler

sends the received serial data back to the host.

"A 0<CR><LF>" turns echo off.

7.4 Write to RAM <start address> <number of bytes>

The host should send the data only after receiving the CMD_SUCCESS return code. The

host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is

generated by adding raw data (before UU-encoding) bytes and is reset after transmitting

20 UU-encoded lines. The length of any UU-encoded line should not exceed

61 characters (bytes) i.e. it can hold 45 data bytes. When the data fits in less then

20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.

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The ISP command handler compares it with the check-sum of the received bytes. If the

check-sum matches, the ISP command handler responds with "OK<CR><LF>" to

continue further transmission. If the check-sum does not match, the ISP command

handler responds with "RESEND<CR><LF>". In response the host should retransmit the

bytes.

Table 576. ISP Write to RAM command

Command

W

Input

Start Address: RAM address where data bytes are to be written. This address

should be a word boundary.

Number of Bytes: Number of bytes to be written. Count should be a multiple of 4

CMD_SUCCESS |

Return Code

ADDR_ERROR (Address not on word boundary) |

ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not multiple of 4) |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to download data to RAM. Data should be in UU-encoded

format. This command is blocked when code read protection levels CRP2 or

CRP3 are enabled.

"W 268435968 4<CR><LF>" writes 4 bytes of data to address 0x1000 0200.

7.5 Read Memory <address> <no. of bytes>

The data stream is followed by the command success return code. The check-sum is sent

after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data

(before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines. The

length of any UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold

45 data bytes. When the data fits in less then 20 UU-encoded lines then the check-sum is

of actual number of bytes sent. The host should compare it with the checksum of the

received bytes. If the check-sum matches then the host should respond with

"OK<CR><LF>" to continue further transmission. If the check-sum does not match then

the host should respond with "RESEND<CR><LF>". In response the ISP command

handler sends the data again.

Table 577. ISP Read Memory command

Command

R

Input

Start Address: Address from where data bytes are to be read. This address

should be a word boundary.

Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.

CMD_SUCCESS followed by <actual data (UU-encoded)> |

ADDR_ERROR (Address not on word boundary) |

ADDR_NOT_MAPPED |

Return Code

COUNT_ERROR (Byte count is not a multiple of 4) |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to read data from RAM or flash memory. This command is

blocked when any level of code read protection is enabled.

"R 268435968 4<CR><LF>" reads 4 bytes of data from address 0x1000 0200.

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7.6 Prepare sector(s) for write operation <start sector number> <end

sector number>

This command makes flash write/erase operation a two step process.

Table 578. ISP Prepare sector(s) for write operation command

Command

P

Input

Start Sector Number

End Sector Number: Should be greater than or equal to start sector number.

Return Code

CMD_SUCCESS |

BUSY |

INVALID_SECTOR |

PARAM_ERROR

Description

Example

This command must be executed before executing "Copy RAM to Flash" or

"Erase Sector(s)" command. Successful execution of the "Copy RAM to Flash" or

"Erase Sector(s)" command causes relevant sectors to be protected again. To

prepare a single sector use the same "Start" and "End" sector numbers.

"P 0 0<CR><LF>" prepares the flash sector 0.

7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes>

Table 579. ISP Copy command

Command

C

Input

Flash Address(DST): Destination flash address where data bytes are to be

written. The destination address should be a 256 byte boundary.

RAM Address(SRC): Source RAM address from where data bytes are to be read.

Number of Bytes: Number of bytes to be written. Should be 256 | 512 | 1024 |

4096.

Return Code CMD_SUCCESS |

SRC_ADDR_ERROR (Address not on word boundary) |

DST_ADDR_ERROR (Address not on correct boundary) |

SRC_ADDR_NOT_MAPPED |

DST_ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |

SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |

BUSY |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to program the flash memory. The "Prepare Sector(s) for

Write Operation" command should precede this command. The affected sectors are

automatically protected again once the copy command is successfully executed.

This command is blocked when code read protection levels CRP2 or CRP3 are

enabled. When code read protection level CRP1 is enabled, individual sectors

other than sector 0 can be written.

"C 0 268468224 512<CR><LF>" copies 512 bytes from the RAM address

0x1000 8000 to the flash address 0.

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7.8 Go <address> <mode>

Table 580. ISP Go command

Command

G

Input

Address: Flash or RAM address from which the code execution is to be started.

This address should be on a word boundary.

Mode (retained for backward compatibility): T (Execute program in Thumb

Mode) | A (not allowed).

Return Code CMD_SUCCESS |

ADDR_ERROR |

ADDR_NOT_MAPPED |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to execute a program residing in RAM or flash memory. It

may not be possible to return to the ISP command handler once this command is

successfully executed. This command is blocked when any level of code read

protection is enabled.

"G 0 T<CR><LF>" branches to address 0x0000 0000.

When the GO command is used, execution begins at the specified address (assuming it is

an executable address) with the device left as it was configured for the ISP code. This

means that some things are different than they would be for entering user code directly

following a chip reset. Most importantly, the main PLL will be running and connected,

configured to generate a CPU clock with a frequency of approximately 14.7456 MHz.

7.9 Erase sector(s) <start sector number> <end sector number>

Table 581. ISP Erase sector command

Command

E

Input

Start Sector Number

End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |

BUSY |

INVALID_SECTOR |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

CMD_LOCKED |

PARAM_ERROR |

CODE_READ_PROTECTION_ENABLED

Description

Example

This command is used to erase one or more sector(s) of on-chip flash memory. This

command is blocked when code read protection level CRP3 is enabled. When code

read protection level CRP1 is enabled, individual sectors other than sector 0 can be

erased. All sectors can be erased at once in CRP1 and CRP2.

"E 2 3<CR><LF>" erases the flash sectors 2 and 3.

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7.10 Blank check sector(s) <sector number> <end sector number>

Table 582. ISP Blank check sector command

Command

I

Input

Start Sector Number:

End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |

SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location>

<Contents of non blank word location>) |

INVALID_SECTOR |

PARAM_ERROR |

Description

Example

This command is used to blank check one or more sectors of on-chip flash memory.

"I 2 3<CR><LF>" blank checks the flash sectors 2 and 3.

7.11 Read Part Identification number

Table 583. ISP Read Part Identification command

Command

J

Input

None.

Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 32–584

“LPC17xx part identification numbers”).

Description

This command is used to read the part identification number. The part identification

number maps to a feature subset within a device family. This number will not

normally change as a result of technical revisions.

Table 584. LPC17xx part identification numbers

Device

ASCII/dec coding Hex coding

LPC1769

LPC1768

LPC1767

LPC1766

LPC1765

LPC1764

LPC1759

LPC1758

LPC1756

LPC1754

LPC1752

LPC1751

638664503

637615927

637610039

637615923

637613875

637606178

621885239

620838711

620828451

620828450

620761377

620761368

0x2611 3F37

0x2601 3F37

0x2601 2837

0x2601 3F33

0x2601 3733

0x2601 1922

0x2511 3737

0x2501 3F37

0x2501 1723

0x2501 1722

0x2500 1121

0x2500 1118

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7.12 Read Boot Code version number

Table 585. ISP Read Boot Code version number command

Command

K

Input

None

Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.

It is to be interpreted as <byte1(Major)>.<byte0(Minor)>.

Description

This command is used to read the boot code version number.

7.13 Read device serial number

Table 586. ISP Read device serial number command

Command

N

Input

None.

Return Code CMD_SUCCESS followed by the device serial number in 4 decimal ASCII groups,

each representing a 32-bit value.

Description

This command is used to read the device serial number. The serial number may be

used to uniquely identify a single unit among all LPC17xx devices.

7.14 Compare <address1> <address2> <no of bytes>

Table 587. ISP Compare command

Command

M

Input

Address1 (DST): Starting flash or RAM address of data bytes to be compared.

This address should be a word boundary.

Address2 (SRC): Starting flash or RAM address of data bytes to be compared.

This address should be a word boundary.

Number of Bytes: Number of bytes to be compared; should be a multiple of 4.

Return Code CMD_SUCCESS | (Source and destination data are equal)

COMPARE_ERROR | (Followed by the offset of first mismatch)

COUNT_ERROR (Byte count is not a multiple of 4) |

ADDR_ERROR |

ADDR_NOT_MAPPED |

PARAM_ERROR |

Description

Example

This command is used to compare the memory contents at two locations. This

command is blocked when any level of code read protection is enabled.

"M 8192 268435968 4<CR><LF>" compares 4 bytes from the RAM address

0x1000 0200 to the 4 bytes from the flash address 0x2000.

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7.15 ISP Return Codes

Table 588. ISP Return Codes Summary

Return Mnemonic

Code

Description

0

CMD_SUCCESS

Command is executed successfully. Sent by ISP

handler only when command given by the host has

been completely and successfully executed.

1

2

3

4

INVALID_COMMAND

SRC_ADDR_ERROR

DST_ADDR_ERROR

SRC_ADDR_NOT_MAPPED

Invalid command.

Source address is not on word boundary.

Destination address is not on a correct boundary.

Source address is not mapped in the memory map.

Count value is taken into consideration where

applicable.

5

DST_ADDR_NOT_MAPPED

Destination address is not mapped in the memory

map. Count value is taken into consideration where

applicable.

6

7

COUNT_ERROR

Byte count is not multiple of 4 or is not a permitted

value.

INVALID_SECTOR

Sector number is invalid or end sector number is

greater than start sector number.

8

9

SECTOR_NOT_BLANK

Sector is not blank.

SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation

WRITE_OPERATION

COMPARE_ERROR

BUSY

was not executed.

10

11

12

Source and destination data not equal.

Flash programming hardware interface is busy.

PARAM_ERROR

Insufficient number of parameters or invalid

parameter.

13

14

ADDR_ERROR

Address is not on word boundary.

ADDR_NOT_MAPPED

Address is not mapped in the memory map. Count

value is taken in to consideration where applicable.

15

16

17

18

19

CMD_LOCKED

Command is locked.

INVALID_CODE

Unlock code is invalid.

Invalid baud rate setting.

Invalid stop bit setting.

Code read protection enabled.

INVALID_BAUD_RATE

INVALID_STOP_BIT

CODE_READ_PROTECTION_

ENABLED

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8. IAP commands

For in application programming the IAP routine should be called with a word pointer in

register r0 pointing to memory (RAM) containing command code and parameters. Result

of the IAP command is returned in the result table pointed to by register r1. The user can

reuse the command table for result by passing the same pointer in registers r0 and r1. The

parameter table should be big enough to hold all the results in case if number of results

are more than number of parameters. Parameter passing is illustrated in the

Figure 32–137. The number of parameters and results vary according to the IAP

command. The maximum number of parameters is 5, passed to the "Copy RAM to Flash"

command. The maximum number of results is 4, returned by the "Read device serial

number" command. The command handler sends the status code INVALID_COMMAND

when an undefined command is received. The IAP routine resides at location

0x1FFF 1FF0.

The IAP function could be called in the following way using C.

Define the IAP location entry point. Bit 0 of the IAP location is set since the Cortex-M3

uses only Thumb mode.

#define IAP_LOCATION 0x1FFF1FF1

Define data structure or pointers to pass IAP command table and result table to the IAP

function:

unsigned long command[5];

unsigned long result[5];

or

unsigned long

*

command;

result;

command=(unsigned long *) 0x……

result= (unsigned long *) 0x……

Define pointer to function type, which takes two parameters and returns void. Note the IAP

returns the result with the base address of the table residing in R1.

typedef void (*IAP)(unsigned int [],unsigned int[]);

IAP iap_entry;

Setting function pointer:

iap_entry=(IAP) IAP_LOCATION;

Whenever you wish to call IAP you could use the following statement.

iap_entry (command, result);

The IAP call could be simplified further by using the symbol definition file feature

supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP

routine using assembly code.

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As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC

0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers

respectively. Additional parameters are passed on the stack. Up to 4 parameters can be

returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned

indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM

suggested scheme is used for the parameter passing/returning then it might create

problems due to difference in the C compiler implementation from different vendors. The

suggested parameter passing scheme reduces such risk.

The flash memory is not accessible during a write or erase operation. IAP commands,

which results in a flash write/erase operation, use 32 bytes of space in the top portion of

the on-chip RAM for execution. The user program should not be use this space if IAP flash

programming is permitted in the application.

Table 589. IAP Command Summary

IAP Command

Command Code

Described in

Table 32–590

Table 32–591

Table 32–592

Table 32–593

Table 32–594

Table 32–595

Table 32–596

Table 32–597

Table 32–598

Prepare sector(s) for write operation

Copy RAM to Flash

Erase sector(s)

50₁₀

51₁₀

52₁₀

53₁₀

54₁₀

55₁₀

58₁₀

56₁₀

57₁₀

Blank check sector(s)

Read part ID

Read Boot Code version

Read device serial number

Compare

Reinvoke ISP

COMMAND CODE

PARAMETER 1

PARAMETER 2

command

parameter table

ARM REGISTER r0

ARM REGISTER r1

PARAMETER n

STATUS CODE

RESULT 1

command

result table

RESULT 2

RESULT n

Fig 137. IAP parameter passing

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8.1 Prepare sector(s) for write operation

This command makes flash write/erase operation a two step process.

Table 590. IAP Prepare sector(s) for write operation command

Command

Prepare sector(s) for write operation

Command code: 50₁₀

Input

Param0: Start Sector Number

Param1: End Sector Number (should be greater than or equal to start sector

number).

Return Code

CMD_SUCCESS |

BUSY |

INVALID_SECTOR

None

Result

Description

This command must be executed before executing "Copy RAM to Flash" or

"Erase Sector(s)" command. Successful execution of the "Copy RAM to Flash" or

"Erase Sector(s)" command causes relevant sectors to be protected again. To

prepare a single sector use the same "Start" and "End" sector numbers.

8.2 Copy RAM to Flash

Table 591. IAP Copy RAM to Flash command

Command

Copy RAM to Flash

Command code: 51₁₀

Input

Param0(DST): Destination flash address where data bytes are to be written. This

address should be a 256 byte boundary.

Param1(SRC): Source RAM address from which data bytes are to be read. This

address should be a word boundary.

Param2: Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.

Param3: CPU Clock Frequency (CCLK) in kHz.

CMD_SUCCESS |

Return Code

SRC_ADDR_ERROR (Address not a word boundary) |

DST_ADDR_ERROR (Address not on correct boundary) |

SRC_ADDR_NOT_MAPPED |

DST_ADDR_NOT_MAPPED |

COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

BUSY |

Result

None

Description

This command is used to program the flash memory. The affected sectors should

be prepared first by calling "Prepare Sector for Write Operation" command. The

affected sectors are automatically protected again once the copy command is

successfully executed.

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8.3 Erase Sector(s)

Table 592. IAP Erase Sector(s) command

Command

Erase Sector(s)

Input

Command code: 52₁₀

Param0: Start Sector Number

Param1: End Sector Number (should be greater than or equal to start sector

number).

Param2: CPU Clock Frequency (CCLK) in kHz.

Return Code

CMD_SUCCESS |

BUSY |

SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |

INVALID_SECTOR

None

Result

Description

This command is used to erase a sector or multiple sectors of on-chip flash

memory. To erase a single sector use the same "Start" and "End" sector numbers.

8.4 Blank check sector(s)

Table 593. IAP Blank check sector(s) command

Command

Blank check sector(s)

Command code: 53₁₀

Input

Param0: Start Sector Number

Param1: End Sector Number (should be greater than or equal to start sector

number).

Return Code

CMD_SUCCESS |

BUSY |

SECTOR_NOT_BLANK |

INVALID_SECTOR

Result

Result0: Offset of the first non blank word location if the Status Code is

SECTOR_NOT_BLANK.

Result1: Contents of non blank word location.

Description

This command is used to blank check a sector or multiple sectors of on-chip flash

memory. To blank check a single sector use the same "Start" and "End" sector

numbers.

8.5 Read part identification number

Table 594. IAP Read part identification number command

Command

Read part identification number

Command code: 54₁₀

Input

Parameters: None

Return Code

Result

CMD_SUCCESS |

Result0: Part Identification Number.

Description

This command is used to read the part identification number. The value returned

is the hexadecimal version of the part ID. See Table 32–584 “LPC17xx part

identification numbers”.

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8.6 Read Boot Code version number

Table 595. IAP Read Boot Code version number command

Command

Read boot code version number

Command code: 55₁₀

Parameters: None

Input

Return Code

Result

CMD_SUCCESS |

Result0: 2 bytes of boot code version number in ASCII format. It is to be

interpreted as <byte1(Major)>.<byte0(Minor)>

Description

This command is used to read the boot code version number.

8.7 Read device serial number

Table 596. IAP Read device serial number command

Command

Read device serial number

Input

Command code: 58₁₀

Parameters: None

Return Code

Result

CMD_SUCCESS |

Result0: First 32-bit word of Device Identification Number (at the lowest address)

Result1: Second 32-bit word of Device Identification Number

Result2: Third 32-bit word of Device Identification Number

Result3: Fourth 32-bit word of Device Identification Number

Description

This command is used to read the device identification number. The serial number

may be used to uniquely identify a single unit among all LPC17xx devices.

8.8 Compare <address1> <address2> <no of bytes>

Table 597. IAP Compare command

Command

Compare

Input

Command code: 56₁₀

Param0(DST): Starting flash or RAM address of data bytes to be compared. This

address should be a word boundary.

Param1(SRC): Starting flash or RAM address of data bytes to be compared. This

address should be a word boundary.

Param2: Number of bytes to be compared; should be a multiple of 4.

CMD_SUCCESS |

Return Code

COMPARE_ERROR |

COUNT_ERROR (Byte count is not a multiple of 4) |

ADDR_ERROR |

ADDR_NOT_MAPPED

Result

Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.

This command is used to compare the memory contents at two locations.

Description

The result may not be correct when the source or destination includes any

of the first 64 bytes starting from address zero. The first 64 bytes can be

re-mapped to RAM.

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8.9 Re-invoke ISP

Table 598. Re-invoke ISP

Command

Input

Compare

Command code: 57₁₀

Return Code

Result

None

None.

Description

This command is used to invoke the boot loader in ISP mode. It maps boot

vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets

TIMER1 and resets the U0FDR (see Section 14–4.12). This command may be

used when a valid user program is present in the internal flash memory and the

P2.10 pin is not accessible to force the ISP mode. The command does not disable

the PLL hence it is possible to invoke the boot loader when the part is running off

the PLL. In such case the ISP utility should pass the CCLK (crystal or PLL output

depending on the clock source selection Section 4–4.1) frequency after auto-baud

handshake.

Another option is to disable the PLL and select the IRC as the clock source before

making this IAP call. In this case frequency sent by ISP is ignored and IRC and

PLL are used to generate CCLK = 14.748 MHz.

8.10 IAP Status Codes

Table 599. IAP Status Codes Summary

Status Mnemonic

Code

Description

0

1

2

3

4

CMD_SUCCESS

Command is executed successfully.

Invalid command.

INVALID_COMMAND

SRC_ADDR_ERROR

DST_ADDR_ERROR

SRC_ADDR_NOT_MAPPED

Source address is not on a word boundary.

Destination address is not on a correct boundary.

Source address is not mapped in the memory map.

Count value is taken in to consideration where

applicable.

5

6

DST_ADDR_NOT_MAPPED

COUNT_ERROR

Destination address is not mapped in the memory

map. Count value is taken in to consideration where

applicable.

Byte count is not multiple of 4 or is not a permitted

value.

7

8

9

INVALID_SECTOR

Sector number is invalid.

Sector is not blank.

SECTOR_NOT_BLANK

SECTOR_NOT_PREPARED_

FOR_WRITE_OPERATION

Command to prepare sector for write operation was

not executed.

10

11

COMPARE_ERROR

BUSY

Source and destination data is not same.

Flash programming hardware interface is busy.

9. JTAG flash programming interface

Debug tools can write parts of the flash image to the RAM and then execute the IAP call

"Copy RAM to Flash" repeatedly with proper offset.

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10. Flash signature generation

The flash module contains a built-in signature generator. This generator can produce a

128-bit signature from a range of flash memory. A typical usage is to verify the flashed

contents against a calculated signature (e.g. during programming).

The address range for generating a signature must be aligned on flash-word boundaries,

i.e. 128-bit boundaries. Once started, signature generation completes independently.

While signature generation is in progress, the flash memory cannot be accessed for other

purposes, and an attempted read will cause a wait state to be asserted until signature

generation is complete. Code outside of the flash (e.g. internal RAM) can be executed

during signature generation. This can include interrupt services, if the interrupt vector

table is re-mapped to memory other than the flash memory. The code that initiates

signature generation should also be placed outside of the flash memory.

10.1 Register description for signature generation

Table 600. Register overview: FMC (base address 0x2020 0000)

Name

Description

Access

Reset

Value

Address

Reference

FMSSTART

FMSSTOP

FMSW0

Signature start address register

Signature stop-address register

128-bit signature Word 0

R/W

R

0

-

0x4008 4020

0x4008 4024

0x4008 402C

0x4008 4030

0x4008 4034

0x4008 4038

0x4008 4FE0

Table 32–601

Table 32–602

Table 32–603

Table 32–604

Table 32–605

Table 32–606

FMSW1

128-bit signature Word 1

R

-

FMSW2

128-bit signature Word 2

R

-

FMSW3

128-bit signature Word 3

R

-

FMSTAT

Signature generation status register

R

0

Section 32–10.1.3

Section 32–10.1.4

FMSTATCLR

Signature generation status clear register

W

-

0x4008 4FE8

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10.1.1 Signature generation address and control registers

These registers control automatic signature generation. A signature can be generated for

any part of the flash memory contents. The address range to be used for generation is

defined by writing the start address to the signature start address register (FMSSTART)

and the stop address to the signature stop address register (FMSSTOP. The start and

stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the

byte address by 16.

Signature generation is started by setting the SIG_START bit in the FMSSTOP register.

Setting the SIG_START bit is typically combined with the signature stop address in a

single write.

Table 32–601 and Table 32–602 show the bit assignments in the FMSSTART and

FMSSTOP registers respectively.

Table 601. Flash Module Signature Start register (FMSSTART - 0x4008 4020) bit description

Bit

Symbol

Description

Reset Value

31:17

-

Reserved, user software should not write ones to reserved bits. The value read from a NA

reserved bit is not defined.

16:0

START

Signature generation start address (corresponds to AHB byte address bits[20:4]).

0

Table 602. Flash Module Signature Stop register (FMSSTOP - 0x4008 4024) bit description

Bit

Symbol

Value Description

Reserved, user software should not write ones to reserved bits. The value

Reset Value

31:18

-

NA

read from a reserved bit is not defined.

17

SIG_START

Start control bit for signature generation.

Signature generation is stopped

0

1

Initiate signature generation

16:0

STOP

BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).

10.1.2 Signature generation result registers

The signature generation result registers return the flash signature produced by the

embedded signature generator. The 128-bit signature is reflected by the four registers

FMSW0, FMSW1, FMSW2 and FMSW3.

The generated flash signature can be used to verify the flash memory contents. The

generated signature can be compared with an expected signature and thus makes saves

time and code space. The method for generating the signature is described in

Section 32–10.2.

Table 32–606 show bit assignment of the FMSW0 and FMSW1, FMSW2, FMSW3

registers respectively.

Table 603. FMSW0 register bit description (FMSW0, address: 0x2020 002C)

Bit

Symbol

Description

Reset Value

31:0

SW0[31:0]

Word 0 of 128-bit signature (bits 31 to 0).

-

Table 604. FMSW1 register bit description (FMSW1, address: 0x2020 0030)

Bit

Symbol

Description

Reset Value

31:0

SW1[63:32]

Word 1 of 128-bit signature (bits 63 to 32).

-

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Table 605. FMSW2 register bit description (FMSW2, address: 0x2020 0034)

Bit

Symbol

Description

Reset Value

31:0

SW2[95:64]

Word 2 of 128-bit signature (bits 95 to 64).

-

Table 606. FMSW3 register bit description (FMSW3, address: 0x2020 0038)

Bit

Symbol

Description

Reset Value

31:0

SW3[127:96]

Word 3 of 128-bit signature (bits 127 to 96).

-

10.1.3 Flash Module Status register (FMSTAT - 0x0x4008 4FE0)

The read-only FMSTAT register provides a means of determining when signature

generation has completed. Completion of signature generation can be checked by polling

the SIG_DONE bit in FMSTAT. SIG_DONE should be cleared via the FMSTATCLR

register before starting a signature generation operation, otherwise the status might

indicate completion of a previous operation.

Table 607. Flash module Status register (FMSTAT - 0x4008 4FE0) bit description

Bit

Symbol

Description

Reset Value

31:2

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

2

SIG_DONE

-

When 1, a previously started signature generation has completed. See

FMSTATCLR register description for clearing this flag.

0

1:0

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

10.1.4 Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8)

The FMSTATCLR register is used to clear the signature generation completion flag.

Table 608. Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8) bit description

Bit

Symbol

Description

Reset Value

31:2

-

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

2

SIG_DONE_CLR

-

Writing a 1 to this bits clears the signature generation completion flag

(SIG_DONE) in the FMSTAT register.

0

1:0

Reserved, user software should not write ones to reserved bits. The value read NA

from a reserved bit is not defined.

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10.2 Algorithm and procedure for signature generation

Signature generation

A signature can be generated for any part of the flash contents. The address range to be

used for signature generation is defined by writing the start address to the FMSSTART

register, and the stop address to the FMSSTOP register.

The signature generation is started by writing a ‘1’ to FMSSTOP.MISR_START. Starting

the signature generation is typically combined with defining the stop address, which is

done in another field FMSSTOP.FMSSTOP of the same register.

The time that the signature generation takes is proportional to the address range for which

the signature is generated. Reading of the flash memory for signature generation uses a

self-timed read mechanism and does not depend on any configurable timing settings for

the flash. A safe estimation for the duration of the signature generation is:

Duration = int( (60 / tcy) + 3 ) x (FMSSTOP - FMSSTART + 1)

When signature generation is triggered via software, the duration is in AHB clock cycles,

and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled

by software to determine when signature generation is complete.

If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is

the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in

this case.

After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3

registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit

signature reflects flash parity bits and check bit values.

Content verification

The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the

reference signature. The algorithms to derive the reference signature is given in

Figure 32–138.

sign = 0

FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP

{

FOR i = 0 TO 126

nextSign[i] = f_Q[address][i] XOR sign[i+1]

nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR

sign[27] XOR sign[29]

sign = nextSign

}

signature128 = sign

Fig 138. Algorithm for generating a 128 bit signature

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Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace

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User manual

1. Features

• Supports both standard JTAG and ARM Serial Wire Debug modes.

• Direct debug access to all memories, registers, and peripherals.

• No target resources are required for the debugging session.

• Trace port provides CPU instruction trace capability. Output can be via a 4-bit trace

data port, or Serial Wire Viewer.

• Eight Breakpoints. Six instruction breakpoints that can also be used to remap

instruction addresses for code patches. Two data comparators that can be used to

remap addresses for patches to literal values.

• Four data Watchpoints that can also be used as trace triggers.

• Instrumentation Trace Macrocell allows additional software controlled trace.

2. Introduction

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watchpoints.

3. Description

Debugging with the LPC17xx defaults to JTAG. Once in the JTAG debug mode, the debug

tool can switch to Serial Wire Debug mode.

Trace can be done using either a 4-bit parallel interface or the Serial Wire Output. When

the Serial Wire Output is used, less data can be traced, but it uses no application related

pins. Parallel trace has a greater bandwidth, but uses 5 functional pins that may be

needed in the application. Note that the trace function available for the Cortex-M3 is

functionally very different than the trace that was available for previous ARM7 based

devices, using only 5 pins instead of 10.

4. Pin Description

The tables below indicate the various pin functions related to debug and trace. Some of

these functions share pins with other functions which therefore may not be used at the

same time. Use of the JTAG port excludes use of Serial Wire Debug and Serial Wire

Output. Use of the parallel trace requires 5 pins that may be part of the user application,

limiting debug possibilities for those features. Trace using the Serial Wire Output does not

have this limitation, but has a limited bandwidth.

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Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace

Table 609. JTAG pin description

Pin Name

Type

Description

TCK

Input

JTAG Test Clock. This pin is the clock for debug logic when in the

JTAG debug mode.

TMS

Input

JTAG Test Mode Select. The TMS pin selects the next state in the

TAP state machine.

TDI

JTAG Test Data In. This is the serial data input for the shift register.

TDO

Output JTAG Test Data Output. This is the serial data output from the shift

register. Data is shifted out of the device on the negative edge of the

TCK signal.

TRST

RTCK

Input

JTAG Test Reset. The TRST pin can be used to reset the test logic

within the debug logic.

Output JTAG Returned Test Clock. This is an extra signal added to the

JTAG port, and is included for backward pin compatibility with

LPC23xx series devices that share the same pinout as this device.

RTCK is not normally used with the Cortex-M3.

For designs based on ARM7TDMI-S processor core, this signal

could be used by external JTAG host interface logic to maintain

synchronization with targets having a slow or varying clock

frequency. For details refer to "Multi-ICE System Design

considerations Application Note 72 (ARM DAI 0072A)".

Table 610. Serial Wire Debug pin description

Pin Name

Type

Description

SWDCLK

Input

Serial Wire Clock. This pin is the clock for debug logic when in the

Serial Wire Debug mode.

SWDIO

SWO

Input / Serial wire debug data input/output. The SWDIO pin is used by an

Output external debug tool to communicate with and control the Cortex-M3

CPU.

Output Serial Wire Output. The SWO pin optionally provides data from the

ITM and/or the ETM for an external debug tool to evaluate.

Table 611. Parallel Trace pin description

Pin Name

Type

Description

TRACECLK

Input

Trace Clock. This pin provides the sample clock for trace data on

the TRACEDATA pins when tracing is enabled by an external debug

tool.

TRACEDATA[3:0] Output Trace Data bits 3 to 0. These pins provide ETM trace data when

tracing is enabled by an external debug tool. The debug tool can

then interpret the compressed information and make it available to

the user.

5. Debug Notes

Important: The user should be aware of certain limitations during debugging. The most

important is that, due to limitations of the Cortex-M3 integration, the LPC17xx cannot

wake up in the usual manner from Deep Sleep and Power-down modes. It is

recommended not to use these modes during debug.

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Another issue is that debug mode changes the way in which reduced power modes are

handled by the Cortex-M3 CPU. This causes power modes at the device level to be

different from normal modes operation. These differences mean that power

measurements should not be made while debugging, the results will be higher than during

normal operation in an application.

During a debugging session, the System Tick Timer and the Repetitive Interrupt Timers

are automatically stopped whenever the CPU is stopped. Other peripherals are not

affected. If the Repetitive Interrupt Timer is configured such that its PCLK rate is lower

than the CPU clock rate, the RIT may not increment predictably during some debug

operations, such as single stepping.

Debugging is disabled if code read protection is enabled.

6. Debug memory re-mapping

Following chip reset, a portion of the Boot ROM is mapped to address 0 so that it will be

automatically executed. The Boot ROM switches the map to point to Flash memory prior

to user code being executed. In this way a user normally does not need to know that this

re-mapping occurs.

However, when a debugger halts CPU execution immediately following reset, the Boot

ROM is still mapped to address 0 and can cause confusion. Ideally, the debugger should

correct the mapping automatically in this case, so that a user does not need to deal with it.

6.1 Memory Mapping Control register (MEMMAP - 0x400F C040)

The MEMMAP register allows switch the mapping of the bottom of memory, including

default reset and interrupt vectors, between the Boot ROM and the bottom of on-chip

Flash memory.

Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description

Bit

Symbol Value Description

Reset

value

0

MAP

Memory map control.

0

1

Boot mode. A portion of the Boot ROM is mapped to address 0.

User mode. The on-chip Flash memory is mapped to address 0.

Reserved. The value read from a reserved bit is not defined.

31:1

-

NA

7. JTAG TAP Identification

The JTAG TAP controller contains device ID that can be used by debugging software to

identify the general type of device. More detailed device information is available through

ISP/IAP commands (see Section 32–7 and Section 32–8). For the LPC17xx family, this ID

value is 0x4BA0 0477.

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Chapter 34: Appendix: Cortex-M3 User Guide

Rev. 01 — 4 January 2010

User manual

1. ARM Cortex-M3 User Guide: Introduction

The material in this appendix is provided by ARM Limited for inclusion in the User

Manuals of devices containing the Cortex-M3 CPU. Minimal changes have been

made to reflect implementation options and other distinctions that apply

specifically to LPC17xx devices.

1.1 About the processor and core peripherals

The Cortex-M3 processor is a high performance 32-bit processor designed for the

microcontroller market. It offers significant benefits to developers, including:

• outstanding processing performance combined with fast interrupt handling

• enhanced system debug with extensive breakpoint and trace capabilities

• efficient processor core, system and memories

• ultra-low power consumption with integrated sleep modes

• platform security, with optional integrated memory protection unit (MPU).

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The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage

pipeline Harvard architecture, making it ideal for demanding embedded applications. The

processor delivers exceptional power efficiency through an efficient instruction set and

extensively optimized design, providing high-end processing hardware including

single-cycle 32x32 multiplication and dedicated hardware division.

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Chapter 34: Appendix: Cortex-M3 User Guide

To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements

tightly-coupled system components that reduce processor area while significantly

improving interrupt handling and system debug capabilities. The Cortex-M3 processor

implements a version of the Thumb instruction set, ensuring high code density and

reduced program memory requirements. The Cortex-M3 instruction set provides the

exceptional performance expected of a modern 32-bit architecture, with the high code

density of 8-bit and 16-bit microcontrollers.

The Cortex-M3 processor closely integrates a configurable nested interrupt controller

(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a

non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight

integration of the processor core and NVIC provides fast execution of interrupt service

routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the

hardware stacking of registers, and the ability to suspend load-multiple and store-multiple

operations. Interrupt handlers do not require any assembler stubs, removing any code

overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead

when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to be rapidly powered down.

LPC17xx devices support additional reduced power modes, see Section 4–8 “Power

control” for details.

1.1.1 System level interface

The Cortex-M3 processor provides multiple interfaces using AMBA technology to provide

high speed, low latency memory accesses. It supports unaligned data accesses and

implements atomic bit manipulation that enables faster peripheral controls, system

spinlocks and thread-safe Boolean data handling.

The Cortex-M3 processor has an optional memory protection unit (MPU) that provides

fine grain memory control, enabling applications to implement security privilege levels,

separating code, data and stack on a task-by-task basis. Such requirements are

becoming critical in many embedded applications such as automotive. The MPU is

included in LPC17xx devices.

1.1.2 Integrated configurable debug

The Cortex-M3 processor implements a complete hardware debug solution. This provides

high system visibility of the processor and memory through either a traditional JTAG port

or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small

package devices. The MCU vendor determines the debug feature configuration and

therefore this can differ across different devices and families.

For system trace the processor integrates an Instrumentation Trace Macrocell (ITM)

alongside data watchpoints and a profiling unit. To enable simple and cost-effective

profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a

stream of software-generated messages, data trace, and profiling information through a

single pin.

The optional Embedded Trace Macrocell (ETM) delivers unrivalled instruction trace

capture in an area far smaller than traditional trace units, enabling many low cost MCUs to

implement full instruction trace for the first time.

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LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include

the Embedded Trace Macrocell. See Section 33–1 for additional information.

1.1.3 Cortex-M3 processor features and benefits summary

• tight integration of system peripherals reduces area and development costs

• Thumb instruction set combines high code density with 32-bit performance

• code-patch ability for ROM system updates

• power control optimization of system components

• integrated sleep modes for low power consumption

• fast code execution permits slower processor clock or increases sleep mode time

• hardware division and fast multiplier

• deterministic, high-performance interrupt handling for time-critical applications

• optional memory protection unit (MPU) for safety-critical applications

• extensive debug and trace capabilities:

– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for

debugging and tracing.

1.1.4 Cortex-M3 core peripherals

These are:

• Nested Vectored Interrupt Controller

The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt

controller that supports low latency interrupt processing.

• System control block

The System control block (SCB) is the programmers model interface to the

processor. It provides system implementation information and system control,

including configuration, control, and reporting of system exceptions.

• System timer

The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time

Operating System (RTOS) tick timer or as a simple counter.

• Memory protection unit

The Memory protection unit (MPU) improves system reliability by defining the

memory attributes for different memory regions. It provides up to eight different

regions, and an optional predefined background region.

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2. ARM Cortex-M3 User Guide: Instruction Set

2.1 Instruction set summary

The processor implements a version of the Thumb instruction set. Table 34–613 lists the

supported instructions.

Note

In Table 34–613:

• angle brackets, <>, enclose alternative forms of the operand

• braces, {}, enclose optional operands

• the Operands column is not exhaustive

•

Op2 is a flexible second operand that can be either a register or a constant

• most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions.

Table 613. Cortex-M3 instructions

Mnemonic

ADC, ADCS

ADD, ADDS

ADD, ADDW

ADR

Operands

{Rd,} Rn, Op2

{Rd,} Rn, #imm12

Rd, label

{Rd,} Rn, Op2

Rd, Rm, <Rs|#n>

label

Brief description

Add with Carry

Flags

Page

N,Z,C,V Section 34–2.5.1

Add

Load PC-relative address

Logical AND

-

Section 34–2.4.1

Section 34–2.5.2

Section 34–2.5.3

Section 34–2.9.1

Section 34–2.8.1

Section 34–2.5.2

Section 34–2.10.1

Section 34–2.9.1

Section 34–2.9.2

Section 34–2.4.9

Section 34–2.5.4

AND, ANDS

ASR, ASRS

B

N,Z,C

Arithmetic Shift Right

Branch

N,Z,C

-

BFC

Rd, #lsb, #width

Rd, Rn, #lsb, #width

{Rd,} Rn, Op2

#imm

Bit Field Clear

-

BFI

Bit Field Insert

-

BIC, BICS

BKPT

Bit Clear

N,Z,C

Breakpoint

-

BL

label

Branch with Link

BLX

Rm

Branch indirect with Link

Branch indirect

BX

Rm

CBNZ

Rn, label

-

Compare and Branch if Non Zero

Compare and Branch if Zero

Clear Exclusive

CBZ

CLREX

CLZ

Rd, Rm

Count leading zeros

Compare Negative

Compare

CMN, CMNS

CMP, CMPS

CPSID

Rn, Op2

N,Z,C,V Section 34–2.5.5

Rn, Op2

iflags

Change Processor State, Disable Interrupts

Change Processor State, Enable Interrupts

Data Memory Barrier

Data Synchronization Barrier

Exclusive OR

-

Section 34–2.10.2

Section 34–2.10.3

Section 34–2.10.4

Section 34–2.5.2

CPSIE

iflags

-

DMB

-

DSB

-

EOR, EORS

{Rd,} Rn, Op2

N,Z,C

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Table 613. Cortex-M3 instructions …continued

Mnemonic

ISB

Operands

-

Brief description

Flags

Page

Instruction Synchronization Barrier

If-Then condition block

-

Section 34–2.10.5

Section 34–2.9.3

Section 34–2.4.6

Section 34–2.4

Section 34–2.4.2

Section 34–2.4.8

Section 34–2.4

Section 34–2.5.3

Section 34–2.6.1

Section 34–2.5.6

Section 34–2.5.7

Section 34–2.5.6

Section 34–2.10.6

IT

-

LDM

Rn{!}, reglist

Rt, [Rn, #offset]

Load Multiple registers, increment after

Load Multiple registers, decrement before

Load Multiple registers, increment after

Load Register with word

-

LDMDB, LDMEA

LDMFD, LDMIA

LDR

-

LDRB, LDRBT

LDRD

Load Register with byte

-

Rt, Rt2, [Rn, #offset] Load Register with two bytes

-

LDREX

Rt, [Rn, #offset]

Rt, [Rn]

Load Register Exclusive

Load Register Exclusive with byte

Load Register Exclusive with halfword

Load Register with halfword

Load Register with signed byte

Load Register with signed halfword

Load Register with word

Logical Shift Left

-

LDREXB

LDREXH

LDRH, LDRHT

LDRSB, LDRSBT

LDRSH, LDRSHT

LDRT

-

Rt, [Rn]

-

Rt, [Rn, #offset]

Rd, Rm, <Rs|#n>

Rd, Rn, Rm, Ra

Rd, Op2

-

LSL, LSLS

LSR, LSRS

MLA

N,Z,C

Logical Shift Right

N,Z,C

Multiply with Accumulate, 32-bit result

Multiply and Subtract, 32-bit result

Move

-

MLS

-

MOV, MOVS

MOVT

N,Z,C

Rd, #imm16

Rd, spec_reg

spec_reg, Rm

{Rd,} Rn, Rm

Rd, Op2

Move Top

-

MOVW, MOV

MRS

Move 16-bit constant

N,Z,C

-

Move from special register to general register

Move from general register to special register

Multiply, 32-bit result

MSR

N,Z,C,V Section 34–2.10.7

MUL, MULS

MVN, MVNS

NOP

N,Z

Section 34–2.6.1

Section 34–2.5.6

Section 34–2.10.8

Section 34–2.5.2

Section 34–2.4.7

Section 34–2.5.8

Move NOT

N,Z,C

-

No Operation

-

ORN, ORNS

ORR, ORRS

POP

{Rd,} Rn, Op2

reglist

Logical OR NOT

N,Z,C

Logical OR

N,Z,C

Pop registers from stack

Push registers onto stack

Reverse Bits

-

PUSH

reglist

RBIT

Rd, Rn

REV

Rd, Rn

Reverse byte order in a word

Reverse byte order in each halfword

REV16

Rd, Rn

REVSH

Rd, Rn

Reverse byte order in bottom halfword and sign

extend

ROR, RORS

RRX, RRXS

RSB, RSBS

SBC, SBCS

SBFX

Rd, Rm, <Rs|#n>

Rd, Rm

Rotate Right

N,Z,C

Section 34–2.5.3

Rotate Right with Extend

Reverse Subtract

{Rd,} Rn, Op2

Rd, Rn, #lsb, #width

N,Z,C,V Section 34–2.5.1

Subtract with Carry

Signed Bit Field Extract

-

Section 34–2.8.2

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Table 613. Cortex-M3 instructions …continued

Mnemonic

SDIV

Operands

{Rd,} Rn, Rm

-

Brief description

Signed Divide

Send Event

Flags

Page

-

Section 34–2.6.3

Section 34–2.10.9

Section 34–2.6.2

SEV

SMLAL

RdLo, RdHi, Rn, Rm

Signed Multiply with Accumulate (32 x 32 + 64),

64-bit result

SMULL

RdLo, RdHi, Rn, Rm

Signed Multiply (32 x 32), 64-bit result

-

Q

-

Section 34–2.6.2

Section 34–2.7.1

Section 34–2.4.6

Section 34–2.4

Section 34–2.4.2

Section 34–2.4.8

Section 34–2.4

SSAT

Rd, #n, Rm {,shift #s} Signed Saturate

STM

Rn{!}, reglist

Rt, [Rn, #offset]

Store Multiple registers, increment after

STMDB, STMEA

STMFD, STMIA

STR

Store Multiple registers, decrement before

Store Multiple registers, increment after

Store Register word

-

STRB, STRBT

STRD

Store Register byte

-

Rt, Rt2, [Rn, #offset] Store Register two words

-

STREX

Rd, Rt, [Rn, #offset]

Rd, Rt, [Rn]

Store Register Exclusive

Store Register Exclusive byte

Store Register Exclusive halfword

Store Register halfword

Store Register word

Subtract

-

STREXB

-

STREXH

Rd, Rt, [Rn]

-

STRH, STRHT

STRT

Rt, [Rn, #offset]

{Rd,} Rn, Op2

{Rd,} Rn, #imm12

#imm

-

SUB, SUBS

SUB, SUBW

SVC

N,Z,C,V Section 34–2.5.1

Subtract

Supervisor Call

-

Section 34–2.10.1

0

SXTB

SXTH

TBB

{Rd,} Rm {,ROR #n}

[Rn, Rm]

Sign extend a byte

Sign extend a halfword

Table Branch Byte

Table Branch Halfword

Test Equivalence

Test

-

Section 34–2.8.3

Section 34–2.9.4

Section 34–2.5.9

Section 34–2.8.2

Section 34–2.6.3

Section 34–2.6.2

-

TBH

[Rn, Rm, LSL #1]

Rn, Op2

-

TEQ

N,Z,C

TST

Rn, Op2

N,Z,C

UBFX

UDIV

UMLAL

Rd, Rn, #lsb, #width

{Rd,} Rn, Rm

Unsigned Bit Field Extract

Unsigned Divide

-

RdLo, RdHi, Rn, Rm

Unsigned Multiply with Accumulate

(32 x 32 + 64), 64-bit result

UMULL

USAT

UXTB

UXTH

WFE

RdLo, RdHi, Rn, Rm

Unsigned Multiply (32 x 32), 64-bit result

-

Section 34–2.6.2

Section 34–2.7.1

Section 34–2.8.3

Rd, #n, Rm {,shift #s} Unsigned Saturate

Q

-

{Rd,} Rm {,ROR #n}

Zero extend a byte

Zero extend a halfword

Wait For Event

{Rd,} Rm {,ROR #n}

-

Section 34–2.10.1

1

WFI

-

Wait For Interrupt

-

Section 34–2.10.1

2

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2.2 Intrinsic functions

ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic

functions that can generate these instructions, provided by the CMIS and that might be

provided by a C compiler. If a C compiler does not support an appropriate intrinsic

function, you might have to use inline assembler to access some instructions.

The CMSIS provides the following intrinsic functions to generate instructions that ANSI

cannot directly access:

Table 614. CMSIS intrinsic functions to generate some Cortex-M3 instructions

Instruction

CMSIS intrinsic function

void __enable_irq(void)

void __disable_irq(void)

void __enable_fault_irq(void)

void __disable_fault_irq(void)

void __ISB(void)

CPSIE

CPSID

CPSIE

CPSID

ISB

I

F

DSB

void __DSB(void)

DMB

void __DMB(void)

REV

uint32_t __REV(uint32_t int value)

uint32_t __REV16(uint32_t int value)

uint32_t __REVSH(uint32_t int value)

uint32_t __RBIT(uint32_t int value)

void __SEV(void)

REV16

REVSH

RBIT

SEV

WFE

void __WFE(void)

WFI

void __WFI(void)

The CMSIS also provides a number of functions for accessing the special registers using

MRS and MSR instructions:

Table 615. CMSIS intrinsic functions to access the special registers

Special register Access

CMSIS function

PRIMASK

FAULTMASK

BASEPRI

CONTROL

MSP

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

uint32_t __get_PRIMASK (void)

void __set_PRIMASK (uint32_t value)

uint32_t __get_FAULTMASK (void)

void __set_FAULTMASK (uint32_t value)

uint32_t __get_BASEPRI (void)

void __set_BASEPRI (uint32_t value)

uint32_t __get_CONTROL (void)

void __set_CONTROL (uint32_t value)

uint32_t __get_MSP (void)

void __set_MSP (uint32_t TopOfMainStack)

uint32_t __get_PSP (void)

PSP

void __set_PSP (uint32_t TopOfProcStack)

2.3 About the instruction descriptions

The following sections give more information about using the instructions:

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• Section 34–2.3.1 “Operands”

• Section 34–2.3.2 “Restrictions when using PC or SP”

• Section 34–2.3.3 “Flexible second operand”

• Section 34–2.3.4 “Shift Operations”

• Section 34–2.3.5 “Address alignment”

• Section 34–2.3.6 “PC-relative expressions”

• Section 34–2.3.7 “Conditional execution”

• Section 34–2.3.8 “Instruction width selection”.

2.3.1 Operands

An instruction operand can be an ARM register, a constant, or another instruction-specific

parameter. Instructions act on the operands and often store the result in a destination

register. When there is a destination register in the instruction, it is usually specified before

the operands.

Operands in some instructions are flexible in that they can either be a register or a

constant. See Section 34–2.3.3.

2.3.2 Restrictions when using PC or SP

Many instructions have restrictions on whether you can use the Program Counter (PC)

or Stack Pointer (SP) for the operands or destination register. See instruction

descriptions for more information.

Remark: Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction

must be 1 for correct execution, because this bit indicates the required instruction set, and

the Cortex-M3 processor only supports Thumb instructions.

2.3.3 Flexible second operand

Many general data processing instructions have a flexible second operand. This is shown

as Operand2 in the descriptions of the syntax of each instruction.

Operand2 can be a:

• Section 34–2.3.3.1 “Constant”

• Section 34–2.3.3.2 “Register with optional shift”

2.3.3.1 Constant

You specify an Operand2 constant in the form:

#constant

where constant can be:

• any constant that can be produced by shifting an 8-bit value left by any number of bits

within a 32-bit word

• any constant of the form 0x00XY00XY

• any constant of the form 0xXY00XY00

• any constant of the form 0xXYXYXYXY

.

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Remark: In the constants shown above,

X and Y are hexadecimal digits.

In addition, in a small number of instructions, constant can take a wider range of values.

These are described in the individual instruction descriptions.

When an Operand2 constant is used with the instructions MOVS

, MVNS, ANDS, ORRS, ORNS, EORS,

BICS

,

TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater

than 255 and can be produced by shifting an 8-bit value. These instructions do not affect

the carry flag if Operand2 is any other constant.

Instruction substitution: Your assembler might be able to produce an equivalent

instruction in cases where you specify a constant that is not permitted. For example, an

assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent

instruction CMN Rd, #0x2

.

2.3.3.2 Register with optional shift

You specify an Operand2 register in the form:

Rm {, shift}

where:

Rm is the register holding the data for the second operand.

shift is an optional shift to be applied to Rm. It can be one of:

ASR#n: arithmetic shift right n bits, 1 ≤ n ≤ 32.

LSL#n: logical shift left n bits, 1 ≤ n ≤ 31.

LSR#n: logical shift right n bits, 1 ≤ n ≤ 32.

ROR#n: rotate right n bits, 1 ≤ n ≤ 31.

RRX: rotate right one bit, with extend.

—: if omitted, no shift occurs, equivalent to LSL#0.

If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.

If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value

is used by the instruction. However, the contents in the register Rm remains unchanged.

Specifying a register with shift also updates the carry flag when used with certain

instructions. For information on the shift operations and how they affect the carry flag, see

Section 34–2.3.4 “Shift Operations”

2.3.4 Shift Operations

Register shift operations move the bits in a register left or right by a specified number of

bits, the shift length. Register shift can be performed:

• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a

destination register

• during the calculation of Operand2 by the instructions that specify the second

operand as a register with shift, see Section 34–2.3.3. The result is used by the

instruction.

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The permitted shift lengths depend on the shift type and the instruction, see the individual

instruction description or Section 34–2.3.3. If the shift length is 0, no shift occurs. Register

shift operations update the carry flag except when the specified shift length is 0. The

following sub-sections describe the various shift operations and how they affect the carry

flag. In these descriptions, Rm is the register containing the value to be shifted, and n is

the shift length.

2.3.4.1 ASR

Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right

by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of

the register into the left-hand n bits of the result. See Figure 34–140.

You can use the ASR #n operation to divide the value in the register Rm by 2ⁿ, with the

result being rounded towards negative-infinity.

When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions

MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit

shifted out, bit[n-1], of the register Rm.

Note

• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.

• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of

Rm.

&DUU\

)ODJ

ꢂꢃ

ꢈ ꢇ ꢂ ꢆ

ꢃ ꢄ

ꢅꢅꢅ

Fig 140. ASR #3

2.3.4.2 LSR

Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by

n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the

result to 0. See Figure 34–141.

You can use the LSR #n operation to divide the value in the register Rm by 2ⁿ, if the value

is regarded as an unsigned integer.

When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions

MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit

shifted out, bit[n-1], of the register Rm.

Note

• If n is 32 or more, then all the bits in the result are cleared to 0.

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• If n is 33 or more and the carry flag is updated, it is updated to 0.

&DUU\

)ODJ

ꢄ

ꢂꢃ

ꢈ ꢇ ꢂ ꢆ

ꢃ ꢄ

ꢅꢅꢅ

Fig 141. LSR#3

2.3.4.3 LSL

Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n

places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the

result to 0. See Figure 34–142.

You can use he LSL #n operation to multiply the value in the register Rm by 2ⁿ, if the value

is regarded as an unsigned integer or a two’s complement signed integer. Overflow can

occur without warning.

When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with

the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated

to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect the

carry flag when used with LSL #0.

Note

• If n is 32 or more, then all the bits in the result are cleared to 0.

• If n is 33 or more and the carry flag is updated, it is updated to 0.

ꢄ

ꢂꢃ

ꢈ

ꢇ

ꢂ

ꢆ

ꢃ ꢄ

&DUU\

)ODJ

ꢅꢅꢅ

Fig 142. LSL#3

2.3.4.4 ROR

Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n

places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the

register into the left-hand n bits of the result. See Figure 34–143.

When the instruction is RORS or when ROR #n is used in Operand2 with the instructions

MOVS

,

MVNS

,

ANDS

,

ORRS

,

ORNS

,

EORS

,

BICS

,

TEQ or TST, the carry flag is updated to the last bit

rotation, bit[n-1], of the register Rm.

Note

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• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag

is updated, it is updated to bit[31] of Rm.

•

ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.

&DUU\

)ODJ

ꢂꢃ

ꢈ

ꢇ

ꢂ

ꢆ

ꢃ ꢄ

ꢅꢅꢅ

Fig 143. ROR#3

2.3.4.5 RRX

Rotate right with extend moves the bits of the register Rm to the right by one bit. And it

copies the carry flag into bit[31] of the result. See Figure 34–144.

When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS

,

MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register

Rm.

&DUU\

)ODJ

ꢂꢃ ꢂꢄ

ꢄ

ꢃ

ꢅꢅꢅ

Fig 144. RRX

2.3.5 Address alignment

An aligned access is an operation where a word-aligned address is used for a word, dual

word, or multiple word access, or where a halfword-aligned address is used for a halfword

access. Byte accesses are always aligned.

The Cortex-M3 processor supports unaligned access only for the following instructions:

•

LDR

,

LDRT

LDRHT

LDRSHT

LDRH

,

LDRSH

,

STR

,

STRT

STRHT

STRH

,

All other load and store instructions generate a usage fault exception if they perform an

unaligned access, and therefore their accesses must be address aligned. For more

information about usage faults see Section 34–3.4 “Fault handling”.

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Unaligned accesses are usually slower than aligned accesses. In addition, some memory

regions might not support unaligned accesses. Therefore, ARM recommends that

programmers ensure that accesses are aligned. To avoid accidental generation of

unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register

to trap all unaligned accesses, see Section 34–4.3.8 “Configuration and Control Register”.

2.3.6 PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction

or literal data. It is represented in the instruction as the PC value plus or minus a numeric

offset. The assembler calculates the required offset from the label and the address of the

current instruction. If the offset is too big, the assembler produces an error.

Note

• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current

instruction plus 4 bytes.

• For all other instructions that use labels, the value of the PC is the address of the

current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it

word-aligned.

• Your assembler might permit other syntaxes for PC-relative expressions, such as a

label plus or minus a number, or an expression of the form [PC, #number]

.

2.3.7 Conditional execution

Most data processing instructions can optionally update the condition flags in the

Application Program Status Register (APSR) according to the result of the operation,

see Section 34–3.1.3.5 “Program Status Register”. Some instructions update all flags, and

some only update a subset. If a flag is not updated, the original value is preserved. See

the instruction descriptions for the flags they affect.

You can execute an instruction conditionally, based on the condition flags set in another

instruction, either:

• immediately after the instruction that updated the flags

• after any number of intervening instructions that have not updated the flags.

Conditional execution is available by using conditional branches or by adding condition

code suffixes to instructions. See Table 34–616 for a list of the suffixes to add to

instructions to make them conditional instructions. The condition code suffix enables the

processor to test a condition based on the flags. If the condition test of a conditional

instruction fails, the instruction:

• does not execute

• does not write any value to its destination register

• does not affect any of the flags

• does not generate any exception.

Conditional instructions, except for conditional branches, must be inside an If-Then

instruction block. See Section 34–2.9.3 for more information and restrictions when using

the IT instruction. Depending on the vendor, the assembler might automatically insert an

IT instruction if you have conditional instructions outside the IT block.

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Use the CBZ and CBNZ instructions to compare the value of a register against zero and

branch on the result.

This section describes:

• Section 34–2.3.7.1 “The condition flags”

• Section 34–2.3.7.2 “Condition code suffixes”.

2.3.7.1 The condition flags

The APSR contains the following condition flags:

N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.

Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise.

C — Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.

V — Set to 1 when the operation caused overflow, cleared to 0 otherwise.

For more information about the APSR see Section 34–3.1.3.5 “Program Status Register”.

A carry occurs:

• if the result of an addition is greater than or equal to 2³²

• if the result of a subtraction is positive or zero

• as the result of an inline barrel shifter operation in a move or logical instruction.

Overflow occurs if the result of an add, subtract, or compare is greater than or equal to

2³¹, or less than –2³¹.

Remark: Most instructions update the status flags only if the S suffix is specified. See the

instruction descriptions for more information.

2.3.7.2 Condition code suffixes

The instructions that can be conditional have an optional condition code, shown in syntax

descriptions as {cond}. Conditional execution requires a preceding IT instruction. An

instruction with a condition code is only executed if the condition code flags in the APSR

meet the specified condition. Table 34–616 shows the condition codes to use.

You can use conditional execution with the IT instruction to reduce the number of branch

instructions in code.

Table 34–616 also shows the relationship between condition code suffixes and the N, Z,

C, and V flags.

Table 616. Condition code suffixes

Suffix

EQ

Flags

Z = 1

Z = 0

C = 1

C = 0

N = 1

Meaning

Equal

NE

Not equal

CS or HS

CC or LO

MI

Higher or same, unsigned ≥

Lower, unsigned <

Negative

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Table 616. Condition code suffixes

Suffix

PL

Flags

Meaning

N = 0

Positive or zero

VS

V = 1

Overflow

VC

V = 0

No overflow

HI

C = 1 and Z = 0

C = 0 or Z = 1

N = V

Higher, unsigned >

Lower or same, unsigned ≤

Greater than or equal, signed ≥

Less than, signed <

Greater than, signed >

LS

GE

LT

N != V

GT

Z = 0 and N = V

LE

Z = 1 and N != V Less than or equal, signed ≤

AL

Can have any

value

Always. This is the default when no suffix is specified.

Section 34– shows the use of a conditional instruction to find the absolute value of a

number. R0 = ABS(R1).

Section 34– shows the use of conditional instructions to update the value of R4 if the

signed values R0 is greater than R1 and R2 is greater than R3.

Example: Absolute value:

MOVS

R0, R1

IT instruction for the negative condition

If negative, R0 -R1

; R0 = R1, setting flags

IT

MI

;

RSBMI

R0, R1, #0

=

Example: Compare and update value:

CMP

R0, R1

; Compare R0 and R1,

setting flags

ITT

CMPGT

MOVGT

GT

R2, R3

R4, R5

;

IT instruction for the two GT conditions

If 'greater than', compare R2 and R3, setting flags

If still 'greater than', do R4

= R5

2.3.8 Instruction width selection

There are many instructions that can generate either a 16-bit encoding or a 32-bit

encoding depending on the operands and destination register specified. For some of

these instructions, you can force a specific instruction size by using an instruction width

suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit

instruction encoding.

If you specify an instruction width suffix and the assembler cannot generate an instruction

encoding of the requested width, it generates an error.

Remark: In some cases it might be necessary to specify the .W suffix, for example if the

operand is the label of an instruction or literal data, as in the case of branch instructions.

This is because the assembler might not automatically generate the right size encoding.

To use an instruction width suffix, place it immediately after the instruction mnemonic and

condition code, if any. Section 34–2.3.8.1 shows instructions with the instruction width

suffix.

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2.3.8.1 Example: Instruction width selection

BCS.W label

; creates a 32-bit instruction even for a short branch

ADDS.W R0, R0, R1

;

creates

operation can be done by

a

32-bit instruction even though the same

16-bit instruction

a

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2.4 Memory access instructions

Table 34–617 shows the memory access instructions:

Table 617. Memory access instructions

Mnemonic

ADR

Brief description

See

Load PC-relative address

Clear Exclusive

Section 34–2.4.1

Section 34–2.4.9

Section 34–2.4.6

Section 34–2.4.2

Section 34–2.4.3

CLREX

LDM{mode}

LDR{type}

LDR{type}T

LDR

Load Multiple registers

Load Register using immediate offset

Load Register using register offset

Load Register with unprivileged access Section 34–2.4.4

Load Register using PC-relative address Section 34–2.4.5

LDREX{type}

POP

Load Register Exclusive

Section 34–2.4.8

Section 34–2.4.7

Section 34–2.4.6

Section 34–2.4.2

Section 34–2.4.3

Pop registers from stack

PUSH

Push registers onto stack

STM{mode}

STR{type}

STR{type}T

STREX{type}

Store Multiple registers

Store Register using immediate offset

Store Register using register offset

Store Register with unprivileged access Section 34–2.4.4

Store Register Exclusive Section 34–2.4.8

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Load PC-relative address.

2.4.1.1 Syntax

ADR{cond} Rd, label

where:

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rd is the destination register.

label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”.

2.4.1.2 Operation

ADR determines the address by adding an immediate value to the PC, and writes the result

to the destination register.

ADR produces position-independent code, because the address is PC-relative.

If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that

bit[0] of the address you generate is set to1 for correct execution.

Values of label must be within the range of −4095 to +4095 from the address in the PC.

Remark: You might have to use the .W suffix to get the maximum offset range or to

generate addresses that are not word-aligned. See Section 34–2.3.8 “Instruction width

selection”.

2.4.1.3 Restrictions

Rd must not be SP and must not be PC.

2.4.1.4 Condition flags

This instruction does not change the flags.

2.4.1.5 Examples

ADR

R1, TextMessage

;

Write address value of

TextMessage to R1

a

location labelled as

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2.4.2 LDR and STR, immediate offset

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed

immediate offset.

2.4.2.1 Syntax

op{type}{cond} Rt, [Rn {, #offset}]

; immediate offset

op{type}{cond} Rt, [Rn, #offset]!

op{type}{cond} Rt, [Rn], #offset

opD{cond} Rt, Rt2, [Rn {, #offset}]

opD{cond} Rt, Rt2, [Rn, #offset]!

opD{cond} Rt, Rt2, [Rn], #offset

where:

; pre-indexed

; post-indexed

; immediate offset, two words

; pre-indexed, two words

; post-indexed, two words

op is one of:

LDR: Load register.

STR: Store register.

type is one of:

B

: unsigned byte, zero extend to 32 bits on loads.

SB: signed byte, sign extend to 32 bits (LDR only).

: unsigned halfword, zero extend to 32 bits on loads.

H

SH: signed halfword, sign extend to 32 bits (LDR only).

—: omit, for word.

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rt is the register to load or store.

Rn is the register on which the memory address is based.

offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.

Rt2 is the additional register to load or store for two-word operations.

2.4.2.2 Operation

LDR instructions load one or two registers with a value from memory.

STR instructions store one or two register values to memory.

Load and store instructions with immediate offset can use the following addressing

modes:

• Offset addressing

The offset value is added to or subtracted from the address obtained from the register

Rn. The result is used as the address for the memory access. The register Rn is

unaltered. The assembly language syntax for this mode is:

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[Rn, #offset]

• Pre-indexed addressing

The offset value is added to or subtracted from the address obtained from the register

Rn. The result is used as the address for the memory access and written back into the

register Rn. The assembly language syntax for this mode is:

[Rn, #offset]!

• Post-indexed addressing

The address obtained from the register Rn is used as the address for the memory

access. The offset value is added to or subtracted from the address, and written back

into the register Rn. The assembly language syntax for this mode is:

[Rn], #offset

The value to load or store can be a byte, halfword, word, or two words. Bytes and

halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address alignment”.

Table 34–618 shows the ranges of offset for immediate, pre-indexed and post-indexed

forms.

Table 618. Offset ranges

Instruction type

Immediate offset

Pre-indexed

Post-indexed

Word, halfword, signed −255 to 4095

halfword, byte, or

−255 to 255

signed byte

Two words

multiple of 4 in the

range −1020 to 1020

multiple of 4 in the

range -1020 to 1020

multiple of 4 in the

range −1020 to 1020

2.4.2.3 Restrictions

For load instructions:

• Rt can be SP or PC for word loads only

• Rt must be different from Rt2 for two-word loads

• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

When Rt is PC in a word load instruction:

• bit[0] of the loaded value must be 1 for correct execution

• a branch occurs to the address created by changing bit[0] of the loaded value to 0

• if the instruction is conditional, it must be the last instruction in the IT block.

For store instructions:

• Rt can be SP for word stores only

• Rt must not be PC

• Rn must not be PC

• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

2.4.2.4 Condition flags

These instructions do not change the flags.

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2.4.2.5 Examples

LDR

LDRNE

R8, [R10]

R2, [R5, #960]!

;

Loads R8 from the address in R10.

Loads (conditionally) R2 from word

960 bytes above the address in R5, and

increments R5 by 960.

a

STR

R2, [R9,#const-struc]

R3, [R4], #4

const-struc is an expression evaluating

to

Store R3 as halfword data into address in

R4, then increment R4 by

Load R8 from word 32 bytes above the

a constant in the range 0-4095.

STRH

LDRD

4

R8, R9, [R3, #0x20]

a

address in R3, and load R9 from

bytes above the address in R3

a word 36

STRD

R0, R1, [R8], #-16

Store R0 to address in R8, and store R1 to

word bytes above the address in R8,

and then decrement R8 by 16.

a

4

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2.4.3 LDR and STR, register offset

Load and Store with register offset.

2.4.3.1 Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}]

where:

op is one of:

LDR: Load Register.

STR: Store Register.

type is one of:

B

: unsigned byte, zero extend to 32 bits on loads.

SB: signed byte, sign extend to 32 bits (LDR only).

: unsigned halfword, zero extend to 32 bits on loads.

H

SH: signed halfword, sign extend to 32 bits (LDR only).

—: omit, for word.

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rt is the register to load or store.

Rn is the register on which the memory address is based.

Rm is a register containing a value to be used as the offset.

LSL #n is an optional shift, with n in the range 0 to 3.

2.4.3.2 Operation

LDR instructions load a register with a value from memory.

STR instructions store a register value into memory.

The memory address to load from or store to is at an offset from the register Rn. The

offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL

.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes

and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address

alignment”.

2.4.3.3 Restrictions

In these instructions:

• Rn must not be PC

• Rm must not be SP and must not be PC

• Rt can be SP only for word loads and word stores

• Rt can be PC only for word loads.

When Rt is PC in a word load instruction:

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• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this

halfword-aligned address

• if the instruction is conditional, it must be the last instruction in the IT block.

2.4.3.4 Condition flags

These instructions do not change the flags.

2.4.3.5 Examples

STR

R0, [R5, R1]

;

Store value of R0 into an address equal to

sum of R5 and R1

Read byte value from an address equal to

sum of R5 and two times R1, sign extended it

LDRSB R0, [R5, R1, LSL #1]

to

a word value and put it in R0

STR

R0, [R1, R2, LSL #2]

Stores R0 to an address equal to sum of R1

and four times R2

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2.4.4 LDR and STR, unprivileged

Load and Store with unprivileged access.

2.4.4.1 Syntax

op{type}T{cond} Rt, [Rn {, #offset}]

; immediate offset

where:

op is one of:

LDR: Load Register.

STR: Store Register.

type is one of:

B

: unsigned byte, zero extend to 32 bits on loads.

SB: signed byte, sign extend to 32 bits (LDR only).

: unsigned halfword, zero extend to 32 bits on loads.

H

SH: signed halfword, sign extend to 32 bits (LDR only).

—: omit, for word.

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rt is the register to load or store.

Rn is the register on which the memory address is based.

offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value

in Rn.

2.4.4.2 Operation

These load and store instructions perform the same function as the memory access

instructions with immediate offset, see Section 34–2.4.2. The difference is that these

instructions have only unprivileged access even when used in privileged software.

When used in unprivileged software, these instructions behave in exactly the same way

as normal memory access instructions with immediate offset.

2.4.4.3 Restrictions

In these instructions:

• Rn must not be PC

• Rt must not be SP and must not be PC.

2.4.4.4 Condition flags

These instructions do not change the flags.

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2.4.4.5 Examples

STRBTEQ R4, [R7]

;

Conditionally store least significant byte in

R4 to an address in R7, with unprivileged access

Load halfword value from an address equal to

LDRHT

R2, [R2, #8]

sum of R2 and

8

into R2, with unprivileged access

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2.4.5 LDR, PC-relative

Load register from memory.

2.4.5.1 Syntax

LDR{type}{cond} Rt, label

LDRD{cond} Rt, Rt2, label

type is one of:

; Load two words

B

: unsigned byte, zero extend to 32 bits on loads.

SB: signed byte, sign extend to 32 bits (LDR only).

: unsigned halfword, zero extend to 32 bits on loads.

H

SH: signed halfword, sign extend to 32 bits (LDR only).

—: omit, for word.

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rt is the register to load or store.

Rt2 is the second register to load or store.

label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”.

2.4.5.2 Operation

LDR loads a register with a value from a PC-relative memory address. The memory

address is specified by a label or by an offset from the PC.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes

and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address

alignment”.

label must be within a limited range of the current instruction. Table 34–619 shows the

possible offsets between label and the PC.

Table 619. Offset ranges

Instruction type

Offset range

−4095 to 4095

−1020 to 1020

Word, halfword, signed halfword, byte, signed byte

Two words

Remark: You might have to use the .W suffix to get the maximum offset range. See

Section 34–2.3.8 “Instruction width selection”.

2.4.5.3 Restrictions

In these instructions:

• Rt can be SP or PC only for word loads

• Rt2 must not be SP and must not be PC

• Rt must be different from Rt2.

When Rt is PC in a word load instruction:

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• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this

halfword-aligned address

• if the instruction is conditional, it must be the last instruction in the IT block.

2.4.5.4 Condition flags

These instructions do not change the flags.

2.4.5.5 Examples

LDR

R0, LookUpTable

R7, localdata

;

Load R0 with

labelled as LookUpTable

Load byte value from an address labelled

a word of data from an address

LDRSB

a

as localdata, sign extend it to

value, and put it in R7

a word

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2.4.6 LDM and STM

Load and Store Multiple registers.

2.4.6.1 Syntax

op{addr_mode}{cond} Rn{!}, reglist

where:

op is one of:

LDM: Load Multiple registers.

STM: Store Multiple registers.

addr_mode is any one of the following:

IA: Increment address After each access. This is the default.

DB: Decrement address Before each access.

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rn is the register on which the memory addresses are based.

! is an optional writeback suffix. If ! is present the final address, that is loaded from or

stored to, is written back into Rn.

reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can

contain register ranges. It must be comma separated if it contains more than one register

or register range, see Section 34–2.4.6.5.

LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full

Descending stacks.

LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending

stacks.

STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty

Ascending stacks.

STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending

stacks

2.4.6.2 Operation

LDM instructions load the registers in reglist with word values from memory addresses

based on Rn.

STM instructions store the word values in the registers in reglist to memory addresses

based on Rn.

For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses

are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of

registers in reglist. The accesses happens in order of increasing register numbers, with

the lowest numbered register using the lowest memory address and the highest number

register using the highest memory address. If the writeback suffix is specified, the value of

Rn + 4 * (n-1) is written back to Rn.

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For LDMDB

,

LDMEA

,

STMDB, and STMFD the memory addresses used for the accesses are at

4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in

reglist. The accesses happen in order of decreasing register numbers, with the highest

numbered register using the highest memory address and the lowest number register

using the lowest memory address. If the writeback suffix is specified, the value of

Rn - 4 * (n-1) is written back to Rn.

The PUSH and POP instructions can be expressed in this form. See Section 34–2.4.7 for

details.

2.4.6.3 Restrictions

In these instructions:

• Rn must not be PC

• reglist must not contain SP

• in any STM instruction, reglist must not contain PC

• in any LDM instruction, reglist must not contain PC if it contains LR

• reglist must not contain Rn if you specify the writeback suffix.

When PC is in reglist in an LDM instruction:

• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch

occurs to this halfword-aligned address

• if the instruction is conditional, it must be the last instruction in the IT block.

2.4.6.4 Condition flags

These instructions do not change the flags.

2.4.6.5 Examples

LDM

STMDB

R8,{R0,R2,R9}

R1!,{R3-R6,R11,R12}

; LDMIA is a synonym for LDM

2.4.6.6 Incorrect examples

STM

LDM

R5!,{R5,R4,R9}

R2, {}

;

Value stored for R5 is unpredictable

There must be at least one register in the list

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2.4.7 PUSH and POP

Push registers onto, and pop registers off a full-descending stack.

2.4.7.1 Syntax

PUSH{cond} reglist

POP{cond} reglist

where:

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It

must be comma separated if it contains more than one register or register range.

PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the

access based on SP, and with the final address for the access written back to the SP. PUSH

and POP are the preferred mnemonics in these cases.

2.4.7.2 Operation

PUSH stores registers on the stack in order of decreasing the register numbers, with the

highest numbered register using the highest memory address and the lowest numbered

register using the lowest memory address.

POP loads registers from the stack in order of increasing register numbers, with the lowest

numbered register using the lowest memory address and the highest numbered register

using the highest memory address.

See Section 34–2.4.6 for more information.

2.4.7.3 Restrictions

In these instructions:

• reglist must not contain SP

• for the PUSH instruction, reglist must not contain PC

• for the POP instruction, reglist must not contain PC if it contains LR.

When PC is in reglist in a POP instruction:

• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch

occurs to this halfword-aligned address

• if the instruction is conditional, it must be the last instruction in the IT block.

2.4.7.4 Condition flags

These instructions do not change the flags.

2.4.7.5 Examples

PUSH

POP

{R0,R4-R7}

{R2,LR}

{R0,R10,PC}

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2.4.8 LDREX and STREX

Load and Store Register Exclusive.

2.4.8.1 Syntax

LDREX{cond} Rt, [Rn {, #offset}]

STREX{cond} Rd, Rt, [Rn {, #offset}]

LDREXB{cond} Rt, [Rn]

STREXB{cond} Rd, Rt, [Rn]

LDREXH{cond} Rt, [Rn]

STREXH{cond} Rd, Rt, [Rn]

where:

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rd is the destination register for the returned status.

Rt is the register to load or store.

Rn is the register on which the memory address is based.

offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the

value in Rn.

2.4.8.2 Operation

LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory

address.

LDREX

,

STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a

memory address. The address used in any Store-Exclusive instruction must be the same

as the address in the most recently executed Load-exclusive instruction. The value stored

by the Store-Exclusive instruction must also have the same data size as the value loaded

by the preceding Load-exclusive instruction. This means software must always use a

Load-exclusive instruction and a matching Store-Exclusive instruction to perform a

synchronization operation, see Section 34–3.2.7 “Synchronization primitives”

If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If

it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive

instruction writes 0 to the destination register, it is guaranteed that no other process in the

system has accessed the memory location between the Load-exclusive and

Store-Exclusive instructions.

For reasons of performance, keep the number of instructions between corresponding

Load-Exclusive and Store-Exclusive instruction to a minimum.

Remark: The result of executing a Store-Exclusive instruction to an address that is

different from that used in the preceding Load-Exclusive instruction is unpredictable.

2.4.8.3 Restrictions

In these instructions:

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• do not use PC

• do not use SP for Rd and Rt

• for STREX, Rd must be different from both Rt and Rn

• the value of offset must be a multiple of four in the range 0-1020.

2.4.8.4 Condition flags

These instructions do not change the flags.

2.4.8.5 Examples

MOV

R1, #0x1

;

Initialize the ‘lock taken’ value

try

LDREX

CMP

ITT

R0, [LockAddr]

R0, #0

EQ

;

Load the lock value

Is the lock free?

IT instruction for STREXEQ and CMPEQ

Try and claim the lock

Did this succeed?

STREXEQ R0, R1, [LockAddr]

CMPEQ

BNE

R0, #0

try

No

–

try again

....

Yes

–

we have the lock

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2.4.9 CLREX

Chapter 34: Appendix: Cortex-M3 User Guide

Clear Exclusive.

2.4.9.1 Syntax

CLREX{cond}

where:

cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

2.4.9.2 Operation

Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination

register and fail to perform the store. It is useful in exception handler code to force the

failure of the store exclusive if the exception occurs between a load exclusive instruction

and the matching store exclusive instruction in a synchronization operation.

See Section 34–3.2.7 “Synchronization primitives” for more information.

2.4.9.3 Condition flags

These instructions do not change the flags.

2.4.9.4 Examples

CLREX

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2.5 General data processing instructions

Table 34–620 shows the data processing instructions:

Table 620. Data processing instructions

Mnemonic

ADC

Brief description

Add with Carry

Add

See

Section 34–2.5.1

Section 34–2.5.2

Section 34–2.5.3

Section 34–2.5.2

Section 34–2.5.4

Section 34–2.5.5

Section 34–2.5.2

Section 34–2.5.3

Section 34–2.5.6

Section 34–2.5.7

Section 34–2.5.6

Section 34–2.5.2

Section 34–2.5.8

Section 34–2.5.3

Section 34–2.5.1

Section 34–2.5.9

ADD

ADDW

AND

Add

Logical AND

ASR

Arithmetic Shift Right

Bit Clear

BIC

CLZ

Count leading zeros

Compare Negative

Compare

CMN

CMP

EOR

Exclusive OR

LSL

Logical Shift Left

Logical Shift Right

Move

LSR

MOV

MOVT

MOVW

MVN

Move Top

Move 16-bit constant

Move NOT

ORN

Logical OR NOT

Logical OR

ORR

RBIT

REV

Reverse Bits

Reverse byte order in a word

Reverse byte order in each halfword

Reverse byte order in bottom halfword and sign extend

Rotate Right

REV16

REVSH

ROR

RRX

Rotate Right with Extend

Reverse Subtract

Subtract with Carry

Subtract

RSB

SBC

SUB

SUBW

TEQ

Subtract

Test Equivalence

Test

TST

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Chapter 34: Appendix: Cortex-M3 User Guide

2.5.1 ADD, ADC, SUB, SBC, and RSB

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.

2.5.1.1 Syntax

op{S}{cond} {Rd,} Rn, Operand2

op{cond} {Rd,} Rn, #imm12

where:

; ADD and SUB only

op is one of:

ADD: Add.

ADC: Add with Carry.

SUB: Subtract.

RSB: Reverse Subtract.

S: is an optional suffix. If S is specified, the condition code flags are updated on the result

of the operation, see Section 34–2.3.7 “Conditional execution”.

cond: is an optional condition code, see Section 34–2.3.7 “Conditional execution”.

Rd is the destination register. If Rd is omitted, the destination register is Rn.

Rn is the register holding the first operand.

Operand2 is a flexible second operand. See Section 34–2.3.3 for details of the options.

imm12 is any value in the range 0-4095.

2.5.1.2 Operation

The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.

The ADC instruction adds the values in Rn and Operand2, together with the carry flag.

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.

The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag

is clear, the result is reduced by one.

The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful

because of the wide range of options for Operand2.

Use ADC and SBC to synthesize multiword arithmetic, see Section 34–2.5.1.6.


型号：	LPC1764FBD100
厂家：	NXP
描述：	LPC17xx User manual LPC17xx用户手册 PC
文件：	总835页 (文件大小：4620K)
中文：	中文翻译
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