LPC2103_技术文档

LPC2101/2102/2103

Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB

ﬂash with ISP/IAP, fast ports and 10-bit ADC

Rev. 01 — 18 January 2006

Preliminary data sheet

1. General description

The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB

of embedded high-speed ﬂash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30 % over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for

applications where miniaturization is a key requirement. A blend of serial communications

interfaces ranging from multiple UARTs, SPI to SSP and two I²C-buses, combined with

on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication

gateways and protocol converters. The superior performance also makes these devices

suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved

10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with

up to nine edge or level sensitive external interrupt pins make these microcontrollers

particularly suitable for industrial control and medical systems.

2. Features

2.1 Key features

■ 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.

■ 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip ﬂash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

■ ISP/IAP via on-chip bootloader software. Single ﬂash sector or full chip erase in

100 ms and programming of 256 bytes in 1 ms.

■ EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.

■ The 10-bit A/D converter provides eight analog inputs, with conversion times as low as

2.44 µs per channel and dedicated result registers to minimize interrupt overhead.

■ Two 32-bit timers/external event counters with combined seven capture and seven

compare channels.

■ Two 16-bit timers/external event counters with combined three capture and seven

compare channels.

■ Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz

clock input.

■ Multiple serial interfaces including two UARTs (16C550), two Fast I²C-buses

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

■ Vectored interrupt controller with conﬁgurable priorities and vector addresses.

■ Up to thirty-two 5 V tolerant fast general purpose I/O pins.

■ Up to 13 edge or level sensitive external interrupt pins available.

■ 70 MHz maximum CPU clock available from programmable on-chip PLL with a

possible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.

■ On-chip integrated oscillator operates with an external crystal in the range from 1 MHz

to 25 MHz.

■ Power saving modes include Idle mode, Power-down mode with RTC active, and

Power-down mode.

■ Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.

■ Processor wake-up from Power-down mode via external interrupt or RTC.

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

LPC2101FBD48 LQFP48

LPC2102FBD48 LQFP48

LPC2103FBD48 LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; SOT313-2

body 7 × 7 × 1.4 mm

plastic low proﬁle quad ﬂat package; 48 leads; SOT313-2

body 7 × 7 × 1.4 mm

plastic low proﬁle quad ﬂat package; 48 leads; SOT313-2

body 7 × 7 × 1.4 mm

LPC2103FA44

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

3.1 Ordering options

Table 2:

Ordering options

Type number

Flash

RAM

ADC

Temperature

memory

range (°C)

LPC2101FBD48

LPC2102FBD48

LPC2103FBD48

LPC2103FA44

8 kB

2 kB

4 kB

8 kB

8 inputs

−40 to +85

16 kB

32 kB

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

2 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

4. Block diagram

TMS

TDI

XTAL2 V

V

DD(3V3) DD(1V8)

XTAL1 RST

V

TRST

TCK

TDO

SS

LPC2101/2102/2103

TEST/DEBUG

INTERFACE

HIGH SPEED

GENERAL

PURPOSE I/O

SYSTEM

FUNCTIONS

PLL

P0[31:0]

8 kB

BOOT ROM

ARM7TDMI-S

system

clock

AHB BRIDGE

VECTORED

INTERRUPT

CONTROLLER

ARM7 local bus

AMBA AHB

(Advanced High-performance Bus)

INTERNAL

SRAM

CONTROLLER

MEMORY

ACCELERATOR

2 kB/4 kB/

8 kB SRAM

8 kB/16 kB/

32 kB FLASH

AHB TO APB

BRIDGE

APB (ARM

peripheral bus)

(1)

SCL0, SCL1

2

EINT2 to

EINT0

I C-BUS SERIAL

EXTERNAL

INTERRUPTS

(1)

INTERFACES 0 AND 1

SDA0, SDA1

(1)

3 × CAP0

(1)

4 × CAP1

3 × CAP2

3 × MAT0

4 × MAT1

3 × MAT2

4 × MAT3

(1)

SCK0, SCK1

CAPTURE/COMPARE

EXTERNAL COUNTER

TIMER 0/TIMER 1/

(1)

SPI AND SSP

SERIAL INTERFACES

MOSI0, MOSI1

MISO0, MISO1

SSEL0, SSEL1

TIMER 2/TIMER 3

(1)

TXD0, TXD1

(1)

RXD0, RXD1

AD0[7:0]

ADC

UART0/UART1

DSR1, CTS1,

RTS1, DTR1

DCD1, RI1

RTXC1

RTXC2

VBAT

GENERAL

PURPOSE I/O

P0[31:0]

REAL-TIME CLOCK

SYSTEM CONTROL

WATCHDOG

TIMER

002aab814

(1) Pins shared with GPIO.

Fig 1. Block diagram

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

3 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

5. Pinning information

5.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

P0.19/MAT1.2/MISO1

P0.11/CTS1/CAP1.1/AD0.4

P0.10/RTS1/CAP1.0/AD0.3

P0.24/AD0.2

P0.20/MAT1.3/MOSI1

P0.21/SSEL1/MAT3.0

VBAT

3

4

P0.23/AD0.1

5

V

P0.22/AD0.0

DD(1V8)

6

RST

V

SSA

LPC2101/2102/2103

7

V

P0.9/RXD1/MAT2.2

P0.8/TXD1/MAT2.1

P0.7/SSEL0/MAT2.0

DBGSEL

SS

8

P0.27/TRST/CAP2.0

P0.28/TMS/CAP2.1

P0.29/TCK/CAP2.2

X1

9

10

11

12

RTCK

X2

RTXC2

002aab821

Fig 2. LQFP48 pin conﬁguration

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

4 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

7

39

38

37

36

35

34

33

32

31

30

29

P0.11/CTS1/CAP1.1/AD0.4

P0.10/RTS1/CAP1.0/AD0.3

P0.24/AD0.2

P0.19/MAT1.2/MISO1

8

P0.20/MAT1.3/MOSI1

P0.21/SSEL1/MAT3.0

9

10

11

12

13

14

15

16

17

V

P0.23/AD0.1

DD(1V8)

RST

P0.22/AD0.0

V

SS

LPC2101/2102/2103

V

SSA

P0.27/TRST/CAP2.0

P0.28/TMS/CAP2.1

P0.29/TCK/CAP2.2

X1

P0.9/RXD1/MAT2.2

P0.8/TXD1/MAT2.1

P0.7/SSEL0/MAT2.0

DBGSEL

X2

RTXC2

002aab920

Fig 3. PLCC44 pin conﬁguration

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

5 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

5.2 Pin description

Table 3:

Symbol

Pin description

LQFP48

PLCC44

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction

controls for each bit. A total of 31 pins of the Port 0 can be

used as general purpose bidirectional digital I/Os while P0.31

is an output only pin. The operation of port 0 pins depends

upon the pin function selected via the pin connect block.

P0.0/TXD0/

MAT3.1

13^[1]

14^[2]

18^[3]

18^[1]

19^[2]

22^[3]

I/O

O

P0.0 — General purpose Input/output digital pin (GPIO).

TXD0 — Transmitter output for UART0.

O

MAT3.1 — PWM output 1 for Timer 3.

P0.1/RXD0/

MAT3.2

I/O

I

P0.1 — General purpose Input/output digital pin (GPIO).

RXD0 — Receiver input for UART0.

O

MAT3.2 — PWM output 2 for Timer 3.

P0.2/SCL0/

CAP0.0

I/O

P0.2 — General purpose Input/output digital pin (GPIO).

SCL0 — I²C0 clock Input/output. Open-drain output (for

I²C-bus compliance).

I

CAP0.0 — Capture input for Timer 0, channel 0.

P0.3/SDA0/

MAT0.0

21^[3]

22^[4]

23^[4]

24^[4]

28^[2]

25^[3]

26^[4]

27^[4]

28^[4]

31^[2]

I/O

P0.3 — General purpose Input/output digital pin (GPIO).

SDA0 — I²C0 data input/output. Open-drain output (for

I²C-bus compliance).

O

MAT0.0 — PWM output for Timer 0, channel 0.

P0.4/SCK0/

CAP0.1

I/O

P0.4 — General purpose Input/output digital pin (GPIO).

SCK0 — Serial clock for SPI0. SPI clock output from master

or input to slave.

I

CAP0.1 — Capture input for Timer 0, channel 1.

P0.5/MISO0/

MAT0.1

I/O

P0.5 — General purpose Input/output digital pin (GPIO).

MISO0 — Master In Slave OUT for SPI0. Data input to SPI

master or data output from SPI slave.

O

MAT0.1 — PWM output for Timer 0, channel 1.

P0.6/MOSI0/

CAP0.2

I/O

P0.6 — General purpose Input/output digital pin (GPIO).

MOSI0 — Master Out Slave In for SPI0. Data output from SPI

master or data input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

P0.7/SSEL0/

MAT2.0

I/O

I

P0.7 — General purpose Input/output digital pin (GPIO).

SSEL0 — Slave Select for SPI0. Selects the SPI interface as

a slave.

O

MAT2.0 — PWM output for Timer 2, channel 0.

P0.8 — General purpose Input/output digital pin (GPIO).

TXD1 — Transmitter output for UART1.

P0.8/TXD1/

MAT2.1

29^[4]

32^[4]

I/O

O

MAT2.1 — PWM output for Timer 2, channel 1.

P0.9 — General purpose Input/output digital pin (GPIO).

RXD1 — Receiver input for UART1.

P0.9/RXD1/

MAT2.2

30^[2]

33^[2]

I/O

I

O

MAT2.2 — PWM output for Timer 2, channel 2.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

6 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3:

Symbol

Pin description …continued

LQFP48

PLCC44

Type

Description

P0.10/RTS1/

CAP1.0/AD0.3

35^[4]

38^[4]

39^[3]

40^[4]

I/O

O

I

P0.10 — General purpose Input/output digital pin (GPIO).

RTS1 — Request to Send output for UART1.

CAP1.0 — Capture input for Timer 1, channel 0.

AD0.3 — ADC 0, input 3.

I

P0.11/CTS1/

CAP1.1/AD0.4

36^[3]

I/O

I

P0.11 — General purpose Input/output digital pin (GPIO).

CTS1 — Clear to Send input for UART1.

I

CAP1.1 — Capture input for Timer 1, channel 1.

AD0.4 — ADC 0, input 4.

I

P0.12/DSR1/

MAT1.0/AD0.5

37^[4]

I/O

I

P0.12 — General purpose Input/output digital pin (GPIO).

DSR1 — Data Set Ready input for UART1.

MAT1.0 — PWM output for Timer 1, channel 0.

AD0.5 — ADC 0, input 5.

O

I

P0.13/DTR1/

MAT1.1

41^[4]

43^[4]

I/O

O

I/O

I

P0.13 — General purpose Input/output digital pin (GPIO).

DTR1 — Data Terminal Ready output for UART1.

MAT1.1 — PWM output for Timer 1, channel 1.

P0.14 — General purpose Input/output digital pin (GPIO).

DCD1 — Data Carrier Detect input for UART1.

P0.14/DCD1/

SCK1/EINT1

44^[3]

2^[3]

I/O

SCK1 — Serial Clock for SPI1. SPI clock output from master

or input to slave.

I

EINT1 — External interrupt 1 input.

P0.15/RI1/

EINT2

45^[4]

3^[4]

4^[2]

5^[1]

I/O

I

P0.15 — General purpose Input/output digital pin (GPIO).

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

P0.16/EINT0/

MAT0.2

46^[2]

I/O

I

P0.16 — General purpose Input/output digital pin (GPIO).

EINT0 — External interrupt 0 input.

O

I/O

I

MAT0.2 — PWM output for Timer 0, channel 2.

P0.17 — General purpose Input/output digital pin (GPIO).

CAP1.2 — Capture input for Timer 1, channel 2.

P0.17/CAP1.2/ 47^[1]

SCL1

I/O

SCL1 — I²C1 clock Input/output. Open-drain output (for

I²C-bus compliance).

P0.18/CAP1.3/ 48^[1]

SDA1

6^[1]

7^[1]

8^[2]

I/O

I

P0.18 — General purpose Input/output digital pin (GPIO).

CAP1.3 — Capture input for Timer 1, channel 3.

SDA1 — I²C1 data Input/output. Open-drain output (for

I²C-bus compliance).

I/O

P0.19/MAT1.2/ 1^[1]

MISO1

I/O

O

P0.19 — General purpose Input/output digital pin (GPIO).

MAT1.2 — PWM output for Timer 1, channel 2.

I/O

MISO1 — Master In Slave Out for SSP. Data input to SPI

master or data output from SSP slave.

P0.20/MAT1.3/ 2^[2]

MOSI1

I/O

O

P0.20 — General purpose Input/output digital pin (GPIO).

MAT1.3 — PWM output for Timer 1, channel 3.

I/O

MOSI1 — Master Out Slave for SSP. Data output from SSP

master or data input to SSP slave.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

7 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3:

Symbol

Pin description …continued

LQFP48

PLCC44

Type

I/O

I

Description

P0.21/SSEL1/

MAT3.0

3^[4]

9^[4]

P0.21 — General purpose Input/output digital pin (GPIO).

SSEL1 — Slave Select for SPI1. Selects the SPI interface as

a slave.

O

I/O

I

MAT3.0 — PWM output for Timer 3, channel 0.

P0.22 — General purpose Input/output digital pin (GPIO).

AD0.0 — ADC 0, input 0.

P0.22/AD0.0

P0.23/AD0.1

P0.24/AD0.2

P0.25/AD0.6

P0.26/AD0.7

32^[4]

33^[1]

34^[1]

38^[1]

39^[1]

8^[4]

35^[4]

36^[1]

37^[1]

41^[1]

n.c.

I/O

I

P0.23 — General purpose Input/output digital pin (GPIO).

AD0.1 — ADC 0, input 1.

I/O

I

P0.24 — General purpose Input/output digital pin (GPIO).

AD0.2 — ADC 0, input 2.

I/O

I

P0.25 — General purpose Input/output digital pin (GPIO).

AD0.6 — ADC 0, input 6.

I/O

I

P0.26 — General purpose Input/output digital pin (GPIO).

AD0.7 — ADC 0, input 7.

P0.27/TRST/

CAP2.0

13^[4]

I/O

I

P0.27 — General purpose Input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

I

CAP2.0 — Capture input for Timer 2, channel 0.

P0.28 — General purpose Input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

CAP2.1 — Capture input for Timer 2, channel 1.

P0.29 — General purpose Input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface.

P0.28/TMS/

CAP2.1

9^[4]

14^[4]

15^[4]

20^[4]

21^[4]

I/O

I

P0.29/TCK/

CAP2.2

10^[4]

15^[4]

16^[4]

I/O

I

CAP2.2 — Capture input for Timer 2, channel 2.

P0.30 — General purpose Input/output digital pin (GPIO).

TDI — Test Data In for JTAG interface.

P0.30/TDI/

MAT3.3

I/O

I

O

I

MAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO

P0.31 — General purpose output only digital pin (GPIO).

TDO — Test Data Out for JTAG interface.

Input to the RTC oscillator circuit.

RTXC1

RTXC2

RTCK

20^[5]

25^[5]

26^[5]

24^[5]

29^[5]

n.c.

O

I/O

Output from the RTC oscillator circuit.

Returned test clock output: Extra signal added to the JTAG

port. Assists debugger synchronization when processor

frequency varies. Bidirectional pin with internal pull-up.

X1

11

16

I

Input to the oscillator circuit and internal clock generator

circuits.

X2

12

27

17

30

O

I

Output from the oscillator ampliﬁer.

DBGSEL

Debug select: When LOW, the part operates normally. When

HIGH, debug mode is entered. Input with internal pull-down.

RST

6

11

I

External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states and processor execution to begin at address 0. TTL

with hysteresis, 5 V tolerant.

V_SS

7, 19, 43

1, 12, 23

I

Ground: 0 V reference.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

8 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 3:

Symbol

V_SSA

Pin description …continued

LQFP48

PLCC44

Type

Description

31

34

I

Analog ground: 0 V reference. This should be nominally the

same voltage as V_SSbut should be isolated to minimize noise

and error.

V_DDA

42

44

I

Analog 3.3 V power supply: This should be nominally the

same voltage as V_DD(3V3)but should be isolated to minimize

noise and error. This voltage is used to power the on-chip

PLL. This pin also provides a voltage reference level for the

ADC.

V_DD(1V8)

V_DD(3V3)

VBAT

5

10

I

1.8 V core power supply: This is the power supply voltage for

internal circuitry.

17, 40

4

42

3.3 V pad power supply: This is the power supply voltage for

the I/O ports.

n.c.

RTC power supply: 3.3 V on this pin supplies the power to

the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If conﬁgured for an input

function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If conﬁgured

for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When conﬁgured as an ADC input, digital

section of the pad is disabled.

[5] Pad provides special analog functionality.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

9 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The particular ﬂash implementation in the LPC2101/2102/2103 allows for full speed

execution also in ARM mode. It is recommended to program performance critical and

short code sections in ARM mode. The impact on the overall code size will be minimal but

the speed can be increased by 30 % over Thumb mode.

6.2 On-chip ﬂash program memory

The LPC2101/2102/2103 incorporate a 8 kB, 16 kB or 32 kB ﬂash memory system

respectively. This memory may be used for both code and data storage. Programming of

the ﬂash memory may be accomplished in several ways. It may be programmed In

System via the serial port. The application program may also erase and/or program the

ﬂash while the application is running, allowing a great degree of ﬂexibility for data storage

ﬁeld ﬁrmware upgrades, etc. The entire ﬂash memory is available for user code as the

bootloader resides in a separate memory.

The LPC2101/2102/2103 ﬂash memory provides a minimum of 100,000 erase/write

cycles and 20 years of data-retention memory.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

10 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provide 2 kB, 4 kB or

8 kB of static RAM.

6.4 Memory map

The LPC2101/2102/2103 memory map incorporates several distinct regions, as shown in

Figure 4.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.17

“System control”.

4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xE000 0000

3.75 GB

3.5 GB

APB PERIPHERALS

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

0x7FFF FFFF

2.0 GB

BOOT BLOCK

0x7FFF E000

0x7FFF DFFF

RESERVED ADDRESS SPACE

0x4000 2000

0x4000 1FFF

8 kB ON-CHIP STATIC RAM (LPC2103)

0x4000 1000

0x4000 0FFF

4 kB ON-CHIP STATIC RAM (LPC2102)

2 kB ON-CHIP STATIC RAM (LPC2101)

RESERVED ADDRESS SPACE

0x4000 0800

0x4000 07FF

0x4000 0000

1.0 GB

0x0000 8000

0x0000 7FFF

32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2103)

0x0000 4000

0x0000 3FFF

16 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2102)

0x0000 2000

0x0000 1FFF

8 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2101)

0x0000 0000

0.0 GB

002aab822

Fig 4. LPC2101/2102/2103 memory map

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6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored

IRQ, and non-vectored IRQ as deﬁned by programmable settings. The programmable

assignment scheme means that priorities of interrupts from the various peripherals can be

dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine does not need to branch into the interrupt service routine but can

run from the interrupt vector location. If more than one request is assigned to the FIQ

class, the FIQ service routine will read a word from the VIC that identiﬁes which FIQ

source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC

provides the address of the highest-priority requesting IRQs service routine, otherwise it

provides the address of a default routine that is shared by all the non-vectored IRQs. The

default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt

Controller, but may have several internal interrupt ﬂags. Individual interrupt ﬂags may also

represent more than one interrupt source.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

The Pin Control Module with its pin select registers deﬁnes the functionality of the

microcontroller in a given hardware environment.

After reset all pins of Port 0 are conﬁgured as input with the following exceptions: If debug

is enabled, the JTAG pins will assume their JTAG functionality. The pins associated with

the I²C0 interface are open-drain.

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6.7 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8 10-bit A/D converter

The LPC2101/2102/2103 contain one analog to digital converter. It is a single 10-bit

successive approximation analog to digital converter with eight channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Every analog input has a dedicated result register to reduce interrupt overhead.

6.9 UARTs

The LPC2101/2102/2103 each contain two UARTs. In addition to standard transmit and

receive data lines, UART1 also provides a full modem control handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/2102/2103 include

a fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can

be achieved with any crystal frequency above 2 MHz.

6.9.1 Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

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• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs.

• UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware ﬂow control (auto-CTS/RTS).

6.10 I²C-bus serial I/O controllers

The LPC2101/2102/2103 each contain two I²C-bus controllers.

The I²C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line

(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the

capability to both receive and send information such as serial memory. Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus,

it can be controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast

I²C).

6.10.1 Features

• Compliant with standard I²C-bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can also be used for test and diagnostic purposes.

6.11 SPI serial I/O controller

The LPC2101/2102/2103 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the

slave, and the slave always sends 8 bits to 16 bits of data to the master.

6.11.1 Features

• Compliant with SPI speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

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• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.12 SSP serial I/O controller

The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. However, only a single master and a single slave can communicate on

the bus during a given data transfer. The SSP supports full duplex transfers, with data

frames of 4 bits to 16 bits ﬂowing from the master to the slave and from the slave to the

master. Often only one of these data streams carries meaningful data.

6.12.1 Features

• Compatible with Motorola SPI, 4-wire TI’s SSI and National Semiconductor’s

Microwire buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.13 General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/2102/2103 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.13.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• External event counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

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– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.14 General purpose 16-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes three capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/2102/2103 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.14.1 Features

• Two 16-bit timer/counters with a programmable 16-bit prescaler.

• External event counter or timer operation.

• Three 16-bit capture channels that can take a snapshot of the timer value when an

input signal transitions. A capture event may also optionally generate an interrupt.

• Four 16-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

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• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_PCLK× 256 × 4) to (T_PCLK× 2³²× 4) in multiples of

T

_PCLK× 4.

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider

allows ﬁne adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

6.17 System control

6.17.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.

The oscillator output frequency is called f_oscand the ARM processor clock frequency is

referred to as CCLK for purposes of rate equations, etc. f_oscand CCLK are the same value

unless the PLL is running and connected. Refer to Section 6.17.2 “PLL” for additional

information.

6.17.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip reset and may be enabled by software. The program must

conﬁgure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 µs.

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6.17.3 Reset and wake-up timer

Reset has two sources on the LPC2101/2102/2103: the RESET pin and watchdog reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of

chip reset by any source starts the wake-up timer (see wake-up timer description below),

causing the internal chip reset to remain asserted until the external reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined reset values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.17.4 Code security

This feature of the LPC2101/2102/2103 allow an application to control whether it can be

debugged or protected from observation.

If after reset on-chip bootloader detects a valid checksum in ﬂash and reads 0x8765 4321

from address 0x1FC in ﬂash, debugging will be disabled and thus the code in ﬂash will be

protected from observation. Once debugging is disabled, it can only be enabled by

performing a full chip erase using the ISP.

6.17.5 External interrupt inputs

The LPC2101/2102/2103 include up to three edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can be

processed as three independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake-up the processor from Power-down mode.

Additionally all 10 capture input pins can also be used as external interrupts without the

option to wake the device up from Power-down mode.

6.17.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

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6.17.7 Power control

The LPC2101/2102/2103 supports two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings during active

and Idle mode.

6.17.8 APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the APB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the APB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the APB

divider control registers reside on the APB bus), the default condition at reset is for the

APB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the APB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the APB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.18 Emulation and debugging

The LPC2101/2102/2103 support emulation and debugging via a JTAG serial port.

6.18.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

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entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

6.18.2 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2101/2102/2103 contain a speciﬁc

conﬁguration of RealMonitor software programmed into the on-chip boot ROM memory.

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7. Limiting values

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). ^[1]

Symbol

V_DD(1V8)

V_DD(3V3)

V_DDA

Parameter

Conditions

Min

Max

+2.5

+3.6

4.6

Unit

V

[2]

[3]

supply voltage (1.8 V)

supply voltage (3.3 V)

analog 3.3 V pad supply voltage

input voltage on pin VBAT

analog input voltage

input voltage

−0.5

V

V_i(VBAT)

V_IA

for the RTC

4.6

V

[4]

5.1

V

[5] [6]

V_I

5 V tolerant I/O

pins

6.0

V

[5]

[8]

other I/O pins

−0.5

V_DD+ 0.5^[7]

100^[9]

125

V

I_DD

supply current

-

mA

°C

W

[10]

[11]

I_SS

ground current

-

T_stg

storage temperature

total power dissipation (per package)

−40

P_tot(pack)

based on package

heat transfer, not

device power

-

1.5

consumption

[1] The following applies to the Limiting values:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Core and internal rail.

[3] External rail.

[4] On ADC related pins.

[5] Including voltage on outputs in 3-state mode.

[6] Only valid when the V_DD(3V3)supply voltage is present.

[7] Not to exceed 4.6 V.

[8] Per supply pin.

[9] The peak current is limited to 25 times the corresponding maximum current.

[10] Per ground pin.

[11] Dependent on package type.

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8. Static characteristics

Table 5:

Static characteristics

T_a= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

1.65

3.0

Typ ^[1]

1.8

Max

1.95

3.6

Unit

V

[2]

[3]

V_DD(1V8)supply voltage (1.8 V)

V_DD(3V3)supply voltage (3.3 V)

3.3

V

V_DDA

analog 3.3 V pad supply

voltage

3.0

3.3

3.6

V

V_i(VBAT)

input voltage on pin VBAT

2.0^[4]

3.3

3.6

V

Standard port pins, RESET, RTCK

I_IL

LOW-state input current

HIGH-state input current

OFF-state output current

V_I= 0 V; no pull-up

-

3

µA

I_IH

I_OZ

V_I= V_DD(3V3); no pull-down

V_O= 0 V, V_O= V_DD(3V3); no

pull-up/down

I_latch

I/O latch-up current

input voltage

−(0.5V_DD(3V3)) < V <

-

100

5.5

mA

V

(1.5V_DD(3V3)

)

T_j< 125 °C

[5] [6]

[7]

V_I

pin conﬁgured to provide a

digital function

0

V_O

output voltage

output active

0

-

V_DD(3V3)

V

V_IH

V_IL

HIGH-state input voltage

LOW-state input voltage

hysteresis voltage

2.0

-

0.8

V_hys

V_OH

0.4

-

[8]

HIGH-state output voltage I_OH= −4 mA

V_DD(3V3)

0.4

−

[8]

[9]

V_OL

I_OH

LOW-state output voltage I_OL= −4 mA

HIGH-state output current V_OH= V_DD(3V3)− 0.4 V

LOW-state output current V_OL= 0.4 V

-

0.4

-

V

−4

4

-

mA

I_OL

-

I_OHS

HIGH-state short-circuit

output current

V_OH= 0 V

−45

[9]

I_OLS

LOW-state short-circuit

output current

V_OL= V_DDA

-

50

mA

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V^[10]

10

−15

0

50

−50

0

150

−85

0

µA

[11]

V_I= 0 V

V_DD(3V3)< V_I< 5 V^[10]

I_DD(act)

active mode supply

current

V_DD(1V8)= 1.8 V, T_a= 25 °C,

code

while(1){}

executed from ﬂash, no active

peripherals

CCLK = 10 MHz

<tbd>

7

<tbd>

mA

CCLK = 70 MHz

41

(other parameters as above)

I_DD(pd)

Power-down mode supply V_DD(1V8)= 1.8 V, T_a= +25 °C

<tbd>

7

<tbd>

µA

current

V_DD(1V8)= 1.8 V, T_a= +85 °C

<tbd>

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

22 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 5:

Static characteristics …continued

T_a= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions

Min

Typ ^[1]

Max

Unit

I_BATpd

Power-down mode battery RTC clock = 32 kHz

supply current ^[12]

(from RTXC pins), T_a= +25 °C

V_DD(1V8)= 1.8 V, VBAT = 2.5 V

V_DD(1V8)= 1.8 V, VBAT = 3.0 V

-

7

8

<tbd>

µA

I_BATact

active mode battery

supply current ^[12]

CCLK = 70 MHz,

PCLK = 17.5 MHz,

PCLK enabled to RTCK,

RTC clock = 32 kHz

(from RTXC pins), T_a= +25 °C

V_DD(1V8)= 1.8 V, VBAT = 3.0 V

<tbd>

µA

I²C-bus pins

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-state input voltage

0.7V_DD(3V3)

-

V

LOW-state input voltage

hysteresis voltage

-

0.3V_DD(3V3)

V

0.5V_DD(3V3)

-

V

[8]

LOW-state output voltage I_OLS= 3 mA

input leakage current^[13]

-

0.4

4

V

V_I= V_DD(3V3)

V_I= 5 V

2

µA

10

22

Oscillator pins

V_i(XTAL1)input voltage on pin XTAL1

0

-

1.8

V

V_o(XTAL2)output voltage on pin

XTAL2

V_i(RTXC1)input voltage on pin

RTXC1

0

-

1.8

V

V_o(RTXC2)output voltage on pin

RTXC2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[2] Core and internal rail.

[3] External rail.

[4] The RTC typically fails when VBAT drops below 1.6 V.

[5] Including voltage on outputs in 3-state mode.

[6] V_DD(3V3)supply voltages must be present.

[7] 3-state outputs go into 3-state mode when V_DD(3V3)is grounded.

[8] Accounts for 100 mV voltage drop in all supply lines.

[9] Only allowed for a short time period.

[10] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[11] Applies to P1.25:16.

[12] On pin VBAT.

[13] To V_SS

.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

23 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

Table 6:

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_a= −40 °C to +85 °C unless otherwise speciﬁed. ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

0

-

C_ia

pF

[1] [2] [3]

[1] [4]

E_D

±1

LSB

%

E_L(adj)

E_O

±2

[1] [5]

±3

[1] [6]

E_G

gain error

±0.5

±4

[1] [7]

E_T

absolute error

LSB

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The A/D is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 5.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 5.

[5] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 5.

[6] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 5.

[7] The absolute error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated A/D

and the ideal transfer curve. See Figure 5.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

24 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

offset

error

gain

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

V

− V

DDA SSA

1 LSB =

1024

002aac046

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 5. A/D conversion characteristics

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

25 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

9. Dynamic characteristics

Table 7:

Dynamic characteristics

T_a= 0 °C to +70 °C for commercial applications, −40 °C to +85 °C for industrial applications, V_DD(1V8), V_DD(3V3)over speciﬁed

ranges ^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ ^[2]

Max

Unit

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

10

40

-

25

100

-

MHz

ns

T_cy(clk)

t_CHCX

T

-

_cy(clk)× 0.4

ns

t_CLCX

-

ns

t_CLCH

5

ns

t_CHCL

clock fall time

-

5

ns

Port pins (except P0.2 and P0.3)

t_r(o)

t_f(o)

output rise time

-

10

-

ns

output fall time

I²C-bus pins (P0.2 and P0.3)

[3]

t_f(o)output fall time

V_IHto V_IL

20 + 0.1 × C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[3] Bus capacitance C_bin pF, from 10 pF to 400 pF.

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

26 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

10. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 6. Package outline SOT313-2 (LQFP48)

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

27 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 7. Package outline SOT187-2 (PLCC44)

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

28 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

11. Abbreviations

Table 8:

Acronym

ADC

APB

Acronym list

Description

Analog-to-Digital Converter

Advanced Peripheral Bus

DCC

DSP

FIFO

FIQ

Debug Communications Channel

Digital Signal Processor

First In, First Out

Fast Interrupt Request

GPIO

IAP

General Purpose Input/Output

In-Application Programming

Interrupt Request

IRQ

ISP

In-System Programming

Phase-Locked Loop

PLL

PWM

SPI

Pulse Width Modulator

Serial Peripheral Interface

Static Random Access Memory

Serial Synchronous Port

Universal Asynchronous Receiver/Transmitter

Vectored Interrupt Controller

SRAM

SSP

UART

VIC

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

29 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

12. Revision history

Table 9:

Revision history

Document ID

Release

date

Data sheet status Change Doc. number

Supersedes

notice

LPC2101_2102_2103_1

20060118

Preliminary data

sheet

-

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

30 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

13. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

14. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

16. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

15. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

17. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

31 of 32

LPC2101/2102/2103

Philips Semiconductors

Single-chip 16-bit/32-bit microcontrollers

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.17.8

6.18

6.18.1

6.18.2

APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Emulation and debugging. . . . . . . . . . . . . . . . 19

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 19

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

2.1

3

3.1

4

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21

Static characteristics . . . . . . . . . . . . . . . . . . . 22

Dynamic characteristics. . . . . . . . . . . . . . . . . 26

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Contact information . . . . . . . . . . . . . . . . . . . . 31

8

9

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

10

11

12

13

14

15

16

17

6

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

6.7.1

6.8

6.8.1

6.9

6.9.1

6.10

6.10.1

6.11

6.11.1

6.12

6.12.1

6.13

Functional description . . . . . . . . . . . . . . . . . . 10

Architectural overview. . . . . . . . . . . . . . . . . . . 10

On-chip ﬂash program memory . . . . . . . . . . . 10

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12

Fast general purpose parallel I/O . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I²C-bus serial I/O controllers. . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SSP serial I/O controller . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General purpose 32-bit timers/external event

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General purpose 16-bit timers/external event

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System control . . . . . . . . . . . . . . . . . . . . . . . . 17

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reset and wake-up timer . . . . . . . . . . . . . . . . 18

Code security . . . . . . . . . . . . . . . . . . . . . . . . . 18

External interrupt inputs . . . . . . . . . . . . . . . . . 18

Memory mapping control . . . . . . . . . . . . . . . . 18

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.13.1

6.14

6.14.1

6.15

6.15.1

6.16

6.16.1

6.17

6.17.1

6.17.2

6.17.3

6.17.4

6.17.5

6.17.6

6.17.7

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 18 January 2006

Document number: LPC2101_02_03_1

Published in the Netherlands


型号：	LPC2103
厂家：	NXP
描述：	Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC 单芯片16位/ 32位微控制器; 8 KB / 16 KB / 32 KB闪存， ISP / IAP ，快速端口和10位ADC 闪存微控制器
文件：	总32页 (文件大小：161K)
中文：	中文翻译
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