LPC2134FBD64_技术文档

LPC2131/2132/2134/2136/2138

Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB

ISP/IAP Flash with 10-bit ADC and DAC

Rev. 02 — 15 April 2005

Preliminary data sheet

1. General description

The LPC2131/2132/2134/2136/2138 microcontrollers are based on a 32/16 bit

ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines

the microcontroller with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high

speed Flash memory. A 128-bit wide memory interface and a unique accelerator

architecture enable 32-bit code execution at maximum clock rate. For critical code size

applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with

minimal performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM

options of 8/16/32 kB, they are very well suited for communication gateways and protocol

converters, soft modems, voice recognition and low end imaging, providing both large

buffer size and high processing power. Various 32-bit timers, single or dual 10-bit

8 channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine edge or

level sensitive external interrupt pins make these microcontrollers particularly suitable for

industrial control and medical systems.

2. Features

2.1 Key features

■ 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

■ 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip Flash program

memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.

■ In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single Flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

■ EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high speed tracing of instruction execution.

■ One (LPC2131/32) or two (LPC2134/36/38) 8 channel 10-bit A/D converters provides

a total of up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.

■ Single 10-bit D/A converter provides variable analog output (LPC2132/34/36/38).

■ Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

■ Low power Real-time clock with independent power and dedicated 32 kHz clock input.

■ Multiple serial interfaces including two UARTs (16C550), two Fast I²C-bus (400 kbit/s),

SPI and SSP with buffering and variable data length capabilities.

■ Vectored interrupt controller with conﬁgurable priorities and vector addresses.

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

■ Up to 47 5 V tolerant general purpose I/O pins in tiny LQFP64 package.

■ Up to nine edge or level sensitive external interrupt pins available.

■ 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

time of 100 µs.

■ On-chip integrated oscillator operates with external crystal in range of 1 MHz to

30 MHz and with external oscillator up to 50 MHz.

■ Power saving modes include Idle and Power-down.

■ Individual enable/disable of peripheral functions as well as peripheral clock scaling

down for additional power optimization.

■ Processor wake-up from Power-down mode via external interrupt or BOD.

■ Single power supply chip with POR and BOD circuits:

◆ CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads.

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

LPC2131FBD64

LPC2132FBD64

LPC2134FBD64

LPC2136FBD64

LPC2138FBD64

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

SOT314-2

body 10 × 10 × 1.4 mm

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

SOT314-2

body 10 × 10 × 1.4 mm

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

body 10 × 10 × 1.4 mm

3.1 Ordering options

Table 2:

Ordering options

Type number

Flash memory RAM

ADC

DAC

Temperature

range (°C)

LPC2131FBD64

LPC2132FBD64

LPC2134FBD64

LPC2136FBD64

LPC2138FBD64

32 kB

8 kB

1

2

-

−40 to +85

64 kB

16 kB

32 kB

1

128 kB

256 kB

512 kB

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

2 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

4. Block diagram

(3)

TMS

(3)

TDI

(3)

XTAL2

XTAL1 RST

(3)

TRST

TCK

TDO

TEST/DEBUG

INTERFACE

LPC2131/2132/2134/2136/2138

SYSTEM

FUNCTIONS

PLL

ARM7TDMI-S

system

clock

VECTORED

INTERRUPT

CONTROLLER

AHB BRIDGE

ARM7 local bus

AMBA AHB

(Advanced High-performance Bus)

INTERNAL

SRAM

FLASH

CONTROLLER

AHB

DECODER

8/16/32 kB

SRAM

32/64/128/

256/512 kB

FLASH

AHB TO VPB

BRIDGE

VPB

DIVIDER

VPB (VLSI

peripheral bus)

SCL0,1

SDA0,1

2

EXTERNAL

INTERRUPTS

I C SERIAL

EINT3:0

INTERFACES 0 AND 1

8 × CAP0

SCK0,1

CAPTURE/

COMPARE

TIMER 0/TIMER 1

MOSI0,1

MISO0,1

SSEL0,1

SPI AND SSP

SERIAL INTERFACES

8 × MAT

AD0.7:0

A/D CONVERTERS

TXD0,1

RXD0,1

(1)

0 AND 1

(1)

AD1.7:0

UART0/UART1

(1)

DSR1 ,CTS1

,

(1)

RTS1 , DTR1

(2)

AOUT

D/A CONVERTER

(1)

DCD1 ,RI1

RTXC1

RTXC2

REAL TIME CLOCK

P0.31:0

GENERAL

PURPOSE I/O

V

BAT

P1.31:16

WATCHDOG

TIMER

PWM6:1

PWM0

SYSTEM

CONTROL

002aab067

(1) LPC2134/2136/2138 only.

(2) LPC2132/2134/2136/2138 only.

(3) Pins shared with GPIO.

Fig 1. Block diagram.

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Rev. 02 — 15 April 2005

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LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

5. Pinning information

5.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTXC1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTXC2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2131

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.12/MAT1.0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab068

Fig 2. LPC2131 pinning.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

4 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/CAP1.3

P0.22/CAP0.0/MAT0.0

RTXC1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/EINT2

3

4

P1.19/TRACEPKT3

RTXC2

5

P1.21/PIPESTAT0

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.14/EINT1/SDA1

P1.22/PIPESTAT1

P0.13/MAT1.1

LPC2132

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.12/MAT1.0

P0.11/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.10/CAP1.0

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

002aab406

Fig 3. LPC2132 pinning.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

5 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTXC1

P1.20/TRACESYNC

P0.17/CAP1.2/SCK1/MAT1.2

P0.16/EINT0/MAT0.2/CAP0.2

P0.15/RI1/EINT2/AD1.5

P1.21/PIPESTAT0

3

4

P1.19/TRACEPKT3

RTXC2

5

6

V

SS

DD

SS

7

V

DDA

8

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.14/DCD1/EINT1/SDA1

P1.22/PIPESTAT1

LPC2134/2136/2138

9

10

11

12

13

14

15

16

P0.26/AD0.5

P0.13/DTR1/MAT1.1/AD1.4

P0.12/DSR1/MAT1.0/AD1.3

P0.11/CTS1/CAP1.1/SCL1

P1.23/PIPESTAT2

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1

P0.28/AD0.1/CAP0.2/MAT0.2

P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P0.10/RTS1/CAP1.0/AD1.2

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4/AD1.1

002aab407

Fig 4. LPC2134/2136/2138 pinning.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

6 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

5.2 Pin description

Table 3:

Symbol

Pin description

Type

Description

P0.0 to P0.31

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

Total of 31 pins of the Port 0 can be used as a general purpose bi-directional

digital I/Os while P0.31 is output only pin. The operation of port 0 pins

depends upon the pin function selected via the pin connect block.

Pin P0.24 is not available.

P0.0/TXD0/

PWM1

19^[1]

21^[2]

O

I

TXD0 — Transmitter output for UART0.

PWM1 — Pulse Width Modulator output 1.

P0.1/RXD0/

RXD0 — Receiver input for UART0.

PWM3/EINT0

O

I

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input

P0.2/SCL0/

CAP0.0

22^[3]

26^[3]

I/O

I

SCL0 — I²C0 clock input/output. Open drain output (for I²C-bus compliance).

CAP0.0 — Capture input for Timer 0, channel 0.

SDA0 — I²C0 data input/output. Open drain output (for I²C-bus compliance).

MAT0.0 — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

P0.3/SDA0/

MAT0.0/EINT1

I/O

O

I

P0.4/SCK0/

CAP0.1/AD0.6

27^[4]

I/O

I

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

CAP0.1 — Capture input for Timer 0, channel 0.

I

AD0.6 — A/D converter 0, input 6. This analog input is always connected to

its pin.

P0.5/MISO0/

29^[4]

I/O

MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data

MAT0.1/AD0.7

output from SPI slave.

O

I

MAT0.1 — Match output for Timer 0, channel 1.

AD0.7 — A/D converter 0, input 7. This analog input is always connected to

its pin.

P0.6/MOSI0/

30^[4]

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

CAP0.2/AD1.0

input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

AD1.0 — A/D converter 1, input 0. This analog input is always connected to

its pin. Available in LPC2138 only.

P0.7/SSEL0/

PWM2/EINT2

31^[2]

I

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

O

I

P0.8/TXD1/

PWM4/AD1.1

33^[4]

O

I

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

AD1.1 — A/D converter 1, input 1. This analog input is always connected to

its pin. Available in LPC2138 only.

P0.9/RXD1/

PWM6/EINT3

34^[2]

I

RXD1 — Receiver input for UART1.

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

O

I

9397 750 14868

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7 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

Table 3:

Symbol

Pin description …continued

Type

Description

P0.10/RTS1/

CAP1.0/AD1.2

35^[4]

O

I

RTS1 — Request to Send output for UART1. Available in LPC2138 only.

CAP1.0 — Capture input for Timer 1, channel 0.

I

AD1.2 — A/D converter 1, input 2. This analog input is always connected to

its pin. Available in LPC2138 only.

P0.11/CTS1/

CAP1.1/SCL1

37^[3]

I

CTS1 — Clear to Send input for UART1. Available in LPC2138 only.

I

CAP1.1 — Capture input for Timer 1, channel 1.

I/O

SCL1 — I²C1 clock input/output. Open drain output (for I²C-bus compliance)

DSR1 — Data Set Ready input for UART1. Available in LPC2138 only.

MAT1.0 — Match output for Timer 1, channel 0.

P0.12/DSR1/

38^[4]

I

MAT1.0/AD1.3

O

I

AD1.3 — A/D converter input 3. This analog input is always connected to its

pin. Available in LPC2138 only.

P0.13/DTR1/

MAT1.1/AD1.4

39^[4]

O

I

DTR1 — Data Terminal Ready output for UART1. Available in LPC2138 only.

MAT1.1 — Match output for Timer 1, channel 1.

AD1.4 — A/D converter input 4. This analog input is always connected to its

pin. Available in LPC2138 only.

P0.14/DCD1/

EINT1/SDA1

41^[3]

I

DCD1 — Data Carrier Detect input for UART1. Available in LPC2138 only.

I

EINT1 — External interrupt 1 input.

I/O

SDA1 — I²C1 data input/output. Open drain output (for I²C-bus compliance)

RI1 — Ring Indicator input for UART1. Available in LPC2138 only.

EINT2 — External interrupt 2 input.

P0.15/RI1/

45^[4]

I

EINT2/AD1.5

AD1.5 — A/D converter 1, input 5. This analog input is always connected to

its pin. Available in LPC2138 only.

P0.16/EINT0/

46^[2]

I

EINT0 — External interrupt 0 input.

MAT0.2/CAP0.2

O

I

MAT0.2 — Match output for Timer 0, channel 2.

CAP0.2 — Capture input for Timer 0, channel 2.

CAP1.2 — Capture input for Timer 1, channel 2.

SCK1 — Serial Clock for SSP. Clock output from master or input to slave.

MAT1.2 — Match output for Timer 1, channel 2.

CAP1.3 — Capture input for Timer 1, channel 3.

P0.17/CAP1.2/ 47^[1]

SCK1/MAT1.2

I

I/O

O

I

P0.18/CAP1.3/ 53^[1]

MISO1/MAT1.3

I/O

MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave.

O

MAT1.3 — Match output for Timer 1, channel 3.

MAT1.2 — Match output for Timer 1, channel 2.

P0.19/MAT1.2/ 54^[1]

MOSI1/CAP1.2

O

I/O

MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data

input to SSP slave.

I

CAP1.2 — Capture input for Timer 1, channel 2.

MAT1.3 — Match output for Timer 1, channel 3.

SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.

EINT3 — External interrupt 3 input.

P0.20/MAT1.3/ 55^[2]

SSEL1/EINT3

O

I

P0.21/PWM5/

AD1.6/CAP1.3

1^[4]

O

I

PWM5 — Pulse Width Modulator output 5.

AD1.6 — A/D converter 1, input 6. This analog input is always connected to

its pin. Available in LPC2138 only.

I

CAP1.3 — Capture input for Timer 1, channel 3.

9397 750 14868

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8 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

Table 3:

Symbol

Pin description …continued

Type

Description

P0.22/AD1.7/

2^[4]

I

AD1.7 — A/D converter 1, input 7. This analog input is always connected to

CAP0.0/MAT0.0

its pin. Available in LPC2138 only.

I

CAP0.0 — Capture input for Timer 0, channel 0.

MAT0.0 — Match output for Timer 0, channel 0.

General purpose digital input/output pin.

O

I/O

I

P0.23

58^[1]

9^[5]

P0.25/AD0.4/

AOUT

AD0.4 — A/D converter 0, input 4. This analog input is always connected to

its pin.

O

I

AOUT — D/A converter output. Available in LPC2132 and LPC2138 only.

P0.26/AD0.5

10^[4]

11^[4]

AD0.5 — A/D converter 0, input 5. This analog input is always connected to

its pin.

P0.27/AD0.0/

I

AD0.0 — A/D converter 0, input 0. This analog input is always connected to

CAP0.1/MAT0.1

its pin.

I

CAP0.1 — Capture input for Timer 0, channel 1.

MAT0.1 — Match output for Timer 0, channel 1.

O

I

P0.28/AD0.1/

CAP0.2/MAT0.2

13^[4]

14^[4]

15^[4]

17^[6]

AD0.1 — A/D converter 0, input 1. This analog input is always connected to

its pin.

I

CAP0.2 — Capture input for Timer 0, channel 2.

MAT0.2 — Match output for Timer 0, channel 2.

O

I

P0.29/AD0.2/

CAP0.3/MAT0.3

AD0.2 — A/D converter 0, input 2. This analog input is always connected to

its pin.

I

CAP0.3 — Capture input for Timer 0, Channel 3.

MAT0.3 — Match output for Timer 0, channel 3.

O

I

P0.30/AD0.3/

EINT3/CAP0.0

AD0.3 — A/D converter 0, input 3. This analog input is always connected to

its pin.

I

EINT3 — External interrupt 3 input.

I

CAP0.0 — Capture input for Timer 0, channel 0.

General purpose digital output only pin.

P0.31

O

Important: This pin MUST NOT be externally pulled LOW when RESET pin

is LOW or the JTAG port will be disabled.

P1.0 to P1.31

I/O

Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon the pin

function selected via the pin connect block. Pins 0 through 15 of port 1 are not

available.

P1.16/

TRACEPKT0

16^[6]

12^[6]

8^[6]

O

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1.17/

TRACEPKT1

P1.18/

TRACEPKT2

P1.19/

TRACEPKT3

4^[6]

P1.20/

TRACESYNC

48^[6]

TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up. LOW on TRACESYNC while RESET is LOW enables pins P1.25:16

to operate as Trace port after reset.

P1.21/

44^[6]

O

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT0

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

9 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

Table 3:

Symbol

Pin description …continued

Type

Description

P1.22/

PIPESTAT1

40^[6]

O

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.23/

PIPESTAT2

36^[6]

32^[6]

O

P1.24/

TRACECLK

P1.25/EXTIN0 28^[6]

I

P1.26/RTCK

24^[6]

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bi-directional pin with internal pull-up. LOW on RTCK while RESET is LOW

enables pins P1.31:26 to operate as Debug port after reset.

P1.27/TDO

P1.28/TDI

P1.29/TCK

P1.30/TMS

P1.31/TRST

RESET

64^[6]

60^[6]

56^[6]

52^[6]

20^[6]

57^[7]

O

I

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

TCK — Test Clock for JTAG interface.

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

I

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

XTAL2

RTXC1

RTXC2

V_SS

62^[8]

61^[8]

3^[8]

I

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator ampliﬁer.

O

I

Input to the RTC oscillator circuit.

5^[8]

O

I

Output from the RTC oscillator circuit.

Ground: 0 V reference.

6, 18, 25, 42,

50

V_SSA

V_DD

59

I

Analog ground: 0 V reference. This should nominally be the same voltage

as V_SS, but should be isolated to minimize noise and error.

23, 43, 51

7

3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

V_DDA

Analog 3.3 V power supply: This should be nominally the same voltage as

V_DDbut should be isolated to minimize noise and error. This voltage is used

to power the on-chip PLL.

V_REF

63

49

I

A/D converter reference: This should be nominally the same voltage as V_DD

but should be isolated to minimize noise and error. Level on this pin is used as

a reference for A/D and D/A convertor(s).

V_BAT

RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If conﬁgured for an input

function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[3] Open drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If conﬁgured

for an input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When conﬁgured as an ADC input, digital

section of the pad is disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When

conﬁgured as the DAC output, digital section of the pad is disabled.

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[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[7] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[8] Pad provides special analog functionality.

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6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-Chip Flash program memory

The LPC2131/2132/2134/2136/2138 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and

512 kB Flash memory system respectively. This memory may be used for both code and

data storage. Programming of the Flash memory may be accomplished in several ways. It

may be programmed In System via the serial port. The application program may also

erase and/or program the Flash while the application is running, allowing a great degree

of ﬂexibility for data storage ﬁeld ﬁrmware upgrades, etc. When the

LPC2131/2132/2134/2136/2138 on-chip bootloader is used, 32/64/128/256/500 kB of

Flash memory is available for user code.

The LPC2131/2132/2134/2136/2138 Flash memory provides a minimum of 100,000

erase/write cycles and 20 years of data-retention.

6.3 On-Chip static RAM

On-Chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2132/2134/2136/2138 provide

8/16/32 kB of static RAM.

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6.4 Memory map

The LPC2131/2132/2134/2136/2138 memory map incorporates several distinct regions,

as shown in Figure 5.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

Flash memory (the default) or on-chip static RAM. This is described in Section 6.21

“System control”.

4.0 GB

0xFFFF FFFF

AHB PERIPHERALS

0xF000 0000

0xE000 0000

3.75 GB

3.5 GB

VPB PERIPHERALS

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY

RESERVED ADDRESS SPACE

0x4001 8000

0x4000 7FFF

TOTAL OF 32 kB ON-CHIP STATIC RAM (LPC2136/38)

TOTAL OF 16 kB ON-CHIP STATIC RAM (LPC2132/34)

TOTAL OF 8 kB ON-CHIP STATIC RAM (LPC2131)

RESERVED ADDRESS SPACE

0x4000 4000

0x4000 3FFF

0x4000 2000

0x4000 1FFF

1.0 GB

0x4000 0000

0x0008 0000

0x0007 FFFF

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2138)

0x0004 0000

0x0003 FFFF

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2136)

0x0002 0000

0x0001 FFFF

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2134)

0x0001 0000

0x0000 FFFF

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2132)

0x0000 8000

0x0000 7FFF

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2131)

0x0000 0000

0.0 GB

002aab069

Fig 5. LPC2131/2132/2134/2136/2138 memory map.

6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored

IRQ, and non-vectored IRQ as deﬁned by programmable settings. The programmable

assignment scheme means that priorities of interrupts from the various peripherals can be

dynamically assigned and adjusted.

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Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned

to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.

The fastest possible FIQ latency is achieved when only one request is classiﬁed as FIQ,

because then the FIQ service routine can simply start dealing with that device. But if more

than one request is assigned to the FIQ class, the FIQ service routine can read a word

from the VIC that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are requesting, the

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than one

interrupt source.

Table 4:

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

-

Reserved for software interrupts only

Embedded ICE, DbgCommRX

Embedded ICE, DbgCommTX

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

RX Line Status (RLS)

ARM Core

TIMER0

TIMER1

UART0

5

6

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

RX Line Status (RLS)

UART1

7

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI) (Available in

LPC2134/2136/2138 only)

PWM0

I²C0

Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

SI (state change)

8

9

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Table 4:

Block

SPI0

Interrupt sources …continued

Flag(s)

VIC channel #

SPIF, MODF

10

11

SSP

TX FIFO at least half empty (TXRIS)

RX FIFO at least half full (RXRIS)

Receive Timeout (RTRIS)

Receive Overrun (RORRIS)

PLL Lock (PLOCK)

PLL

12

13

14

15

16

17

18

19

20

21

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

A/D Converter 0

AD0

I2C1

BOD

AD1

SI (state change)

Brown Out Detect

A/D Converter 1 (Available in LPC2134/2136/2138 only)

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

The Pin Control Module contains three registers as shown in Table 5.

Table 5:

Pin control module registers

Address

Name

Description

Access

0xE002C000

0xE002C004

0xE002C014

PINSEL0

PINSEL1

PINSEL2

Pin function select register 0

Pin function select register 1

Pin function select register 2

Read/Write

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6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in

Table 6. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions, direction is controlled automatically.

Settings other than those shown in Table 6 are reserved, and should not be used.

Table 6:

Pin function select register 0 (PINSEL0 - 0xE002C000)

PINSEL0

Pin name

Value

Function

Value after

reset

1:0

P0.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO Port 0.0

TXD (UART0)

PWM1

0

Reserved

3:2

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

GPIO Port 0.1

RXD (UART0)

PWM3

EINT0

5:4

GPIO Port 0.2

SCL0 (I²C0)

Capture 0.0 (Timer 0)

Reserved

7:6

GPIO Port 0.3

SDA0 (I²C0)

Match 0.0 (Timer 0)

EINT1

9:8

GPIO Port 0.4

SCK0 (SPI0)

Capture 0.1 (Timer 0)

AD0.6

11:10

13:12

GPIO Port 0.5

MISO0 (SPI0)

Match 0.1 (Timer 0)

AD0.7

GPIO Port 0.6

MOSI0 (SPI0)

Capture 0.2 (Timer 0)

Reserved (LPC2131/32)

AD1.0 (LPC2134/2136/2138)

15:14

P0.7

0

1

0

1

0

1

GPIO Port 0.7

SSEL0 (SPI0)

PWM2

0

EINT2

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Table 6:

Pin function select register 0 (PINSEL0 - 0xE002C000) …continued

PINSEL0

Pin name

Value

Function

Value after

reset

17:16

P0.8

0

1

0

1

0

1

GPIO Port 0.8

TXD UART1

PWM4

0

Reserved (LPC2131/32)

AD1.1 (LPC2134/36/38)

19:18

21:20

P0.9

0

1

0

1

0

1

0

1

GPIO Port 0.9

RXD (UART1)

PWM6

0

EINT3

P0.10

GPIO Port 0.10

Reserved (LPC2131/32)

RTS (UART1) (LPC2134/36/38)

1

0

1

Capture 1.0 (Timer 1)

Reserved (LPC2131/32)

AD1.2 (LPC2134/36/38)

23:22

25:24

P0.11

P0.12

0

1

GPIO Port 0.11

0

Reserved (LPC2131/32)

CTS (UART1) (LPC2134/36/38)

1

0

1

0

1

Capture 1.1 (Timer 1)

SCL1 (I²C1)

GPIO Port 0.12

Reserved (LPC2131/32)

DSR (UART1) (LPC2134/36/38)

1

0

1

Match 1.0 (Timer 1)

Reserved (LPC2131/32)

AD1.3 (LPC2134/36/38)

27:26

P0.13

0

1

GPIO Port 0.13

0

Reserved (LPC2131/32)

DTR (UART1) (LPC2134/36/38)

1

0

1

Match 1.1 (Timer 1)

Reserved (LPC2131/32)

AD1.4 (LPC2138)

29:28

31:30

P0.14

P0.15

0

1

GPIO Port 0.14

0

Reserved (LPC2131/32)

DCD (UART1) (LPC2134/36/38)

1

0

1

0

1

EINT1

SDA1 (I²C1)

GPIO Port 0.15

Reserved (LPC2131/32)

RI (UART1) (LPC2134/36/38)

1

0

1

EINT2

Reserved (LPC2131/32)

AD1.5 (LPC2134/36/38)

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6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)

The PINSEL1 register controls the functions of the pins as per the settings listed in

Table 7. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions direction is controlled automatically.

Settings other than those shown in Table 7 are reserved, and should not be used.

Table 7:

PINSEL1

1:0

Pin function select register 1 (PINSEL1 - 0xE002C004)

Pin Name Value

Function

Value after reset

P0.16

P0.17

P0.18

P0.19

P0.20

P0.21

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

GPIO Port 0.16

EINT0

0

Match 0.2 (Timer 0)

Capture 0.2 (Timer 0)

GPIO Port 0.17

Capture 1.2 (Timer 1)

SCK (SSP)

3:2

0

Match 1.2 (Timer 1)

GPIO Port 0.18

Capture 1.3 (Timer 1)

MISO (SSP)

5:4

Match 1.3 (Timer 1)

GPIO Port 0.19

Match 1.2 (Timer 1)

MOSI (SSP)

7:6

Capture 1.2 (Timer 1)

GPIO Port 0.20

Match 1.3 (Timer 1)

SSEL (SSP)

9:8

EINT3

11:10

GPIO Port 0.21

PWM5

Reserved (LPC2131/32)

AD1.6 (LPC2134/36/38)

1

0

1

0

1

Capture 1.3 (Timer 1)

GPIO Port 0.22

13:12

15:14

P0.22

P0.23

0

Reserved (LPC2131/32)

AD1.7 (LPC2134/36/38)

1

0

1

0

1

0

1

0

1

Capture 0.0 (Timer 0)

Match 0.0 (Timer 0)

GPIO Port 0.23

Reserved

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Table 7:

PINSEL1

17:16

Pin function select register 1 (PINSEL1 - 0xE002C004) …continued

Pin Name Value

Function

Reserved

GPIO Port 0.25

AD0.4

Value after reset

P0.24

0

1

0

1

0

1

0

1

0

1

0

19:18

P0.25

0

Reserved (LPC2131)

AOUT (DAC) (LPC2132/34/36/38)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

21:20

23:22

25:24

27:26

29:28

31:30

P0.26

P0.27

P0.28

P0.29

P0.30

P0.31

GPIO Port 0.26

AD0.5

0

Reserved

GPIO Port 0.27

AD0.0

Capture 0.1 (Timer 0)

Match 0.1 (Timer 0)

GPIO Port 0.28

AD0.1

Capture 0.2 (Timer 0)

Match 0.2 (Timer 0)

GPIO Port 0.29

AD0.2

Capture 0.3 (Timer 0)

Match 0.3 (Timer 0)

GPIO Port 0.30

AD0.3

EINT3

Capture 0.0 (Timer 0)

GPIO Port

Reserved

6.9 Pin function select register 2 (PINSEL2 - 0xE002C014)

The PINSEL2 register controls the functions of the pins as per the settings listed in

Table 8. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions direction is controlled automatically.

Settings other than those shown in Table 8 are reserved, and should not be used.

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Table 8:

Pin function select register 2 (PINSEL2 - 0xE002C014)

PINSEL2 bits

Description

Reset value

1:0

2

Reserved

-

When 0, pins P1.31:26 are GPIO pins. When 1,

P1.31:26 are used as Debug port.

0

3

When 0, pins P1.25:16 are used as GPIO pins. When 1,

P1.25:16 are used as Trace port.

0

-

31:30

Reserved

6.10 General purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.10.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.11 10-bit A/D converter

The LPC2131/32 contain one and the LPC2134/2136/2138 contains two analog to digital

converters. These converters are single 10-bit successive approximation analog to digital

converters with eight multiplexed channels.

6.11.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Global Start command for both converters (LPC2134/2136/2138 only).

6.12 10-bit D/A converter

This peripheral is available in the LPC2132/2134/2136/2138 only. The D/A converter

enables the LPC2132/2134/2136/2138 to generate variable analog output.

6.12.1 Features

• 10 bit digital to analog converter.

• Buffered output.

• Power-down mode available.

• Selectable speed versus power.

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6.13 UARTs

Single-chip 16/32-bit microcontrollers

The LPC2131/2132/2134/2136/2138 each contain two UARTs. In addition to standard

transmit and receive data lines, the LPC2134/2136/2138 UART1 also provides a full

modem control handshake interface.

6.13.1 Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to ‘550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Built-in baud rate generator.

• Standard modem interface signals included on UART1. (LPC2134/2136/2138 only)

• The LPC2131/2132/2134/2136/2138 transmission FIFO control enables

implementation of software (XON/XOFF) ﬂow control on both UARTs and hardware

(CTS/RTS) ﬂow control on the LPC2134/2136/2138 UART1 only.

6.14 I²C-bus serial I/O controller

The LPC2131/2132/2134/2136/2138 each contain two I²C-bus controllers.

The I²C-bus is bi-directional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2131/2132/2134/2136/2138 supports bit rates up to

400 kbit/s (Fast I²C).

6.14.1 Features

• Standard I²C compliant bus interface.

• Easy to conﬁgure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

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6.15 SPI serial I/O controller

The LPC2131/2132/2134/2136/2138 each contain one SPI controller. The SPI is a full

duplex serial interface, designed to be able to handle multiple masters and slaves

connected to a given bus. Only a single master and a single slave can communicate on

the interface during a given data transfer. During a data transfer the master always sends

a byte of data to the slave, and the slave always sends a byte of data to the master.

6.15.1 Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.16 SSP serial I/O controller

The LPC2131/2132/2134/2136/2138 each contain one Serial Synchronous Port controller

(SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus.

It can interact with multiple masters and slaves on the bus. However, only a single master

and a single slave can communicate on the bus during a given data transfer. The SSP

supports full duplex transfers, with frames of 4 bits to 16 bits of data ﬂowing from the

master to the slave and from the slave to the master. Often only one of these data ﬂows

carries meaningful data.

6.16.1 Features

• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire

buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.17 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock, and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

At any given time only one of peripheral’s capture inputs can be selected as an external

event signal source, i.e., timer’s clock. The rate of external events that can be successfully

counted is limited to PCLK/2. In this conﬁguration, unused capture lines can be selected

as regular timer capture inputs.

6.17.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

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• External Event Counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.18 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.18.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T_PCLK× 256 × 4) to (T_PCLK× 2³²× 4) in multiples of

T

_PCLK× 4.

6.19 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.19.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

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• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider

allows ﬁne adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

6.20 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2131/2132/2134/2136/2138. The Timer is

designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts

or perform other actions when speciﬁed timer values occur, based on seven match

registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.20.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

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• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.21 System control

6.21.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz

and with external oscillator up to 50 MHz. The oscillator output frequency is called f_oscand

the ARM processor clock frequency is referred to as CCLK for purposes of rate equations,

etc. f_oscand CCLK are the same value unless the PLL is running and connected. Refer to

Section 6.21.2 “PLL” for additional information.

6.21.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 µs.

6.21.3 Reset and wake-up timer

Reset has two sources on the LPC2131/2132/2134/2136/2138: the RESET pin and

watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter.

Assertion of chip reset by any source starts the wake-up timer (see wake-up timer

description below), causing the internal chip reset to remain asserted until the external

reset is de-asserted, the oscillator is running, a ﬁxed number of clocks have passed, and

the on-chip Flash controller has completed its initialization.

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When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.21.4 Brown-out detector

The LPC2131/2132/2134/2136/2138 include 2-stage monitoring of the voltage on the V_DD

pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the Vectored

Interrupt Controller. This signal can be enabled for interrupt; if not, software can monitor

the signal by reading dedicated register.

The second stage of low-voltage detection asserts reset to inactivate the

LPC2131/2132/2134/2136/2138 when the voltage on the V_DDpins falls below 2.6 V. This

reset prevents alteration of the Flash as operation of the various elements of the chip

would otherwise become unreliable due to low voltage. The BOD circuit maintains this

reset down below 1 V, at which point the POR circuitry maintains the overall reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

6.21.5 Code security

This feature of the LPC2131/2132/2134/2136/2138 allow an application to control whether

it can be debugged or protected from observation.

If after reset on-chip boot-loader detects a valid checksum in Flash and reads

0x87654321 from address 0x1FC in Flash, debugging will be disabled and thus the code

in Flash will be protected from observation. Once debugging is disabled, it can be enabled

only by performing a full chip erase using the ISP.

6.21.6 External interrupt inputs

The LPC2131/2132/2134/2136/2138 include up to nine edge or level sensitive External

Interrupt Inputs as selectable pin functions. When the pins are combined, external events

can be processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake up the processor from Power-down mode.

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6.21.7 Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip

Flash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.21.8 Power Control

The LPC2131/2132/2134/2136/2138 support two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.21.9 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via VPB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the VPB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the VPB

divider control registers reside on the VPB bus), the default condition at reset is for the

VPB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the VPB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.22 Emulation and debugging

The LPC2131/2132/2134/2136/2138 support emulation and debugging via a JTAG serial

port. A trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

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6.22.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

6.22.2 Embedded trace

Since the LPC2131/2132/2134/2136/2138 have signiﬁcant amounts of on-chip memory, it

is not possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell provides real-time trace capability for

deeply embedded processor cores. It outputs information about processor execution to

the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

6.22.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2131/2132/2134/2136/2138 contain a

speciﬁc conﬁguration of RealMonitor software programmed into the on-chip Flash

memory.

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7. Limiting values

Table 9:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). ^[1]

Symbol

V_DD

V_DDA

V_BAT

V_REF

V_IA

Parameter

Conditions

Min

Max

+3.6

4.6

Unit

V

supply voltage, core and external rail

analog 3.3 V pad supply voltage

RTC power supply voltage

−0.5

V

4.6

V

A/D converter reference voltage

analog input voltage on A/D related pins

DC input voltage, 5 V tolerant I/O pins

DC input voltage, other I/O pins

4.6

V

5.1

V

[2] [3]

[2]

V_I

6.0

V

V_I

V_DD

+

V

0.5^[4]

100^[5]

125

I_DD

DC supply current per supply pin

DC ground current per ground pin

storage temperature^[6]

-

mA

°C

I_SS

-

T_stg

−40

P_tot(pack)

total power dissipation

based on package

heat transfer, not

device power

-

1.5

W

consumption

[1] The following applies to the Limiting values:

a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in Section 8 “Static characteristics”and

Section 9 “Dynamic characteristics” of this speciﬁcation is not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Only valid when the V_DDsupply voltage is present.

[4] Not to exceed 4.6 V.

[5] The peak current is limited to 25 times the corresponding maximum current.

[6] Dependent on package type.

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8. Static characteristics

Table 10: DC characteristics

T_a= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ ^[1]

Max

Unit

V_DD

supply voltage, core and

3.0

3.3

3.6

V

external rail

V_DDA

analog 3.3 V pad supply

voltage

2.5

3.3

3.6

V

V_BAT

V_REF

RTC supply voltage

2.0^[2]

3.0

3.3

3.6

V

A/D converter reference

voltage

Standard port pins, RESET, RTCK

I_IL

LOW-state input current

HIGH-state input current

V_I= 0 V; no pull-up

-

3

µA

I_IH

I_OZ

V_I= V_DD; no-pull-down

3-state output leakage

current

V_O= 0 V, V_O= V_DD; no

pull-up/down

I_latch

I/O latch-up current

−(0.5 V_DD) < V < (1.5 V_DD

)

-

100

5.5

mA

V

T_j< 125 °C

[3] [4] [5]

V_I

input voltage

pin conﬁgured to provide a

digital function

0

V_O

output voltage

output active

0

-

V_DD

V

V_IH

V_IL

HIGH-state input voltage

LOW-state input voltage

hysteresis voltage

HIGH-state output voltage^[6]I_OH= −4 mA

LOW-state output voltage ^[6]I_OL= −4 mA

HIGH-state output current^[6]V_OH= V_DD− 0.4 V

LOW-state output current^[6]V_OL= 0.4 V

2.0

-

V

-

0.8

V

V_hys

V_OH

V_OL

I_OH

I_OL

0.4

-

V

V_DD− 0.4

-

V

-

0.4

-

V

−4

4

-

mA

-

I_OHS

HIGH-state short circuit

current^[7]

V_OH= 0 V

−45

I_OLS

LOW-state short circuit

current^[7]

V_OL= V_DDA

-

50

mA

I_pd

I_pu

pull-down current

V_I= 5 V ^[8]

10

−15

0

50

−50

0

150

−85

0

µA

pull-up current (applies to

P1.16 to P1.25)

V_I= 0 V

V_DD< V_I< 5 V ^[8]

I_DD

active mode supply current V_DD= 3.3 V, T_a= 25 °C,

code

while(1){}

executed from FLASH, no

active peripherals

CCLK = 10 MHz

-

10

40

-

mA

CCLK = 60 MHz

(other parameters as above)

Power-down mode

V_DD= 3.3 V, T_a= +25 °C,

V_DD= 3.3 V, T_a= +85 °C

-

60

-

µA

<tbd>

500

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Table 10: DC characteristics …continued

T_a= −40 °C to +85 °C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ ^[1]

Max

Unit

I_BATPower-down mode V_BAT

RTC clock = 32 kHz

(from RTXC pins),

T_a= +25 °C

supply current

V_DD= 3.0 V, V_BAT= 2.5 V

V_DD= 3.0 V, V_BAT= 3.0 V

V_DD= 3.3 V, V_BAT= 3.3 V

V_DD= 3.6 V, V_BAT= 3.6 V

-

14

16

18

20

-

µA

active mode V_BATsupply

current

CCLK = 60 MHz,

PCLK = 15 MHz,

PCLK enabled to RTCK,

RTC clock = 32 kHz

(from RTXC pins),

T_a= +25 °C

V_DD= 3.0 V, V_BAT= 3.0 V

V_DD= 3.3 V, V_BAT= 3.3 V

V_DD= 3.6 V, V_BAT= 3.6 V

-

78

80

82

-

µA

active mode V_BATsupply

current optimized for low

battery consumption

PCLK disabled to RTCK in

the PCONP register,

RTC clock = 32 kHz

(from RTXC pins),

T_a= +25 °C, V_BAT= 3.3 V

CCLK = 6 MHz

CCLK = 25 MHz

CCLK = 50 MHz

CCLK = 60 MHz

-

21

23

27

30

-

µA

I²C-bus pins

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-state input voltage^[9]V_tolis from 4.5 V to 5.5 V

0.7V_tol

-

V

LOW-state input voltage ^[9]

V_tolis from 4.5 V to 5.5 V

-

0.3V_tol

V

hysteresis voltage

V_tolis from 4.5 V to 5.5 V

0.5V_tol

-

V

LOW-state output voltage ^[6]I_OLS= 3 mA

input leakage current to V_SSV_I= V_DD

V_I= 5 V

-

0.4

4

V

2

µA

10

22

Oscillator pins

V_XTAL1XTAL1 input voltages

V_XTAL2XTAL2 output voltages

V_RTXC1RTXC1 input voltages

V_RTXC2RTXC2 output voltages

0

-

1.8

V

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[2] The RTC typically fails when V_BATdrops below 1.6 V.

[3] Including voltage on outputs in 3-state mode.

[4] V_DDsupply voltages must be present.

[5] 3-state outputs go into 3-state mode when V_DDis grounded.

[6] Accounts for 100 mV voltage drop in all supply lines.

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[7] Only allowed for a short time period.

[8] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[9] The input threshold voltage of I²C-bus pins meets the I²C-bus speciﬁcation, so an input voltage below 1.5 V will be recognized as a logic

0 while an input voltage above 3.0 V will be recognized as a logic 1.

Table 11: A/D converter DC electrical characteristics

V_DDA= 2.5 V to 3.6 V; T_a= −40 °C to +85 °C unless otherwise speciﬁed. A/D converter frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

0

-

C_iss

analog input

capacitance

pF

[1] [2]

[3]

E_D

differential

non-linearity

-

±1

LSB

[1] [4]

[1] [5]

[1] [6]

[1] [7]

E_L(adj)

E_O

integral non-linearity

offset error

-

±2

LSB

%

±3

E_G

gain error

±0.5

±4

E_T

absolute error

LSB

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The A/D is monotonic, there are no missing codes.

[3] The differential non-linearity (E_D) is the difference between the actual step width and the ideal step width. See Figure 6.

[4] The integral no-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 6.

[5] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 6.

[6] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 6.

[7] The absolute voltage error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated A/D and the ideal transfer curve. See Figure 6.

9397 750 14868

Preliminary data sheet

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Philips Semiconductors

Single-chip 16/32-bit microcontrollers

gain

error

offset

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

V

− V

SSA

DDA

1 LSB =

offset

error

1024

002aab136

E

O

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential non-linearity (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 6. A/D conversion characteristics.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

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LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

9. Dynamic characteristics

Table 12: AC characteristics

T_a= 0 °C to +70 °C for commercial applications, −40 °C to +85 °C for industrial applications, V_DDover speciﬁed ranges ^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ ^[1]

Max

Unit

oscillator frequency

oscillator clock period

clock HIGH time

clock LOW time

clock rise time

10

40

-

25

100

-

MHz

ns

T_clk

t_CHCX

T

-

_clk× 0.4

ns

t_CLCX

_clk× 0.4

-

ns

t_CLCH

5

ns

t_CHCL

clock fall time

-

5

ns

Port pins (except P0.2 and P0.3)

t_r(O)

t_f(O)

output rise time

-

10

-

ns

output fall time

I²C-bus pins (P0.2 and P0.3)

t_ofoutput fall time

V_IHto V_IL

20 + 0.1 ×

C_b

-

ns

[2]

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance C_bin pF, from 10 pF to 400 pF.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

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Philips Semiconductors

9.1 Timing

Single-chip 16/32-bit microcontrollers

V

DD

− 0.5 V

0.2V

+ 0.9

DD

0.2V

− 0.1 V

DD

0.45 V

t

CHCX

t

CHCL

t

CLCH

CLCX

T

clk

002aab137

Fig 7. External clock timing.

9.2 LPC2138 power consumption measurements

002aab404

40

(1)

(2)

(3)

(4)

(5)

I

current

(mA)

DD

30

20

10

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: code executed from Flash; all peripherals are enabled in PCONP register; PCLK = CCLK/4.

(1) 3.6 V_DDat −60 °C (max)

(2) 3.6 V_DDat 140 °C

(3) 3.6 V_DDat 25 °C

(4) 3.3 V_DDat 25 °C (typical)

(5) 3.3 V_DDat 95 °C (typical)

Fig 8. I_DDactive measured at different frequencies (CCLK) and temperatures.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

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LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

002aab403

15

I

current

DD

(mA)

(1)

(2)

(3)

(4)

(5)

10

5

0

10

20

30

40

50

60

frequency (MHz)

Test conditions: Idle mode entered executing code from Flash; all peripherals are enabled in PCONP register;

PCLK = CCLK/4.

(1) 3.6 V_DDat 140 °C (max)

(2) 3.6 V_DDat −60 °C

(3) 3.6 V_DDat 25 °C

(4) 3.3 V_DDat 25 °C (typical)

(5) 3.3 V_DDat 95 °C (typical)

Fig 9. I_DDidle measured at different frequencies (CCLK) and temperatures.

002aab405

500

I

current

(uA)

(1)

(2)

(3)

(4)

DD

400

300

200

100

0

-60

-20

20

60

100

140

temp (C)

Test conditions: Power-down mode entered executing code from Flash; all peripherals are enabled in PCONP register.

(1) 3.6 V_DD

(2) 3.3 V_DD(max)

(3) 3.0 V_DD

(4) 3.3 V_DD(typical)

Fig 10. I_DDpower-down measured at different temperatures.

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

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LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

10. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 11. Package outline SOT314-2 (LQFP64).

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

37 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

11. Abbreviations

Table 13: Acronym list

Acronym

ADC

Description

Analog-to-Digital Converter

Brown-Out Detection

BOD

CPU

Central Processing Unit

Digital-to-Analog Converter

Debug Communications Channel

First In, First Out

DAC

DCC

FIFO

GPIO

PLL

General Purpose Input/Output

Phase-Locked Loop

POR

PWM

RAM

SRAM

UART

VIC

Power-On Reset

Pulse Width Modulator

Random Access Memory

Static Random Access Memory

Universal Asynchronous Receiver/Transmitter

Vector Interrupt Controller

VLSI Peripheral Bus

VPB

9397 750 14868

Preliminary data sheet

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Single-chip 16/32-bit microcontrollers

12. Revision history

Table 14: Revision history

Document ID

Release

date

Data sheet status Change

notice

Doc. number

Supersedes

LPC2131_32_34_36_38_2 20050415

Preliminary data

sheet

-

9397 750 14868 LPC2131_2132_2138_1

Modiﬁcations:

• Added new devices LPC2134 and LPC2136.

LPC2131_2132_2138_1

20041118

Preliminary data

sheet

-

9397 750 14008

-

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

39 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

13. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

14. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

16. Trademarks

Notice — All referenced brands, product names, service names and

15. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

17. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14868

Preliminary data sheet

Rev. 02 — 15 April 2005

40 of 41

LPC2131/2132/2134/2136/2138

Philips Semiconductors

Single-chip 16/32-bit microcontrollers

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.21.1

6.21.2

6.21.3

6.21.4

6.21.5

6.21.6

6.21.7

6.21.8

6.21.9

6.22

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 25

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset and wake-up timer . . . . . . . . . . . . . . . . 25

Brown-out detector. . . . . . . . . . . . . . . . . . . . . 26

Code security . . . . . . . . . . . . . . . . . . . . . . . . . 26

External interrupt inputs. . . . . . . . . . . . . . . . . 26

Memory Mapping Control. . . . . . . . . . . . . . . . 27

Power Control. . . . . . . . . . . . . . . . . . . . . . . . . 27

VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Emulation and debugging. . . . . . . . . . . . . . . . 27

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 28

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 28

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

2.1

3

3.1

4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.22.1

6.22.2

6.22.3

6

Functional description . . . . . . . . . . . . . . . . . . 12

Architectural overview. . . . . . . . . . . . . . . . . . . 12

On-Chip Flash program memory . . . . . . . . . . 12

On-Chip static RAM . . . . . . . . . . . . . . . . . . . . 12

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 13

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 14

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 15

Pin function select register 0 (PINSEL0 -

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

7

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

Static characteristics . . . . . . . . . . . . . . . . . . . 30

9

9.1

9.2

Dynamic characteristics. . . . . . . . . . . . . . . . . 34

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

LPC2138 power consumption measurements 35

10

11

12

13

14

15

16

17

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 40

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Contact information . . . . . . . . . . . . . . . . . . . . 40

0xE002C000) . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin function select register 1 (PINSEL1 -

0xE002C004) . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin function select register 2 (PINSEL2 -

6.8

6.9

0xE002C014) . . . . . . . . . . . . . . . . . . . . . . . . . 19

General purpose parallel I/O. . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10-bit D/A converter . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I²C-bus serial I/O controller . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SSP serial I/O controller . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

General purpose timers/external event

6.10

6.10.1

6.11

6.11.1

6.12

6.12.1

6.13

6.13.1

6.14

6.14.1

6.15

6.15.1

6.16

6.16.1

6.17

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pulse width modulator . . . . . . . . . . . . . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System control . . . . . . . . . . . . . . . . . . . . . . . . 25

6.17.1

6.18

6.18.1

6.19

6.19.1

6.20

6.20.1

6.21

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 15 April 2005

Document number: 9397 750 14868

Published in the Netherlands


型号：	LPC2134FBD64
厂家：	NXP
描述：	Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC 单芯片16位/ 32位微控制器; 32/64/512 KB ISP / IAP闪存与10位ADC和DAC 闪存微控制器
文件：	总41页 (文件大小：182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2134FBD64 [NXP]

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