LPC2292_07_技术文档

LPC2292/2294

16/32-bit ARM microcontrollers; 256 kB ISP/IAP ﬂash with

CAN, 10-bit ADC and external memory interface

Rev. 06 — 10 December 2007

Product data sheet

1. General description

The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with

real-time emulation and embedded trace support, together with 256 kB of embedded

high-speed ﬂash memory. A 128-bit wide memory interface and a unique accelerator

architecture enable 32-bit code execution at the maximum clock rate. For critical code size

applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with

minimal performance penalty.

With their 144-pin package, low power consumption, various 32-bit timers, 8-channel

10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine

external interrupt pins these microcontrollers are particularly suitable for automotive and

industrial control applications as well as medical systems and fault-tolerant maintenance

buses. The number of available fast GPIOs ranges from 76 (with external memory)

through 112 (single-chip). With a wide range of additional serial communications

interfaces, they are also suited for communication gateways and protocol converters as

well as many other general-purpose applications.

Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with

and without the /00 or /01 sufﬁx. The sufﬁxes /00 and /01 will be used to differentiate from

other devices only when necessary.

2. Features

2.1 Key features brought by LPC2292/2294/01 devices

I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.

They also allow for a port pin to be read at any time regardless of its function.

I Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when conﬁgured for digital I/O function(s).

I UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake ﬂow-control fully implemented in hardware.

I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

I SPI programmable data length and master mode enhancement.

I Diversiﬁed Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2292/2294/00 devices as well.

I General purpose timers can operate as external event counters.

2.2 Key features common for all devices

I 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

I 16 kB on-chip static RAM and 256 kB on-chip ﬂash program memory. 128-bit wide

interface/accelerator enables high-speed 60 MHz operation.

I In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader

software. Single ﬂash sector or full chip erase in 400 ms and programming of 256 B in

1 ms.

I EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software as well as high-speed real-time tracing of instruction

execution.

I Two/four (LPC2292/2294) interconnected CAN interfaces with advanced acceptance

ﬁlters. Additional serial interfaces include two UARTs (16C550), Fast I²C-bus

(400 kbit/s) and two SPIs.

I Eight channel 10-bit ADC with conversion time as low as 2.44 µs.

I Two 32-bit timers (with four capture and four compare channels), PWM unit (six

outputs), Real-Time Clock (RTC), and watchdog.

I Vectored Interrupt Controller (VIC) with conﬁgurable priorities and vector addresses.

I Conﬁgurable external memory interface with up to four banks, each up to 16 MB and

8/16/32-bit data width.

I Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive

external interrupt pins available.

I 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

time of 100 µs.

I On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

I Power saving modes include Idle and Power-down.

I Processor wake-up from Power-down mode via external interrupt.

I Individual enable/disable of peripheral functions for power optimization.

I Dual power supply:

N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).

N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2292FBD144

LQFP144

plastic low proﬁle quad ﬂat package;

SOT486-1

144 leads; body 20 × 20 × 1.4 mm

LPC2292FBD144/00

LPC2292FBD144/01

LPC2292FET144/00

LPC2292FET144/01

LPC2292FET144/G

LQFP144

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

SOT486-1

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

TFBGA144 plastic thin ﬁne-pitch ball grid array package; SOT569-1

144 balls; body 12 × 12 × 0.8 mm

TFBGA144 plastic thin ﬁne-pitch ball grid array package; SOT569-1

144 balls; body 12 × 12 × 0.8 mm

TFBGA144 plastic thin ﬁne-pitch ball grid array package; SOT569-1

144 balls; body 12 × 12 × 0.8 mm

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

2 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 1.

Ordering information …continued

Type number

Package

Name

Description

Version

LPC2294HBD144

LQFP144

plastic low proﬁle quad ﬂat package;

SOT486-1

144 leads; body 20 × 20 × 1.4 mm

LPC2294HBD144/00

LPC2294HBD144/01

LQFP144

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

SOT486-1

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash

memory

RAM

CAN

Fast GPIO/

SSP/

Temperature range

Enhanced

UART, ADC,

Timer

LPC2292FBD144

256 kB

16 kB

2 channels no

2 channels yes

2 channels no

2 channels yes

2 channels no

4 channels no

4 channels yes

−40 °C to +85 °C

−40 °C to +125 °C

LPC2292FBD144/00 256 kB

LPC2292FBD144/01 256 kB

LPC2292FET144/00 256 kB

LPC2292FET144/01 256 kB

LPC2292FET144/G 256 kB

LPC2294HBD144

256 kB

LPC2294HBD144/00 256 kB

LPC2294HBD144/01 256 kB

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

3 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

4. Block diagram

(1)

TMS

(1)

TDI

(1)

XTAL2

XTAL1 RST

(1)

TRST

TCK

TDO

LPC2292

LPC2294

TEST/DEBUG

INTERFACE

SYSTEM

FUNCTIONS

PLL

ARM7TDMI-S

HIGH-SPEED

GPI/O

112 PINS TOTAL

system

clock

P0, P1,

P2, P3

(4)

VECTORED

INTERRUPT

CONTROLLER

AHB BRIDGE

AMBA AHB

(Advanced High-performance Bus)

ARM7 local bus

INTERNAL

SRAM

INTERNAL

FLASH

CONTROLLER

AHB

DECODER

(2)

16 kB

SRAM

256 kB

FLASH

CS3 to CS0

(2)

AHB TO APB

BRIDGE

APB

DIVIDER

A23 to A0

EXTERNAL MEMORY

CONTROLLER

(2)

BLS3 to BLS0

(2)

OE, WE

APB (advanced

peripheral bus)

EXTERNAL

(2)

D31 to D0

EINT3 to EINT0

INTERRUPTS

SCL

SDA

2

I C-BUS SERIAL

INTERFACE

4 × CAP0

4 × CAP1

4 × MAT0

4 × MAT1

CAPTURE/

COMPARE

TIMER 0/TIMER 1

SCK1

MOSI1

MISO1

SSEL1

(4)

SPI1/SSP

SERIAL INTERFACE

AIN3 to AIN0

AIN7 to AIN4

A/D CONVERTER

SCK0

SPI0

MOSI0

MISO0

SSEL0

SERIAL INTERFACE

P0[30:0]

P1[31:16], P1[1:0]

P2[31:0]

GENERAL

PURPOSE I/O

TXD0, TXD1

RXD0, RXD1

P3[31:0]

UART0/UART1

DSR1, CTS1,

DCD1, RI1

PWM6 to PWM1

PWM0

TD2, TD1

RD2, RD1

TD4, TD3

CAN

(3)

REAL-TIME CLOCK

SYSTEM CONTROL

(3)

RD4, RD3

WATCHDOG

TIMER

002aad184

(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(2) Pins shared with GPIO.

(3) Available in LPC2294 only.

(4) SSP interface and high-speed GPIO are available on LPC2292/2294/01 only.

Fig 1. Block diagram

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

4 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

5. Pinning information

5.1 Pinning

1

108

LPC2292FBD

LPC2294HBD⁽¹⁾

36

73

002aad185

(1) Pin conﬁguration is identical for devices with and without /00 and /01 sufﬁxes.

Fig 2. LQFP144 pinning

ball A1

index area

LPC2292FET144⁽¹⁾

1

2 3 4 5 6 7 8 9 10 11 12 13

A

B

C

D

E

F

G

H

J

K

L

M

N

002aad191

Transparent top view

(1) Pin conﬁguration is identical for devices with and without /00 and /01 sufﬁxes.

Fig 3. TFBGA144 pinning

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

5 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

5.2 Pin description

Table 4.

Symbol

Pin description

Pin (LQFP)

(TFBGA)^[1]

Type

Description

P0[0] to P0[31]

I/O

Port 0: Port 0 is a 32-bit bidirectional I/O port with individual

direction controls for each bit. The operation of port 0 pins

depends upon the pin function selected via the Pin Connect

Block.

Pins 26 and 31 of port 0 are not available.

TXD0 — Transmitter output for UART0.

PWM1 — Pulse Width Modulator output 1.

RXD0 — Receiver input for UART0.

P0[0]/TXD0/

PWM1

42^[2]

49^[4]

L4^[2]

K6^[4]

O

I

P0[1]/RXD0/

PWM3/EINT0

O

I

PWM3 — Pulse Width Modulator output 3.

EINT0 — External interrupt 0 input

P0[2]/SCL/

CAP0[0]

50^[5]

58^[5]

L6^[5]

I/O

SCL — I²C-bus clock input/output. Open-drain output (for

I²C-bus compliance).

I

CAP0[0] — Capture input for Timer 0, channel 0.

SDA — I²C-bus data input/output. Open-drain output (for

I²C-bus compliance).

P0[3]/SDA/

MAT0[0]/EINT1

M8^[5]

I/O

O

I

MAT0[0] — Match output for Timer 0, channel 0.

EINT1 — External interrupt 1 input.

P0[4]/SCK0/

CAP0[1]

59^[2]

61^[2]

68^[2]

69^[4]

L8^[2]

I/O

SCK0 — Serial clock for SPI0. SPI clock output from master

or input to slave.

I

CAP0[1] — Capture input for Timer 0, channel 1.

P0[5]/MISO0/

MAT0[1]

N9^[2]

I/O

MISO0 — Master In Slave OUT for SPI0. Data input to SPI

master or data output from SPI slave.

O

MAT0[1] — Match output for Timer 0, channel 1.

P0[6]/MOSI0/

CAP0[2]

N11^[2]

M11^[4]

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI

master or data input to SPI slave.

I

CAP0[2] — Capture input for Timer 0, channel 2.

P0[7]/SSEL0/

PWM2/EINT2

SSEL0 — Slave Select for SPI0. Selects the SPI interface as

a slave.

O

I

PWM2 — Pulse Width Modulator output 2.

EINT2 — External interrupt 2 input.

P0[8]/TXD1/

PWM4

75^[2]

76^[4]

L12^[2]

L13^[4]

O

I

TXD1 — Transmitter output for UART1.

PWM4 — Pulse Width Modulator output 4.

RXD1 — Receiver input for UART1.

P0[9]/RXD1/

PWM6/EINT3

O

I

PWM6 — Pulse Width Modulator output 6.

EINT3 — External interrupt 3 input.

P0[10]/RTS1/

CAP1[0]

78^[2]

83^[2]

K11^[2]

J12^[2]

O

I

RTS1 — Request to Send output for UART1.

CAP1[0] — Capture input for Timer 1, channel 0.

CTS1 — Clear to Send input for UART1.

CAP1[1] — Capture input for Timer 1, channel 1.

P0[11]/CTS1/

CAP1[1]

I

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

8 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

Description

P0[12]/DSR1/

MAT1[0]/RD4

84^[2]

J13^[2]

H10^[2]

G10^[4]

I

DSR1 — Data Set Ready input for UART1.

MAT1[0] — Match output for Timer 1, channel 0.

RD4 — CAN4 receiver input (LPC2294 only).

DTR1 — Data Terminal Ready output for UART1.

MAT1[1] — Match output for Timer 1, channel 1.

TD4 — CAN4 transmitter output (LPC2294 only).

DCD1 — Data Carrier Detect input for UART1.

EINT1 — External interrupt 1 input.

O

I

P0[13]/DTR1/

MAT1[1]/TD4

85^[2]

O

I

P0[14]/DCD1/

EINT1

92^[4]

I

Note: LOW on this pin while RESET is LOW forces on-chip

bootloader to take over control of the part after reset.

P0[15]/RI1/

EINT2

99^[4]

E11^[4]

E10^[4]

I

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

P0[16]/EINT0/

MAT0[2]/

CAP0[2]

100^[4]

I

EINT0 — External interrupt 0 input.

O

MAT0[2] — Match output for Timer 0, channel 2.

CAP0[2] — Capture input for Timer 0, channel 2.

CAP1[2] — Capture input for Timer 1, channel 2.

SCK1 — Serial Clock for SPI1/SSP^[3]. SPI clock output from

master or input to slave.

I

P0[17]/CAP1[2]/ 101^[2]

SCK1/MAT1[2]

D13^[2]

D8^[2]

C8^[2]

B8^[4]

I

I/O

O

I

MAT1[2] — Match output for Timer 1, channel 2.

CAP1[3] — Capture input for Timer 1, channel 3.

MISO1 — Master In Slave Out for SPI1/SSP^[3]. Data input to

P0[18]/CAP1[3]/ 121^[2]

MISO1/MAT1[3]

I/O

SPI master or data output from SPI slave.

O

MAT1[3] — Match output for Timer 1, channel 3.

MAT1[2] — Match output for Timer 1, channel 2.

MOSI1 — Master Out Slave In for SPI1/SSP^[3]. Data output

P0[19]/MAT1[2]/ 122^[2]

MOSI1/CAP1[2]

O

I/O

from SPI master or data input to SPI slave.

I

CAP1[2] — Capture input for Timer 1, channel 2.

MAT1[3] — Match output for Timer 1, channel 3.

SSEL1 — Slave Select for SPI1/SSP^[3]. Selects the SPI

P0[20]/MAT1[3]/ 123^[4]

SSEL1/EINT3

O

I

interface as a slave.

I

EINT3 — External interrupt 3 input.

P0[21]/PWM5/ 4^[2]

RD3/CAP1[3]

C1^[2]

D4^[2]

O

I

PWM5 — Pulse Width Modulator output 5.

RD3 — CAN3 receiver input (LPC2294 only).

CAP1[3] — Capture input for Timer 1, channel 3.

TD3 — CAN3 transmitter output (LPC2294 only).

CAP0[0] — Capture input for Timer 0, channel 0.

MAT0[0] — Match output for Timer 0, channel 0.

RD2 — CAN2 receiver input.

I

P0[22]/TD3/

CAP0[0]/

MAT0[0]

5^[2]

O

I

O

I

P0[23]/RD2

P0[24]/TD2

P0[25]/RD1

6^[2]

8^[2]

21^[2]

D3^[2]

D1^[2]

H1^[2]

O

I

TD2 — CAN2 transmitter output.

RD1 — CAN1 receiver input.

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

9 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

Description

P0[27]/AIN0/

CAP0[1]/

MAT0[1]

23^[6]

H3^[6]

J1^[6]

L1^[6]

L2^[6]

I

AIN0 — ADC, input 0. This analog input is always connected

to its pin.

I

CAP0[1] — Capture input for Timer 0, channel 1.

MAT0[1] — Match output for Timer 0, channel 1.

O

I

P0[28]/AIN1/

CAP0[2]/

MAT0[2]

25^[6]

32^[6]

33^[6]

AIN1 — ADC, input 1. This analog input is always connected

to its pin.

I

CAP0[2] — Capture input for Timer 0, channel 2.

MAT0[2] — Match output for Timer 0, channel 2.

O

I

P0[29]/AIN2/

CAP0[3]/

MAT0[3]

AIN2 — ADC, input 2. This analog input is always connected

to its pin.

I

CAP0[3] — Capture input for Timer 0, Channel 3.

MAT0[3] — Match output for Timer 0, channel 3.

O

I

P0[30]/AIN3/

AIN3 — ADC, input 3. This analog input is always connected

EINT3/CAP0[0]

to its pin.

I

EINT3 — External interrupt 3 input.

I

CAP0[0] — Capture input for Timer 0, channel 0.

P1[0] to P1[31]

I/O

Port 1: Port 1 is a 32-bit bidirectional I/O port with individual

direction controls for each bit. The operation of port 1 pins

depends upon the pin function selected via the Pin Connect

Block.

Pins 2 through 15 of port 1 are not available.

CS0 — LOW-active Chip Select 0 signal.

P1[0]/CS0

P1[1]/OE

91^[7]

G11^[7]

O

(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)

OE — LOW-active Output Enable signal.

90^[7]

34^[7]

G13^[7]

L3^[7]

O

P1[16]/

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with

TRACEPKT0

internal pull-up.

P1[17]/

TRACEPKT1

24^[7]

15^[7]

7^[7]

H4^[7]

F2^[7]

O

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with

internal pull-up.

P1[18]/

TRACEPKT2

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with

internal pull-up.

P1[19]/

TRACEPKT3

D2^[7]

D12^[7]

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with

internal pull-up.

P1[20]/

102^[7]

TRACESYNC — Trace Synchronization. Standard I/O port

TRACESYNC

with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins

P1[25:16] to operate as Trace port after reset.

P1[21]/

PIPESTAT0

95^[7]

86^[7]

82^[7]

70^[7]

F11^[7]

H11^[7]

J11^[7]

L11^[7]

O

PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with

internal pull-up.

P1[22]/

PIPESTAT1

PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with

internal pull-up.

P1[23]/

PIPESTAT2

PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with

internal pull-up.

P1[24]/

TRACECLK — Trace Clock. Standard I/O port with internal

TRACECLK

pull-up.

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

10 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

I

Description

P1[25]/EXTIN0 60^[7]

K8^[7]

N6^[7]

EXTIN0 — External Trigger Input. Standard I/O with internal

pull-up.

P1[26]/RTCK

52^[7]

I/O

RTCK — Returned Test Clock output. Extra signal added to

the JTAG port. Assists debugger synchronization when

processor frequency varies. Bidirectional pin with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins

P1[31:26] to operate as Debug port after reset.

P1[27]/TDO

P1[28]/TDI

P1[29]/TCK

144^[7]

140^[7]

126^[7]

B2^[7]

A3^[7]

A7^[7]

O

I

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

I

TCK — Test Clock for JTAG interface. This clock must be

slower than ¹⁄₆of the CPU clock (CCLK) for the JTAG interface

to operate.

P1[30]/TMS

113^[7]

43^[7]

D10^[7]

M4^[7]

I

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

P1[31]/TRST

P2[0] to P2[31]

I

I/O

Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual

direction controls for each bit. The operation of port 2 pins

depends upon the pin function selected via the Pin Connect

Block.

P2[0]/D0

98^[7]

E12^[7]

C12^[7]

C11^[7]

B12^[7]

A13^[7]

C10^[7]

B10^[7]

A10^[7]

D9^[7]

C9^[7]

A9^[7]

A8^[7]

B7^[7]

C7^[7]

A6^[7]

B6^[7]

I/O

D0 — External memory data line 0.

D1 — External memory data line 1.

D2 — External memory data line 2.

D3 — External memory data line 3.

D4 — External memory data line 4.

D5 — External memory data line 5.

D6 — External memory data line 6.

D7 — External memory data line 7.

D8 — External memory data line 8.

D9 — External memory data line 9.

D10 — External memory data line 10.

D11 — External memory data line 11.

D12 — External memory data line 12.

D13 — External memory data line 13.

D14 — External memory data line 14.

D15 — External memory data line 15.

D16 — External memory data line 16.

D17 — External memory data line 17.

D18 — External memory data line 18.

D19 — External memory data line 19.

D20 — External memory data line 20.

D21 — External memory data line 21.

D22 — External memory data line 22.

D23 — External memory data line 23.

P2[1]/D1

105^[7]

106^[7]

108^[7]

109^[7]

114^[7]

115^[7]

116^[7]

117^[7]

118^[7]

120^[7]

124^[7]

125^[7]

127^[7]

129^[7]

130^[7]

131^[7]

132^[7]

133^[7]

134^[7]

136^[7]

137^[7]

1^[7]

P2[2]/D2

P2[3]/D3

P2[4]/D4

P2[5]/D5

P2[6]/D6

P2[7]/D7

P2[8]/D8

P2[9]/D9

P2[10]/D10

P2[11]/D11

P2[12]/D12

P2[13]/D13

P2[14]/D14

P2[15]/D15

P2[16]/D16

P2[17]/D17

P2[18]/D18

P2[19]/D19

P2[20]/D20

P2[21]/D21

P2[22]/D22

P2[23]/D23

C6^[7]

D6^[7]

A5^[7]

B5^[7]

D5^[7]

A4^[7]

A1^[7]

E3^[7]

10^[7]

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

11 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

Description

P2[24]/D24

P2[25]/D25

11^[7]

12^[7]

13^[7]

E2^[7]

E1^[7]

F4^[7]

I/O

I

D24 — External memory data line 24.

D25 — External memory data line 25.

D26 — External memory data line 26.

P2[26]/D26/

BOOT0

BOOT0 — While RESET is low, together with BOOT1 controls

booting and internal operation. Internal pull-up ensures high

state if pin is left unconnected.

P2[27]/D27/

BOOT1

16^[7]

F1^[7]

I/O

I

D27 — External memory data line 27.

BOOT1 — While RESET is low, together with BOOT0 controls

booting and internal operation. Internal pull-up ensures high

state if pin is left unconnected.

BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.

BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.

BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.

BOOT1:0 = 11 selects internal ﬂash memory.

D28 — External memory data line 28.

P2[28]/D28

P2[29]/D29

17^[7]

18^[7]

19^[4]

G2^[7]

G1^[7]

G3^[4]

I/O

I

D29 — External memory data line 29.

P2[30]/D30/

AIN4

D30 — External memory data line 30.

AIN4 — ADC, input 4. This analog input is always connected

to its pin.

P2[31]/D31/

AIN5

20^[4]

G4^[4]

I/O

I

D31 — External memory data line 31.

AIN5 — ADC, input 5. This analog input is always connected

to its pin.

P3[0] to P3[31]

I/O

Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual

direction controls for each bit. The operation of port 3 pins

depends upon the pin function selected via the Pin Connect

Block.

P3[0]/A0

89^[7]

88^[7]

87^[7]

81^[7]

80^[7]

74^[7]

73^[7]

72^[7]

71^[7]

66^[7]

65^[7]

64^[7]

63^[7]

62^[7]

56^[7]

55^[7]

53^[7]

G12^[7]

H13^[7]

H12^[7]

J10^[7]

K13^[7]

M13^[7]

N13^[7]

M12^[7]

N12^[7]

M10^[7]

N10^[7]

K9^[7]

O

A0 — External memory address line 0.

A1 — External memory address line 1.

A2 — External memory address line 2.

A3 — External memory address line 3.

A4 — External memory address line 4.

A5 — External memory address line 5.

A6 — External memory address line 6.

A7 — External memory address line 7.

A8 — External memory address line 8.

A9 — External memory address line 9.

A10 — External memory address line 10.

A11 — External memory address line 11.

A12 — External memory address line 12.

A13 — External memory address line 13.

A14 — External memory address line 14.

A15 — External memory address line 15.

A16 — External memory address line 16.

P3[1]/A1

P3[2]/A2

P3[3]/A3

P3[4]/A4

P3[5]/A5

P3[6]/A6

P3[7]/A7

P3[8]/A8

P3[9]/A9

P3[10]/A10

P3[11]/A11

P3[12]/A12

P3[13]/A13

P3[14]/A14

P3[15]/A15

P3[16]/A16

L9^[7]

M9^[7]

K7^[7]

L7^[7]

M7^[7]

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

12 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

Description

P3[17]/A17

P3[18]/A18

P3[19]/A19

P3[20]/A20

P3[21]/A21

P3[22]/A22

48^[7]

47^[7]

46^[7]

45^[7]

44^[7]

41^[7]

40^[7]

N5^[7]

M5^[7]

L5^[7]

K5^[7]

N4^[7]

K4^[7]

N3^[7]

O

I/O

O

A17 — External memory address line 17.

A18 — External memory address line 18.

A19 — External memory address line 19.

A20 — External memory address line 20.

A21 — External memory address line 21.

A22 — External memory address line 22.

A23 — External memory address line 23.

XCLK — Clock output.

P3[23]/A23/

XCLK

P3[24]/CS3

P3[25]/CS2

P3[26]/CS1

P3[27]/WE

36^[7]

35^[7]

30^[7]

M2^[7]

M1^[7]

K2^[7]

CS3 — LOW-active Chip Select 3 signal.

(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)

CS2 — LOW-active Chip Select 2 signal.

(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)

CS1 — LOW-active Chip Select 1 signal.

(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)

WE — LOW-active Write enable signal.

O

29^[7]

28^[4]

K1^[7]

J4^[4]

O

I

P3[28]/BLS3/

AIN7

BLS3 — LOW-active Byte Lane Select signal (Bank 3).

AIN7 — ADC, input 7. This analog input is always connected

to its pin.

P3[29]/BLS2/

AIN6

27^[6]

J3^[6]

O

I

BLS2 — LOW-active Byte Lane Select signal (Bank 2).

AIN6 — ADC, input 6. This analog input is always connected

to its pin.

P3[30]/BLS1

P3[31]/BLS0

TD1

97^[6]

96^[6]

22^[7]

135^[8]

E13^[6]

F10^[6]

H2^[7]

O

I

BLS1 — LOW-active Byte Lane Select signal (Bank 1).

BLS0 — LOW-active Byte Lane Select signal (Bank 0).

TD1: CAN1 transmitter output.

RESET

C5^[8]

External Reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0. TTL

with hysteresis, 5 V tolerant.

XTAL1

142^[9]

141^[9]

C3^[9]

B3^[9]

I

Input to the oscillator circuit and internal clock generator

circuits.

XTAL2

V_SS

O

I

Output from the oscillator ampliﬁer.

3, 9, 26, 38, C2, E4, J2,

54, 67, 79, N2, N7, L10,

93, 103, 107, K12, F13,

Ground: 0 V reference.

111, 128

D11, B13,

B11, D7

V_SSA

139

C4

I

Analog ground: 0 V reference. This should nominally be the

same voltage as V_SS, but should be isolated to minimize noise

and error.

V_SSA(PLL)

138

B4

PLL analog ground: 0 V reference. This should nominally be

the same voltage as V_SS, but should be isolated to minimize

noise and error.

V_DD(1V8)

37, 110

N1, A12

1.8 V core power supply: This is the power supply voltage

for internal circuitry.

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

13 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Pin (LQFP)

(TFBGA)^[1]

Type

Description

V_DDA(1V8)

143

A2

I

Analog 1.8 V core power supply: This is the power supply

voltage for internal circuitry. This should be nominally the

same voltage as V_DD(1V8)but should be isolated to minimize

noise and error.

V_DD(3V3)

2, 31, 39, 51, B1, K3, M3,

57, 77, 94, M6, N8, K10,

104, 112, 119 F12, C13,

A11, B9

I

3.3 V pad power supply: This is the power supply voltage for

the I/O ports.

V_DDA(3V3)

14

F3

Analog 3.3 V pad power supply: This should be nominally

the same voltage as V_DD(3V3)but should be isolated to

minimize noise and error.

[1] LPC2294 only.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[3] SSP interface available on LPC2292/2294/01 only.

[4] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If conﬁgured for an input

function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns.

[5] Open drain 5 V tolerant digital I/O I²C-bus 400 kHz speciﬁcation compatible pad. It requires external pull-up to provide an output

functionality.

[6] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If conﬁgured

for a digital input function, this pad utilizes built-in glitch ﬁlter that blocks pulses shorter than 3 ns. When conﬁgured as an ADC input,

digital section of the pad is disabled.

[7] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[9] Pad provides special analog functionality.

LPC2292_2294_6

Product data sheet

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14 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on RISC

principles, and the instruction set and related decode mechanism are much simpler than

those of microprogrammed CISC. This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set

• A 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip ﬂash program memory

The LPC2292/2294 incorporate a 256 kB ﬂash memory system respectively. This memory

may be used for both code and data storage. Programming of the ﬂash memory may be

accomplished in several ways. It may be programmed In System via the serial port. The

application program may also erase and/or program the ﬂash while the application is

running, allowing a great degree of ﬂexibility for data storage ﬁeld ﬁrmware upgrades, etc.

When the on-chip bootloader is used, 248 kB of ﬂash memory is available for user code.

The LPC2292/2294 ﬂash memory provides a minimum of 100000 erase/write cycles and

20 years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2292/2294 on-chip ﬂash memory. When the CRP is enabled, the JTAG debug port,

external memory boot and ISP commands accessing either the on-chip RAM or ﬂash

memory are disabled. However, the ISP ﬂash erase command can be executed at any

time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of

full on-chip user ﬂash. With the CRP off, full access to the chip via the JTAG and/or ISP is

restored.

LPC2292_2294_6

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LPC2292/LPC2294

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16/32-bit ARM microcontrollers with external memory interface

6.3 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed

as 8-bit, 16-bit, and 32-bit. The LPC2292/2294 provide 16 kB of SRAM.

6.4 Memory map

The LPC2292/2294 memory maps incorporate several distinct regions, as shown in

Figure 4.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.19

“System control”.

4.0 GB

3.75 GB

3.5 GB

0xFFFF FFFF

AHB PERIPHERALS

APB PERIPHERALS

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xDFFF FFFF

0xC000 0000

3.0 GB

RESERVED ADDRESS SPACE

0x8000 0000

0x7FFF FFFF

2.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

0x7FFF E000

0x7FFF DFFF

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

1.0 GB

RESERVED ADDRESS SPACE

0x0004 0000

0x0003 FFFF

256 kB ON-CHIP FLASH MEMORY

0x0000 0000

0.0 GB

002aaa754

Fig 4. LPC2292/2294 memory map

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LPC2292/LPC2294

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16/32-bit ARM microcontrollers with external memory interface

6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt

Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as deﬁned by

programmable settings. The programmable assignment scheme means that priorities of

interrupts from the various peripherals can be dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are requesting, the

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the VIC, but may have several internal interrupt ﬂags.

Individual interrupt ﬂags may also represent more than one interrupt source.

Table 5.

Block

Interrupt sources

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

0

1

2

3

4

-

Reserved for software interrupts only

EmbeddedICE, DbgCommRx

ARM Core

Timer 0

EmbeddedICE, DbgCommTx

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

RX Line Status (RLS)

Timer 1

UART0

5

6

Transmit Holding Register Empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

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LPC2292/LPC2294

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16/32-bit ARM microcontrollers with external memory interface

Table 5.

Interrupt sources …continued

Block

Flag(s)

VIC channel #

UART1

RX Line Status (RLS)

7

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

SI (state change)

PWM0

I2C

8

9

SPI0

SPIF, MODF

10

SPI1 and SSP^[1]SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS

11

PLL

PLL Lock (PLOCK)

12

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

13

System Control External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

14

15

External Interrupt 2 (EINT2)

16

External Interrupt 3 (EINT3)

17

ADC

CAN

ADC

18

1 ORed CAN Acceptance Filter

CAN1 (TX int, RX int)

19

20, 21

22, 23

24, 25

26, 27

CAN2 (TX int, RX int)

CAN3 (TX int, RX int) - LPC2294 only

CAN4 (TX int, RX int) - LPC2294 only

[1] SSP interface available on LPC2292/2294/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.7 External memory controller

The external Static Memory Controller is a module which provides an interface between

the system bus and external (off-chip) memory devices. It provides support for up to four

independently conﬁgurable memory banks (16 MB each with byte lane enable control)

simultaneously. Each memory bank is capable of supporting SRAM, ROM, ﬂash EPROM,

burst ROM memory, or some external I/O devices.

Each memory bank may be 8-bit, 16-bit, or 32-bit wide.

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LPC2292/LPC2294

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16/32-bit ARM microcontrollers with external memory interface

6.8 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.8.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8.2 Features added with the Fast GPIO set of registers available on

LPC2292/2294/01 only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All Fast GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

6.9 10-bit ADC

The LPC2292/2294 each contain a single 10-bit successive approximation ADC with four

multiplexed channels.

6.9.1 Features

• Measurement range of 0 V to 3 V.

• Capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.9.2 ADC features available in LPC2292/2294/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

• The ADC pads are 5 V tolerant when conﬁgured for digital I/O function(s).

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LPC2292/LPC2294

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16/32-bit ARM microcontrollers with external memory interface

6.10 CAN controllers and acceptance ﬁlter

The LPC2292/2294 each contain two/four CAN controllers. The CAN is a serial

communications protocol which efﬁciently supports distributed real-time control with a

very high level of security. Its domain of application ranges from high-speed networks to

low cost multiplex wiring.

6.10.1 Features

• Data rates up to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN speciﬁcation 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit RX identiﬁers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard identiﬁers.

6.11 UARTs

The LPC2292/2294 each contain two UARTs. In addition to standard transmit and receive

data lines, the UART1 also provides a full modem control handshake interface.

6.11.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs.

• UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware ﬂow control (auto-CTS/RTS).

6.11.2 UART features available in LPC2292/2294/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2292/2294/01 introduce

a fractional baud rate generator for both UARTs, enabling these microcontrollers to

achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz.

In addition, auto-CTS/RTS ﬂow-control functions are fully implemented in hardware.

• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

• Auto-bauding.

• Auto-CTS/RTS ﬂow-control fully implemented in hardware.

6.12 I²C-bus serial I/O controller

The I²C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

LPC2292_2294_6

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16/32-bit ARM microcontrollers with external memory interface

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I²C-bus implemented in LPC2292/2294 supports bit rate up to 400 kbit/s (Fast

I²C-bus).

6.12.1 Features

• Compliant with standard I²C-bus interface.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

6.13 SPI serial I/O controller

The LPC2292/2294 each contain two SPIs. The SPI is a full duplex serial interface,

designed to be able to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

6.13.1 Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

• Maximum data bit rate of ¹⁄₈of the input clock rate.

6.13.2 Features available in LPC2292/2294/01 only

• Eight to 16 bits per frame.

• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).

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6.14 SSP controller (LPC2292/94/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. Application can switch on the

ﬂy from SPI1 to SSP and back.

6.14.1 Features

• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four to 16 bits per frame.

6.15 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.15.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Timer or external event counter operation

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

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6.15.2 Features available in LPC2292/2294/01 only

The LPC2292/2294/01 can count external events on one of the capture inputs if the

external pulse lasts at least one half of the period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

• When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter

than 1 / (2PCLK).

6.16 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (T_cy(PCLK)× 256 × 4) to (T_cy(PCLK)× 2³²× 4) in multiples of

T

_cy(PCLK)× 4.

6.17 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.17.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.

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6.18 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2292/2294. The Timer is designed to

count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform

other actions when speciﬁed timer values occur, based on seven match registers. The

PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.18.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

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• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

6.19 System control

6.19.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called f_oscand the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. f_oscand CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.19.2 “PLL” for additional information.

6.19.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 µs.

6.19.3 Reset and wake-up timer

Reset has two sources on the LPC2292/2294: the RESET pin and watchdog reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip

reset by any source starts the Wake-up Timer (see Wake-up Timer description below),

causing the internal chip reset to remain asserted until the external reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power-on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

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The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of V_DDramp (in the case of power-on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.19.4 Code security (Code Read Protection - CRP)

This feature of the LPC2292/2294/01 allows the user to enable different levels of security

in the system so that access to the on-chip ﬂash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It

is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP

calls or call reinvoke ISP command to enable ﬂash update via UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Remark: Devices without a /00 or /01 in the name have only a security level equivalent to

CRP2 available.

6.19.5 External interrupt inputs

The LPC2292/2294 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

6.19.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

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6.19.7 Power control

The LPC2292/2294 support two reduced power modes: Idle mode and Power-down

mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates power used

by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode, and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.19.8 APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the APB bus may be

slowed down to ¹⁄₂to ¹⁄₄of the processor clock rate. Because the APB bus must work

properly at power-up (and its timing cannot be altered if it does not work since the APB

divider control registers reside on the APB bus), the default condition at reset is for the

APB bus to run at ¹⁄₄of the processor clock rate. The second purpose of the APB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the APB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

6.20 Emulation and debugging

The LPC2292/2294 support emulation and debugging via a JTAG serial port. A trace port

allows tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on Port 1. This means that all communication, timer and interface peripherals

residing on Port 0 are available during the development and debugging phase as they are

when the application is run in the embedded system itself.

6.20.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote

debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

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communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than ¹⁄₆of the CPU clock (CCLK) for the JTAG

interface to operate.

6.20.2 Embedded trace

Since the LPC2292/2294 have signiﬁcant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the trace

port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code cannot be traced

because of this restriction.

6.20.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the Debug

Communications Channel (DCC), which is present in the EmbeddedICE logic. The

LPC2292/2294 contain a speciﬁc conﬁguration of RealMonitor software programmed into

the on-chip ﬂash memory.

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7. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD(1V8)

V_DD(3V3)

V_DDA(3V3)

V_IA

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

[2]

[3]

supply voltage (1.8 V)

supply voltage (3.3 V)

analog supply voltage (3.3 V)

analog input voltage

input voltage

+2.5

+3.6

V

+4.6

V

+5.1

V

[4][5]

[4][6]

[7][8]

[8][9]

V_I

5 V tolerant I/O pins

other I/O pins

+6.0

V

V_DD(3V3)+ 0.5

100

V

I_DD

supply current

mA

°C

W

I_SS

ground current

-

100

T_j

junction temperature

storage temperature

-

150

[10]

[11]

T_stg

P_tot(pack)

−65

-

+150

1.5

total power dissipation (per

package)

based on package heat

transfer, not device

power consumption

V_esd

electrostatic discharge voltage human body model

all pins

−2000

+2000

V

[1] The following applies to Table 6:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] Only valid when the V_DD(3V3)supply voltage is present.

[6] Not to exceed 4.6 V.

[7] Per supply pin.

[8] The peak current is limited to 25 times the corresponding maximum current.

[9] Per ground pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

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8. Static characteristics

Table 7.

Static characteristics

T_amb= −40 °C to +125 °C, unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

1.65

3.0

Typ^[1]

1.8

Max

1.95

3.6

Unit

V

[2]

[3]

V_DD(1V8)supply voltage (1.8 V)

V_DD(3V3)supply voltage (3.3 V)

3.3

V

V_DDA(3V3)analog supply voltage

(3.3 V)

2.5

3.3

3.6

V

Standard port pins, RESET, RTCK

I_IL

LOW-level input current

HIGH-level input current

OFF-state output current

V_I= 0 V; no pull-up

-

3

µA

I_IH

I_OZ

V_I= V_DD(3V3); no pull-down

V_O= 0 V, V_O= V_DD(3V3)

;

no pull-up/down

I_latch

V_I

I/O latch-up current

input voltage

−(0.5V_DD(3V3)) < V_I<

(1.5V_DD(3V3)); T_j< 125 °C

100

0

-

mA

V

[4][5]

[6]

5.5

V_O

output voltage

output active

0

-

V_DD(3V3)

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

-

V

-

0.8

V

V_hys

V_OH

V_OL

I_OH

I_OL

0.4

-

V

[7]

[8]

HIGH-level output voltage

LOW-level output voltage

HIGH-level output current

LOW-level output current

I_OH= −4 mA

I_OL= 4 mA

V

-

_DD(3V3)− 0.4 -

-

V

-

0.4

-

V

V_OH= V_DD(3V3)− 0.4 V

V_OL= 0.4 V

−4

4

-

mA

-

I_OHS

HIGH-level short-circuit

output current

V_OH= 0 V

−45

[8]

I_OLS

LOW-level short-circuit

output current

V_OL= V_DD(3V3)

-

50

mA

[9]

[10]

[9]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

−15

0

50

−50

0

150

−85

0

µA

V_I= 0 V

V_DD(3V3)< V_I< 5 V

Power consumption LPC2292, LPC2292/00, LPC2294, LPC2294/00

I_DD(act)

active mode supply current V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

-

50

-

mA

T

_amb= 25 °C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP^[11]register but not

conﬁgured to run

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Table 7.

Static characteristics …continued

T_amb= −40 °C to +125 °C, unless otherwise speciﬁed.

Symbol Parameter

I_DD(pd)Power-down mode supply

current

Conditions

Min

Typ^[1]

Max

Unit

V_DD(1V8)= 1.8 V;

-

10

-

µA

T

_amb= 25 °C

V_DD(1V8)= 1.8 V;

_amb= 85 °C

V_DD(1V8)= 1.8 V;

_amb= 125 °C

Power consumption LPC2292/01 and LPC2294/01

-

110

300

500

µA

T

1000

T

I_DD(act)

active mode supply current V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

-

45

-

mA

T

_amb= 25 °C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP^[11]register but not

conﬁgured to run

I_DD(idle)

Idle mode supply current

V_DD(1V8)= 1.8 V;

CCLK = 60 MHz;

-

11.5

-

mA

T

_amb= 25 °C;

executed from ﬂash; all

peripherals enabled via

PCONP^[11]register but not

conﬁgured to run

I_DD(pd)

Power-down mode supply

current

V_DD(1V8)= 1.8 V;

-

10

-

µA

T

_amb= 25 °C

V_DD(1V8)= 1.8 V;

_amb= 85 °C

V_DD(1V8)= 1.8 V;

_amb= 125 °C

180

430

T

-

T

I²C-bus pins

V_IH

V_IL

V_hys

V_OL

I_LI

HIGH-level input voltage

0.7V_DD(3V3)

-

V

LOW-level input voltage

hysteresis voltage

-

0.3V_DD(3V3)

V

0.5V_DD(3V3)

-

V

[7]

LOW-level output voltage

input leakage current

I_OLS= 3 mA

V_I= V_DD(3V3)

V_I= 5 V

-

0.4

4

V

[12]

2

µA

10

22

Oscillator pins

V_i(XTAL1)

input voltage on pin XTAL1

0

-

1.8

V

V_o(XTAL2)output voltage on pin

XTAL2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), nominal supply voltages.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] V_DD(3V3)supply voltages must be present.

[6] 3-state outputs go into 3-state mode when V_DD(3V3)is grounded.

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[7] Accounts for 100 mV voltage drop in all supply lines.

[8] Only allowed for a short time period.

[9] Minimum condition for V_I= 4.5 V, maximum condition for V_I= 5.5 V.

[10] Applies to P1[25:16].

[11] See the LPC2119/2129/2194/2292/2294 User Manual.

[12] To V_SS

.

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Table 8.

ADC static characteristics

V_DDA= 2.5 V to 3.6 V; T_amb= −40 °C to +125 °C unless otherwise speciﬁed. ADC frequency 4.5 MHz.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_DDA

1

Unit

V

analog input voltage

0

-

C_ia

analog input

capacitance

pF

E_D

differential linearity

error

-

±1

LSB

[1][2][3]

[1][4]

[1][5]

[1][6]

[1][7]

E_L(adj)

E_O

integral non-linearity

offset error

-

±2

LSB

%

±3

E_G

gain error

±0.5

±4

E_T

absolute error

LSB

[1] Conditions: V_SSA= 0 V, V_DDA= 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width. See Figure 5.

[4] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 5.

[5] The offset error (E_O) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 5.

[6] The gain error (E_G) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 5.

[7] The absolute voltage error (E_T) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 5.

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gain

error

offset

error

E

O

G

1023

1022

1021

1020

1019

1018

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

1018 1019 1020 1021 1022 1023 1024

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

V

− V

SSA

DDA

1 LSB =

offset

error

1024

002aaa668

E

O

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 5. ADC characteristics

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

34 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

8.1 Power consumption measurements for LPC2292/01 and LPC2294/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP register, but for these measurements,

the peripherals were not conﬁgured to run. Peripherals were disabled through the PCONP

register. For a description of the PCONP register bits, refer to the

LPC2119/2129/2194/2292/2294 User Manual.

002aad102

50

I

DD(act)

(mA)

40

30

20

10

0

all peripherals enabled

all peripherals disabled

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V.

Fig 6. Typical LPC2292/01 I_DD(act)measured at different frequencies

002aad103

50

60 MHz

I

DD(act)

(mA)

48 MHz

40

30

20

10

0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V; all peripherals enabled but not active.

Fig 7. Typical LPC2292/01 I_DD(act)measured at different voltages

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

35 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad104

45

60 MHz

I

DD(act)

(mA)

48 MHz

35

25

15

5

12 MHz

-40

-15

10

35

60

85

temperature (°C)

Test conditions: Active mode entered executing code on-chip ﬂash; PCLK = ^CCLK⁄₄;

core voltage 1.8 V; all peripherals disabled.

Fig 8. Typical LPC2292/01 I_DD(act)measured at different temperatures

002aad105

10.0

I

DD(idle)

(mA)

8.0

6.0

4.0

2.0

0.0

all peripherals enabled

all peripherals disabled

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V.

Fig 9. Typical LPC2292/01 I_DD(idle)measured at different frequencies

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

36 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad106

10.0

I

DD(idle)

(mA)

60 MHz

48 MHz

8.0

6.0

4.0

2.0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V; all peripherals enabled but not active.

Fig 10. Typical LPC2292/01 I_DD(idle)measured at different voltages

002aad107

6.0

I

DD(idle)

(mA)

5.0

4.0

3.0

2.0

1.0

60 MHz

48 MHz

12 MHz

-40

-15

10

35

60

85

temperature (°C)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

Core voltage 1.8 V; all peripherals disabled.

Fig 11. Typical LPC2292/01 I_DD(idle)measured at different temperatures

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

37 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad108

200

I

DD(pd)

(µA)

1.95 V

1.8 V

160

120

80

1.65 V

40

0

-40

-15

10

35

60

85

temperature (°C)

Test conditions: Power-down mode entered executing code from on-chip ﬂash.

Fig 12. Typical LPC2292/01 core power-down current I_DD(pd)measured at different temperatures

002aad109

50.0

I

DD(act)

(mA)

all peripherals enabled

all peripherals disabled

40.0

30.0

20.0

10.0

0.0

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V.

Fig 13. Typical LPC2294/01 I_DD(act)measured at different frequencies

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

38 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad110

55.0

I

DD(act)

(mA)

60 MHz

48 MHz

45.0

35.0

25.0

15.0

5.0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V; all peripherals enabled but not active.

Fig 14. Typical LPC2294/01 I_DD(act)measured at different voltages

002aad111

45.0

60 MHz

I

DD(act)

(mA)

48 MHz

35.0

25.0

15.0

5.0

12 MHz

-40

-25

-10

5

20

35

50

65

80

95

110

temperature (°C)

125

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

core voltage 1.8 V; all peripherals disabled.

Fig 15. Typical LPC2294/01 I_DD(act)measured at different temperatures

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

39 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad112

15.0

I

DD(idle)

(mA)

10.0

5.0

all peripherals enabled

all peripherals disabled

0.0

12

20

28

36

44

52

60

frequency (MHz)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V.

Fig 16. Typical LPC2294/01 I_DD(idle)measured at different frequencies

002aad113

15.0

I

DD(idle)

(mA)

60 MHz

48 MHz

10.0

5.0

12 MHz

0.0

1.65

1.80

1.95

voltage (V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

T_amb= 25 °C; core voltage 1.8 V; all peripherals enabled but not active.

Fig 17. Typical LPC2294/01 I_DD(idle)measured at different voltages

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

40 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad114

6.50

I

DD(idle)

(mA)

60 MHz

5.50

48 MHz

4.50

3.50

2.50

1.50

0.50

12 MHz

-40

-25

-10

5

20

35

50

65

80

95

110

125

temperature (°C)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

core voltage 1.8 V; all peripherals disabled.

Fig 18. Typical LPC2294/01 I_DD(idle)measured at different temperatures

002aad115

500

I

DD(pd)

(µA)

1.95 V

1.8 V

400

300

200

100

0

1.65 V

-40

-25

-10

5

20

35

50

65

80

95

110

125

temperature (°C)

Test conditions: Power-down mode entered executing code from on-chip ﬂash.

Fig 19. Typical LPC2294/01 core power-down current I_DD(pd)measured at different temperatures

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

41 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

002aad116

45.0

I

DD(act)

(mA)

60 MHz

48 MHz

35.0

25.0

15.0

5.0

12 MHz

1.65

1.80

1.95

voltage (V)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 20. Typical LPC2292/01 and LPC2294/01 I_DD(act)measured at different voltages

002aad117

10.0

I

DD(idle)

(mA)

60 MHz

48 MHz

5.0

12 MHz

0.0

1.65

1.80

1.95

voltage (V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = ^CCLK⁄₄;

Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 21. Typical LPC2292/01 and LPC2294/01 I_DD(idle)measured at different voltages

Table 9.

Typical LPC2292/01 peripheral power consumption in active mode

Core voltage 1.8 V; T_amb= 25 °C; all measurements in µA; PCLK = ^CCLK⁄₄; all peripherals enabled.

Peripheral

Timer0

CCLK = 12 MHz

CCLK = 48 MHz

CCLK = 60 MHz

43

141

150

320

351

184

180

398

421

Timer1

46

UART0

UART1

98

103

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

42 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 9.

Typical LPC2292/01 peripheral power consumption in active mode …continued

Core voltage 1.8 V; T_amb= 25 °C; all measurements in µA; PCLK = ^CCLK⁄₄; all peripherals enabled.

Peripheral

PWM0

I²C-bus

SPI0/1

RTC

CCLK = 12 MHz

CCLK = 48 MHz

CCLK = 60 MHz

103

9

341

37

407

53

6

27

29

16

306

33

229

55

78

PCEMC

ADC

994

128

771

1205

167

914

CAN1/2

Table 10. Typical LPC2294/01 peripheral power consumption in active mode

Core voltage 1.8 V; T_amb= 25 °C; all measurements in µA; PCLK = ^CCLK⁄₄; all peripherals enabled.

Peripheral

Timer0

Timer1

UART0

UART1

PWM0

CCLK = 12 MHz

CCLK = 48 MHz

CCLK = 60 MHz

43

46

98

103

9

141

150

320

351

341

37

184

180

398

421

407

53

I²C-bus

SPI0/1

6

27

29

RTC

16

306

33

230

55

78

PCEMC

ADC

994

128

769

1205

167

912

CAN1/2/3/4

9. Dynamic characteristics

Table 11. Dynamic characteristics

T_amb= −40 °C to +125 °C; V_DD(1V8), V_DD(3V3)over speciﬁed ranges.^[1]

Symbol

External clock

f_osc

Parameter

Conditions

Min

Typ

Max

Unit

oscillator frequency

supplied by an external

oscillator (signal generator)

1

-

50

30

MHz

external clock frequency

supplied by an external

crystal oscillator

external clock frequency if

on-chip PLL is used

10

-

25

MHz

external clock frequency if

on-chip bootloader is used

for initial code download

T_cy(clk)

t_CHCX

t_CLCX

clock cycle time

clock HIGH time

clock LOW time

20

-

1000

ns

T_cy(clk)× 0.4

_cy(clk)× 0.4

-

T

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

43 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 11. Dynamic characteristics …continued

T_amb= −40 °C to +125 °C; V_DD(1V8), V_DD(3V3)over speciﬁed ranges.^[1]

Symbol

t_CLCH

Parameter

Conditions

Min

Typ

Max

5

Unit

ns

clock rise time

clock fall time

-

t_CHCL

5

ns

Port pins (except P0[2] and P0[3])

t_r

t_f

rise time

-

10

-

ns

fall time

I²C-bus pins (P0[2] and P0[3])

[2]

t_ffall time

V_IHto V_IL

20 + 0.1 × C_b

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance C_bin pF, from 10 pF to 400 pF.

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

44 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 12. External memory interface dynamic characteristics

C_L= 25 pF, T_amb= 40 °C

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Common to read and write cycles

t_CHAV

XCLK HIGH to address valid

time

-

10

ns

t_CHCSL

t_CHCSH

XCLK HIGH to CS LOW time

-

10

ns

XCLK HIGH to CS HIGH

time

t_CHANV

XCLK HIGH to address

invalid time

-

10

ns

Read cycle parameters

t_CSLAVCS LOW to address valid

[1]

−5

-

+10

ns

time

t_OELAV

OE LOW to address valid

time

t_CSLOEL

t_am

CS LOW to OE LOW time

memory access time

-

+5

-

ns

[2][3]

[2][4]

[5]

(T_cy(CCLK)× (2 + WST1)) +

(−20)

t_am(ibr)

t_am(sbr)

memory access time (initial

burst-ROM)

(T_cy(CCLK)× (2 + WST1)) +

(−20)

-

ns

memory access time

T_cy(CCLK)+ (−20)

(subsequent burst-ROM)

t_h(D)

data hold time

0

-

ns

t_CSHOEH

t_OEHANV

CS HIGH to OE HIGH time

−5

+5

OE HIGH to address invalid

time

t_CHOEL

t_CHOEH

XCLK HIGH to OE LOW time

−5

-

+5

ns

XCLK HIGH to OE HIGH

time

Write cycle parameters

[1]

t_AVCSL

address valid to CS LOW

T

_cy(CCLK)− 10

-

ns

time

t_CSLDV

CS LOW to data valid time

CS LOW to WE LOW time

CS LOW to BLS LOW time

WE LOW to data valid time

CS LOW to data valid time

WE LOW to WE HIGH time

−5

-

+5

ns

t_CSLWEL

t_CSLBLSL

t_WELDV

t_CSLDV

[2]

t_WELWEH

T

_cy(CCLK)× (1 + WST2) − 5

_cy(CCLK)− 5

T

_cy(CCLK)× (1 +

WST2) + 5

t_BLSLBLSHBLS LOW to BLS HIGH time

-

T_cy(CCLK)

(1 + WST2) + 5

×

ns

t_WEHANV

t_WEHDNV

WE HIGH to address invalid

time

T_cy(CCLK)+ 5

[2]

WE HIGH to data invalid time

(2 × T_cy(CCLK)) − 5

T_cy(CCLK)− 5

-

(2 × T_cy(CCLK)) + 5 ns

T_cy(CCLK)+ 5 ns

t_BLSHANVBLS HIGH to address invalid

time

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

45 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 12. External memory interface dynamic characteristics …continued

C_L= 25 pF, T_amb= 40 °C

Symbol

Parameter

Conditions

Min

Typ Max

Unit

[2]

t_BLSHDNVBLS HIGH to data invalid

time

(2 × T_cy(CCLK)) − 5

-

(2 × T_cy(CCLK)) + 5 ns

t_CHDV

XCLK HIGH to data valid

time

-

10

ns

t_CHWEL

t_CHBLSL

t_CHWEH

t_CHBLSH

t_CHDNV

XCLK HIGH to WE LOW

time

XCLK HIGH to BLS LOW

time

XCLK HIGH to WE HIGH

time

XCLK HIGH to BLS HIGH

time

XCLK HIGH to data invalid

time

[1] Except on initial access, in which case the address is set up T_cy(CCLK)earlier.

[2] T_cy(CCLK)= ¹⁄_CCLK

.

[3] Latest of address valid, CS LOW, OE LOW to data valid.

[4] Address valid to data valid.

[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.

Table 13. Standard read access speciﬁcations

Access cycle

Max frequency

WST^[1]setting

Memory access time requirement

WST ≥ 0; round up to

integer

standard read

2 + WST1

_RAM+ 20 ns

t

_RAM+ 20 ns

t_RAM≤ t_cy(CCLK)× (2 + WST1) – 20 ns

f _MAX

≤

--------------------------------

WST1 ≥

WST2 ≥

– 2

--------------------------------

t_cy(CCLK)

t

standard write

1 + WST2

t

_WRITE– t_CYC+ 5

t_WRITE≤ t_cy(CCLK)× (1 + WST2) – 5 ns

t_INIT≤ t_cy(CCLK)× (2 + WST1) – 20 ns

---------------------------------

-------------------------------------------

t

_WRITE+ 5 ns

t_cy(CCLK)

burst read - initial

burst read - subsequent 3×

2 + WST1

t_INIT+ 20 ns

-------------------------------

WST1 ≥

– 2

-------------------------------

t_INIT+ 20 ns

t_cy(CCLK)

N/A

1

t

_ROM≤ t_cy(CCLK)– 20 ns

--------------------------------

t_ROM+ 20 ns

[1] See the LPC2119/2129/2194/2292/2294 User Manual for a description of the WSTn bits.

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

46 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

9.1 Timing

XCLK

t

CSHOEH

CSLAV

CS

addr

data

t

h(D)

am

t

CSLOEL

t

OEHANV

OELAV

OE

t

CHOEH

CHOEL

002aaa749

Fig 22. External memory read access

XCLK

CS

t

CSLDV

t

AVCSL

t

WELWEH

t

CSLWEL

t

BLSLBLSH

BLS/WE

t

WEHANV

t

WELDV

CSLBLSL

t

BLSHANV

addr

data

t

WEHDNV

BLSHDNV

t

CSLDV

OE

002aaa750

Fig 23. External memory write access

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

47 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

V

DD

− 0.5 V

0.2V

+ 0.9 V

DD

0.2V

− 0.1 V

DD

0.45 V

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 24. External clock timing

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

48 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

10. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

y

X

A

108

109

73

72

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

37

144

1

36

v M

Z

A

w M

D

b

p

e

D

B

H

v M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

mm

1.6

0.25

1

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

Fig 25. Package outline SOT486-1 (LQFP144)

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

49 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls; body 12 x 12 x 0.8 mm

SOT569-1

B

D

A

D

1

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

v M

C

A B

C

1

b

e

w M

N

M

L

e

K

J

H

G

F

e

2

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

7

8

9 10111213

shape

X

optional (4×)

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

E

e

2

y

D

E

v

w

y

1

2

1

max.

0.36 0.84 0.53 12.2 11.9 12.2 11.9

0.24 0.74 0.43 11.8 11.7 11.8 11.7

mm

1.2

0.1

0.8

9.6

0.15 0.08

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

03-07-09

05-09-14

SOT569-1

MO-216

Fig 26. Package outline SOT569-1 (TFBGA144)

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

50 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

11. Abbreviations

Table 14. Acronym list

Acronym

ADC

AMBA

APB

Description

Analog-to-Digital Converter

Advanced Microcontroller Bus Architecture

Advanced Peripheral Bus

Controller Area Network

CAN

CISC

FIFO

GPIO

I/O

Complex Instruction Set Computer

First In, First Out

General Purpose Input/Output

Input/Output

JTAG

PLL

Joint Test Action Group

Phase-Locked Loop

PWM

RISC

SPI

Pulse Width Modulator

Reduced Instruction Set Computer

Serial Peripheral Interface

Static Random Access Memory

Synchronous Serial Interface

Synchronous Serial Port

SRAM

SSI

SSP

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

UART

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

51 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

12. Revision history

Table 15. Revision history

Document ID

LPC2292_2294_6

Modiﬁcations:

Release date

20071210

Data sheet status

Change notice

Supersedes

Product data sheet

-

LPC2292_2294_5

• Type number LPC2292FBD144/01 has been added.

• Type number LPC2292FET144/01 has been added.

• Type number LPC2294HBD144/01 has been added.

• Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)

and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.

• Power consumption measurements for LPC2292/2294/01 added.

• Description of JTAG pin TCK has been updated.

LPC2292_2294_5

LPC2292_2294_4

LPC2292_2294_3

LPC2292_2294-02

20070215

20060711

20051101

20041223

Product data sheet

Product data

-

LPC2292_2294_4

LPC2292_2294_3

LPC2292_2294-02

LPC2292_2294-01

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

52 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

13.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

53 of 54

LPC2292/LPC2294

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

15. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.17

6.17.1

6.18

6.18.1

6.19

6.19.1

6.19.2

6.19.3

6.19.4

6.19.5

6.19.6

6.19.7

6.19.8

6.20

Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pulse width modulator . . . . . . . . . . . . . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System control . . . . . . . . . . . . . . . . . . . . . . . . 25

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 25

PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset and wake-up timer . . . . . . . . . . . . . . . . 25

Code security (Code Read Protection - CRP) 26

External interrupt inputs. . . . . . . . . . . . . . . . . 26

Memory mapping control . . . . . . . . . . . . . . . . 26

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27

APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Emulation and debugging. . . . . . . . . . . . . . . . 27

EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 27

Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 28

RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features brought by LPC2292/2294/01

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features common for all devices . . . . . . . . 1

2.2

3

3.1

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

6

Functional description . . . . . . . . . . . . . . . . . . 15

Architectural overview. . . . . . . . . . . . . . . . . . . 15

On-chip ﬂash program memory . . . . . . . . . . . 15

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17

Pin connect block . . . . . . . . . . . . . . . . . . . . . . 18

External memory controller. . . . . . . . . . . . . . . 18

General purpose parallel I/O (GPIO) and

Fast I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features added with the Fast GPIO set of

registers available on LPC2292/2294/01 only 19

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ADC features available in LPC2292/2294/01

only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CAN controllers and acceptance ﬁlter . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UART features available in LPC2292/2294/01

only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I²C-bus serial I/O controller . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features available in LPC2292/2294/01 only . 21

SSP controller (LPC2292/94/01 only). . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

General purpose timers . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Features available in LPC2292/2294/01 only . 23

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

6.2

6.3

6.4

6.5

6.5.1

6.6

6.7

6.8

6.20.1

6.20.2

6.20.3

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

8

8.1

Static characteristics . . . . . . . . . . . . . . . . . . . 30

Power consumption measurements for

LPC2292/01 and LPC2294/01 . . . . . . . . . . . . 35

9

Dynamic characteristics. . . . . . . . . . . . . . . . . 43

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 49

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51

Revision history . . . . . . . . . . . . . . . . . . . . . . . 52

9.1

10

11

12

6.8.1

6.8.2

6.9

6.9.1

6.9.2

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53

13.1

13.2

13.3

13.4

6.10

6.10.1

6.11

6.11.1

6.11.2

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.12

6.12.1

6.13

6.13.1

6.13.2

6.14

6.14.1

6.15

6.15.1

6.15.2

6.16

6.16.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 December 2007

Document identifier: LPC2292_2294_6


型号：	LPC2292_07
厂家：	NXP
描述：	16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface 16位/ 32位ARM微控制器; 256 kB的ISP / IAP闪存， CAN ， 10位ADC和外部存储器接口闪存存储微控制器
文件：	总54页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2292_07 [NXP]

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