LPC2460FET208-S [NXP]
LPC2460FET208-S;
| 型号： | LPC2460FET208-S |
| 厂家： | 
NXP |
| 描述： | LPC2460FET208-S PC |
| 文件： | 总73页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC2420/2460
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 03 — 20 November 2008
Preliminary data sheet
1. General description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means
engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2420/2460 microcontroller is ideal for multi-purpose communication applications.
It incorporates a 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), a USB
full-speed Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two
Controller Area Network (CAN) channels (LPC2460 only), an SPI interface, two
Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. Supporting
this collection of serial communications interfaces are the following feature components;
an on-chip 4 MHz internal precision oscillator, 82/98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet (LPC2460 only), 16 kB SRAM for general
purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller
(EMC). These features make this device optimally suited for communication gateways and
protocol converters. Complementing the many serial communication controllers, versatile
clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit
ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO
lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware based Vector
Interrupt Controller (VIC) that means these external inputs can generate edge-triggered
interrupts. All of these features make the LPC2420/2460 particularly suitable for industrial
control and medical systems.
2. Features
I ARM7TDMI-S processor, running at up to 72 MHz.
I 82/98 kB on-chip SRAM includes:
N 64 kB of SRAM on the ARM local bus for high performance CPU access.
N 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
(LPC2460 only)
N 16 kB SRAM for general purpose DMA use also accessible by the USB.
N 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
I Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention (LPC2460 only).
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
I EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as Single Data Rate SDRAM.
I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
I General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I2S, and SD/MMC interface as well as for memory-to-memory transfers.
I Serial Interfaces:
N Ethernet MAC with MII/RMII interface and associated DMA controller (LPC2460
only). These functions reside on an independent AHB.
N USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and
associated DMA controller.
N Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
N CAN controller with two channels (LPC2460 only).
N SPI controller.
N Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA
controller.
N Three I2C-bus interfaces (one with open-drain and two with standard port pins).
N I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
I Other peripherals:
N SD/MMC memory card interface.
N 160 General purpose I/O pins with configurable pull-up/down resistors.
N 10-bit ADC with input multiplexing among 8 pins.
N 10-bit DAC.
N Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
N Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
N RTC with separate power domain, clock source can be the RTC oscillator or the
APB clock.
N 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
N WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
I Standard ARM test/debug interface for compatibility with existing tools.
I Emulation trace module supports real-time trace.
I Single 3.3 V power supply (3.0 V to 3.6 V).
I Three reduced power modes: idle, sleep, and power-down.
I Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
I Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, port 0/2
pin interrupt, Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460
only).
I Two independent power domains allow fine tuning of power consumption based on
needed features.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
2 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
I Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30 %.
I Brownout detect with separate thresholds for interrupt and forced reset.
I On-chip power-on reset.
I On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
I 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
I On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
I Boundary scan for simplified board testing.
I Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
I Industrial control
I Medical systems
I Protocol converter
I Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
Type number
Description
Version
LPC2420FBD208 LQFP208
LPC2460FBD208 LQFP208
plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm
plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm
SOT459-1
SOT459-1
LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm SOT950-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash
(kB)
SRAM (kB)
External
bus
Ethernet USB
OTG/
SD/ GP
MMC DMA
Temp
range
OHCI/
DEV
+ 4 kB
FIFO
LPC2420FBD208
LPC2460FBD208
LPC2460FET208
N/A
N/A
N/A
64
-
16 2 82 Full 32-bit
-
yes
-
yes
yes
yes
yes
yes
yes
8
8
8
1
1
1
−40 °C to
+85 °C
64 16 16 2 98 Full 32-bit MII/RMII yes
64 16 16 2 98 Full 32-bit MII/RMII yes
2
2
−40 °C to
+85 °C
−40 °C to
+85 °C
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
3 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
5. Block diagram
XTAL1
XTAL2
V
DD(3V3)
DDA
TMS TDI
trace signals
V
TRST TCK TDO
RESET
EXTIN0 DBGEN
VREF
SYSTEM
FUNCTIONS
LPC2420/2460
PLL
V
V
, V
, V
P0, P1, P2,
P3, P4
SSA SSCORE SSIO
64 kB
SRAM
TEST/DEBUG
INTERFACE
DD(DCDC)(3V3)
system
clock
INTERNAL RC
OSCILLATOR
HIGH-SPEED
GPI/O
160 PINS
TOTAL
INTERNAL
SRAM
CONTROLLER
ARM7TDMI-S
D[31:0]
A[23:0]
EXTERNAL
MEMORY
CONTROLLER
16 kB
SRAM
VIC
control lines
AHB1
AHB2
AHB
BRIDGE
AHB
BRIDGE
V
BUS
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
16 kB
SRAM
(1)
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
ETHERNET
MAC WITH
DMA
port1
port2
MII/RMII
(1)
AHB TO
APB BRIDGE
GP DMA
CONTROLLER
EINT3 to EINT0
P0, P2
I2SRX_CLK
I2STX_CLK
EXTERNAL INTERRUPTS
I2SRX_WS
I2STX_WS
I2SRX_SDA
2
I S INTERFACE
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2/MAT3,
2 × MAT0,
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I2STX_SDA
SCK, SCK0
3 × MAT1
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SPI, SSP0 INTERFACE
SSP1 INTERFACE
6 × PWM0/PWM1
PWM0, PWM1
1 × PCAP0,
2 × PCAP1
SCK1
LEGACY GPI/O
64 PINS TOTAL
MOSI1
MISO1
SSEL1
P0, P1
8 × AD0
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
MCICLK, MCIPWR
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
AOUT
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
UART0, UART2, UART3
UART1
VBAT
TXD1
RXD1
DTR1, RTS1
power domain 2
REAL-
TIME
RTCX1
RTCX2
RTC
OSCILLATOR
DSR1, CTS1, DCD1,
RI1
CLOCK
ALARM
RD1, RD2
TD1, TD2
(1)
(1)
CAN1 , CAN2
WATCHDOG TIMER
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
2
2
2
I C0, I C1, I C2
SYSTEM CONTROL
002aad313
(1) LPC2460 only.
Fig 1. LPC2420/2460 block diagram
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
4 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
6. Pinning information
6.1 Pinning
1
156
105
LPC2420FBD208
LPC2460FBD208
52
002aad314
Fig 2. LPC2420/2460 pinning LQFP208 package
ball A1
index area
2
4
6
8
10 12 14 16
9 11 13 15 17
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
LPC2460FET208
M
N
P
R
T
U
002aad315
Transparent top view
Fig 3. LPC2460 pinning TFBGA208 package
Table 3.
Pin allocation table
Pin Symbol
Row A
Pin Symbol
Pin Symbol
Pin Symbol
1
P3[27]/D27/
CAP1[0]/PWM1[4]
2
6
VSSIO
P1[9]/ENET_RXD0
3
7
P1[0]/ENET_TXD0
4
8
P4[31]/CS1
5
P1[4]/ENET_TX_EN
P1[14]/ENET_RX_ER
P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
9
P1[17]/ENET_MDIO
10 P1[3]/ENET_TXD3/
MCICMD/PWM0[2]
11 P4[15]/A15
12 VSSIO
13 P3[20]/D20/
PWM0[5]/DSR1
14 P1[11]/ENET_RXD2/
MCIDAT2/PWM0[6]
15 P0[8]/I2STX_WS/
MISO1/MAT2[2]
16 P1[12]/ENET_RXD3/
MCIDAT3/PCAP0[0]
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
5 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 3.
Pin allocation table
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
17 P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
-
-
-
Row B
1
5
9
P3[2]/D2
2
6
P3[10]/D10
VSSIO
3
7
P3[1]/D1
4
8
P3[0]/D0
P1[1]/ENET_TXD1
P4[25]/WE
P4[30]/CS0
P4[24]/OE
10 P4[29]/BLS3/
MAT2[1]/RXD3
11 P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
12 P0[4]/I2SRX_CLK/RD2/
CAP2[0]
13 VDD(3V3)
14 P3[19]/D19/
PWM0[4]/DCD1
15 P4[14]/A14
16 P4[13]/A13
17 P2[0]/PWM1[1]/TXD1/
TRACECLK
-
-
-
Row C
1
5
P3[13]/D13
P3[9]/D9
2
6
TDI
3
7
RTCK
4
P0[2]/TXD0
P3[22]/D22/
PCAP0[0]/RI1
P1[8]/ENET_CRS_DV/E 8
NET_CRS
P1[10]/ENET_RXD1
9
VDD(3V3)
10 P3[21]/D21/
PWM0[6]/DTR1
11 P4[28]/BLS2/
MAT2[0]/TXD3
12 P0[5]/I2SRX_WS/TD2/
CAP2[1]
13 P0[7]/I2STX_CLK/SCK1 14 P0[9]/I2STX_SDA/
15 P3[18]/D18/
PWM0[3]/CTS1
16 P4[12]/A12
/MAT2[1]
17 VDD(3V3)
Row D
MOSI1/MAT2[3]
-
-
-
1
TRST
2
6
P3[28]/D28/
CAP1[1]/PWM1[5]
3
7
TDO
4
8
P3[12]/D12
P3[8]/D8
5
9
P3[11]/D11
P0[3]/RXD0
VDD(3V3)
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
10 P1[16]/ENET_MDC
11 VDD(DCDC)(3V3)
12 VSSCORE
13 P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
14 P1[7]/ENET_COL/
MCIDAT1/PWM0[5]
15 P2[2]/PWM1[3]/
CTS1/PIPESTAT1
16 P1[13]/ENET_RX_DV
-
17 P2[4]/PWM1[5]/
DSR1/TRACESYNC
-
-
Row E
1
P0[26]/AD0[3]/
AOUT/RXD3
2
TCK
3
TMS
4
P3[3]/D3
14 P2[1]/PWM1[2]/RXD1/
PIPESTAT0
15 VSSIO
16 P2[3]/PWM1[4]/
DCD1/PIPESTAT2
17 P2[6]/PCAP1[0]/
RI1/TRACEPKT1
Row F
1
P0[25]/AD0[2]/
2
P3[4]/D4
3
P3[29]/D29/
4
DBGEN
I2SRX_SDA/TXD3
MAT1[0]/PWM1[6]
14 P4[11]/A11
15 P3[17]/D17/
16 P2[5]/PWM1[6]/
DTR1/TRACEPKT0
17 P3[16]/D16/
PWM0[1]/TXD1
PWM0[2]/RXD1
Row G
1
P3[5]/D5
2
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
3
VDD(3V3)
4
VDDA
14 n.c.
15 P4[27]/BLS1
16 P2[7]/RD2/
RTS1/TRACEPKT2
17 P4[10]/A10
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
6 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 3.
Pin allocation table
Pin Symbol
Row H
Pin Symbol
Pin Symbol
Pin Symbol
1
P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
2
P3[14]/D14
3
P3[30]/D30/
MAT1[1]/RTS1
4
VDD(DCDC)(3V3)
14 VSSIO
15 P2[8]/TD2/
16 P2[9]/
USB_CONNECT1/
17 P4[9]/A9
TXD2/TRACEPKT3
RXD2/EXTIN0
Row J
1
P3[6]/D6
2
VSSA
3
P3[31]/D31/MAT1[2]
4
n.c.
14 P0[16]/RXD1/
SSEL0/SSEL
15 P4[23]/A23/
RXD2/MOSI1
16 P0[15]/TXD1/
SCK0/SCK
17 P4[8]/A8
Row K
1
VREF
2
RTCX1
3
RSTOUT
4
VSSCORE
14 P4[22]/A22/
TXD2/MISO1
15 P0[18]/DCD1/
MOSI0/MOSI
16 VDD(3V3)
17 P0[17]/CTS1/
MISO0/MISO
Row L
1
P3[7]/D7
2
RTCX2
3
VSSIO
4
P2[30]/DQMOUT2/
MAT3[2]/SDA2
14 n.c.
15 P4[26]/BLS0
16 P4[7]/A7
17 P0[19]/DSR1/
MCICLK/SDA1
Row M
1
P3[15]/D15
2
RESET
3
VBAT
4
XTAL1
14 P4[6]/A6
15 P4[21]/A21/
SCL2/SSEL1
16 P0[21]/RI1/
MCIPWR/RD1
17 P0[20]/DTR1/
MCICMD/SCL1
Row N
1
ALARM
2
P2[31]/DQMOUT3/
MAT3[3]/SCL2
3
P2[29]/DQMOUT1
4
XTAL2
14 P2[12]/EINT2/
MCIDAT2/I2STX_WS
15 P2[10]/EINT0
16 VSSIO
17 P0[22]/RTS1/
MCIDAT0/TD1
Row P
1
5
9
P1[31]/USB_OVRCR2/
SCK1/AD0[5]
2
6
P1[30]/USB_PWRD2/
BUS/AD0[4]
3
7
P2[27]/CKEOUT3/
MAT3[1]/MOSI0
4
8
P2[28]/DQMOUT0
VDD(3V3)
V
P2[24]/CKEOUT0
VDD(3V3)
P1[18]/USB_UP_LED1/
PWM1[1]/CAP1[0]
P1[23]/USB_RX_DP1/
PWM1[4]/MISO0
10 VSSCORE
11 VDD(DCDC)(3V3)
12 VSSIO
13 P2[15]/CS3/
CAP2[1]/SCL1
14 P4[17]/A17
-
15 P4[18]/A18
-
16 P4[19]/A19
-
17 VDD(3V3)
Row R
1
5
9
P0[12]/USB_PPWR2/
MISO1/AD0[6]
2
6
P0[13]/USB_UP_LED2/
MOSI1/AD0[7]
3
7
P0[28]/SCL0
4
8
P2[25]/CKEOUT1
P3[24]/D24/
CAP0[1]/PWM1[1]
P0[30]/USB_D−1
P2[19]/CLKOUT1
P1[21]/USB_TX_DM1/
PWM1[3]/SSEL0
VSSIO
10 P1[26]/USB_SSPND1/ 11 P2[16]/CAS
PWM1[6]/CAP0[0]
12 P2[14]/CS2/
CAP2[0]/SDA1
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
7 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 3.
Pin allocation table
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
13 P2[17]/RAS
14 P0[11]/RXD2/SCL2/
MAT3[1]
15 P4[4]/A4
16 P4[5]/A5
17 P4[20]/A20/
SDA2/SCK1
-
-
-
Row T
1
P0[27]/SDA0
2
6
P0[31]/USB_D+2
3
7
P3[26]/D26/
MAT0[1]/PWM1[3]
4
8
P2[26]/CKEOUT2/
MAT3[0]/MISO0
5
VSSIO
P3[23]/D23/
CAP0[0]/PCAP1[0]
P0[14]/USB_HSTEN2/
USB_CONNECT2/
SSEL1
P2[20]/DYCS0
9
P1[24]/USB_RX_DM1/ 10 P1[25]/USB_LS1/
PWM1[5]/MOSI0 USB_HSTEN1/MAT1[1]
11 P4[2]/A2
12 P1[27]/USB_INT1/
USB_OVRCR1/CAP0[1]
13 P1[28]/USB_SCL1/
PCAP1[0]/MAT0[0]
14 P0[1]/TD1/RXD3/SCL1 15 P0[10]/TXD2/SDA2/
MAT3[0]
16 P2[13]/EINT3/
MCIDAT3/I2STX_SDA
17 P2[11]/EINT1/
-
-
-
MCIDAT1/I2STX_CLK
Row U
1
5
9
USB_D−2
2
6
P3[25]/D25/
MAT0[0]/PWM1[2]
3
7
P2[18]/CLKOUT0
4
8
P0[29]/USB_D+1
P2[23]/DYCS3/
CAP3[1]/SSEL0
P1[19]/USB_TX_E1/
USB_PPWR1/CAP1[1]
P1[20]/USB_TX_DP1/
PWM1[2]/SCK0
P1[22]/USB_RCV1/
USB_PWRD1/MAT1[0]
P4[0]/A0
10 P4[1]/A1
11 P2[21]/DYCS1
12 P2[22]/DYCS2/
CAP3[0]/SCK0
13 VDD(3V3)
14 P1[29]/USB_SDA1/
PCAP1[1]/MAT0[1]
15 P0[0]/RD1/TXD3/SDA1 16 P4[3]/A3
17 P4[16]/A16
-
-
-
6.2 Pin description
Table 4.
Pin description
Symbol
Pin
Ball
Type Description
P0[0] to P0[31]
I/O
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 0 pins depends upon the pin function selected
via the Pin Connect block.
P0[0]/RD1/
TXD3/SDA1
94[1]
U15[1]
I/O
I
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input (LPC2460 only).
TXD3 — Transmitter output for UART3.
O
I/O
I/O
O
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output (LPC2460 only).
RXD3 — Receiver input for UART3.
P0[1]/TD1/RXD3/
SCL1
96[1]
T14[1]
I
I/O
I/O
O
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
P0[2]/TXD0
202[1]
C4[1]
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
8 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Pin description …continued
Symbol
Pin
Ball
Type Description
P0[3]/RXD0
204[1]
D6[1]
I/O
I
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
168[1]
B12[1]
I/O
I/O
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
I
RD2 — CAN2 receiver input (LPC2460 only).
CAP2[0] — Capture input for Timer 2, channel 0.
P0[5] — General purpose digital input/output pin.
I
P0[5]/
166[1]
C12[1]
I/O
I/O
I2SRX_WS/
TD2/CAP2[1]
I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
O
TD2 — CAN2 transmitter output (LPC2460 only).
CAP2[1] — Capture input for Timer 2, channel 1.
P0[6] — General purpose digital input/output pin.
I
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
164[1]
162[1]
160[1]
D13[1]
C13[1]
A15[1]
I/O
I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
O
SSEL1 — Slave Select for SSP1.
MAT2[0] — Match output for Timer 2, channel 0.
P0[7] — General purpose digital input/output pin.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
I/O
I/O
I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
I/O
O
SCK1 — Serial Clock for SSP1.
MAT2[1] — Match output for Timer 2, channel 1.
P0[8] — General purpose digital input/output pin.
P0[8]/
I/O
I/O
I2STX_WS/
MISO1/MAT2[2]
I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
I/O
O
MISO1 — Master In Slave Out for SSP1.
MAT2[2] — Match output for Timer 2, channel 2.
P0[9] — General purpose digital input/output pin.
P0[9]/
158[1]
C14[1]
I/O
I/O
I2STX_SDA/
MOSI1/MAT2[3]
I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
O
MOSI1 — Master Out Slave In for SSP1.
MAT2[3] — Match output for Timer 2, channel 3.
P0[10] — General purpose digital input/output pin.
TXD2 — Transmitter output for UART2.
P0[10]/TXD2/
SDA2/MAT3[0]
98[1]
T15[1]
I/O
O
I/O
O
SDA2 — I2C2 data input/output (this is not an open-drain pin).
MAT3[0] — Match output for Timer 3, channel 0.
P0[11] — General purpose digital input/output pin.
RXD2 — Receiver input for UART2.
P0[11]/RXD2/
SCL2/MAT3[1]
100[1]
R14[1]
I/O
I
I/O
O
SCL2 — I2C2 clock input/output (this is not an open-drain pin).
MAT3[1] — Match output for Timer 3, channel 1.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
9 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P0[12]/
USB_PPWR2/
MISO1/AD0[6]
41[2]
R1[2]
I/O
O
P0[12] — General purpose digital input/output pin.
USB_PPWR2 — Port Power enable signal for USB port 2.
I/O
I
MISO1 — Master In Slave Out for SSP1.
AD0[6] — A/D converter 0, input 6.
P0[13]/
USB_UP_LED2/
MOSI1/AD0[7]
45[2]
R2[2]
I/O
O
P0[13] — General purpose digital input/output pin.
USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when
device is configured (non-control endpoints enabled). It is HIGH when the
device is not configured or during global suspend.
I/O
I
MOSI1 — Master Out Slave In for SSP1.
AD0[7] — A/D converter 0, input 7.
P0[14]/
69[1]
T7[1]
I/O
O
P0[14] — General purpose digital input/output pin.
USB_HSTEN2 — Host Enabled status for USB port 2.
USB_HSTEN2/
USB_CONNECT2/
SSEL1
O
USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to
switch an external 1.5 kΩ resistor under software control. Used with the
SoftConnect USB feature.
I/O
I/O
O
SSEL1 — Slave Select for SSP1.
P0[15]/TXD1/
SCK0/SCK
128[1]
130[1]
126[1]
124[1]
122[1]
120[1]
J16[1]
J14[1]
K17[1]
K15[1]
L17[1]
M17[1]
P0[15] — General purpose digital input/output pin.
TXD1 — Transmitter output for UART1.
I/O
I/O
I/O
I
SCK0 — Serial clock for SSP0.
SCK — Serial clock for SPI.
P0[16]/RXD1/
SSEL0/SSEL
P0 [16] — General purpose digital input/output pin.
RXD1 — Receiver input for UART1.
I/O
I/O
I/O
I
SSEL0 — Slave Select for SSP0.
SSEL — Slave Select for SPI.
P0[17]/CTS1/
MISO0/MISO
P0[17] — General purpose digital input/output pin.
CTS1 — Clear to Send input for UART1.
MISO0 — Master In Slave Out for SSP0.
MISO — Master In Slave Out for SPI.
I/O
I/O
I/O
I
P0[18]/DCD1/
MOSI0/MOSI
P0[18] — General purpose digital input/output pin.
DCD1 — Data Carrier Detect input for UART1.
MOSI0 — Master Out Slave In for SSP0.
MOSI — Master Out Slave In for SPI.
I/O
I/O
I/O
I
P0[19]/DSR1/
MCICLK/SDA1
P0[19] — General purpose digital input/output pin.
DSR1 — Data Set Ready input for UART1.
MCICLK — Clock output line for SD/MMC interface.
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[20] — General purpose digital input/output pin.
DTR1 — Data Terminal Ready output for UART1.
MCICMD — Command line for SD/MMC interface.
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
O
I/O
I/O
O
P0[20]/DTR1/
MCICMD/SCL1
I/O
I/O
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
10 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P0[21]/RI1/
MCIPWR/RD1
118[1]
M16[1]
I/O
I
P0[21] — General purpose digital input/output pin.
RI1 — Ring Indicator input for UART1.
O
MCIPWR — Power Supply Enable for external SD/MMC power supply.
RD1 — CAN1 receiver input (LPC2460 only).
P0[22] — General purpose digital input/output pin.
RTS1 — Request to Send output for UART1.
MCIDAT0 — Data line 0 for SD/MMC interface.
TD1 — CAN1 transmitter output (LPC2460 only).
P0[23] — General purpose digital input/output pin.
AD0[0] — A/D converter 0, input 0.
I
P0[22]/RTS1/
MCIDAT0/TD1
116[1]
N17[1]
I/O
O
I/O
O
P0[23]/AD0[0]/
I2SRX_CLK/
CAP3[0]
18[2]
H1[2]
I/O
I
I/O
I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
I
CAP3[0] — Capture input for Timer 3, channel 0.
P0[24] — General purpose digital input/output pin.
AD0[1] — A/D converter 0, input 1.
P0[24]/AD0[1]/
I2SRX_WS/
CAP3[1]
16[2]
G2[2]
I/O
I
I/O
I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
I
CAP3[1] — Capture input for Timer 3, channel 1.
P0[25] — General purpose digital input/output pin.
AD0[2] — A/D converter 0, input 2.
P0[25]/AD0[2]/
I2SRX_SDA/
TXD3
14[2]
F1[2]
I/O
I
I/O
I2SRX_SDA — Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
O
TXD3 — Transmitter output for UART3.
P0[26] — General purpose digital input/output pin.
AD0[3] — A/D converter 0, input 3.
P0[26]/AD0[3]/
AOUT/RXD3
12[2][3]
E1[2][3]
I/O
I
O
AOUT — D/A converter output.
I
RXD3 — Receiver input for UART3.
P0[27]/SDA0
P0[28]/SCL0
50[4]
48[4]
T1[4]
R3[4]
I/O
I/O
P0[27] — General purpose digital input/output pin.
SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus
compliance).
I/O
I/O
P0[28] — General purpose digital input/output pin.
SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus
compliance).
P0[29]/USB_D+1
P0[30]/USB_D−1
P0[31]/USB_D+2
P1[0] to P1[31]
61[5]
62[5]
51[5]
U4[5]
R6[5]
T2[5]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0[29] — General purpose digital input/output pin.
USB_D+1 — USB port 1 bidirectional D+ line.
P0[30] — General purpose digital input/output pin.
USB_D−1 — USB port 1 bidirectional D− line.
P0[31] — General purpose digital input/output pin.
USB_D+2 — USB port 2 bidirectional D+ line.
Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each
bit. The operation of port 1 pins depends upon the pin function selected
via the Pin Connect block.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
11 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P1[0]/
ENET_TXD0
196[1]
A3[1]
I/O
O
P1[0] — General purpose digital input/output pin.
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface) (LPC2460
only).
P1[1]/
ENET_TXD1
194[1]
185[1]
B5[1]
D9[1]
I/O
O
P1[1] — General purpose digital input/output pin.
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface) (LPC2460
only).
P1[2]/
I/O
O
P1[2] — General purpose digital input/output pin.
ENET_TXD2/
MCICLK/
PWM0[1]
ENET_TXD2 — Ethernet transmit data 2 (MII interface) (LPC2460 only).
MCICLK — Clock output line for SD/MMC interface.
PWM0[1] — Pulse Width Modulator 0, output 1.
O
O
P1[3]/
177[1]
A10[1]
I/O
O
P1[3] — General purpose digital input/output pin.
ENET_TXD3/
MCICMD/
PWM0[2]
ENET_TXD3 — Ethernet transmit data 3 (MII interface) (LPC2460 only).
MCICMD — Command line for SD/MMC interface.
PWM0[2] — Pulse Width Modulator 0, output 2.
I/O
O
P1[4]/
ENET_TX_EN
192[1]
156[1]
A5[1]
I/O
O
P1[4] — General purpose digital input/output pin.
ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface)
(LPC2460 only).
P1[5]/
A17[1]
I/O
O
P1[5] — General purpose digital input/output pin.
ENET_TX_ER/
MCIPWR/
PWM0[3]
ENET_TX_ER — Ethernet Transmit Error (MII interface) (LPC2460 only).
MCIPWR — Power Supply Enable for external SD/MMC power supply.
PWM0[3] — Pulse Width Modulator 0, output 3.
O
O
P1[6]/
171[1]
B11[1]
I/O
I
P1[6] — General purpose digital input/output pin.
ENET_TX_CLK/
MCIDAT0/
PWM0[4]
ENET_TX_CLK — Ethernet Transmit Clock (MII interface) (LPC2460
only).
I/O
O
MCIDAT0 — Data line 0 for SD/MMC interface.
PWM0[4] — Pulse Width Modulator 0, output 4.
P1[7] — General purpose digital input/output pin.
ENET_COL — Ethernet Collision detect (MII interface) (LPC2460 only).
MCIDAT1 — Data line 1 for SD/MMC interface.
PWM0[5] — Pulse Width Modulator 0, output 5.
P1[8] — General purpose digital input/output pin.
P1[7]/
153[1]
D14[1]
I/O
I
ENET_COL/
MCIDAT1/
PWM0[5]
I/O
O
P1[8]/
ENET_CRS_DV/
ENET_CRS
190[1]
188[1]
186[1]
163[1]
C7[1]
A6[1]
C8[1]
A14[1]
I/O
I
ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII
interface)/ Ethernet Carrier Sense (MII interface) (LPC2460 only).
P1[9]/
ENET_RXD0
I/O
I
P1[9] — General purpose digital input/output pin.
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface) (LPC2460
only).
P1[10]/
ENET_RXD1
I/O
I
P1[10] — General purpose digital input/output pin.
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface) (LPC2460
only).
P1[11]/
I/O
I
P1[11] — General purpose digital input/output pin.
ENET_RXD2 — Ethernet Receive Data 2 (MII interface) (LPC2460 only).
MCIDAT2 — Data line 2 for SD/MMC interface.
ENET_RXD2/
MCIDAT2/
PWM0[6]
I/O
O
PWM0[6] — Pulse Width Modulator 0, output 6.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
12 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P1[12]/
157[1]
A16[1]
I/O
P1[12] — General purpose digital input/output pin.
ENET_RXD3/
MCIDAT3/
PCAP0[0]
I
ENET_RXD3 — Ethernet Receive Data (MII interface) (LPC2460 only).
MCIDAT3 — Data line 3 for SD/MMC interface.
I/O
I
PCAP0[0] — Capture input for PWM0, channel 0.
P1[13] — General purpose digital input/output pin.
P1[13]/
ENET_RX_DV
147[1]
184[1]
182[1]
D16[1]
A7[1]
A8[1]
I/O
I
ENET_RX_DV — Ethernet Receive Data Valid (MII interface) (LPC2460
only).
P1[14]/
ENET_RX_ER
I/O
I
P1[14] — General purpose digital input/output pin.
ENET_RX_ER — Ethernet receive error (RMII/MII interface) (LPC2460
only).
P1[15]/
I/O
I
P1[15] — General purpose digital input/output pin.
ENET_REF_CLK/
ENET_RX_CLK
ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII
interface)/ Ethernet Receive Clock (MII interface) (LPC2460 only).
P1[16]/
ENET_MDC
180[1]
178[1]
66[1]
D10[1]
A9[1]
P7[1]
I/O
O
P1[16] — General purpose digital input/output pin.
ENET_MDC — Ethernet MIIM clock (LPC2460 only).
P1[17] — General purpose digital input/output pin.
ENET_MDIO — Ethernet MIIM data input and output (LPC2460 only).
P1[18] — General purpose digital input/output pin.
P1[17]/
ENET_MDIO
I/O
I/O
I/O
O
P1[18]/
USB_UP_LED1/
PWM1[1]/
CAP1[0]
USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when
device is configured (non-control endpoints enabled). It is HIGH when the
device is not configured or during global suspend.
O
I
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
CAP1[0] — Capture input for Timer 1, channel 0.
P1[19]/
68[1]
70[1]
72[1]
74[1]
U6[1]
U7[1]
R8[1]
U8[1]
I/O
O
O
I
P1[19] — General purpose digital input/output pin.
USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).
USB_PPWR1 — Port Power enable signal for USB port 1.
CAP1[1] — Capture input for Timer 1, channel 1.
USB_TX_E1/
USB_PPWR1/
CAP1[1]
P1[20]/
USB_TX_DP1/
PWM1[2]/SCK0
I/O
O
O
I/O
I/O
O
O
I/O
I/O
I
P1[20] — General purpose digital input/output pin.
USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
SCK0 — Serial clock for SSP0.
P1[21]/
USB_TX_DM1/
PWM1[3]/SSEL0
P1[21] — General purpose digital input/output pin.
USB_TX_DM1 — D− transmit data for USB port 1 (OTG transceiver).
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
SSEL0 — Slave Select for SSP0.
P1[22]/
P1[22] — General purpose digital input/output pin.
USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).
USB_PWRD1 — Power Status for USB port 1 (host power switch).
MAT1[0] — Match output for Timer 1, channel 0.
USB_RCV1/
USB_PWRD1/
MAT1[0]
I
O
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
13 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P1[23]/
USB_RX_DP1/
PWM1[4]/MISO0
76[1]
P9[1]
I/O
I
P1[23] — General purpose digital input/output pin.
USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
MISO0 — Master In Slave Out for SSP0.
O
I/O
I/O
I
P1[24]/
USB_RX_DM1/
PWM1[5]/MOSI0
78[1]
80[1]
82[1]
88[1]
90[1]
92[1]
42[2]
T9[1]
P1[24] — General purpose digital input/output pin.
USB_RX_DM1 — D− receive data for USB port 1 (OTG transceiver).
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
MOSI0 — Master Out Slave in for SSP0.
O
I/O
I/O
O
O
O
I/O
O
O
I
P1[25]/
T10[1]
R10[1]
T12[1]
T13[1]
U14[1]
P2[2]
P1[25] — General purpose digital input/output pin.
USB_LS1 — Low-speed status for USB port 1 (OTG transceiver).
USB_HSTEN1 — Host Enabled status for USB port 1.
MAT1[1] — Match output for Timer 1, channel 1.
P1[26] — General purpose digital input/output pin.
USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
CAP0[0] — Capture input for Timer 0, channel 0.
P1[27] — General purpose digital input/output pin.
USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).
USB_OVRCR1 — USB port 1 Over-Current status.
CAP0[1] — Capture input for Timer 0, channel 1.
P1[28] — General purpose digital input/output pin.
USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver).
PCAP1[0] — Capture input for PWM1, channel 0.
MAT0[0] — Match output for Timer 0, channel 0.
P1[29] — General purpose digital input/output pin.
USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver).
PCAP1[1] — Capture input for PWM1, channel 1.
MAT0[1] — Match output for Timer 0, channel 0.
P1[30] — General purpose digital input/output pin.
USB_PWRD2 — Power Status for USB port 2.
USB_LS1/
USB_HSTEN1/
MAT1[1]
P1[26]/
USB_SSPND1/
PWM1[6]/
CAP0[0]
P1[27]/
I/O
I
USB_INT1/
USB_OVRCR1/
CAP0[1]
I
I
P1[28]/
I/O
I/O
I
USB_SCL1/
PCAP1[0]/
MAT0[0]
O
I/O
I/O
I
P1[29]/
USB_SDA1/
PCAP1[1]/
MAT0[1]
O
I/O
I
P1[30]/
USB_PWRD2/
VBUS/AD0[4]
I
VBUS — Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
AD0[4] — A/D converter 0, input 4.
I
P1[31]/
USB_OVRCR2/
SCK1/AD0[5]
40[2]
P1[2]
I/O
I
P1[31] — General purpose digital input/output pin.
USB_OVRCR2 — Over-Current status for USB port 2.
SCK1 — Serial Clock for SSP1.
I/O
I
AD0[5] — A/D converter 0, input 5.
P2[0] to P2[31]
I/O
Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 2 pins depends upon the pin function selected
via the Pin Connect block.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
14 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P2[0]/PWM1[1]/
TXD1/
TRACECLK
154[1]
B17[1]
I/O
O
O
O
I/O
O
I
P2[0] — General purpose digital input/output pin.
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
TXD1 — Transmitter output for UART1.
TRACECLK — Trace Clock.
P2[1]/PWM1[2]/
RXD1/
PIPESTAT0
152[1]
150[1]
144[1]
142[1]
140[1]
138[1]
136[1]
134[1]
E14[1]
D15[1]
E16[1]
D17[1]
F16[1]
E17[1]
G16[1]
H15[1]
P2[1] — General purpose digital input/output pin.
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
RXD1 — Receiver input for UART1.
O
I/O
O
I
PIPESTAT0 — Pipeline Status, bit 0.
P2[2]/PWM1[3]/
CTS1/
PIPESTAT1
P2[2] — General purpose digital input/output pin.
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
CTS1 — Clear to Send input for UART1.
O
I/O
O
I
PIPESTAT1 — Pipeline Status, bit 1.
P2[3]/PWM1[4]/
DCD1/
PIPESTAT2
P2[3] — General purpose digital input/output pin.
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
DCD1 — Data Carrier Detect input for UART1.
PIPESTAT2 — Pipeline Status, bit 2.
O
I/O
O
I
P2[4]/PWM1[5]/
DSR1/
TRACESYNC
P2[4] — General purpose digital input/output pin.
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
DSR1 — Data Set Ready input for UART1.
TRACESYNC — Trace Synchronization.
O
I/O
O
O
O
I/O
I
P2[5]/PWM1[6]/
DTR1/
TRACEPKT0
P2[5] — General purpose digital input/output pin.
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
DTR1 — Data Terminal Ready output for UART1.
TRACEPKT0 — Trace Packet, bit 0.
P2[6]/PCAP1[0]/
RI1/TRACEPKT1
P2[6] — General purpose digital input/output pin.
PCAP1[0] — Capture input for PWM1, channel 0.
RI1 — Ring Indicator input for UART1.
I
O
I/O
I
TRACEPKT1 — Trace Packet, bit 1.
P2[7]/RD2/
RTS1/
TRACEPKT2
P2[7] — General purpose digital input/output pin.
RD2 — CAN2 receiver input (LPC2460 only).
RTS1 — Request to Send output for UART1.
TRACEPKT2 — Trace Packet, bit 2.
O
O
I/O
O
O
O
P2[8]/TD2/
TXD2/
TRACEPKT3
P2[8] — General purpose digital input/output pin.
TD2 — CAN2 transmitter output (LPC2460 only).
TXD2 — Transmitter output for UART2.
TRACEPKT3 — Trace Packet, bit 3.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
15 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P2[9]/
USB_CONNECT1/
RXD2/
132[1]
H16[1]
I/O
O
P2[9] — General purpose digital input/output pin.
USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch
an external 1.5 kΩ resistor under the software control. Used with the
SoftConnect USB feature.
EXTIN0
I
RXD2 — Receiver input for UART2.
I
EXTIN0 — External Trigger Input.
P2[10]/EINT0
110[6]
N15[6]
I/O
P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to
take over control of the part after a reset.
I
EINT0 — External interrupt 0 input.
P2[11]/EINT1/
MCIDAT1/
I2STX_CLK
108[6]
T17[6]
I/O
I
P2[11] — General purpose digital input/output pin.
EINT1 — External interrupt 1 input.
I/O
I/O
MCIDAT1 — Data line 1 for SD/MMC interface.
I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
106[6]
N14[6]
I/O
I
P2[12] — General purpose digital input/output pin.
EINT2 — External interrupt 2 input.
I/O
I/O
MCIDAT2 — Data line 2 for SD/MMC interface.
I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
102[6]
T16[6]
I/O
I
P2[13] — General purpose digital input/output pin.
EINT3 — External interrupt 3 input.
I/O
I/O
MCIDAT3 — Data line 3 for SD/MMC interface.
I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
P2[14]/CS2/
CAP2[0]/SDA1
91[6]
R12[6]
I/O
O
P2[14] — General purpose digital input/output pin.
CS2 — LOW active Chip Select 2 signal.
I
CAP2[0] — Capture input for Timer 2, channel 0.
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P2[15] — General purpose digital input/output pin.
CS3 — LOW active Chip Select 3 signal.
I/O
I/O
O
P2[15]/CS3/
99[6]
P13[6]
CAP2[1]/SCL1
I
CAP2[1] — Capture input for Timer 2, channel 1.
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P2[16] — General purpose digital input/output pin.
CAS — LOW active SDRAM Column Address Strobe.
P2[17] — General purpose digital input/output pin.
RAS — LOW active SDRAM Row Address Strobe.
P2[18] — General purpose digital input/output pin.
CLKOUT0 — SDRAM clock 0.
I/O
I/O
O
P2[16]/CAS
P2[17]/RAS
87[1]
95[1]
59[1]
67[1]
R11[1]
R13[1]
U3[1]
I/O
O
P2[18]/
CLKOUT0
I/O
O
P2[19]/
R7[1]
I/O
O
P2[19] — General purpose digital input/output pin.
CLKOUT1 — SDRAM clock 1.
CLKOUT1
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
16 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Pin description …continued
Symbol
Pin
Ball
Type Description
P2[20]/DYCS0
73[1]
T8[1]
I/O
O
P2[20] — General purpose digital input/output pin.
DYCS0 — SDRAM chip select 0.
P2[21]/DYCS1
81[1]
85[1]
U11[1]
U12[1]
I/O
O
P2[21] — General purpose digital input/output pin.
DYCS1 — SDRAM chip select 1.
P2[22]/DYCS2/
CAP3[0]/SCK0
I/O
O
P2[22] — General purpose digital input/output pin.
DYCS2 — SDRAM chip select 2.
I
CAP3[0] — Capture input for Timer 3, channel 0.
SCK0 — Serial clock for SSP0.
I/O
I/O
O
P2[23]/DYCS3/
CAP3[1]/SSEL0
64[1]
U5[1]
P2[23] — General purpose digital input/output pin.
DYCS3 — SDRAM chip select 3.
I
CAP3[1] — Capture input for Timer 3, channel 1.
SSEL0 — Slave Select for SSP0.
I/O
I/O
O
P2[24]/
CKEOUT0
53[1]
54[1]
57[1]
P5[1]
R4[1]
T4[1]
P2[24] — General purpose digital input/output pin.
CKEOUT0 — SDRAM clock enable 0.
P2[25]/
CKEOUT1
I/O
O
P2[25] — General purpose digital input/output pin.
CKEOUT1 — SDRAM clock enable 1.
P2[26]/
I/O
O
P2[26] — General purpose digital input/output pin.
CKEOUT2 — SDRAM clock enable 2.
CKEOUT2/
MAT3[0]/MISO0
O
MAT3[0] — Match output for Timer 3, channel 0.
MISO0 — Master In Slave Out for SSP0.
I/O
I/O
O
P2[27]/
CKEOUT3/
MAT3[1]/MOSI0
47[1]
P3[1]
P2[27] — General purpose digital input/output pin.
CKEOUT3 — SDRAM clock enable 3.
O
MAT3[1] — Match output for Timer 3, channel 1.
MOSI0 — Master Out Slave In for SSP0.
I/O
I/O
O
P2[28]/
DQMOUT0
49[1]
43[1]
31[1]
P4[1]
N3[1]
L4[1]
P2[28] — General purpose digital input/output pin.
DQMOUT0 — Data mask 0 used with SDRAM and static devices.
P2[29] — General purpose digital input/output pin.
DQMOUT1 — Data mask 1 used with SDRAM and static devices.
P2[30] — General purpose digital input/output pin.
DQMOUT2 — Data mask 2 used with SDRAM and static devices.
MAT3[2] — Match output for Timer 3, channel 2.
SDA2 — I2C2 data input/output (this is not an open-drain pin).
P2[31] — General purpose digital input/output pin.
DQMOUT3 — Data mask 3 used with SDRAM and static devices.
MAT3[3] — Match output for Timer 3, channel 3.
SCL2 — I2C2 clock input/output (this is not an open-drain pin).
P2[29]/
DQMOUT1
I/O
O
P2[30]/
DQMOUT2/
MAT3[2]/SDA2
I/O
O
O
I/O
I/O
O
P2[31]/
DQMOUT3/
MAT3[3]/SCL2
39[1]
N2[1]
O
I/O
I/O
P3[0] to P3[31]
P3[0]/D0
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 3 pins depends upon the pin function selected
via the Pin Connect block.
197[1]
B4[1]
I/O
I/O
P3[0] — General purpose digital input/output pin.
D0 — External memory data line 0.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
17 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
P3[1]/D1
Pin description …continued
Pin
Ball
Type Description
P3[1] — General purpose digital input/output pin.
D1 — External memory data line 1.
201[1]
B3[1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3[2]/D2
207[1]
3[1]
B1[1]
E4[1]
F2[1]
G1[1]
J1[1]
L1[1]
D8[1]
C5[1]
B2[1]
D5[1]
D4[1]
C1[1]
H2[1]
P3[2] — General purpose digital input/output pin.
D2 — External memory data line 2.
P3[3]/D3
P3[3] — General purpose digital input/output pin.
D3 — External memory data line 3.
P3[4]/D4
13[1]
17[1]
23[1]
27[1]
191[1]
199[1]
205[1]
208[1]
1[1]
P3[4] — General purpose digital input/output pin.
D4 — External memory data line 4.
P3[5]/D5
P3[5] — General purpose digital input/output pin.
D5 — External memory data line 5.
P3[6]/D6
P3[6] — General purpose digital input/output pin.
D6 — External memory data line 6.
P3[7]/D7
P3[7] — General purpose digital input/output pin.
D7 — External memory data line 7.
P3[8]/D8
P3[8] — General purpose digital input/output pin.
D8 — External memory data line 8.
P3[9]/D9
P3[9] — General purpose digital input/output pin.
D9 — External memory data line 9.
P3[10]/D10
P3[11]/D11
P3[12]/D12
P3[13]/D13
P3[14]/D14
P3[10] — General purpose digital input/output pin.
D10 — External memory data line 10.
P3[11] — General purpose digital input/output pin.
D11 — External memory data line 11.
P3[12] — General purpose digital input/output pin.
D12 — External memory data line 12.
7[1]
P3[13] — General purpose digital input/output pin.
D13 — External memory data line 13.
21[1]
P3[14] — General purpose digital input/output pin.
D14 — External memory data line 14. On POR, this pin serves as the
BOOT0 pin.
P3[15]/D15
28[1]
M1[1]
I/O
I/O
P3[15] — General purpose digital input/output pin.
D15 — External memory data line 15. On POR, this pin serves as the
BOOT1 pin.
BOOT[1:0] = 00 selects 8-bit external memory on CS1.
BOOT[1:0] = 01 is reserved. Do not use.
BOOT[1:0] = 10 selects 32-bit external memory on CS1.
BOOT[1:0] = 11 selects 16-bit external memory on CS1.
P3[16] — General purpose digital input/output pin.
D16 — External memory data line 16.
P3[16]/D16/
PWM0[1]/TXD1
137[1]
F17[1]
I/O
I/O
O
PWM0[1] — Pulse Width Modulator 0, output 1.
TXD1 — Transmitter output for UART1.
O
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
18 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P3[17]/D17/
PWM0[2]/RXD1
143[1]
F15[1]
I/O
I/O
O
P3[17] — General purpose digital input/output pin.
D17 — External memory data line 17.
PWM0[2] — Pulse Width Modulator 0, output 2.
RXD1 — Receiver input for UART1.
I
P3[18]/D18/
PWM0[3]/CTS1
151[1]
161[1]
167[1]
175[1]
195[1]
65[1]
C15[1]
B14[1]
A13[1]
C10[1]
C6[1]
T6[1]
I/O
I/O
O
P3[18] — General purpose digital input/output pin.
D18 — External memory data line 18.
PWM0[3] — Pulse Width Modulator 0, output 3.
CTS1 — Clear to Send input for UART1.
I
P3[19]/D19/
PWM0[4]/DCD1
I/O
I/O
O
P3[19] — General purpose digital input/output pin.
D19 — External memory data line 19.
PWM0[4] — Pulse Width Modulator 0, output 4.
DCD1 — Data Carrier Detect input for UART1.
P3[20] — General purpose digital input/output pin.
D20 — External memory data line 20.
I
P3[20]/D20/
PWM0[5]/DSR1
I/O
I/O
O
PWM0[5] — Pulse Width Modulator 0, output 5.
DSR1 — Data Set Ready input for UART1.
P3[21] — General purpose digital input/output pin.
D21 — External memory data line 21.
I
P3[21]/D21/
PWM0[6]/DTR1
I/O
I/O
O
PWM0[6] — Pulse Width Modulator 0, output 6.
DTR1 — Data Terminal Ready output for UART1.
P3[22] — General purpose digital input/output pin.
D22 — External memory data line 22.
O
P3[22]/D22/
PCAP0[0]/RI1
I/O
I/O
I
PCAP0[0] — Capture input for PWM0, channel 0.
RI1 — Ring Indicator input for UART1.
I
P3[23]/D23/
CAP0[0]/
PCAP1[0]
I/O
I/O
I
P3[23] — General purpose digital input/output pin.
D23 — External memory data line 23.
CAP0[0] — Capture input for Timer 0, channel 0.
PCAP1[0] — Capture input for PWM1, channel 0.
P3[24] — General purpose digital input/output pin.
D24 — External memory data line 24.
I
P3[24]/D24/
CAP0[1]/
PWM1[1]
58[1]
R5[1]
U2[1]
T3[1]
I/O
I/O
I
CAP0[1] — Capture input for Timer 0, channel 1.
PWM1[1] — Pulse Width Modulator 1, output 1.
P3[25] — General purpose digital input/output pin.
D25 — External memory data line 25.
O
P3[25]/D25/
MAT0[0]/
PWM1[2]
56[1]
I/O
I/O
O
MAT0[0] — Match output for Timer 0, channel 0.
PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26] — General purpose digital input/output pin.
D26 — External memory data line 26.
O
P3[26]/D26/
MAT0[1]/
PWM1[3]
55[1]
I/O
I/O
O
MAT0[1] — Match output for Timer 0, channel 1.
PWM1[3] — Pulse Width Modulator 1, output 3.
O
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
19 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
Pin description …continued
Pin
Ball
Type Description
P3[27]/D27/
CAP1[0]/
PWM1[4]
203[1]
A1[1]
I/O
I/O
I
P3[27] — General purpose digital input/output pin.
D27 — External memory data line 27.
CAP1[0] — Capture input for Timer 1, channel 0.
PWM1[4] — Pulse Width Modulator 1, output 4.
P3[28] — General purpose digital input/output pin.
D28 — External memory data line 28.
O
P3[28]/D28/
CAP1[1]/
PWM1[5]
5[1]
D2[1]
F3[1]
H3[1]
J3[1]
I/O
I/O
I
CAP1[1] — Capture input for Timer 1, channel 1.
PWM1[5] — Pulse Width Modulator 1, output 5.
P3[29] — General purpose digital input/output pin.
D29 — External memory data line 29.
O
P3[29]/D29/
MAT1[0]/
PWM1[6]
11[1]
19[1]
25[1]
I/O
I/O
O
MAT1[0] — Match output for Timer 1, channel 0.
PWM1[6] — Pulse Width Modulator 1, output 6.
P3[30] — General purpose digital input/output pin.
D30 — External memory data line 30.
O
P3[30]/D30/
MAT1[1]/
RTS1
I/O
I/O
O
MAT1[1] — Match output for Timer 1, channel 1.
RTS1 — Request to Send output for UART1.
P3[31] — General purpose digital input/output pin.
D31 — External memory data line 31.
O
P3[31]/D31/
MAT1[2]
I/O
I/O
O
MAT1[2] — Match output for Timer 1, channel 2.
P4[0] to P4[31]
I/O
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 4 pins depends upon the pin function selected
via the Pin Connect block.
P4[0]/A0
P4[1]/A1
P4[2]/A2
P4[3]/A3
P4[4]/A4
P4[5]/A5
P4[6]/A6
P4[7]/A7
P4[8]/A8
75[1]
U9[1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P4[0] — ]General purpose digital input/output pin.
A0 — External memory address line 0.
79[1]
U10[1]
T11[1]
U16[1]
R15[1]
R16[1]
M14[1]
L16[1]
J17[1]
P4[1] — General purpose digital input/output pin.
A1 — External memory address line 1.
83[1]
P4[2] — General purpose digital input/output pin.
A2 — External memory address line 2.
97[1]
P4[3] — General purpose digital input/output pin.
A3 — External memory address line 3.
103[1]
107[1]
113[1]
121[1]
127[1]
P4[4] — General purpose digital input/output pin.
A4 — External memory address line 4.
P4[5] — General purpose digital input/output pin.
A5 — External memory address line 5.
P4[6] — General purpose digital input/output pin.
A6 — External memory address line 6.
P4[7] — General purpose digital input/output pin.
A7 — External memory address line 7.
P4[8] — General purpose digital input/output pin.
A8 — External memory address line 8.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
20 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 4.
Symbol
P4[9]/A9
Pin description …continued
Pin
Ball
Type Description
P4[9] — General purpose digital input/output pin.
A9 — External memory address line 9.
131[1]
H17[1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
P4[10]/A10
P4[11]/A11
P4[12]/A12
P4[13]/A13
P4[14]/A14
P4[15]/A15
P4[16]/A16
P4[17]/A17
P4[18]/A18
P4[19]/A19
135[1]
145[1]
149[1]
155[1]
159[1]
173[1]
101[1]
104[1]
105[1]
111[1]
109[1]
G17[1]
F14[1]
C16[1]
B16[1]
B15[1]
A11[1]
U17[1]
P14[1]
P15[1]
P16[1]
R17[1]
P4[10] — General purpose digital input/output pin.
A10 — External memory address line 10.
P4[11] — General purpose digital input/output pin.
A11 — External memory address line 11.
P4[12] — General purpose digital input/output pin.
A12 — External memory address line 12.
P4[13] — General purpose digital input/output pin.
A13 — External memory address line 13.
P4[14] — General purpose digital input/output pin.
A14 — External memory address line 14.
P4[15] — General purpose digital input/output pin.
A15 — External memory address line 15.
P4[16] — General purpose digital input/output pin.
A16 — External memory address line 16.
P4[17] — General purpose digital input/output pin.
A17 — External memory address line 17.
P4[18] — General purpose digital input/output pin.
A18 — External memory address line 18.
P4[19] — General purpose digital input/output pin.
A19 — External memory address line 19.
P4[20] — General purpose digital input/output pin.
A20 — External memory address line 20.
SDA2 — I2C2 data input/output (this is not an open-drain pin).
SCK1 — Serial Clock for SSP1.
P4[20]/A20/
SDA2/SCK1
P4[21]/A21/
SCL2/SSEL1
115[1]
123[1]
129[1]
183[1]
M15[1]
K14[1]
J15[1]
B8[1]
P4[21] — General purpose digital input/output pin.
A21 — External memory address line 21.
SCL2 — I2C2 clock input/output (this is not an open-drain pin).
SSEL1 — Slave Select for SSP1.
P4[22]/A22/
TXD2/MISO1
P4[22] — General purpose digital input/output pin.
A22 — External memory address line 22.
TXD2 — Transmitter output for UART2.
I/O
I/O
I/O
I
MISO1 — Master In Slave Out for SSP1.
P4[23]/A23/
RXD2/MOSI1
P4[23] — General purpose digital input/output pin.
A23 — External memory address line 23.
RXD2 — Receiver input for UART2.
I/O
I/O
O
MOSI1 — Master Out Slave In for SSP1.
P4[24]/OE
P4[24] — General purpose digital input/output pin.
OE — LOW active Output Enable signal.
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Table 4.
Pin description …continued
Symbol
Pin
Ball
Type Description
P4[25]/WE
179[1]
B9[1]
I/O
O
P4[25] — General purpose digital input/output pin.
WE — LOW active Write Enable signal.
P4[26]/BLS0
P4[27]/BLS1
119[1]
139[1]
170[1]
L15[1]
G15[1]
C11[1]
I/O
O
P4[26] — General purpose digital input/output pin.
BLS0 — LOW active Byte Lane select signal 0.
P4[27] — General purpose digital input/output pin.
BLS1 — LOW active Byte Lane select signal 1.
P4 [28] — General purpose digital input/output pin.
BLS2 — LOW active Byte Lane select signal 2.
MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.
I/O
O
P4[28]/BLS2/
MAT2[0]/TXD3
I/O
O
O
O
P4[29]/BLS3/
MAT2[1]/RXD3
176[1]
B10[1]
I/O
O
P4[29] — General purpose digital input/output pin.
BLS3 — LOW active Byte Lane select signal 3.
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
O
I
P4[30]/CS0
P4[31]/CS1
ALARM
187[1]
193[1]
37[8]
B7[1]
A4[1]
N1[8]
I/O
O
P4[30] — General purpose digital input/output pin.
CS0 — LOW active Chip Select 0 signal.
I/O
O
P4[31] — General purpose digital input/output pin.
CS1 — LOW active Chip Select 1 signal.
O
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when
a RTC alarm is generated.
USB_D−2
52
9[1]
U1
F4[1]
I/O
I
USB_D−2 — USB port 2 bidirectional D− line.
DBGEN
DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO
TDI
2[1]
4[1]
6[1]
8[1]
10[1]
D3[1]
C2[1]
E3[1]
D1[1]
E2[1]
O
I
TDO — Test data out for JTAG interface.
TDI — Test data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TMS
TRST
TCK
I
I
I
TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK
206[1]
C3[1]
I/O
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT
RESET
29
K3
O
I
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2420/2460
being in Reset state.
35[7]
M2[7]
external reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
XTAL2
RTCX1
RTCX2
44[8]
46[8]
34[8]
36[8]
M4[8]
N4[8]
K2[8]
L2[8]
I
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
O
I
Input to the RTC oscillator circuit.
O
Output from the RTC oscillator circuit.
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Table 4.
Symbol
VSSIO
Pin description …continued
Pin Ball
Type Description
I ground: 0 V reference for the digital I/O pins.
33, 63, L3, T5,
77, 93, R9,
114,
133,
148,
169,
189,
200[8]
P12,
N16,
H14,
E15,
A12,
B6, A2[8]
VSSCORE
VSSA
32, 84, K4,P10, I
ground: 0 V reference for the core.
172[8]
22[8]
D12[8]
J2[8]
I
I
analog ground: 0 V reference. This should nominally be the same
voltage as VSSIO/VSSCORE, but should be isolated to minimize noise and
error.
VDD(3V3)
15, 60, G3,
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
71, 89, P6, P8,
112,
125,
146,
165,
181,
198[8]
U13,
P17,
K16,
C17,
B13,
C9,
D7[8]
n.c.
30, 117, J4, L14,
141[8] G14[8]
I
I
not connected pins: These pins must be left unconnected (floating).
VDD(DCDC)(3V3)
26, 86, H4,
3.3 V DC-to-DC converter supply voltage: This is the power supply for
the on-chip DC-to-DC converter.
174[8]
P11,
D11[8]
VDDA
20[8]
G4[8]
K1[8]
M3[8]
I
I
I
analog 3.3 V pad supply voltage: This should be nominally the same
voltage as VDD(3V3) but should be isolated to minimize noise and error.
This voltage is used to power the ADC and DAC.
VREF
VBAT
24[8]
38[8]
ADC reference: This should be nominally the same voltage as VDD(3V3)
but should be isolated to minimize noise and error. The level on this pin is
used as a reference for ADC and DAC.
RTC power supply: 3.3 V on this pin supplies the power to the RTC.
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C-bus lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[8] Pad provides special analog functionality.
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7. Functional description
7.1 Architectural overview
The LPC2420/2460 microcontroller consists of an ARM7TDMI-S CPU with emulation
support, the ARM7 local bus for closely coupled, high-speed access to the majority of
on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and
external memory, and the AMBA APB for connection to other on-chip peripheral functions.
The microcontroller permanently configures the ARM7TDMI-S processor for little-endian
byte order.
The LPC2460 only implements two AHB in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the VIC, GPDMA controller, and EMC.
The second AHB (LPC2460 only), referred to as AHB2, includes only the Ethernet block
and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the
secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space
into off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB. The
AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a
2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is
allocated a 16 kB address space within the APB address space.
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• the standard 32-bit ARM set
• a 16-bit Thumb set
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The Thumb set’s 16-bit instruction length allows it to approach higher density compared to
standard ARM code while retaining most of the ARM’s performance.
7.2 On-chip SRAM
The LPC2420/2460 includes a SRAM memory of 64 kB reserved for the ARM processor
exclusive use. This RAM may be used for code and/or data storage and may be accessed
as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller (LPC2460 only) and a
16 kB SRAM associated with the second AHB can be used both for data and code
storage, too. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is
battery powered and retains the content in the absence of the main power supply.
7.3 Memory map
The LPC2420/2460 memory map incorporates several distinct regions as shown in
Table 5 and Figure 4.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in boot
ROM or SRAM (see Section 7.25.6).
Table 5.
LPC2420/2460 memory usage and details
Address range General use
Address range details and description
0x0000 0000 to fast I/O
0x3FFF FFFF
0x3FFF C000 to 0x3FFF FFFF fast GPIO registers
0x4000 0000 to on-chip RAM
0x7FFF FFFF
0x4000 0000 to 0x4000 FFFF
RAM (64 kB)
0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)
(LPC2460 only)
0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)
0x8000 0000 to off-chip memory Four static memory banks, 16 MB each
0xDFFF FFFF
0x8000 0000 to 0x80FF FFFF
0x8100 0000 to 0x81FF FFFF
0x8200 0000 to 0x82FF FFFF
0x8300 0000 to 0x83FF FFFF
static memory bank 0
static memory bank 1
static memory bank 2
static memory bank 3
Four dynamic memory banks, 256 MB each
0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0
0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1
0xC000 0000 to 0xCFFF FFFF dynamic memory bank 2
0xD000 0000 to 0xDFFF FFFF dynamic memory bank 3
0xE000 0000 to APB peripherals 36 peripheral blocks, 16 kB each
0xEFFF FFFF
0xF000 0000 to AHB peripherals
0xFFFF FFFF
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4.0 GB
0xFFFF FFFF
AHB PERIPHERALS
3.75 GB
0xF000 0000
0xE000 0000
APB PERIPHERALS
3.5 GB
EXTERNAL STATIC AND DYNAMIC MEMORY
2.0 GB
0x8000 0000
0x7FFF FFFF
BOOT ROM
RESERVED ADDRESS SPACE
ON-CHIP STATIC RAM
SPECIAL REGISTERS
1.0 GB
0x4000 0000
0x3FFF FFFF
0x3FFF 8000
RESERVED ADDRESS SPACE
0.0 GB
0x0000 0000
002aad316
Fig 4. LPC2420/2460 memory map
7.4 Interrupt controller
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be
programmed as FIQ or vectored IRQ types. The programmable assignment scheme
means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs
the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ
latency is achieved when only one request is classified as FIQ, because then the FIQ
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service routine can simply start dealing with that device. But if more than one request is
assigned to the FIQ class, the FIQ service routine can read a word from the VIC that
identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a
programmable interrupt priority. When more than one interrupt is assigned the same
priority and occur simultaneously, the one connected to the lowest numbered VIC channel
will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
7.4.1 Interrupt sources
Each peripheral device has one interrupt line connected to the VIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both. Such
interrupt request coming from port 0 and/or port 2 will be combined with the EINT3
interrupt requests.
7.5 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.6 External memory controller
The LPC2420/2460 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral
offering support for asynchronous static memory devices such as RAM, ROM, and flash.
In addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
7.6.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 24 address lines wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
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– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048, 4096, and 8192 row address synchronous memory parts.
That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per
device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.7 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2420/2460
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
7.7.1 Features
• Two DMA channels. Each channel can support a unidirectional transfer.
• The GPDMA can transfer data between the 16 kB SRAM, external memory, and
peripherals such as the SD/MMC, two SSPs, and the I2S interface.
• Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
• AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
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• One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
• Internal four-word FIFO per channel.
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC2420/2460 use accelerated GPIO functions:
• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a falling
edge, or both. The edge detection is asynchronous, so it may operate when clocks are not
present such as during Power-down mode. Each enabled interrupt can be used to wake
the chip up from Power-down mode.
7.8.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• Backward compatibility with other earlier devices is maintained with legacy port 0 and
port 1 registers appearing at the original addresses on the APB.
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7.9 Ethernet (LPC2460 only)
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2420/2460 takes place on a different AHB subsystem, effectively separating
Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip
memory via the EMC, as well as the SRAM located on another AHB. However, using
memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet
access to memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
7.9.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
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– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
7.10 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC2420/2460 USB interface includes a device, Host, and OTG Controller. Details on
typical USB interfacing solutions can be found in Section 11.1 “Suggested USB interface
solutions” on page 60.
7.10.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.10.1.1 Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, LPC2420/2460 can enter one of the reduced
power modes and wake up on USB activity.
• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.10.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the OHCI specification.
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7.10.2.1 Features
• OHCI compliant.
• Two downstream ports.
• Supports per-port power switching.
7.10.3 USB OTG Controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only
I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus
interface controls an external OTG transceiver.
7.10.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.11 CAN controller and acceptance filters (LPC2460 only)
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.11.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
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• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
7.12 10-bit ADC
The LPC2420/2460 contains one ADC. It is a single 10-bit successive approximation ADC
with eight channels.
7.12.1 Features
• 10-bit successive approximation ADC
• Input multiplexing among 8 pins
• Power-down mode
• Measurement range 0 V to Vi(VREF)
• 10-bit conversion time ≥ 2.44 µs
• Burst conversion mode for single or multiple inputs
• Optional conversion on transition of input pin or Timer Match signal
• Individual result registers for each ADC channel to reduce interrupt overhead
7.13 10-bit DAC
The DAC allows the LPC2420/2460 to generate a variable analog output. The maximum
output value of the DAC is Vi(VREF)
.
7.13.1 Features
• 10-bit DAC
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable output drive
7.14 UARTs
The LPC2420/2460 contains four UARTs. In addition to standard transmit and receive
data lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.14.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
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• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
• UART3 includes an IrDA mode to support infrared communication.
7.15 SPI serial I/O controller
The LPC2420/2460 contains one SPI controller. SPI is a full duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
7.15.1 Features
• Compliant with SPI specification
• Synchronous, Serial, Full Duplex Communication
• Combined SPI master and slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 bits to 16 bits per transfer
7.16 SSP serial I/O controller
The LPC2420/2460 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.16.1 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave
mode) of the input clock rate
• DMA transfers supported by GPDMA
7.17 SD/MMC card interface
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
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7.17.1 Features
• The MCI provides all functions specific to the SD/MMC memory card. These include
the clock generation unit, power management control, and command and data
transfer.
• Conforms to Multimedia Card Specification v2.11.
• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
• Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
• DMA supported through the GPDMA controller.
7.18 I2C-bus serial I/O controller
The LPC2420/2460 contains three I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can
be controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2420/2460 supports bit rates up to 400 kbit/s (Fast
I2C-bus).
7.18.1 Features
• I2C0 is a standard I2C compliant bus interface with open-drain pins.
• I2C1 and I2C2 use standard I/O pins and do not support powering off of individual
devices connected to the same bus lines.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
7.19 I2S-bus serial I/O controllers
The I2S-bus provides a standard communication interface for digital audio applications.
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The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S connection has one master, which is always the
master, and one slave. The I2S interface on the LPC2420/2460 provides a separate
transmit and receive channel, each of which can operate as either a master or a slave.
7.19.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected to
the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
7.20 General purpose 32-bit timers/external event counters
The LPC2420/2460 includes four 32-bit Timer/Counters. The Timer/Counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts or perform other actions at specified timer values, based on
four match registers. The Timer/Counter also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.20.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Counter or Timer operation.
• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
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– Do nothing on match.
7.21 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2420/2460. The Timer is designed to
count cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. A
dedicated match register controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, a dedicated match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
7.21.1 Features
• LPC2420/2460 has two PWMs with the same operational features. These may be
operated in a synchronized fashion by setting them both up to run at the same rate,
then enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave
for this use.
• Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
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• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
7.22 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.22.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and
wiring, for increased reliability.
7.23 RTC and battery RAM
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. It uses little power in Power-down mode. On the LPC2420/2460, the RTC
can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider
based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT,
which can be connected to a battery or to the same 3.3 V supply used by the rest of the
device.
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The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that can be used by external hardware to restore chip power
and resume operation.
7.23.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• An alarm output pin is included to assist in waking up when the chip has had power
removed to all functions except the RTC and Battery RAM.
• Periodic interrupts can be generated from increments of any field of the time registers,
and selected fractional second values. This enhancement enables the RTC to be
used as a System Timer.
• 2 kB data SRAM powered by VBAT.
• RTC and Battery RAM power supply is isolated from the rest of the chip.
7.24 Clocking and power control
7.24.1 Crystal oscillators
The LPC2420/2460 includes three independent oscillators. These are the Main Oscillator,
the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more
than one purpose as required in a particular application. Any of the three clock sources
can be chosen by software to drive the PLL and ultimately the CPU.
Following reset, the LPC2420/2460 will operate from the Internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
7.24.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is
trimmed to 1 % accuracy.
Upon power-up or any chip reset, the LPC2420/2460 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.24.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency can
be boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
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PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 7.24.2 for additional information.
7.24.1.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the
RTC oscillator can be used to drive the PLL and the CPU.
7.24.2 PLL
The PLL accepts an input clock frequency in the range of 32 kHz to 24 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 24 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to lock, then connect to the PLL as a clock source.
7.24.3 Wake-up timer
The LPC2420/2460 begins operation at power-up and when awakened from Power-down
mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to
resume quickly. If the main oscillator or the PLL is needed by the application, software will
need to enable these features and wait for them to stabilize before they are used as a
clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
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7.24.4 Power control
The LPC2420/2460 supports a variety of power control features. There are three special
modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode.
The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, Peripheral power control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Each of the peripherals
has its own clock divider which provides even better power control.
The LPC2420/2460 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the RTC and a small SRAM,
referred to as the Battery RAM.
7.24.4.1 Idle mode
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.24.4.2 Sleep mode
In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The
32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value.
On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the
code execution and peripherals activities will resume after 4 cycles expire. If the main
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
7.24.4.3 Power-down mode
Power-down mode does everything that Sleep mode does but also turns off the IRC
oscillator.
On the wake-up from Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 µs to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. The customers need
to reconfigure the PLL and clock dividers accordingly after a wake-up from Power-down
mode.
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7.24.4.4 Power domains
The LPC2420/2460 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the Battery
RAM.
On the LPC2420/2460, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
VDD(DCDC)(3V3) pins power the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
7.25 System control
7.25.1 Reset
Reset has four sources on the LPC2420/2460: the RESET pin, the Watchdog reset,
power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wake-up timer (see description in Section 7.24.3 “Wake-up
timer”), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, and a fixed number of clocks have passed.
Once the internal reset is removed, all of the processor and peripheral registers have
been initialized to predetermined values and the LPC2420/2460 continues with booting
from an external static memory.
7.25.2 Boot process
The processor always boots from the off-chip static memory bank 1, executing code from
address 0x8100 0000 (see Table 5 “LPC2420/2460 memory usage and details”). During
the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled,
and the external memory banks 0 and 1 are configured with the same data bus width. The
data bus width is determined by the setting of the two boot pins. Unused address pins are
configured as GPIO. See Section 11.2 “Suggested boot memory interface solutions” for
an example of address and data bus interfacing.
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Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.
The user code residing in the external boot memory must be linked to execute from
address location 0x8000 0000.
When booting from external memory, the interrupt vectors are mapped to the bottom of
the external memory. Once booting is over, the application must map interrupt vectors to
the proper domain.
7.25.3 Brownout detection
The LPC2420/2460 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset
(if this reset source is enabled in software) to inactivate the LPC2420/2460 when the
voltage on the VDD(3V3) pins falls below 2.65 V. The BOD circuit maintains this reset down
below 1 V, at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
7.25.4 AHB
The LPC2460 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1, is
implemented on LPC2420 as well and includes the Vectored Interrupt Controller, GPDMA
controller, USB interface, and 16 kB SRAM.
The second AHB, referred to as AHB2, is implemented on LPC2460 only and includes
only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is
provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion
of Ethernet buffer space into off-chip memory or unused space in memory residing on
AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
7.25.5 External interrupt inputs
The LPC2420/2460 includes up to 68 edge sensitive interrupt inputs combined with up to
four level sensitive external interrupt inputs as selectable pin functions. The external
interrupt inputs can optionally be used to wake up the processor from Power-down mode.
7.25.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
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Flashless 16-bit/32-bit microcontroller
7.26 Emulation and debugging
The LPC2420/2460 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
7.26.1 EmbeddedICE
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core.
The DCC allows the JTAG port to be used for sending and receiving data without affecting
the normal program flow. The DCC data and control registers are mapped in to addresses
in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.
7.26.2 Embedded trace
Since the LPC2420/2460 have significant amounts of on-chip memories, it is not possible
to determine how the processor core is operating simply by observing the external pins.
The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace port. A software debugger allows
configuration of the ETM using a JTAG interface and displays the trace information that
has been captured.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
Trace Port Analyzer captures the trace information under software debugger control. The
trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)
shows the flow of execution of the processor and provides a list of all the instructions that
were executed. Instruction trace is significantly compressed by only broadcasting branch
addresses as well as a set of status signals that indicate the pipeline status on a cycle by
cycle basis. Trace information generation can be controlled by selecting the trigger
resource. Trigger resources include address comparators, counters and sequencers.
Since trace information is compressed the software debugger requires a static image of
the code being executed. Self-modifying code can not be traced because of this
restriction.
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Preliminary data sheet
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
7.26.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2420/2460 contain a specific configuration of
RealMonitor software programmed into the on-chip ROM memory.
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Preliminary data sheet
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NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
VDD(3V3)
supply voltage (3.3 V)
core and external
rail
3.0
3.6
V
VDD(DCDC)(3V3) DC-to-DC converter supply voltage
(3.3 V)
3.0
3.6
V
VDDA
analog 3.3 V pad supply voltage
input voltage on pin VBAT
input voltage on pin VREF
analog input voltage
−0.5
−0.5
−0.5
−0.5
+4.6
+4.6
+4.6
+5.1
V
V
V
V
Vi(VBAT)
Vi(VREF)
VIA
for the RTC
on ADC related
pins
[2]
VI
input voltage
5 V tolerant I/O
pins; only valid
when the VDD(3V3)
supply voltage is
present
−0.5
+6.0
V
[2][3]
other I/O pins
−0.5
VDD(3V3)
0.5
+
V
[4]
[4]
[5]
IDD
supply current
per supply pin
per ground pin
-
100
100
+150
1.5
mA
mA
°C
ISS
ground current
-
Tstg
storage temperature
total power dissipation (per package)
−65
Ptot(pack)
based on package
heat transfer, not
device power
-
W
consumption
[6]
Vesd
electrostatic discharge voltage
human body
−2000
+2000
V
model; all pins
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSSIO/VSSCORE
unless otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The peak current is limited to 25 times the corresponding maximum current.
[5] Dependent on package type.
[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
9. Static characteristics
Table 7.
Static characteristics
Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
3.0
3.0
Typ[1]
3.3
Max
3.6
Unit
V
VDD(3V3)
supply voltage (3.3 V) core and external rail
VDD(DCDC)(3V3)
DC-to-DC converter
supply voltage (3.3 V)
3.3
3.6
V
VDDA
analog 3.3 V pad
supply voltage
3.0
2.0
2.5
3.3
3.3
3.3
3.6
V
V
V
[2]
Vi(VBAT)
Vi(VREF)
input voltage on pin
VBAT
3.6
input voltage on pin
VREF
VDDA
Standard port pins, RESET, RTCK
IIL
LOW-level input
current
VI = 0 V; no pull-up
-
-
-
-
-
-
-
-
3
µA
µA
µA
mA
IIH
HIGH-level input
current
VI = VDD(3V3); no pull-down
3
IOZ
Ilatch
OFF-state output
current
VO = 0 V; VO = VDD(3V3)
no pull-up/down
;
3
I/O latch-up current
−(0.5VDD(3V3)) < VI <
100
(1.5VDD(3V3));
Tj < 125 °C
[3][4][5]
[6]
VI
input voltage
pin configured to provide a
digital function
0
-
5.5
V
VO
output voltage
output active
0
-
-
VDD(3V3)
-
V
V
VIH
HIGH-level input
voltage
2.0
VIL
LOW-level input
voltage
-
-
0.8
V
Vhys
VOH
hysteresis voltage
0.4
-
-
-
-
V
V
[7]
[7]
[7]
[7]
[8]
HIGH-level output
voltage
IOH = −4 mA
VDD(3V3)
0.4
−
VOL
IOH
LOW-level output
voltage
IOL = −4 mA
-
-
-
-
-
0.4
-
V
HIGH-level output
current
VOH = VDD(3V3) − 0.4 V
VOL = 0.4 V
−4
4
-
mA
mA
mA
IOL
LOW-level output
current
-
IOHS
HIGH-level
VOH = 0 V
−45
short-circuit output
current
[8]
[9]
IOLS
LOW-level short-circuit VOL = VDDA
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
10
−15
0
50
−50
0
150
−85
0
µA
µA
µA
VI = 0 V
[9]
VDD(3V3) < VI < 5 V
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Preliminary data sheet
Rev. 03 — 20 November 2008
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 7.
Static characteristics …continued
Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) = 3.3 V;
converter supply
current (3.3 V)
Tamb = 25 °C; code
while(1){}
executed from the on-chip
SRAM; no peripherals
enabled; PCLK = CCLK
CCLK = 10 MHz
CCLK = 72 MHz
-
-
<tbd>
<tbd>
-
-
mA
mA
all peripherals enabled;
PCLK = CCLK / 8
CCLK = 10 MHz
CCLK = 72 MHz
-
-
<tbd>
<tbd>
-
-
mA
mA
all peripherals enabled;
PCLK = CCLK
CCLK = 10 MHz
CCLK = 72 MHz
-
-
<tbd>
<tbd>
-
-
mA
mA
IDD(DCDC)pd(3V3) power-down mode
DC-to-DC converter
V
DD(DCDC)(3V3) = 3.3 V;
T
amb = 25 °C
supply current (3.3 V)
-
-
-
150
20
-
-
-
µA
µA
µA
[10]
[10]
IBATact
active mode battery
supply current
DC-to-DC converter on
DC-to-DC converter off
28
I2C-bus pins (P0[27] and P0[28])
VIH
HIGH-level input
voltage
0.7VDD(3V3)
-
-
-
-
V
V
VIL
LOW-level input
voltage
0.3VDD(3V3)
Vhys
VOL
hysteresis voltage
-
-
0.5VDD(3V3)
-
-
V
V
[7]
LOW-level output
voltage
IOLS = 3 mA
0.4
[11]
ILI
input leakage current VI = VDD(3V3)
VI = 5 V
-
-
2
4
µA
µA
10
22
Oscillator pins
Vi(XTAL1)
input voltage on pin
XTAL1
0
0
0
0
-
-
-
-
1.8
1.8
1.8
1.8
V
V
V
V
Vo(XTAL2)
Vi(RTCX1)
Vo(RTCX2)
output voltage on pin
XTAL2
input voltage on pin
RTCX1
output voltage on pin
RTCX2
USB pins
IOZ
OFF-state output
current
0 V < VI < 3.3 V
-
-
-
-
±10
µA
VBUS
bus supply voltage
5.25
V
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
48 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 7.
Static characteristics …continued
Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VDI
differential input
|(D+) − (D−)|
0.2
-
-
V
sensitivity voltage
VCM
differential common
mode voltage range
includes VDI range
0.8
0.8
-
-
2.5
2.0
V
V
Vth(rs)se
single-ended receiver
switching threshold
voltage
VOL
LOW-level output
voltage for
low-/full-speed
RL of 1.5 kΩ to 3.6 V
RL of 15 kΩ to GND
pin to GND
-
-
-
0.18
3.5
V
V
VOH
HIGH-level output
voltage (driven) for
low-/full-speed
2.8
Ctrans
ZDRV
transceiver
capacitance
-
-
-
20
pF
[12]
driver output
with 33 Ω series resistor;
36
44.1
Ω
impedance for driver
which is not
steady state drive
high-speed capable
Rpu
pull-up resistance
SoftConnect = ON
1.1
-
1.9
kΩ
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages
[2] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[3] Including voltage on outputs in 3-state mode.
[4] VDD(3V3) supply voltages must be present.
[5] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[6] Please also see the errata note mentioned in errata sheet.
[7] Accounts for 100 mV voltage drop in all supply lines.
[8] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[9] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[10] On pin VBAT.
[11] To VSSIO/VSSCORE
[12] Includes external resistors of 18 Ω ± 1 % on D+ and D−.
Table 8.
ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
VIA
Parameter
Conditions
Min
Typ
Max
Unit
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
VDDA
1
V
Cia
pF
[1][2][3]
[1][4]
ED
-
±1
LSB
LSB
LSB
EL(adj)
EO
-
±2
[1][5]
-
±3
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
49 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 8.
ADC static characteristics …continued
VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
EG
Parameter
gain error
Conditions
Min
Typ
Max
±0.5
±4
Unit
%
[1][6]
[1][7]
[8]
-
-
-
-
-
-
ET
absolute error
LSB
kΩ
Rvsi
voltage source interface
resistance
40
[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 5.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.
[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
and the ideal transfer curve. See Figure 5.
[8] See Figure 6.
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
IA
(LSB
)
ideal
offset error
E
O
V
− V
DDA SSA
1 LSB =
1024
002aac046
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 5. ADC characteristics
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
LPC2XXX
R
vsi
20 kΩ
AD0[y]
AD0[y]
SAMPLE
3 pF
5 pF
V
EXT
V
V
SSIO, SSCORE
002aad586
Fig 6. Suggested ADC interface - LPC2420/2460 AD0[y] pin
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
52 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
10. Dynamic characteristics
Table 9.
Dynamic characteristics of USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3),unless otherwise specified.
Symbol
Parameter
rise time
fall time
Conditions
10 % to 90 %
10 % to 90 %
tr / tf
Min
8.5
7.7
-
Typ
Max
13.8
13.7
109
Unit
ns
tr
-
-
-
tf
ns
tFRFM
differential rise and fall time
matching
%
VCRS
output signal crossover voltage
source SE0 interval of EOP
1.3
160
−2
-
-
-
2.0
175
+5
V
tFEOPT
tFDEOP
see Figure 8
ns
ns
source jitter for differential transition see Figure 8
to SE0 transition
tJR1
receiver jitter to next transition
−18.5
−9
-
-
-
+18.5
ns
ns
ns
tJR2
receiver jitter for paired transitions
EOP width at receiver
10 % to 90 %
+9
-
[1]
[1]
tEOPR1
must reject as
EOP; see
Figure 8
40
tEOPR2
EOP width at receiver
must accept as
EOP; see
82
-
-
ns
Figure 8
[1] Characterized but not implemented as production test. Guaranteed by design.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
53 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 10. Dynamic characteristics
Tamb = −40 °C to +85 °C for commercial applications; VDD(3V3) over specified ranges.[1]
Symbol
External clock
fosc
Parameter
Conditions
Min
Typ[2]
Max
Unit
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
1
-
-
-
-
-
-
24
MHz
ns
Tcy(clk)
tCHCX
42
1000
T
T
-
cy(clk) × 0.4
-
ns
tCLCX
cy(clk) × 0.4
-
ns
tCLCH
5
5
ns
tCHCL
clock fall time
-
ns
I2C-bus pins (P0[27] and P0[28])
[3]
tf(o)
output fall time
VIH to VIL
20 + 0.1 × Cb
-
-
-
ns
ns
SSP interface
tsu(SPI_MISO)
SPI_MISO set-up time
Tamb =25 °C;
measured in
SPI Master
mode; see
Figure 9
-
11
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
54 of 73
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Table 11. Dynamic characteristics: Static external memory interface
CL = 30 pF, Tamb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHz
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Common to read and write cycles[1]
tCSLAV
CS LOW to address valid
time
−0.29
0.20
2.54
ns
Read cycle parameters[1][2]
tOELAV
OE LOW to address valid
−0.29
0.20
2.54
ns
time
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
−0.78 + Tcy(CCLK) × WAITOEN 0 + Tcy(CCLK) × WAITOEN
0.49 + Tcy(CCLK) × WAITOEN ns
(WAITRD − WAITOEN + 1) × (WAITRD − WAITOEN + 1) × (WAITRD − WAITOEN + 1) × ns
cy(CCLK) − 8.11 cy(CCLK) − 9.57 cy(CCLK) − 12.70
[3][4]
[5]
T
T
T
th(D)
data input hold time
1.29
4.22
0
5.20
0.20
2.44
ns
ns
ns
tCSHOEH CS HIGH to OE HIGH time
−0.49
−0.20
tOEHANV OE HIGH to address invalid
time
0.20
tOELOEH OE LOW to OE HIGH time
−0.59 + (WAITRD −
0 + (WAITRD − WAITOEN + 0.10 + (WAITRD −
WAITOEN + 1) × Tcy(CCLK)
1) × Tcy(CCLK)
WAITOEN + 1) × Tcy(CCLK)
tBLSLAV
BLS LOW to address valid
time
−0.39
0
2.54
ns
ns
tCSHBLSH CS HIGH to BLS HIGH time
−0.88
0.49
0.68
Write cycle parameters[1][6]
tCSLWEL
CS LOW to WE LOW time
−0.88 + Tcy(CCLK) × (1 +
0.10 + Tcy(CCLK) × (1 +
0.20 + Tcy(CCLK) × (1 +
ns
WAITWEN)
WAITWEN)
WAITWEN)
tCSLBLSL CS LOW to BLS LOW time
−0.88
0.68
0
0.49
0.98
5.86
4.79
ns
ns
ns
ns
tWELDV
tCSLDV
WE LOW to data valid time
CS LOW to data valid time
2.54
2.64
[3]
[3]
[3]
tWELWEH WE LOW to WE HIGH time
−0.78 + Tcy(CCLK)
×
0 + Tcy(CCLK) × (WAITWR −
0.10 + Tcy(CCLK)
(WAITWR − WAITWEN + 1)
×
(WAITWR − WAITWEN + 1) WAITWEN + 1)
−0.88 + Tcy(CCLK) 0 + Tcy(CCLK) × (WAITWR −
(WAITWR − WAITWEN + 3) WAITWEN + 3)
0 + Tcy(CCLK) 0.20 + Tcy(CCLK)
tBLSLBLSH BLS LOW to BLS HIGH
time
×
0.59 + Tcy(CCLK)
(WAITWR − WAITWEN + 3)
×
ns
ns
tWEHANV WE HIGH to address invalid
time
2.74 + Tcy(CCLK)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 11. Dynamic characteristics: Static external memory interface …continued
CL = 30 pF, Tamb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHz
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[3]
[3]
[3]
tWEHDNV WE HIGH to data invalid
time
0.78
2.54
5.96
ns
tBLSHANV BLS HIGH to address
invalid time
−0.29
0.20
2.54
2.54
5.37
ns
ns
tBLSHDNV BLS HIGH to data invalid
time
0
[1] VOH = 2.5 V, VOL = 0.2 V.
[2] VIH = 2.5 V, VIL = 0.5 V.
[3] Tcy(CCLK) = 1⁄CCLK
.
[4] Latest of address valid, CS LOW, OE LOW to data valid.
[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.
[6] Byte lane state bit (PB) = 1.
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
Table 12. Dynamic characteristics: Dynamic external memory interface
CL = 30 pF, Tamb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHz
Symbol
Common
td(SV)
Parameter
Conditions
Min
Typ
Max
Unit
chip select valid delay time
chip select hold time
-
1.05
1.02
1.51
1.51
0.98
0.97
0.84
0.84
0.95
1
1.76
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(S)
0.1
-
-
td(RASV)
th(RAS)
td(CASV)
th(CAS)
td(WV)
th(W)
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
1.95
0.5
-
-
1.27
0.1
-
-
1.95
write hold time
0.1
-
-
td(GV)
output enable valid delay time
output enable hold time
1.86
th(G)
0.1
-
-
td(AV)
address valid delay time
address hold time
0.87
0.81
1.95
-
th(A)
0.1
Read cycle parameters
tsu(D) data input set-up time
th(D) data input hold time
Write cycle parameters
td(QV) data output valid delay time
th(Q) data output hold time
0.51
0.57
2.24
2.41
-
-
ns
ns
-
2.65
2.61
4.36
-
ns
ns
0.49
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10.1 Timing
Flashless 16-bit/32-bit microcontroller
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 7. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
t
PERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: t
FEOPT
differential data to
SE0/EOP skew
n × t
+ t
PERIOD
FDEOP
receiver EOP width: t
, t
EOPR1 EOPR2
002aab561
Fig 8. Differential data-to-EOP transition skew and EOP width
shifting edges
SCK
sampling edges
MOSI
MISO
t
su(SPI_MISO)
002aad326
Fig 9. MISO line set-up time in SSP Master mode
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
t
t
CSHOEH
CSLAV
CS
addr
data
t
t
h(D)
am
t
CSLOEL
t
t
OEHANV
OELAV
t
OELOEH
OE
t
CSHBLSH
t
BLSLAV
BLS
002aad955
Fig 10. External memory read access
CS
t
AVCSL
t
WELWEH
t
CSLWEL
t
BLSLBLSH
BLS/WE
addr
t
WEHANV
t
t
WELDV
CSLBLSL
t
BLSHANV
t
WEHDNV
t
CSLDV
t
BLSHDNV
data
OE
002aad956
Fig 11. External memory write access
LPC2420_60_3
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Preliminary data sheet
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
reference
clock
t
t
h(XXX)
d(XXX)
output signal (O)
input signal (I)
t
t
su(D)
h(D)
002aad636
Fig 12. Signal timing
11. Application information
11.1 Suggested USB interface solutions
V
DD(3V3)
USB_UP_LED
USB_CONNECT
LPC24XX
soft-connect switch
R1
1.5 kΩ
V
BUS
R
R
= 33 Ω
= 33 Ω
S
USB-B
connector
USB_D+
S
USB_D−
V
V
SSIO, SSCORE
002aad587
Fig 13. LPC2420/2460 USB interface on a self-powered device
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Preliminary data sheet
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
V
DD(3V3)
R2
LPC24XX
R1
1.5 kΩ
USB_UP_LED
V
BUS
USB-B
connector
R
R
= 33 Ω
= 33 Ω
S
USB_D+
S
USB_D−
V
V
SSIO, SSCORE
002aad588
Fig 14. LPC2420/2460 USB interface on a bus-powered device
LPC2420_60_3
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Preliminary data sheet
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
V
DD
R1
R2
R3
R4
VBUS
ID
RSTOUT
RESET_N
ADR/PSW
OE_N/INT_N
SPEED
33 Ω
DP
V
DD
Mini-AB
33 Ω
connector
DM
ISP1301
SUSPEND
R4
R5
R6
V
SSIO,
SCL
SDA
USB_SCL1
USB_SDA1
USB_INT1
V
SSCORE
INT_N
USB_D+1
USB_D−1
V
DD
USB_UP_LED1
R7
LPC24XX
5 V
V
DD
IN
ENA
OUTA
FLAGA
LM3526-L
USB_PPWR2
USB_OVRCR2
V
USB_PWRD2
USB_D+2
BUS
33 Ω
33 Ω
D+
USB-A
connector
D−
USB_D−2
V
SSIO,
SSCORE
15 kΩ
15 kΩ
V
V
DD
USB_UP_LED2
R8
002aad589
Fig 15. LPC2420/2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host
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NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
V
DD
RSTOUT
RESET_N
OE_N/INT_N
DAT_VP
USB_TX_E1
USB_TX_DP1
USB_TX_DM1
SE0_VM
RCV
VP
USB_RCV1
USB_RX_DP1
USB_RX_DM1
VBUS
ID
VM
V
33 Ω
33 Ω
DD
USB MINI-AB
connector
DP
ISP1301
DM
LPC24XX
ADR/PSW
SPEED
V
SSIO,
SSCORE
V
SUSPEND
USB_SCL1
USB_SDA1
USB_INT1
SCL
SDA
INT_N
V
DD
USB_UP_LED1
002aad590
Fig 16. LPC2420/2460 USB OTG port configuration: VP_VM mode
LPC2420_60_3
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Preliminary data sheet
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
V
DD
USB_UP_LED1
V
SSIO,
SSCORE
V
33 Ω
33 Ω
D+
USB_D+1
USB_D−1
D−
USB-A
connector
15 kΩ
15 kΩ
V
DD
V
USB_PWRD1
USB_OVRCR1
BUS
USB_PPWR1
FLAGA
OUTA
ENA
5 V
LM3526-L
IN
LPC24XX
V
DD
USB_UP_LED2
V
DD
USB_CONNECT2
V
SSIO,
SSCORE
V
33 Ω
33 Ω
USB_D+2
D+
USB-B
connector
D−
USB_D−2
V
V
BUS
BUS
002aad595
Fig 17. LPC2420/2460 USB OTG port configuration: USB port 2 device, USB port 1 host
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
64 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
V
DD
USB_UP_LED1
V
SSIO,
SSCORE
V
33 Ω
D+
USB_D+1
33 Ω
USB_D−1
D−
USB-A
connector
15 kΩ
15 kΩ
V
DD
V
USB_PWRD1
USB_OVRCR1
BUS
USB_PPWR1
FLAGA
OUTA
ENA
5 V
V
DD
IN
LM3526-L
OUTB
LPC24XX
USB_PPWR2
ENB
FLAGB
USB_OVRCR2
USB_PWRD2
V
BUS
USB-A
connector
33 Ω
33 Ω
USB_D+2
D+
D−
USB_D−2
V
SSIO,
SSCORE
15 kΩ
15 kΩ
V
V
DD
USB_UP_LED2
002aad596
Fig 18. LPC2420/2460 USB OTG port configuration: USB port 1 host, USB port 2 host
11.2 Suggested boot memory interface solutions
‘a_m’ and ‘a_b’ in the following figures refer to the highest order address line of the
memory chip and the highest order microcontroller’s address line used respectively.
CS1
OE
CE
OE
WE
CE
OE
WE
BLS1
BLS0
D[7:0]
8-bit
MEMORY
8-bit
MEMORY
IO[7:0]
IO[7:0]
D[15:8]
A[a_m:0]
A[a_m:0]
A[a_b:1]
002aad322
Fig 19. Booting from two 8-bit memory chips
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
65 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
CS1
OE
CE
OE
WE
WE
UB
LB
16-bit
MEMORY
BLS1
BLS0
IO[15:0]
D[15:0]
A[a_m:0]
A[a_b:1]
002aad323
Fig 20. Booting from a single 16-bit memory chip
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
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LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
12. Package outline
LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm
SOT459-1
y
X
A
105
104
156
157
Z
E
e
H
E
E
(A )
3
A
2
A
A
1
w M
p
θ
L
L
b
p
detail X
pin 1 index
53
208
1
52
v
M
B
A
Z
w M
D
b
p
e
D
B
H
v
M
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 28.1 28.1
0.17 0.09 27.9 27.9
30.15 30.15
29.85 29.85
0.75
0.45
1.43 1.43
1.08 1.08
mm
1.6
0.25
1
0.12 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-06
03-02-20
SOT459-1
136E30
MS-026
Fig 21. Package outline SOT459-1 (LQFP208)
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
67 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm
SOT950-1
D
B
A
ball A1
index area
A
2
E
A
A
1
detail X
e
1
C
M
v
C
C
A
B
b
e
y
y
M
w
C
1
U
T
P
R
N
M
K
H
e
L
J
e
2
G
F
E
D
B
C
A
ball A1
index area
1
3
5
7
9
11 13 15 17
10 12 14 16
2
4
6
8
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
e
2
v
w
y
y
1
1
max
0.4
0.3
0.8
0.6
0.5
0.4
15.1 15.1
14.9 14.9
mm
1.2
0.8
12.8 12.8 0.15 0.08 0.12
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
06-06-01
06-06-14
SOT950-1
- - -
Fig 22. Package outline SOT950-1 (TFBGA208)
LPC2420_60_3
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Preliminary data sheet
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68 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
13. Abbreviations
Table 13. Acronym list
Acronym
ADC
AHB
AMBA
APB
Description
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
BrownOut Detection
BOD
CAN
DAC
DCC
DMA
EOP
ETM
GP
Controller Area Network
Digital-to-Analog Converter
Debug Communication Channel
Direct Memory Access
End Of Packet
Embedded Trace Macrocell
General Purpose
GPIO
IrDA
General Purpose Input/Output
Infrared Data Association
Joint Test Action Group
JTAG
MII
Media Independent Interface
Media Independent Interface Management
Open Host Controller Interface
On-The-Go
MIIM
OHCI
OTG
PHY
PLL
Physical Layer
Phase-Locked Loop
POR
PWM
RMII
SD/MMC
SE0
Power-On Reset
Pulse Width Modulator
Reduced Media Independent Interface
Secure Digital/MultiMediaCard
Single Ended Zero
SPI
Serial Peripheral Interface
Synchronous Serial Interface
Synchronous Serial Port
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
SSI
SSP
TTL
UART
USB
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
69 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
14. Revision history
Table 14. Revision history
Document ID
LPC2420_60_3
Modifications:
Release date
20081120
Data sheet status
Change notice
Supersedes
Preliminary data sheet
LPC2460_2
• Table 1, Table 2, added LPC2420FBD208.
• Added Table 11 “Dynamic characteristics: Static external memory interface”.
• Added Table 12, dynamic external memory interface characteristics.
• Added Figure 10 “External memory read access” and Figure 11 “External memory write
access”.
• Table 7, updated IOHS and IOLS footnote.
• Table 7, Vhys, moved 0.4 from Typ to Min column.
• Table 7, added Table note 6.
• Figure 7, updated graphic, changed title.
• Added Figure 12, signal timing.
LPC2460_2
20080201
Preliminary data sheet
-
LPC2460_1
Modifications:
• Table 4 “Pin description”: pin RSTOUT changed from 1.8 V to 3.3 V
• Section 7.6.1 “Features”: ’Controller supports’ changed from ’2 kbit, 4 kbit, and 8 kbit’ to
’2048, 4096, and 8192’.
LPC2460_1
20080123
Preliminary data sheet
-
-
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
70 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
I2C-bus — logo is a trademark of NXP B.V.
SoftConnect — is a trademark of NXP B.V.
GoodLink — is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC2420_60_3
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Preliminary data sheet
Rev. 03 — 20 November 2008
71 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
17. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
7.18.1
7.19
7.19.1
7.20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2S-bus serial I/O controllers . . . . . . . . . . . . . 35
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General purpose 32-bit timers/external
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
4.1
5
event counters . . . . . . . . . . . . . . . . . . . . . . . . 36
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pulse width modulator . . . . . . . . . . . . . . . . . . 37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 38
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RTC and battery RAM . . . . . . . . . . . . . . . . . . 38
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clocking and power control . . . . . . . . . . . . . . 39
Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 39
7.20.1
7.21
7.21.1
7.22
7.22.1
7.23
7.23.1
7.24
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
7.1
7.2
7.3
7.4
7.4.1
7.5
7.6
7.6.1
7.7
7.7.1
7.8
7.8.1
7.9
7.9.1
7.10
7.10.1
Functional description . . . . . . . . . . . . . . . . . . 24
Architectural overview. . . . . . . . . . . . . . . . . . . 24
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 26
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 27
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 27
External memory controller. . . . . . . . . . . . . . . 27
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General purpose DMA controller . . . . . . . . . . 28
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fast general purpose parallel I/O . . . . . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ethernet (LPC2460 only) . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB device controller . . . . . . . . . . . . . . . . . . . 31
7.24.1
7.24.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 39
7.24.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 39
7.24.1.3 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 40
7.24.2
7.24.3
7.24.4
7.24.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.24.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.24.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 41
7.24.4.4 Power domains. . . . . . . . . . . . . . . . . . . . . . . . 42
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 40
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.25
System control . . . . . . . . . . . . . . . . . . . . . . . . 42
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Boot process . . . . . . . . . . . . . . . . . . . . . . . . . 42
Brownout detection . . . . . . . . . . . . . . . . . . . . 43
AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External interrupt inputs. . . . . . . . . . . . . . . . . 43
Memory mapping control . . . . . . . . . . . . . . . . 43
Emulation and debugging. . . . . . . . . . . . . . . . 44
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 44
Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 44
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.25.1
7.25.2
7.25.3
7.25.4
7.25.5
7.25.6
7.26
7.26.1
7.26.2
7.26.3
7.10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.10.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 31
7.10.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.10.3 USB OTG Controller. . . . . . . . . . . . . . . . . . . . 32
7.10.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.11
CAN controller and acceptance filters
(LPC2460 only). . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SSP serial I/O controller . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SD/MMC card interface . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C-bus serial I/O controller . . . . . . . . . . . . . . 35
7.11.1
7.12
7.12.1
7.13
7.13.1
7.14
7.14.1
7.15
7.15.1
7.16
7.16.1
7.17
7.17.1
7.18
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 46
Static characteristics . . . . . . . . . . . . . . . . . . . 47
Dynamic characteristics. . . . . . . . . . . . . . . . . 53
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
10
10.1
11
11.1
11.2
Application information . . . . . . . . . . . . . . . . . 60
Suggested USB interface solutions . . . . . . . . 60
Suggested boot memory interface solutions . 65
12
13
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 67
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 69
Revision history . . . . . . . . . . . . . . . . . . . . . . . 70
Legal information . . . . . . . . . . . . . . . . . . . . . . 71
continued >>
LPC2420_60_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 20 November 2008
72 of 73
LPC2420/2460
NXP Semiconductors
Flashless 16-bit/32-bit microcontroller
15.1
15.2
15.3
15.4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 71
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 71
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 November 2008
Document identifier: LPC2420_60_3
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