LPC2888FET180/01_技术文档

LPC2880; LPC2888

16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB ﬂash,

Hi-Speed USB 2.0 device, and SDRAM memory interface

Rev. 03 — 17 April 2008

Preliminary data sheet

1. General description

The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring

low power and high performance. It includes a USB 2.0 Hi-Speed device interface, an

external memory interface that can interface to SDRAM and ﬂash, an SD/MMC memory

card interface, ADC and DACs, and serial interfaces including UART, I²C-bus, and

I²S-bus. Architectural enhancements like multi-channel DMA, processor cache,

simultaneous operations on multiple internal buses, and ﬂexible clock generation help

ensure that the LPC2880/2888 can handle more demanding applications than many

competing devices. The chip can be powered from a single battery, from the USB, or from

regulated 1.8 V and 3.3 V.

2. Features

2.1 Key features

I ARM7TDMI processor with 8 kB cache, operating at up to 60 MHz

I 1 MB on-chip ﬂash program memory with 128-bit access for high performance

I 64 kB SRAM

I Boot ROM allows execution of ﬂash code, external code, or ﬂash programming via

USB

I On-chip DC-to-DC converter can generate all required voltages from a single battery

or from USB power

I Multiple internal buses allow simultaneous simple DMA, USB DMA, and program

execution from on-chip ﬂash without contention

I External memory controller supports ﬂash, SRAM, ROM, and SDRAM

I Advanced vectored interrupt controller, supporting up to 30 vectored interrupts

I Innovative event router allows interrupt, power-up, and clock-start capabilities from up

to 107 sources

I Multi-channel general purpose DMA controller that can be used with most on-chip

peripherals as well as for memory-to-memory transfers

I Serial interfaces:

N Hi-Speed or Full-Speed USB 2.0 device (480 Mbit/s or 12 Mbit/s) with on-chip

physical layer

N UART with fractional baud rate generation, ﬂow control, IrDA support, and FIFOs

N I²C-bus interface

N I²S-bus (Inter IC Sound bus) interface for independent stereo digital audio input

and output

I SD/MMC memory card interface

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

I 10-bit ADC with 5-channel input multiplexing

I 16-bit stereo ADC and DACs with gain control

I Advanced clock generation and power control reduce power consumption

I Two 32-bit timers with selectable prescalers

I 8-bit/4-bit LCD interface bus

I Real-Time Clock (RTC) can be clocked by 32 kHz oscillator or another source

I Watchdog timer with interrupt and/or reset capabilities

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC2880FET180

TFBGA180 plastic thin ﬁne-pitch ball grid array package;

SOT640-1

180 balls; body 10 × 10 × 0.8 mm

LPC2888FET180/01

TFBGA180 plastic thin ﬁne-pitch ball grid array package;

SOT640-1

180 balls; body 10 × 10 × 0.8 mm

LPC2888FET180/D1 TFBGA180 plastic thin ﬁne-pitch ball grid array package;

180 balls; body 10 × 10 × 0.8 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash memory

JTAG interface

enabled

RAM

64 kB

Temperature range

LPC2880FET180

LPC2888FET180/01

LPC2888FET180/D1

-

−40 °C to +85 °C

1 MB

enabled

disabled^[1]

[1] JTAG interface disabled to provide code read protection. These devices are meant for volume production (no JTAG debugging is

possible). The on-chip ﬂash on these devices can only be programmed via USB.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

2 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

4. Block diagram

A[20:0],

DP, DM, VBUS,

RREF, RPU

D[15:0],

etc.

LPC2880/2888

EXTERNAL

MEMORY

CONTROLLER

HS USB

WITH DMA

JTAG DEBUG

INTERFACE

1 MB

64 kB

SRAM

BOOT

ROM

(1)

FLASH

ARM7TDMI

VECTORED

INTERRUPT

CONTROLLER

FLASH

INTERFACE INTERFACE

SRAM

ROM

INTERFACE

8 kB CACHE

MULTI-LAYER AHB

+1.5 V

or +5 V

DC-TO-DC

CONVERTER

3.3 V,

1.8 V

AHB TO APB

BRIDGE 0

AHB TO APB

BRIDGE 1

AHB TO APB

BRIDGE 2

GP DMA

CONTROLLER

START,

STOP

register

interface

WATCHDOG

TIMER

AHB TO APB

BRIDGE 3

MCLK, MCMD

MD[3:0]

SD/MMC CARD

INTERFACE

SYSTEM

CONTROL

TXD, RTS

RXD, CTS

UART WITH

IrDA

EVENT

ROUTER

LCD

INTERFACE

CLOCK

OSCILLATOR

GENERATION

AND PLLs

LCD bus

XTALI

XTALO

UNIT

2

I C-BUS

X32I

SCL, SDA

REAL-TIME

OSCILLATOR

INTERFACE

CLOCK

X32O

32-BIT

TIMER 0

GENERAL

PURPOSE I/O

Px.y

32-BIT

TIMER 1

10-BIT A/D

CONVERTER

AIN[4:0]

V

REF,

AIN_LNA,

AINA, AINB

DATI

BCKI, WSI

2

TRIPLE ANALOG

I S-BUS

INPUT

FIFO

INPUT

AOUT_LNA

2

DATO

BCKO, DCLKO,

WSO

DUAL ANALOG

OUTPUT

I S-BUS

AOUTA,

AOUTA_DAC,

AOUTB,

OUTPUT

AOUTB_DAC

002aac296

(1) LPC2888 only.

Fig 1. Block diagram

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

3 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

5. Pinning information

5.1 Pinning

ball A1

index area

2

4

6

8

10 12 14 16 18

9 11 13 15 17

1

3

5

7

A

B

C

D

E

F

G

H

J

K

L

LPC2880FET180

LPC2888FET180/01

LPC2888FET180/D1

M

N

P

R

T

U

V

002aac239

Transparent top view

Fig 2. Pin conﬁguration

Table 3.

Pin allocation table

Pin Symbol

Row A

Pin Symbol

1

D0/P0[0]

2

D1/P0[1]

V_SS2(EMC)

3

D3/P0[3]

4

D4/P0[4]

STCS1/P1[6]

BLS0/P1[12]

V_DD1(EMC)

-

5

D6/P0[6]

6

7

V_DD2(EMC)

DQM1/P1[11]

V_SS1(EMC)

-

8

9

RAS/P1[17]

A18/P1[2]

OE/P1[18]

10

14

18

MCLKO/P1[14]

A15/P0[31]

A6/P0[22]

11

15

12

16

13

17

Row B

1

RPO/P1[19]

2

D2/P0[2]

3

LCS/P4[0]

D13/P0[13]

STCS2/P1[7]

A13/P0[29]

-

4

D5/P0[5]

D15/P0[15]

BLS1/P1[13]

A11/P0[27]

-

5

D7/P0[7]

6

D11/P0[11]

CKE/P1[9]

A16/P1[0]

A7/P0[23]

7

8

9

DYCS/P1[8]

A19/P1[3]

A9/P0[25]

10

14

18

11

15

12

16

13

17

Row C

1

LD1/P4[5]

2

LD0/P4[4]

D10/P0[10]

CAS/P1[16]

A17/P1[1]

A8/P0[24]

3

LD2/P4[6]

D12/P0[12]

WE/P1[15]

A14/P0[30]

-

4

D8/P0[8]

D14/P0[14]

DQM0/P1[10]

A12/P0[28]

-

5

D9/P0[9]

6

7

8

9

STCS0/P1[5]

A20/P1[4]

A10/P0[26]

10

14

18

11

15

12

16

13

17

Row D

LD4/P4[8]

1

2

LD3/P4[7]

3

LD5/P4[9]

4

-

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

4 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 3.

Pin allocation table …continued

Pin Symbol

13

17

-

14

18

-

15

-

16

A3/P0[19]

-

A4/P0[20]

A5/P0[21]

Row E

1

V_DD1(IO3V3)

2

LD6/P4[10]

-

3

LD7/P4[11]

4

-

13

17

-

14

18

15

-

16

A0/P0[16]

-

A1/P0[17]

A2/P0[18]

Row F

1

V_SS1(IO)

2

LER/P4[3]

3

LRS/P4[1]

4

-

13

17

-

14

18

-

15

-

16

DCLKO/P3[3]

-

DATO/P3[6]

WSO

Row G

1

V_SS1(CORE)

2

LRW/P4[2]

-

3

MCLK/P5[0]

4

-

13

17

-

14

18

15

-

16

DATI/P3[0]

-

WSI/P3[2]

BCKO/P3[5]

Row H

1

V_DD1(CORE1V8)

2

MCMD/P5[1]

3

MD0/P5[5]

4

-

13

17

-

14

18

-

15

-

16

SCL

-

BCKI/P3[1]

V_SS4(IO)

Row J

1

MD2/P5[3]

2

MD1/P5[4]

-

3

MD3/P5[2]

4

-

13

17

-

14

18

15

-

16

MODE2/P2[3]

-

SDA

V_DD4(IO3V3)

Row K

1

RTS/P6[3]

2

CTS/P6[2]

3

RXD/P6[0]

4

-

13

17

-

14

18

-

15

-

16

P2[0]

-

P2[1]

MODE1/P2[2]

Row L

1

V_DD(DAC3V3)

2

VREFP(DAC)

3

TXD/P6[1]

4

-

13

17

-

14

18

-

15

-

16

DCDC_GND

-

START

STOP

Row M

1

VREFN(DAC)

2

AOUTL

3

AOUTR

4

-

13

17

-

14

18

-

15

-

16

DCDC_V_DDI(3V3)

-

DCDC_V_BAT

DCDC_CLEAN

Row N

1

i.c.^[1]

2

i.c.^[1]

3

i.c.^[1]

4

-

13

17

-

14

18

-

15

-

16

DCDC_V_SS2

-

DCDC_LX2

DCDC_V_DDO(1V8)

Row P

1

V_SS6(IO)

2

V_SS5(IO)

-

3

i.c.^[1]

-

4

-

13

-

14

15

16

RREF

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

5 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 3.

Pin allocation table …continued

Pin Symbol

17

DCDC_LX1

18

DCDC_V_SS1

-

Row R

1

V_DD5(IO3V3)

2

V_DD6(IO3V3)

3

i.c.^[1]

4

-

13

17

-

14

18

-

15

-

16

V_SS2(USB)

-

V_SS1(USB)

DCDC_V_DDO(3V3)

Row T

1

AINR

2

i.c.^[1]

3

V_COM(DADC)

AIN1

4

AINL

5

JTAG_TDI

V_SS(OSC)

JTAG_TRST

DM

6

AIN3

7

8

X32O

V_SS1(INT)

V_SS3(USB)

-

9

10

14

18

XTALI

11

15

V_SS3(INT)

CONNECT

-

12

16

13

17

RESET

DCDC_V_USB

Row U

1

VREF(DADC)

2

VREFP(DADC)

AIN2

3

V_DD(DADC3V3)

AIN0

4

JTAG_SEL

V_DD(OSC321V8)

JTAG_TMS

V_DD2(USB1V8)

-

5

AIN4

6

7

8

9

V_DD(OSC1V8)

JTAG_TDO

DP

10

14

18

V_SS(ADC)

11

15

V_SS2(INT)

V_DD1(USB1V8)

-

12

16

13

17

VBUS/P7[0]

V_DD3(USB3V3)

Row V

1

VREFN(DADC)

2

V_SS(DADC)

V_SS2(IO)

3

V_DD(DADC1V8)

X32I

4

JTAG_TCK

V_SS(OSC32)

V_SS2(CORE)

V_{DD2(FLASH1V8)}

-

5

V_DD2(IO3V3)

XTALO

6

7

8

9

10

14

18

V_DD(ADC3V3)

V_DD3(IO3V3)

V_DD4(USB3V3)

11

15

V_DD2(CORE1V8)

V_{DD1(FLASH1V8)}

-

12

16

13

17

V_SS3(IO)

V_SS3(CORE)

[1] These pins are connected internally and must be left unconnected in an application.

5.2 Pin description

Table 4.

Symbol

Pin description

Ball #

Type^[1]

Description

Analog in (dual converter)

AINL

T4

T1

T3

I

analog L input channel

analog R input channel

AINR

I

VCOM(DADC)

RV

ADC common reference voltage and analog output reference voltage

combined on-chip

VREF(DADC)

VREFN(DADC)

VREFP(DADC)

V_DD(DADC1V8)

V_DD(DADC3V3)

V_SS(DADC)

U1

V1

U2

V3

U3

V2

RV

P

ADC reference voltage

ADC negative reference voltage

ADC positive reference voltage

1.8 V for dual ADC

P

3.3 V for dual ADC

P

ground for dual ADC

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

6 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Ball #

Type^[1]

Description

Analog in (single converter)

AIN0

U7

T7

I

multiplexed analog input

3.3 V analog supply and reference voltage

ground

AIN1

I

AIN2

U6

T6

I

AIN3

I

AIN4

U5

V10

U10

I

V_DD(ADC3V3)

V_SS(ADC)

P

Analog out (dual channel)

AOUTL

M2

M3

M1

L2

O

DAC L analog out

AOUTR

O

DAC R analog out

VREFN(DAC)

VREFP(DAC)

V_DD(DAC3V3)

DAI interface

BCKI/P3[1]

DATI/P3[0]

WSI/P3[2]

RV

P

negative reference voltage

positive reference voltage

3.3 V for DAC

L1

H17

G16

G17

FI

DAI bit clock; 5 V tolerant GPIO pin

DAI serial data input; 5 V tolerant GPIO pin

DAI word select; 5 V tolerant GPIO pin

DAO interface

BCKO/P3[5]

DATO/P3[6]

DCLKO/P3[3]

WSO

G18

F17

F16

F18

FO

O

DAO bit clock; 5 V tolerant GPIO pin

DAO serial data output; 5 V tolerant GPIO pin

256 × clock output; 5 V tolerant GPIO pin

DAO word select; 5 V tolerant pin

DC-to-DC converters

START

L17

L18

M18

L16

P17

N17

M17

I

DC-to-DC converter activation

STOP

I

DC-to-DC converter deactivation

DCDC_CLEAN

DCDC_GND

DCDC_LX1

DCDC_LX2

DCDC_V_BAT

P

reference circuit ground, not connected to substrate

DC-to-DC converter main ground and substrate

connect to external coil for DC/DC1

connect to external coil for DC/DC2

connect to battery +

DCDC_V_DDI(3V3)M16

DCDC_V_DDO(1V8)N18

DCDC_V_DDO(3V3)R18

DC/DC1 3.3 V input voltage

DC/DC2 1.8 V output voltage

DC/DC1 3.3 V output voltage

DCDC_V_SS1

DCDC_V_SS2

DCDC_V_USB

P18

N16

T18

ground for DC/DC1, not connected to substrate

ground for DC/DC2, not connected to substrate

connect to +5 V pin of USB connector

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

7 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Ball #

Type^[1]

Description

External memory interface

D0/P0[0]

A1

FI

external memory data bus, low byte (I/O); GPIO pins

external memory data bus, high byte (I/O); GPIO pins

address bus for SDRAM and static memory; GPIO pins

D1/P0[1]

A2

D2/P0[2]

B2

D3/P0[3]

A3

D4/P0[4]

A4

D5/P0[5]

B4

D6/P0[6]

A5

D7/P0[7]

B5

D8/P0[8]

C4

FI

D9/P0[9]

C5

D10/P0[10]

D11/P0[11]

D12/P0[12]

D13/P0[13]

D14/P0[14]

D15/P0[15]

A0/P0[16]

A1/P0[17]

A2/P0[18]

A3/P0[19]

A4/P0[20]

A5/P0[21]

A6/P0[22]

A7/P0[23]

A8/P0[24]

A9/P0[25]

A10/P0[26]

A11/P0[27]

A12/P0[28]

A13/P0[29]

A14/P0[30]

A15/P0[31]

A16/P1[0]

A17/P1[1]

A18/P1[2]

A19/P1[3]

A20/P1[4]

BLS0/P1[12]

BLS1/P1[13]

CAS/P1[16]

C6

B6

C7

B7

C8

B8

E16

E17

E18

D16

D17

D18

A18

B18

C18

B17

C17

B16

C16

B15

C15

A14

B14

C14

A13

B13

C13

A12

B12

C10

FO

address bus for static memory; GPIO pins

FO

byte lane select for D[7:0], active LOW for static memory; GPIO pin

byte lane select for D[15:8], active LOW for static memory; GPIO pin

column address strobe, active LOW for SDRAM; GPIO pin

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

8 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Pin description …continued

Symbol

Ball #

B10

C12

A11

B9

Type^[1]

FO

Description

CKE/P1[9]

clock enable; active HIGH for SDRAM; GPIO pin

DQM0/P1[10]

DQM1/P1[11]

DYCS/P1[8]

MCLKO/P1[14]

OE/P1[18]

data mask output for D[7:0], active HIGH for SDRAM; GPIO pin

data mask output for D[15:8], active HIGH for SDRAM; GPIO pin

chip select, active LOW for SDRAM; GPIO pin

A10

A17

A9

clock for SDRAM and SyncFlash memory; GPIO pin

output enable, active LOW for static memory; GPIO pin

row address strobe, active LOW for SDRAM; GPIO pin

reset power-down, active LOW for SyncFlash memory; GPIO pin

chip select, active LOW for static memory bank 0; GPIO pin

chip select, active LOW for static memory bank 1; GPIO pin

chip select, active LOW for static memory bank 2; GPIO pin

write enable, active LOW for SDRAM and static memory; GPIO pin

RAS/P1[17]

RPO/P1[19]

STCS0/P1[5]

STCS1/P1[6]

STCS2/P1[7]

WE/P1[15]

B1

C9

A8

B11

C11

GPIO and mode control

MODE1/P2[2]

MODE2/P2[3]

P2[0]

K18

J16

K16

K17

FI

start-up mode pin 1 (pull-down); 5 V tolerant GPIO pin

start-up mode pin 2 (pull-down); 5 V tolerant GPIO pin

5 V tolerant GPIO pin

P2[1]

5 V tolerant GPIO pin

I²C-bus interface

SCL

H16

J17

I/O

serial clock (input/open-drain output); 5 V tolerant pin

serial data (input/open-drain output); 5 V tolerant pin

SDA

JTAG interface

JTAG_SEL

JTAG_TCK

JTAG_TDI

JTAG_TMS

JTAG_TRST

JTAG_TDO

LCD interface

LCS/P4[0]

LD0/P4[4]

LD1/P4[5]

LD2/P4[6]

LD3/P4[7]

LD4/P4[8]

LD5/P4[9]

LD6/P4[10]

LD7/P4[11]

LER/P4[3]

LRS/P4[1]

U4

I

JTAG selection (pull-down); 5 V tolerant pin

JTAG reset input (pull-down); 5 V tolerant pin

JTAG data input (pull-up); 5 V tolerant pin

JTAG mode select input (pull-up); 5 V tolerant pin

JTAG reset input (pull-down); 5 V tolerant pin

JTAG data output; 5 V tolerant pin

V4

I

T5

I

U12

T13

U13

I

O

B3

C2

C1

C3

D2

D1

D3

E2

E3

F2

F3

FO

chip select to LCD device, programmable polarity; 5 V tolerant GPIO pin

data bus to/from LCD (I/O) or 5 V tolerant GPIO pins

6800 E or 8080 RD or 5 V tolerant GPIO pin

‘HIGH’ data register select, ‘LOW’ instruction register select, or 5 V tolerant

GPIO pin

LRW/P4[2]

G2

FO

6800 W/R or 8080 WR or 5 V tolerant GPIO pin

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

9 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Ball #

Type^[1]

Description

Memory card interface

MCMD/P5[1]

MD0/P5[5]

MD1/P5[4]

MD2/P5[3]

MD3/P5[2]

MCLK/P5[0]

H2

H3

J2

FI

FO

command (I/O); 5 V tolerant GPIO pin

data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin

MCI clock output; 5 V tolerant GPIO pin

J1

J3

G3

Oscillator (32.768 kHz)

X32I

V7

T8

U8

V8

I

32.768 kHz oscillator input

32.768 kHz oscillator output

1.8 V

X32O

O

P

V_DD(OSC321V8)

V_SS(OSC32)

Oscillator (main)

XTALI

ground

T10

V9

I

main oscillator input

main oscillator output

1.8 V

XTALO

O

P

V_DD(OSC1V8)

V_SS(OSC)

U9

T9

ground

Reset

RESET

T14

I

master reset, active LOW; 5 V tolerant pin

UART

CTS/P6[2]

RXD/P6[0]

RTS/P6[3]

TXD/P6[1]

USB interface

CONNECT

K2

K3

K1

L3

FI

clear to send or transmit ﬂow control, active LOW; 5 V tolerant GPIO pin

serial input; 5 V tolerant GPIO pin

FI

FO

request to send or receive ﬂow control, active LOW; 5 V tolerant GPIO pin

serial output; 5 V tolerant GPIO pin

T15

P

used for signalling speed capability; for high-speed USB, connect an external

1.5 kΩ resistor to 3.3 V

DM

T17

U17

P16

U14

U15

U16

U18

V18

R17

R16

T16

I/O

P

negative USB data line

DP

positive USB data line

RREF

transceiver reference; connect an external 12 kΩ 1 % resistor to ground

VBUS/P7[0]

V_DD1(USB1V8)

V_DD2(USB1V8)

V_DD3(USB3V3)

V_DD4(USB3V3)

V_SS1(USB)

V_SS2(USB)

V_SS3(USB)

FI

P

USB supply detection; 5 V tolerant GPIO pin

analog 1.8 V

P

analog 1.8 V

P

analog 3.3 V

P

analog 3.3 V

P

analog ground

P

analog ground

P

analog ground

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

10 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 4.

Symbol

Pin description …continued

Ball #

Type^[1]

Description

Digital power and ground

V_DD1(CORE1V8)

V_{DD1(FLASH1V8)}

V_DD1(EMC)

V_DD1(IO3V3)

V_DD2(CORE1V8)

V_DD2(EMC)

V_{DD2(FLASH1V8)}

V_DD2(IO3V3)

V_DD3(IO3V3)

V_DD4(IO3V3)

V_DD5(IO3V3)

V_DD6(IO3V3)

V_SS1(CORE)

V_SS1(EMC)

V_SS1(INT)

H1

P

1.8 V for internal RAM and ROM

1.8 V for internal ﬂash memory

1.8 V or 3.3 V for external memory controller

3.3 V for peripherals

V15

A16

E1

V11

A7

1.8 V for core

1.8 V or 3.3 V for external memory controller

1.8 V for internal ﬂash memory

3.3 V for peripherals

V16

V5

V14

J18

R1

3.3 V for peripherals

R2

3.3 V for peripherals

G1

ground for internal RAM and ROM

ground for external memory controller

ground for other internal blocks

ground for peripherals

A15

T12

F1

V_SS1(IO)

V_SS2(CORE)

V_SS2(EMC)

V_SS2(INT)

V12

A6

ground for core

ground for external memory controller

ground for other internal blocks

ground for peripherals

U11

V6

V_SS2(IO)

V_SS3(CORE)

V_SS3(INT)

V17

T11

V13

H18

P2

ground for core, substrate, ﬂash

ground for other internal blocks

ground for peripherals

V_SS3(IO)

V_SS4(IO)

ground for peripherals

V_SS5(IO)

ground for peripherals

V_SS6(IO)

P1

ground for peripherals

[1] I = input; O = output; I/O = input/output; RV = reference voltage; FI = functional input; FO = functional output; P = power or ground

6. Functional description

6.1 Architectural overview

The LPC2880/2888 includes an ARM7TDMI CPU with an 8 kB cache, an AMBA AHB

interfacing to high-speed on-chip peripherals and internal and external memory, and four

AMBA APBs for connection to other on-chip peripheral functions.

The LPC2880/2888 includes a multi-layer AHB and four separate APBs, in order to

minimize interference between the USB controller, other DMA operations, and processor

activity. Bus masters include the ARM7 itself, the USB block, and the general purpose

DMA controller.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

11 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Lower speed peripheral functions are connected to the APBs. The four AHB-to-APB

bridges interface the APBs to the AHB.

6.1.1 ARM7TDMI processor

The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance

and very low power consumption. The ARM architecture is based on RISC principles, and

the instruction set and related decode mechanism are much simpler than those of

microprogrammed CISCs. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI processor also employs a unique architectural strategy known as Thumb,

which makes it ideally suited to high-volume applications with memory restrictions, or

applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit Thumb instruction set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide down to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI processor is described in detail on the ARM web site.

6.1.2 On-chip ﬂash memory system

The LPC2880/2888 includes a 1 MB ﬂash memory system. This memory may be used for

both code and data storage. Programming of the ﬂash memory may be accomplished in

several ways. It may be programmed In System via the USB port. The application program

may also erase and/or program the ﬂash while the application is running, allowing a great

degree of ﬂexibility for data storage ﬁeld ﬁrmware upgrades, etc.

The ﬂash is 128 bit wide and includes buffering to allow 3 out of 4 sequential read

operations to operate without wait states.

6.1.3 On-chip SRAM

The LPC2880/2888 includes 64 kB of SRAM that may be used for code and/or data

storage.

6.1.4 On-chip ROM

The LPC2880/2888 includes an on-chip ROM that contains boot code. Execution begins

in on-chip ROM after a reset.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

12 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

The boot code in this ROM reads the state of the mode inputs and accordingly does one

of the following:

• Starts execution in internal ﬂash

• Starts execution in external memory

• Performs a hardware self-test, or

• Downloads code from the USB interface into on-chip RAM and transfers control to the

downloaded code

6.2 Memory map

The LPC2880/2888 memory map incorporates several distinct regions, as shown in

Figure 3. When an application is running, the CPU interrupt vectors are remapped to allow

them to reside in on-chip SRAM.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

13 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

4.0 GB

0xFFFF FFFF

0x9000 0000 to 0xFFFF FFFF

0x9000 0000

reserved

0x8FFF FFFF

peripherals

2.0 GB

includes AHB and 4 APB buses

reserved

0x8000 0000 to 0x8FFF FFFF

0x5400 0000 to 0x7FFF FFFF

0x5000 0000 to 0x53FF FFFF

0x4820 0000 to 0x4FFF FFFF

0x4800 0000 to 0x481F FFFF

0x4420 0000 to 0x47FF FFFF

0x4400 0000 to 0x441F FFFF

0x4020 0000 to 0x43FF FFFF

0x4000 0000 to 0x401F FFFF

0x3400 0000 to 0x3FFF FFFF

0x3000 0000 to 0x33FF FFFF

0x2820 0000 to 0x2FFF FFFF

0x2800 0000 to 0x281F FFFF

0x2420 0000 to 0x27FF FFFF

0x2400 0000 to 0x241F FFFF

0x2020 0000 to 0x23FF FFFF

0x2000 0000 to 0x201F FFFF

0x1050 0000 to 0x1FFF FFFF

0x1040 0000 to 0x104F FFFF

0x8000 0000

0x7FFF FFFF

dynamic memory bank 0, 64 MB

reserved

static memory bank 2, 2 MB

reserved

external memory

(second instance)

static memory bank 1, 2 MB

reserved

static memory bank 0, 2 MB

reserved

0x4000 0000

0x3FFF FFFF

1.0 GB

dynamic memory bank 0, 64 MB

reserved

static memory bank 2, 2 MB

reserved

external memory

(first instance)

static memory bank 1, 2 MB

reserved

static memory bank 0, 2 MB

reserved

0x2000 0000

0x1FFF FFFF

internal memory

internal flash (1 MB)

reserved

0x1000 0000 to 0x0000 003F

0x0050 0000 to 0x0FFF FFFF

0x1000 0000

0x0FFF FFFF

internal RAM (64 kB)

0x0040 0000 to 0x0040 FFFF

remapped area

internal ROM (32 kB)

exception vectors

0x0020 0000 to 0x0020 7FFF

0x0000 0000 to 0x0000 001F

0x0000 0000

002aac240

0.0 GB

Fig 3. Memory map

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

14 of 43

LPC2880; LPC2888

NXP Semiconductors

6.3 Cache

16/32-bit ARM microcontrollers with external memory interface

The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache.

The cache is 8 kB in size and can store both data and instruction code.

If code that is being executed is present in the cache from a previous execution, the CPU

will not experience code fetch waits. Similarly, if requested data is present in the cache,

the CPU will not experience a data access wait.

The trade-off of introducing this cache is that each AHB access that bypasses the cache

will have an extra wait state inserted. Therefore it is advisable that both instruction caching

and data caching are turned on for most regions of on and off-chip memory.

6.3.1 Cache operation

The cache works as follows, for each page for which it is enabled:

• If data is read and is not in the cache (a cache miss), a line of eight 32-bit words is

read from the AHB bus. The CPU waits until this process is complete.

• If data is read and is found in the cache (a cache hit), data is read from cache with

zero wait states.

• If data is written, and the location is not in the cache (a cache miss), the data is written

directly to memory.

• If data is written, and the location is in the cache because this location has been read

before (a cache hit), the data is written into the cache with zero wait states, and the

cache line is marked as ‘dirty’.

• If a ‘dirty’ cache line is about to be discarded because of a cache miss (the cache line

needs to be reused for a different memory region), the old line is written back to

memory (a cache-line ﬂush).

The cache can be set to data-only, instruction-only or combined (uniﬁed) caching. The

cache has 16 conﬁgurable pages, each 2 MB in range. The pages occupy the bottom

32 MB of the memory map. The virtual address and enable/disable status is conﬁgurable

for each page.

6.3.2 Features

• 8 kB, 2-way set-associative cache.

• May be used as both an instruction and data cache.

• Zero wait states for a cache hit.

• 16 conﬁgurable pages, each 2 MB in range.

6.4 Flash memory and programming

The LPC2888 incorporates 1 MB of ﬂash memory, while the LPC2880 is a ﬂash-less

device. The ﬂash memory of the LPC2888 may be used for both code and data storage.

Programming of the ﬂash memory may be accomplished in several ways. It may be

programmed In System via the USB port. The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility for

data storage, ﬁeld ﬁrmware upgrades, etc.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

15 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Programming the ﬂash in a running application is accomplished via a register interface on

the APB bus. The ﬂash module can generate an interrupt request when burning or erasing

is completed.

The ﬂash memory contains a buffer to allow for faster execution. Information is read from

the ﬂash 128 bits at a time. The buffer holds this entire amount, which can represent four

32-bit ARM instructions. These captured instructions can them be executed without ﬂash

read delays, improving system performance.

6.4.1 Features

• Flash access for processor execution and data read is via the AHB bus.

• Flash programming in a running application is via an APB register interface.

• Initial programming or reprogramming is can be accomplished from the USB port.

6.5 DC-to-DC converters

The LPC2880/2888 include two DC-to-DC converters providing an on-chip power system

which allows the device to be powered by a standard single cell battery (AA or AAA for

example) as well as receive power from a USB port or other power source.

The LPC2880/2888 need two supply voltages, 3.3 V and 1.8 V, for various internal

functions. When power is available from a higher voltage source such as USB, two

internal Low Dropout regulators (LDO regulators) reduce the incoming voltage to the level

needed by the LPC2880/2888. When only a low voltage battery supply is available, two

DC-to-DC converters boost the voltage up to the needed levels. Switching between the

two modes is supported.

6.6 External memory controller

The LPC2880/2888 External Memory Controller (EMC) is a multi-port memory controller

that supports asynchronous static memory devices such as RAM, ROM and ﬂash, as well

as dynamic memories such as Single Data Rate SDRAM. It complies with ARM’s AMBA.

6.6.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and ﬂash, with or

without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8-bit and 16-bit static memory support.

• 16-bit SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read.

– Programmable wait states.

– Bus turnaround delay.

– Output enable and write enable delays.

– Extended wait.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

16 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

– 2 MB address range with three chip selects.

• One chip select for synchronous memory and three chip selects for static memory

devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048, 4096, and 8192 row address synchronous memory parts.

That is typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per

device.

Remark: Synchronous static memory devices (synchronous burst mode) are not

supported.

6.7 GPIO

Many device pins that are not needed for a speciﬁc peripheral function can be used as

GPIOs. These pins can be controlled by the mode registers. Pins may be dynamically

conﬁgured as inputs or outputs. Separate registers allow setting or clearing any number of

outputs simultaneously. The current state of the port pins may be read back via the PIN

registers.

6.7.1 Features

• 81 pins have dual use as a speciﬁc function I/O or as a GPIO.

• Each dual use pin can be programmed for functional I/O, drive high, drive low, or

hi-Z/input.

• Four pins are dedicated as GPIO, programmable for drive high, drive low, or

hi-Z/input.

6.8 Interrupt controller

The interrupt controller accepts all of the interrupt request inputs and categorizes them as

FIQ or IRQ. The programmable assignment scheme means that priorities of interrupts

from the various peripherals can be dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the interrupt

controller combines the requests to produce the FIQ signal to the ARM processor.

The interrupt controller combines the requests from all the vectored IRQs to produce the

IRQ signal to the ARM processor. The IRQ service routine can start by reading a register

from the interrupt controller and jumping there.

6.8.1 Features

• Maps all LPC2880/2888 interrupt sources to processor FIQ and IRQ

• Level sensitive sources

• Programmable priority among sources

• Nested interrupt capability

• Software interrupt capability for each source

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

17 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

6.9 Event router

88 external and 11 internal LPC2880/2888 signals are connected to the Event Router

block. GPIO input pins, functional input pins, and even functional outputs can be

monitored by the Event Router.

Each signal can act as an interrupt source or a clock-enable for LPC2880/2888 modules,

with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity.

The outputs of the polarity and sensitivity logic can be read from Raw Status Registers 0

to 3.

Each active state is next masked/enabled by a “global” mask bit for that signal. The results

can be read from Pending Registers 0 to 3.

All 99 Pending signals are presented to each of the ﬁve output logic blocks. Each output

logic block includes a set of four Interrupt Output Mask Registers, each set totalling

99 bits, that control whether each signal applies to that output. These are logically ANDed

with the corresponding Pending signals, and the 99 results in each logic block are logically

ORed to make the output of the block. The 496 results can be read in the Interrupt Output

Pending Registers.

Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually

enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it

can serve to enable clocking for selected clock domains. The ﬁve outputs can be read in

the Output Register.

6.10 General purpose timers

The LPC2880/2888 contains two fully independent general purpose timers. Each timer is

a 32 bit wide down counter with a selectable prescaler. The prescaler allows either the

system clock to be used directly, or the clock to be divided by 16 or 256.

Two modes of operation are available, free-running and periodic timer. In periodic timer

mode, the counter will generate an interrupt at a constant interval. In free-running mode

the timer will overﬂow after reaching its zero value and continue to count down from the

maximum value.

6.10.1 Features

• Two independent 32-bit timers.

• Free-running or periodic operating modes.

• Generate timed interrupts.

6.11 Watchdog timer

The purpose of the watchdog timer is to interrupt and/or reset the microcontroller within a

reasonable amount of time if it enters an erroneous state. When enabled, the watchdog

will generate an interrupt or a system reset if the user program fails to reset the watchdog

within a predetermined amount of time. Alternatively, it can be used as an additional

general purpose Timer.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

18 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

The WDT clock increments a 32-bit Prescale Counter, the value of which is continually

compared to the value of the Prescale Register. When the Prescale Counter matches the

Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit

Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the

value in the Prescale Register plus one.

The value of the Timer Counter is continually compared to the values in two registers

called Match Register 0 and 1. When/if the value of the Timer Counter matches that of

Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router,

which can be programmed to send an interrupt signal to the Interrupt Controller as a

result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT

clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result.

The CGU also includes a ﬂag to indicate whether a reset is due to a watchdog time-out.

6.11.1 Features

• Optionally resets chip (via Clock Generation Unit) if not periodically reloaded.

• Optional interrupt via Event Router.

• 32-bit Prescaler and 32-bit Counter allow extended watchdog period.

6.12 Real-time clock

The Real-time clock is a set of counters for measuring time when system power is on, and

optionally when it is off. It uses little power in either mode.

6.12.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra Low Power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Dedicated 32 kHz oscillator.

• Dedicated power supply pin can be connected to a battery or to the main 1.8 V.

6.13 General purpose DMA controller

The General Purpose DMA controller (GPDMA) is an AMBA AHB compliant master

allowing selected LPC2880/2888 peripherals to have DMA support. Peripherals that can

be serviced by the GPDMA channels include the SD/MCI card interface, UART TX and/or

RX, the I²C-bus interface, the Simple Analog Out (SAO) front-ends to the I²S/DAO and

16-bit dual DACs, the Simple Analog In (SAI) interfaces for data from the I²S/DAI and

16-bit dual ADCs, and the LCD interface.

6.13.1 Features

• Eight DMA channels. Each channel can support a unidirectional transfer, or a pair of

channels can be used together to follow a linked list of buffer addresses and transfer

counts.

The GPDMA provides 16 peripheral DMA request lines. Most of these are connected

to the peripherals listed above; two can be used for external requests.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

19 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

• The GPDMA supports a subset of the ﬂow control signals supported by ARM DMA

channels, speciﬁcally ‘single’ but not ‘burst’ operation.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Rotating channel priority. Each DMA channel has equal opportunity to perform

transfers.

• The GPDMA is one of three AHB masters in the LPC2880/2888, the others being the

ARM7 processor and the USB interface.

• Incrementing or non-incrementing addressing for source and destination.

• Supports 8 bit, 16 bit, and 32 bit wide transactions.

• GPDMA channels can be programmed to swap data between big- and little-endian

formats during a transfer.

• An interrupt to the processor can be generated on DMA completion, when a DMA

channel is halfway to completion, or when a DMA error has occurred.

6.14 UART and IrDA

The LPC2880/2888 contains one UART with baud rate generator and IrDA support.

6.14.1 Features

• 32-Byte Receive and Transmit FIFOs.

• Register locations conform to the 16C650 industry standard.

• Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B.

• Built-in baud rate generator.

• CGU generates UART clock including fractional divider capability.

• Auto baud capability.

• Optional hardware ﬂow control.

• IrDA mode for infrared communication.

6.15 I²C-bus interface

The LPC2880/2888 I²C-bus interface is byte oriented and has four operating modes:

master Transmit mode, master Receive mode, slave Transmit mode and slave Receive

mode. The interface complies with the entire I²C-bus speciﬁcation, and allows turning

power off to the LPC2880/2888 without causing a problem with other devices on the same

I²C-bus.

6.15.1 Features

• Standard I²C-bus interface, conﬁgurable as Master, Slave, or Master/Slave.

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Programmable clock allows adjustment of I²C-bus transfer rates.

• Bidirectional data transfer between masters and slaves.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

20 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• Supports normal (100 kHz) and fast (400 kHz) operation.

6.16 10-bit ADC

The LPC2880/2888 contains a single 10-bit successive approximation ADC with ﬁve

multiplexed channels.

6.16.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 5 pins.

• Power-down mode.

• Measurement range 0 V to 3.3 V.

• 10-bit conversion time ≥ 2.44 µs.

• Single or continuous conversion mode.

6.17 Analog I/O

The analog I/O system includes an I²S-bus input channel, an I²S-bus output channel, a

dual ADC, and a dual DAC. Each channel includes a separate 4-sample FIFO.

Each of the two ADC inputs is connected to a Programmable Gain Ampliﬁer (PGA).

Each DAC has two output pins.

6.17.1 Features

• I²S-bus input channel with a 4-sample FIFO for stereo DAI.

• I²S-bus output channel with a 4-sample FIFO for stereo DAO.

• Dual 16-bit ADCs with individual inputs routed through programmable gain ampliﬁers.

Input takes place through a 4-sample FIFO.

• Dual 16-bit DACs. Each DAC has its own output pin. Output takes place through a

4-sample FIFO.

6.18 USB 2.0 Hi-Speed device controller

The USB is a 4-wire bus that supports communication between a host and a number (127

maximum) of peripherals. The host controller allocates the USB bandwidth to attached

devices through a token based protocol. The bus supports hot plugging, un-plugging and

dynamic conﬁguration of the devices. All transactions are initiated by the host controller.

The host schedules transactions in 1 ms frames. Each frame contains an SOF marker and

transactions that transfer data to/from device endpoints. There are four types of transfers

deﬁned for the endpoints. Control transfers are used to conﬁgure the device. Interrupt

transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer

is not critical. Isochronous transfers have guaranteed delivery time but no error correction.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

21 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

The LPC2880/2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange with a

USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX

physical interface.

The USB controller consists of the protocol engine and buffer management blocks. It

includes an SRAM that is accessible to the DMA engine and to the processor via the

register interface.

The DMA engine is an AHB master, having direct access to all of ARM memory space but

particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via

DMA is allocated to a logical DMA channel in the DMA engine.

Endpoints with small packet sizes can be handled by software via registers in the USB

controller. In particular, Control Endpoint 0 is always handled in this way.

6.18.1 Features

• Fully compliant with USB 2.0 speciﬁcation (Hi-Speed and Full-Speed).

• 8 logical endpoints = 16 physical endpoints.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Endpoint type selection by software.

• Endpoint maximum packet size setting by software.

• Supports SoftConnect feature (requires an external 1.5 kΩ resistor between the

CONNECT pad and 3.3 V).

• Supports bus-powered capability with low suspend current.

• Two DMA channels, assignable to any of 4 physical endpoints.

• Supports Burst data transfers on the AHB.

• Supports Retry and Split transactions on the AHB.

6.19 SD/MMC card interface

The SD and MCI is an interface between the APB and multimedia and/or secure digital

memory cards.

The interface provides all functions speciﬁc to the Secure Digital/MultiMedia memory

card, such as the clock generation unit, power management control, command, data

transfer, interrupt generation, and DMA request generation.

6.19.1 Features

• Conformance to Multimedia Card Speciﬁcation v2.11.

• Conformance to Secure Digital Memory Card Physical Layer Speciﬁcation, v0.96.

• Use as a multimedia card bus or a secure digital memory card bus host. It can be

connected to several multimedia cards, or a single secure digital memory card.

• DMA transfers are supported through the Simple DMA facility.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

22 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

6.20 LCD interface

The LCD interface contains logic to interface to a 6800 or 8080 bus compatible LCD

controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus

standard, with one address pin (RS) for selecting the data or instruction register.

The LCD interface makes use of a conﬁgurable clock (programmed in the CGU) to adjust

the speed of the 6800/8080 bus to the speed of the connected peripheral.

6.20.1 Features

• 8-bit or 4-bit parallel interface mode: 6800-series, 8080-series.

• Selectable bus frequency supports high and low speed LCD controllers.

• Supports polling the busy ﬂag from the LCD controller to avoid CPU polling.

• Contains a 16 B FIFO for sending control and data information to the LCD controller.

• Contains a serial interface which uses the same FIFO for serial transmissions.

• Supports FIFO level ﬂow control to the General Purpose DMA controller.

6.21 Clocking and power control

Clocking in the LPC2880/2888 is controlled by a versatile CGU, so that system and

peripheral requirements may be met while allowing optimization of power consumption.

Clocks to most functions may be turned off if not needed, and may be enabled and

disabled by selected events through the Event Router.

Clock sources include a high frequency (1 MHz to 20 MHz) crystal oscillator and a 32 kHz

RTC oscillator. Higher frequency clocks may be generated through the use of two

programmable PLLs.

Reset of individual functional blocks is also controlled by the CGU. Full chip reset can be

initiated by the external reset pin or by the watchdog timer.

6.21.1 Features

• Power and performance control provided by versatile clock generation to individual

functional blocks.

• Multiple clock sources including external crystal and programmable PLLs.

• Individual control of software reset to many functional blocks.

6.21.2 Reset

The LPC2880/2888 has two sources of reset: the RESET pin and the watchdog reset. The

RESET pin includes an on-chip pull-up. RESET must remain low at power-up for 1 ms

after power supply voltages are stable. This includes on-chip DC-to-DC converter

voltages.

When either reset is removed, the processor begins executing at address 0, which is the

reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

23 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

The on-chip watchdog timer can cause a chip reset if not updated within a programmable

time interval. A status register allows software to determine if a reset was caused by the

watchdog timer. The watchdog timer can also be conﬁgured to generate an interrupt if

desired.

Software reset of many individual functional blocks may be performed via registers within

the CGU.

6.21.3 Crystal oscillator

The main oscillator is the basis for the clocks most chip functions use by default. The

oscillator may be used with crystal frequencies from 1 MHz to 20 MHz.

6.21.4 PLLs

The LPC2880/2888 includes two PLLs: the main PLL provides clocks to most chip

functions, and a high-speed PLL that can be used to generate faster clocks for selected

chip functions. Each PLL can be driven from several clock sources. These include the

main oscillator (1 MHz to 20 MHz), the RTC oscillator (32 kHz), the bit clock or word

select inputs of the I²S input channel, the clock input from the SD/MMC card interface, or

the output clock from the other PLL.

The low power PLL takes the input clock and multiplies it up to a higher frequency (by 1 to

32), then divides it down (by 1, 2, 4, or 8) to provide the output clock used by the CGU.

The output frequency of this PLL can range from 10 MHz to 320 MHz. Functional blocks

may have limitations below this upper limit.

The high-speed PLL takes the input clock, optionally divides it down (by 1 to 256), then

multiplies it up to a higher frequency (by 1 to 1024), then divides it down (by 1 to 16) to

provide the output clock used by the CGU. The output frequency of this PLL can range

from 4.3 MHz to 550 MHz. Functional blocks may have limitations below this upper limit.

6.21.5 Power control and modes

Power control on the LPC2880/2888 is accomplished by detailed control over the clocking

of each functional block via the CGU. The LPC2880/2888 includes a very versatile

clocking scheme that provides a great deal of control over performance and power usage.

On-chip functions are divided into 11 groups. Each group has a selection for one of

several basic clock sources. Graceful (glitch-free) switching between these clock sources

is provided.

Three of these functional groups include one fractional divider that allows any rate below

the selected clock to be derived. Three other functional groups include more than one

fractional divider, allowing several different slower clocks to be generated within the group.

Each function within the group can then be assigned to use any one of the generated

clocks.

Each function within any group can also be individually turned off by disabling the clock to

that function. When added to the versatile clock rate selection, this allows very detailed

control of power utilization.

Each function also can be conﬁgured to have clocks automatically turned on and off

based on a signal from the Event Router.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

24 of 43

LPC2880; LPC2888

NXP Semiconductors

6.21.6 APBs

16/32-bit ARM microcontrollers with external memory interface

Most peripheral functions are accessed by on-chip APBs that are attached to the higher

speed AHB. The APBs perform reads and writes to peripheral registers in three peripheral

clocks.

6.22 Emulation and debugging

The LPC2880/2888 supports emulation via a dedicated JTAG serial port. The dedicated

JTAG port allows debugging of all chip features without impact to any pins that may be

used in the application.

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM core.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

25 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD(1V8)

V_DD(3V3)

V_DD(EMC)

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage (1.8 V)

supply voltage (3.3 V)

+1.95

+4.6

V

external memory controller

supply voltage

in 1.8 V range

in 3.3 V range

+1.95

+3.6

V

V_IA

V_I

analog input voltage

input voltage

V_DD(ADC3V3)

+6.0

V

[2][4]

5 V tolerant pins

other pins

V

[2][3][4]

input voltage

V_DD+ 0.5

100

V

I_DD

supply current

per supply pin

per ground pin

mA

°C

W

I_SS

ground current

storage temperature

-

100

T_stg

−40

-

+125

1.5

[5]

[6]

P_tot(pack)

total power dissipation (per

package)

V_esd

electrostatic discharge voltage

human body model

all pins

−1000

+1000

V

[1] The following applies to Table 5:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] All inputs are 5 V tolerant except external memory bus and USB pins.

[3] Referenced to the applicable V_DDfor the pin. Not to exceed 4.6 V.

[4] Including voltage on outputs in 3-state mode.

[5] Based on package heat transfer, not device power consumption.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

26 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

8. Static characteristics

Table 6.

Static characteristics

T_amb= −40 °C to +85 °C, unless otherwise speciﬁed.

Symbol

V_DD(1V8)

V_DD(3V3)

V_DDA(3V3)

V_DD(EMC)

Parameter

Conditions

Min

1.7

3

Typ^[1]

1.8

Max

1.95

3.6

Unit

V

[2]

[3]

[4]

[5]

supply voltage (1.8 V)

supply voltage (3.3 V)

analog supply voltage (3.3 V)

3.3

V

3

3.3

3.6

V

external memory controller

supply voltage

in 1.8 V range

in 3.3 V range

1.7

2.7

1.8

1.95

3.6

V

3.3

V

Standard pins

I_IL

LOW-level input current

HIGH-level input current

OFF-state output current

V_I= 0 V; no pull-up

-

1

µA

[6]

I_IH

I_OZ

V_I= V_DD; no pull-down

V_O= 0 V; V_O= V_DD; no

pull-up/down

V_hys(i)

I_latch

V_I

input hysteresis voltage

I/O latch-up current

input voltage

300

-

mV

mA

V

[6]

[6][7]

[6][7][10]

[8]

−(1.5V_DD) < V_I< (1.5V_DD

)

-

100

V_DD

5.5

-

0

-

0

-

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

1.6

2.0

-

V

[9]

-

V

[8]

-

0.6

0.8

-

V

[9]

-

V

[8][11]

[9][11]

[8][11]

[9][11]

[6][11]

[12]

V_OH

I_OH= −1 mA

I_OH= −4 mA

I_OL= 4 mA

V

-

_DD− 0.4

-

V

_DD− 0.4

-

V

V_OL

-

0.4

-

V

I_OL= 4 mA

-

V

I_OH

I_OL

HIGH-level output current

LOW-level output current

V_OH= V_DD− 0.4 V

V_OL= 0.4 V

-

−4

4

mA

-

I_OHS

HIGH-level short-circuit output V_OH= 0 V

current

-

−45

-

[6][12]

I_OLS

I_pu

LOW-level short-circuit output

current

V_OL= V_DD

-

50

-

mA

[6]

[6][10]

[6]

pull-up current

V_I= 0 V

−13

-

−36

0

−50

-

µA

V_DD< V_I< 5.5 V

V_I= V_DD

I_pd

pull-down current

20

50

75

I²C-bus pins

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

input hysteresis voltage

LOW-level output voltage

input leakage current

3.5

-

V

-

1.5

-

V

V_hys(i)

V_OL

I_LI

250

-

mV

V

I_OL= 3 mA

V_I= V_DD

V_I= 5 V

-

0.4

4

[6]

2

10

µA

22

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

27 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Oscillator pins

V_i(xtal)

crystal input voltage

crystal output voltage

on pins XTALI and X32I

on pins XTALO and X32O

0

-

1.8

V

V_o(xtal)

DC-to-DC converter

V_BAT

battery supply voltage

0.9

-

1.2

3.2

1.6

-

V

V_O(DCDC1)

DC-to-DC converter 1 output

voltage

V_BAT= 1.2 V;

I

_{L(DCDC1)(max)}= 100 mA

I_{L(DCDC1)(max)}maximum DC-to-DC converter

1 load current

-

100

12

-

mA

MHz

V

f_{i(clk)(DCDC1)}DC-to-DC converter 1 clock

input frequency

V_O(DCDC2)

DC-to-DC converter 2 output

voltage

V_BAT= 1.2 V;

_{L(DCDC2)(max)}= 90 mA

1.83

90

I

I_{L(DCDC2)(max)}maximum DC-to-DC converter

2 load current

mA

MHz

f_{i(clk)(DCDC2)}DC-to-DC converter 2 clock

input frequency

12

V_USB

USB supply voltage

LDO1 output voltage

4.0

-

5.0

3.4

5.5

-

V

V_O(LDO1)

V_USB= 5.0 V;

_L(LDO1)(max)= 150 mA

I

I_L(LDO1)(max)maximum LDO1 load current

V_O(LDO2)LDO2 output voltage

-

150

-

mA

V

V_USB= 5.0 V;

_L(LDO2)(max)= 100 mA

1.88

I

I_L(LDO2)(max)maximum LDO2 load current

-

100

-

mA

Power consumption

[13]

[14]

I_DD(CORE)

I_DD(EMC)

core supply current

V_DD= 1.8 V

-

60

-

mA

external memory controller

supply current

V_DD(EMC)= 1.8 V;

HCLK = 18 MHz

1.2

[14]

V_DD(EMC)= 3.3 V;

HCLK = 36 MHz

-

2.2

-

mA

I_BAT

battery supply current

oscillator supply current

RTC supply current

V_{DCDC_VBAT}= 1.2 V

powered down

oscillator running

oscillator powered down

oscillator running

oscillator powered down

normal

-

130

18

300

-

mA

µA

mA

µA

mA

µA

-

[15]

[16]

[17]

[18]

[19]

I_CC(osc)

I_DD(RTC)

I_DD(ADC)

I_DDIA

-

10

300

-

10

ADC supply current

-

400

powered down

normal

-

< 1

analog input supply current

DAC output supply current

6

-

powered down

normal

10

0.7

10

I_DDO(DAC)

powered down

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

28 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise speciﬁed.

Symbol Parameter Conditions

Power consumption (battery supplies voltage)

I_BATbattery supply current stop mode

Power consumption (DC-to-DC converter supplies voltage)

Min

Typ^[1]

17.7

Max

Unit

µA

[20]

-

I_DD

supply current

32.768 kHz oscillator runs;

12 MHz oscillator stops;

DC-to-DC converter

supplies 1.8 V

0.20

mA

[20]

32.768 kHz oscillator stops;

12 MHz oscillator runs;

DC-to-DC converter

supplies 1.8 V

-

0.99

0.79

-

mA

32.768 kHz oscillator runs;

12 MHz oscillator stops;

DC-to-DC converter

supplies 3.3 V

32.768 kHz oscillator stops;

12 MHz oscillator runs;

DC-to-DC converter

supplies 3.3 V

Power consumption (LDO regulator supplies voltage)

[20]

I_DD

supply current

32.768 kHz oscillator runs;

12 MHz oscillator stops;

LDO regulator supplies

1.8 V

-

1.61

-

mA

[20]

I_DD

supply current

32.768 kHz oscillator stops;

12 MHz oscillator runs; LDO

regulator supplies 1.8 V

-

2.47

3.12

-

mA

I_DD

32.768 kHz oscillator runs;

12 MHz oscillator stops;

LDO regulator supplies

3.3 V

[20]

I_DD

supply current

32.768 kHz oscillator stops;

12 MHz oscillator runs; LDO

regulator supplies 3.3 V

-

3.12

0.20

-

mA

Power consumption (external DC-to-DC converter supplies voltage)

I_DD

supply current

32.768 kHz oscillator runs;

12 MHz oscillator stops;

external DC-to-DC

converter supplies 1.8 V

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

29 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 6.

Static characteristics …continued

T_amb= −40 °C to +85 °C, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[20]

I_DD

supply current

32.768 kHz oscillator stops;

12 MHz oscillator runs;

external DC-to-DC

-

0.97

-

mA

converter supplies 1.8 V

I_DD

supply current

32.768 kHz oscillator runs;

12 MHz oscillator stops;

external DC-to-DC

-

1.27

-

mA

converter supplies 3.3 V

I_DD

32.768 kHz oscillator stops;

12 MHz oscillator runs;

external DC-to-DC

converter supplies 3.3 V

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[2] Applies to pins V_DD1(CORE1V8), V_DD2(CORE1V8), V_DD(DADC1V8), V_{DD1(FLASH1V8)}, V_{DD2(FLASH1V8)}, V_DD(OSC1V8), V_DD(OSC321V8), V_DD1(USB1V8)

V_DD2(USB1V8)

[3] External supply voltage; applies to pins V_DD3(USB3V3), V_DD4(USB3V3), V_DD1(IO3V3), V_DD2(IO3V3), V_DD3(IO3V3), V_DD4(IO3V3)

[4] Applies to pins V_DD(DADC3V3), V_DD(ADC3V3), V_DD(DAC3V3), V_DD5(IO3V3), V_DD6(IO3V3)

[5] External supply voltage; applies to pins V_DD1(EMC), V_DD2(EMC)

,

.

[6] Referenced to the applicable V_DDfor the pin, which must be present.

[7] Including voltage on outputs in 3-state mode.

[8] Applies to pins with a V_DDsupply of 1.8 V.

[9] Applies to pins with a V_DDsupply of 3.3 V.

[10] Applies to 5 V tolerant pins.

[11] Accounts for 100 mV voltage drop in all supply lines.

[12] Only allowed for a short time period.

[13] Applies to pins V_DD1(CORE1V8), V_DD2(CORE1V8), V_{DD1(FLASH1V8)}, V_{DD2(FLASH1V8)}

[14] Applies to pins V_DD1(EMC), V_DD2(EMC)

[15] Applies to pin V_DD(OSC1V8)

[16] Applies to pin V_DD(OSC321V8)

[17] Applies to pin V_DD(ADC3V3)

[18] Applies to pins V_DD(DADC1V8), V_DD(DADC3V3)

[19] Applies to pin V_DD(DAC3V3)

.

[20] All the above tests were done on the Icetech LPC288x evaluation board. Here are the different conﬁgurations that need to be done to

achieve the above numbers:

a) Resistors R7 and R8 on the board should be removed to reduce the power consumption on the LED’s D2 and D3.

b) The Analog-to-Digital Converter (ADC), the Dual-channel 16-bit Analog-to-Digital Converter and the Dual-channel 16-bit

Digital-to-Analog Converter are powered down.

c) The USB device controller is suspended.

d) All power control registers in the Clock Generation Unit have a value of 7h, and the Power Mode register in the Clock Generation Unit

has a value of 3h such that the output clocks of all spreading stages are disabled.

e) The ﬂoating pins are set to output state.

f) The Event Router is conﬁgured in such a way that it will generate its wake-up output to the Clock Generation Unit with a rising-edge

signal on the MODE1/P2[2] or the MODE2/P2[3].

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

30 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

9. Dynamic characteristics

Table 7.

Dynamic characteristics

T_amb= −40 °C to +85 °C, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External clock

[2]

f_ext

external clock frequency

1

12

20

MHz

Port pins

t_r

t_f

rise time

fall time

-

5

-

ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Supplied by an external crystal.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

31 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 8.

Dynamic characteristics: static external memory interface

C_L= 25 pF, T_amb= 20 °C, V_DD1(EMC)= V_DD2(EMC)= 3.3 V and 1.8 V.

Symbol Parameter Conditions Min Typ

Common to read and write cycles

Max Unit

t_CSLAV

CS LOW to address valid

time

-

0

-

ns

Read cycle parameters

[1]

t_OELAV

OE LOW to address valid

time

-

0 − WAITOEN × HCLK

-

ns

t_BLSLAV

BLS LOW to address valid

time

t_CSLOEL

t_CSLBLSL

t_OELOEH

CS LOW to OE LOW time

CS LOW to BLS LOW time

OE LOW to OE HIGH time

-

0 + WAITOEN × HCLK

-

ns

[1]

[1][2][3]

0 + WAITOEN × HCLK

(WAITRD − WAITOEN + 1) × HCLK

t_BLSLBLSHBLS LOW to BLS HIGH time

(WAITRD − WAITOEN + 1) × HCLK

t_su(DQ)

t_h(DQ)

data input/output set-up time

data input/output hold time

CS HIGH to OE HIGH time

33.3

0

t_CSHOEH

0

t_CSHBLSHCS HIGH to BLS HIGH time

0

t_OEHANV

OE HIGH to address invalid

time

2 × HCLK

t_BLSHANVBLS HIGH to address invalid

time

-

2 × HCLK

-

ns

Write cycle parameters

t_CSLDV

CS LOW to data valid time

CS LOW to WE LOW time

CS LOW to BLS LOW time

WE LOW to data valid time

WE LOW to WE HIGH time

-

0

-

ns

[4]

t_CSLWEL

t_CSLBLSL

t_WELDV

(WAITWEN + 1) × HCLK

WAITWEN × HCLK

[4]

0 − (WAITWEN + 1) × HCLK

(WAITWR − WAITWEN + 1) × HCLK

(WAITWR − WAITWEN + 3) × HCLK

1 × HCLK

[4][5][6]

[4][5]

t_WELWEH

t_BLSLBLSHBLS LOW to BLS HIGH time

t_WEHANV

WE HIGH to address invalid

time

t_WEHDNV

WE HIGH to data invalid time

-

1 × HCLK

-

ns

t_BLSHANVBLS HIGH to address invalid

time

0

t_BLSHDNVBLS HIGH to data invalid

time

-

0

-

ns

[1] Refer to the LPC2800 user manual UM10208_2 for the programming of WAITOEN and HCLK.

[2] Refer to the LPC2800 user manual UM10208_2 for the programming of WAITRD and HCLK.

[3] (WAITRD − WAITOEN + 1) = 3 min at 60 MHz.

[4] Refer to the LPC2800 user manual UM10208_2 for the programming of WAITWEN and HCLK.

[5] Refer to the LPC2800 user manual UM10208_2 for the programming of WAITWR and HCLK.

[6] (WAITWD − WAITWEN + 1) = 3 min at 60 MHz.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

32 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 9.

Dynamic characteristics: dynamic external memory interface

C_L= 25 pF, T_amb= 20 °C, V_DD1(EMC)= V_DD2(EMC)= 3.3 V.

Symbol Parameter Conditions

Read cycle parameters^[1]

Min

Typ

Max

Unit

t_CHCX

t_CLCX

T_CLCL

t_su(S)

clock HIGH time

-

11.1

27.8

7.5

-

ns

clock LOW time

clock cycle time

chip select set-up time

chip select hold time

row address strobe set-up time

row address strobe hold time

t_h(S)

3.5

t_su(RAS)

t_h(RAS)

t_su(CAS)

7.5

3.5

column address strobe set-up

time

7.5

t_h(CAS)

t_su(G)

t_h(G)

column address strobe hold time

output enable set-up time

output enable hold time

address set-up time

-

3.5

7.5

3.5

7.5

3.5

23.5

3.5

-

ns

t_su(A)

t_h(A)

t_su(DQ)

t_h(DQ)

address hold time

data input/output set-up time

data input/output hold time

Write cycle parameters^[2]

t_CHCX

t_CLCX

T_CLCL

t_su(S)

clock HIGH time

-

11.1

27.8

7.5

-

ns

clock LOW time

clock cycle time

chip select set-up time

chip select hold time

row address strobe set-up time

row address strobe hold time

t_h(S)

3.5

t_su(RAS)

t_h(RAS)

t_su(CAS)

7.5

3.5

column address strobe set-up

time

7.5

t_h(CAS)

t_su(W)

t_h(W)

column address strobe hold time

write set-up time

-

3.5

7.5

3.5

7.5

3.5

7.5

3.5

16.5

10.5

-

ns

write hold time

t_su(DQM)

t_h(DQM)

t_su(A)

DQM set-up time

DQM hold time

address set-up time

address hold time

t_h(A)

t_su(DQ)

t_h(DQ)

data input/output set-up time

data input/output hold time

[1] CKE is HIGH during the read cycle.

[2] CKE is HIGH during the write cycle

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

33 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

Table 10. Dynamic characteristics: dynamic external memory interface

C_L= 25 pF, T_amb= 20 °C, V_DD1(EMC)= V_DD2(EMC)= 1.8 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Read cycle parameters^[1]

t_CHCX

t_CLCX

T_CLCL

t_su(S)

clock HIGH time

-

23

-

ns

clock LOW time

23

clock cycle time

55.6

40

chip select set-up time

chip select hold time

row address strobe set-up time

row address strobe hold time

t_h(S)

3.5

40

t_su(RAS)

t_h(RAS)

t_su(CAS)

3.5

40

column address strobe set-up

time

t_h(CAS)

t_su(G)

t_h(G)

column address strobe hold time

output enable set-up time

output enable hold time

address set-up time

-

3.5

40

-

ns

3.5

36

t_su(A)

t_h(A)

t_su(DQ)

t_h(DQ)

address hold time

19.5

51.5

4

data input/output set-up time

data input/output hold time

Write cycle parameters^[2]

t_CHCX

t_CLCX

T_CLCL

t_su(S)

clock HIGH time

-

23

-

ns

clock LOW time

23

clock cycle time

55.6

40

chip select set-up time

chip select hold time

row address strobe set-up time

row address strobe hold time

t_h(S)

3.5

40

t_su(RAS)

t_h(RAS)

t_su(CAS)

3.5

40

column address strobe set-up

time

t_h(CAS)

t_su(W)

t_h(W)

column address strobe hold time

write set-up time

-

3.5

40

-

ns

write hold time

3.5

40

t_su(DQM)

t_h(DQM)

t_su(A)

DQM set-up time

DQM hold time

3.5

36

address set-up time

address hold time

t_h(A)

19.5

31

t_su(DQ)

t_h(DQ)

data input/output set-up time

data input/output hold time

24.5

[1] CKE is HIGH during the read cycle.

[2] CKE is HIGH during the write cycle.

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

34 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

9.1 Timing

STCS

t

CSLAV

A

t

CSHOEH

t

OELAV

OE

t

OELOEH

t

CSLOEL

BLSLAV

OEHANV

CSHBLSH

BLS

t

BLSLBLSH

t

CSLBLSL

BLSHANV

D

t

h(DQ)

t

su(DQ)

002aac966

Fig 4. External memory read access to static memory

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

35 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

STCS

t

CSLAV

A

t

BLSHANV

WEHANV

t

CSLDV

D

t

WELWEH

t

CSLWEL

WEHDNV

BLSHDNV

WE

WELDV

t

BLSLBLSH

t

CSLBLSL

BLS

002aac974

Fig 5. External memory write access to static memory

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

36 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

T

CLCL

t

CHCX

CLK

t

CLCX

DYCS

t

h(S)

t

su(S)

RAS

t

h(RAS)

su(RAS)

CAS, DQM

t

h(CAS), h(G)

t

su(CAS), su(G)

A

t

h(A)

t

su(A)

D

t

h(DQ)

su(DQ)

002aac975

Fig 6. External memory read access to dynamic memory

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

37 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

T

CLCL

t

CHCX

CLK

t

CLCX

DYCS

t

h(S)

t

su(S)

RAS

t

h(RAS)

su(RAS)

WE

t

h(W)

t

su(W)

CAS, DQM

t

h(CAS), h(DQM)

t

su(CAS), su(DQM)

A

t

h(A)

t

su(A)

D

t

h(DQ)

su(DQ)

002aac976

Fig 7. External memory write access to dynamic memory

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

38 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

10. Package outline

TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls; body 10 x 10 x 0.8 mm

SOT640-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

v

M

C

A

B

C

1

b

e

1/2 e

w M

V

U

R

N

L

e

T

P

M

K

H

F

e

2

J

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11 13 15 17

10 12 14 16 18

X

2

4

6

8

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

D

E

e

v

w

y

1

2

1

2

1

max.

0.31 0.84 0.39 10.1 10.1

mm 1.11

8.5

0.12

0.1

0.5

0.1

0.15

0.19 0.76 0.29

9.9

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

01-06-07

03-03-03

SOT640-1

MO-195

Fig 8. Package outline SOT640-1 (TFBGA180)

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

39 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

11. Abbreviations

Table 11. Acronym list

Acronym

ADC

Description

Analog-to-Digital Converter

Advanced Microcontroller Bus Architecture

Advanced High-performance Bus

Advanced Peripheral Bus

Complex Instruction Set Computer

Clock Generation Unit

AMBA

AHB

APB

CISC

CGU

DAC

Digital-to-Analog Converter

Direct Memory Access

DMA

DAI

Digital Audio Input

DAO

Digital Audio Output

FIQ

Fast Interrupt Request

GPIO

IrDA

General Purpose Input/Output

Infrared Data Association

Interrupt Request

IRQ

JTAG

LCD

Joint Test Action Group

Liquid Crystal Display

MCI

Multimedia Card Interface

Phase-Locked Loop

PLL

RISC

SD

Reduced Instruction Set Computer

Secure Digital

SD/MMC

SDRAM

SOF

Secure Digital/MultiMedia Card

Synchronous Dynamic Random Access Memory

Start Of Frame

SRAM

UART

USB

Static Random Access Memory

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

WDT

WatchDog Timer

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

40 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

12. Revision history

Table 12. Revision history

Document ID

Release date

20080417

Data sheet status

Change notice

Supersedes

LPC2880_LPC2888_3

Modiﬁcations:

Preliminary data sheet

-

LPC2880_2888_2

• Table 1 “Ordering information”; added /01 and /D1 parts.

• Table 2 “Ordering options”; added JTAG interface column to show the difference between

/01 and /D1 devices.

• Table 5; ESD speciﬁcation added.

• Table 6; DC-to-DC converter and power consumption characteristics added.

• Table 8, Table 9, Table 10; external memory interface dynamic characteristics added.

• Figure 1, changed ‘ARM7TDMI-S’ to ‘ARM7TDMI’.

• Figure 4, Figure 5, Figure 6, Figure 7; external memory interface timing diagrams added.

LPC2880_LPC2888_2

LPC2880_LPC2888_1

20061121

Preliminary data sheet

-

LPC2880_LPC2888_1

20060622

Preliminary data sheet

-

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

41 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

13.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

SoftConnect — is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

LPC2880_LPC2888_3

Preliminary data sheet

Rev. 03 — 17 April 2008

42 of 43

LPC2880; LPC2888

NXP Semiconductors

16/32-bit ARM microcontrollers with external memory interface

15. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

6.19

6.19.1

6.20

6.20.1

6.21

6.21.1

6.21.2

6.21.3

6.21.4

6.21.5

6.21.6

6.22

SD/MMC card interface . . . . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clocking and power control . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 24

PLLs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power control and modes. . . . . . . . . . . . . . . . 24

APBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Emulation and debugging. . . . . . . . . . . . . . . . 25

2

2.1

3

3.1

4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.2

Functional description . . . . . . . . . . . . . . . . . . 11

Architectural overview. . . . . . . . . . . . . . . . . . . 11

ARM7TDMI processor . . . . . . . . . . . . . . . . . . 12

On-chip ﬂash memory system . . . . . . . . . . . . 12

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 12

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 12

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Cache operation . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flash memory and programming . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC-to-DC converters . . . . . . . . . . . . . . . . . . . 16

External memory controller. . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 18

General purpose timers . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General purpose DMA controller . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

UART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

USB 2.0 Hi-Speed device controller . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

Static characteristics . . . . . . . . . . . . . . . . . . . 27

Dynamic characteristics. . . . . . . . . . . . . . . . . 31

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

8

9

9.1

10

11

12

6.3

6.3.1

6.3.2

6.4

6.4.1

6.5

6.6

6.6.1

6.7

6.7.1

6.8

6.8.1

6.9

6.10

6.10.1

6.11

6.11.1

6.12

6.12.1

6.13

6.13.1

6.14

6.14.1

6.15

6.15.1

6.16

6.16.1

6.17

6.17.1

6.18

6.18.1

13

Legal information . . . . . . . . . . . . . . . . . . . . . . 42

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.1

13.2

13.3

13.4

14

15

Contact information . . . . . . . . . . . . . . . . . . . . 42

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 April 2008

Document identifier: LPC2880_LPC2888_3


型号：	LPC2888FET180/01
厂家：	NXP
描述：	16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface 16位/ 32位ARM微控制器; 8 KB的高速缓存，高达1 MB闪存，高速USB 2.0设备，并且SDRAM存储器接口闪存存储微控制器和处理器外围集成电路动态存储器时钟
文件：	总43页 (文件大小：203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC2888FET180/01 [NXP]

相关型号：

LPC2888FET180/01-S

LPC2888FET180/D1

LPC2888FET180/D1,5

LPC2888FET180/D1-S

LPC2915

LPC2917

LPC2917/01

LPC2917FBD144

LPC2917FBD144/01

LPC2917FBD144/01,551

LPC2919

LPC2919/01