LPC2919FBD144/01/ [NXP]
32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144;型号: | LPC2919FBD144/01/ |
厂家: | NXP |
描述: | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144 微控制器 |
文件: | 总86页 (文件大小:393K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC2917/2919/01
ARM9 microcontroller with CAN and LIN
Rev. 02 — 17 June 2009
Preliminary data sheet
1. General description
The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM
blocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to
768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC2917/2919/01
has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and
scaling.
2. Features
I ARM968E-S processor running at frequencies of up to 125 MHz maximum.
I Multi-layer AHB system bus at 125 MHz with three separate layers.
I On-chip memory:
N Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data
TCM (DTCM).
N Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
N 8 kB ETB SRAM also available for code execution and data.
N Up to 768 kB high-speed flash-program memory.
N 16 kB true EEPROM, byte-erasable and programmable.
I Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
I External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
I Serial interfaces:
N Two-channel CAN controller supporting FullCAN and extensive message filtering
N Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
N Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and
RS485/EIA-485 (9 bit) support.
N Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
N Two I2C-bus interfaces.
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
I Other peripherals:
N Two 10-bit ADCs, 8 channels each, with 3.3 V measurement range and conversion
times as low as 2.44 µs per channel. Each channel provides a compare function to
minimize interrupts.
N Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external
signal input.
N Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
N Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
N Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
N Quadrature encoder interface that can monitor one external quadrature encoder.
N 32-bit watchdog with timer change protection, running on safe clock.
I Up to 108 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
I Vectored Interrupt Controller (VIC) with 16 priority levels.
I Up to 19 level-sensitive external interrupt pins, including CAN and LIN wake-up
features.
I Configurable clock-out pin for driving external system clocks.
I Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
I Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
I Flexible Clock-Generation Unit (CGU0) able to control clock frequency of individual
modules:
N On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
N On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz. PLL input range 10 MHz to 25 MHz.
N On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
N Generation of up to 11 base clocks.
N Seven fractional dividers.
I Second CGU (CGU1) with its own PLL generates a configurable clock output.
I Highly configurable system Power Management Unit (PMU):
N clock control of individual modules.
N allows minimization of system operating power consumption in any configuration.
I Standard ARM test and debug interface with real-time in-circuit emulator.
I Boundary-scan test supported.
I ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
I Dual power supply:
N CPU operating voltage: 1.8 V ± 5 %.
N I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
I 144-pin LQFP package.
I
−40 °C to +85 °C ambient operating temperature range.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
2 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC2917FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
LPC2919FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
SOT486-1
SOT486-1
3.1 Ordering options
Table 2.
Part options
Type number
Flash memory SRAM
SMC
LIN 2.0
CAN
Package
LPC2917FBD144/01
LPC2919FBD144/01
512 kB
768 kB
56 kB + 2 × 16 kB TCM 32-bit
56 kB + 2 × 16 kB TCM 32-bit
2
2
2
2
LQFP144
LQFP144
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
3 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
4. Block diagram
JTAG
interface
TEST/DEBUG
INTERFACE
LPC2917/01
LPC2919/01
ITCM
16 kB
DTCM
16 kB
8 kB SRAM
ARM968E-S
1 × master
2 × slave
master
master
slave
VECTORED
INTERRUPT
CONTROLLER
AHB TO DTL
GPDMA CONTROLLER
GPDMA REGISTERS
BRIDGE
slave
slave
slave
CLOCK
GENERATION
UNIT CGU0/1
AHB TO DTL
BRIDGE
EXTERNAL STATIC
MEMORY CONTROLLER
RESET
GENERATION
UNIT
slave
slave
EMBEDDED SRAM 16 kB
EMBEDDED SRAM 32 kB
POWER
MANAGEMENT
UNIT
slave
slave
EMBEDDED FLASH
512/768 kB
16 kB
EEPROM
slave
AHB
AHB TO APB
BRIDGE
TIMER0/1 MTMR
PWM0/1/2/3
MULTI
LAYER
MATRIX
AHB TO APB
BRIDGE
SYSTEM CONTROL
EVENT ROUTER
CHIP FEATURE ID
3.3 V ADC1/2
slave
QUADRATURE
ENCODER
AHB TO APB
BRIDGE
GENERAL PURPOSE I/O
PORTS 0/1/2/3
slave
AHB TO APB
BRIDGE
CAN0/1
TIMER 0/1/2/3
SPI0/1/2
GLOBAL
ACCEPTANCE
FILTER
RS485 UART0/1
WDT
LIN0/1
2
I C0/1
002aad959
Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA.
Fig 1. LPC2917/2919/01 block diagram
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
4 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
5. Pinning information
5.1 Pinning
1
108
LPC2917FBD144/01
LPC2919FBD144/01
36
73
002aae265
Fig 2. Pin configuration for SOT486-1 (LQFP144)
5.2 Pin description
5.2.1 General description
The LPC2917/2919/01 has up to four ports: two of 32 pins each, one of 28 pins and one of
16 pins. The pin to which each function is assigned is controlled by the SFSP registers in
the SCU. The functions combined on each port pin are shown in the pin description tables
in this section.
5.2.2 LQFP144 pin assignment
Table 3.
LQFP144 pin assignment
Pin name
Pin
Description
Default function
IEEE 1149.1 test data out
GPIO 2, pin 21
Function 1
Function 2
Function 3
TDO
1[1]
2[1]
P2[21]/SDI2/
PCAP2[1]/D19
SPI2 SDI
PWM2 CAP1
CAN1 TXD
EXTBUS D19
SPI2 SCS0
P0[24]/TXD1/
3[1]
GPIO 0, pin 24
UART1 TXD
TXDC1/SCS2[0
]
P0[25]/RXD1/
RXDC1/SDO2
4[1]
5[1]
6[1]
GPIO 0, pin 25
UART1 RXD
CAN1 RXD
SPI2 SDO
P0[26]/TXD1/
SDI2
GPIO 0, pin 26
-
-
-
-
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
SPI2 SDI
P0[27]/RXD1/
SCK2
P0[28]/CAP0[0]/ 7[1]
MAT0[0]
P0[29]/CAP0[1]/ 8[1]
MAT0[1]
GPIO 0, pin 27
SPI2 SCK
GPIO 0, pin 28
TIMER0 MAT0
TIMER0 MAT1
GPIO 0, pin 29
VDD(IO)
9
3.3 V power supply for I/O
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
5 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
GPIO 2, pin 22
Function 1
Function 2
Function 3
P2[22]/SCK2/
PCAP2[2]/D20
10[1]
SPI2 SCK
PWM2 CAP2
EXTBUS D20
P2[23]/SCS1[0]/ 11[1]
PCAP3[0]/D21
P3[6]/SCS0[3]/ 12[1]
PMAT1[0]/
GPIO 2, pin 23
GPIO 3, pin 6
SPI1 SCS0
SPI0 SCS3
PWM3 CAP0
PWM1 MAT0
EXTBUS D21
LIN1/UART TXD
TXDL1
P3[7]/SCS2[1]/ 13[1]
PMAT1[1]/
GPIO 3, pin 7
SPI2 SCS1
PWM1 MAT1
LIN1/UART RXD
RXDL1
P0[30]/CAP0[2]/ 14[1]
MAT0[2]
P0[31]/CAP0[3]/ 15[1]
MAT0[3]
P2[24]/SCS1[1]/ 16[1]
PCAP3[1]/D22
P2[25]/SCS1[2]/ 17[1]
PCAP3[2]/D23
GPIO 0, pin 30
GPIO 0, pin 31
GPIO 2, pin 24
GPIO 2, pin 25
-
TIMER0 CAP2
TIMER0 CAP3
PWM3 CAP1
PWM3 CAP2
TIMER0 MAT2
TIMER0 MAT3
EXTBUS D22
EXTBUS D23
-
SPI1 SCS1
SPI1 SCS2
VDD(CORE)
18
19
1.8 V power supply for digital core
ground for digital core
VSS(CORE)
P1[31]/CAP0[1]/ 20[1]
MAT0[1]/EI5
GPIO 1, pin 31
TIMER0 CAP1
TIMER0 MAT1
EXTINT5
VSS(IO)
P1[30]/CAP0[0]/ 22[1]
MAT0[0]/EI4
21
ground for I/O
GPIO 1, pin 30
TIMER0 CAP0
SPI2 SCS0
TIMER0 MAT0
PWM1 MAT2
PWM1 MAT3
PWM TRAP0
EXTINT4
P3[8]/SCS2[0]/ 23[1]
PMAT1[2]
P3[9]/SDO2/PM 24[1]
AT1[3]
P1[29]/CAP1[0]/ 25[1]
TRAP0/
GPIO 3, pin 8
GPIO 3, pin 9
GPIO 1, pin 29
-
SPI2 SDO
-
TIMER1 CAP0
PWM3 MAT5
PMAT3[5]
P1[28]/CAP1[1]/ 26[1]
TRAP1/
GPIO 1, pin 28
TIMER1 CAP1, ADC1 PWM TRAP1
EXT START
PWM3 MAT4
PMAT3[4]
P2[26]/CAP0[2]/ 27[1]
MAT0[2]/EI6
P2[27]/CAP0[3]/ 28[1]
MAT0[3]/EI7
P1[27]/CAP1[2]/ 29[1]
TRAP2/
GPIO 2, pin 26
GPIO 2, pin 27
GPIO 1, pin 27
TIMER0 CAP2
TIMER0 CAP3
TIMER0 MAT2
TIMER0 MAT3
EXTINT6
EXTINT7
TIMER1 CAP2, ADC2 PWM TRAP2
EXT START
PWM3 MAT3
PMAT3[3]
P1[26]/
30[1]
GPIO 1, pin 26
PWM2 MAT0
PWM TRAP3
PWM3 MAT2
PMAT2[0]/
TRAP3/
PMAT3[2]
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
6 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
3.3 V power supply for I/O
GPIO 1, pin 25
Function 1
Function 2
Function 3
VDD(IO)
31
32[1]
P1[25]/
PWM1 MAT0
-
PWM3 MAT1
PMAT1[0]/
PMAT3[1]
P1[24]/
33[1]
GPIO 1, pin 24
PWM0 MAT0
-
PWM3 MAT0
PMAT0[0]/
PMAT3[0]
P1[23]/
RXD0/CS5
34[1]
35[1]
GPIO 1, pin 23
GPIO 1, pin 22
UART0 RXD
UART0 TXD
-
-
EXTBUS CS5
EXTBUS CS4
P1[22]/TXD0/
CS4
TMS
36[1]
37[1]
IEEE 1149.1 test mode select, pulled up internally
IEEE 1149.1 test clock
TCK
P1[21]/CAP3[3]/ 38[1]
CAP1[3]/D7
P1[20]/CAP3[2]/ 39[1]
SCS0[1]/D6
P1[19]/CAP3[1]/ 40[1]
SCS0[2]/D5
P1[18]/CAP3[0]/ 41[1]
SDO0/D4
GPIO 1, pin 21
GPIO 1, pin 20
GPIO 1, pin 19
GPIO 1, pin 18
GPIO 1, pin 17
TIMER3 CAP3
TIMER3 CAP2
TIMER3 CAP1
TIMER3 CAP0
TIMER2 CAP3
TIMER1 CAP3,
MSCSS PAUSE
EXTBUS D7
EXTBUS D6
EXTBUS D5
EXTBUS D4
EXTBUS D3
SPI0 SCS1
SPI0 SCS2
SPI0 SDO
SPI0 SDI
P1[17]/CAP2[3]/ 42[1]
SDI0/D3
VSS(IO)
P1[16]/CAP2[2]/ 44[1]
SCK0/D2
43
ground for I/O
GPIO 1, pin 16
TIMER2 CAP2
TIMER2 MAT0
TIMER2 MAT1
SPI2 SDI
SPI0 SCK
EXTBUS D2
EXTBUS D8
EXTBUS D9
-
P2[0]/MAT2[0]/ 45[1]
TRAP3/D8
P2[1]/MAT2[1]/ 46[1]
TRAP2/D9
GPIO 2, pin 0
GPIO 2, pin 1
GPIO 3, pin 10
GPIO 3, pin 11
GPIO 1, pin 15
GPIO 1, pin 14
GPIO 1, pin 13
GPIO 1, pin 12
PWM TRAP3
PWM TRAP2
PWM1 MAT4
PWM1 MAT5
SPI0 SCS0
SPI0 SCS3
I2C1 SCL
P3[10]/SDI2/
PMAT1[4]
47[1]
P3[11]/SCK2/
PMAT1[5]
48[1]
SPI2 SCK
-
P1[15]/CAP2[1]/ 49[1]
SCS0[0]/D1
P1[14]/CAP2[0]/ 50[1]
SCS0[3]/D0
TIMER2 CAP1
TIMER2 CAP0
EXTINT3
EXTBUS D1
EXTBUS D0
EXTBUS WE
EXTBUS OE
P1[13]/SCL1/
EI3/WE
51[1]
52[1]
53
P1[12]/SDA1/
EI2/OE
EXTINT2
I2C1 SDA
VDD(IO)
3.3 V power supply for I/O
GPIO 2, pin 2
P2[2]/MAT2[2]/ 54[1]
TRAP1/D10
TIMER2 MAT2
PWM TRAP1
EXTBUS D10
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
7 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
GPIO 2, pin 3
Function 1
Function 2
Function 3
P2[3]/MAT2[3]/ 55[1]
TRAP0/D11
TIMER2 MAT3
PWM TRAP0
EXTBUS D11
P1[11]/SCK1/
SCL0/CS3
56[1]
GPIO 1, pin 11
SPI1 SCK
SPI1 SDI
I2C0 SCL
I2C0 SDA
EXTINT4
EXTBUS CS3
P1[10]/SDI1/
SDA0/CS2
P3[12]/SCS1[0]/ 58[1]
EI4
57[1]
GPIO 1, pin 10
EXTBUS CS2
-
GPIO 3, pin 12
SPI1 SCS0
VSS(CORE)
VDD(CORE)
59
ground for digital core
60
1.8 V power supply for digital core
P3[13]/SDO1/
EI5/IDX0
P2[4]/MAT1[0]/ 62[1]
EI0/D12
P2[5]/MAT1[1]/ 63[1]
EI1/D13
61[1]
GPIO 3, pin 13
GPIO 2, pin 4
GPIO 2, pin 5
GPIO 1, pin 9
SPI1 SDO
EXTINT5
QEI0 IDX
TIMER1 MAT0
TIMER1 MAT1
SPI1 SDO
EXTINT0
EXTBUS D12
EXTBUS D13
EXTBUS CS1
EXTINT1
P1[9]/SDO1/
RXDL1/CS1
64[1]
LIN1/UART RXD
VSS(IO)
P1[8]/SCS1[0]/ 66[1]
TXDL1/CS0
65
ground for I/O
GPIO 1, pin 8
SPI1 SCS0
SPI1 SCS3
SPI1 SCS2
TIMER1 MAT2
SPI1 SCS1
SPI2 SCS2
LIN1/UART TXD
UART1 RXD
UART1 TXD
EXTINT2
EXTBUS CS0
EXTBUS A7
EXTBUS A6
EXTBUS D14
EXTBUS A5
EXTBUS A4
P1[7]/SCS1[3]/ 67[1]
RXD1/A7
P1[6]/SCS1[2]/ 68[1]
TXD1/A6
P2[6]/MAT1[2]/ 69[1]
EI2/D14
P1[5]/SCS1[1]/ 70[1]
PMAT3[5]/A5
GPIO 1, pin 7
GPIO 1, pin 6
GPIO 2, pin 6
GPIO 1, pin 5
GPIO 1, pin 4
PWM3 MAT5
PWM3 MAT4
P1[4]/SCS2[2]/ 71[1]
PMAT3[4]/A4
TRST
72[1]
73[1]
74
75[2]
76[2]
77
IEEE 1149.1 test reset NOT; active LOW; pulled up internally
asynchronous device reset; active LOW; pulled up internally
ground for oscillator
RST
VSS(OSC)
XOUT_OSC
XIN_OSC
VDD(OSC)
VSS(PLL)
crystal out for oscillator
crystal in for oscillator
1.8 V supply for oscillator
78
ground for PLL
P2[7]/MAT1[3]/ 79[1]
EI3/D15
GPIO 2, pin 7
GPIO 3, pin 14
GPIO 3, pin 15
TIMER1 MAT3
SPI1 SDI
EXTINT3
EXTINT6
EXTINT7
EXTBUS D15
CAN0 TXD
CAN0 RXD
P3[14]/SDI1/
EI6/TXDC0
80[1]
P3[15]/SCK1/
EI7/RXDC0
81[1]
SPI1 SCK
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
8 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
3.3 V power supply for I/O
GPIO 2, pin 8
Function 1
Function 2
Function 3
VDD(IO)
82
83[1]
P2[8]/
CLK_OUT
PWM0 MAT0
SPI0 SCS2
CLK_OUT/
PMAT0[0]/
SCS0[2]
P2[9]/PMAT0[1]/ 84[1]
SCS0[1]
P1[3]/SCS2[1]/ 85[1]
PMAT3[3]/A3
P1[2]/SCS2[3]/ 86[1]
PMAT3[2]/A2
GPIO 2, pin 9
-
PWM0 MAT1
PWM3 MAT3
PWM3 MAT2
PWM3 MAT1
SPI0 SCS1
EXTBUS A3
EXTBUS A2
EXTBUS A1
GPIO 1, pin 3
SPI2 SCS1
SPI2 SCS3
EXTINT1
GPIO 1, pin 2
P1[1]/EI1/
87[1]
GPIO 1, pin 1
PMAT3[1]/A1
VSS(CORE)
VDD(CORE)
88
ground for digital core
89
1.8 V power supply for digital core
P1[0]/EI0/
PMAT3[0]/A0
90[1]
GPIO 1, pin 0
EXTINT0
PWM3 MAT0
PWM0 MAT2
EXTBUS A0
SPI0 SCS0
P2[10]/
91[1]
GPIO 2, pin 10
-
PMAT0[2]/
SCS0[0]
P2[11]/
PMAT0[3]/SCK0
92[1]
93[1]
GPIO 2, pin 11
GPIO 0, pin 0
-
PWM0 MAT3
CAN0 TXD
SPI0 SCK
P0[0]/PHB0/
TXDC0/D24
QEI0 PHB
EXTBUS D24
VSS(IO)
94
95[1]
ground for I/O
GPIO 0, pin 1
P0[1]/PHA0/
RXDC0/D25
QEI 0 PHA
CLK_OUT
CAN0 RXD
EXTBUS D25
EXTBUS D26
P0[2]/
96[1]
GPIO 0, pin 2
PWM0 MAT0
CLK_OUT/
PMAT0[0]/D26
P0[3]/PMAT0[1]/ 97[1]
D27
P3[0]/PMAT2[0]/ 98[1]
CS6
P3[1]/PMAT2[1]/ 99[1]
CS7
GPIO 0, pin 3
GPIO 3, pin 0
GPIO 3, pin 1
-
-
-
-
-
PWM0 MAT1
PWM2 MAT0
PWM2 MAT1
PWM0 MAT4
PWM0 MAT5
EXTBUS D27
EXTBUS CS6
EXTBUS CS7
SPI0 SDI
P2[12]/
100[1] GPIO 2, pin 12
PMAT0[4]/SDI0
P2[13]/
101[1] GPIO 2, pin 13
SPI0 SDO
PMAT0[5]/
SDO0
P0[4]/PMAT0[2]/ 102[1] GPIO 0, pin 4
D28
P0[5]/PMAT0[3]/ 103[1] GPIO 0, pin 5
D29
-
-
PWM0 MAT2
PWM0 MAT3
EXTBUS D28
EXTBUS D29
VDD(IO)
104
3.3 V power supply for I/O
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
9 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
Function 1
Function 2
Function 3
P0[6]/
105[1] GPIO 0, pin 6
-
PWM0 MAT4
EXTBUS D30
PMAT0[4]/D30
P0[7]/
106[1] GPIO 0, pin 7
-
PWM0 MAT5
EXTBUS D31
PMAT0[5]/D31
VDDA(ADC3V3)
JTAGSEL
107
3.3 V power supply for ADC
108[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan; pulled up internally.
n.c.
109
not connected to a function, must be tied to 3.3 V power supply for ADC VDDA(ADC3V3)
.
VREFP
VREFN
110[2] HIGH reference for ADC
111[2] LOW reference for ADC
P0[8]/IN1[0]/TX 112[3] GPIO 0, pin 8
DL0/A20
ADC1 IN0
ADC1 IN1
ADC1 IN2
ADC1 IN3
I2C1 SDA
I2C1 SCL
TIMER3 MAT0
LIN0/UART TXD
LIN0/UART RXD
PWM1 MAT0
PWM1 MAT1
PWM0 CAP0
PWM0 CAP1
PWM2 MAT2
EXTBUS A20
EXTBUS A21
EXTBUS A8
EXTBUS A9
EXTBUS BLS0
EXTBUS BLS1
-
P0[9]/IN1[1]/
RXDL0/A21
113[3] GPIO 0, pin 9
114[3] GPIO 0, pin 10
115[3] GPIO 0, pin 11
116[1] GPIO 2, pin 14
117[1] GPIO 2, pin 15
P0[10]/IN1[2]/
PMAT1[0]/A8
P0[11]/IN1[3]/
PMAT1[1]/A9
P2[14]/SDA1/
PCAP0[0]/BLS0
P2[15]/SCL1/
PCAP0[1]/BLS1
P3[2]/MAT3[0]/ 118[1] GPIO 3, pin 2
PMAT2[2]
VSS(IO)
119
ground for I/O
P3[3]/MAT3[1]/ 120[1] GPIO 3, pin 3
PMAT2[3]
TIMER3 MAT1
ADC1 IN4
ADC1 IN5
ADC1 IN6
ADC1 IN7
ADC2 IN0
ADC2 IN1
PWM2 MAT3
PWM1 MAT2
PWM1 MAT3
PWM1 MAT4
PWM1 MAT5
UART0 TXD
UART0 RXD
-
P0[12]/IN1[4]/
PMAT1[2]/A10
121[3] GPIO 0, pin 12
122[3] GPIO 0, pin 13
123[3] GPIO 0, pin 14
124[3] GPIO 0, pin 15
125[3] GPIO 0, pin 16
126[3] GPIO 0, pin 17
EXTBUS A10
EXTBUS A11
EXTBUS A12
EXTBUS A13
EXTBUS A22
EXTBUS A23
P0[13]/IN1[5]/
PMAT1[3]/A11
P0[14]/IN1[6]/
PMAT1[4]/A12
P0[15]/IN1[7]/
PMAT1[5]/A13
P0[16]IN2[0]/
TXD0/A22
P0[17]/IN2[1]/
RXD0/A23
VDD(CORE)
VSS(CORE)
127
128
1.8 V power supply for digital core
ground for digital core
P2[16]/TXD1/
PCAP0[2]/BLS2
129[1] GPIO 2, pin 16
UART1 TXD
PWM0 CAP2
PWM1 CAP0
EXTBUS BLS2
EXTBUS BLS3
P2[17]/RXD1/
130[1] GPIO 2, pin 17
UART1 RXD
PCAP1[0]/BLS3
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
10 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 3.
LQFP144 pin assignment …continued
Pin name
Pin
Description
Default function
Function 1
Function 2
Function 3
VDD(IO)
131
3.3 V power supply for I/O
P0[18]/IN2[2]/
PMAT2[0]/A14
132[3] GPIO 0, pin 18
ADC2 IN2
PWM2 MAT0
PWM2 MAT1
PWM2 MAT4
EXTBUS A14
EXTBUS A15
CAN1 TXD
P0[19]/IN2[3]/
PMAT2[1]/A15
P3[4]/MAT3[2]/ 134[1] GPIO 3, pin 4
133[3] GPIO 0, pin 19
ADC2 IN3
TIMER3 MAT2
PMAT2[4]/
TXDC1
P3[5]/MAT3[3]/ 135[1] GPIO 3, pin 5
TIMER3 MAT3
PWM2 MAT5
CAN1 RXD
PMAT2[5]/
RXDC1
P2[18]/SCS2[1]/ 136[1] GPIO 2, pin 18
PCAP1[1]/D16
P2[19]/SCS2[0]/ 137[1] GPIO 2, pin 19
PCAP1[2]/D17
SPI2 SCS1
SPI2 SCS0
ADC2 IN4
ADC2 IN5
ADC2 IN6
PWM1 CAP1
PWM1 CAP2
PWM2 MAT2
PWM2 MAT3
PWM2 MAT4
EXTBUS D16
EXTBUS D17
EXTBUS A16
EXTBUS A17
EXTBUS A18
P0[20]/IN2[4]/
PMAT2[2]/A16
138[3] GPIO 0, pin 20
139[3] GPIO 0, pin 21
140[3] GPIO 0, pin 22
P0[21]/IN2[5]/
PMAT2[3]/A17
P0[22]/IN2[6]/
PMAT2[4]/A18
VSS(IO)
141
ground for I/O
P0[23]/IN2[7]/
PMAT2[5]/A19
142[3] GPIO 0, pin 23
ADC2 IN7
SPI2 SDO
PWM2 MAT5
PWM2 CAP0
EXTBUS A19
EXTBUS D18
P2[20]/
143[1] GPIO 2, pin 20
PCAP2[0]/D18
TDI
144[1] IEEE 1149.1 data in, pulled up internally
[1] Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5V tolerant; TTL with hysteresis; programmable pull-up /
pull-down / repeater.
[2] Analog pad; analog I/O
[3] Analog pad.
6. Functional description
6.1 Architectural overview
The LPC2917/2919/01 consists of:
• An ARM968E-S processor with real-time emulation support
• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
• Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
11 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
• One ARM Peripheral Bus for event router and system control.
The LPC2917/2919/01 configures the ARM968E-S processor in little-endian byte order.
All peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the APB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
6.2 ARM968E-S processor
The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective controller
core.
Amongst the most compelling features of the ARM968E-S are:
• Separate directly connected instruction and data Tightly Coupled Memory (TCM)
interfaces
• Write buffers for the AHB and TCM buses
• Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed-
point DSP instructions to accelerate signal-processing algorithms and applications.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline
architecture. Typically, in a three-stage pipeline architecture, while one instruction is being
executed its successor is being decoded and a third instruction is being fetched from
memory. In the five-stage pipeline additional stages are added for memory access and
write-back cycles.
The ARM968E-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions or to applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM968E-S processor has two instruction sets:
• Standard 32-bit ARMv5TE set
• 16-bit THUMB set
The THUMB set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
12 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.
The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2.
6.3 On-chip flash memory system
The LPC2917/2919/01 includes a 512 kB or 768 kB flash memory system. This memory
can be used for both code and data storage. Programming of the flash memory can be
accomplished via the flash memory controller or JTAG.
The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated
on the LPC2917/2919/01.
6.4 On-chip static RAM
In addition to the two 16 kB TCMs the LPC2917/2919/01 includes two static RAM
memories: one of 32 kB and one of 16 kB. Both may be used for code and/or data
storage.
In addition, 8 kB SRAM for the ETB can be used as static memory for code and data
storage. However, DMA access to this memory region is not supported.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
13 of 86
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
LPC2917/2919/01
4 GB
0xFFFF FFFF
0xFFFF 8000
0xE00A 0000
PCR/VIC control
0xFFFF FFFF
0xFFFF F000
reserved
LIN1
VIC
reserved
CGU1
PMU
0xE008 B000
0xE008 A000
0xE008 9000
reserved
0xF080 0000
0xF000 0000
PCR/VIC
subsystem
0xFFFF C000
0xFFFF B000
DMA interface to TCM
reserved
LIN0
peripherals #4
networking
subsystem
CAN common regs
CAN AF regs
CAN ID LUT
reserved
I2C1
0xE018 3000
0xE018 2000
0xE018 0000
0xE014 0000
0xE008 8000
0xE008 7000
0xFFFF A000
ETB control
8 kB ETB SRAM
DMA controller
RGU
0xFFFF 9000
0xFFFF 8000
CGU0
0xE008 6000
0xE008 4000
0xE008 3000
0xE008 2000
reserved
reserved
0xE00E 0000
0xE00C A000
0xE00C 9000
0xE00C 8000
0xE010 0000
reserved
I2C0
0xE00E 0000
quadrature encoder
CAN1
peripheral subsystem #6
reserved
0xE008 1000
0xE008 0000
PWM3
PWM2
0xE00C 0000
0xE00A 0000
0xE008 0000
CAN0
0xE00C 7000
0xE00C 6000
0xE00C 5000
peripherals #6
MSCSS
subsystem
PWM1
0xE006 0000
0xE004 E000
0xE004 D000
0xE004 C000
peripheral subsystem #4
reserved
GPIO3
PWM0
reserved
ADC2
0xE006 0000
0xE004 0000
0xE00C 4000
0xE00C 3000
peripheral subsystem #2
GPIO2
GPIO1
GPIO0
ADC1
reserved
peripheral subsystem #0
reserved
reserved
MSCSS timer1
MSCSS timer0
0xE004 B000
0xE00C 2000
0xE002 0000
0xE000 0000
0xE004 A000
0xE004 9000
0xE004 8000
0xE00C 1000
0xE00C 0000
SPI2
SPI1
peripherals #2
peripheral
0x8000 C000
remappable to
shadow area
16 kB AHB SRAM
32 kB AHB SRAM
reserved
subsystem
0x8000 8000
0x8000 0000
SPI0
0xE004 7000
0xE004 6000
0x2020 4000
0x2020 0000
UART1
UART0
TIMER3
TIMER2
TIMER1
TIMER0
WDT
flash controller
reserved
2 GB
flash
memory
0xE004 5000
0xE004 4000
0xE004 3000
0xE004 2000
0x6000 4000
0x6000 0000
SMA controller
0x200C 0000
0x2008 0000
0x2000 0000
768 kB on-chip flash
512 kB on-chip flash
external static memory banks 7 to 2
0x4300 0000
0x4200 0000
0x4100 0000
16 MB external static memory bank 1
reserved
0xE004 1000
0xE004 0000
0x2000 0000
no physical
memory
16 MB external static memory bank 0
0x0080 0000
1 GB
0x4000 0000
0x2020 4000
0xE002 0000
ITCM/DTCM
memory
reserved
reserved
peripherals #0
general
reserved
event router
SCU
0x0040 4000
0x0040 0000
0xE000 2000
0xE000 2000
16 kB DTCM
subsystem
on-chip flash
0xE000 1000
0xE000 0000
reserved
0x2000 0000
0x0000 0000
CFID
0x0000 4000
0x0000 0000
512 MB shadow area
ITCM/DTCM
16 kB ITCM
002aad963
0 GB
Fig 3. LPC2917/2919/01 memory map
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.6 Reset, debug, test, and power description
6.6.1 Reset and power-up behavior
The LPC2917/2919/01 contains external reset input and internal power-up reset circuits.
This ensures that a reset is extended internally until the oscillators and flash have reached
a stable state. See Section 8 for trip levels of the internal power-up reset circuit1. See
Section 9 for characteristics of the several start-up and initialization times. Table 4 shows
the reset pin.
Table 4.
Symbol
RST
Reset pin
Direction
IN
Description
external reset input, active LOW; pulled up internally
At activation of the RST pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/2919/01 is assumed to be connected to debug hardware, and internal
circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead
of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
6.6.2 Reset strategy
The LPC2917/2919/01 contains a central module, the Reset Generator Unit (RGU) in the
Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals
towards the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2917/2919/01 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
pins can be used to connect a debugger probe for the embedded ARM processor. Pin
JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the
boundary- scan test pins.
Table 5.
Symbol
JTAGSEL
IEEE 1149.1 boundary-scan test and debug interface
Description
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan and flash programming; pulled up internally
TRST
TMS
TDI
test reset input; pulled up internally (active LOW)
test mode select input; pulled up internally
test data input, pulled up internally
test data output
TDO
TCK
test clock input
1. Only for 1.8 V power sources
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
15 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.6.3.1 ETM/ETB
The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace buffer. A software debugger
allows configuration of the ETM using a JTAG interface and displays the trace information
that has been captured in a format that a user can easily understand. The ETB stores
trace data produced by the ETM.
The ETM/ETB module has the following features:
• Closely tracks the instructions that the ARM core is executing.
• On-chip trace data storage (ETB).
• All registers are programmed through JTAG interface.
• Does not consume power when trace is not being used.
• THUMB/Java instruction set support.
6.6.4 Power supply pins
Table 6 shows the power supply pins.
Table 6.
Symbol
VDD(CORE)
VSS(CORE)
VDD(IO)
Power supply pins
Description
digital core supply 1.8 V
digital core ground (digital core, ADC1/2)
I/O pins supply 3.3 V
I/O pins ground
VSS(IO)
VDD(OSC)
VSS(OSC)
VDDA(ADC3V3)
VSS(PLL)
oscillator and PLL supply
oscillator ground
ADC1 and ADC2 3.3 V supply
PLL ground
6.7 Clocking strategy
6.7.1 Clock architecture
The LPC2917/2919/01 contains several different internal clock areas. Peripherals like
Timers, SPI, UART, CAN and LIN have their own individual clock sources called base
clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be
unrelated in frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Bus infrastructure has its own base clock. This
means most peripherals are clocked independently from the system clock. See Figure 4
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See Section 6.15 for
more details of clock and power control within the device.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
16 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Two of the base clocks generated by the CGU0 are used as input into a second, dedicated
CGU (CGU1). The CGU1 uses its own PLL and fractional divider to generate the base
clock for an independent clock output.
BA SE_ICLK0_CLK
BASE_SYS_CLK
BASE_OUT_CLK
CLOCK
OUT
BASE_ICLK1_CLK
branch
clock
CPU
AHB MULTILAYER MATRIX
AHB TO APB BRIDGES
VIC
CGU1
BASE_IVNSS_CLK
networking subsystem
CAN0/1
GPDMA
branch
clocks
FLASH/SRAM/SMC
GLOBAL
ACCEPTANCE
FILTER
branch
clocks
general subsytem
LIN0/1
I2C0/1
SYSTEM CONTROL
EVENT ROUTER
CFID
BASE_PCR_CLK
peripheral subsystem
GPIO0/1/2/3
power control subsystem
branch
clock
RESET/CLOCK
GENERATION AND
POWER
MANAGEMENT
BASE_TMR_CLK
BASE_SPI_CLK
BASE_MSCSS_CLK
TIMER 0/1/2/3
SPI0/1/2
UART0/1
WDT
modulation and sampling
control subsystem
T_CLK
BASE_UAR
TIMER0/1 MTMR
PWM0/1/2/3
QEI
BASE_SAFE_CLK
branch
clocks
BASE_ADC_CLK
ADC1/2
branch
clocks
CGU0
002aad962
Fig 4. LPC2917/2919/01 block diagram, overview of clock areas
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
17 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.7.2 Base clock and branch clock relationship
Table 7 and Table 8 contain an overview of all the base blocks in the LPC2917/2919/01
and their derived branch clocks. In relevant cases more detailed information can be found
in the specific subsystem description. Some branch clocks have special protection since
they clock vital system parts of the device and should (for example) not be switched off.
See Section 6.15.5 for more details of how to control the individual branch clocks.
Table 7.
CGU0 generated base clock and branch clock overview
Base clock
Branch clock name
Parts of the device clocked
Remark
by this branch clock
[1]
BASE_SAFE_CLK
BASE_SYS_CLK
CLK_SAFE
watchdog timer
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
ARM968E-S and TCMs
AHB bus infrastructure
AHB side of bridge in PCRSS
Flash-Memory Controller
Embedded SRAM Controller 0
(32 kB)
CLK_SYS_RAM1
CLK_SYS_SMC
Embedded SRAM Controller 1
(16 kB)
External Static-Memory
Controller
CLK_SYS_GESS
CLK_SYS_VIC
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
[2] [4]
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
GPIO bank 1
GPIO bank 2
GPIO bank 3
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
GPDMA
[1] [3]
BASE_PCR_CLK
CLK_PCR_SLOW
PCRSS, CGU, RGU and PMU
logic clock
,
BASE_IVNSS_CLK
CLK_IVNSS_APB
APB side of the IVNSS
CLK_IVNSS_CANCA
CAN controller Acceptance
Filter
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
CAN channel 0
CAN channel 1
I2C0
I2C1
LIN channel 0
LIN channel 1
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
18 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 7.
CGU0 generated base clock and branch clock overview …continued
Base clock
Branch clock name
Parts of the device clocked
by this branch clock
Remark
BASE_MSCSS_CLK
CLK_MSCSS_APB
APB side of the MSCSS
Timer 0 in the MSCSS
Timer 1 in the MSCSS
PWM 0
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
PWM 1
PWM 2
PWM 3
CLK_MSCSS_ADC1_APB APB side of ADC 1
CLK_MSCSS_ADC2_APB APB side of ADC 2
CLK_MSCSS_QEI
CLK_UART0
CLK_UART1
-
Quadrature encoder
BASE_UART_CLK
UART 0 interface clock
UART 1 interface clock
CGU1 input clock
BASE_ICLK0_CLK
BASE_SPI_CLK
CLK_SPI0
CLK_SPI1
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
SPI 0 interface clock
SPI 1 interface clock
SPI 2 interface clock
BASE_TMR_CLK
BASE_ADC_CLK
Timer 0 clock for counter part
Timer 1 clock for counter part
Timer 2 clock for counter part
Timer 3 clock for counter part
Control of ADC 1, capture
sample result
CLK_ADC2
Control of ADC 2, capture
sample result
reserved
-
-
-
BASE_ICLK1_CLK
CGU1 input clock
[1] This clock is always on (cannot be switched off for system safety reasons)
[2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock
source. See Section 6.12 for details.
[3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock
source. See Section 6.15 for details.
[4] The clock should remain activated when system wake-up on timer or UART is required.
Table 8.
CGU1 base clock and branch clock overview
Base clock
Branch clock name
Parts of the device clocked by this
branch clock
BASE_OUT_CLK
CLK_OUT_CLK
clockout pin
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
19 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.8 Flash memory controller
The flash memory has a 128-bit wide data interface and the flash controller offers two
128-bit buffer lines to improve system performance. The flash has to be programmed
initially via JTAG. In-system programming must be supported by the bootloader.
In-application programming is possible. Flash memory contents can be protected by
disabling JTAG access. Suspension of burning or erasing is not supported.
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two
tasks:
• Memory data transfer
• Memory configuration via triggering, programming, and erasing
The key features are:
• Programming by CPU via AHB
• Programming by external programmer via JTAG
• JTAG access protection
• Burn-finished and erase-finished interrupt
6.8.1 Functional description
After reset, flash initialization is started, which takes tinit time (see Section 9). During this
initialization, flash access is not possible and AHB transfers to flash are stalled, blocking
the AHB bus.
During flash initialization, the index sector is read to identify the status of the JTAG access
protection and sector security. If JTAG access protection is active, the flash is not
accessible via JTAG. In this case, ARM debug facilities are disabled and flash-memory
contents cannot be read. If sector security is active, only the unsecured sections can be
read.
Flash can be read synchronously or asynchronously to the system clock. In synchronous
operation, the flash goes into standby after returning the read data. Started reads cannot
be stopped, and speculative reading and dual buffering are therefore not supported.
With asynchronous reading, transfer of the address to the flash and of read data from the
flash is done asynchronously, giving the fastest possible response time. Started reads can
be stopped, so speculative reading and dual buffering are supported.
Buffering is offered because the flash has a 128-bit wide data interface while the AHB
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash
word, from which four words can be read. Without buffering every AHB data port read
starts a flash read. A flash read is a slow process compared to the minimum AHB cycle
time, so with buffering the average read time is reduced. This can improve system
performance.
With single buffering, the most recently read flash word remains available until the next
flash read. When an AHB data-port read transfer requires data from the same flash word
as the previous read transfer, no new flash read is done and the read data is given without
wait cycles.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
20 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
When an AHB data port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
With dual buffering, a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer, hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
Both buffer lines are invalidated after:
• Initialization
• Configuration-register access
• Data-latch reading
• Index-sector reading
The modes of operation are listed in Table 9.
Table 9.
Flash read modes
Synchronous timing
No buffer line
for single (non-linear) reads; one flash-word read per word read
Single buffer line
default mode of operation; most recently read flash word is kept until
another flash word is required
Asynchronous timing
No buffer line
one flash-word read per word read
Single buffer line
most recently read flash word is kept until another flash word is
required
Dual buffer line, single
speculative
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
Dual buffer line, always
speculative
most recently used flash word is copied into second buffer line; next
flash-word read is started; highest performance for linear reads
6.8.2 Pin description
The flash memory controller has no external pins. However, the flash can be programmed
via the JTAG pins, see Section 6.6.3.
6.8.3 Clock description
The flash memory controller is clocked by CLK_SYS_FMC, see Section 6.7.2.
6.8.4 Flash layout
The ARM processor can program the flash for ISP (In-System Programming) and IAP (In-
Application Programming). Note that the flash always has to be programmed by ‘flash
words’ of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
21 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 10 gives an overview of the flash-sector base addresses.
Table 10. Flash sector overview
Sector number
Sector size (kB)
Sector base address
0x2000 0000
0x2000 2000
0x2000 4000
0x2000 6000
0x2000 8000
0x2000 A000
0x2000 C000
0x2000 E000
0x2001 0000
0x2002 0000
0x2003 0000
0x2004 0000
0x2005 0000
0x2006 0000
0x2007 0000
0x2008 0000
0x2009 0000
0x200A 0000
0x200B 0000
11
12
13
14
15
16
17
18
0
8
8
8
8
8
8
8
8
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7[1]
8[1]
9[1]
10[1]
[1] Availability of sector 15 to sector 18 depends on device type, see Section 3 “Ordering information”.
The index sector is a special sector in which the JTAG access protection and sector
security are located. The address space becomes visible by setting the FS_ISS bit and
overlaps the regular flash sector’s address space.
Note that the index sector cannot be erased, and that access to it has to be performed via
code outside the flash.
6.8.5 Flash bridge wait-states
To eliminate the delay associated with synchronizing flash-read data, a predefined
number of wait-states must be programmed. These depend on flash-memory response
time and system clock period. The minimum wait-states value can be calculated with the
following formulas:
Synchronous reading:
t
WST > acc(clk) – 1
(1)
(2)
------------------
tt
tclk(sys)
Asynchronous reading:
t
WST > acc(addr) – 1
---------------------
ttclk(sys)
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
22 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Remark: If the programmed number of wait-states is more than three, flash-data reading
cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative
reading is active.
6.8.6 EEPROM
EEPROM is a non-volatile memory mostly used for storing relatively small amounts of
data, for example for storing settings. It contains one 16 kB memory block and is
byte-programmable and byte-erasable.
The EEPROM can be accessed only through the flash controller.
6.9 External static memory controller
The LPC2917/2919/01 contains an external Static Memory Controller (SMC) which
provides an interface for external (off-chip) memory devices.
Key features are:
• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices.
• Asynchronous page-mode read operation in non-clocked memory subsystems.
• Asynchronous burst-mode read access to burst-mode ROM devices.
• Independent configuration for up to eight banks, each up to 16 MB.
• Programmable bus-turnaround (idle) cycles (one to 16).
• Programmable read and write wait states (up to 32), for static RAM devices.
• Programmable initial and subsequent burst-read wait state for burst-ROM devices.
• Programmable write protection.
• Programmable burst-mode operation.
• Programmable external data width: 8 bits, 16 bits or 32 bits.
• Programmable read-byte lane enable control.
6.9.1 Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing. Table 11 shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects, and bank internal addresses.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
23 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 11. External memory-bank address bit description
32-bit
Symbol
Description
system
address bit
field
31 to 29
BA[2:0]
external static-memory base address (three most significant bits);
the base address can be found in the memory map; see Ref. 1. This
field contains ‘010’ when addressing an external memory bank.
28 to 26
25 and 24
23 to 0
CS[2:0]
-
chip select address space for eight memory banks; see Ref. 1.
always ‘00’; other values are ‘mirrors’ of the 16 MB bank address.
16 MB memory banks address space
A[23:0]
Table 12. External static-memory controller banks
CS[2:0]
000
Bank
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
001
010
011
100
101
110
111
6.9.2 Pin description
The external static-memory controller module in the LPC2917/2919/01 has the following
pins, which are combined with other functions on the port pins of the LPC2917/2919/01.
Table 13 shows the external memory controller pins.
Table 13. External memory controller pins
Symbol
Direction
OUT
Description
EXTBUS CSx
EXTBUS BLSy
EXTBUS WE
EXTBUS OE
memory-bank x select, x runs from 0 to 7
byte-lane select input y, y runs from 0 to 3
write enable (active LOW)
output enable (active LOW)
address bus
OUT
OUT
OUT
EXTBUS A[23:0] OUT
EXTBUS D[31:0] IN/OUT
data bus
6.9.3 Clock description
The External Static-Memory Controller is clocked by CLK_SYS_SMC, see Section 6.7.2.
6.9.4 External memory timing diagrams
A timing diagram for reading from external memory is shown in Figure 5. The relationship
between the wait-state settings is indicated with arrows.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
24 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
CLK(SYS)
CS
OE
A
D
WST1
WSTOEN
002aae704
WSTOEN = 3, WST1 = 6
Fig 5. Reading from external memory
A timing diagram for writing to external memory is shown In Figure 6. The relationship
between wait-state settings is indicated with arrows.
CLK(SYS)
CS
(1)
WE/BLS
BLS
A
D
WST2
WSTWEN
002aae705
WSTWEN = 3, WST2 = 7
(1) BLS has the same timing as WE in configurations that use the byte lane enable signals to connect
to write enable (8 bit devices).
Fig 6. Writing to external memory
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
25 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Usage of the idle/turn-around time (IDCY) is demonstrated In Figure 7. Extra wait states
are added between a read and a write cycle in the same external memory device.
CLK(SYS)
CS
WE
OE
A
D
WST1
WST2
WSTWEN
IDCY
WSTOEN
002aae706
WSTOEN = 2, WSTWEN = 4, WST1 = 6, WST2 = 4, IDCY = 5
Fig 7. Reading/writing external memory
Address pins on the device are shared with other functions. When connecting external
memories, check that the I/O pin is programmed for the correct function. Control of these
settings is handled by the SCU.
6.10 DMA controller
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master or one area by each master.
The DMA controls eight DMA channels with hardware prioritization. The DMA controller
interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width.
DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either
big-endian or little-endian. Incrementing or non-incrementing addressing for source and
destination are supported, as well as programmable DMA burst size. Scatter or gather
DMA is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas of memory.
6.10.1 DMA support for peripherals
The GPDMA supports the following peripherals: SPI0/1/2 and UART0/1. The GPDMA can
access both embedded SRAM blocks (16 kB and 32 kB), both TCMs, external static
memory, and flash memory.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
26 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.10.2 Clock description
The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see
Section 6.7.2.
6.11 General subsystem
6.11.1 General subsystem clock description
The general subsystem is clocked by CLK_SYS_GESS, see Section 6.7.2.
6.11.2 Chip and feature identification
The Chip/Feature ID (CFID) module contains registers which show and control the
functionality of the chip. It contains an ID to identify the silicon and also registers
containing information about the features enabled or disabled on the chip.
The key features are:
• Identification of product
• Identification of features enabled
The CFID has no external pins.
6.11.3 System Control Unit (SCU)
The system control unit contains system-related functions.The key feature is configuration
of the I/O port-pins multiplexer. It defines the function of each I/O pin of the
LPC2917/2919/01. The I/O pin configuration should be consistent with peripheral function
usage.
The SCU has no external pins.
6.11.4 Event router
The event router provides bus-controlled routing of input events to the vectored interrupt
controller for use as interrupt or wake-up signals.
Key features:
• Up to 19 level-sensitive external interrupt pins, including the receive pins of SPI, CAN,
LIN, and UART, as well as the I2C-bus SCL pins plus three internal event sources.
• Input events can be used as interrupt source either directly or latched
(edge-detected).
• Direct events disappear when the event becomes inactive.
• Latched events remain active until they are explicitly cleared.
• Programmable input level and edge polarity.
• Event detection maskable.
• Event detection is fully asynchronous, so no clock is required.
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
27 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
The vectored interrupt-controller inputs are active HIGH.
6.11.4.1 Pin description
The event router module in the LPC2917/2919/01 is connected to the pins listed below.
The pins are combined with other functions on the port pins of the LPC2917/2919/01.
Table 14 shows the pins connected to the event router, and also the corresponding bit
position in the event-router registers and the default polarity.
Table 14. Event-router pin connections
Symbol
EXTINT 7 - 0
CAN0 RXD
CAN1 RXD
I2C0_SCL
I2C1_SCL
LIN0 RXD
LIN1 RXD
SPI0 SDI
SPI1 SDI
SPI2 SDI
UART0 RXD
UART1 RXD
-
Direction
Description
Default polarity
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
na
na
na
external interrupt input 7 - 0
CAN0 receive data input wake-up
CAN1 receive data input wake-up
I2C0 SCL clock input
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
I2C1 SCL clock input
LIN0 receive data input wake-up
LIN1 receive data input wake-up
SPI0 receive data input
SPI1 receive data input
SPI2 receive data input
UART0 receive data input
UART1 receive data input
CAN interrupt (internal)
VIC FIQ (internal)
-
-
VIC IRQ (internal)
6.12 Peripheral subsystem
6.12.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
• CLK_SAFE see Section 6.7.2
6.12.2 Watchdog timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
• Internal chip reset if not periodically triggered
• Timer counter register runs on always-on safe clock
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
28 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Optional interrupt generation on watchdog time-out
• Debug mode with disabling of reset
• Watchdog control register change-protected with key
• Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
6.12.2.1 Functional description
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out, it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
reset. See Section 6.15.4.
6.12.2.2 Clock description
The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see Section 6.7.2. The register interface towards the system bus is clocked by
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
6.12.3 Timer
The LPC2917/2919/01 contains six identical timers: four in the peripheral subsystem and
two in the Modulation and Sampling Control SubSystem (MSCSS) located at different
peripheral base addresses. This section describes the four timers in the peripheral
subsystem. Each timer has four capture inputs and/or match outputs. Connection to
device pins depends on the configuration programmed into the port function-select
registers. The two timers located in the MSCSS have no external capture or match pins,
but the memory map is identical, see Section 6.14.6. One of these timers has an external
input for a pause function.
The key features are:
• 32-bit timer/counter with programmable 32-bit prescaler
• Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt
• Four 32-bit match registers per timer that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
29 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
• Pause input pin (MSCSS timers only)
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
prescale counter triggering the 32 bit timer counter. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See section Section 6.15.5 for information on generation of these
clocks.
6.12.3.1 Pin description
The four timers in the peripheral subsystem of the LPC2917/2919/01 have the pins
described below. The two timers in the modulation and sampling subsystem have no
external pins except for the pause pin on MSCSS timer 1. See Section 6.14.6 for a
description of these timers and their associated pins. The timer pins are combined with
other functions on the port pins of the LPC2917/2919/01, see Section 6.11.3. Table
Table 15 shows the timer pins (x runs from 0 to 3).
Table 15. Timer pins
Symbol
Pin name
Direction
IN
Description
TIMERx CAP[0] CAPx[0]
TIMERx CAP[1] CAPx[1]
TIMERx CAP[2] CAPx[2]
TIMERx CAP[3] CAPx[3]
TIMERx MAT[0] MATx[0]
TIMERx MAT[1] MATx[1]
TIMERx MAT[2] MATx[2]
TIMERx MAT[3] MATx[3]
TIMER x capture input 0
TIMER x capture input 1
TIMER x capture input 2
TIMER x capture input 3
TIMER x match output 0
TIMER x match output 1
TIMER x match output 2
TIMER x match output 3
IN
IN
IN
OUT
OUT
OUT
OUT
6.12.3.2 Clock description
The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx
(x = 0-3), see Section 6.7.2. Note that each timer has its own CLK_TMRx branch clock for
power management. The frequency of all these clocks is identical as they are derived from
the same base clock BASE_CLK_TMR. The register interface towards the system bus is
clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by
CLK_TMRx.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
30 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
6.12.4 UARTs
ARM9 microcontroller with CAN and LIN
The LPC2917/2919/01 contains two identical UARTs located at different peripheral base
addresses. The key features are:
• 16-byte receive and transmit FIFOs.
• Register locations conform to 550 industry standard.
• Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes.
• Built-in baud rate generator.
• Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART is commonly used to implement a serial interface such as RS232. The
LPC2917/2919/01 contains two industry-standard 550 UARTs with 16-byte transmit and
receive FIFOs, but they can also be put into 450 mode without FIFOs.
6.12.4.1 Pin description
The UART pins are combined with other functions on the port pins of the
LPC2917/2919/01. Table 16 shows the UART pins (x runs from 0 to 1).
Table 16. UART pins
Symbol
Pin name
Direction
OUT
Description
UARTx TXD TXDx
UARTx RXD RXDx
UART channel x transmit data output
UART channel x receive data input
IN
6.12.4.2 Clock description
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0-1), see Section 6.7.2. Note that each UART has its own CLK_UARTx
branch clock for power management. The frequency of all CLK_UARTx clocks is identical
since they are derived from the same base clock BASE_CLK_UART. The register
interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is
clocked by the CLK_UARTx.
6.12.5 Serial peripheral interface (SPI)
The LPC2917/2919/01 contains three Serial Peripheral Interface modules (SPIs) to allow
synchronous serial communication with slave or master peripherals.
The key features are:
• Master or slave operation
• Each SPI supports up to four slaves in sequential multi-slave operation
• Supports timer-triggered operation
• Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock
• Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep
• Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces
• Programmable data-frame size from 4 to 16 bits
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
31 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
• Serial clock-rate master mode: fserial_clk ≤ fclk(SPI)/2
• Serial clock-rate slave mode: fserial_clk = fclk(SPI)/4
• Internal loopback test mode
The SPI module can operate in:
• Master mode:
– Normal transmission mode
– Sequential slave mode
• Slave mode
6.12.5.1 Functional description
The SPI module is a master or slave interface for synchronous serial communication with
peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial
Interfaces.
The SPI module performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories (16 bits wide ×
32 words deep). Serial data is transmitted on pins SDOx and received on pins SDIx.
The SPI module includes a programmable bit-rate clock divider and prescaler to generate
the SPI serial clock from the input clock CLK_SPIx.
The SPI module’s operating mode, frame format, and word size are programmed through
the SLVn_SETTINGS registers.
A single combined interrupt request SPI_INTREQ output is asserted if any of the
interrupts are asserted and unmasked.
Depending on the operating mode selected, the SPI SCS outputs operate as an
active-HIGH frame synchronization output for Texas Instruments synchronous serial
frame format or an active LOW chip select for SPI.
Each data frame is between four and 16 bits long, depending on the size of words
programmed, and is transmitted starting with the MSB.
6.12.5.2 Pin description
The SPI pins are combined with other functions on the port pins of the LPC2917/2919/01,
see Section 6.11.3. Table 17 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3).
Table 17. SPI pins
Symbol
Pin name
SCSx[y]
SCKx
Direction
IN/OUT
IN/OUT
IN
Description
SPIx SCSy
SPIx SCK
SPIx SDI
SPIx SDO
SPIx chip select[1][2]
SPIx clock[1]
SDIx
SPIx data input
SPIx data output
SDOx
OUT
[1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in
master mode, input in slave mode.
[2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in
slave mode.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
32 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.12.5.3 Clock description
The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx
(x = 0, 1, 2), see Section 6.7.2. Note that each SPI has its own CLK_SPIx branch clock for
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
6.12.6 General-purpose I/O
The LPC2917/2919/01 contains four general-purpose I/O ports located at different
peripheral base addresses. All I/O pins are bidirectional, and the direction can be
programmed individually. The I/O pad behavior depends on the configuration programmed
in the port function-select registers.
The key features are:
• General-purpose parallel inputs and outputs
• Direction control of individual bits
• Synchronized input sampling for stable input-data values
• All I/O defaults to input at reset to avoid any possible bus conflicts
6.12.6.1 Functional description
The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output: when set to input the signal floats and can be
pulled up internally or externally.
6.12.6.2 Pin description
The five GPIO ports in the LPC2917/2919/01 have the pins listed below. The GPIO pins
are combined with other functions on the port pins of the LPC2917/2919/01. Table 18
shows the GPIO pins.
Table 18. GPIO pins
Symbol
Pin name
Direction
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Description
GPIO0 pin[31:0] P0[31:0]
GPIO1 pin[31:0] P1[31:0]
GPIO2 pin[27:0] P2[27:0]
GPIO3 pin[15:0] P3[15:0]
GPIO port x pins 31 to 0
GPIO port x pins 31 to 0
GPIO port x pins 27 to 0
GPIO port x pins 15 to 0
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
33 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.12.6.3 Clock description
The GPIO modules are clocked by several clocks, all of which are derived from
BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0, 1, 2, 3), see
Section 6.7.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for
power management. The frequency of all clocks CLK_SYS_GPIOx is identical to
CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.
6.13 Networking subsystem
6.13.1 CAN gateway
Controller Area Network (CAN) is the definition of a high-performance communication
protocol for serial data communication. The two CAN controllers in the LPC2917/2919/01
provide a full implementation of the CAN protocol according to the CAN specification
version 2.0B. The gateway concept is fully scalable with the number of CAN controllers,
and always operates together with a separate powerful and flexible hardware acceptance
filter.
The key features are:
• Supports 11-bit as well as 29-bit identifiers
• Double receive buffer and triple transmit buffer
• Programmable error-warning limit and error counters with read/write access
• Arbitration-lost capture and error-code capture with detailed bit position
• Single-shot transmission (i.e. no re-transmission)
• Listen-only mode (no acknowledge; no active error flags)
• Reception of ‘own’ messages (self-reception request)
• FullCAN mode for message reception
6.13.1.1 Global acceptance filter
The global acceptance filter provides look-up of received identifiers - called acceptance
filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table
memory, in which software maintains one to five sections of identifiers. The CAN ID
look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024
standard frame identifiers or 512 extended frame identifiers or a mixture of both types. It is
also possible to define identifier groups for standard and extended message formats.
6.13.1.2 Pin description
The two CAN controllers in the LPC2917/2919/01 have the pins listed below. The CAN
pins are combined with other functions on the port pins of the LPC2917/2919/01. Table 19
shows the CAN pins (x runs from 0 to 1).
Table 19. CAN pins
Symbol
Pin name
TXDC0/1
RXDC0/1
Direction
OUT
Description
CANx TXD
CANx RXD
CAN channel x transmit data output
CAN channel x receive data input
IN
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
34 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
6.13.2 LIN
ARM9 microcontroller with CAN and LIN
The LPC2917/2919/01 contain two LIN 2.0 master controllers. These can be used as
dedicated LIN 2.0 master controllers with additional support for sync break generation and
with hardware implementation of the LIN protocol according to spec 2.0.
Remark: Both LIN channels can be also configured as UART channels.
The key features are:
• Complete LIN 2.0 message handling and transfer
• One interrupt per LIN message
• Slave response time-out detection
• Programmable sync-break length
• Automatic sync-field and sync-break generation
• Programmable inter-byte space
• Hardware or software parity generation
• Automatic checksum generation
• Fault confinement
• Fractional baud rate generator
6.13.2.1 Pin description
The two LIN 2.0 master controllers in the LPC2917/2919/01 have the pins listed below.
The LIN pins are combined with other functions on the port pins of the LPC2917/2919/01.
Table 20 shows the LIN pins. For more information see Ref. 1 subsection 3.43, LIN master
controller.
Table 20. LIN controller pins
Symbol
Pin name
Direction
OUT
Description
LIN0/1 TXD TXDL0/1
LIN0/1 RXD RXDL0/1
LIN channel 0/1 transmit data output
LIN channel 0/1 receive data input
IN
6.13.3 I2C-bus serial I/O controllers
The LPC2917/2919/01 each contain two I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus, and it can be
controlled by more than one bus master connected to it.
The main features if the I2C-bus interfaces are:
• I2C0 and I2C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus)
and do not support powering off of individual devices connected to the same bus
lines.
• Easy to configure as master, slave, or master/slave.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
35 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.
6.13.3.1 Pin description
Table 21. I2C-bus pins[1]
Symbol Pin name
Direction
I/O
Description
I2C SCL0/1 SCL0/1
I2C SDA0/1 SDA0/1
I2C clock input/output
I2C data input/output
I/O
[1] Note that the pins are not I2C-bus compliant open-drain pins.
6.14 Modulation and sampling control subsystem
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2917/2919/01
includes four Pulse-Width Modulators (PWMs), two 10-bit successive approximation
Analog-to-Digital Converters (ADCs) and two timers.
The key features of the MSCSS are:
• Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options
• Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality
• Two dedicated timers to schedule and synchronize the PWMs and ADCs
• Quadrature encoder interface
6.14.1 Functional description
The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
Figure 8 provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of
communication with the AHB system bus. Two internal timers are dedicated to this
subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the
first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the
PWMs. These carrier patterns can be used, for example, in applications requiring current
control. Several other trigger possibilities are provided for the ADCs (external, cascaded
or following a PWM). The capture inputs of both timers can also be used to capture the
start pulse of the ADCs.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
36 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
The PWMs can be used to generate waveforms in which the frequency, duty cycle and
rising and falling edges can be controlled very precisely. Capture inputs are provided to
measure event phases compared to the main counter. Depending on the applications,
these inputs can be connected to digital sensor motor outputs or digital external signals.
Interrupt signals are generated on several events to closely interact with the CPU.
The ADCs can be used for any application needing accurate digitized data from analog
sources. To support applications like motor control, a mechanism to synchronize several
PWMs and ADCs is available (sync_in and sync_out).
Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see
Section 6.15.2.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
37 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
AHB-TO-APB BRIDGE
MSCSS
IDX0
PHA0
PHB0
QEI
ADC1 EXT START
ADC1 IN[7:0]
capture
start
ADC1
MSCSS
TIMER0
ADC2 EXT START
start
ADC2 IN[7:0]
ADC2
start
PWM0 MAT[5:0]
PWM0
capture
carrier
carrier
carrier
synch
PWM1 MAT[5:0]
PWM2 MAT[5:0]
PWM1
PAUSE
MSCSS
TIMER1
synch
PWM2
carrier
synch
PWM3
PWM3 MAT[5:0]
PWM0 TRAP
PWM0 CAP[2:0]
PWM1 TRAP
PWM1 CAP[2:0]
PWM2 TRAP
PWM2 CAP[2:0]
PWM3 TRAP
PWM3 CAP[2:0]
002aad961
Fig 8. Modulation and Sampling Control Subsystem (MSCSS) block diagram
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
38 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.14.2 Pin description
The pins of the LPC2917/2919/01 MSCSS associated with the two ADC modules are
described in Section 6.14.4.2. Pins connected to the four PWM modules are described in
Section 6.14.5.4, pins directly connected to the MSCSS timer 1 module are described in
Section 6.14.6.1, and pins connected to the quadrature encoder interface are described in
Section 6.14.7.1.
6.14.3 Clock description
The MSCSS is clocked from a number of different sources:
• CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge
• CLK_MSCSS_APB clocks the subsystem APB bus
• CLK_MSCSS_MTMR0/1 clocks the timers
• CLK_MSCSS_PWM0..3 clocks the PWMs.
Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 1
or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see
Section 6.7.2.
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
6.14.4 Analog-to-digital converter
The MSCSS in the LPC2917/2919/01 includes two 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are:
• ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3 V
• External reference-level inputs
• 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at
2-bit resolution
• Programmable resolution from 2-bit to 10-bit
• Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode
• Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC
• Converted digital values are stored in a register for each channel
• Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel
• Power-down mode
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
39 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.14.4.1 Functional description
The ADC block diagram, Figure 9, shows the basic architecture of each ADC. The ADC
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than
or equal to the system clock frequency. To meet this constraint or to select the desired
lower sampling frequency, the clock generation unit provides a programmable fractional
system-clock divider dedicated to the ADC clock. Conversion rate is determined by the
ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC
registers requires an enabled ADC clock, which is controllable via the clock generation
unit, see Section 6.15.2.
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see Figure 8 for details.
ADC clock
(up to 4.5 MHz)
(BASE_ADC_CLK)
APB clock
(BASE_MSCSS_CLK)
SYSTEM DOMAIN
ADC DOMAIN
ANALOG
MUX
3.3 V
ADC1
ADC1 IN[7:0]
ADC2 IN[7:0]
update
3.3 V IN
ADC
REGISTERS
APB system bus
IRQ scan
ADC
CONTROL
conversion data
ANALOG
MUX
configuration data
3.3 V
ADC2
IRQ compare
3.3 V IN
IRQ
ADC
start 0
ADC
start 2
ADC
start 1
ADC
start 3
sync_out
002aad960
Fig 9. ADC block diagram
6.14.4.2 Pin description
The two ADC modules in the MSCSS have the pins described below. The ADCx input pins
are combined with other functions on the port pins of the LPC2917/2919/01. The VREFN
and VREFP pins are common for both ADCs. Table 22 shows the ADC pins.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
40 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 22. Analog to digital converter pins
Symbol
ADC1/2 IN[7:0]
Pin name
Direction Description
IN1/2[7:0]
IN
analog input for 3.3 V ADC1/2, channel 7 to
channel 0
ADCn_EXT_START CAP1[n]
IN
IN
IN
ADC external start-trigger input (n = 1 or 2)
ADC LOW reference level
ADC HIGH reference level
VREFN
VREFP
VREFN
VREFP
Remark: Note that the ADC1 and ADC2 accept an input voltage up to of 3.6 V (see
Table 33) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant.
6.14.4.3 Clock description
The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and
CLK_ADCx (x = 1 or 2), see Section 6.7.2. Note that each ADC has its own CLK_ADCx
and CLK_MSCSS_ADCx_APB branch clocks for power management. If an ADC is
unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off.
The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to
CLK_MSCSS_APB since they are derived from the same base clock
BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical
since they are derived from the same base clock BASE_ADC_CLK.
The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.
Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also
Figure 9.
6.14.5 Pulse Width Modulator (PWM)
The MSCSS in the LPC2917/2919/01 includes four PWM modules with the following
features.
• Six pulse-width modulated output signals
• Double edge features (rising and falling edges programmed individually)
• Optional interrupt generation on match (each edge)
• Different operation modes: continuous or run-once
• 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods
• A protective mode (TRAP) holding the output in a software-controllable state and with
optional interrupt generation on a trap event
• Three capture registers and capture trigger pins with optional interrupt generation on
a capture event
• Interrupt generation on match event, capture event, PWM counter overflow or trap
event
• A burst mode mixing the external carrier signal with internally generated PWM
• Programmable sync-delay output to trigger other PWM modules (master/slave
behavior)
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
41 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.14.5.1 Functional description
The ability to provide flexible waveforms allows PWM blocks to be used in multiple
applications; e.g. dimmer/lamp control and fan control. Pulse-width modulation is the
preferred method for regulating power since no additional heat is generated, and it is
energy-efficient when compared with linear-regulating voltage control networks.
The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A
very basic application of these pulses can be in controlling the amount of power
transferred to a load. Since the duty cycle of the pulses can be controlled, the desired
amount of power can be transferred for a controlled duration. Two examples of such
applications are:
• Dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle
period allows the PWM to control the amount of power to be transferred to the load.
The PWM functions as a dimmer controller in this application
• Motor controller: The PWM provides multi-phase outputs, and these outputs can be
controlled to have a certain pattern sequence. In this way the force/torque of the
motor can be adjusted as desired. This makes the PWM function as a motor drive.
sync_in
transfer_enable_in
APB DOMAIN
update
PWM DOMAIN
match outputs
capture inputs
APB system bus
capture data
PWM,
COUNTER,
PRESCALE
COUNTER
&
PWM
CONTROL
&
PWM counter value
IRQ pwm
REGISTERS
SHADOW
REGISTERS
IRQ capt_match
config data
IRQs
trap input
carrier inputs
transfer_enable_out
sync_out
002aad837
Fig 10. PWM block diagram
The PWM block diagram in Figure 10 shows the basic architecture of each PWM. PWM
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
42 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock
source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer
counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references
are related to the period of this clock. See Section 6.15 for information on generation of
these clocks.
6.14.5.2 Synchronizing the PWM counters
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See Figure 8 for details of the connections of the PWM modules within the MSCSS in the
LPC2917/2919/01. PWM 0 can be master over PWM 1; PWM 1 can be master over
PWM 2, etc.
6.14.5.3 Master and slave mode
A PWM module can provide synchronization signals to other modules (also called Master
mode). The signal sync_out is a pulse of one clock cycle generated when the internal
PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out,
generated if a transfer from system registers to PWM shadow registers occurred when the
PWM counter restarted. A delay may be inserted between the counter start and
generation of trans_enable_out and sync_out.
A PWM module can use input signals trans_enable_in and sync_in to synchronize its
internal PWM counter and the transfer of shadow registers (Slave mode).
6.14.5.4 Pin description
Each of the four PWM modules in the MSCSS has the following pins. These are combined
with other functions on the port pins of the LPC2917/2919/01. Table 23 shows the PWM0
to PWM3 pins.
Table 23. PWM pins
Symbol
Pin name
PCAPn[0]
PCAPn[1]
PCAPn[2]
PMATn[0]
PMATn[1]
PMATn[2]
PMATn[3]
PMATn[4]
PMATn[5]
TRAPn
Direction
IN
Description
PWMn CAP[0]
PWMn CAP[1]
PWMn CAP[2]
PWMn MAT[0]
PWMn MAT[1]
PWMn MAT[2]
PWMn MAT[3]
PWMn MAT[4]
PWMn MAT[5]
PWMn TRAP
PWM n capture input 0
PWM n capture input 1
PWM n capture input 2
PWM n match output 0
PWM n match output 1
PWM n match output 2
PWM n match output 3
PWM n match output 4
PWM n match output 5
PWM n trap input
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
43 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.14.5.5 Clock description
The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 - 3), see Section 6.7.2.
Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power
management. The frequency of all these clocks is identical to CLK_MSCSS_APB since
they are derived from the same base clock BASE_MSCSS_CLK.
Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer
counter registers of the PWM modules run at the same clock as the APB system interface
CLK_MSCSS_APB. This clock is independent of the AHB system clock.
If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.
6.14.6 Timers in the MSCSS
The two timers in the MSCSS are functionally identical to the timers in the peripheral
subsystem, see Section 6.12.3. The features of the timers in the MSCSS are the same as
the timers in the peripheral subsystem, but the capture inputs and match outputs are not
available on the device pins. These signals are instead connected to the ADC and PWM
modules as outlined in the description of the MSCSS, see Section 6.14.1.
See section Section 6.12.3 for a functional description of the timers.
6.14.6.1 Pin description
MSCSS timer 0 has no external pins.
MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined
with other functions on the port pins of the LPC2917/2919/01. Table 24 shows the MSCSS
timer 1 external pin.
Table 24. MSCSS timer 1 pin
Symbol
Direction
Description
MSCSS PAUSE
IN
pause pin for MSCSS timer 1
6.14.6.2 Clock description
The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0 to 1), see
Section 6.7.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for
power management. The frequency of all these clocks is identical to CLK_MSCSS_APB
since they are derived from the same base clock BASE_MSCSS_CLK.
Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter
registers run at the same clock as the APB system interface CLK_MSCSS_APB. This
clock is independent of the AHB system clock.
If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.
6.14.7 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
44 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
The QEI has the following features:
• Tracks encoder position.
• Increments/ decrements depending on direction.
• Programmable for 2X or 4X position counting.
• Velocity capture using built-in timer.
• Velocity compare function with less than interrupt.
• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
• Connected to APB.
6.14.7.1 Pin description
The QEI module in the MSCSS has the following pins. These are combined with other
functions on the port pins of the LPC2917/2919/01. Table 25 shows the QEI pins.
Table 25. QEI pins
Symbol
Pin name
IDX0
Direction
Description
QEI0 IDX
QEI0 PHA
IN
IN
Index signal. Can be used to reset the position.
PHA0
Sensor signal. Corresponds to PHA in
quadrature mode and to direction in
clock/direction mode.
QEI0 PHB
PHB0
IN
Sensor signal. Corresponds to PHB in
quadrature mode and to clock signal in
clock/direction mode.
6.14.7.2 Clock description
The QEI module is clocked by CLK_MSCSS_QEI, see Section 6.7.2. The frequency of
this clock is identical to CLK_MSCSS_APB since they are derived from the same base
clock BASE_MSCSS_CLK.
If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off.
6.15 Power, clock and reset control subsystem
The Power, Clock, and Reset Control Subsystem (PCRSS) in the LPC2917/2919/01
includes the Clock Generator Units (CGU0 and CGU1), a Reset Generator Unit (RGU)
and a Power Management Unit (PMU).
Figure 11 provides an overview of the PCRSS. An AHB-to-DTL bridge provides
communication with the AHB system bus.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
45 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
PMU
CGU0
CGU1
OUT
PLL
EXTERNAL
OSCILLATOR
OUT6
OUT11
PLL
branch
clocks
CLOCK
GATES
OUT0
OUT1
FDIV
LOW POWER
RING
OSCILLATOR
OUT5
OUT7
FDIV[6:0]
AHB
master
disable:
OUT9
CGU0/1
REGISTERS
CLOCK
ENABLE
CONTROL
grant
request
PMU
REGISTERS
AHB2DTL
BRIDGE
wakeup_a
RGU
AHB_RST
RGU
REGISTERS
SCU_RST
RESET OUTPUT
DELAY LOGIC
WARM_RST
COLD_RST
PCR_RST
RGU_RST
POR_RST
INPUT
DEGLITCH/
SYNC
POR
RST (device pin)
reset from watchdog counter
002aae355
Fig 11. Power, Clock, and Reset control Sub System (PCRSS) block diagram
6.15.1 Clock description
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see Section 6.7.2. CLK_SYS_PCRSS is derived from
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
46 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.15.2 Clock Generation Unit (CGU0)
The key features are:
• Generation of 11 base clocks, selectable from several embedded clock sources.
• Crystal oscillator with power-down.
• Control PLL with power-down.
• Very low-power ring oscillator, always on to provide a ‘safe clock’.
• Seven fractional clock dividers with L/D division.
• Individual source selector for each base clock, with glitch-free switching.
• Autonomous clock-activity detection on every clock source.
• Protection against switching to invalid or inactive clock sources.
• Embedded frequency counter.
• Register write-protection mechanism to prevent unintentional alteration of clocks.
Remark: Any clock-frequency adjustment has a direct impact on the timing of all on-board
peripherals.
6.15.2.1 Functional description
The clock generation unit provides 11 internal clock sources as described in Table 26.
Table 26. CGU0 base clocks
Numbe Name
r
Frequency
(MHz) [1]
Description
0
BASE_SAFE_CLK
0.4
base safe clock (always on)
base system clock
1
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_UART_CLK
BASE_ICLK0_CLK
BASE_SPI_CLK
BASE_TMR_CLK
BASE_ADC_CLK
reserved
125
0.4 [2]
125
125
125
125
50
2
base PCR subsystem clock
base IVNSS subsystem clock
base MSCSS subsystem clock
base UART clock
3
4
5
6
base internal clock 0, for CGU1
base SPI clock
7
8
125
4.5
base timers clock
9
base ADCs clock
10
11
-
-
BASE_ICLK1_CLK
125
base internal clock 1, for CGU1
[1] Maximum frequency that guarantees stable operation of the LPC2917/2919/01.
[2] Fixed to low-power oscillator.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
47 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
CLOCK GENERATION UNIT (CGU0)
OUT 0
BASE_SAFE_CLK
BASE_SYS_CLK
FDIV0
FDIV1
OUT 1
OUT 2
OUT 3
400 kHz LP_OSC
clkout
clkout120
EXTERNAL
OSCILLATOR
PLL
BASE_PCR_CLK
clkout240
BASE_IVNSS_CLK
OUT 11
BASE_ICLK1_CLK
FDIV6
FREQUENCY
MONITOR
CLOCK
DETECTION
AHB TO DTL BRIDGE
002aae147
Fig 12. Block diagram of the CGU0
For generation of these base clocks, the CGU consists of primary and secondary clock
generators and one output generator for each base clock.
There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a
crystal oscillator. See Figure 12.
LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU0 itself and for
BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog
timer). To prevent the device from losing its clock source LP_OSC cannot be put into
power-down. The crystal oscillator can be used as source for high-frequency clocks or as
an external clock input if a crystal is not connected.
Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL
has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
48 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Configuration of the CGU0: For every output generator generating the base clocks a
choice can be made from the primary and secondary clock generators according to
Figure 13.
LP_OSC
FDIV0:6
EXTERNAL
OSCILLATOR
clkout
clkout120
PLL
clkout240
OUTPUT
CONTROL
clock
outputs
002aad834
Fig 13. Structure of the clock generation scheme
Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be
connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to
LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only
LP_OSC as source.
The fractional dividers can be connected to one of the outputs of the PLL or directly to
LP_OSC/crystal Oscillator.
The PLL is connected to the crystal oscillator.
In this way every output generating the base clocks can be configured to get the required
clock. Multiple output generators can be connected to the same primary or secondary
clock source, and multiple secondary clock sources can be connected to the same PLL
output or primary clock source.
Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL
outputs itself for example - will be blocked by hardware. The control register will not be
written, the previous value will be kept, although all other fields will be written with new
data. This prevents clocks being blocked by incorrect programming.
Default Clock Sources: Every secondary clock generator or output generator is
connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.
It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as one
of the first steps in the boot code after verifying that the high-frequency clock generator is
running.
Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid,
and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the
control registers. This is accomplished by adding a clock detector to every clock
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
49 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
generator. The RDET register keeps track of which clocks are active and inactive, and the
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32 BASE_PCR_CLK cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched
glitch-free, both at the output generator stage and also at secondary source generators.
In the case of the PLL the clock will be stopped and held low for long enough to allow the
PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch
will occur as quickly as possible, although there will always be a period when the clock is
held low due to synchronization requirements.
If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is
assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the
interface.
6.15.2.2 PLL functional description
A block diagram of the PLL is shown in Figure 14. The input clock is fed directly to the
analog section. This block compares the phase and frequency of the inputs and generates
the main clock2. These clocks are either divided by 2 × P by the programmable post
divider to create the output clock, or sent directly to the output. The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the analog section is also monitored by the lock detector to signal
when the PLL has locked onto the input clock.
PSEL bits
P23EN bit
clkout120
clkout240
clkout
/ 2PDIV
input clock
P23
CCO
bypass
direct
clkout
/ MDIV
002aad833
MSEL bits
Fig 14. PLL block diagram
2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 35, Dynamic characteristics.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
50 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Triple output phases: For applications that require multiple clock phases two additional
clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks
with a 120° phase difference. In this mode all three clocks generated by the analog
section are sent to the output dividers. When the PLL has not yet achieved lock the
second and third phase output dividers run unsynchronized, which means that the phase
relation of the output clocks is unknown. When the PLL LOCK register is set the second
and third phase of the output dividers are synchronized to the main output clock CLKOUT
PLL, thus giving three clocks with a 120° phase difference.
Direct output mode: In normal operating mode (with DIRECT set to logic 0) the CCO
clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an
output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock
can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not
directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can
deviate from 50 %.
Power-down control: A Power-down mode has been incorporated to reduce power
consumption when the PLL clock is not needed. This is enabled by setting the PD control
register bit. In this mode the analog section of the PLL is turned off, the oscillator and the
phase-frequency detector are stopped and the dividers enter a reset state. While in
Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When
Power-down mode is terminated by clearing the PD control-register bit the PLL resumes
normal operation, and makes the LOCK signal high once it has regained lock on the input
clock.
6.15.2.3 Pin description
The CGU0 module in the LPC2917/2919/01 has the pins listed in Table 27 below.
Table 27. CGU0 pins
Symbol
Direction
OUT
Description
XOUT_OSC
XIN_OSC
Oscillator crystal output
IN
Oscillator crystal input or external clock input
6.15.3 Clock generation for CLK_OUT (CGU1)
The CGU1 block is functionally identical to the CGU0 block and generates a dedicated
output clock. The CGU1 block uses its own PLL and fractional divider. The PLLs used in
CGU0 and CGU1 are identical (see Section 6.15.2.2).
The clock input to the CGU1 PLL is provided by one of two base clocks generated in the
CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL
can be configured to drive the output clock directly.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
51 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
CLOCK GENERATION UNIT
(CGU1)
OUT
BASE_OUT_CLK
clkout
BASE_ICLK0_CLK
BASE_ICLK1_CLK
clkout120
PLL
FDIV0
clkout240
AHB TO DTL BRIDGE
002aae266
Fig 15. Block diagram of the CGU1
6.15.3.1 Pin description
The CGU1 module in the LPC2917/2919/01 has the pins listed in Table 27 below.
Table 28. CGU1 pins
Symbol
Direction
Description
CLK_OUT
OUT
clock output
6.15.4 Reset Generation Unit (RGU)
The RGU controls all internal resets.
The key features of the Reset Generation Unit (RGU) are:
• Reset controlled individually per subsystem
• Automatic reset stretching and release
• Monitor function to trace resets back to source
• Register write-protection mechanism to prevent unintentional resets
6.15.4.1 Functional description
Each reset output is defined as a combination of reset input sources including the external
reset input pins and internal power-on reset, see Table 29. The first five resets listed in this
table form a sort of cascade to provide the multiple levels of impact that a reset may have.
The combined input sources are logically OR-ed together so that activating any of the
listed reset sources causes the output to go active.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
52 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 29. Reset output configuration
Reset output Reset source
Parts of the device reset when activated
POR_RST
power-on reset module
POR_RST, RST pin
LP_OSC; is source for RGU_RST
RGU_RST
RGU internal; is source for PCR_RST
PCR_RST
RGU_RST, WATCHDOG PCR internal; is source for COLD_RST
COLD_RST
WARM_RST
SCU_RST
PCR_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
CFID_RST
CFID
FMC_RST
embedded Flash-Memory Controller (FMC)
embedded SRAM-Memory Controller
external Static-Memory Controller (SMC)
GeSS AHB-to-APB bridge
PeSS AHB-to-APB bridge
all GPIO modules
EMC_RST
SMC_RST
GESS_A2A_RST
PESS_A2A_RST
GPIO_RST
UART_RST
all UART modules
TMR_RST
all Timer modules in PeSS
all SPI modules
SPI_RST
IVNSS_A2A_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2A_RST
IVNSS AHB-to-APB bridge
all CAN modules including Acceptance filter
all LIN modules
MSCSS AHB to APB bridge
all PWM modules
MSCSS_PWM_RST WARM_RST
MSCSS_ADC_RST WARM_RST
MSCSS_TMR_RST WARM_RST
all ADC modules
all Timer modules in MSCSS
all I2C modules
I2C_RST
QEI_RST
DMA_RST
VIC_RST
AHB_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
Quadrature encoder
GPDMA controller
Vectored Interrupt Controller (VIC)
CPU and AHB Bus infrastructure
6.15.4.2 Pin description
The RGU module in the LPC2917/2919/01 has the following pins. Table 30 shows the
RGU pins.
Table 30. RGU pins
Symbol
Direction Description
IN external reset input, Active LOW; pulled up internally
RST
6.15.5 Power Management Unit (PMU)
This module enables software to actively control the system’s power consumption by
disabling clocks not required in a particular operating mode.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
53 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Using the base clocks from the CGU as input, the PMU generates branch clocks to the
rest of the LPC2917/2919/01. Output clocks branched from the same base clock are
phase- and frequency-related. These branch clocks can be individually controlled by
software programming.
The key features are:
• Individual clock control for all LPC2917/2919/01 sub-modules
• Activates sleeping clocks when a wake-up event is detected
• Clocks can be individually disabled by software
• Supports AHB master-disable protocol when AUTO mode is set
• Disables wake-up of enabled clocks when Power-down mode is set
• Activates wake-up of enabled clocks when a wake-up event is received
• Status register is available to indicate if an input base clock can be safely switched off
(i.e. all branch clocks are disabled)
6.15.5.1 Functional description
The PMU controls all internal clocks coming out of the CGU0 for power-mode
management. With some exceptions, each branch clock can be switched on or off
individually under control of software register bits located in its individual configuration
register. Some branch clocks controlling vital parts of the device operate in a fixed mode.
Table 31 shows which mode- control bits are supported by each branch clock.
By programming the configuration register the user can control which clocks are switched
on or off, and which clocks are switched off when entering Power-down mode.
Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting
the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU
into power-down should be controlled by disabling the branch clock for the CPU.
Remark: For any disabled branch clocks to be re-activated their corresponding base
clocks must be running (controlled by CGU0).
Table 31 shows the relation between branch and base clocks, see also Section 6.7.1.
Every branch clock is related to one particular base clock: it is not possible to switch the
source of a branch clock in the PMU.
Table 31. Branch clock overview
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Branch clock name
Base clock
Implemented switch on/off
mechanism
WAKE-UP
AUTO
RUN
CLK_SAFE
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
0
+
+
+
+
0
+
+
+
+
1
1
1
1
+
CLK_SYS_CPU
CLK_SYS
CLK_SYS_PCR
CLK_SYS_FMC
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
54 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 31. Branch clock overview …continued
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Branch clock name
Base clock
Implemented switch on/off
mechanism
WAKE-UP
AUTO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
RUN
+
+
+
+
+
+
+
+
+
+
+
+
+
1
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_PCR_SLOW
CLK_IVNSS_APB
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
CLK_MSCSS_APB
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK
CLK_MSCSS_ADC2_APB BASE_MSCSS_CLK
CLK_MSCSS_QEI
CLK_OUT_CLK
CLK_UART0
CLK_UART1
CLK_SPI0
BASE_MSCSS_CLK
BASE_OUT_CLK
BASE_UART_CLK
BASE_UART_CLK
BASE_SPI_CLK
CLK_SPI1
BASE_SPI_CLK
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
55 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 31. Branch clock overview …continued
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Branch clock name
Base clock
Implemented switch on/off
mechanism
WAKE-UP
AUTO
RUN
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
CLK_ADC2
BASE_SPI_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_ADC_CLK
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
6.16 Vectored Interrupt Controller (VIC)
The LPC2917/2919/01 contains a very flexible and powerful Vectored Interrupt Controller
to interrupt the ARM processor on request.
The key features are:
• Level-active interrupt request with programmable polarity.
• 56 interrupt-request inputs.
• Software-interrupt request capability associated with each request input.
• Interrupt request state can be observed before masking.
• Software-programmable priority assignments to interrupt requests up to 15 levels.
• Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ.
• Fast identification of interrupt requests through vector.
• Support for nesting of interrupt service routines.
6.16.1 Functional description
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
• Target 0 is ARM processor FIQ (fast interrupt service).
• Target 1 is ARM processor IRQ (standard interrupt service).
Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never
lead to an interrupt).
• Priority 1 corresponds to the lowest priority.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
56 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
• Priority 15 corresponds to the highest priority.
Software interrupt support is provided and can be supplied for:
• Testing RTOS (Real-Time Operating System) interrupt handling without using
device-specific interrupt service routines.
• Software emulation of an interrupt-requesting device, including interrupts.
6.16.2 Clock description
The VIC is clocked by CLK_SYS_VIC, see Section 6.7.2.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
57 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
7. Limiting values
Table 32. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Supply pins
Ptot
[1]
total power dissipation
core supply voltage
-
1.5
W
V
VDD(CORE)
VDD(OSC_PLL)
−0.5
−0.5
+2.0
+2.0
oscillator and PLL supply
voltage
V
VDDA(ADC3V3)
3.3 V ADC analog supply
voltage
−0.5
+4.6
V
VDD(IO)
IDD
input/output supply voltage
supply current
−0.5
+4.6
98
V
[2]
[2]
average value per supply
pin
-
mA
ISS
ground current
average value per ground
pin
-
98
mA
Input pins and I/O pins
VXIN_OSC voltage on pin XIN_OSC
VI(IO)
−0.5
−0.5
−0.5
+2.0
V
V
V
[3][4][5]
[4][5]
I/O input voltage
VDD(IO) + 3.0
VI(ADC)
ADC input voltage
for ADC1/2: I/O port 0 pin 8
to pin 23.
VDDA(ADC3V3)
+ 0.5
VVREFP
VVREFN
II(ADC)
voltage on pin VREFP
voltage on pin VREFN
ADC input current
−0.5
−0.5
-
+3.6
+3.6
35
V
V
[2]
average value per input pin
mA
Output pins and I/O pins configured as output
[6]
[6]
IOHS
HIGH-level short-circuit
output current
drive HIGH, output shorted
to VSS(IO)
-
-
−33
mA
mA
IOLS
LOW-level short-circuit
output current
drive LOW, output shorted
to VDD(IO)
+38
General
Tstg
storage temperature
ambient temperature
−65
−40
+150
+85
°C
°C
Tamb
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
58 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 32. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
ESD
Parameter
Conditions
Min
Max
Unit
VESD
electrostatic discharge
voltage
on all pins
[7]
human body model
charged device model
on corner pins
−2000
−500
+2000
+500
V
V
charged device model
−750
+750
V
[1] Based on package heat transfer, not device power consumption.
[2] Peak current must be limited at 25 times average current.
[3] For I/O Port 0, the maximum input voltage is defined by VI(ADC)
.
[4] Only when VDD(IO) is present.
[5] Note that pull-up should be off. With pull-up do not exceed 3.6 V.
[6] 112 mA per VDD(IO) or VSS(IO) should not be exceeded.
[7] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
59 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
8. Static characteristics
Table 33. Static characteristics
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 °C to +85 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
Core supply
VDD(CORE)
IDD(CORE)
core supply voltage
core supply current
1.71
-
1.80
75
1.89
-
V
Device state after reset;
system clock at
mA
125 MHz; Tamb = 85 °C;
executing code
while(1){} from flash.
[2]
all clocks off
-
30
475
µA
I/O supply
VDD(IO)
input/output supply
voltage
2.7
-
-
3.6
V
IDD(IO)
I/O supply current
Power-down mode
0.5
3.25
µA
Oscillator supply
VDD(OSC_PLL) oscillator and PLL supply
voltage
1.71
1.80
1.89
V
IDD(OSC_PLL) oscillator and PLL supply normal mode
current
-
-
-
-
1
2
mA
Power-down mode
µA
Analog-to-digital converter supply
VDDA(ADC3V3) 3.3 V ADC analog supply
voltage
3.0
3.3
3.6
V
IDDA(ADC3V3) 3.3 V ADC analog supply normal mode
current
-
-
-
-
1.9
4
mA
Power-down mode
µA
Input pins and I/O pins configured as input
[3][4]
VI
input voltage
all port pins and VDD(IO)
applied;
−0.5
-
+ 5.5
V
see Section 7
[4]
port 0 pins 8 to 23 when
ADC1/2 is used
VVREFP
+3.6
all port pins and VDD(IO)
not applied
−0.5
−0.5
-
-
V
V
all other I/O pins, RST,
TRST, TDI, JTAGSEL,
TMS, TCK
VDD(IO)
VIH
HIGH-level input voltage all port pins, RST,
TRST, TDI, JTAGSEL,
TMS, TCK; see
2.0
-
-
-
-
V
V
Figure 22
VIL
LOW-level input voltage
all port pins, RST,
TRST, TDI, JTAGSEL,
TMS, TCK; see
Figure 21
0.8
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
60 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 33. Static characteristics …continued
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 °C to +85 °C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Vhys
Parameter
Conditions
Min
0.4
-
Typ
Max
Unit
V
hysteresis voltage
-
-
-
ILIH
HIGH-level input leakage
current
1
µA
ILIL
LOW-level input leakage
current
-
-
1
µA
µA
µA
II(pd)
II(pu)
pull-down input current
all port pins, VI = 3.3 V;
VI = 5.5 V; see Figure 23
25
−25
50
−50
100
−115
pull-up input current
all port pins, RST,
TRST, TDI, JTAGSEL,
TMS: VI = 0 V; VI > 3.6 V
is not allowed; see
Figure 24
[5]
Ci
input capacitance
-
3
8
pF
Output pins and I/O pins configured as output
VO
output voltage
0
-
-
-
-
VDD(IO)
V
VOH
HIGH-level output voltage IOH = −4 mA
LOW-level output voltage IOL = 4 mA
load capacitance
VDD(IO) – 0.4
-
V
VOL
-
-
0.4
25
V
CL
pF
Oscillator
VXIN_OSC
Rs(xtal)
voltage on pin XIN_OSC
0
-
1.8
V
[6]
crystal series resistance
fosc = 10 MHz to 15 MHz
Cxtal = 10 pF;
ext = 18 pF
Cxtal = 20 pF;
ext = 39 pF
-
-
-
-
160
60
Ω
Ω
C
C
[6]
[7]
fosc = 15 MHz to 20 MHz
Cxtal = 10 pF;
-
-
-
80
2
Ω
C
ext = 18 pF
Ci
input capacitance
of XIN_OSC
pF
Power-up reset
[8]
[8]
[8]
Vtrip(high)
Vtrip(low)
Vtrip(dif)
high trip level voltage
1.1
1.0
50
1.4
1.3
120
1.6
1.5
180
V
low trip level voltage
V
difference between high
and low trip level voltage
mV
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C on wafer
level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover
the specified temperature and power-supply voltage range.
[2] Leakage current is exponential to temperature; worst-case value is at 85 °C Tvj. All clocks off. Analog modules and FLASH powered
down.
[3] Not 5 V-tolerant when pull-up is on.
[4] For I/O Port 0, the maximum input voltage is defined by VI(ADC)
.
[5] For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input
capacitance to ADC.
[6] Cxtal is crystal load capacitance and Cext are the two external load capacitors.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
61 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
[7] This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are
based on simulation results.
[8] The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 µs before reset is de-asserted; VDD(CORE) must be below
Vtrip(low) for 11 µs before internal reset is asserted.
Table 34. ADC static characteristics
VDDA(ADC3V3) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol
VVREFN
VVREFP
Zi
Parameter
Conditions
Min
Typ
Max
Unit
V
voltage on pin VREFN
voltage on pin VREFP
input impedance
0
-
-
-
VVREFP − 2
VVREFN + 2
4.4
VDDA(ADC3V3)
-
V
between VVREFN and
VVREFP
kΩ
VIA
Cia
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
VVREFN
-
-
-
-
-
-
-
-
-
VVREFP
1
V
pF
[1][2][3]
[1][4]
[1][5]
[1][6]
[1][7]
[8]
ED
±1
LSB
LSB
LSB
%
EL(adj)
EO
-
-
-
-
-
±2
±3
EG
gain error
±0.5
±4
ET
absolute error
LSB
kΩ
Rvsi
voltage source interface
resistance
40
[1] Conditions: VSS(IO) = 0 V, VDDA(ADC3V3) = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 17.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 17.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 17.
[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
and the ideal transfer curve. See Figure 17.
[8] See Figure 16.
LPC2XXX
R
vsi
20 kΩ
ADC IN[y]
ADC IN[y]
SAMPLE
3 pF
5 pF
V
EXT
V
V
SS(IO), SS(CORE)
002aae280
Fig 16. Suggested ADC interface - LPC2917/2919/01 ADC1/2 IN[y] pin
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
62 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
IA
(LSB
)
ideal
offset error
E
O
002aae703
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 17. ADC characteristics
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
63 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
8.1 Power consumption
002aae241
80
I
DD(CORE)
(mA)
60
40
20
0
10
50
90
130
core frequency (MHz)
Conditions: Tamb = 25 °C; active mode entered executing code from flash; core voltage 1.8 V; all
peripherals enabled but not configured to run.
Fig 18. IDD(CORE) at different core frequencies (active mode)
002aae240
80
125 MHz
I
DD(CORE)
(mA)
60
40
20
0
100 MHz
80 MHz
40 MHz
10 MHz
1.8
1.7
1.9
core voltage (V)
Conditions: Tamb = 25 °C; active mode entered executing code from flash; all peripherals enabled
but not configured to run.
Fig 19. IDD(CORE) at different core voltages VDD(CORE) (active mode)
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
64 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
002aae239
80
125 MHz
I
DD(CORE)
(mA)
60
40
20
0
100 MHz
80 MHz
40 MHz
10 MHz
−40
−15
10
35
60
85
temperature (°C)
Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals
enabled but not configured to run.
Fig 20. IDD(CORE) at different temperatures (active mode)
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
65 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
8.2 Electrical pin characteristics
002aae689
500
OL
V
(mV)
400
85 °C
25 °C
0 °C
300
200
100
0
−40 °C
1.0
2.0
3.0
4.0
5.0
6.0
I
(mA)
OL
VDD(IO) = 3.3 V.
Fig 21. Typical LOW-level output voltage versus LOW-level output current
002aae690
3.5
V
OH
(V)
85 °C
25 °C
0 °C
3.0
−40 °C
2.5
2.0
1.0
2.0
3.0
4.0
5.0
6.0
I
(mA)
OH
VDD(IO) = 3.3 V.
Fig 22. Typical HIGH-level output voltage versus HIGH-level output current
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
66 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
002aae691
80
I
I(pd)
(µA)
70
V
= 3.6 V
3.0 V
DD(IO)
60
50
40
2.7 V
−40
−15
10
35
60
85
temperature (°C)
VI = 3.3 V.
Fig 23. Typical pull-down current versus temperature
002aae692
−20
I
I(pu)
(µA)
V
= 2.7 V
DD(IO)
−40
3.3 V
3.6 V
−60
−80
−100
−40
−15
10
35
60
85
temperature (°C)
VI = 0 V.
Fig 24. Typical pull-up current versus temperature
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
67 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
9. Dynamic characteristics
9.1 Dynamic characteristics: I/O pins, internal clock, oscillators, PLL, and
CAN
Table 35. Dynamic characteristics
VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
I/O pins
tTHL
Parameter
Conditions
Min
Typ
Max
Unit
HIGH to LOW transition CL = 30 pF
time
4
4
-
-
13.8
13.8
ns
ns
tTLH
LOW to HIGH transition CL = 30 pF
time
CLKOUT pin
fclk
clock frequency
on pin CLKOUT
-
-
40
MHz
Internal clock
fclk(sys)
[2]
[2]
system clock frequency
system clock period
10
8
-
-
125
100
MHz
ns
Tclk(sys)
Low-power ring oscillator
fref(RO)
RO reference
frequency
0.36
-
0.4
6
0.42
-
MHz
[3]
tstartup
start-up time
at maximum frequency
µs
Oscillator
fi(osc)
oscillator input
frequency
maximum frequency is
the clock input of an
external clock source
applied to the XIN_OSC
pin
10
-
100
MHz
[3]
[4]
tstartup
start-up time
at maximum frequency
-
500
-
µs
PLL
fi(PLL)
fo(PLL)
PLL input frequency
PLL output frequency
10
10
156
-
-
-
-
-
-
25
MHz
MHz
MHz
ns
160
320
63.4
60.3
CCO; direct mode
ta(clk)
ta(A)
clock access time
address access time
-
ns
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
68 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
Table 35. Dynamic characteristics …continued
VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground; positive currents flow into the IC; unless otherwise specified.[1]
Symbol
Jitter specification for CAN
tjit(cc)(p-p) cycle to cycle jitter
(peak-to-peak value)
Parameter
Conditions
Min
Typ
Max
Unit
[3]
on CAN TXDC pin
-
0.4
1
ns
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] See Table 26.
[3] This parameter is not part of production testing or final testing, hence only a typical value is stated.
[4] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
002aae373
520
1.9 V
f
ref(RO)
(kHz)
1.8 V
1.7 V
510
500
490
480
−40
−15
10
35
60
85
temperature (°C)
Fig 25. Low-power ring oscillator thermal characteristics
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
69 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
9.2 Dynamic characteristics: I2C-bus interface
Table 36. Dynamic characteristic: I2C-bus pins
VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground; positive currents flow into the IC; unless otherwise specified[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
[3]
tf(o)
output fall time
VIH to VIL
20 + 0.1 × Cb
-
-
ns
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.
9.3 Dynamic characteristics: SPI
Table 37. Dynamic characteristics of SPI pins
VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; VDDA(ADC5V0) = 3.0 V to 5.5 V;
Tvj = -40 °C to +85 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise
specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
fSPI
SPI operating frequency
master operation
slave operation
⁄
65024fclk(SPI)
-
1⁄2fclk(SPI) MHz
1⁄4fclk(SPI) MHz
1
⁄65024fclk(SPI)
-
tsu(SPI_MISO)
SPI_MISO set-up time
Tamb = 25 °C;
measured in SPI
Master mode;
see Figure 26
-
11
-
ns
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
shifting edges
SCKn
sampling edges
SDOn
SDIn
t
su(SPI_MISO)
002aae695
Fig 26. SPI data input set-up time in SSP Master mode
Rev. 02 — 17 June 2009
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
70 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
9.4 Dynamic characteristics: flash memory and EEPROM
Table 38. Flash characteristics
Tamb = -40 °C to +85 °C; VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V;
VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
Symbol Parameter
Conditions
Min
Typ
Max
-
Unit
cycles
years
years
ms
[1]
Nendu
endurance
10000
-
tret
retention time
powered
unpowered
word
10
20
0.95
95
95
-
-
-
-
-
tprog
ter
programming time
erase time
1
1.05
105
105
150
1.05
70
global
100
ms
sector
100
ms
tinit
initialization time
page write time
-
µs
twr(pg)
tfl(BIST)
ta(clk)
ta(A)
0.95
-
1
38
-
ms
flash word BIST time
clock access time
address access time
ns
-
63.4
60.3
ns
-
-
ns
[1] Number of program/erase cycles.
Table 39. EEPROM characteristics
Tamb = -40 °C to +85 °C; VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V;
DDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
V
Symbol
Parameter
Conditions
Min
Typ
375
500000
-
Max
Unit
fclk
clock frequency
endurance
200
400
kHz
Nendu
tret
100000
10
-
-
cycles
years
retention time
powered
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
71 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
9.5 Dynamic characteristics: external static memory
Table 40. External static memory interface dynamic characteristics
VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground.[1]
Symbol Parameter
Conditions
Min
Typ
Max Unit
100 ns
20.5 ns
24.9 ns
TCLCL
ta(R)int
ta(W)int
clock cycle time
8
-
-
-
-
internal read access time
internal write access time
-
Read cycle parameters
tCSLAV CS LOW to address valid
−5
−2.5
-
-
ns
ns
time
tOELAV
OE LOW to address valid
time
−5 − WSTOEN × TCLCL −2.5 − WSTOEN × TCLCL
tCSLOEL
tsu(DQ)
CS LOW to OE LOW time
-
0 + WSTOEN × TCLCL
-
ns
ns
data input /output set-up
time
11
16
22
th(D)
data input hold time
0
-
2.5
0
5
-
ns
ns
ns
tCSHOEH CS HIGH to OE HIGH time
tBLSLBLSH BLS LOW to BLS HIGH time
-
(WST1 − WSTOEN +1) ×
-
TCLCL
tOELOEH OE LOW to OE HIGH time
-
-
(WST1 − WSTOEN +1) ×
TCLCL
-
-
ns
ns
tBLSLAV
BLS LOW to address valid
time
0 + WSTOEN × TCLCL
Write cycle parameters
[2]
[3]
tCSHBLSH CS HIGH to BLS HIGH time
-
0
-
-
-
-
ns
ns
ns
ns
tCSLWEL
CS LOW to WE LOW time
-
(WSTWEN + 0.5) × TCLCL
WSTWEN × TCLCL
(WSTWEN + 0.5) × TCLCL
−0.1
tCSLBLSL CS LOW to BLS LOW time
-
tWELDV
tCSLDV
WE LOW to data valid time
CS LOW to data valid time
-
−0.5
0.3 ns
tWELWEH WE LOW to WE HIGH time
-
(WST2 − WSTWEN +1) ×
-
ns
TCLCL
[4]
tBLSLBLSH BLS LOW to BLS HIGH time
-
(WST2 - WSTWEN +2) ×
-
ns
TCLCL
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] When the byte lane select signals are used to connect the write enable input (8 bit devices), tCSHBLSH = −0.5 × TCLCL
.
[3] When the byte lane select signals are used to connect the write enable input (8 bit devices), tCSLBLSL = tCSLWEL
[4] For 16 and 32 bit devices.
.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
72 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
t
t
CSHOEH
CSLAV
CS
A
t
t
h(D)
su(DQ)
D
t
CSLOEL
t
, t
OELAV BLSLAV
t
, t
OELOEH BLSLBLSH
OE/BLS
002aae687
Fig 27. External memory read access
t
t
CSHBLSH
CSLDV
CS
t
BLSLBLSH
BLS
t
CSLBLSL
t
t
CSLWEL
WELWEH
WE
t
WELDV
A
D
t
CSLDV
002aae688
Fig 28. External memory write access
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
73 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
9.6 Dynamic characteristics: ADC
Table 41. ADC dynamic characteristics
VDD(CORE) = VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to
ground.[1]
Symbol
fi(ADC)
Parameter
Conditions
Min
Typ
Max
Unit
[2]
ADC input frequency
maximum sampling rate
4
-
4.5
MHz
fs(max)
fi(ADC) = 4.5 MHz;
fs = fi(ADC)/(n + 1) with
n = resolution
resolution 2 bit
resolution 10 bit
-
-
-
-
1500
400
11
ksample/s
ksample/s
cycles
-
tconv
conversion time
In number of ADC
clock cycles
3
In number of bits
2
-
10
bits
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 85 °C ambient
temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] Duty cycle clock should be as close as possible to 50 %.
10. Application information
10.1 Operating frequency selection
The LPC2917/2919/01 is specified to operate at a maximum frequency of 125 MHz,
maximum temperature of 85 °C, and maximum core voltage of 1.89 V. Figure 29 and
Figure 30 show that the user can achieve higher operating frequencies for the
LPC2917/2919/01 by controlling the temperature and the core voltage accordingly.
002aae194
145
core
V
= 1.95 V
= 1.8 V
frequency
(MHz)
DD(CORE)
135
125
115
105
V
DD(CORE)
V
= 1.65 V
DD(CORE)
25
45
65
85
temperature (°C)
Fig 29. Core operating frequency versus temperature for different core voltages
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
74 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
002aae193
145
core
frequency
(MHz)
135
125
115
105
25 °C
45 °C
65 °C
85 °C
1.65
1.75
1.85
1.95
core voltage (V)
Fig 30. Core operating frequency versus core voltage for different temperatures
10.2 SPI signal forms
SCKn (CPOL = 0)
SCKn (CPOL = 1)
SDOn
MSB OUT
MSB IN
DATA VALID
DATA VALID
LSB OUT
LSB IN
CPHA = 1
SDIn
SDOn
MSB OUT
DATA VALID
LSB OUT
CPHA = 0
SDIn
MSB IN
DATA VALID
LSB IN
002aae693
Fig 31. SPI timing in master mode
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
75 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
SCKn (CPOL = 0)
SCKn (CPOL = 1)
SDIn
MSB IN
DATA VALID
DATA VALID
LSB IN
CPHA = 1
SDOn
MSB OUT
LSB OUT
SDIn
MSB IN
DATA VALID
LSB IN
CPHA = 0
SDOn
MSB OUT
DATA VALID
LSB OUT
002aae694
Fig 32. SPI timing in slave mode
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
76 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
10.3 XIN_OSC input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mVrms is needed. For more details see the LPC29xx User
manual UM10316.
LPC29xx
XIN_OSC
C
i
C
g
100 pF
002aae730
Fig 33. Slave mode operation of the on-chip oscillator
10.4 XIN_OSC Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in
case of third overtone crystal usage, have a common ground plane. The external
components must also be connected to the ground plain. Loops must be made as small
as possible, in order to keep the noise coupled in via the PCB as small as possible. Also
parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen
smaller accordingly to the increase in parasitics of the PCB layout.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
77 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
11. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
y
X
A
108
109
73
72
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v M
Z
A
w M
D
b
p
e
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 20.1
0.17 0.09 19.9 19.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-03-14
03-02-20
SOT486-1
136E23
MS-026
Fig 34. Package outline SOT486-1 (LQFP144)
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
78 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
79 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 35) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 42 and 43
Table 42. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 43. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 35.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
80 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 35. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
81 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
13. Abbreviations
Table 44. Abbreviations list
Abbreviation Description
AHB
AMBA
APB
BCL
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
ARM Peripheral Bus
Buffer Control List
BDL
Buffer Descriptor List
BEL
Buffer Entry List
BIST
CCO
CISC
DMA
DSP
DTL
Built-In Self Test
Current Controlled Oscillator
Complex Instruction Set Computers
Direct Memory Access
Digital Signal Processing
Device Transaction Level
Embedded Trace Buffer
ETB
ETM
FIQ
Embedded Trace Macrocell
Fast Interrupt reQuest
GPDMA
IRQ
General Purpose DMA
Interrupt Request
LIN
Local Interconnect Network
Media Access Control
MAC
PLL
Phase-Locked Loop
RISC
SFSP
SCL
Reduced Instruction Set Computer
SCU Function Select Port x,y (use without the P if there are no x,y)
Slot Control List
UART
Universal Asynchronous Receiver Transmitter
14. References
[1] UM10316 — LPC29xx user manual
[2] ARM — ARM web site
[3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference
manual
[4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1:
data link layer and physical signalling
[5] LIN — LIN specification package, revision 2.0
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
82 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
15. Revision history
Table 45. Revision history
Document ID
Release date
20090617
Data sheet status
Change notice
Supersedes
LPC2917_19_01_2
Modifications:
Preliminary data sheet
-
LPC2917_19_01_1
• Dynamic characteristics of CLKOUT pin added (Table 35).
• Flash/EEPROM endurance and retention characteristics updated (Table 38 and Table 39).
• Electrical pin characteristics added (Figure 21 to Figure 23).
• External static memory timing parameters and diagrams updated (Section 9.5. and
Figure 5 to Figure 7).
• SPI signal forms added (Figure 31 and Figure 32).
• SPI timing parameters and diagram updated (Section 9.3).
•
PCB layout guidelines added (Section 10.4).
• XIN_OSC circuit added (Section 10.3).
• IDD(CORE) conditions and value updated in Table 33.
• Dynamic characterization of CLKOUT pin added.
LPC2917_19_01_1
20090112
Preliminary data sheet
-
-
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
83 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
84 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
18. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
6.12
6.12.1
6.12.2
Peripheral subsystem. . . . . . . . . . . . . . . . . . . 28
Peripheral subsystem clock description . . . . . 28
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 28
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
4
6.12.2.1 Functional description . . . . . . . . . . . . . . . . . . 29
6.12.2.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 29
6.12.3
6.12.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12.3.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 30
6.12.4
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
5.1
5.2
5.2.1
5.2.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
General description. . . . . . . . . . . . . . . . . . . . . . 5
LQFP144 pin assignment . . . . . . . . . . . . . . . . . 5
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.12.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 31
6.12.4.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 31
6.12.5
Serial peripheral interface (SPI). . . . . . . . . . . 31
6
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
Functional description . . . . . . . . . . . . . . . . . . 11
Architectural overview. . . . . . . . . . . . . . . . . . . 11
ARM968E-S processor. . . . . . . . . . . . . . . . . . 12
On-chip flash memory system . . . . . . . . . . . . 13
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset, debug, test, and power description . . . 15
Reset and power-up behavior. . . . . . . . . . . . . 15
Reset strategy. . . . . . . . . . . . . . . . . . . . . . . . . 15
IEEE 1149.1 interface pins
6.12.5.1 Functional description . . . . . . . . . . . . . . . . . . 32
6.12.5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12.5.3 Clock description . . . . . . . . . . . . . . . . . . . . . . 33
6.12.6
General-purpose I/O . . . . . . . . . . . . . . . . . . . 33
6.12.6.1 Functional description . . . . . . . . . . . . . . . . . . 33
6.12.6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 33
6.12.6.3 Clock description . . . . . . . . . . . . . . . . . . . . . . 34
6.13
6.13.1
6.13.1.1 Global acceptance filter . . . . . . . . . . . . . . . . . 34
6.13.1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 34
6.13.2
6.13.2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 35
6.13.3
I2C-bus serial I/O controllers . . . . . . . . . . . . . 35
6.13.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 36
Networking subsystem. . . . . . . . . . . . . . . . . . 34
CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . 34
(JTAG boundary-scan test). . . . . . . . . . . . . . . 15
ETM/ETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply pins. . . . . . . . . . . . . . . . . . . . . . 16
Clocking strategy . . . . . . . . . . . . . . . . . . . . . . 16
Clock architecture. . . . . . . . . . . . . . . . . . . . . . 16
Base clock and branch clock relationship. . . . 18
Flash memory controller. . . . . . . . . . . . . . . . . 20
Functional description. . . . . . . . . . . . . . . . . . . 20
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock description . . . . . . . . . . . . . . . . . . . . . . 21
Flash layout. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash bridge wait-states . . . . . . . . . . . . . . . . . 22
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External static memory controller . . . . . . . . . . 23
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock description . . . . . . . . . . . . . . . . . . . . . . 24
External memory timing diagrams . . . . . . . . . 24
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 26
DMA support for peripherals. . . . . . . . . . . . . . 26
Clock description . . . . . . . . . . . . . . . . . . . . . . 27
General subsystem. . . . . . . . . . . . . . . . . . . . . 27
General subsystem clock description . . . . . . . 27
Chip and feature identification . . . . . . . . . . . . 27
System Control Unit (SCU). . . . . . . . . . . . . . . 27
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6.3.1
6.6.4
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.10
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.14
Modulation and sampling control subsystem . 36
Functional description . . . . . . . . . . . . . . . . . . 36
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 39
Clock description . . . . . . . . . . . . . . . . . . . . . . 39
Analog-to-digital converter . . . . . . . . . . . . . . . 39
6.14.1
6.14.2
6.14.3
6.14.4
6.14.4.1 Functional description . . . . . . . . . . . . . . . . . . 40
6.14.4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 40
6.14.4.3 Clock description . . . . . . . . . . . . . . . . . . . . . . 41
6.14.5
Pulse Width Modulator (PWM). . . . . . . . . . . . 41
6.14.5.1 Functional description . . . . . . . . . . . . . . . . . . 42
6.14.5.2 Synchronizing the PWM counters . . . . . . . . . 43
6.14.5.3 Master and slave mode . . . . . . . . . . . . . . . . . 43
6.14.5.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 43
6.14.5.5 Clock description . . . . . . . . . . . . . . . . . . . . . . 44
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.14.6
Timers in the MSCSS. . . . . . . . . . . . . . . . . . . 44
6.14.6.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 44
6.14.6.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 44
6.14.7
6.14.7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 45
6.14.7.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 45
6.15
Quadrature Encoder Interface (QEI) . . . . . . . 44
Power, clock and reset control subsystem . . . 45
6.11.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 28
continued >>
LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
85 of 86
LPC2917/01; LPC2919/01
NXP Semiconductors
ARM9 microcontroller with CAN and LIN
6.15.1
6.15.2
Clock description . . . . . . . . . . . . . . . . . . . . . . 46
Clock Generation Unit (CGU0) . . . . . . . . . . . . 47
16.1
16.2
16.3
16.4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 84
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.15.2.1 Functional description. . . . . . . . . . . . . . . . . . . 47
6.15.2.2 PLL functional description . . . . . . . . . . . . . . . 50
6.15.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 51
6.15.3
6.15.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 52
6.15.4 Reset Generation Unit (RGU). . . . . . . . . . . . . 52
17
18
Contact information . . . . . . . . . . . . . . . . . . . . 84
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Clock generation for CLK_OUT (CGU1). . . . . 51
6.15.4.1 Functional description. . . . . . . . . . . . . . . . . . . 52
6.15.4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 53
6.15.5
Power Management Unit (PMU). . . . . . . . . . . 53
6.15.5.1 Functional description. . . . . . . . . . . . . . . . . . . 54
6.16
6.16.1
6.16.2
Vectored Interrupt Controller (VIC) . . . . . . . . . 56
Functional description. . . . . . . . . . . . . . . . . . . 56
Clock description . . . . . . . . . . . . . . . . . . . . . . 57
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 58
8
8.1
8.2
Static characteristics. . . . . . . . . . . . . . . . . . . . 60
Power consumption . . . . . . . . . . . . . . . . . . . . 64
Electrical pin characteristics . . . . . . . . . . . . . . 66
9
9.1
Dynamic characteristics . . . . . . . . . . . . . . . . . 68
Dynamic characteristics: I/O pins,
internal clock, oscillators, PLL,
and CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Dynamic characteristics: I2C-bus
9.2
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Dynamic characteristics: SPI . . . . . . . . . . . . . 70
Dynamic characteristics:
9.3
9.4
flash memory and EEPROM. . . . . . . . . . . . . . 71
Dynamic characteristics:
external static memory . . . . . . . . . . . . . . . . . . 72
Dynamic characteristics:
9.5
9.6
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10
Application information. . . . . . . . . . . . . . . . . . 74
Operating frequency selection . . . . . . . . . . . . 74
SPI signal forms . . . . . . . . . . . . . . . . . . . . . . . 75
XIN_OSC input . . . . . . . . . . . . . . . . . . . . . . . . 77
XIN_OSC Printed Circuit Board
10.1
10.2
10.3
10.4
(PCB) layout guidelines . . . . . . . . . . . . . . . . . 77
11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78
12
Soldering of SMD packages . . . . . . . . . . . . . . 79
Introduction to soldering . . . . . . . . . . . . . . . . . 79
Wave and reflow soldering . . . . . . . . . . . . . . . 79
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 79
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 80
12.1
12.2
12.3
12.4
13
14
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 82
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 83
Legal information. . . . . . . . . . . . . . . . . . . . . . . 84
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 June 2009
Document identifier: LPC2917_19_01_2
相关型号:
©2020 ICPDF网 联系我们和版权申明