LPC435X [NXP]
32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC;型号: | LPC435X |
厂家: | NXP |
描述: | 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC CD 静态存储器 |
文件: | 总162页 (文件大小:7360K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC
Rev. 5.4 — 10 January 2020
Product data sheet
1. General description
The LPC435X_3X_2X_1X are ARM Cortex-M4 based microcontrollers with Floating Point
Unit (FPU) for embedded applications which include an ARM Cortex-M0 coprocessor, up
to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, two
high-speed USB controllers, Ethernet, LCD, an external memory controller, a quad SPI
Flash Interface (SPIFI) that supports execute-in-place, advanced configurable peripherals
such as the State Configurable Timer (SCTimer/PWM) and the Serial General Purpose
I/O (SGPIO) interface, and multiple digital and analog peripherals. The
LPC435X_3X_2X_1X operate at CPU frequencies of up to 204 MHz.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core,
which is upward code- and tool-compatible with the Cortex-M4 core. It is ideal for handling
control or peripheral handling to free up the Cortex-M4 for real-time processing. The
Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set
and reduced code size. In LPC43xx, the Cortex-M0 coprocessor hardware multiply is
implemented as a 32-cycle iterative multiplier.
For additional documentation related to the LPC43xx parts, see Section 17.
2. Features and benefits
Cortex-M4 Processor core
ARM Cortex-M4 processor (version r0p1), running at frequencies of up to
204 MHz.
Built-in Memory Protection Unit (MPU) supporting eight regions.
Built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four
watch points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Cortex-M0 Processor core
ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM
Cortex-M4 application processor.
Running at frequencies of up to 204 MHz.
JTAG
Built-in NVIC.
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
136 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64 kB ROM containing boot code and on-chip software drivers.
64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose
use.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCTimer/PWM) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
Up to two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One SPI controller.
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
One standard I2C-bus interface with monitor mode and with standard I/O pins.
Two I2S interfaces, each with DMA support and with one input and one output.
Digital peripherals
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
LPC435X_3X_2X_1X
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Product data sheet
Rev. 5.4 — 10 January 2020
2 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LCD controller with DMA support and a programmable display resolution of up to
1024 H 768 V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct
pixel mapping. Available on parts LPC4357/53 only.
Secure Digital Input Output (SD/MMC) card interface.
Eight-channel General-Purpose DMA controller can access all memories on the
AHB and all DMA-capable AHB slaves.
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
Four general-purpose timer/counters with capture and match capabilities.
One motor control Pulse Width Modulator (PWM) for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer (WWDT).
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
Analog peripherals
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
Unique ID for each device.
Clock generation unit
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and
voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).
Ultra-low power Real-Time Clock (RTC) crystal oscillator.
Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL can be used with the High-speed USB,
the third PLL can be used as audio PLL.
Clock output.
Power
Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip DC-to-DC converter for the
core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
LPC435X_3X_2X_1X
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Product data sheet
Rev. 5.4 — 10 January 2020
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available as LQFP208, LQFP144, LBGA256, or TFBGA100 packages.
3. Applications
Motor control
Embedded audio applications
Industrial automation
e-metering
Power management
White goods
RFID readers
LPC435X_3X_2X_1X
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Product data sheet
Rev. 5.4 — 10 January 2020
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC4357FET256 LBGA256
LPC4357JET256 LBGA256
LPC4357JBD208 LQFP208
LPC4353FET256 LBGA256
LPC4353JET256 LBGA256
LPC4353JBD208 LQFP208
LPC4337FET256 LBGA256
LPC4337JET256 LBGA256
LPC4337JBD144 LQFP144
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
SOT740-2
SOT740-2
SOT459-1
SOT740-2
SOT740-2
SOT459-1
SOT740-2
SOT740-2
SOT486-1
LPC4337JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4333FET256 LBGA256
LPC4333JET256 LBGA256
LPC4333JBD144 LQFP144
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
SOT740-2
SOT740-2
SOT486-1
LPC4333JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4327JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4327JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4325JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4325JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4323JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4323JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4322JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4322JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4317JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4317JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4315JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4315JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4313JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4313JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4312JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4312JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC435X_3X_2X_1X
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Product data sheet
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
LPC4357FET256 1 MB
LPC4357JET256 1 MB
LPC4357JBD208 1 MB
512 kB 512 kB 136 kB yes
512 kB 512 kB 136 kB yes
512 kB 512 kB 136 kB yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/no no
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/yes yes
yes yes yes/no no
yes
yes
yes
yes
yes
yes
yes
yes
no
8
8
8
8
8
8
8
8
8
4
8
8
8
4
8
4
8
4
8
4
8
4
8
4
8
4
8
4
8
4
F
J
J
F
J
J
F
J
J
J
F
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
164
164
142
164
164
142
164
164
83
LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes
LPC4353JET256 512 kB 256 kB 256 kB 136 kB yes
LPC4353JBD208 512 kB 256 kB 256 kB 136 kB yes
LPC4337FET256 1 MB
LPC4337JET256 1 MB
LPC4337JBD144 1 MB
LPC4337JET100 1 MB
512 kB 512 kB 136 kB no
512 kB 512 kB 136 kB no
512 kB 512 kB 136 kB no
512 kB 512 kB 136 kB no
no
49
LPC4333FET256 512 kB 256 kB 256 kB 136 kB no
LPC4333JET256 512 kB 256 kB 256 kB 136 kB no
LPC4333JBD144 512 kB 256 kB 256 kB 136 kB no
LPC4333JET100 512 kB 256 kB 256 kB 136 kB no
yes
yes
no
164
164
83
no
49
LPC4327JBD144 1 MB
LPC4327JET100 1 MB
512 kB 512 kB 136 kB no
512 kB 512 kB 136 kB no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
yes no/no
yes no/no
yes no/no
yes no/no
yes no/no
yes no/no
yes no/no
yes no/no
yes
no
no
83
no
49
LPC4325JBD144 768 kB 384 kB 384 kB 136 kB no
LPC4325JET100 768 kB 384 kB 384 kB 136 kB no
LPC4323JBD144 512 kB 256 kB 256 kB 104 kB no
LPC4323JET100 512 kB 256 kB 256 kB 104 kB no
yes
no
no
83
no
49
yes
no
no
83
no
49
LPC4322JBD144 512 kB 512 kB 0 kB
LPC4322JET100 512 kB 512 kB 0 kB
104 kB no
104 kB no
yes
no
no
83
no
49
LPC4317JBD144 1 MB
LPC4317JET100 1 MB
512 kB 512 kB 136 kB no
512 kB 512 kB 136 kB no
no
no
no
no
no
no
no
no
no/no
no/no
no/no
no/no
no/no
no/no
no/no
no/no
yes
no
no
83
no
49
LPC4315JBD144 768 kB 384 kB 384 kB 136 kB no
LPC4315JET100 768 kB 384 kB 384 kB 136 kB no
LPC4313JBD144 512 kB 256 kB 256 kB 104 kB no
LPC4313JET100 512 kB 256 kB 256 kB 104 kB no
yes
no
no
83
no
49
yes
no
no
83
no
49
LPC4312JBD144 512 kB 512 kB 0 kB
LPC4312JET100 512 kB 512 kB 0 kB
104 kB no
104 kB no
yes
no
no
83
no
49
[1] J = -40 °C to +105 °C; F = -40 °C to +85 °C.
LPC435X_3X_2X_1X
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Product data sheet
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
LPC435x/3x/2/1x
TEST/DEBUG
INTERFACE
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
HIGH-SPEED PHY
HIGH-SPEED
ARM
CORTEX-M4F
(1)
ETHERNET
10/100
HIGH-SPEED
(1)
SD/
MMC
USB0
(1)
(1)
LCD
USB1
DMA
MAC
HOST/
DEVICE/OTG
HOST/DEVICE
IEEE 1588
masters
slaves
BRIDGE
AHB MULTILAYER MATRIX
SPI
SGPIO
slaves
64 kB ROM
BRIDGE 0
BRIDGE 1
BRIDGE 2
BRIDGE 3
BRIDGE
BRIDGE
32 kB LOCAL SRAM
40 kB LOCAL SRAM
2
RI TIMER
USART2
USART3
TIMER2
TIMER3
SSP1
I C1
CGU
CCU1
CCU2
RGU
ALARM TIMER
WWDT
MOTOR
CONTROL
32 kB AHB SRAM
(1)
BACKUP REGISTERS
POWER MODE CONTROL
USART0
10-bit DAC
C_CAN0
PWM
16 kB +
16 kB AHB SRAM
2
I C0
UART1
SSP0
2
I S0
10-bit ADC0
10-bit ADC1
CONFIGURATION
REGISTERS
16 kB EEPROM
512/256 kB FLASH A
2
I S1
TIMER0
EVENT ROUTER
OTP MEMORY
512/256 kB FLASH B
C_CAN1
TIMER1
SCU
SCT
(1)
QEI
RTC
RTC OSC
12 MHz IRC
RTC POWER DOMAIN
EMC
HS GPIO
SPIFI
GIMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
= connected to DMA
002aah234
(1) Not available on all parts. See Table 2.
Fig 1. LPC435x/3x/2x/1x Block diagram
LPC435X_3X_2X_1X
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Product data sheet
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
6. Pinning information
6.1 Pinning
LPC435x/3xFET256
ball A1
index area
ball A1
index area
LPC433x/2x/1xFET100
2
4
6
8
10 12 14 16
11 13 15
1
3
5
7
9
1
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
002aah177
002aah179
Transparent top view
Transparent top view
Fig 2. Pin configuration LBGA256 package
Fig 3. Pin configuration TFBGA100 package
157
208
104
109
144
72
LPC4357/53FBD208
LPC433x/2x/1xFBD144
37
53
002aah180
002aah181
Fig 4. Pin configuration LQFP208 package
Fig 5. Pin configuration LQFP144 package
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
6.2 Pin description
On the LPC435x/3x/2x/1x, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin can support up to eight different
digital functions, including General Purpose I/O (GPIO), selectable through the System
Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port
assigned to it.
The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and
ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel
0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel
0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are
tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are
eight ADC channels total for the two ADCs.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description
Pin name
Description
Multiplexed digital pins
[2]
P0_0
L3
G2
47
32
N;
PU
I/O GPIO0[0] — General purpose digital input/output pin.
I/O SSP1_MISO — Master In Slave Out for SSP1.
I
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
I/O SGPIO0 — General purpose digital input/output pin.
-
-
R — Function reserved.
R — Function reserved.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
[2]
P0_1
M2
G1
50
34
N;
PU
I/O GPIO0[1] — General purpose digital input/output pin.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
I
ENET_COL — Ethernet Collision detect (MII interface).
I/O SGPIO1 — General purpose digital input/output pin.
-
-
R — Function reserved.
R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
[2]
P1_0
P2
H1
54
38
N;
I/O GPIO0[4] — General purpose digital input/output pin.
PU
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
I/O EMC_A5 — External memory address line 5.
-
-
R — Function reserved.
R — Function reserved.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SGPIO7 — General purpose digital input/output pin.
I/O EMC_D12 — External memory data line 12.
LPC435X_3X_2X_1X
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Product data sheet
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
P1_1
P1_2
P1_3
P1_4
R2
R3
P5
T3
K2
K1
J1
J2
58
60
61
64
42
43
44
47
N;
PU
I/O GPIO0[8] — General purpose digital input/output pin. Boot
pin (see Table 5).
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O EMC_A6 — External memory address line 6.
I/O SGPIO8 — General purpose digital input/output pin.
-
R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
R — Function reserved.
-
I/O EMC_D13 — External memory data line 13.
N;
PU
I/O GPIO0[9] — General purpose digital input/output pin. Boot
pin (see Table 5).
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I/O EMC_A7 — External memory address line 7.
I/O SGPIO9 — General purpose digital input/output pin.
-
R — Function reserved.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
R — Function reserved.
-
I/O EMC_D14 — External memory data line 14.
N;
PU
I/O GPIO0[10] — General purpose digital input/output pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
I/O SGPIO10 — General purpose digital input/output pin.
O
O
EMC_OE — LOW active Output Enable signal.
USB0_IND1 — USB0 port indicator LED control
output 1.
I/O SSP1_MISO — Master In Slave Out for SSP1.
-
R — Function reserved.
O
SD_RST — SD/MMC reset signal for MMC4.4 card.
N;
PU
I/O GPIO0[11] — General purpose digital input/output pin.
CTOUT_9 — SCT output 9. Match output 3 of timer 3.
I/O SGPIO11 — General purpose digital input/output pin.
O
O
O
EMC_BLS0 — LOW active Byte Lane select signal 0.
USB0_IND0 — USB0 port indicator LED control output 0.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
I/O EMC_D15 — External memory data line 15.
O
SD_VOLT1 — SD/MMC bus voltage select output 1.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P1_5
R5
J4
65
48
N;
I/O GPIO1[8] — General purpose digital input/output pin.
PU
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.
R — Function reserved.
O
I
EMC_CS0 — LOW active Chip Select 0 signal.
USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on
the USB bus (external circuitry required to detect
over-current condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
O
SD_POW — SD/MMC power monitor output.
[2]
P1_6
T4
K4
67
49
N;
I/O GPIO1[9] — General purpose digital input/output pin.
PU
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
R — Function reserved.
-
O
-
EMC_WE — LOW active Write Enable signal.
R — Function reserved.
O
EMC_BLS0 — LOW active Byte Lane select signal 0.
I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
[2]
P1_7
T5
G4
69
50
N;
I/O GPIO1[0] — General purpose digital input/output pin.
PU
I
U1_DSR — Data Set Ready input for UART1.
O
CTOUT_13 — SCT output 13. Match output 3 of timer 3.
I/O EMC_D0 — External memory data line 0.
O
USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that
VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P1_8
R7
H5
71
51
N;
I/O GPIO1[1] — General purpose digital input/output pin.
PU
O
O
U1_DTR — Data Terminal Ready output for UART1.
CTOUT_12 — SCT output 12. Match output 3 of
timer 3.
I/O EMC_D1 — External memory data line 1.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
SD_VOLT0 — SD/MMC bus voltage select output 0.
[2]
[2]
[2]
P1_9
T7
R8
T9
J5
H6
J7
73
75
77
52
53
55
N;
PU
I/O GPIO1[2] — General purpose digital input/output pin.
O
O
U1_RTS — Request to Send output for UART1.
CTOUT_11 — SCT output 11. Match output 3 of timer 2.
I/O EMC_D2 — External memory data line 2.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O SD_DAT0 — SD/MMC data bus line 0.
P1_10
N;
PU
I/O GPIO1[3] — General purpose digital input/output pin.
I
U1_RI — Ring Indicator input for UART1.
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O EMC_D3 — External memory data line 3.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O SD_DAT1 — SD/MMC data bus line 1.
P1_11
N;
I/O GPIO1[4] — General purpose digital input/output pin.
PU
I
U1_CTS — Clear to Send input for UART1.
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O EMC_D4 — External memory data line 4.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O SD_DAT2 — SD/MMC data bus line 2.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
P1_12
P1_13
P1_14
P1_15
R9
K7
78
83
85
87
56
60
61
62
N;
PU
I/O GPIO1[5] — General purpose digital input/output pin.
I
U1_DCD — Data Carrier Detect input for UART1.
R — Function reserved.
-
I/O EMC_D5 — External memory data line 5.
I
T0_CAP1 — Capture input 1 of timer 0.
R — Function reserved.
-
I/O SGPIO8 — General purpose digital input/output pin.
I/O SD_DAT3 — SD/MMC data bus line 3.
R10 H8
R11 J8
T12 K8
N;
PU
I/O GPIO1[6] — General purpose digital input/output pin.
O
-
U1_TXD — Transmitter output for UART1.
R — Function reserved.
I/O EMC_D6 — External memory data line 6.
I
T0_CAP0 — Capture input 0 of timer 0.
R — Function reserved.
-
I/O SGPIO9 — General purpose digital input/output pin.
SD_CD — SD/MMC card detect input.
I/O GPIO1[7] — General purpose digital input/output pin.
I
N;
PU
I
U1_RXD — Receiver input for UART1.
R — Function reserved.
-
I/O EMC_D7 — External memory data line 7.
O
-
T0_MAT2 — Match output 2 of timer 0.
R — Function reserved.
I/O SGPIO10 — General purpose digital input/output pin.
R — Function reserved.
I/O GPIO0[2] — General purpose digital input/output pin.
U2_TXD — Transmitter output for USART2.
I/O SGPIO2 — General purpose digital input/output pin.
-
N;
PU
O
I
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
T0_MAT1 — Match output 1 of timer 0.
R — Function reserved.
O
-
I/O EMC_D8 — External memory data line 8.
R — Function reserved.
-
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[3]
[2]
P1_16
P1_17
P1_18
M7
H9
90
64
66
67
N;
PU
I/O GPIO0[3] — General purpose digital input/output pin.
U2_RXD — Receiver input for USART2.
I/O SGPIO3 — General purpose digital input/output pin.
I
I
ENET_CRS — Ethernet Carrier Sense (MII interface).
T0_MAT0 — Match output 0 of timer 0.
R — Function reserved.
O
-
I/O EMC_D9 — External memory data line 9.
I
ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).
M8
H10 93
N;
PU
I/O GPIO0[12] — General purpose digital input/output pin.
I/O U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
-
R — Function reserved.
I/O ENET_MDIO — Ethernet MIIM data input and output.
I
T0_CAP3 — Capture input 3 of timer 0.
CAN1_TD — CAN1 transmitter output.
O
I/O SGPIO11 — General purpose digital input/output pin.
R — Function reserved.
-
N12 J10
95
N;
I/O GPIO0[13] — General purpose digital input/output pin.
PU
I/O U2_DIR — RS-485/EIA-485 output enable/direction control
for USART2.
-
R — Function reserved.
O
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII
interface).
O
I
T0_MAT3 — Match output 3 of timer 0.
CAN1_RD — CAN1 receiver input.
I/O SGPIO12 — General purpose digital input/output pin.
I/O EMC_D10 — External memory data line 10.
[2]
P1_19
M11 K9
96
68
N;
PU
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).
I/O SSP1_SCK — Serial clock for SSP1.
-
R — Function reserved.
-
R — Function reserved.
O
-
CLKOUT — Clock output pin.
R — Function reserved.
O
I2S0_RX_MCLK — I2S receive master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P1_20
M10 K10 100 70
N;
PU
I/O GPIO0[15] — General purpose digital input/output pin.
I/O SSP1_SSEL — Slave Select for SSP1.
-
R — Function reserved.
O
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII
interface).
I
T0_CAP2 — Capture input 2 of timer 0.
R — Function reserved.
-
I/O SGPIO13 — General purpose digital input/output pin.
I/O EMC_D11 — External memory data line 11.
[2]
P2_0
T16 G10 108 75
N;
I/O SGPIO4 — General purpose digital input/output pin.
PU
O
U0_TXD — Transmitter output for USART0. See Table 4 for
ISP mode.
I/O EMC_A13 — External memory address line 13.
O
USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that
VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
I/O GPIO5[0] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP0 — Capture input 0 of timer 3.
ENET_MDC — Ethernet MIIM clock.
O
[2]
P2_1
N15 G7
116 81
N;
I/O SGPIO5 — General purpose digital input/output pin.
PU
I
U0_RXD — Receiver input for USART0. See Table 4 for ISP
mode.
I/O EMC_A12 — External memory address line 12.
I
USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on
the USB bus (external circuitry required to detect
over-current condition).
I/O GPIO5[1] — General purpose digital input/output pin.
-
I
R — Function reserved.
T3_CAP1 — Capture input 1 of timer 3.
R — Function reserved.
-
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P2_2
M15 F5
121 84
N;
I/O SGPIO6 — General purpose digital input/output pin.
PU
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O EMC_A11 — External memory address line 11.
O
USB0_IND1 — USB0 port indicator LED control output 1.
I/O GPIO5[2] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
T3_CAP2 — Capture input 2 of timer 3.
I
O
EMC_CS1 — LOW active Chip Select 1 signal.
[3]
P2_3
J12 D8
127 87
N;
I/O SGPIO12 — General purpose digital input/output pin.
PU
I/O I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).
O
I
U3_TXD — Transmitter output for USART3. See Table 4 for
ISP mode.
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.
I/O GPIO5[3] — General purpose digital input/output pin.
-
R — Function reserved.
O
O
T3_MAT0 — Match output 0 of timer 3.
USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that
VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
[3]
P2_4
K11 D9
128 88
N;
I/O SGPIO13 — General purpose digital input/output pin.
PU
I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).
I
U3_RXD — Receiver input for USART3. See Table 4 for ISP
mode.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
I/O GPIO5[4] — General purpose digital input/output pin.
-
R — Function reserved.
O
I
T3_MAT1 — Match output 1 of timer 3.
USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on
the USB bus (external circuitry required to detect
over-current condition).
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[3]
P2_5
K14 D10 131 91
N;
I/O SGPIO14 — General purpose digital input/output pin.
PU
I
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.
ADCTRIG1 — ADC trigger input 1.
I
I/O GPIO5[5] — General purpose digital input/output pin.
-
R — Function reserved.
O
O
T3_MAT2 — Match output 2 of timer 3.
USB0_IND0 — USB0 port indicator LED control output 0.
[2]
P2_6
K16 G9
137 95
N;
I/O SGPIO7 — General purpose digital input/output pin.
PU
I/O U0_DIR — RS-485/EIA-485 output enable/direction control
for USART0.
I/O EMC_A10 — External memory address line 10.
O
USB0_IND0 — USB0 port indicator LED control
output 0.
I/O GPIO5[6] — General purpose digital input/output pin.
I
CTIN_7 — SCT input 7.
I
T3_CAP3 — Capture input 3 of timer 3.
EMC_BLS1 — LOW active Byte Lane select signal 1.
O
[2]
P2_7
H14 C10 138 96
N;
PU
I/O GPIO0[7] — General purpose digital input/output pin. If this
pin is pulled LOW at reset, the part enters ISP mode or boots
from an external source (see Table 4 and Table 5).
O
CTOUT_1 — SCT output 1. Match output 3 of timer 3.
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O EMC_A9 — External memory address line 9.
-
R — Function reserved.
-
R — Function reserved.
O
-
T3_MAT3 — Match output 3 of timer 3.
R — Function reserved.
[2]
P2_8
J16 C6
140 98
N;
I/O SGPIO15 — General purpose digital input/output pin. Boot
PU
pin (see Table 5).
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control
for USART3.
I/O EMC_A8 — External memory address line 8.
I/O GPIO5[7] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P2_9
H16 B10 144 102
N;
I/O GPIO1[10] — General purpose digital input/output pin. Boot
PU
pin (see Table 5).
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
I/O U3_BAUD — Baud pin for USART3.
I/O EMC_A0 — External memory address line 0.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
[2]
[2]
[2]
P2_10
P2_11
P2_12
G16 E8
F16 A9
E15 B9
146 104
148 105
153 106
N;
PU
I/O GPIO0[14] — General purpose digital input/output pin.
O
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
U2_TXD — Transmitter output for USART2.
I/O EMC_A1 — External memory address line 1.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
I/O GPIO1[11] — General purpose digital input/output pin.
O
I
CTOUT_5 — SCT output 5. Match output 3 of timer 3.
U2_RXD — Receiver input for USART2.
I/O EMC_A2 — External memory address line 2.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
I/O GPIO1[12] — General purpose digital input/output pin.
PU
O
-
CTOUT_4 — SCT output 4. Match output 3 of timer 3.
R — Function reserved.
I/O EMC_A3 — External memory address line 3.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P2_13
C16 A10 156 108
N;
I/O GPIO1[13] — General purpose digital input/output pin.
PU
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
R — Function reserved.
-
I/O EMC_A4 — External memory address line 4.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O U2_DIR — RS-485/EIA-485 output enable/direction control
for USART2.
[2]
P3_0
F13 A8
161 112
N;
PU
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the
master and received by the slave. Corresponds to the signal
SCK in the I2S-bus specification.
O
I2S0_RX_MCLK — I2S receive master clock.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O SSP0_SCK — Serial clock for SSP0.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
[2]
P3_1
G11 F7
163 114
N;
PU
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I
CAN0_RD — CAN receiver input.
O
USB1_IND1 — USB1 Port indicator LED control output 1.
I/O GPIO5[8] — General purpose digital input/output pin.
-
R — Function reserved.
LCD_VD15 — LCD data.
R — Function reserved.
O
-
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P3_2
F11 G6
166 116
OL; I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
PU
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
O
O
CAN0_TD — CAN transmitter output.
USB1_IND0 — USB1 Port indicator LED control output 0.
I/O GPIO5[9] — General purpose digital input/output pin.
-
R — Function reserved.
LCD_VD14 — LCD data.
R — Function reserved.
R — Function reserved.
O
-
[4]
P3_3
B14 A7
169 118
N;
-
PU
I/O SPI_SCK — Serial clock for SPI.
I/O SSP0_SCK — Serial clock for SSP0.
O
O
-
SPIFI_SCK — Serial clock for SPIFI.
CGU_OUT1 — CGU spare clock output 1.
R — Function reserved.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
[2]
P3_4
A15 B8
171 119
N;
I/O GPIO1[14] — General purpose digital input/output pin.
PU
-
-
R — Function reserved.
R — Function reserved.
I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.
U1_TXD — Transmitter output for UART 1.
O
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
O
LCD_VD13 — LCD data.
LPC435X_3X_2X_1X
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Product data sheet
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21 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P3_5
C12 B7
173 121
N;
I/O GPIO1[15] — General purpose digital input/output pin.
PU
-
-
R — Function reserved.
R — Function reserved.
I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.
U1_RXD — Receiver input for UART 1.
I
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O I2S1_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
O
LCD_VD12 — LCD data.
[2]
[2]
[2]
P3_6
P3_7
P3_8
B13 C7
C11 D7
C10 E7
174 122
176 123
179 124
N;
PU
I/O GPIO0[6] — General purpose digital input/output pin.
I/O SPI_MISO — Master In Slave Out for SPI.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output
IO1.
-
R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
I/O SPI_MOSI — Master Out Slave In for SPI.
I/O SSP0_MISO — Master In Slave Out for SSP0.
I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output
IO0.
I/O GPIO5[10] — General purpose digital input/output pin.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
-
-
-
I
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
SPI_SSEL — Slave Select for SPI. Note that this pin in an
input pin only. The SPI in master mode cannot drive the CS
input on the slave. Any GPIO pin can be used for SPI chip
select in master mode.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
I/O SPIFI_CS — SPIFI serial flash chip select.
I/O GPIO5[11] — General purpose digital input/output pin.
I/O SSP0_SSEL — Slave Select for SSP0.
-
-
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P4_0
D5
-
1
1
N;
I/O GPIO2[0] — General purpose digital input/output pin.
PU
O
I
MCOA0 — Motor control PWM channel 0, output A.
NMI — External interrupt input to NMI.
R — Function reserved.
-
-
R — Function reserved.
O
LCD_VD13 — LCD data.
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
-
R — Function reserved.
[5]
P4_1
A1
-
3
3
N;
I/O GPIO2[1] — General purpose digital input/output pin.
PU
O
O
-
CTOUT_1 — SCT output 1. Match output 3 of timer 3.
LCD_VD0 — LCD data.
R — Function reserved.
-
R — Function reserved.
O
O
I
LCD_VD19 — LCD data.
U3_TXD — Transmitter output for USART3.
ENET_COL — Ethernet Collision detect (MII interface).
AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[2]
P4_2
D3
-
12
8
N;
I/O GPIO2[2] — General purpose digital input/output pin.
PU
O
O
-
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
LCD_VD3 — LCD data.
R — Function reserved.
-
R — Function reserved.
O
I
LCD_VD12 — LCD data.
U3_RXD — Receiver input for USART3.
I/O SGPIO8 — General purpose digital input/output pin.
I/O GPIO2[3] — General purpose digital input/output pin.
[5]
P4_3
C2
-
10
7
N;
PU
O
O
-
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
LCD_VD2 — LCD data.
R — Function reserved.
-
R — Function reserved.
O
LCD_VD21 — LCD data.
I/O U3_BAUD — Baud pin for USART3.
I/O SGPIO9 — General purpose digital input/output pin.
AI ADC0_0 — DAC, ADC0 and ADC1, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[5]
P4_4
B1
-
14
9
N;
I/O GPIO2[4] — General purpose digital input/output pin.
PU
O
O
-
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
LCD_VD1 — LCD data.
R — Function reserved.
-
R — Function reserved.
O
LCD_VD20 — LCD data.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control
for USART3.
I/O SGPIO10 — General purpose digital input/output pin.
O
DAC — DAC output. Configure the pin as GPIO input and
use the analog function select register in the SCU to select
the DAC.
[2]
P4_5
D2
-
15
10
N;
I/O GPIO2[5] — General purpose digital input/output pin.
PU
O
O
CTOUT_5 — SCT output 5. Match output 3 of timer 3.
LCD_FP — Frame pulse (STN). Vertical synchronization
pulse (TFT).
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O SGPIO11 — General purpose digital input/output pin.
I/O GPIO2[6] — General purpose digital input/output pin.
[2]
P4_6
C1
-
17
11
N;
PU
O
O
CTOUT_4 — SCT output 4. Match output 3 of timer 3.
LCD_ENAB/LCDM — STN AC bias drive or TFT data
enable input.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
I/O SGPIO12 — General purpose digital input/output pin.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P4_7
H4
-
21
14
O;
PU
O
I
LCD_DCLK — LCD panel clock.
GP_CLKIN — General purpose clock input to the CGU.
R — Function reserved.
-
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
[2]
[2]
[2]
P4_8
P4_9
P4_10
E2
-
-
-
23
48
51
15
33
35
N;
PU
-
R — Function reserved.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
LCD_VD9 — LCD data.
O
-
R — Function reserved.
I/O GPIO5[12] — General purpose digital input/output pin.
O
O
LCD_VD22 — LCD data.
CAN1_TD — CAN1 transmitter output.
I/O SGPIO13 — General purpose digital input/output pin.
L2
N;
PU
-
R — Function reserved.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
LCD_VD11 — LCD data.
O
-
R — Function reserved.
I/O GPIO5[13] — General purpose digital input/output pin.
O
I
LCD_VD15 — LCD data.
CAN1_RD — CAN1 receiver input.
I/O SGPIO14 — General purpose digital input/output pin.
M3
N;
-
R — Function reserved.
PU
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
LCD_VD10 — LCD data.
O
-
R — Function reserved.
I/O GPIO5[14] — General purpose digital input/output pin.
O
-
LCD_VD14 — LCD data.
R — Function reserved.
I/O SGPIO15 — General purpose digital input/output pin.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P5_0
N3
-
53
37
N;
PU
I/O GPIO2[9] — General purpose digital input/output pin.
MCOB2 — Motor control PWM channel 2, output B.
I/O EMC_D12 — External memory data line 12.
O
-
I
R — Function reserved.
U1_DSR — Data Set Ready input for UART 1.
T1_CAP0 — Capture input 0 of timer 1.
R — Function reserved.
I
-
-
R — Function reserved.
[2]
P5_1
P3
-
55
39
N;
PU
I/O GPIO2[10] — General purpose digital input/output pin.
MCI2 — Motor control PWM channel 2, input.
I/O EMC_D13 — External memory data line 13.
I
-
R — Function reserved.
O
U1_DTR — Data Terminal Ready output for UART 1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART 1.
I
T1_CAP1 — Capture input 1 of timer 1.
R — Function reserved.
-
-
R — Function reserved.
[2]
P5_2
R4
-
63
46
N;
PU
I/O GPIO2[11] — General purpose digital input/output pin.
MCI1 — Motor control PWM channel 1, input.
I/O EMC_D14 — External memory data line 14.
I
-
R — Function reserved.
O
U1_RTS — Request to Send output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
I
T1_CAP2 — Capture input 2 of timer 1.
R — Function reserved.
-
-
R — Function reserved.
[2]
P5_3
T8
-
76
54
N;
PU
I/O GPIO2[12] — General purpose digital input/output pin.
MCI0 — Motor control PWM channel 0, input.
I/O EMC_D15 — External memory data line 15.
I
-
I
R — Function reserved.
U1_RI — Ring Indicator input for UART 1.
T1_CAP3 — Capture input 3 of timer 1.
R — Function reserved.
I
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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Product data sheet
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26 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
P5_4
P5_5
P5_6
P5_7
P9
-
-
-
-
80
81
89
91
57
58
63
65
N;
PU
I/O GPIO2[13] — General purpose digital input/output pin.
MCOB0 — Motor control PWM channel 0, output B.
I/O EMC_D8 — External memory data line 8.
O
-
R — Function reserved.
I
U1_CTS — Clear to Send input for UART 1.
T1_MAT0 — Match output 0 of timer 1.
R — Function reserved.
O
-
-
R — Function reserved.
P10
T13
R12
N;
PU
I/O GPIO2[14] — General purpose digital input/output pin.
MCOA1 — Motor control PWM channel 1, output A.
I/O EMC_D9 — External memory data line 9.
O
-
R — Function reserved.
I
U1_DCD — Data Carrier Detect input for UART 1.
T1_MAT1 — Match output 1 of timer 1.
R — Function reserved.
O
-
-
R — Function reserved.
N;
PU
I/O GPIO2[15] — General purpose digital input/output pin.
MCOB1 — Motor control PWM channel 1, output B.
I/O EMC_D10 — External memory data line 10.
O
-
R — Function reserved.
O
O
-
U1_TXD — Transmitter output for UART 1.
T1_MAT2 — Match output 2 of timer 1.
R — Function reserved.
-
R — Function reserved.
N;
PU
I/O GPIO2[7] — General purpose digital input/output pin.
MCOA2 — Motor control PWM channel 2, output A.
I/O EMC_D11 — External memory data line 11.
O
-
R — Function reserved.
I
U1_RXD — Receiver input for UART 1.
T1_MAT3 — Match output 3 of timer 1.
R — Function reserved.
O
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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Product data sheet
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27 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P6_0
M12 H7
105 73
N;
-
R — Function reserved.
PU
O
-
I2S0_RX_MCLK — I2S receive master clock.
R — Function reserved.
-
R — Function reserved.
I/O I2S0_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
[2]
P6_1
R15 G5
107 74
N;
PU
I/O GPIO3[0] — General purpose digital input/output pin.
EMC_DYCS1 — SDRAM chip select 1.
O
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
-
I
R — Function reserved.
T2_CAP0 — Capture input 2 of timer 2.
R — Function reserved.
-
-
R — Function reserved.
[2]
P6_2
L13 J9
111 78
N;
PU
I/O GPIO3[1] — General purpose digital input/output pin.
EMC_CKEOUT1 — SDRAM clock enable 1.
O
I/O U0_DIR — RS-485/EIA-485 output enable/direction control
for USART0.
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
-
I
R — Function reserved.
T2_CAP1 — Capture input 1 of timer 2.
R — Function reserved.
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P6_3
P15
-
113 79
N;
I/O GPIO3[2] — General purpose digital input/output pin.
PU
O
USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that the
VBUS signal must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
I/O SGPIO4 — General purpose digital input/output pin.
O
-
EMC_CS1 — LOW active Chip Select 1 signal.
R — Function reserved.
I
T2_CAP2 — Capture input 2 of timer 2.
R — Function reserved.
-
-
R — Function reserved.
[2]
[2]
[2]
P6_4
P6_5
P6_6
R16 F6
114 80
117 82
119 83
N;
PU
I/O GPIO3[3] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
U0_TXD — Transmitter output for USART0.
EMC_CAS — LOW active SDRAM Column Address Strobe.
R — Function reserved.
O
O
-
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
P16 F9
N;
PU
I/O GPIO3[4] — General purpose digital input/output pin.
O
I
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
U0_RXD — Receiver input for USART0.
EMC_RAS — LOW active SDRAM Row Address Strobe.
R — Function reserved.
O
-
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
L14
-
N;
PU
I/O GPIO0[5] — General purpose digital input/output pin.
EMC_BLS1 — LOW active Byte Lane select signal 1.
I/O SGPIO5 — General purpose digital input/output pin.
O
I
USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on
the USB bus (external circuitry required to detect
over-current condition).
-
I
R — Function reserved.
T2_CAP3 — Capture input 3 of timer 2.
R — Function reserved.
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
P6_7
P6_8
P6_9
P6_10
J13
-
123 85
125 86
139 97
142 100
N;
PU
-
R — Function reserved.
I/O EMC_A15 — External memory address line 15.
I/O SGPIO6 — General purpose digital input/output pin.
O
USB0_IND1 — USB0 port indicator LED control output 1.
I/O GPIO5[15] — General purpose digital input/output pin.
O
-
T2_MAT0 — Match output 0 of timer 2.
R — Function reserved.
-
R — Function reserved.
H13
-
N;
PU
-
R — Function reserved.
I/O EMC_A14 — External memory address line 14.
I/O SGPIO7 — General purpose digital input/output pin.
O
USB0_IND0 — USB0 port indicator LED control output 0.
I/O GPIO5[16] — General purpose digital input/output pin.
O
-
T2_MAT1 — Match output 1 of timer 2.
R — Function reserved.
-
R — Function reserved.
J15 F8
N;
PU
I/O GPIO3[5] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
-
EMC_DYCS0 — SDRAM chip select 0.
R — Function reserved.
O
-
T2_MAT2 — Match output 2 of timer 2.
R — Function reserved.
-
R — Function reserved.
H15
-
N;
I/O GPIO3[6] — General purpose digital input/output pin.
PU
O
-
MCABORT — Motor control PWM, LOW-active fast abort.
R — Function reserved.
O
EMC_DQMOUT1 — Data mask 1 used with SDRAM and
static devices.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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30 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P6_11
H12 C9
143 101
N;
I/O GPIO3[7] — General purpose digital input/output pin.
PU
-
R — Function reserved.
-
R — Function reserved.
O
-
EMC_CKEOUT0 — SDRAM clock enable 0.
R — Function reserved.
O
-
T2_MAT3 — Match output 3 of timer 2.
R — Function reserved.
-
R — Function reserved.
[2]
P6_12
G15
-
145 103
N;
I/O GPIO2[8] — General purpose digital input/output pin.
PU
O
-
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
R — Function reserved.
O
EMC_DQMOUT0 — Data mask 0 used with SDRAM and
static devices.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
[2]
P7_0
B16
-
158 110
N;
I/O GPIO3[8] — General purpose digital input/output pin.
PU
O
-
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
R — Function reserved.
O
-
LCD_LE — Line end signal.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
I/O GPIO3[9] — General purpose digital input/output pin.
[2]
P7_1
C14
-
162 113
N;
PU
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
O
O
-
LCD_VD19 — LCD data.
LCD_VD7 — LCD data.
R — Function reserved.
O
U2_TXD — Transmitter output for USART2.
I/O SGPIO5 — General purpose digital input/output pin.
LPC435X_3X_2X_1X
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Product data sheet
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31 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P7_2
A16
-
165 115
N;
PU
I/O GPIO3[10] — General purpose digital input/output pin.
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
I
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
O
O
-
LCD_VD18 — LCD data.
LCD_VD6 — LCD data.
R — Function reserved.
I
U2_RXD — Receiver input for USART2.
I/O SGPIO6 — General purpose digital input/output pin.
I/O GPIO3[11] — General purpose digital input/output pin.
[2]
P7_3
C13
-
167 117
N;
PU
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
R — Function reserved.
-
O
O
-
LCD_VD17 — LCD data.
LCD_VD5 — LCD data.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
[5]
P7_4
C8
-
189 132
N;
I/O GPIO3[12] — General purpose digital input/output pin.
PU
O
-
CTOUT_13 — SCT output 13. Match output 3 of timer 3.
R — Function reserved.
O
O
O
-
LCD_VD16 — LCD data.
LCD_VD4 — LCD data.
TRACEDATA[0] — Trace data, bit 0.
R — Function reserved.
-
R — Function reserved.
AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[5]
P7_5
A7
-
191 133
N;
I/O GPIO3[13] — General purpose digital input/output pin.
PU
O
-
CTOUT_12 — SCT output 12. Match output 3 of timer 3.
R — Function reserved.
O
O
O
-
LCD_VD8 — LCD data.
LCD_VD23 — LCD data.
TRACEDATA[1] — Trace data, bit 1.
R — Function reserved.
-
R — Function reserved.
AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P7_6
C7
-
194 134
N;
I/O GPIO3[14] — General purpose digital input/output pin.
PU
O
-
CTOUT_11 — SCT output 1. Match output 3 of timer 2.
R — Function reserved.
O
LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
-
R — Function reserved.
O
-
TRACEDATA[2] — Trace data, bit 2.
R — Function reserved.
-
R — Function reserved.
[5]
P7_7
B6
-
201 140
N;
I/O GPIO3[15] — General purpose digital input/output pin.
PU
O
-
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
R — Function reserved.
O
-
LCD_PWR — LCD panel power enable.
R — Function reserved.
O
O
TRACEDATA[3] — Trace data, bit 3.
ENET_MDC — Ethernet MIIM clock.
I/O SGPIO7 — General purpose digital input/output pin.
AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[3]
P8_0
E5
-
2
-
N;
I/O GPIO4[0] — General purpose digital input/output pin.
PU
I
USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on
the USB bus (external circuitry required to detect
over-current condition).
-
I
R — Function reserved.
MCI2 — Motor control PWM channel 2, input.
I/O SGPIO8 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT0 — Match output 0 of timer 0.
[3]
P8_1
H5
-
34
-
N;
I/O GPIO4[1] — General purpose digital input/output pin.
PU
O
-
USB0_IND1 — USB0 port indicator LED control output 1.
R — Function reserved.
I
MCI1 — Motor control PWM channel 1, input.
I/O SGPIO9 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT1 — Match output 1 of timer 0.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[3]
[2]
[2]
[2]
P8_2
P8_3
P8_4
P8_5
K4
J3
J2
J1
-
-
-
-
36
37
39
40
-
-
-
-
N;
PU
I/O GPIO4[2] — General purpose digital input/output pin.
O
-
USB0_IND0 — USB0 port indicator LED control output 0.
R — Function reserved.
I
MCI0 — Motor control PWM channel 0, input.
I/O SGPIO10 — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
T0_MAT2 — Match output 2 of timer 0.
N;
PU
I/O GPIO4[3] — General purpose digital input/output pin.
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
R — Function reserved.
O
O
-
LCD_VD12 — LCD data.
LCD_VD19 — LCD data.
R — Function reserved.
-
R — Function reserved.
O
T0_MAT3 — Match output 3 of timer 0.
N;
PU
I/O GPIO4[4] — General purpose digital input/output pin.
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
R — Function reserved.
O
O
-
LCD_VD7 — LCD data.
LCD_VD16 — LCD data.
R — Function reserved.
-
R — Function reserved.
I
T0_CAP0 — Capture input 0 of timer 0.
N;
PU
I/O GPIO4[5] — General purpose digital input/output pin.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
-
R — Function reserved.
O
O
-
LCD_VD6 — LCD data.
LCD_VD8 — LCD data.
R — Function reserved.
-
R — Function reserved.
I
T0_CAP1 — Capture input 1 of timer 0.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P8_6
K3
-
43
-
N;
I/O GPIO4[6] — General purpose digital input/output pin.
PU
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.
-
R — Function reserved.
LCD_VD5 — LCD data.
O
O
LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
-
-
I
R — Function reserved.
R — Function reserved.
T0_CAP2 — Capture input 2 of timer 0.
[2]
[2]
[2]
P8_7
P8_8
P9_0
K1
L1
T1
-
-
-
45
49
59
-
-
-
N;
PU
I/O GPIO4[7] — General purpose digital input/output pin.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end
or interrupt transfers to the PHY.
-
R — Function reserved.
O
O
-
LCD_VD4 — LCD data.
LCD_PWR — LCD panel power enable.
R — Function reserved.
-
R — Function reserved.
I
T0_CAP3 — Capture input 3 of timer 0.
R — Function reserved.
N;
PU
-
I
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
O
CGU_OUT0 — CGU spare clock output 0.
I2S1_TX_MCLK — I2S1 transmit master clock.
N;
I/O GPIO4[12] — General purpose digital input/output pin.
PU
O
-
MCABORT — Motor control PWM, LOW-active fast abort.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I
ENET_CRS — Ethernet Carrier Sense (MII interface).
I/O SGPIO0 — General purpose digital input/output pin.
I/O SSP0_SSEL — Slave Select for SSP0.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P9_1
N6
-
66
-
N;
I/O GPIO4[13] — General purpose digital input/output pin.
PU
O
-
MCOA2 — Motor control PWM channel 2, output A.
R — Function reserved.
-
R — Function reserved.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I
ENET_RX_ER — Ethernet receive error (MII interface).
I/O SGPIO1 — General purpose digital input/output pin.
I/O SSP0_MISO — Master In Slave Out for SSP0.
I/O GPIO4[14] — General purpose digital input/output pin.
[2]
P9_2
N8
-
70
-
N;
PU
O
-
MCOB2 — Motor control PWM channel 2, output B.
R — Function reserved.
-
R — Function reserved.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I
ENET_RXD3 — Ethernet receive data 3 (MII interface).
I/O SGPIO2 — General purpose digital input/output pin.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
I/O GPIO4[15] — General purpose digital input/output pin.
[2]
P9_3
M6
-
79
-
N;
PU
O
O
-
MCOA0 — Motor control PWM channel 0, output A.
USB1_IND1 — USB1 Port indicator LED control output 1.
R — Function reserved.
-
R — Function reserved.
I
ENET_RXD2 — Ethernet receive data 2 (MII interface).
I/O SGPIO9 — General purpose digital input/output pin.
O
-
U3_TXD — Transmitter output for USART3.
R — Function reserved.
[2]
P9_4
N10
-
92
-
N;
PU
O
O
-
MCOB0 — Motor control PWM channel 0, output B.
USB1_IND0 — USB1 Port indicator LED control output 0.
R — Function reserved.
I/O GPIO5[17] — General purpose digital input/output pin.
ENET_TXD2 — Ethernet transmit data 2 (MII interface).
I/O SGPIO4 — General purpose digital input/output pin.
U3_RXD — Receiver input for USART3.
O
I
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
P9_5
M9
-
98
69
N;
-
R — Function reserved.
PU
O
O
MCOA1 — Motor control PWM channel 1, output A.
USB1_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that
VBUS must be driven (active high).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
-
R — Function reserved.
I/O GPIO5[18] — General purpose digital input/output pin.
ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O SGPIO3 — General purpose digital input/output pin.
U0_TXD — Transmitter output for USART0.
I/O GPIO4[11] — General purpose digital input/output pin.
O
O
[2]
P9_6
L11
-
103 72
N;
PU
O
I
MCOB1 — Motor control PWM channel 1, output B.
USB1_PWR_FAULT — USB1 Port power fault signal
indicating over-current condition; this signal monitors
over-current on the USB1 bus (external circuitry required to
detect over-current condition).
-
-
I
R — Function reserved.
R — Function reserved.
ENET_COL — Ethernet Collision detect (MII interface).
I/O SGPIO8 — General purpose digital input/output pin.
I
U0_RXD — Receiver input for USART0.
R — Function reserved.
[2]
PA_0
L12
-
126
-
N;
-
PU
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
O
-
I2S1_RX_MCLK — I2S1 receive master clock.
CGU_OUT1 — CGU spare clock output 1.
R — Function reserved.
[3]
PA_1
J14
-
134
-
N;
I/O GPIO4[8] — General purpose digital input/output pin.
PU
I
QEI_IDX — Quadrature Encoder Interface INDEX input.
R — Function reserved.
-
O
-
U2_TXD — Transmitter output for USART2.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[3]
[3]
[2]
[2]
PA_2
PA_3
PA_4
PB_0
K15
H11
G13
B15
-
-
-
-
136
147
151
164
-
-
-
-
N;
PU
I/O GPIO4[9] — General purpose digital input/output pin.
I
QEI_PHB — Quadrature Encoder Interface PHB input.
R — Function reserved.
-
I
U2_RXD — Receiver input for USART2.
R — Function reserved.
-
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
I/O GPIO4[10] — General purpose digital input/output pin.
I
QEI_PHA — Quadrature Encoder Interface PHA input.
R — Function reserved.
-
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
PU
-
R — Function reserved.
O
-
CTOUT_9 — SCT output 9. Match output 3 of timer 3.
R — Function reserved.
I/O EMC_A23 — External memory address line 23.
I/O GPIO5[19] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
-
R — Function reserved.
PU
O
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.
LCD_VD23 — LCD data.
R — Function reserved.
I/O GPIO5[20] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PB_1
A14
-
175
-
N;
PU
-
I
R — Function reserved.
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP
data line direction.
O
-
LCD_VD22 — LCD data.
R — Function reserved.
I/O GPIO5[21] — General purpose digital input/output pin.
O
-
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
R — Function reserved.
-
R — Function reserved.
[2]
[2]
[2]
PB_2
PB_3
PB_4
B12
A13
B11
-
-
-
177
178
180
-
-
-
N;
PU
-
R — Function reserved.
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
O
-
LCD_VD21 — LCD data.
R — Function reserved.
I/O GPIO5[22] — General purpose digital input/output pin.
O
-
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
R — Function reserved.
-
R — Function reserved.
N;
PU
-
R — Function reserved.
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.
O
-
LCD_VD20 — LCD data.
R — Function reserved.
I/O GPIO5[23] — General purpose digital input/output pin.
O
-
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
R — Function reserved.
-
R — Function reserved.
N;
-
R — Function reserved.
PU
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
O
-
LCD_VD15 — LCD data.
R — Function reserved.
I/O GPIO5[24] — General purpose digital input/output pin.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
R — Function reserved.
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PB_5
A12
-
181
-
N;
-
R — Function reserved.
PU
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.
O
-
LCD_VD14 — LCD data.
R — Function reserved.
I/O GPIO5[25] — General purpose digital input/output pin.
I
CTIN_7 — SCT input 7.
O
-
LCD_PWR — LCD panel power enable.
R — Function reserved.
[5]
PB_6
A6
-
-
-
N;
-
R — Function reserved.
PU
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
O
-
LCD_VD13 — LCD data.
R — Function reserved.
I/O GPIO5[26] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
LCD_VD19 — LCD data.
O
-
R — Function reserved.
AI ADC0_6 — ADC0 and ADC1, input channel 6. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[5]
PC_0
D4
-
7
-
N;
PU
-
I
R — Function reserved.
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.
-
R — Function reserved.
I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).
O
-
LCD_DCLK — LCD panel clock.
R — Function reserved.
-
R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the
pin as input (USB_ULPI_CLK) and use the ADC function
select register in the SCU to select the ADC.
[2]
PC_1
E4
-
9
-
N;
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
PU
-
R — Function reserved.
I
U1_RI — Ring Indicator input for UART 1.
ENET_MDC — Ethernet MIIM clock.
O
I/O GPIO6[0] — General purpose digital input/output pin.
-
R — Function reserved.
I
T3_CAP0 — Capture input 0 of timer 3.
SD_VOLT0 — SD/MMC bus voltage select output 0.
O
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PC_2
F6
-
13
-
N;
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.
PU
-
R — Function reserved.
I
U1_CTS — Clear to Send input for UART 1.
ENET_TXD2 — Ethernet transmit data 2 (MII interface).
O
I/O GPIO6[1] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
SD_RST — SD/MMC reset signal for MMC4.4 card.
[5]
PC_3
F5
-
11
-
N;
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
PU
-
R — Function reserved.
O
U1_RTS — Request to Send output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
O
ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O GPIO6[2] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
O
SD_VOLT1 — SD/MMC bus voltage select output 1.
AI ADC1_0 — DAC, ADC1 and ADC0, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.
[2]
PC_4
F4
-
16
-
N;
-
R — Function reserved.
PU
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.
-
R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
I/O GPIO6[3] — General purpose digital input/output pin.
-
I
R — Function reserved.
T3_CAP1 — Capture input 1 of timer 3.
I/O SD_DAT0 — SD/MMC data bus line 0.
R — Function reserved.
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
[2]
PC_5
G4
-
20
-
N;
PU
-
-
R — Function reserved.
O
ENET_TX_ER — Ethernet Transmit Error (MII interface).
I/O GPIO6[4] — General purpose digital input/output pin.
-
I
R — Function reserved.
T3_CAP2 — Capture input 2 of timer 3.
I/O SD_DAT1 — SD/MMC data bus line 1.
LPC435X_3X_2X_1X
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41 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
PC_6
PC_7
PC_8
H6
G5
N4
-
-
-
22
-
-
-
N;
PU
-
R — Function reserved.
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
I
R — Function reserved.
ENET_RXD2 — Ethernet receive data 2 (MII interface).
I/O GPIO6[5] — General purpose digital input/output pin.
-
I
R — Function reserved.
T3_CAP3 — Capture input 3 of timer 3.
I/O SD_DAT2 — SD/MMC data bus line 2.
R — Function reserved.
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
N;
PU
-
-
I
R — Function reserved.
ENET_RXD3 — Ethernet receive data 3 (MII interface).
I/O GPIO6[6] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT0 — Match output 0 of timer 3.
I/O SD_DAT3 — SD/MMC data bus line 3.
R — Function reserved.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
-
N;
PU
-
-
I
R — Function reserved.
ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).
I/O GPIO6[7] — General purpose digital input/output pin.
-
R — Function reserved.
O
I
T3_MAT1 — Match output 1 of timer 3.
SD_CD — SD/MMC card detect input.
R — Function reserved.
[2]
PC_9
K2
-
-
-
N;
-
PU
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.
-
I
R — Function reserved.
ENET_RX_ER — Ethernet receive error (MII interface).
I/O GPIO6[8] — General purpose digital input/output pin.
-
R — Function reserved.
O
O
T3_MAT2 — Match output 2 of timer 3.
SD_POW — SD/MMC power monitor output.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
PC_10
PC_11
PC_12
M5
L5
L6
-
-
-
-
-
-
-
-
-
N;
PU
-
R — Function reserved.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end
or interrupt transfers to the PHY.
I
U1_DSR — Data Set Ready input for UART 1.
R — Function reserved.
-
I/O GPIO6[9] — General purpose digital input/output pin.
-
R — Function reserved.
O
T3_MAT3 — Match output 3 of timer 3.
I/O SD_CMD — SD/MMC command signal.
N;
PU
-
I
R — Function reserved.
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI
data line direction.
I
U1_DCD — Data Carrier Detect input for UART 1.
R — Function reserved.
-
I/O GPIO6[10] — General purpose digital input/output pin.
-
-
R — Function reserved.
R — Function reserved.
I/O SD_DAT4 — SD/MMC data bus line 4.
N;
PU
-
R — Function reserved.
R — Function reserved.
-
O
U1_DTR — Data Terminal Ready output for UART 1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART 1.
-
R — Function reserved.
I/O GPIO6[11] — General purpose digital input/output pin.
I/O SGPIO11 — General purpose digital input/output pin.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O SD_DAT5 — SD/MMC data bus line 5.
[2]
PC_13
M1
-
-
-
N;
-
R — Function reserved.
PU
-
R — Function reserved.
O
-
U1_TXD — Transmitter output for UART 1.
R — Function reserved.
I/O GPIO6[12] — General purpose digital input/output pin.
I/O SGPIO12 — General purpose digital input/output pin.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
I/O SD_DAT6 — SD/MMC data bus line 6.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PC_14
N1
-
-
-
N;
PU
-
-
I
R — Function reserved.
R — Function reserved.
U1_RXD — Receiver input for UART 1.
R — Function reserved.
-
I/O GPIO6[13] — General purpose digital input/output pin.
I/O SGPIO13 — General purpose digital input/output pin.
O
ENET_TX_ER — Ethernet Transmit Error (MII interface).
I/O SD_DAT7 — SD/MMC data bus line 7.
[2]
PD_0
N2
-
-
-
N;
-
R — Function reserved.
PU
O
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
EMC_DQMOUT2 — Data mask 2 used with SDRAM and
static devices.
-
R — Function reserved.
I/O GPIO6[14] — General purpose digital input/output pin.
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
[2]
PD_1
P1
-
-
-
N;
-
R — Function reserved.
PU
-
R — Function reserved.
O
-
EMC_CKEOUT2 — SDRAM clock enable 2.
R — Function reserved.
I/O GPIO6[15] — General purpose digital input/output pin.
O
-
SD_POW — SD/MMC power monitor output.
R — Function reserved.
I/O SGPIO5 — General purpose digital input/output pin.
[2]
PD_2
R1
-
-
-
N;
-
R — Function reserved.
PU
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O EMC_D16 — External memory data line 16.
R — Function reserved.
I/O GPIO6[16] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO6 — General purpose digital input/output pin.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PD_3
PD_4
PD_5
PD_6
P4
T2
P6
R6
-
-
-
-
-
-
-
-
-
N;
PU
-
R — Function reserved.
O
CTOUT_6 — SCT output 7. Match output 2 of timer 1.
I/O EMC_D17 — External memory data line 17.
R — Function reserved.
I/O GPIO6[17] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO7 — General purpose digital input/output pin.
-
N;
PU
-
R — Function reserved.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
I/O EMC_D18 — External memory data line 18.
R — Function reserved.
I/O GPIO6[18] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO8 — General purpose digital input/output pin.
-
N;
PU
-
R — Function reserved.
O
CTOUT_9 — SCT output 9. Match output 3 of timer 3.
I/O EMC_D19 — External memory data line 19.
R — Function reserved.
I/O GPIO6[19] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO9 — General purpose digital input/output pin.
68
N;
-
R — Function reserved.
PU
O
CTOUT_10 — SCT output 10. Match output 3 of timer 3.
I/O EMC_D20 — External memory data line 20.
R — Function reserved.
I/O GPIO6[20] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO10 — General purpose digital input/output pin.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PD_7
PD_8
PD_9
PD_10
T6
-
-
-
-
72
74
84
86
-
-
-
-
N;
PU
-
I
R — Function reserved.
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
I/O EMC_D21 — External memory data line 21.
R — Function reserved.
I/O GPIO6[21] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO11 — General purpose digital input/output pin.
P8
N;
PU
-
I
R — Function reserved.
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
I/O EMC_D22 — External memory data line 22.
R — Function reserved.
I/O GPIO6[22] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO12 — General purpose digital input/output pin.
T11
N;
PU
-
R — Function reserved.
O
CTOUT_13 — SCT output 13. Match output 3 of timer 3.
I/O EMC_D23 — External memory data line 23.
R — Function reserved.
I/O GPIO6[23] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
I/O SGPIO13 — General purpose digital input/output pin.
P11
N;
PU
-
I
R — Function reserved.
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.
O
-
EMC_BLS3 — LOW active Byte Lane select signal 3.
R — Function reserved.
I/O GPIO6[24] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PD_11
PD_12
PD_13
PD_14
N9
-
-
-
-
88
94
97
99
-
-
-
-
N;
PU
-
R — Function reserved.
-
R — Function reserved.
O
-
EMC_CS3 — LOW active Chip Select 3 signal.
R — Function reserved.
I/O GPIO6[25] — General purpose digital input/output pin.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
O
-
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
R — Function reserved.
N11
T14
R13
N;
PU
-
R — Function reserved.
-
R — Function reserved.
O
-
EMC_CS2 — LOW active Chip Select 2 signal.
R — Function reserved.
I/O GPIO6[26] — General purpose digital input/output pin.
-
R — Function reserved.
O
-
CTOUT_10 — SCT output 10. Match output 3 of timer 3.
R — Function reserved.
N;
PU
-
R — Function reserved.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
EMC_BLS2 — LOW active Byte Lane select signal 2.
R — Function reserved.
O
-
I/O GPIO6[27] — General purpose digital input/output pin.
-
R — Function reserved.
O
-
CTOUT_13 — SCT output 13. Match output 3 of timer 3.
R — Function reserved.
N;
-
R — Function reserved.
PU
-
R — Function reserved.
O
-
EMC_DYCS2 — SDRAM chip select 2.
R — Function reserved.
I/O GPIO6[28] — General purpose digital input/output pin.
-
R — Function reserved.
O
-
CTOUT_11 — SCT output 11. Match output 3 of timer 2.
R — Function reserved.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PD_15
PD_16
PE_0
T15
R14
P14
N14
-
-
-
-
101
104
106
112
-
-
-
-
N;
PU
-
-
R — Function reserved.
R — Function reserved.
I/O EMC_A17 — External memory address line 17.
R — Function reserved.
I/O GPIO6[29] — General purpose digital input/output pin.
-
I
SD_WP — SD/MMC card write protect input.
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
R — Function reserved.
O
-
N;
PU
-
R — Function reserved.
-
R — Function reserved.
I/O EMC_A16 — External memory address line 16.
R — Function reserved.
I/O GPIO6[30] — General purpose digital input/output pin.
-
O
O
-
SD_VOLT2 — SD/MMC bus voltage select output 2.
CTOUT_12 — SCT output 12. Match output 3 of timer 3.
R — Function reserved.
N;
PU
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
I/O EMC_A18 — External memory address line 18.
I/O GPIO7[0] — General purpose digital input/output pin.
O
-
CAN1_TD — CAN1 transmitter output.
R — Function reserved.
-
R — Function reserved.
PE_1
N;
-
R — Function reserved.
PU
-
R — Function reserved.
-
R — Function reserved.
I/O EMC_A19 — External memory address line 19.
I/O GPIO7[1] — General purpose digital input/output pin.
I
CAN1_RD — CAN1 receiver input.
R — Function reserved.
-
-
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PE_2
PE_3
PE_4
PE_5
M14
K12
K13
N16
-
-
-
-
115
118
120
122
-
-
-
-
N;
PU
I
I
-
ADCTRIG0 — ADC trigger input 0.
CAN0_RD — CAN receiver input.
R — Function reserved.
I/O EMC_A20 — External memory address line 20.
I/O GPIO7[2] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
PU
-
R — Function reserved.
O
I
CAN0_TD — CAN transmitter output.
ADCTRIG1 — ADC trigger input 1.
I/O EMC_A21 — External memory address line 21.
I/O GPIO7[3] — General purpose digital input/output pin.
-
-
-
-
I
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
R — Function reserved.
NMI — External interrupt input to NMI.
R — Function reserved.
-
I/O EMC_A22 — External memory address line 22.
I/O GPIO7[4] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
-
R — Function reserved.
PU
O
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
U1_RTS — Request to Send output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
I/O EMC_D24 — External memory data line 24.
I/O GPIO7[5] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
[2]
PE_6
PE_7
PE_8
PE_9
M16
F15
F14
E16
-
-
-
-
124
149
150
152
-
-
-
-
N;
PU
-
R — Function reserved.
O
I
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
U1_RI — Ring Indicator input for UART 1.
I/O EMC_D25 — External memory data line 25.
I/O GPIO7[6] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
PU
-
R — Function reserved.
O
I
CTOUT_5 — SCT output 5. Match output 3 of timer 3.
U1_CTS — Clear to Send input for UART1.
I/O EMC_D26 — External memory data line 26.
I/O GPIO7[7] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
N;
PU
-
R — Function reserved.
O
I
CTOUT_4 — SCT output 4. Match output 3 of timer 3.
U1_DSR — Data Set Ready input for UART 1.
I/O EMC_D27 — External memory data line 27.
I/O GPIO7[8] — General purpose digital input/output pin.
-
-
-
-
I
R — Function reserved.
R — Function reserved.
R — Function reserved.
N;
PU
R — Function reserved.
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
U1_DCD — Data Carrier Detect input for UART 1.
I
I/O EMC_D28 — External memory data line 28.
I/O GPIO7[9] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PE_10
E14
-
154
-
N;
-
R — Function reserved.
PU
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
O
U1_DTR — Data Terminal Ready output for UART 1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART 1.
I/O EMC_D29 — External memory data line 29.
I/O GPIO7[10] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
[2]
PE_11
D16
-
-
-
N;
-
R — Function reserved.
PU
O
O
CTOUT_12 — SCT output 12. Match output 3 of timer 3.
U1_TXD — Transmitter output for UART 1.
I/O EMC_D30 — External memory data line 30.
I/O GPIO7[11] — General purpose digital input/output pin.
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
-
-
[2]
PE_12
D15
-
-
-
N;
-
PU
O
CTOUT_11 — SCT output 11. Match output 3 of
timer 2.
I
U1_RXD — Receiver input for UART 1.
I/O EMC_D31 — External memory data line 31.
I/O GPIO7[12] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
[2]
PE_13
G14
-
-
-
N;
-
R — Function reserved.
PU
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).
O
EMC_DQMOUT3 — Data mask 3 used with SDRAM and
static devices.
I/O GPIO7[13] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
PE_14
C15
-
-
-
N;
-
R — Function reserved.
PU
-
R — Function reserved.
-
R — Function reserved.
O
EMC_DYCS3 — SDRAM chip select 3.
I/O GPIO7[14] — General purpose digital input/output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
[2]
PE_15
E13
-
-
-
N;
-
R — Function reserved.
PU
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).
O
EMC_CKEOUT3 — SDRAM clock enable 3.
I/O GPIO7[15] — General purpose digital input/output pin.
-
-
-
R — Function reserved.
R — Function reserved.
R — Function reserved.
[2]
PF_0
D12
-
159
-
O;
I/O SSP0_SCK — Serial clock for SSP0.
PU
I
GP_CLKIN — General purpose clock input to the CGU.
R — Function reserved.
-
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
-
I2S1_TX_MCLK — I2S1 transmit master clock.
R — Function reserved.
[2]
PF_1
E11
-
-
-
N;
PU
-
R — Function reserved.
I/O SSP0_SSEL — Slave Select for SSP0.
R — Function reserved.
I/O GPIO7[16] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO0 — General purpose digital input/output pin.
R — Function reserved.
-
-
-
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[2]
[2]
[2]
PF_2
PF_3
PF_4
D11
-
168
-
N;
PU
-
R — Function reserved.
O
U3_TXD — Transmitter output for USART3.
I/O SSP0_MISO — Master In Slave Out for SSP0.
R — Function reserved.
I/O GPIO7[17] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO1 — General purpose digital input/output pin.
-
-
-
-
I
R — Function reserved.
E10
-
170
-
N;
PU
R — Function reserved.
U3_RXD — Receiver input for USART3.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
R — Function reserved.
I/O GPIO7[18] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO2 — General purpose digital input/output pin.
R — Function reserved.
I/O SSP1_SCK — Serial clock for SSP1.
-
-
-
D10 H4
172 120
O;
PU
I
GP_CLKIN — General purpose clock input to the CGU.
TRACECLK — Trace clock.
O
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the
master and received by the slave. Corresponds to the signal
SCK in the I2S-bus specification.
[5]
PF_5
E9
-
190
-
N;
-
R — Function reserved.
PU
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O SSP1_SSEL — Slave Select for SSP1.
O
TRACEDATA[0] — Trace data, bit 0.
I/O GPIO7[19] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
R — Function reserved.
-
-
AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[5]
PF_6
E7
-
192
-
N;
-
R — Function reserved.
PU
I/O U3_DIR — RS-485/EIA-485 output enable/direction control
for USART3.
I/O SSP1_MISO — Master In Slave Out for SSP1.
O
TRACEDATA[1] — Trace data, bit 1.
I/O GPIO7[20] — General purpose digital input/output pin.
R — Function reserved.
-
I/O SGPIO5 — General purpose digital input/output pin.
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[5]
PF_7
B7
-
193
-
N;
-
R — Function reserved.
PU
I/O U3_BAUD — Baud pin for USART3.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
O
TRACEDATA[2] — Trace data, bit 2.
I/O GPIO7[21] — General purpose digital input/output pin.
R — Function reserved.
-
I/O SGPIO6 — General purpose digital input/output pin.
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.
AI/ ADC1_7 — ADC1 and ADC0, input channel 7 or band gap
O
output. Configure the pin as GPIO input and use the ADC
function select register in the SCU to select the ADC.
[5]
PF_8
E6
-
-
-
N;
-
R — Function reserved.
PU
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
TRACEDATA[3] — Trace data, bit 3.
O
I/O GPIO7[22] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO7 — General purpose digital input/output pin.
R — Function reserved.
-
-
AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[5]
PF_9
D6
-
203
-
N;
-
R — Function reserved.
PU
I/O U0_DIR — RS-485/EIA-485 output enable/direction control
for USART0.
O
-
CTOUT_1 — SCT output 1. Match output 3 of timer 3.
R — Function reserved.
I/O GPIO7[23] — General purpose digital input/output pin.
R — Function reserved.
I/O SGPIO3 — General purpose digital input/output pin.
R — Function reserved.
-
-
AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[5]
PF_10
A3
-
205
-
N;
-
R — Function reserved.
PU
O
-
U0_TXD — Transmitter output for USART0.
R — Function reserved.
-
R — Function reserved.
I/O GPIO7[24] — General purpose digital input/output pin.
-
I
R — Function reserved.
SD_WP — SD/MMC card write protect input.
R — Function reserved.
-
AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
[5]
PF_11
A2
-
207
-
N;
PU
-
I
R — Function reserved.
U0_RXD — Receiver input for USART0.
R — Function reserved.
-
-
R — Function reserved.
I/O GPIO7[25] — General purpose digital input/output pin.
-
R — Function reserved.
O
-
SD_VOLT2 — SD/MMC bus voltage select output 2.
R — Function reserved.
AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the
pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
Clock pins
[4]
CLK0
N5
K3
62
45
O;
PU
O
O
-
EMC_CLK0 — SDRAM clock 0.
CLKOUT — Clock output pin.
R — Function reserved.
-
R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
EMC_CLK01 — SDRAM clock 0 and clock 1 combined.
I/O SSP1_SCK — Serial clock for SSP1.
O
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).
[4]
CLK1
T10
-
-
-
O;
PU
O
O
-
EMC_CLK1 — SDRAM clock 1.
CLKOUT — Clock output pin.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
-
CGU_OUT0 — CGU spare clock output 0.
R — Function reserved.
O
O
O
-
I2S1_TX_MCLK — I2S1 transmit master clock.
EMC_CLK3 — SDRAM clock 3.
CLKOUT — Clock output pin.
R — Function reserved.
[4]
CLK2
D14 K6
141 99
O;
PU
-
R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
O
O
EMC_CLK23 — SDRAM clock 2 and clock 3 combined.
I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
[4]
CLK3
P12
-
-
-
O;
PU
O
O
-
EMC_CLK2 — SDRAM clock 2.
CLKOUT — Clock output pin.
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
-
CGU_OUT1 — CGU spare clock output 1.
R — Function reserved.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
Debug pins
[2]
DBGEN
L4
A6
41
28
I
I
JTAG interface control signal. Also used for boundary scan.
To use the part in functional mode, connect this pin in one of
the following ways:
• Leave DBGEN open. The DBGEN pin is pulled up
internally by a 50 kΩ resistor.
• Tie DBGEN to VDDIO.
• Pull DBGEN up to VDDIO with an external pull-up
resistor.
[2]
TCK/SWDCLK J5
H2
38
27
I; F
I
Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.
[2]
[2]
TRST
M4
K6
B4
C4
42
44
29
30
I; PU I
I; PU I
Test Reset for JTAG interface.
TMS/SWDIO
Test Mode Select for JTAG interface (default) or SW debug
data input/output.
[2]
[2]
TDO/SWO
K5
J4
H3
G3
46
35
31
26
O
O
Test Data Out for JTAG interface (default) or SW trace
output.
TDI
I; PU I
Test Data In for JTAG interface.
USB0 pins
USB0_DP
[6]
F2
G2
F1
H2
E1
E2
E3
F1
26
28
29
30
18
20
21
22
-
-
-
-
I/O USB0 bidirectional D+ line. Do not add an external series
resistor.
[6]
USB0_DM
USB0_VBUS
USB0_ID
I/O USB0 bidirectional D line. Do not add an external series
resistor.
[6][7]
[8]
I
I
VBUS pin (power on USB cable). This pin includes an
internal pull-down resistor of 64 k (typical) 16 k.
Indicates to the transceiver whether connected as an
A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). For
OTG this pin has an internal pull-up resistor.
[8]
USB0_RREF
H1
F3
32
24
-
12.0 k (accuracy 1 %) on-board resistor to ground for
current reference.
USB1 pins
[9]
[9]
USB1_DP
F12 E9
129 89
-
-
I/O USB1 bidirectional D+ line. Add an external series resistor of
33 +/- 2 %.
USB1_DM
G12 E10 130 90
I/O USB1 bidirectional D line. Add an external series resistor of
33 +/- 2 %.
I2C-bus pins
[10]
[10]
I2C0_SCL
L15 D6
L16 E6
132 92
133 93
I; F I/O I2C clock input/output. Open-drain output (for I2C-bus
compliance).
I; F I/O I2C data input/output. Open-drain output (for I2C-bus
compliance).
I2C0_SDA
Reset and wake-up pins
[11]
RESET
D9
B6
185 128
I; IA
I
External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. This
pin does not have an internal pull-up.
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[11]
[11]
[11]
[11]
WAKEUP0
WAKEUP1
WAKEUP2
A9
A4
187 130
I; IA
I; IA
I; IA
I; IA
I
I
I
I
External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 0 of the event monitor.No internal pull-up is enabled
when this pin is configured as input.
A10
C9
D8
-
-
-
-
-
-
-
-
-
External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 1 of the event monitor. No internal pull-up is enabled
when this pin is configured as input.
External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 2 of the event monitor. This pin does not have an
internal pull-up.
WAKEUP3
External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part. This pin does
not have an internal pull-up.
ADC pins
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
ADC0_0/
ADC1_0/DAC
E3
C3
A4
B5
C6
B3
A5
C5
A2
A1
B3
A3
-
8
4
6
2
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I
I
I
I
I
I
I
I
ADC input channel 0. Shared between 10-bit ADC0/1 and
DAC.
ADC0_1/
ADC1_1
ADC input channel 1. Shared between 10-bit ADC0/1.
ADC input channel 2. Shared between 10-bit ADC0/1.
ADC input channel 3. Shared between 10-bit ADC0/1.
ADC input channel 4. Shared between 10-bit ADC0/1.
ADC input channel 5. Shared between 10-bit ADC0/1.
ADC input channel 6. Shared between 10-bit ADC0/1.
ADC input channel 7. Shared between 10-bit ADC0/1.
ADC0_2/
ADC1_2
206 143
200 139
199 138
208 144
204 142
197 136
ADC0_3/
ADC1_3
ADC0_4/
ADC1_4
ADC0_5/
ADC1_5
-
ADC0_6/
ADC1_6
-
ADC0_7/
ADC1_7
-
RTC
[11]
[8]
RTC_ALARM
RTCX1
A11 C3
186 129
182 125
183 126
-
-
-
O
I
RTC controlled output.
A8
B8
A5
B5
Input to the RTC 32 kHz ultra-low power oscillator circuit.
[8]
RTCX2
O
Output from the RTC 32 kHz ultra-low power oscillator
circuit.
[11]
SAMPLE
B9
-
-
-
O
O
Event monitor sample output.
Crystal oscillator pins
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[8]
[8]
XTAL1
XTAL2
D1
E1
B1
C1
18
19
12
13
-
-
I
Input to the oscillator circuit and internal clock generator
circuits.
O
Output from the oscillator amplifier.
Power and ground pins
USB0_VDDA
3V3_DRIVER
F3
G3
H3
G1
B4
D1
D2
D3
F2
B2
24
25
27
31
16
17
19
23
-
-
-
-
-
-
-
-
Separate analog 3.3 V power supply for driver.
USB 3.3 V separate power supply voltage.
USB0
_VDDA3V3
USB0_VSSA
_TERM
Dedicated analog ground for clean reference for termination
resistors.
USB0_VSSA
_REF
Dedicated clean analog ground for generation of reference
currents and voltages.
VDDA
VBAT
198 137
184 127
-
-
-
-
Analog power supply and ADC reference voltage.
B10 C5
RTC power supply: 3.3 V on this pin supplies power to the
RTC.
VDDREG
F10, E4,
135, 94,
188, 131,
195, 59,
82, 25
33
-
Main regulator power supply. Tie the VDDREG and VDDIO
pins to a common power supply to ensure the same ramp-up
time for both supply voltages.
F9,
L8,
L7
E5,
F4
[12]
[12]
VPP
E8
-
-
-
-
-
-
-
OTP programming voltage.
VDDIO
D7,
E12, K5
F7,
F10, 6,
5,
I/O power supply. Tie the VDDREG and VDDIO pins to a
common power supply to ensure the same ramp-up time for
both supply voltages.
52, 36,
57, 41,
102, 71,
110, 77,
155, 107,
160, 111,
202 141
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13
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32-bit ARM Cortex-M4/M0 microcontroller
Table 3.
Pin description …continued
Pin name
Description
[13]
VSS
G9, C8,
H7, D4,
J10, D5,
J11, G8,
-
-
-
-
-
-
Ground.
K8
J3,
J6
[13]
VSSIO
C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
-
5,
4,
Ground.
56, 40,
109, 76,
157 109
J9,
K9,
K10,
M13,
P7,
P13
VSSA
B2
C2
196 135
-
-
Analog ground.
[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in
the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA
= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset
without boot code operation.
[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.
[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels, and hysteresis; high drive strength.
[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed
digital I/O functions with TTL levels and hysteresis.
[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;
if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.
[6] 5 V tolerant transparent analog pad.
[7] For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS
= 0.2 V when it is no longer driven.
[8] Transparent analog pad. Not 5 V tolerant.
[9] Pad provides USB functions; 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with
the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output and hysteresis.
[12] VPP is internally connected to VDDIO for all packages with the exception of the LBGA256 package.
[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.
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32-bit ARM Cortex-M4/M0 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus,
and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and
data accesses from different slave ports.
The LPC435x/3x/2x/1x use a multi-layer AHB matrix to connect the ARM Cortex-M4
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
An ARM Cortex-M0 co-processor is included in the LPC435x/3x/2x/1x, capable of
off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are
connected to both processors. The processors communicate with each other via an
interprocessor communication protocol.
7.2 ARM Cortex-M4 processor
The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture
with separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated in the core. The processor includes an
NVIC with up to 53 interrupts.
7.3 ARM Cortex-M0 co-processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M0 co-processor uses a
3-stage pipeline von Neumann architecture and a small but powerful instruction set
providing high-end processing hardware. In LPC43xx, the Cortex-M0 coprocessor
hardware multiply is implemented as a 32-cycle iterative multiplier. The co-processor
incorporates an NVIC with 32 interrupts.
7.4 Interprocessor communication
The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on
using shared SRAM as mailbox and one processor raising an interrupt on the other
processor's NVIC, for example after it has delivered a new message in the mailbox. The
receiving processor can reply by raising an interrupt on the sending processor's NVIC to
acknowledge the message.
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32-bit ARM Cortex-M4/M0 microcontroller
7.5 AHB multilayer matrix
HIGH-SPEED PHY
TEST/DEBUG
INTERFACE
TEST/DEBUG
INTERFACE
ARM
ARM
SD/
MMC
DMA
1
ETHERNET
USB0
USB1
LCD
masters
CORTEX-M4 CORTEX-M0
System
I-
D-
0
bus code code
bus bus
slaves
256/512 kB FLASH A
256/512 kB FLASH B
16 kB EEPROM
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
32 kB AHB SRAM
16 kB AHB SRAM
16 kB AHB SRAM
SPIFI
SGPIO
EXTERNAL
MEMORY
CONTROLLER
AHB PERIPHERALS
REGISTER
INTERFACES
APB, RTC
DOMAIN
PERIPHERALS
AHB MULTILAYER MATRIX
= master-slave connection
002aah080
Fig 6. AHB multilayer matrix master and slave connections
7.6 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
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32-bit ARM Cortex-M4/M0 microcontroller
7.6.1 Features
• ARM Cortex-M4 core:
– Controls system exceptions and peripheral interrupts
– Support for up to 53 vectored interrupts
– Eight programmable interrupt priority levels with hardware priority level masking
– Relocatable vector table
– Non-Maskable Interrupt (NMI)
– Software interrupt generation
• ARM Cortex-M0 core:
– Support for up to 32 interrupts
– Four programmable interrupt priority levels with hardware priority level masking
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
7.7 System Tick timer (SysTick)
The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
Remark: The SysTick is not included in the ARM Cortex-M0 core implementation.
7.8 Event router
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event
router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,
Deep-sleep, Power-down, and Deep power-down modes. Individual events can be
configured as edge or level sensitive and can be enabled or disabled in the event router.
The event router can be battery powered.
The following events if enabled in the event router can create a wake-up signal from
sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:
• External pins WAKEUP0/1/2/3 and RESET
• Alarm timer, RTC (32 kHz oscillator running)
The following events if enabled in the event router can create a wake-up signal from sleep
mode only and/or create an interrupt:
• WWDT, BOD interrupts.
• C_CAN0/1 and QEI interrupts.
• Ethernet, USB0, USB1 signals.
• Selected outputs of combined timers (SCTimer/PWM and timer0/1/3).
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32-bit ARM Cortex-M4/M0 microcontroller
Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in
the NVIC.
7.9 Global Input Multiplexer Array (GIMA)
The GIMA allows to route signals to event-driven peripheral targets like the
SCTimer/PWM, timers, event router, or the ADCs.
7.9.1 Features
• Single selection of a source.
• Signal inversion.
• Can capture a pulse if the input event source is faster than the target clock.
• Synchronization of input event and target clock.
• Single-cycle pulse generation for target.
7.10 On-chip static RAM
The LPC435x/3x/2x/1x support up to 136 kB SRAM with separate bus master access for
higher throughput and individual power control for low power operation.
7.11 On-chip flash memory
The LPC435x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With
dual-bank flash memory, the user code can write or erase one flash bank while reading
the other flash bank without interruption. A two-port flash accelerator maximizes the flash
performance.
In-System Programming (ISP) and In-Application Programming (IAP) routines for
programming the flash memory are provided in the Boot ROM.
7.12 EEPROM
The LPC435x/3x/2x/1x contain 16 kB of on-chip byte-erasable and byte-programmable
EEPROM memory.
The EEPROM memory is divided into 128 pages. The user can access pages 1 through
127. Page 128 is protected.
7.13 Boot ROM
The internal ROM memory is used to store the boot code of the LPC435x/3x/2x/1x. After a
reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• The ROM memory size is 64 kB.
• Supports booting from external static memory such as NOR flash, SPI flash, quad SPI
flash, USB0, and USB1.
• Includes API for OTP programming.
• Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
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32-bit ARM Cortex-M4/M0 microcontroller
Several boot modes are available if P2_7 is LOW on reset depending on the values of the
OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are
all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2,
and P1_1.
Table 4.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC BOOT_SRC BOOT_SRC BOOT_SRC Description
bit 3
bit 2
bit 1
bit 0
Pin state
USART0
SPIFI
0
0
0
0
Boot source is defined by the reset state of P1_1,
P1_2, P2_8 pins, and P2_9. See Table 5.
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Enter ISP mode using USART0 pins P2_0 and
P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit
EMC 16-bit
EMC 32-bit
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
0
0
1
1
1
0
1
1
0
0
1
0
Boot from USB0.
Boot from USB1.
USB1
SPI (SSP)
Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
USART3
1
0
0
1
Enter ISP mode using USART3 pins P2_3 and
P2_4.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
Table 5.
Boot mode when OPT BOOT_SRC bits are zero
Pins
Boot mode
Description
P2_9
P2_8
P1_2
P1_1
USART0
SPIFI
LOW
LOW
LOW
LOW
Enter ISP mode using USART0 pins P2_0 and
P2_1.
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8[1].
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from USB0
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32-bit ARM Cortex-M4/M0 microcontroller
Table 5.
Boot mode when OPT BOOT_SRC bits are zero
Boot mode
Pins
P2_9
LOW
LOW
Description
P2_8
HIGH
HIGH
P1_2
HIGH
HIGH
P1_1
LOW
HIGH
USB1
Boot from USB1.
SPI (SSP)
Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]
USART3
HIGH
LOW
LOW
LOW
Enter ISP mode using USART3 pins P2_3 and
P2_4.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
7.14 Memory mapping
The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the
Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between
both processors. Each processor uses its own ARM private bus memory map for the
NVIC and other system functions.
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32-bit ARM Cortex-M4/M0 microcontroller
LPC435x/3x/2x/1x
4 GB
0xFFFF FFFF
reserved
0xE010 0000
ARM private bus
0xE000 0000
reserved
0x8800 0000
128 MB SPIFI data
0x8000 0000
256 MB dynamic external memory DYCS3
0x7000 0000
256 MB dynamic external memory DYCS2
0x6000 0000
reserved
0x4400 0000
peripheral bit band alias region
0x4200 0000
reserved
0x4010 2000
SGPIO
0x4010 1000
0x4010 0000
SPI
reserved
0x400F 8000
high-speed GPIO
0x400F 4000
reserved
0x400F 2000
reserved
0x2000 0000
0x400F 1000
16 MB static external memory CS3
reserved
0x1F00 0000
0x1E00 0000
0x1D00 0000
0x1C00 0000
0x400F 0000
16 MB static external memory CS2
16 MB static external memory CS1
APB peripherals #3
0x400E 0000
reserved
0x400D 0000
16 MB static external memory CS0
APB peripherals #2
0x400C 0000
reserved
reserved
0x400B 0000
APB peripherals #1
0x1B08 0000
0x1B04 0000
0x1B00 0000
0x400A 0000
reserved
256 kB flash B
256 kB flash B
0x4009 0000
APB peripherals #0
0x4008 0000
reserved
0x4006 0000
reserved
clocking/reset peripherals
0x1A08 0000
0x1A04 0000
0x1A00 0000
0x4005 0000
RTC domain peripherals
0x4004 0000
256 kB flash A
256 kB flash A
reserved
reserved
0x4001 2000
AHB peripherals
1 GB
0x4000 0000
256 MB dynamic external memory DYCS1
0x1800 0000
0x1400 0000
0x3000 0000
64 MB SPIFI data
reserved
128 MB dynamic external memory DYCS0
0x2800 0000
reserved
0x1041 0000
0x2400 0000
64 kB ROM
reserved
0x1040 0000
0x1008 A000
32 MB AHB SRAM bit banding
0x2200 0000
reserved
32 kB + 8 kB local SRAM
0x1008 0000
0x2004 4000
16 kB EEPROM
0x2004 0000
reserved
reserved
0x2001 0000
4 x 16 kB AHB SRAM
0x1000 8000
0x1000 0000
0x2000 0000
local SRAM/flash/SPIFI data/ROM
external static memory banks
32 kB local SRAM
0x1000 0000
256 MB shadow area
0x0000 0000
0 GB
002aah182
Fig 7. LPC435x/3x/2x/1x Memory mapping (overview)
LPC435X_3X_2X_1X
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC435x/3x/2x/1x
0x400F 0000
0x400E 5000
0x400E 4000
0x400E 3000
0x400E 2000
0x4006 0000
0x4005 4000
reserved
ADC1
0xFFFF FFFF
reserved
RGU
APB3
peripherals
external memories and
ARM private bus
0x4005 3000
0x4005 2000
0x4005 1000
0x4005 0000
clocking
reset control
peripherals
ADC0
CCU2
CCU1
CGU
0x6000 0000
0x4400 0000
C_CAN0
DAC
reserved
peripheral bit band alias region
reserved
0x400E 1000
I2C1
0x4200 0000
0x4010 2000
0x4010 1000
0x4010 0000
0x400E 0000
0x400C 8000
0x4005 0000
0x4004 7000
SGPIO
SPI
GIMA
reserved
RTC/event monitor
OTP controller
event router
0x400C 7000
0x400C 6000
QEI
SSP1
0x4004 6000
0x4004 5000
0x4004 4000
0x4004 3000
0x4004 2000
0x4004 1000
APB2
peripherals
reserved
0x400C 5000
0x400C 4000
0x400C 3000
0x400C 2000
0x400C 1000
0x400F 8000
0x400F 4000
0x400F 2000
timer3
RTC domain
peripherals
high-speed GPIO
reserved
CREG
timer2
power mode control
backup registers
alarm timer
USART3
USART2
reserved
reserved
0x400F 1000
0x400F 0000
0x400E 0000
0x400D 0000
0x400C 0000
RI timer
0x400C 0000
0x400B 0000
0x4004 0000
0x4002 0000
0x4001 2000
0x4001 0000
APB3 peripherals
reserved
reserved
C_CAN1
I2S1
I2S0
reserved
ethernet
reserved
0x400A 5000
0x400A 4000
0x400A 3000
0x400A 2000
0x400A 1000
APB2 peripherals
reserved
APB1
peripherals
0x400B 0000
0x400A 0000
0x4009 0000
0x4008 0000
0x4000 F000
0x4000 E000
0x4000 D000
APB1 peripherals
EEPROM controller
flash B controller
flash A controller
reserved
I2C0
reserved
motor control PWM
0x400A 0000
APB0 peripherals
0x4000 C000
0x4000 9000
0x4000 8000
0x4000 7000
0x4000 6000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000
GPIO GROUP1 interrupt
reserved
0x4006 0000
0x4005 0000
0x4004 0000
LCD
USB1
USB0
EMC
AHB
peripherals
GPIO GROUP0 interrupt
GPIO interrupts
SCU
clocking/reset peripherals
RTC domain peripherals
reserved
0x4008 6000
0x4008 5000
0x4008 4000
0x4008 3000
0x4008 2000
APB0
peripherals
timer1
timer0
0x4002 0000
0x4000 0000
0x4000 5000
0x4000 4000
0x4000 3000
0x4000 2000
0x4000 1000
AHB peripherals
SD/MMC
SPIFI
SRAM, flash, EEPROM memories,
SPIFI data, ROM
SSP0
external memory banks
DMA
UART1 w/ modem
USART0
0x1000 0000
0x0000 0000
256 MB memory shadow area
reserved
SCT
0x4008 1000
0x4008 0000
WWDT
0x4000 0000
002aah183
Fig 8. LPC435x/3x/2x/1x Memory mapping (peripherals)
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
7.15 One-Time Programmable (OTP) memory
The OTP provides 64 bit+ 256 bit of memory for general-purpose use.
7.16 General Purpose I/O (GPIO)
The LPC435x/3x/2x/1x provide eight GPIO ports with up to 31 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on
reset. The input buffer must be turned on in the system control block SFS register before
the GPIO input can be read.
7.16.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request (GPIO interrupts).
• Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO
group0 and group1 interrupts).
7.17 Configurable digital peripherals
7.17.1 State Configurable Timer (SCTimer/PWM) subsystem
The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input
capture operations. The inputs and outputs of the SCTimer/PWM are shared with the
capture and match inputs/outputs of the 32-bit general purpose counter/timers.
The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In
the two-counter case, in addition to the counter value the following operational elements
are independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
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In the two-counter case, the following operational elements are global to the
SCTimer/PWM, but the last three can use match conditions from either counter:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts
7.17.1.1 Features
• Two 16-bit counters or one 32-bit counter.
• Counters clocked by bus clock or selected input.
• Up counters or up-down counters.
• State variable allows sequencing across multiple counter cycles.
• The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.
• Events control outputs, interrupts, and DMA requests.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• Selected events can limit, halt, start, or stop a counter.
• Supports:
– 8 inputs
– 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
– Match register 0 to 5 support a fractional component for the dither engine
7.17.2 Serial GPIO (SGPIO)
The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate
serial stream processing.
7.17.2.1 Features
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.
• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value
from a pin or an output value to a pin with every cycle of a shift clock.
• Each slice is double-buffered.
• Interrupt is generated on a full FIFO, shift clock, or pattern match.
• Slices can be concatenated to increase buffer size.
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• Each slice has a 32-bit pattern match filter.
7.18 AHB peripherals
7.18.1 General Purpose DMA
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
7.18.1.1 Features
• Eight DMA channels. Each channel can support a unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.18.2 SPI Flash Interface (SPIFI)
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM
Cortex-M4 processor with little performance penalty compared to parallel flash devices
with higher pin count.
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32-bit ARM Cortex-M4/M0 microcontroller
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Simple sequences of commands handle erasing and
programming.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.18.2.1 Features
• Interfaces to serial flash memory in the main memory map.
• Supports classic and 4-bit bidirectional serial protocols.
• Half-duplex protocol compatible with various vendors and devices.
• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per
second.
• Supports DMA access.
7.18.3 SD/MMC card interface
The SD/MMC card interface supports the following modes to control:
• Secure Digital memory (SD version 3.0)
• Secure Digital I/O (SDIO version 2.0)
• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
• MultiMedia Cards (MMC version 4.4)
7.18.4 External Memory Controller (EMC)
Remark: The EMC is available on all LPC435x/3x/2x/1x parts. The following memory bus
widths are supported:
• LBGA256 packages: 32 bit
• TFBGA100 packages: 16 bit
• LQFP208 packages: 16 bit
• LQFP144 packages: 16 bit
The LPC435x/3x/2x/1x EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it
can be used as an interface with off-chip memory-mapped devices and peripherals.
Table 6.
EMC pinout for different packages
Function
LBGA256
TFBGA100
EMC_A[13:0]
EMC_D[7:0]
EMC_BLS0
EMC_CS0
LQFP208
LQFP144
A
EMC_A[23:0]
EMC_D[31:0]
EMC_BLS[3:0]
EMC_CS[3:0]
EMC_A[23:0]
EMC_D[15:0]
EMC_BLS[1:0]
EMC_CS[3:0]
EMC_A[15:0]
EMC_D[15:0]
EMC_BLS[1:0]
EMC_CS[1:0]
D
BLS
CS
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32-bit ARM Cortex-M4/M0 microcontroller
Table 6.
EMC pinout for different packages
Function
OE
LBGA256
EMC_OE
EMC_WE
TFBGA100
EMC_OE
EMC_WE
LQFP208
EMC_OE
EMC_WE
LQFP144
EMC_OE
EMC_WE
WE
CKEOUT
EMC_
EMC_
EMC_
EMC_
CKEOUT[3:0]
CKEOUT[1:0]
CKEOUT[1:0]
CKEOUT[1:0]
CLK
EMC_CLK[3:0]; EMC_CLK0,
EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23
EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23
EMC_CLK01,
EMC_CLK23
EMC_CLK3;
EMC_CLK01,
EMC_CLK23
DQMOUT
DYCS
EMC_
DQMOUT[3:0]
-
EMC_
DQMOUT[1:0]
EMC_
DQMOUT[1:0]
EMC_
EMC_DYCS[1:0]
EMC_DYCS[2:0]
EMC_DYCS[1:0]
DYCS[3:0]
CAS
RAS
EMC_CAS
EMC_RAS
EMC_CAS
EMC_RAS
EMC_CAS
EMC_RAS
EMC_CAS
EMC_RAS
7.18.4.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and NOR flash,
with or without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 24 address lines wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. Those are typically 512 MB, 256 MB, and
128 MB parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
• SDRAM clock can run at full or half the Cortex-M4 core frequency.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
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7.18.5 High-speed USB Host/Device/OTG interface (USB0)
Remark: USB0 is available on the following parts: LPC435x, LPC433x, LPC432x. USB0
is not available on the LPC431x parts.
The USB OTG module allows the LPC435x/3x/2x/1x to connect directly to a USB Host
such as a PC (in device mode) or to a USB Device in host mode.
7.18.5.1 Features
• Contains UTMI+ compliant high-speed transceiver (PHY).
• Complies with Universal Serial Bus specification 2.0.
• Complies with USB On-The-Go supplement.
• Complies with Enhanced Host Controller Interface Specification.
• Supports auto USB 2.0 mode discovery.
• Supports all high-speed USB-compliant peripherals.
• Supports all full-speed USB-compliant peripherals.
• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Supports interrupts.
• Supports Start Of Frame (SOF) frame length adjust.
• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.18.6 High-speed USB Host/Device interface with ULPI (USB1)
Remark: USB1 is available on the following parts: LPC435x and LPC433x. USB1 is not
available on the LPC432x and LPC431x parts.
The USB1 interface can operate as a full-speed USB Host/Device interface or can
connect to an external ULPI PHY for High-speed operation.
7.18.6.1 Features
• Complies with Universal Serial Bus specification 2.0.
• Complies with Enhanced Host Controller Interface Specification.
• Supports auto USB 2.0 mode discovery.
• Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
• Supports all full-speed USB-compliant peripherals.
• Supports interrupts.
• Supports Start Of Frame (SOF) frame length adjust.
• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.18.7 LCD controller
Remark: The LCD controller is only available on parts LPC435x. LCD is not available on
parts LPC433x, LPC432x, and LPC431x.
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The LCD controller provides all of the necessary control signals to interface directly to
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of
the displayed data) while still supporting many colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time required to operate the display.
7.18.7.1 Features
• AHB master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320 200, 320 240,
640 200, 640 240, 640 480, 800 600, and 1024 768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
• 16 bpp true-color non-palettized for color STN and TFT.
• 24 bpp true-color non-palettized for color TFT.
• Programmable timing for different display panels.
• 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM.
• Frame, line, and pixel clock signals.
• AC bias signal for STN, data enable signal for TFT panels.
• Supports little and big-endian, and Windows CE data formats.
• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.18.8 Ethernet
Remark: The ethernet controller is available on parts LPC435x and LPC433x. Ethernet is
not available on parts LPC432x and LPC431x.
7.18.8.1 Features
• 10/100 Mbit/s
• DMA support
• Power management remote wake-up frame and magic packet detection
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• Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.
• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE
1588-2008 v2).
7.19 Digital serial peripherals
7.19.1 UART1
Remark: The LPC435x/3x/2x/1x contain one UART with standard transmit and receive
data lines.
UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd
can be achieved with any crystal frequency above 2 MHz.
7.19.1.1 Features
• Maximum UART data bit rate of 8 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Equipped with standard modem interface signals. This module also provides full
support for hardware flow control.
• Support for RS-485/9-bit/EIA-485 mode (UART1).
• DMA support.
7.19.2 USART0/2/3
Remark: The LPC435x/3x/2x/1x contain three USARTs. In addition to standard transmit
and receive data lines, the USARTs support a synchronous mode.
The USARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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7.19.2.1 Features
• Maximum UART data bit rate of 8 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Support for RS-485/9-bit/EIA-485 mode.
• USART3 includes an IrDA mode to support infrared communication.
• All USARTs have DMA support.
• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.
• Smart card mode conforming to ISO7816 specification
7.19.3 SPI serial I/O controller
Remark: The LPC435x/3x/2x/1x contain one SPI controller.
SPI is a full duplex serial interface designed to handle multiple masters and slaves
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to
the master.
7.19.3.1 Features
• Maximum SPI data bit rate 25 Mbit/s.
• Compliant with SPI specification
• Synchronous, serial, full duplex communication
• Combined SPI master and slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 bits to 16 bits per transfer
7.19.4 SSP serial I/O controller
Remark: The LPC435x/3x/2x/1x contain two SSP controllers.
The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.19.4.1 Features
• Maximum SSP speed in full-duplex mode of 25.5 Mbit/s; for transmit only 51 Mbit/s
(master) and 11 Mbit/s (slave)
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• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• DMA transfers supported by GPDMA
7.19.5 I2C-bus interface
Remark: The LPC435x/3x/2x/1x each contain two I2C-bus interfaces.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and
can be controlled by more than one bus master connected to it.
7.19.5.1 Features
• I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.
7.19.6 I2S interface
Remark: The LPC435x/3x/2x/1x each contain two I2S-bus interfaces.
The I2S-bus provides a standard communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
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7.19.6.1 Features
• The I2S interfaces has separate input/output channels, each of which can operate in
master or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,
96, 192) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests controlled by programmable buffer levels. The DMA requests are
connected to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
7.19.7 C_CAN
Remark: The LPC435x/3x/2x/1x each contain two C_CAN controllers.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a high level of reliability.
7.19.7.1 Features
• Conforms to protocol version 2.0 parts A and B.
• Supports bit rate of up to 1 Mbit/s.
• Supports 32 Message Objects.
• Each Message Object has its own identifier mask.
• Provides programmable FIFO mode (concatenation of Message Objects).
• Provides maskable interrupts.
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
7.20 Counter/timers and motor control
7.20.1 General purpose 32-bit timers/external event counters
Remark: The LPC435x/3x/2x/1x include four 32-bit timer/counters.
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The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.20.1.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
7.20.2 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input causes the PWM to release all
motor drive outputs immediately . At the same time, the motor control PWM is highly
configurable for other generalized timing, counting, capture, and compare applications.
7.20.3 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user code can track the position, direction of rotation,
and velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.20.3.1 Features
• Tracks encoder position.
• Increments/decrements depending on direction.
• Programmable for 2 or 4 position counting.
• Velocity capture using built-in timer.
• Velocity compare function with “less than” interrupt.
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• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
7.20.4 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare function can be masked such that they do not contribute to the match
detection. The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
7.20.4.1 Features
• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This mechanism allows for combinations not possible
with a simple compare.
7.20.5 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.20.5.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) uses the IRC as the clock source.
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7.21 Analog peripherals
7.21.1 Analog-to-Digital Converter (ADC0/1)
Remark: The LPC435x/3x/2x/1x contain two 10-bit ADCs.
7.21.1.1 Features
• 10-bit successive approximation analog to digital converter.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 to VDDA.
• Sampling frequency up to 400 kSamples/s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
• Individual result registers for each A/D channel to reduce interrupt overhead.
• DMA support.
7.21.2 Digital-to-Analog Converter (DAC)
7.21.2.1 Features
• 10-bit resolution
• Monotonic by design (resistor string architecture)
• Controllable conversion speed
• Low power consumption
7.22 Peripherals in the RTC power domain
7.22.1 RTC
The Real Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses little power when the CPU does not access its
registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the
RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own
power supply pin, VBAT.
7.22.1.1 Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.
• Ultra-low power design to support battery powered systems. Uses power from the
CPU power supply when it is present.
• Dedicated battery power supply pin.
• RTC power supply is isolated from the rest of the chip.
• Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.
• Periodic interrupts can be generated from increments of any field of the time registers.
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• Alarm interrupt can be generated for a specific date/time.
7.22.1.2 Event monitor/recorder
The event monitor/recorder allows recording and creating a time stamp of events related
to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the
event monitor/recorder stores records of such events. The event recorder can be
powered by the backup battery.
The event monitor/recorder can monitor the integrity of the device and record any
tampering events.
Features
• Supports three digital event inputs in the VBAT power domain.
• An event is defined as a level change at the digital event inputs.
• For each event channel, two timestamps mark the first and the last occurrence of an
event. Each channel also has a dedicated counter tracking the total number of events.
Timestamp values are taken from the RTC.
• Runs in VBAT power domain, independent of system power supply. The
event/recorder/monitor can therefore operate in Deep power-down mode.
• Low power consumption.
• Interrupt available if system is running.
• A qualified event can be used as a wake-up trigger.
• State of event interrupts accessible by software through GPIO.
7.22.2 Alarm timer
The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating
alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00
and asserts an interrupt if enabled.
The alarm timer is part of the RTC power domain and can be battery powered.
7.23 System control
7.23.1 Configuration registers (CREG)
The following settings are controlled in the configuration register block:
• BOD trip settings
• Oscillator output
• DMA-to-peripheral muxing
• Ethernet mode
• Memory mapping
• Timer/USART inputs
• Enabling the USB controllers
In addition, the CREG block contains the part identification and part configuration
information.
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7.23.2 System Control Unit (SCU)
The system control unit determines the function and electrical mode of the digital pins. By
default function 0 is selected for all pins with pull-up enabled. For pins that support a
digital and analog function, the ADC function select registers in the SCU enable the
analog function.
A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are
located on separate pads and are not controlled through the SCU.
In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that
select the pin interrupts are located in the SCU.
7.23.3 Clock Generation Unit (CGU)
The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be
unrelated in frequency and phase and can have different clock sources within the CGU.
One CGU base clock is routed to the CLKOUT pins. The base clock that generates the
CPU clock is referred to as CCLK.
Multiple branch clocks are derived from each base clock. The branch clocks offer flexible
control for power-management purposes. All branch clocks are outputs of one of two
Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase.
7.23.4 Internal RC oscillator (IRC)
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1.5 %
accuracy for Tamb = 0 °C to 85 °C and 3% accuracy for Tamb = -40 °C to 0 °C and Tamb
85 °C to 105 °C.
=
Upon power-up or any chip reset, the LPC435x/3x/2x/1x use the IRC as the clock source.
The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and
PLL0USB or PLL0AUDIO as needed if an external boot source is selected.
7.23.5 PLL0USB (for USB0)
PLL0 is a dedicated PLL for the USB0 High-speed controller.
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
7.23.6 PLL0AUDIO (for audio)
The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This
PLL accepts an input clock frequency derived from an external oscillator or internal IRC.
The input frequency is multiplied up to a high frequency with a Current Controlled
Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the
desired output frequency. The output frequency can be set as a multiple of the sampling
frequency fs to 32fs, 64fs, 128 fs, 256 fs, 384 fs, 512 fs and the sampling
frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz.
Many other frequencies are possible as well using the integrated fractional divider.
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7.23.7 System PLL1
The PLL1 accepts an input clock frequency from an external oscillator in the range of
1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz. This range is possible through an
additional divider in the loop to keep the CCO within its frequency range while the PLL is
providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,
or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset. After reset, software can enable the PLL. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a
clock source. The PLL settling time is 100 s.
7.23.8 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC435x/3x/2x/1x.
7.23.9 Power Management Controller (PMC)
The PMC controls the power to the cores, peripherals, and memories.
The LPC435x/3x/2x/1x support the following power modes in order from highest to lowest
power consumption:
1. Active mode
2. Sleep mode
3. Power-down modes:
a. Deep-sleep mode
b. Power-down mode
c. Deep power-down mode
Active mode and sleep mode apply to the state of the core. In a dual-core system, either
core can be in active or sleep mode independently of the other core.
If the core is in Active mode, it is fully operational and can access peripherals and
memories as configured by software. If the core is in Sleep mode, it receives no clocks,
but peripherals and memories remain running.
Either core can enter sleep mode from active mode independently of the other core and
while the other core remains in active mode or is in sleep mode.
Power-down modes apply to the entire system. In the Power-down modes, both cores and
all peripherals except for peripherals in the always-on power domain are shut down.
Memories can remain powered for retaining memory contents as defined by the individual
power-down mode.
Either core in active mode can put the part into one of the three power down modes if the
core is enabled to do so. If both cores are enabled for putting the system into power-down,
then the system enters power-down only once both cores have received a WFI or WFE
instruction.
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Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The
interrupt is captured in the NVIC and an event is captured in the Event router. Both cores
can wake up from sleep mode independently of each other.
Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down,
is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.
When waking up from Deep power-down mode, the part resets and attempts to boot.
7.23.10 Power control
The LPC435x/3x/2x/1x feature several independent power domains to control power to
the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain. The main regulator or a battery supply can
power the RTC. A power selector switch ensures that the RTC block is always powered
on.
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LPC43xx
VDDIO
to I/O pads
to cores
VSS
REGULATOR
to memories,
peripherals,
oscillators,
PLLs
VDDREG
MAIN POWER DOMAIN
to RTC
ULTRA LOW-POWER
REGULATOR
domain
VBAT
peripherals
RESET
WAKEUP0/1/2/3
RESET/WAKE-UP
to RTC I/O
pads (V
CONTROL
)
ps
BACKUP REGISTERS
REAL-TIME CLOCK
RTCX1
RTCX2
32 kHz
OSCILLATOR
ALARM
ALWAYS-ON/RTC POWER DOMAIN
DAC
VDDA
VSSA
ADC
ADC POWER DOMAIN
OTP
VPP
OTP POWER DOMAIN
USB0_VDDA3V_DRIVER
USB0_VDDA3V3
USB0
USB0 POWER DOMAIN
002aag378
Fig 9. Power domains
7.23.11 Code security (Code Read Protection - CRP)
CRP enables different levels of security so that access to the on-chip flash and use of the
JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by CRP.
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32-bit ARM Cortex-M4/M0 microcontroller
There are three levels of the Code Read Protection:
• In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are
allowed (excluding flash sector 0) using a limited set of the ISP commands. This level
is useful when CRP is required and flash field updates are needed. CRP1 does
prevent the user code from erasing all sectors.
• In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and
update using a reduced set of the ISP commands is allowed.
• In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This
mode also disables the ISP override using P2_7 pin. If necessary, the application
code must provide a flash update mechanism using the IAP calls or using the
reinvoke ISP command to enable flash update via USART0. See Table 5.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
7.24 Serial Wire Debug/JTAG
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watch points.
Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only,
The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM
Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0
cores separately or both cores simultaneously.
Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the
RGU block.
LPC43xx
TCK
TMS
TRST
TDI
TCK
TMS
TRST
TDI
ARM Cortex-M4
TCK
TMS
TRST
TDI
ARM Cortex-M0
TDO
TDO
JTAG ID = 0x4BA0 0477
JTAG ID = 0x0BA0 1477
TDO
DBGEN
RESET
DBGEN = HIGH
RESET = HIGH
002aah448
Fig 10. Dual-core debug configuration
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8. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions
Min
Max
Unit
VDD(REG)(3V3) regulator supply voltage on pin VDDREG
(3.3 V)
0.5
3.6
V
VDD(IO)
input/output supply
voltage
on pin VDDIO
0.5
0.5
3.6
3.6
V
V
VDDA(3V3)
analog supply voltage
(3.3 V)
on pin VDDA
VBAT
battery supply voltage
on pin VBAT
on pin VPP
0.5
0.5
3.6
3.6
V
V
Vprog(pf)
polyfuse programming
voltage
[2]
VI
input voltage
when VDD(IO) 2.4 V
0.5
0.5
5.5
V
V
5 V tolerant digital I/O pins
ADC/DAC pins and digital I/O
pins configured for an analog
function
VDDA(3V3)
USB0 pins USB0_DP;
USB0_DM;USB0_VBUS
0.3
0.3
0.3
5.25
3.6
V
V
V
USB0 pins USB0_ID;
USB0_RREF
USB1 pins USB1_DP and
USB1_DM
5.25
IDD
supply current
per supply pin
-
-
-
100
100
100
mA
mA
mA
ISS
ground current
I/O latch-up current
per ground pin
Ilatch
(0.5VDD(IO)) < VI < (1.5VDD(IO));
Tj < 125 C
[3]
[4]
Tstg
storage temperature
65
+150
1.5
C
Ptot(pack)
total power dissipation
(per package)
based on package heat transfer,
not device power consumption
-
W
VESD
electrostatic discharge
voltage
human body model; all pins
-
2000
V
[1] The following applies to the limiting values:
a) Absolute maximum ratings state the extreme limits that the product can withstand without leading to irrecoverable failure. Failure
includes the loss of reliability and shorter lifetime of the device. Conditions for functional operation of the part are shown in Table 11
“Static characteristics”.
b) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Dependent on package type.
[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = Tamb + PD Rth j – a
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 8.
Symbol
Tj(max)
Thermal characteristics
Parameter
Conditions Min
Typ
Max
Unit
maximum junction
temperature
-
-
-
125
C
Table 9.
Thermal resistance (LQFP packages)
Conditions
Symbol Parameter
Thermal resistance in C/W
±15 %
LQFP144
thermal resistance from JEDEC (4.5 in 4 in); still 38
LQFP208
Rth(j-a)
31
junction to ambient
air
Single-layer (4.5 in 3 in); 50
still air
39
10
Rth(j-c)
thermal resistance from -
junction to case
11
Table 10. Thermal resistance value (BGA packages)
Symbol Parameter Conditions
Thermal resistance in C/W ±15 %
LBGA256
TFBGA100
Rth(j-a)
thermal resistance from JEDEC (4.5 in 4 in); 29
46
junction to ambient
still air
8-layer (4.5 in 3 in); 24
still air
37
11
Rth(j-c)
thermal resistance from
junction to case
14
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10. Static characteristics
Table 11. Static characteristics
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Supply pins
VDD(IO)
[17]
[2]
input/output supply
voltage
2.4
2.4
-
-
3.6
3.6
V
V
VDD(REG)(3V3)
VDDA(3V3)
regulator supply voltage
(3.3 V)
analog supply voltage
(3.3 V)
on pin VDDA
2.4
3.0
-
3.6
3.6
V
V
on pins
3.3
USB0_VDDA3V3_
DRIVER and
USB0_VDDA3V3
[2]
[3]
VBAT
battery supply voltage
2.4
2.7
-
-
3.6
3.6
V
V
Vprog(pf)
polyfuse programming on pin VPP (for OTP)
voltage
Iprog(pf)
polyfuse programming on pin VPP; OTP
-
-
30
mA
current
programming time
1.6 ms
IDD(REG)(3V3)
regulator supply current Active mode; ARM
(3.3 V)
Cortex-M0 core in reset;
code
while(1){}
executed from RAM; all
peripherals disabled;
PLL1 enabled
[4]
[4]
[4]
[4]
[4]
CCLK = 12 MHz
CCLK = 60 MHz
CCLK = 120 MHz
CCLK = 180 MHz
CCLK = 204 MHz
-
10
28
51
74
83
-
-
-
-
-
mA
mA
mA
mA
mA
-
-
-
IDD(REG)(3V3)
regulator supply current after WFE/WFI instruction
(3.3 V)
executed from RAM; all
peripherals disabled;
ARM Cortex-M0 core in
reset
[4][5]
[4]
sleep mode
-
-
-
-
8.8
-
-
-
-
mA
A
A
A
deep-sleep mode
power-down mode
145
23
[4]
[4][6]
deep power-down
mode
0.05
[4]
[7]
deep power-down
mode; VBAT floating
-
-
3.0
-
A
IBAT
battery supply current
VBAT = 3.0 V;
0.1
nA
V
DD(REG)(3V3) = 3.3 V
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
[8]
IBAT
battery supply current
VDD(REG)(3V3) = 3.3 V;
V
BAT = 3.6 V
deep-sleep mode
power-down mode
-
-
1.5
1.5
-
-
A
A
[8]
[8]
deep power-down
mode
-
1.5
-
A
IBAT
battery supply current
Deep power-down mode;
RTC running;
V
DD(REG) = VDDA =
VDDIO = 0 V;
BAT = 3.3 V
V
-
-
3.0
-
A
VDD(REG)(3V3)
BAT = 3.3 V
=
V
1.5
-
-
-
-
-
A
A
A
A
IDD(IO)
I/O supply current
deep sleep mode
power-down mode
deep power-down mode
on pin VDDA;
-
-
-
-
< 0.1
< 0.1
< 0.1
0.4
[10]
IDDA
Analog supply current
deep sleep mode
power-down mode
A
A
[10]
[10]
-
-
0.4
-
-
deep power-down
mode
0.007
A
RESET pin
[9]
[9]
[9]
VIH
HIGH-level input
voltage
0.8 (Vps -
0.35)
5.5
V
VIL
LOW-level input voltage
0.5
-
-
0.3 (Vps V
0.1)
Vhys
hysteresis voltage
0.05 (Vps
0.35)
-
V
Standard I/O pins - normal drive strength
CI
input capacitance
-
-
-
2
-
pF
nA
ILL
LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
3
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
3
-
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
-
-
-
0.5
40
3
-
-
-
nA
nA
nA
IOZ
OFF-state output
current
VO = 0 V to VDD(IO);
on-chip pull-up/down
resistors disabled;
absolute value
VI
input voltage
pin configured to provide
a digital function;
0
0
-
-
5.5
3.6
V
V
VDD(IO) 2.4 V
V
DD(IO) = 0 V
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
VO
Parameter
Conditions
Min
Typ[1]
Max
VDD(IO)
5.5
Unit
V
output voltage
output active
0
-
-
VIH
HIGH-level input
voltage
0.7
VDD(IO)
V
VIL
LOW-level input voltage
0.5
-
0.3
V
VDD(IO)
Vhys
VOH
VOL
IOH
hysteresis voltage
0.1
VDD(IO)
-
-
V
HIGH-level output
voltage
IOH = 6 mA
VDD(IO)
0.4
-
-
V
LOW-level output
voltage
IOL = 6 mA
-
-
0.4
V
HIGH-level output
current
VOH = VDD(IO) 0.4 V
VOL = 0.4 V
6
6
-
-
-
mA
mA
mA
mA
A
IOL
LOW-level output
current
-
-
[11]
[11]
IOHS
IOLS
Ipd
HIGH-level short-circuit drive HIGH; connected to
output current ground
-
86.5
76.5
-
LOW-level short-circuit drive LOW; connected to
output current
-
-
VDD(IO)
[13]
[14]
[15]
pull-down current
VI = 5 V
-
93
[13]
[14]
[15]
Ipu
pull-up current
VI = 0 V
-
-
62
-
-
A
V
DD(IO) < VI 5 V
10
A
Rs
series resistance
on I/O pins with analog
function; analog function
enabled
200
I/O pins - high drive strength
CI
input capacitance
-
-
-
5.2
-
pF
nA
ILL
LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
3
IOZ
OFF-state output
current
VO = 0 V to VDD(IO)
;
-
3
-
nA
on-chip pull-up/down
resistors disabled;
absolute value
VI
input voltage
pin configured to provide
a digital function;
VDD(IO) 2.4 V
VDD(IO) = 0 V
0
0
0
-
-
-
-
5.5
V
V
V
V
3.6
VO
output voltage
output active
VDD(IO)
5.5
VIH
HIGH-level input
voltage
0.7
VDD(IO)
VIL
LOW-level input voltage
0.5
-
0.3
V
VDD(IO)
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Vhys
hysteresis voltage
0.1
-
-
V
VDD(IO)
[13]
[14]
[15]
Ipd
pull-down current
pull-up current
VI = VDD(IO)
-
62
-
-
A
A
[13]
[14]
[15]
Ipu
VI = 0 V
-
62
V
DD(IO) < VI 5 V
-
-
10
3
-
-
A
I/O pins - high drive strength: standard drive mode
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
VOH = VDD(IO) 0.4 V
-
0.6
65
-
-
-
-
nA
nA
mA
-
IOH
HIGH-level output
current
4
IOL
LOW-level output
current
VOL = 0.4 V
4
-
-
-
-
-
mA
mA
mA
[11]
[11]
IOHS
IOLS
HIGH-level short-circuit drive HIGH; connected to
output current ground
32
32
LOW-level short-circuit drive LOW; connected to
output current VDD(IO)
-
I/O pins - high drive strength: medium drive mode
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
3
-
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
VOH = VDD(IO) 0.4 V
-
0.7
70
-
-
-
-
nA
nA
mA
-
IOH
HIGH-level output
current
8
IOL
LOW-level output
current
VOL = 0.4 V
8
-
-
-
-
-
mA
mA
mA
[11]
[11]
IOHS
IOLS
HIGH-level short-circuit drive HIGH; connected to
output current ground
65
63
LOW-level short-circuit drive LOW; connected to
output current VDD(IO)
-
I/O pins - high drive strength: high drive mode
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
3
-
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
VOH = VDD(IO) 0.4 V
-
0.6
63
-
-
-
-
nA
nA
mA
-
IOH
HIGH-level output
current
14
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
IOL
LOW-level output
current
VOL = 0.4 V
14
-
-
mA
[11]
[11]
IOHS
IOLS
HIGH-level short-circuit drive HIGH; connected to
output current ground
-
-
-
-
113
110
mA
mA
LOW-level short-circuit drive LOW; connected to
output current VDD(IO)
I/O pins - high drive strength: ultra-high drive mode
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
3
-
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
VOH = VDD(IO) 0.4 V
-
0.6
63
-
-
-
-
nA
nA
mA
-
IOH
HIGH-level output
current
20
IOL
LOW-level output
current
VOL = 0.4 V
20
-
-
-
-
-
mA
mA
mA
[11]
[11]
IOHS
IOLS
HIGH-level short-circuit drive HIGH; connected to
output current ground
165
156
LOW-level short-circuit drive LOW; connected to
-
output current
VDD(IO)
I/O pins - high-speed
CI
input capacitance
-
-
-
2
-
pF
nA
ILL
LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
3
ILH
HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
3
-
nA
VI = 5 V; Tamb = 25 °C
VI = 5 V; Tamb = 105 °C
-
-
-
0.5
40
3
-
-
-
nA
nA
nA
IOZ
OFF-state output
current
VO = 0 V to VDD(IO);
on-chip pull-up/down
resistors disabled;
absolute value
VI
input voltage
pin configured to provide
a digital function;
VDD(IO) 2.4 V
VDD(IO) = 0 V
0
0
0
-
-
-
-
5.5
V
V
V
V
3.6
VO
output voltage
output active
VDD(IO)
5.5
VIH
HIGH-level input
voltage
0.7
VDD(IO)
VIL
LOW-level input voltage
0.5
-
-
0.3
VDD(IO)
V
V
Vhys
hysteresis voltage
0.1
-
VDD(IO)
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VOH
HIGH-level output
voltage
IOH = 8 mA
VDD(IO)
0.4
-
-
V
VOL
IOH
IOL
LOW-level output
voltage
IOL = 8 mA
-
-
0.4
-
V
HIGH-level output
current
VOH = VDD(IO) 0.4 V
VOL = 0.4 V
8
8
-
-
mA
mA
mA
mA
A
LOW-level output
current
-
-
[11]
[11]
IOHS
IOLS
Ipd
HIGH-level short-circuit drive HIGH; connected to
output current ground
-
86
76
-
LOW-level short-circuit drive LOW; connected to
output current
-
-
VDD(IO)
[13]
[14]
[15]
pull-down current
VI = VDD(IO)
-
62
[13]
[14]
[15]
Ipu
pull-up current
VI = 0 V
-
-
62
-
A
A
V
DD(IO) < VI 5 V
0
-
-
Open-drain I2C0-bus pins
VIH
HIGH-level input
voltage
0.7
VDD(IO)
-
V
V
V
V
VIL
LOW-level input voltage
0.5
0.14
0.3
VDD(IO)
Vhys
VOL
ILI
hysteresis voltage
0.1
VDD(IO)
-
-
-
LOW-level output
voltage
IOLS = 3 mA
-
0.4
[12]
input leakage current
VI = VDD(IO)
VI = 5 V
-
-
4.5
-
-
A
A
10
Oscillator pins
Vi(XTAL1)
input voltage on pin
XTAL1
0.5
0.5
-
-
-
-
1.2
1.2
0.8
V
Vo(XTAL2)
Cio
output voltage on pin
XTAL2
V
[16]
input/output
capacitance
pF
USB0 pins[17]
VI
input voltage
on pins USB0_DP;
USB0_DM; USB0_VBUS
VDD(IO) 2.4 V
VDD(IO) = 0 V
0
-
5.25
3.6
80
V
0
-
V
Rpd
pull-down resistance
on pin USB0_VBUS
48
64
k
LPC435X_3X_2X_1X
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Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
50
800
Typ[1]
200
-
Max
500
Unit
mV
mV
VIC
common-mode input
voltage
high-speed mode
full-speed/low-speed
mode
2500
chirp mode
50
-
600
mV
mV
Vi(dif)
differential input voltage
100
400
1100
USB1 pins (USB1_DP/USB1_DM)[17]
[17]
[18]
IOZ
OFF-state output
current
0 V < VI < 3.3 V
-
-
10
A
VBUS
VDI
bus supply voltage
-
-
-
5.25
-
V
V
differential input
(D+) (D)
0.2
sensitivity voltage
VCM
differential common
mode voltage range
includes VDI range
0.8
0.8
-
-
2.5
2.0
V
V
Vth(rs)se
single-ended receiver
switching threshold
voltage
VOL
LOW-level output
voltage for
low-/full-speed
RL of 1.5 k to 3.6 V
RL of 15 k to GND
-
-
-
0.18
3.5
V
V
VOH
HIGH-level output
voltage (driven) for
low-/full-speed
2.8
Ctrans
ZDRV
transceiver capacitance pin to GND
-
-
-
20
pF
[19]
driver output
with 33 series resistor;
steady state drive
36
44.1
impedance for driver
which is not high-speed
capable
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Special conditions for VDD(REG)(3V3) apply
when writing to the flash and EEPROM. See Table 14 and Table 15.
[3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure
the same ramp-up time for both supply voltages.
[4]
VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb = 25 C.
[5] PLL1 disabled; IRC running; CCLK = 12 MHz.
[6] VBAT = 3.6 V.
[7] Tamb = -40 C to +105 C; VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 204 MHz; in active mode, sleep
mode; deep-sleep mode, power-down mode, and deep power-down mode.
[8] On pin VBAT; Tamb = 25 C.
[9] Vps corresponds to the output of the power switch (see Table 9) which is determined by the greater of VBAT and VDD(Reg)(3V3)
.
[10] VDDA(3V3) = 3.3 V; Tamb = 25 C.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[12] To VSS
.
[13] The values specified are simulated and absolute values.
[14] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.
[15] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO)
.
LPC435X_3X_2X_1X
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[16] The parameter value specified is a simulated value excluding bond capacitance.
[17] For USB operation 3.0 V VDD((IO) 3.6 V. Guaranteed by design.
[18] VDD(IO) present.
[19] Includes external resistors of 33 1 % on D+ and D.
10.1 Power consumption
aaa-013450
100
I
DD(REG)(3V3)
(mA)
204 MHz
80
60
40
20
180 MHz
120 MHz
60 MHz
12 MHz
2.8
0
2.2
2.4
2.6
3
3.2
3.4
3.6
V
(V)
DD(REG)(3V3)
Conditions: Tamb = 25 C; executing code while (1){} from SRAM; M0 core in reset; system PLL
enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled.
Fig 11. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active
mode
aaa-013449
100
I
DD(REG)(3V3)
(mA)
204 MHz
180 MHz
80
60
40
20
120 MHz
60 MHz
12 MHz
20
0
-40
-20
0
40
60
80
100
120
temperature (°C)
Conditions: VDD(REG)(3V3) = 3.3 V; executing code while (1){} from SRAM; M0 core in reset; system
PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled.
Fig 12. Typical supply current versus temperature in active mode
LPC435X_3X_2X_1X
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aaa-013452
100
DD(REG)(3V3)
(mA)
+105 °CCC
+90 °CC
+25 °CC
0 °CCC
I
80
60
40
20
0
-40 °CC
12
36
60
84
108
132
156
180
204
frequency (MHz)
Conditions: active mode entered executing code while (1){} from SRAM; M0 core in reset;
VDD(REG)(3V3) = 3.3 V; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral
clocks disabled.
Fig 13. Typical supply current versus core frequency in active mode; code executed from
SRAM
aaa-013047
20
I
DD(REG)(3V3)
(mA)
15
10
5
0
-40
-20
0
20
40
60
80
100
120
temperature (°C)
Conditions: VDD(REG)(3V3) = 3.3 V; internal pull-up resistors disabled; M0 core in reset; system PLL
disabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. CCLK = 12 MHz.
Fig 14. Typical supply current versus temperature in sleep mode
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002aah410
002aah412
1.6
300
DD(REG)(3V3)
(μA)
I
I
DD(REG)(3V3)
(mA)
240
180
120
60
1.2
0.8
0.4
0
0
-40
0
40
80
temperature (°C)
120
-40
0
40
80
120
temperature (°C)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.
Fig 15. Typical supply current versus temperature in
Deep-sleep mode
Fig 16. Typical supply current versus temperature in
Power-down mode
002aah424
002aah415
25
30
I
/I
IBBAATT
BAT
(μA)
DD(REG)(3V3) BAT
25
20
15
10
5
20
15
10
5
I
DD(REG)(3V3)
BAT
I
0
0
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
temperature (°C)
temperature (°C)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. VBAT
VDD(REG)(3V3) + 0.4 V.
=
Conditions: VBAT = 3.6 V. VDD(REG)(3V3) not present.
Fig 17. Typical supply current versus temperature in
Deep power-down mode
Fig 18. Typical battery supply current versus
temperature
LPC435X_3X_2X_1X
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002aah379
100
I
BAT
(μA)
80
60
40
20
0
-0.4
-0.2
0
0.2
0.4
0.6
V
BAT
- V
(V)
DD(REG)(3V3)
Conditions: VDD(REG)(3V3) = 3.0 V; VBAT = 2.6 V to 3.6 V; CCLK = 12 MHz.
Remark: The recommended operating condition for the battery supply is
VDD(REG)(3V3) > VBAT + 0.2 V.
Fig 19. Typical battery supply current in Active mode
10.2 Peripheral power consumption
The typical power consumption at T = 25 C for each individual peripheral is measured as
follows:
1. Enable all branch clocks and measure the current IDD(REG)(3V3)
.
2. Disable the branch clock to the peripheral to be measured and keep all other branch
clocks enabled.
3. Calculate the difference between measurement 1 and 2. The result is the peripheral
power consumption.
Table 12. Peripheral power consumption
Peripheral
Branch clock
IDD(REG)(3V3) in mA
Branch clock
Branch clock
frequency = 48 MHz
frequency = 96 MHz
M0 core
I2C1
CLK_M4_M0APP
CLK_APB3_I2C1
CLK_APB1_I2C0
CLK_APB3_DAC
CLK_APB3_ADC0
CLK_APB3_ADC1
CLK_APB3_CAN0
CLK_APB1_CAN1
CLK_APB1_MOTOCON
CLK_APB1_I2S
3.3
6.6
0.01
< 0.01
0.01
0.07
0.07
0.17
0.16
0.04
0.09
1.14
0.01
0.02
0.02
0.07
0.07
0.17
0.15
0.04
0.08
2.29
I2C0
DAC
ADC0
ADC1
CAN0
CAN1
MOTOCON
I2S
SPIFI
CLK_SPIFI,
CLK_M4_SPIFI
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Table 12. Peripheral power consumption
Peripheral
Branch clock
IDD(REG)(3V3) in mA
Branch clock
Branch clock
frequency = 48 MHz
frequency = 96 MHz
GPIO
CLK_M4_GPIO
0.72
0.91
1.06
0.24
1.43
1.82
2.15
0.43
LCD
CLK_M4_LCD
ETHERNET
UART0
CLK_M4_ETHERNET
CLK_M4_UART0,
CLK_APB0_UART0
UART1
UART2
UART3
CLK_M4_UART1,
CLK_APB0_UART1
0.24
0.26
0.27
0.43
0.5
CLK_M4_UART2,
CLK_APB2_UART2
CLK_M4_USART3,
CLK_APB2_UART3
0.45
TIMER0
TIMER1
TIMER2
TIMER3
SDIO
CLK_M4_TIMER0
CLK_M4_TIMER1
CLK_M4_TIMER2
CLK_M4_TIMER3
0.08
0.09
0.1
0.15
0.15
0.19
0.16
1.17
0.08
0.66
CLK_M4_SDIO,
CLK_SDIO
SCTimer/PWM
SSP0
CLK_M4_SCT
0.66
0.13
1.3
CLK_M4_SSP0,
0.23
CLK_APB0_SSP0
SSP1
CLK_M4_SSP1,
0.14
0.27
CLK_APB2_SSP1
DMA
CLK_M4_DMA
CLK_M4_WWDT
CLK_M4_QEI
1.81
0.03
0.28
1.9
3.61
0.09
0.55
3.9
WWDT
QEI
USB0
CLK_M4_USB0,
CLK_USB0
USB1
CLK_M4_USB1,
CLK_USB1
3.02
5.69
RITIMER
EMC
CLK_M4_RITIMER
0.05
3.94
0.1
CLK_M4_EMC,
7.95
CLK_M4_EMC_DIV
SCU
CLK_M4_SCU
0.1
0.21
0.7
CREG
CLK_M4_CREG
CLK_M4_FLASHA
CLK_M4_FLASHB
CLK_PERIPH_SGPIO
CLK_SPI
0.35
1.47
1.4
Flash bank A
Flash bank B
SGPIO
2.97
2.84
0.17
0.11
0.1
SPI
0.07
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10.3 Electrical pin characteristics
002aah368
002aah359
3.6
3.2
2.8
2.4
2
3.6
V
V
OH
(V)
OH
(V)
-40 °C
3.2
2.8
2.4
2
+25 °C
+85 °C
+105 °C
-40 °C
+25 °C
+85 °C
+105 °C
0
16
32
48
64
80
96
0
6
12
18
24
30
36
I
(mA)
I
(mA)
OH
OH
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V.
Fig 20. Standard I/O pins; typical LOW level output
current IOL versus LOW level output voltage
VOL
Fig 21. Standard I/O pins; typical HIGH level output
voltage VOH versus HIGH level output current
IOH
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002aah360
-40 °C
+25 °C
+85 °C
+105 °C
002aah361
15
25
-40 °C
I
I
OL
(mA)
OL
+25 °C
+85 °C
+105 °C
(mA)
12
9
20
15
10
5
6
3
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
(V)
0.6
V
(V)
V
OL
OL
Conditions:VDD(REG)(3V3) = VDD(IO) = 3.3 V;normal-drive;
EHD = 0x0.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;
medium-drive; EHD = 0x1.
002aah362
002aah363
40
60
45
30
15
0
-40 °C
-40 °C
I
I
OL
(mA)
OL
+25 °C
+25 °C
+85 °C
+105 °C
(mA)
+85 °C
+105 °C
32
24
16
8
0
0
0.1
0.2
0.3
0.4
0.5
(V)
0.6
0
0.1
0.2
0.3
0.4
0.5
(V)
0.6
V
V
OL
OL
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive;
EHD = 0x2.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra
high-drive; EHD = 0x3.
Fig 22. High-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL
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002aah364
002aah367
3.6
3.6
V
V
OH
(V)
OH
(V)
-40 °C
-40 °C
3.2
2.8
2.4
2
3.2
2.8
2.4
2
+25 °C
+85 °C
+105 °C
+25 °C
+85 °C
+105 °C
0
4
8
12
16
20
24
0
8
16
24
32
40
48
I
(mA)
I
(mA)
OH
OH
Conditions:VDD(REG)(3V3) = VDD(IO) = 3.3 V;normal-drive;
EHD = 0x0.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V;
medium-drive; EHD = 0x1.
002aah368
002aah369
3.6
3.6
3.2
2.8
2.4
2
V
OH
(V)
V
OH
(V)
-40 °C
-40 °C
3.2
2.8
2.4
2
+25 °C
+85 °C
+105 °C
+25 °C
+85 °C
+105 °C
0
16
32
48
64
80
96
0
20
40
60
80
100
120
I
(mA)
I
(mA)
OH
OH
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive;
EHD = 0x2.
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra
high-drive; EHD = 0x3.
Fig 23. High-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH
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002aah422
20
0
Ipu
pu
(μA)
+105 °CCC
+25 °CC
-40 °CC
-20
-40
-60
-80
0
1
2
3
4
5
VI (V)
Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature.
Fig 24. Pull-up current Ipu versus input voltage VI
002aah418
120
Ipd
pd
(μA)
-40 °CC
90
60
30
0
+25 °CC
+105 °CCC
0
1
2
3
4
5
V (V)
I
Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature.
Fig 25. Pull-down current Ipd versus input voltage VI
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10.4 BOD and band gap static characteristics
Table 13. BOD static characteristics[1]
Tamb = 25 C; simulated values for nominal processing.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage interrupt level 2
assertion
-
-
2.95
3.03
-
-
V
V
de-assertion
interrupt level 3
assertion
-
-
3.05
3.13
-
-
V
V
de-assertion
reset level 2
assertion
-
-
2.1
-
-
V
V
de-assertion
reset level 3
2.18
assertion
-
-
2.2
-
-
V
V
de-assertion
2.28
[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see
the LPC43xx user manual.
Table 14. Band gap characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Unit
[1]
Vref(bg)
band gap reference voltage
0.707
0.745
0.783
mV
[1] Based on characterization, not tested in production.
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32-bit ARM Cortex-M4/M0 microcontroller
11. Dynamic characteristics
11.1 Flash/EEPROM memory
Table 15. Flash characteristics
Tamb = 40 C to +105 C, unless otherwise specified. VDD(REG)(3V3) = 2.4 V to 3.6 V for read
operations; VDD(REG)(3V3) = 2.7 V to 3.6 V for erase/program operations.
Symbol Parameter
Nendu endurance
Conditions
Min
Typ
Max
Unit
[1]
sector erase/program
10000
1000
-
-
-
-
cycles
cycles
page erase/program; page
in large sector
page erase/program; page
in small sector
10000
-
-
cycles
tret
retention time powered
unpowered
10
10
-
-
-
-
-
years
years
ms
-
ter
erase time
page, sector, or multiple
consecutive sectors
100
[2]
tprog
programming
time
-
1
-
ms
[1] Number of erase/program cycles.
[2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash
in blocks of 512 bytes.
Table 16. EEPROM characteristics
Tamb = 40 C to +105 C; VDD(REG)(3V3) = 2.7 V to 3.6 V.
Symbol
fclk
Parameter
Conditions
Min
Typ
1500
-
Max
Unit
kHz
clock frequency
endurance
800
1600
Nendu
tret
100000
-
-
-
-
-
cycles
years
years
ns
retention time
Tamb = 40 C to +85 C
85 C < Tamb 105 C
read
20
10
-
-
-
ta
access time
120
1.99
erase/program;
fclk = 1500 kHz
-
ms
erase/program;
fclk = 1600 kHz
-
1.87
-
ms
[1]
[1]
[1]
[1]
[1]
twait
wait time
read; RPHASE1
read; RPHASE2
write; PHASE1
write; PHASE2
write; PHASE3
70
35
20
40
10
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
[1] See the LPC43xx user manual how to program the wait states for the different read (RPHASEx) and erase/program phases (PHASEx)
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11.2 Wake-up times
Table 17. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep
power-down modes
Tamb = 40 C to +105 C
Symbol Parameter
Conditions
Min
Typ[1]
3 Tcy(clk) 5 Tcy(clk)
Max Unit
[2]
twake
wake-up time from Sleep mode
-
-
ns
from Deep-sleep and
Power-down mode
12
51
s
from Deep power-down mode
after reset
-
-
200
200
-
-
μs
μs
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] Tcy(clk) = 1/CCLK with CCLK = CPU clock frequency.
11.3 External clock for oscillator in slave mode
Remark: The input voltage on the XTAL1/2 pins must be 1.2 V (see Table 11). For
connecting the oscillator to the XTAL pins, also see Section 13.2 and Section 13.4.
Table 18. Dynamic characteristic: external clock
Tamb = 40 C to +105 C; VDD(IO) over specified ranges.[1]
Symbol Parameter
Conditions
Min
Max
Unit
MHz
ns
fosc
oscillator frequency
1
25
Tcy(clk)
tCHCX
tCLCX
clock cycle time
clock HIGH time
clock LOW time
40
1000
Tcy(clk) 0.4
Tcy(clk) 0.4
Tcy(clk) 0.6
Tcy(clk) 0.6
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
t
CHCX
t
CLCX
T
cy(clk)
002aag698
Fig 26. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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11.4 Crystal oscillator
Table 19. Dynamic characteristic: oscillator
Tamb = 40 C to +105 C; VDD(IO) over specified ranges; 2.4 V VDD(REG)(3V3) 3.6 V.[1]
Symbol
Low-frequency mode (1-20 MHz)[5]
tjit(per) period jitter time
Parameter
Conditions
Min
Typ[2]
Max
Unit
[3][4]
[3][4]
5 MHz crystal
10 MHz crystal
15 MHz crystal
-
-
-
13.2
6.6
-
-
-
ps
ps
ps
4.8
High-frequency mode (20 - 25 MHz)[6]
tjit(per)
period jitter time
20 MHz crystal
25 MHz crystal
-
-
4.3
3.7
-
-
ps
ps
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[3] Indicates RMS period jitter.
[4] PLL-induced jitter is not included.
[5] Select HF = 0 in the XTAL_OSC_CTRL register.
[6] Select HF = 1 in the XTAL_OSC_CTRL register.
11.5 IRC oscillator
Table 20. Dynamic characteristic: IRC oscillator
2.4 V VDD(REG)(3V3) 3.6 V
Symbol Parameter
Conditions
Min
Typ[1 Max
]
Unit
fosc(RC) internal RC
oscillator
-40 C Tamb 0 C
0 C Tamb 85 C
12.0 - 3 %
12.0 12.0 + 3 %
MHz
12.0 - 1.5 % 12.0 12.0 + 1.5 % MHz
12.0 12.0 + 3 % MHz
frequency
85 C Tamb 105 C 12.0 - 3 %
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.6 RTC oscillator
See Section 13.3 for connecting the RTC oscillator to an external clock source.
Table 21. Dynamic characteristic: RTC oscillator
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V or 2.4 V VBAT 3.6 V[1]
Symbol Parameter
Conditions
Min
Typ[1]
32.768
280
Max
-
Unit
kHz
nA
fi
input frequency
-
-
ICC(osc)
oscillator supply
current
800
[1] Parameters are valid over operating temperature range unless otherwise specified.
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11.7 GPCLKIN
Table 22. Dynamic characteristic: GPCLKIN
Tamb = 25 C; 2.4 V VDD(REG)(3V3) 3.6 V
Symbol Parameter
GP_CLKIN input frequency
Min
Typ
Max
Unit
-
-
25
MHz
11.8 I/O pins
For I/O pins that are configured as input only, there is no limitation on the rise and fall
times.
Table 23. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +105 C; 2.7 V VDD(IO) 3.6 V.
Symbol Parameter Conditions
Min
Typ
Max Unit
Standard I/O pins - normal drive strength
[2][3]
[2][3]
[2][3]
[2][3]
tr
tf
tr
tf
rise time
fall time
rise time
fall time
pin configured as output; EHS = 1
pin configured as output; EHS = 1
pin configured as output; EHS = 0
pin configured as output; EHS = 0
1.0
0.9
1.9
1.9
-
-
-
-
2.5 ns
2.5 ns
4.3 ns
4.0 ns
I/O pins - high drive strength
[2][5]
[2][5]
[2][5]
[2][5]
[2][5]
[2][5]
[2][5]
[2][5]
tr
tf
tr
tf
tr
tf
tr
tf
rise time
fall time
rise time
fall time
rise time
fall time
rise time
fall time
pin configured as output; standard
drive mode (EHD = 0x0)
4.3
4.7
3.2
3.2
2.9
2.5
2.8
2.4
-
-
-
-
-
-
-
-
7.9 ns
8.7 ns
5.7 ns
5.5 ns
4.9 ns
3.9 ns
4.7 ns
3.4 ns
pin configured as output; standard
drive mode (EHD = 0x0)
pin configured as output; medium
drive mode (EHD = 0x1)
pin configured as output; medium
drive mode (EHD = 0x1)
pin configured as output; high drive
mode (EHD = 0x2)
pin configured as output; high drive
mode (EHD = 0x2)
pin configured as output; ultra-high
drive mode (EHD = 0x3)
pin configured as output; ultra-high
drive mode (EHD = 0x3)
I/O pins - high-speed
[2][3]
[2][3]
[2][3]
[2][3]
tr
tf
tr
tf
rise time
fall time
rise time
fall time
pin configured as output; EHS = 1
pin configured as output; EHS = 1
pin configured as output; EHS = 0
pin configured as output; EHS = 0
350
450
1.0
1.0
-
-
-
-
670 ps
730 ps
1.9 ns
2.0 ns
[1] Simulated data.
[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.
[3] The slew rate is configured in the system control block in the SFSP registers using the EHS bit. See the
LPC43xx user manual.
[4] CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.
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[5] The drive modes are configured in the system control block in the SFSP registers using the EHD bit. See
the LPC43xx user manual.
11.9 I2C-bus
Table 24. Dynamic characteristic: I2C-bus pins
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V.[1]
Symbol
Parameter
Conditions
Min
Max
100
400
1
Unit
kHz
kHz
MHz
ns
fSCL
SCL clock frequency
Standard-mode
Fast-mode
0
0
0
-
Fast-mode Plus
[3][4][5][6]
tf
fall time
of both SDA and
SCL signals
300
Standard-mode
Fast-mode
20 + 0.1 Cb
300
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
Fast-mode Plus
Standard-mode
Fast-mode
[2][3][7]
[8][9]
tHD;DAT
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up time
250
100
50
Fast-mode Plus
[1] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.
[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
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t
t
SU;DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 27. I2C-bus pins clock timing
11.10 I2S-bus interface
Table 25. Dynamic characteristics: I2S-bus interface pins
Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.
Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
common to input and output
tr
rise time
-
4
4
-
-
-
-
ns
ns
ns
tf
fall time
-
tWH
pulse width HIGH
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
36
tWL
pulse width LOW
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
36
-
-
ns
output
[1]
tv(Q)
data output valid time on pin I2Sx_TX_SDA
on pin I2Sx_TX_WS
-
-
4.4
4.3
-
-
ns
ns
input
[1]
[1]
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
on pin I2Sx_RX_WS
-
0
-
ns
ns
ns
ns
0.20
3.7
3.9
th(D)
data input hold time
on pin I2Sx_RX_SDA
on pin I2Sx_RX_WS
-
-
-
-
[1] Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface
PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns, corresponds to the SCK signal in the
I2S-bus specification.
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T
t
f
t
r
cy(clk)
I2Sx_TX_SCK
t
t
WL
WH
I2Sx_TX_SDA
I2Sx_TX_WS
t
v(Q)
002aag497
t
v(Q)
Fig 28. I2S-bus timing (transmit)
T
t
f
t
r
cy(clk)
I2Sx_RX_SCK
I2Sx_RX_SDA
I2Sx_RX_WS
t
t
WL
WH
t
t
t
su(D)
h(D)
002aag498
t
su(D)
h(D)
Fig 29. I2S-bus timing (receive)
11.11 USART interface
Table 26. USART dynamic characteristics
Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.
sampled at 10 % and 90 % of the signal level; EHS = 1 for all pins. Simulated values.
Symbol
Parameter
Min
Max
Unit
USART master (in synchronous mode)
tsu(D)
th(D)
tv(Q)
data input set-up time
26.6
0
-
ns
ns
ns
data input hold time
data output valid time
-
0
10.4
USART slave (in synchronous mode)
tsu(D)
th(D)
tv(Q)
data input set-up time
2.4
0
-
ns
ns
ns
data input hold time
data output valid time
-
4.3
24.3
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T
cy(clk)
SCLK (FES = 1)
SCLK (FES = 0)
TXD
t
t
v(Q)
v(Q)
START
START
BIT0
BIT1
t
h(D)
t
su(D)
BIT1
BIT0
RXD
aaa-016717
Fig 30. USART timing
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11.12 SSP interface
Table 27. Dynamic characteristics: SSP pins in SPI mode
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF; sampled at 10 % and 90 % of
the signal level; EHS = 1 for all pins. Simulated values.
Symbol Parameter
SSP master
Conditions
Min
Typ
Max
Unit
[1]
Tcy(clk)
clock cycle time
full-duplex mode
1/(25.5 106)
1/(51 106)
-
-
-
-
-
-
s
when only transmitting
-
s
tDS
data set-up time in SPI mode
data hold time in SPI mode
12.2
3.6
-
-
ns
ns
ns
tDH
tv(Q)
-
data output valid in SPI mode
time
6.7
th(Q)
tlead
data output hold in SPI mode
time
1.7
-
-
-
ns
ns
lead time
continuous transfer mode
T
cy(clk) + 3.3
Tcy(clk) + 8.2
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
0.5 Tcy(clk) + 3.3 -
Tcy(clk) + 3.3
0.5 Tcy(clk) + 8.2 ns
Tcy(clk) + 8.2 ns
SPI mode; CPOL = 1;
CPHA = 0
-
SPI mode; CPOL = 1;
CPHA = 1
0.5 Tcy(clk) + 3.3 -
0.5 Tcy(clk) + 3.3 -
0.5 Tcy(clk) + 8.2 ns
0.5 Tcy(clk) + 8.2 ns
synchronous serial
frame mode
microwire frame format
Tcy(clk) + 3.3
-
-
Tcy(clk) + 8.2
-
ns
ns
tlag
lag time
continuous transfer mode
0.5 Tcy(clk)
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
Tcy(clk)
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
SPI mode; CPOL = 1;
CPHA = 0
0.5 Tcy(clk)
Tcy(clk)
SPI mode; CPOL = 1;
CPHA = 1
synchronous serial
frame mode
Tcy(clk)
microwire frame format
0.5 Tcy(clk)
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Table 27. Dynamic characteristics: SSP pins in SPI mode
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF; sampled at 10 % and 90 % of
the signal level; EHS = 1 for all pins. Simulated values.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
td
delay time
continuous transfer mode
-
0.5 Tcy(clk)
-
ns
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
-
-
-
-
-
n/a
-
-
-
-
-
ns
ns
ns
ns
ns
SPI mode; CPOL = 1;
CPHA = 0
0.5 Tcy(clk)
n/a
SPI mode; CPOL = 1;
CPHA = 1
synchronous serial
frame mode
Tcy(clk)
n/a
microwire frame format
SSP slave
PCLK
Peripheral clock
frequency
-
-
204
MHz
[2]
Tcy(clk)
tDS
clock cycle time
1/(11 106)
-
-
-
-
-
-
-
s
data set-up time in SPI mode
data hold time in SPI mode
1.5
2
ns
ns
tDH
tv(Q)
data output valid in SPI mode
time
-
[4 (1/PCLK)] + 1 ns
th(Q)
tlead
data output hold in SPI mode
time
4.5
-
-
-
-
ns
ns
lead time
continuous transfer mode
Tcy(clk)
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
0.5 Tcy(clk)
Tcy(clk)
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
SPI mode; CPOL = 1;
CPHA = 0
SPI mode; CPOL = 1;
CPHA = 1
0.5 Tcy(clk)
0.5 Tcy(clk)
Tcy(clk)
synchronous serial
frame mode
microwire frame format
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Table 27. Dynamic characteristics: SSP pins in SPI mode
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF; sampled at 10 % and 90 % of
the signal level; EHS = 1 for all pins. Simulated values.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tlag
lag time
continuous transfer mode
0.5 x Tcy(clk) + 1.5 -
-
ns
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
Tcy(clk) + 1.5
-
-
-
-
-
ns
ns
ns
ns
SPI mode; CPOL = 1;
CPHA = 0
0.5 Tcy(clk) + 1.5 -
SPI mode; CPOL = 1;
CPHA = 1
Tcy(clk) + 1.5
Tcy(clk) + 1.5
-
-
synchronous serial
frame mode
microwire frame format
0.5 Tcy(clk)
-
-
-
ns
ns
td
delay time
continuous transfer mode
-
0.5 Tcy(clk)
SPI mode; CPOL = 0;
CPHA = 0
SPI mode; CPOL = 0;
CPHA = 1
-
-
-
-
-
n/a
-
-
-
-
-
ns
ns
ns
ns
ns
SPI mode; CPOL = 1;
CPHA = 0
0.5 Tcy(clk)
n/a
SPI mode; CPOL = 1;
CPHA = 1
synchronous serial
frame mode
Tcy(clk)
n/a
microwire frame format
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] Tcy(clk) 12 Tcy(PCLK)
.
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11.13 SPI interface
Table 28. Dynamic characteristics: SPI
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Simulated values.
Symbol Parameter
Conditions
Min
5
Typ
Max
Unit
ns
Tcy(PCLK) PCLK cycle time
[1]
Tcy(clk)
Master
tDS
clock cycle time
40
-
-
ns
data set-up time
7.2
-
-
-
-
-
ns
ns
ns
ns
tDH
data hold time
0
-
-
tv(Q)
th(Q)
Slave
tDS
data output valid time
data output hold time
3.7
1.2
-
data set-up time
1.2
-
-
-
-
-
-
ns
ns
tDH
data hold time
3 Tcy(PCLK) + 0.54
tv(Q)
th(Q)
data output valid time
data output hold time
-
-
3 Tcy(PCLK) + 9.7 ns
2 Tcy(PCLK) + 7.1 ns
[1] Tcy(clk) = 8/BASE_SPI_CLK. Tcy(PCLK) = 1/BASE_SPI_CLK.
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11.14 SSP/SPI timing diagrams
T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
d
t
lag
t
SSEL
lead
MOSI (CPHA = 0)
MISO (CPHA = 0)
t
t
h(Q)
v(Q)
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
IDLE
t
t
DH
DS
DATA VALID
DATA VALID
DATA VALID (LSB)
MOSI (CPHA = 1)
MISO (CPHA = 1)
t
t
h(Q)
v(Q)
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
DATA VALID (LSB)
DATA VALID
t
t
DH
DS
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
DATA VALID
aaa-013462
Fig 31. SSP in SPI mode and SPI master timing
LPC435X_3X_2X_1X
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T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
d
t
lag
t
SSEL
lead
MISO (CPHA = 0)
MOSI (CPHA = 0)
t
t
h(Q)
v(Q)
IDLE
IDLE
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
t
t
DH
DS
DATA VALID (MSB)
DATA VALID
DATA VALID (LSB)
MISO (CPHA = 1)
MOSI (CPHA = 1)
t
t
h(Q)
v(Q)
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
DATA VALID
IDLE
IDLE
t
t
DH
DS
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
DATA VALID
aaa-014942
Fig 32. SSP in SPI mode and SPI slave timing
LPC435X_3X_2X_1X
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11.15 SPIFI
32-bit ARM Cortex-M4/M0 microcontroller
Table 29. Dynamic characteristics: SPIFI
Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. CL = 20 pF. Sampled
at 90 % and 10 % of the signal level. EHS = 1 for all pins. Simulated values.
Symbol
Tcy(clk)
tDS
Parameter
Min
9.6
3.2
0
Max
Unit
ns
clock cycle time
data set-up time
data hold time
-
-
ns
tDH
-
ns
tv(Q)
data output valid time
data output hold time
-
3.2
-
ns
th(Q)
0.6
ns
T
cy(clk)
SPIFI_SCK
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
SPIFI data out
SPIFI data in
t
t
DH
DS
DATA VALID
DATA VALID
002aah409
Fig 33. SPIFI timing (Mode 0)
11.16 SGPIO timing
The following considerations apply to SGPIO timing:
• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To
guarantee that no samples are missed, all input signals should have a duration of at
least one SGPIO_CLOCK cycle plus the set-up and hold times.
• When an external clock input is used to generate output data, synchronization causes
a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one
output every two SGPIO_CLOCK cycles.
• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling
several inputs. This may cause inputs with very similar timings to be sampled with a
difference of one SGPIO_CLOCK cycle.
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Table 30. Dynamic characteristics: SGPIO
Tamb = 40 C to +105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Simulated values.
Symbol Parameter
tsu(D) data input set-up time
th(D) data input hold time
data input set-up time sampled by
SGPIO_CLOCK
sampled by
SGPIO_CLOCK
Conditions
Min
Typ
Max
Unit
ns
2
-
-
-
-
-
-
[1]
[1]
TSGPIO + 2
TSGPIO + 2
ns
tsu(D)
ns
[1]
th(D)
data input hold time
TSGPIO + 2
-
-
ns
[1]
[1]
[1]
tv(Q)
th(Q)
tv(Q)
data output valid time
data output hold time
-
-
-
-
2 TSGPIO
ns
ns
ns
TSGPIO
-3
data output valid time sampled by
SGPIO_CLOCK
3
3
[1]
th(Q)
data output hold time sampled by
SGPIO_CLOCK
-3
-
ns
[1] SGPIO_CLOCK is the internally generated SGPIO clock. TSGPIO = 1/fSGPIO_CLOCK
.
SGPIO_CLOCK
CLKINext
t
h(D)
sync(CLKINext) = CLKINi
t
su(D)
DIN
DINi
sync(DIN)
DINi
t
v(Q)
CLKout
Dout
t
h(Q)
DQi
002aah668
Fig 34. SGPIO timing
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11.17 External memory interface
Table 31. Dynamic characteristics: Static asynchronous external memory interface
CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V;
2.7 V VDD(IO) 3.6 V; values guaranteed by design; the values in the table have been calculated with WAITTURN = 0x0 in
STATICWAITTURN register. Timing parameters are given for single memory access cycles. In a normal read operation, the
EMC changes the address while CS is asserted which results in multiple memory accesses.
Symbol
Read cycle parameters
Parameter[1]
Conditions
Min
Typ
Max
Unit
tCSLAV
CS LOW to address valid
time
3.1
-
-
1.6
ns
ns
[2]
[2]
tCSLOEL
CS LOW to OE LOW time
0.6 + Tcy(clk)
WAITOEN
1.3 + Tcy(clk)
WAITOEN
tCSLBLSL
tOELOEH
CS LOW to BLS LOW time PB = 1
OE LOW to OE HIGH time
0.7
-
-
1.8
ns
ns
[2]
0.6 +
0.4 +
(WAITRD
WAITOEN + 1)
(WAITRD
WAITOEN + 1)
Tcy(clk)
Tcy(clk)
tam
memory access time
data input hold time
-
-
16 +
ns
(WAITRD
WAITOEN +1)
Tcy(clk)
th(D)
16
-
-
-
-
-
-
ns
ns
ns
ns
ns
tCSHBLSH CS HIGH to BLS HIGH time PB = 1
0.4
0.4
2.0
2.0
1.9
1.4
2.6
0
tCSHOEH
tOEHANV
tCSHEOR
CS HIGH to OE HIGH time
OE HIGH to address invalid PB = 1
[3]
[4]
CS HIGH to end of read
time
tCSLSOR
CS LOW to start of read
time
0
-
-
1.8
ns
ns
Write cycle parameters
tCSLAV
CS LOW to address valid
time
3.1
3.1
1.6
1.5
tCSLDV
CS LOW to data valid time
CS LOW to WE LOW time
-
-
ns
ns
tCSLWEL
PB = 1
1.5 +
0.2 +
(WAITWEN + 1)
Tcy(clk)
(WAITWEN + 1)
Tcy(clk)
tCSLBLSL
tWELWEH
CS LOW to BLS LOW time PB = 1
WE LOW to WE HIGH time PB = 1
0.7
-
-
1.8
ns
ns
[2]
[2]
0.6 +
0.4 +
(WAITWR
WAITWEN + 1)
Tcy(clk)
(WAITWR
WAITWEN + 1)
Tcy(clk)
tWEHDNV
WE HIGH to data invalid
time
PB = 1
PB = 1
PB = 0
0.9 + Tcy(clk)
-
-
-
2.3 + Tcy(clk)
ns
ns
ns
[2]
[5]
tWEHEOW WE HIGH to end of write
time
0.4 + Tcy(clk)
0.3 + Tcy(clk)
tCSLBLSL
CS LOW to BLS LOW
0.7 +
1.8 +
(WAITWEN + 1)
Tcy(clk)
(WAITWEN + 1)
Tcy(clk)
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Table 31. Dynamic characteristics: Static asynchronous external memory interface …continued
CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V;
2.7 V VDD(IO) 3.6 V; values guaranteed by design; the values in the table have been calculated with WAITTURN = 0x0 in
STATICWAITTURN register. Timing parameters are given for single memory access cycles. In a normal read operation, the
EMC changes the address while CS is asserted which results in multiple memory accesses.
Symbol
Parameter[1]
Conditions
Min
Typ
Max
Unit
[2]
tBLSLBLSH BLS LOW to BLS HIGH time PB = 0
0.9 +
-
0.1 +
ns
(WAITWR
WAITWEN + 1)
Tcy(clk)
(WAITWR
WAITWEN + 1)
Tcy(clk)
[2]
[5]
tBLSHEOW BLS HIGH to end of write
time
PB = 0
PB = 0
1.9 + Tcy(clk)
2.5 + Tcy(clk)
2.0
-
-
-
-
-
0.5 + Tcy(clk)
1.4 + Tcy(clk)
0
ns
ns
ns
ns
ns
[2]
tBLSHDNV BLS HIGH to data invalid
time
[5]
tCSHEOW
CS HIGH to end of write
time
tBLSHDNV BLS HIGH to data invalid
time
PB = 1
2.5
1.4
tWEHANV
WE HIGH to address invalid PB = 1
time
0.9 + Tcy(clk)
2.4 + Tcy(clk)
[1] Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.
[2] Tcy(clk) = 1/CCLK (see LPC43xx User manual).
[3] End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH
[4] Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL
.
.
[5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.
EMC_An
t
CSLAV
t
CSHEOW
t
t
t
CSLAV
OEHANV
EMC_CSn
EMC_OE
t
CSLOEL
t
t
OELOEH
t
BLSHEOW
CSHOEH
t
t
CSLBLSL BLSLBLSH
EMC_BLSn
EMC_WE
t
CSLDV
am
t
t
CSHEOR
BLSHDNV
t
CSLSOR
t
h(D)
EMC_Dn
EOW
SOR
EOR
002aag699
Fig 35. External static memory read/write access (PB = 0)
LPC435X_3X_2X_1X
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EMC_An
t
CSLAV
t
t
t
CSLAV
OEHANV
t
CSHEOW
EMC_CSn
EMC_OE
t
CSLOEL
t
OELOEH
t
CSLBLSL
CSHOEH
t
CSLBLSL
EMC_BLSn
EMC_WE
t
CSHBLSH
t
t
CSLWEL WELWEH
t
WEHEOW
t
t
BLSHDNV
am
t
CSHEOR
t
CSLDV
t
t
h(D)
WEHDNV
t
CSLSOR
EMC_Dn
EOR
SOR
EOW
002aag700
Fig 36. External static memory read/write access (PB = 1)
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Table 32. Dynamic characteristics: Dynamic external memory interface
Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,
EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 105 C;
2.4 V VDD(REG)(3V3) 3.6 V; VDD(IO) =3.3 V 10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY
= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.
Symbol
Parameter
Min
Typ
Max
Unit
Tcy(clk)
clock cycle time
8.4
-
-
ns
Common to read and write cycles
td(DYCSV)
th(DYCS)
td(RASV)
th(RAS)
dynamic chip select valid delay time
-
3.1 + 0.5 Tcy(clk)
5.1 + 0.5 Tcy(clk) ns
ns
4.9 + 0.5 Tcy(clk) ns
ns
4.6 + 0.5 Tcy(clk) ns
ns
5.9 + 0.5 Tcy(clk) ns
ns
5.0 + 0.5 Tcy(clk) ns
ns
6.3 + 0.5 Tcy(clk) ns
ns
5.1 + 0.5 Tcy(clk) ns
dynamic chip select hold time
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write enable valid delay time
write enable hold time
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)
3.1 + 0.5 Tcy(clk)
0.5 + 0.5 Tcy(clk) 1.1 + 0.5 Tcy(clk)
2.9 + 0.5 Tcy(clk)
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)
3.2 + 0.5 Tcy(clk)
1.3 + 0.5 Tcy(clk) 1.4 + 0.5 Tcy(clk)
3.1 + 0.5 Tcy(clk)
0.2 + 0.5 Tcy(clk) 0.8 + 0.5 Tcy(clk)
3.8 + 0.5 Tcy(clk)
0.3 + 0.5 Tcy(clk) 0.9 + 0.5 Tcy(clk)
-
-
-
td(CASV)
th(CAS)
td(WEV)
th(WE)
-
-
-
-
td(DQMOUTV) DQMOUT valid delay time
-
th(DQMOUT)
td(AV)
DQMOUT hold time
address valid delay time
address hold time
-
-
th(A)
-
td(CKEOUTV) CKEOUT valid delay time
th(CKEOUT) CKEOUT hold time
Read cycle parameters
tsu(D) data input set-up time
th(D) data input hold time
Write cycle parameters
td(QV) data output valid delay time
th(Q) data output hold time
-
3.1 + 0.5 Tcy(clk)
0.7 + 0.5 Tcy(clk)
0.5 Tcy(clk)
-
ns
1.5
0.5
-
-
ns
ns
2.2
0.8
-
3.8 + 0.5 Tcy(clk)
0.7 + 0.5 Tcy(clk)
6.2 + 0.5 Tcy(clk) ns
ns
0.5 Tcy(clk)
-
Table 33. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0]
delay values
Tamb = 40 C to 105 C; VDD(IO) =3.3 V 10 %; 2.4 V VDD(REG)(3V3) 3.6 V.
Symbol Parameter
td delay time
Conditions
delay value
Min
Typ
Max
Unit
[1]
CLKn_DELAY = 0
CLKn_DELAY = 1
CLKn_DELAY = 2
CLKn_DELAY = 3
CLKn_DELAY = 4
CLKn_DELAY = 5
CLKn_DELAY = 6
CLKn_DELAY = 7
0.0
0.4
0.7
1.1
1.4
1.7
2.1
2.5
0.0
0.5
1.0
1.6
2.0
2.6
3.1
3.6
0.0
0.8
1.7
2.5
3.3
4.1
4.9
5.8
ns
ns
ns
ns
ns
ns
ns
ns
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1] Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual).
The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =
CLK2_DELAY = CLK3_DELAY.
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EMC_CLKn
delay > 0
EMC_CLKn delay t ; programmable CLKn_DELAY
d
T
cy(clk)
EMC_CLKn
delay = 0
t
- t
d
t
- t
d
d(xV)
h(x)
t
t
EMC_DYCSn,
EMC_RAS,
d(xV)
h(x)
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
t
- t
d
t
- t
d
d(QV)
h(Q)
t
d(QV)
t
h(Q)
EMC_D[31:0]
write
t
t
su(D)
h(D)
EMC_D[31:0]
read; delay > 0
t
t
su(D)
h(D)
EMC_D[31:0]
read; delay = 0
002aag703
For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 31.
Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK
register.
Fig 37. SDRAM timing
LPC435X_3X_2X_1X
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11.18 USB interface
Table 34. Dynamic characteristics: USB0 and USB1 pins (full-speed)
CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO), unless otherwise specified; 3.0 V VDD(IO) 3.6 V.
Symbol
Parameter
rise time
fall time
Conditions
10 % to 90 %
10 % to 90 %
tr / tf
Min
4.0
4.0
90
Typ
Max
Unit
ns
tr
-
-
-
20.0
tf
20.0
ns
tFRFM
differential rise and fall time
matching
111.11
%
VCRS
output signal crossover voltage
source SE0 interval of EOP
1.3
160
2
-
-
-
2.0
175
+5
V
tFEOPT
tFDEOP
see Figure 38
ns
ns
source jitter for differential transition see Figure 38
to SE0 transition
tJR1
receiver jitter to next transition
18.5
9
-
-
-
+18.5
ns
ns
ns
tJR2
receiver jitter for paired transitions
EOP width at receiver
10 % to 90 %
+9
-
[1]
[1]
tEOPR1
must reject as
EOP; see
Figure 38
40
tEOPR2
EOP width at receiver
must accept as
EOP; see
82
-
-
ns
Figure 38
[1] Characterized but not implemented as production test. Guaranteed by design.
Remark: If only USB0 (HS USB) is used, the pins VDDREG and VDDIO can be at
different voltages within the operating range but should have the same ramp up time. If
USB1(FS USB) is used, the pins VDDREG and VDDIO should be a minimum of 3.0 V and
be tied together.
T
PERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: t
FEOPT
differential data to
SE0/EOP skew
n × T
+ t
PERIOD
FDEOP
receiver EOP width: t
, t
EOPR1 EOPR2
002aab561
Fig 38. Differential data-to-EOP transition skew and EOP width
LPC435X_3X_2X_1X
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Table 35. Static characteristics: USB0 PHY pins[1]
Symbol Parameter
High-speed mode
Conditions
Min
Typ
Max
Unit
[2]
[3]
Pcons
power consumption
-
68
-
mW
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;
total supply current
during transmit
-
-
-
-
-
18
31
14
14
7
-
-
-
-
-
mA
mA
mA
mA
mA
during receive
with driver tri-stated
IDDD
Full-speed/low-speed mode
Pcons power consumption
digital supply current
[2]
-
15
-
mW
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;
total supply current
during transmit
-
-
-
-
-
3.5
5
-
-
-
-
-
mA
mA
mA
mA
mA
during receive
3
with driver tri-stated
3
IDDD
digital supply current
3
Suspend mode
IDDA(3V3) analog supply current (3.3 V)
-
-
-
-
24
24
3
-
-
-
-
A
A
mA
A
with driver tri-stated
with OTG functionality enabled
IDDD
digital supply current
30
VBUS detector outputs
Vth
threshold voltage
for VBUS valid
for session end
for A valid
4.4
0.2
0.8
2
-
-
V
-
0.8
2
V
-
V
for B valid
-
4
V
Vhys
hysteresis voltage
for session end
A valid
-
150
200
200
10
10
10
mV
mV
mV
-
B valid
-
[1] Characterized but not implemented as production test.
[2] Total average power consumption.
[3] The driver is active only 20 % of the time.
11.19 Ethernet
Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply
with the IEEE standard 802.3.
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32-bit ARM Cortex-M4/M0 microcontroller
Table 36. Dynamic characteristics: Ethernet
Tamb = 40 C to 105 C, 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Values guaranteed
by design.
Symbol Parameter
RMII mode
Conditions
Min
Max
Unit
[1]
fclk
clk
tsu
clock frequency for ENET_RX_CLK
clock duty cycle
-
50
50
-
MHz
%
[1]
50
4
[1][2]
set-up time
for ENET_TXDn, ENET_TX_EN,
ns
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
th
hold time
for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
2
-
ns
MII mode
[1]
fclk
clk
tsu
clock frequency for ENET_TX_CLK
clock duty cycle
-
25
50
-
MHz
%
[1]
50
4
[1][2]
set-up time
for ENET_TXDn, ENET_TX_EN,
ns
ENET_TX_ER
[1][2]
th
hold time
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
2
-
ns
[1]
fclk
clk
tsu
clock frequency for ENET_RX_CLK
clock duty cycle
-
25
50
-
MHz
%
[1]
50
4
[1][2]
set-up time
for ENET_RXDn, ENET_RX_ER,
ns
ENET_RX_DV
[1][2]
th
hold time
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
2
-
ns
[1] Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
ENET_RX_CLK
ENET_TX_CLK
t
su
t
h
ENET_RXD[n]
ENET_RX_DV
ENET_RX_ER
ENET_TXD[n]
ENET_TX_EN
ENET_TX_ER
002aag210
Fig 39. Ethernet timing
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
11.20 SD/MMC
Table 37. Dynamic characteristics: SD/MMC
Tamb = 40 C to +105 C, 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V, CL = 20 pF. SAMPLE_DELAY = 0x9,
DRV_DELAY = 0x6 in the SDDELAY register, sampled at 90 % and 10 % of the signal level, EHS = 1 for SD_CLK pin, EHS =
0 for SD_DATn and SD_CMD pins. Simulated values.
Symbol Parameter
Conditions
Min
-
Max
Unit
MHz
ns
fclk
clock frequency
on pin SD_CLK; data transfer mode
on pins SD_DATn as inputs
on pins SD_CMD as inputs
on pins SD_DATn as inputs
on pins SD_CMD as inputs
on pins SD_DATn as outputs
on pins SD_CMD as outputs
on pins SD_DATn as outputs
on pins SD_CMD as outputs
52
-
tsu(D)
data input set-up time
5.2
7
-
ns
th(D)
data input hold time
0.2
1
-
-
ns
ns
td(QV)
data output valid delay
time
15.7
ns
-
15.9
ns
th(Q)
data output hold time
3.5
3.5
-
-
ns
ns
T
cy(clk)
SD_CLK
t
t
h(Q)
d(QV)
SD_CMD (O)
SD_DATn (O)
t
t
su(D)
h(D)
SD_CMD (I)
SD_DATn (I)
002aag204
Fig 40. SD/MMC timing
11.21 LCD
Table 38. Dynamic characteristics: LCD
Tamb = 40 C to 105 C; 2.4 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.
Simulated values.
Symbol Parameter
Conditions
Min
Typ
50
-
Max Unit
fclk
clock frequency
on pin LCD_DCLK
-
-
-
MHz
ns
td(QV)
data output valid
delay time
17
th(Q)
data output hold time
8.5
-
-
ns
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
12. ADC/DAC electrical characteristics
Table 39. ADC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ
Max
Unit
V
VIA
Cia
ED
analog input voltage
0
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDA(3V3)
analog input capacitance
differential linearity error
-
2
-
-
-
-
-
-
-
-
-
-
pF
[1][2]
[3]
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
see Figure 42
0.8
1.0
0.8
1.5
0.15
0.15
0.3
0.35
3
LSB
LSB
LSB
LSB
LSB
LSB
%
EL(adj)
integral non-linearity
offset error
[4]
EO
[5]
EG
gain error
%
[6]
ET
absolute error
LSB
LSB
k
4
Rvsi
Ri
voltage source interface
resistance
-
1/(7 fclk(ADC)
Cia)
[7][8]
input resistance
-
-
-
-
-
-
1.2
4.5
400
M
fclk(ADC) ADC clock frequency
fs sampling frequency
MHz
10-bit resolution; 11 clock
cycles
kSamples/s
2-bit resolution; 3 clock
cycles
1.5
MSamples/s
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 41.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 41.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 41.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 41.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 41.
[7] Tamb = 25 C.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs Cia).
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offset
error
gain
error
E
E
G
O
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
offset error
E
O
V
− V
SSA
DDA(3V3)
1 LSB =
1024
002aaf959
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 41. 10-bit ADC characteristics
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32-bit ARM Cortex-M4/M0 microcontroller
R
vsi
LPC43xx
2 kΩ (analog pin)
2.2 kΩ (multiplexed pin)
ADC0_n/ADC1_n
R
s
ADC
COMPARATOR
C
= 2 pF
ia
V
EXT
V
SS
002aah084
Rs < 1/((7 fclk(ADC) Cia) 2 k
Fig 42. ADC interface to pins
Table 40. DAC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
LSB
LSB
LSB
[1]
[1]
ED
differential linearity error 2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
-
-
-
0.8
1.0
1.0
-
-
-
EL(adj)
integral non-linearity
code = 0 to 975
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
2.7 V VDDA(3V3) 3.6 V
2.4 V VDDA(3V3) < 2.7 V
-
-
-
-
-
-
1
1.5
0.8
1.0
0.3
1.0
-
-
LSB
LSB
LSB
%
[1]
[1]
EO
EG
offset error
gain error
-
-
-
-
%
CL
RL
ts
load capacitance
load resistance
settling time
200
-
pF
-
k
[2]
0.4
[1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual).
[2] Settling time is calculated within 1/2 LSB of the final value.
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32-bit ARM Cortex-M4/M0 microcontroller
13. Application information
13.1 LCD panel signal usage
Table 41. LCD panel connections for STN single panel mode
External pin
4-bit mono STN single panel
8-bit mono STN single panel
Color STN single panel
LPC43xx pin
used
LCD function LPC43xx pin
LCD function
LPC43xx pin
used
LCD function
used
LCD_VD[23:8]
LCD_VD7
LCD_VD6
LCD_VD5
LCD_VD4
LCD_VD3
LCD_VD2
LCD_VD1
LCD_VD0
LCD_LP
-
-
-
-
-
-
-
-
P8_4
P8_5
P8_6
P8_7
P4_2
P4_3
P4_4
P4_1
P7_6
P4_6
UD[7]
UD[6]
UD[5]
UD[4]
UD[3]
UD[2]
UD[1]
UD[0]
LCDLP
P8_4
P8_5
P8_6
P8_7
P4_2
P4_3
P4_4
P4_1
P7_6
P4_6
UD[7]
UD[6]
UD[5]
UD[4]
UD[3]
UD[2]
UD[1]
UD[0]
LCDLP
-
-
-
-
-
-
P4_2
P4_3
P4_4
P4_1
P7_6
P4_6
UD[3]
UD[2]
UD[1]
UD[0]
LCDLP
LCD_ENAB/
LCDM
LCDENAB/
LCDM
LCDENAB/
LCDM
LCDENAB/
LCDM
LCD_FP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
LCD_DCLK
LCD_LE
LCDDCLK
LCDLE
LCDDCLK
LCDLE
LCDDCLK
LCDLE
LCD_PWR
GP_CLKIN
CDPWR
LCDCLKIN
LCDPWR
LCDCLKIN
LCDPWR
LCDCLKIN
Table 42. LCD panel connections for STN dual panel mode
External pin 4-bit mono STN dual panel 8-bit mono STN dual panel
Color STN dual panel
LPC43xx pin
used
LCD function LPC43xx pin
LCD function
LPC43xx pin
used
LCD function
used
LCD_VD[23:16] -
-
-
-
-
-
LCD_VD15
LCD_VD14
LCD_VD13
LCD_VD12
LCD_VD11
LCD_VD10
LCD_VD9
LCD_VD8
LCD_VD7
LCD_VD6
LCD_VD5
LCD_VD4
LCD_VD3
-
-
PB_4
PB_5
PB_6
P8_3
P4_9
P4_10
P4_8
P7_5
LD[7]
LD[6]
LD[5]
LD[4]
LD[3]
LD[2]
LD[1]
LD[0]
UD[7]
UD[6]
UD[5]
UD[4]
UD[3]
PB_4
PB_5
PB_6
P8_3
P4_9
P4_10
P4_8
P7_5
P8_4
P8_5
P8_6
P8_7
P4_2
LD[7]
LD[6]
LD[5]
LD[4]
LD[3]
LD[2]
LD[1]
LD[0]
UD[7]
UD[6]
UD[5]
UD[4]
UD[3]
-
-
-
-
-
-
P4_9
LD[3]
P4_10
LD[2]
P4_8
LD[1]
P7_5
LD[0]
-
-
-
-
P8_5
P8_6
P8_7
P4_2
-
-
-
-
P4_2
UD[3]
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 42. LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
LPC43xx pin
used
LCD function LPC43xx pin
LCD function
LPC43xx pin
used
LCD function
used
P4_3
P4_4
P4_1
P7_6
P4_6
LCD_VD2
LCD_VD1
LCD_VD0
LCD_LP
P4_3
P4_4
P4_1
P7_6
P4_6
UD[2]
UD[1]
UD[0]
LCDLP
UD[2]
UD[1]
UD[0]
LCDLP
P4_3
P4_4
P4_1
P7_6
P4_6
UD[2]
UD[1]
UD[0]
LCDLP
LCD_ENAB/
LCDM
LCDENAB/
LCDM
LCDENAB/
LCDM
LCDENAB/
LCDM
LCD_FP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
P4_5
P4_7
P7_0
P7_7
PF_4
LCDFP
LCD_DCLK
LCD_LE
LCDDCLK
LCDLE
LCDDCLK
LCDLE
LCDDCLK
LCDLE
LCD_PWR
GP_CLKIN
LCDPWR
LCDCLKIN
LCDPWR
LCDCLKIN
LCDPWR
LCDCLKIN
Table 43. LCD panel connections for TFT panels
External
pin
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx LCD
LPC43xx
pin used
LCD
function
LPC43xxpin LCD
LPC43xx
pin used
LCD
function
pin used
function
used
PB_0
PB_1
PB_2
PB_3
P7_1
P7_2
-
function
LCD_VD23 PB_0
LCD_VD22 PB_1
LCD_VD21 PB_2
LCD_VD20 PB_3
BLUE3
PB_0
PB_1
PB_2
PB_3
P7_1
-
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
-
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
intensity
-
PB_0
PB_1
PB_2
PB_3
P7_1
P7_2
P7_3
P7_4
PB_4
PB_5
PB_6
P8_3
P4_9
P4_10
P4_8
P7_5
P8_4
P8_5
P8_6
P8_7
P4_2
P4_3
P4_4
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
BLUE2
BLUE1
BLUE0
LCD_VD19
LCD_VD18
LCD_VD17
LCD_VD16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VD15 PB_4
LCD_VD14 PB_5
LCD_VD13 PB_6
LCD_VD12 P8_3
GREEN3
PB_4
PB_5
PB_6
P8_3
P4_9
P4_10
-
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
-
PB_4
PB_5
PB_6
P8_3
P4_9
P4_10
-
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
intensity
-
GREEN2
GREEN1
GREEN0
LCD_VD11
LCD_VD10
LCD_VD9
LCD_VD8
LCD_VD7
LCD_VD6
LCD_VD5
LCD_VD4
LCD_VD3
LCD_VD2
LCD_VD1
-
-
-
-
-
-
-
-
-
-
-
-
P8_4
RED3
P8_4
P8_5
P8_6
P8_7
P4_2
-
RED4
RED3
RED2
RED1
RED0
-
P8_4
P8_5
P8_6
P8_7
P4_2
P4_3
-
RED4
RED3
RED2
RED1
RED0
intensity
-
P8_5
RED2
RED6
P8_6
RED1
RED5
P8_7
RED0
RED4
-
-
-
-
-
-
RED3
RED2
-
-
RED1
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 43. LCD panel connections for TFT panels
External
pin
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx LCD
LPC43xx
pin used
LCD
function
LPC43xxpin LCD
LPC43xx
pin used
LCD
function
pin used
function
used
function
LCD_VD0
LCD_LP
-
-
-
-
-
-
P4_1
P7_6
RED0
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCDLP
LCD_ENAB P4_6
/LCDM
LCDENAB/ P4_6
LCDM
LCDENAB/ P4_6
LCDM
LCDENAB/ P4_6
LCDM
LCDENAB/
LCDM
LCD_FP
LCD_DCLK P4_7
LCD_LE P7_0
P4_5
LCDFP
LCDDCLK P4_7
LCDLE P7_0
P4_5
LCDFP
P4_5
P4_7
P7_0
P7_7
LCDFP
LCDDCLK P4_7
LCDLE P7_0
P4_5
LCDFP
LCDDCLK
LCDLE
LCDDCLK
LCDLE
LCD_PWR P7_7
GP_CLKIN PF_4
LCDPWR P7_7
LCDCLKIN PF_4
LCDPWR
LCDPWR P7_7
LCDCLKIN PF_4
LCDPWR
LCDCLKIN
LCDCLKIN PF_4
13.2 Crystal oscillator
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see
LPC43xx user manual).
The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.
The oscillator can operate in one of two modes: slave mode and oscillation mode.
• In slave mode, couple the input clock signal with a capacitor of 100 pF (CC in
Figure 43), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this
configuration can be left unconnected.
• External components and models used in oscillation mode are shown in Figure 44,
and in Table 43 and Table 44. Since the feedback resistance is integrated on chip,
only a crystal and the capacitances CX1 and CX2 need to be connected externally in
case of fundamental mode oscillation (L, CL and RS represent the fundamental
frequency). Capacitance CP in Figure 44 represents the parallel package capacitance
and must not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the
crystal manufacturer.
Table 44. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors
X1, CX2
C
2 MHz
4 MHz
8 MHz
< 200
< 200
< 200
< 200
< 200
< 200
< 200
< 200
33 pF, 33 pF
39 pF, 39 pF
56 pF, 56 pF
18 pF, 18 pF
39 pF, 39 pF
56 pF, 56 pF
18 pF, 18 pF
39 pF, 39 pF
LPC435X_3X_2X_1X
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Table 44. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors
X1, CX2
C
12 MHz
16 MHz
20 MHz
< 160
< 160
< 120
< 80
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
33 pF, 33 pF
18 pF, 18 pF
33 pF, 33 pF
< 100
< 80
Table 45. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors CX1
CX2
,
15 MHz
20 MHz
< 80
< 80
< 100
18 pF, 18 pF
39 pF, 39 pF
47 pF, 47 pF
LPC43xx
XTAL1
C
i
C
g
100 pF
002aag379
Fig 43. Slave mode operation of the on-chip oscillator
LPC43xx
L
XTAL1
XTAL2
C
R
C
P
=
L
XTAL
S
C
C
X2
X1
002aag380
Fig 44. Oscillator modes with external crystal model used for CX1/CX2 evaluation
LPC435X_3X_2X_1X
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
13.3 RTC oscillator
In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and
CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and
CRTCX2 are CRTCX1/2 = 20 (typical) 4 pF.
An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended
amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of
5 pF to 10 pF.
LPC43xx
RTCX1
RTCX2
XTAL
C
C
RTCX2
RTCX1
002aah083
Fig 45. RTC 32 kHz oscillator circuit
13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
Connect the crystal on the PCB as close as possible to the oscillator input and output pins
of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone
crystal usage have a common ground plane. Also connect the external components to the
ground plain. To keep the noise coupled in via the PCB as small as possible, make loops
and parasitics as small as possible. Choose smaller values of CX1 and CX2 if parasitics
increase in the PCB layout.
Ensure that no high-speed or high-drive signals are near the RTCX1/2 signals.
13.5 Standard I/O pin configuration
Figure 46 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver enabled/disabled
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Digital input: Input buffer enabled/disabled
• Analog input
The default configuration for standard I/O pins is input buffer disabled and pull-up
enabled. The weak MOS devices provide a drive capability equivalent to pull-up and
pull-down resistors.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
VDDIO
ESD
enable output driver
data output from core
PIN
slew rate bit EHS
input buffer enable bit EZI
data input to core
glitch
filter
filter select bit ZIF
pull-up enable bit EPUN
ESD
pull-down enable bit EPD
analog I/O
VSSIO
002aah028
The glitch filter rejects pulses of typical 12 ns width.
Fig 46. Standard I/O pin configuration with analog input
13.5.1 Reset pin configuration
V
ps
V
ps
V
ps
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aag702
Fig 47. Reset pin configuration
13.5.2 Suggested USB interface solutions
The USB device can be connected to the USB as self-powered device (see Figure 48) or
bus-powered device (see Figure 49).
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
On the LPC435x/3x/2x/1x, USBn_VBUS pins are 5 V tolerant only when VDDIO is applied
and at operating voltage level. Therefore, if the USBn_VBUS function is connected to the
USB connector and the device is self-powered, the USBn_VBUS pins must be protected
for situations when VDDIO = 0 V.
If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be
connected directly to the VBUS pin on the USB connector.
For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn_VBUS
pins, precautions must be taken to reduce the voltage to below 3.6 V, which is the
maximum allowable voltage on the USBn_VBUS pins in this case.
One method is to use a voltage divider to connect the USBn_VBUS pins to VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be
greater than 0.7VDDIO to indicate a logic HIGH while below the 3.6 V allowable maximum
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDDIO = 3.6 V,
the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
For bus-powered devices, a regulator powered by USB can provide 3.3 V to VDDIO
whenever bus power is present and ensure that power to the USBn_VBUS pins is always
present when the 5 V VBUS signal is applied. See Figure 49.
Remark: Applying 5 V to the USBn_VBUS pins for a short time while the regulator ramps
up might compromise the long-term reliability of the part but does not affect its function.
LPC43xx
VDDIO
R2
R3
USBn_VBUS
VBUS
USB-B
connector
USB
aaa-013458
Fig 48. USB interface on a self-powered device where USBn_VBUS = 5 V
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LPC43xx
VDDIO
REGULATOR
USBn_VBUS
VBUS
USB-B
connector
USB
aaa-013459
Fig 49. USB interface on a bus-powered device
Remark: If the VBUS function of the USB1 interface is not connected, configure the pin
function for GPIO using the function control bits in the SYSCON block.
VDDIO
R1
LPC43xx
T2
T1
R2
R3
USBn_VBUS
VBUS
USB-B
connector
USB
aaa-013460
Fig 50. USB interface for USB operating in OTG mode
Remark: In OTG mode, it is important to be able to detect the VBUS level and to charge
and discharge VBUS. This requires adding active devices that disconnect the link when
VDDIO is not present.
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
14. Package outline
LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm
SOT740-2
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
C
e
1
y
1 C
y
∅ v M
∅ w M
b
C
C
A
B
e
1/2 e
T
R
N
L
P
M
K
H
F
e
J
e
2
G
E
C
A
1/2 e
D
B
ball A1
index area
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
X
5
scale
10 mm
0
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max
0.45
0.35
1.1
0.9
0.55 17.2 17.2
0.45 16.8 16.8
mm
1.55
1
15
15
0.25
0.1
0.12 0.35
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
05-06-16
05-08-04
SOT740-2
MO-192
- - -
Fig 51. Package outline LBGA256 package
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm
SOT459-1
y
X
A
105
104
156
157
Z
E
e
H
E
E
(A )
3
A
2
A
A
1
w M
p
θ
L
L
b
p
detail X
pin 1 index
53
208
1
52
v
M
B
A
Z
w M
D
b
p
e
D
B
H
v
M
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 28.1 28.1
0.17 0.09 27.9 27.9
30.15 30.15
29.85 29.85
0.75
0.45
1.43 1.43
1.08 1.08
mm
1.6
0.25
1
0.12 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-06
03-02-20
SOT459-1
136E30
MS-026
Fig 52. Package outline of the LQFP208 package
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
SOT926-1
D
B
A
ball A1
index area
A
2
E
A
A
1
detail X
e
1
C
M
∅ v
∅ w
C
C
A
B
b
e
1/2 e
y
y
M
C
1
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e
ball A1
index area
1
2
3
4
5
6
7
8
9
10
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max
0.4
0.3
0.8
0.65
0.5
0.4
9.1
8.9
9.1
8.9
mm
1.2
0.8
7.2
7.2
0.15 0.05 0.08
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
05-12-09
05-12-22
SOT926-1
- - -
- - -
Fig 53. Package outline of the TFBGA100 package
LPC435X_3X_2X_1X
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LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
y
X
A
108
109
73
72
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w
p
M
L
p
b
L
pin 1 index
detail X
37
144
1
36
v
M
A
Z
w
M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
Z
E
θ
1
2
3
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 20.1
0.17 0.09 19.9 19.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-03-14
03-02-20
SOT486-1
136E23
MS-026
Fig 54. Package outline for the LQFP144 package
LPC435X_3X_2X_1X
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
15. Soldering
Footprint information for reflow soldering of LBGA256 package
SOT740-2
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
SR
occupied area
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
Hx
Hy
1.00
0.450 0.450 0.600 17.500 17.500
sot740-2_fr
Fig 55. Reflow soldering of the LBGA256 package
LPC435X_3X_2X_1X
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of LQFP208 package
SOT459-1
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 31.300 31.300 28.300 28.300 1.500 0.280 0.400 28.500 28.500 31.550 31.550
sot459-1_fr
Fig 56. Reflow soldering of the LQFP208 package
LPC435X_3X_2X_1X
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NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of LQFP144 package
SOT486-1
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550
sot486-1_fr
Fig 57. Reflow soldering of the LQFP144 package
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Footprint information for reflow soldering of TFBGA100 package
SOT926-1
Hx
P
P
Hy
see detail X
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
SL
SP
SR
occupied area
solder resist
detail X
DIMENSIONS in mm
P
SL
SP
SR
Hx
Hy
0.80
0.330 0.400 0.480 9.400 9.400
sot926-1_fr
Fig 58. Reflow soldering of the TFBGA100 package
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
16. Abbreviations
Table 46. Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
Advanced Peripheral Bus
APB
API
Application Programming Interface
BrownOut Detection
BOD
CAN
Controller Area Network
CMAC
CSMA/CD
DAC
Cipher-based Message Authentication Code
Carrier Sense Multiple Access with Collision Detection
Digital-to-Analog Converter
Direct Current-to-Direct Current
Direct Memory Access
DC-DC
DMA
GPIO
IRC
General Purpose Input/Output
Internal RC
IrDA
Infrared Data Association
JTAG
LCD
Joint Test Action Group
Liquid Crystal Display
LSB
Least Significant Bit
MAC
MCU
MIIM
n.c.
Media Access Control
MicroController Unit
Media Independent Interface Management
not connected
OHCI
OTG
PHY
Open Host Controller Interface
On-The-Go
Physical Layer
PLL
Phase-Locked Loop
PMC
PWM
RIT
Power Mode Control
Pulse Width Modulator
Repetitive Interrupt Timer
RMII
Reduced Media Independent Interface
Synchronous Dynamic Random Access Memory
Single Instruction Multiple Data
Serial Peripheral Interface
Serial Synchronous Interface
Synchronous Serial Port
SDRAM
SIMD
SPI
SSI
SSP
UART
ULPI
USART
USB
Universal Asynchronous Receiver/Transmitter
UTMI+ Low Pin Interface
Universal Synchronous Asynchronous Receiver/Transmitter
Universal Serial Bus
UTMI
USB2.0 Transceiver Macrocell Interface
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
17. References
[1] LPC43xx User manual UM10503:
http://www.nxp.com/documents/user_manual/UM10503.pdf
[2] LPC43xx Errata sheet:
http://www.nxp.com/documents/errata_sheet/ES_LPC43XX.pdf
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
18. Revision history
Table 47. Revision history
Document ID
Release date Data sheet status
20200110 Product data sheet
• Updated for rise and fall times for I/O pins configured as input only.
20160303 Product data sheet LPC435X_3X_2X_1X v.5.2
Change notice Supersedes
LPC435X_3X_2X_1X v.5.4
-
LPC435X_3X_2X_1X v.5.3
LPC435X_3X_2X_1X v.5.3
-
• Updated Table 32 “Dynamic characteristics: Dynamic external memory interface”:
Read cycle parameters th(D) min value is 2.2 ns and max value is “-”.
LPC435X_3X_2X_1X v.5.2
Modifications:
20151125
• Fixed cross references in Table 3 “Pin description”.
<tbd> Product data sheet 2015110041
Product data sheet
LPC435X_3X_2X_1X v.5.1
LPC435X_3X_2X_1X v.5.1
Modifications:
LPC435X_3X_2X_1X v.5
• Updated Table 2 “Ordering options”. TFBGA100 packages do not support ULPI
interface.
• Changed the EMC on TFBGA100 packages from 8 bit to 16 bit. See Section 7.18.4
“External Memory Controller (EMC)”
• Fixed the sentence: the voltage divider should provide a reduction of 3.6 V/5.25 V or
~0.686 V to read the voltage divider should provide a reduction of 3.6 V/5.25 V or
~0.686 in Section 13.5.2 “Suggested USB interface solutions” on page 141.
• Changed footnote 12 in Table 3 “Pin description” with the text: VPP is internally
connected to VDDIO for all packages with the exception of the LFBGA256 package.
• Updated the features of the SSP functional description: Maximum SSP speed in
full-duplex mode of 25.5 Mbit/s; for transmit only 51 Mbit/s (master) and 11 Mbit/s
(slave), see Section 7.19.4.1 “Features”.
• Updated SSP slave and SSP master values in Table 27 “Dynamic characteristics:
SSP pins in SPI mode”. Updated footnote 2 to: Tcy(clk) 12 Tcy(PCLK)
.
–
removed tv(Q), data output valid time in SPI mode, minimum value of 3 ´ (1/PCLK)
from SSP slave mode.
–
added units to td, delay time, for SSP slave and master mode.
• Updated Figure 29 “I2S-bus timing (receive)”.
• Added GPCLKIN section and table. See Section 11.7 “GPCLKIN” and Table 22
“Dynamic characteristic: GPCLKIN”.
• Updated Table 11 “Static characteristics”. IBAT in deep power-down mode; RTC
running; VDD(REG) = VDDA = VDDIO = 0 V; Was: VDD(REG)(3V3) floating.
LPC435X_3X_2X_1X v.5
<tbd>
Product data sheet
201408004F01 LPC435X_3X_2X_1X v.4
LPC435X_3X_2X_1X
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Rev. 5.4 — 10 January 2020
154 of 162
LPC435x/3x/2x/1x
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32-bit ARM Cortex-M4/M0 microcontroller
Table 47. Revision history …continued
Document ID
Release date Data sheet status
• Updated Section 1 “General description”.
• Minimum operating voltage changed from 2.2 V to 2.4 V for VDD(REG)(3V3), VDD(IO)
DDA(3V3), VBAT in Table 11.
• Operating temperature corrected in Table 27. Tamb = Tamb = -40 °C to 105 °C.
Change notice Supersedes
Modifications:
,
V
• Max and min values of parameters tlag and tlead corrected for SSP master mode in
Table 27.
• Figure 32 “SSP in SPI mode and SPI slave timing” updated.
• Typical values for parameters tDS, tDH, tv(Q), th(Q) for SSP slave mode replaced by min
and max numbers in Table 25.
• Parameters tlead, tlag, and td added to SSP slave mode in Table 27.
• SPIFI timing data restated for CL = 20 pF in Table 29 “Dynamic characteristics:
SPIFI”.
• USART timing added for master and slave mode in Figure 30 “USART timing”.
• USB0_VBUS changed to input only. See Table 3 “Pin description”.
• Changed the flash erase time (ter) to 100ms. See Table 15.
• Updated Dynamic characteristics: SD/MMC table. See Table 37.
• Added Band gap characteristics table. See Table 14.
• Updated Table 2: Motor control PWM instead of PWM.
• Updated Dynamic characteristics: USB0 and USB1 pins (full-speed). See Table 34.
• Added a table note: The values in the table have been calculated with WAITTURN =
0x0 in STATICWAITTURN register. See Table 31.
• Added a remark to Table 34.
• Updated Table 13 “BOD static characteristics[1]”. Removed BOD interrupt levels 0
and 1; removed Reset levels 0 and 1. Not applicable.
LPC435X_3X_2X_1X v.4
<tbd>
Product data sheet
-
LPC435X_3X_2X_1X v.3
LPC435X_3X_2X_1X
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Rev. 5.4 — 10 January 2020
155 of 162
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32-bit ARM Cortex-M4/M0 microcontroller
Table 47. Revision history …continued
Document ID
Release date Data sheet status
Change notice Supersedes
Modifications:
• Parameter tret (retention time) for EEPROM updated in Table 15.
• SGPIO and SPI location corrected in Figure 1.
• SGPIO-to-DMA connection updated in Figure 6.
• Parameter VDDA(3V3) added for pins USB0_VDDA3V3_DRIVER and
USB0_VDDA3V3 in Table 11.
• Parameter name IDD(ADC) changed to IDDA in Table 11.
• Minimum wake-up time from sleep mode added in Table 16.
• Data for IDD(IO) added in Table 11.
• Corrected max voltage on pins USB0_DP, USB0_DM, USB0_VBUS, USB1_DP, and
USB1_DM in Table 7 and Table 11 to be consistent with USB specifications.
• SPI and SGPIO peripheral power consumption added in Table 12.
• SPI timing characteristics added. See Section 11.12.
• SGPIO timing characteristics added. See Section 11.15.
• Data sheet status changed to Product data sheet.
• Conditions RPHASE1 and RPHASE2 corrected in Table 15 “EEPROM
characteristics”. RPHASE1: twait > 70 ns. RPHASE2: twait > 35 ns.
• IDD(REG)(3V3) updated in Table 11 “Static characteristics” for the following conditions:
–
–
–
–
–
–
Active mode: CCLK = 12 MHz; IDD(REG)(3V3) changed from 9.3 mA to 10 mA.
Active mode: CCLK = 60 MHz; IDD(REG)(3V3) changed from 26 mA to 28 mA.
Active mode: CCLK = 120 MHz; IDD(REG)(3V3) changed from 46 mA to 51 mA.
Active mode: CCLK = 180 MHz; IDD(REG)(3V3) changed from 66 mA to 74 mA.
Active mode: CCLK = 204 MHz; IDD(REG)(3V3) changed from 75 mA to 83 mA.
Sleep mode: CCLK = 12 MHz; IDD(REG)(3V3) changed from 6.2 mA to 8.8 mA.
• Power consumption data in Figure 11 to Figure 14 updated.
• IRC specifications corrected in Table 19 “Dynamic characteristic: IRC oscillator”.
Accuracy changed to +/- 3 % over the entire temperature range.
• SPIFI timing diagram corrected and specified for mode 0. See Table 27.
• Table 21 “Dynamic characteristic: I/O pins[1]” added.
• Parameter CI corrected for high-drive pins (changed from 2 pF to 5.2 pF). See
Table 11.
• Internal pull-up resistor configuration added for RESET, WAKEUPn, and ALARM
pins. See Table 3.
• Description of DEBUG pin updated.
• Input range for PLL1 corrected: 1 MHz to 25 MHz. See Section 7.23.7 “System PLL1”.
• Signal polarity of EMC_CKEOUT and EMC_DQMOUT corrected. Both signals are
active HIGH.
• SPIFI output timing parameters in Table 27 corrected to apply to Mode 0:
–
tv(Q) changed to 3.2 ns.
–
th(Q) changed to 0.2 ns,
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32-bit ARM Cortex-M4/M0 microcontroller
Table 47. Revision history …continued
Document ID
Release date Data sheet status
Change notice Supersedes
Modifications:
• SD/MMC timing data updated. See Table 35 “Dynamic characteristics: SD/MMC”.
• IEEE standard 802.3 compliance added to Section 11.18. Covers Ethernet dynamic
characteristics of ENET_MDIO and ENET_MDC signals.
• SSP master mode timing diagram updated with SSEL timing parameters. See Figure
31 “SSP in SPI mode and SPI master timing”.
• Parameters tlead, tlag, and td added in Table 25 “Dynamic characteristics: SSP pins in
SPI mode”.
• Parameter tCSLWEL with condition PB = 1 corrected: (WAITWEN + 1) Tcy(clk) added.
See Table 29 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Parameter tCSLBLSL with condition PB = 0 corrected: (WAITWEN + 1) Tcy(clk) added.
See Table 29 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Removed restriction on C_CAN bus usage. See CAN.1 errata in Ref. 2.
• General-purpose OTP size corrected.
LPC435X_3X_2X_1X v.3
Modifications:
20121206
Preliminary data sheet
-
LPC4357_53_37_33 v.2.1
• TFBGA180 packages removed.
• Part LPC432x and LPC431x added.
• SCT dither engine added and SCT bi-directional event enable features added.
• Figure 10 “Dual-core debug configuration” added.
• T = 105 °C data added in Figure 20 to Figure 23.
• Change symbol names and parameter names in Table 21.
• Parameter ILH updated for condition VI = 5 V and Tamb = 25 °C/105 °C in Table 11.
• Power consumption data added in Section 10.1.
• SPIFI dynamic characteristics added in Section 11.16.
• IRC accuracy corrected to 2 % for Tamb = -40 °C to 0 °C and Tamb = 85 °C to 105 °C.
• Pull-up and Pull-down current data (Figure 24 and Figure 25) updated with data for
T
amb = 105 °C.
• SPIFI maximum data rate changed to 52 MB per second.
• Recommendation for VBAT use added: The recommended operating condition for the
battery supply is VDD(REG)(3V3) > VBAT + 0.2 V.
• Table 14 “Band gap characteristics” added.
• Section 7.23.9 “Power Management Controller (PMC)” added.
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC
is connected to ADC0 and ADC1. See Table 3.
• OTP memory size changed to 64 bit.
• Use of C_CAN peripheral restricted in Section 2.
• ADC channels limited to a total of 8 channels shared between ADC0 and ADC1.
LPC4357_53_37_33 v.2.1
Modifications:
20120904
Preliminary data sheet
-
LPC4357_53_37_33 v.2
• SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin
P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• SWD removed for ARM Cortex-M0.
• BOD de-assertion levels added in Table 13.
• Peripheral power consumption data added in Table 12.
• Minimum value for all supply voltages changed to -0.5 V in Table 7.
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
Table 47. Revision history …continued
Document ID
Release date Data sheet status
20120711 Preliminary data sheet
Change notice Supersedes
LPC4357_53_37_33 v.2
Modifications:
-
LPC4357_53 v.1
• Data sheet status changed to preliminary.
• Parts LPC4337 and LPC4333 added.
• Minimum value of VI for conditions “USB0 pins USB0_DP; USB0_DM; USB0_VBUS”,
“USB0 pins USB0_ID; USB0_RREF”, and “USB1 pins USB1_DP and USB1_DM”
changed to 0.3 V in Table 6.
• Section 10.2 added.
• Table 8 “Thermal resistance (LQFP packages)” and Table 9 “Thermal resistance
value (BGA packages)” added.
• AES removed. Available on parts LPC43Sxx only.
• Dynamic characteristics of the SD/MMC controller updated in Table 30.
• Dynamic characteristics of the LCD controller updated in Table 31.
• Dynamic characteristics of the SSP controller updated in Table 23.
• Parameters IIL and IIH renamed to ILL and ILH in Table 10.
LPC4357_53 v.1
20120604
Objective data sheet
-
-
LPC435X_3X_2X_1X
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32-bit ARM Cortex-M4/M0 microcontroller
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
LPC435X_3X_2X_1X
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
19.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
7.18.6
High-speed USB Host/Device interface with ULPI
(USB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information. . . . . . . . . . . . . . . . . . . . . 5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.7 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.8 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 8
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.19
7.19.1
Digital serial peripherals. . . . . . . . . . . . . . . . . 76
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.19.2 USART0/2/3. . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.19.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.19.3 SPI serial I/O controller . . . . . . . . . . . . . . . . . 77
7.19.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.19.4 SSP serial I/O controller. . . . . . . . . . . . . . . . . 77
7.19.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.19.5
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 78
7.19.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.19.6
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.19.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.19.7 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.19.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7
7.8
7.9
7.9.1
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.16.1
7.17
7.17.1
Functional description . . . . . . . . . . . . . . . . . . 61
Architectural overview. . . . . . . . . . . . . . . . . . . 61
ARM Cortex-M4 processor . . . . . . . . . . . . . . . 61
ARM Cortex-M0 co-processor . . . . . . . . . . . . 61
Interprocessor communication . . . . . . . . . . . . 61
AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 62
Nested Vectored Interrupt Controller (NVIC) . 62
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 63
System Tick timer (SysTick) . . . . . . . . . . . . . . 63
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Global Input Multiplexer Array (GIMA) . . . . . . 64
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 64
On-chip flash memory. . . . . . . . . . . . . . . . . . . 64
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 66
One-Time Programmable (OTP) memory. . . . 69
General Purpose I/O (GPIO) . . . . . . . . . . . . . 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Configurable digital peripherals . . . . . . . . . . . 69
State Configurable Timer (SCTimer/PWM)
7.20
7.20.1
Counter/timers and motor control. . . . . . . . . . 79
General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.20.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.20.2
7.20.3
7.20.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.20.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 81
7.20.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.20.5 Windowed WatchDog Timer (WWDT) . . . . . . 81
7.20.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Motor control PWM . . . . . . . . . . . . . . . . . . . . 80
Quadrature Encoder Interface (QEI) . . . . . . . 80
7.21
7.21.1
Analog peripherals . . . . . . . . . . . . . . . . . . . . . 82
Analog-to-Digital Converter (ADC0/1) . . . . . . 82
subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.17.2 Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 70
7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.18
7.18.1
7.18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.18.2 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 71
7.18.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.18.3
7.18.4
7.21.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.21.2 Digital-to-Analog Converter (DAC). . . . . . . . . 82
7.21.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.22
7.22.1
7.22.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.22.1.2 Event monitor/recorder. . . . . . . . . . . . . . . . . . 83
7.22.2
7.23
7.23.1
7.23.2
7.23.3
7.23.4
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 71
General Purpose DMA . . . . . . . . . . . . . . . . . . 71
Peripherals in the RTC power domain . . . . . . 82
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 83
System control . . . . . . . . . . . . . . . . . . . . . . . . 83
Configuration registers (CREG) . . . . . . . . . . . 83
System Control Unit (SCU) . . . . . . . . . . . . . . 84
Clock Generation Unit (CGU). . . . . . . . . . . . . 84
Internal RC oscillator (IRC) . . . . . . . . . . . . . . 84
SD/MMC card interface . . . . . . . . . . . . . . . . . 72
External Memory Controller (EMC). . . . . . . . . 72
7.18.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.18.5
High-speed USB Host/Device/OTG interface
(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
continued >>
LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 5.4 — 10 January 2020
161 of 162
LPC435x/3x/2x/1x
NXP Semiconductors
32-bit ARM Cortex-M4/M0 microcontroller
7.23.5
7.23.6
7.23.7
7.23.8
7.23.9
PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 84
16
17
18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 152
References. . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Revision history . . . . . . . . . . . . . . . . . . . . . . 154
PLL0AUDIO (for audio). . . . . . . . . . . . . . . . . . 84
System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reset Generation Unit (RGU). . . . . . . . . . . . . 85
Power Management Controller (PMC) . . . . . . 85
19
Legal information . . . . . . . . . . . . . . . . . . . . . 159
Data sheet status . . . . . . . . . . . . . . . . . . . . . 159
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 159
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 160
19.1
19.2
19.3
19.4
7.23.10 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.23.11 Code security (Code Read Protection - CRP) 87
7.24
Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 88
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 89
Thermal characteristics. . . . . . . . . . . . . . . . . . 90
8
20
21
Contact information . . . . . . . . . . . . . . . . . . . 160
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9
10
Static characteristics. . . . . . . . . . . . . . . . . . . . 91
Power consumption . . . . . . . . . . . . . . . . . . . . 98
Peripheral power consumption . . . . . . . . . . . 101
Electrical pin characteristics . . . . . . . . . . . . . 103
BOD and band gap static characteristics . . . 107
10.1
10.2
10.3
10.4
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Dynamic characteristics . . . . . . . . . . . . . . . . 108
Flash/EEPROM memory . . . . . . . . . . . . . . . 108
Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 109
External clock for oscillator in slave mode . . 109
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 110
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110
GPCLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . 113
USART interface. . . . . . . . . . . . . . . . . . . . . . 114
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 116
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 119
SSP/SPI timing diagrams . . . . . . . . . . . . . . . 120
SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SGPIO timing . . . . . . . . . . . . . . . . . . . . . . . . 122
External memory interface . . . . . . . . . . . . . . 124
USB interface . . . . . . . . . . . . . . . . . . . . . . . . 129
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
12
ADC/DAC electrical characteristics . . . . . . . 133
13
Application information. . . . . . . . . . . . . . . . . 136
LCD panel signal usage . . . . . . . . . . . . . . . . 136
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 138
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 140
XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . 140
Standard I/O pin configuration . . . . . . . . . . . 140
Reset pin configuration. . . . . . . . . . . . . . . . . 141
Suggested USB interface solutions . . . . . . . 141
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . 144
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 January 2020
Document identifier: LPC435X_3X_2X_1X
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