LPC54102J256BD64_技术文档

LPC5410x

32-bit ARM Cortex-M4/M0+ MCU; 104 kB SRAM; 512 kB flash,

3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers,

SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC

Rev. 2.11 — 19 September 2019

Product data sheet

1. General description

The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications.

These devices include:

• Optional ARM Cortex-M0+ coprocessor.

• 104 kB of on-chip SRAM.

• Up to 512 kB on-chip flash.

• State-Configurable Timer with PWM capabilities (SCTimer/PWM).

• RTC/alarm timer.

• 24-bit Multi-Rate Timer (MRT).

• 12-bit 5.0 Msamples/sec ADC.

• Repetitive Interrupt Timer (RIT).

• Windowed Watchdog Timer (WWDT).

• Two SPIs.

• Three Fast-mode plus I²C-bus interfaces with high-speed slave mode.

• Four USARTs.

• Five general-purpose timers.

The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power

consumption, enhanced debug features, and a high level of support block integration. The

ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A

hardware floating-point unit is integrated in the core.

The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core

which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor

offers up to 150 MHz performance with a simple instruction set and reduced code size. In

LPC5410x, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle

iterative multiplier.

LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

2. Features and benefits

 Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at

the same frequency as the M4 core. Both cores operate up to a maximum frequency of

150 MHz.

 ARM Cortex-M4 core (version r0p1):

 ARM Cortex-M4 processor, running at a frequency of up to 150 MHz, using the

same clock as the Cortex-M4.

 Floating Point Unit (FPU) and Memory Protection Unit (MPU).

 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input with a selection of sources.

 Serial Wire Debug with eight breakpoints and four watch points.

Includes Serial Wire Output for enhanced debug capabilities.

 System tick timer.

 ARM Cortex-M0+ core (version r0p1):

 ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input with a selection of sources.

 Serial Wire Debug with four breakpoints and two watch points.

 System tick timer.

 On-chip memory:

 Up to 512 kB on-chip flash program memory with flash accelerator and 256 byte

page erase and write.

 104 kB total SRAM composed of:

 Up to 96 kB contiguous main SRAM.

 An additional 8 kB SRAM.

 ROM API support:

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 Power control API.

 Serial interfaces:

 Four USART interfaces with synchronous mode and 32 kHz mode for wake-up

from deep sleep and power down modes. The USARTs have FIFO support from

the System FIFO and share a fractional baud-rate generator.

 Two SPI interfaces, each with four slave selects and flexible data configuration.

The SPIs have FIFO support from the System FIFO. The slave function is able to

wake up the device from deep sleep and power down modes.

 Three I²C-bus interfaces supporting fast mode and Fast-mode Plus with data rates

of up to 1Mbit/s and with multiple address recognition and monitor mode. Each

I²C-bus interface also supports High Speed Mode (3.4 Mbit/s) as a slave. The

slave function is able to wake up the device from deep sleep and power down

modes.

 Digital peripherals:

 DMA controller with 22 channels and 20 programmable triggers, able to access all

memories and DMA-capable peripherals.

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

 Up to 50 General-Purpose Input/Output (GPIO) pins. Most GPIOs have

configurable pull-up/pull-down resistors, programmable open-drain mode, and

input inverter.

 GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.

 Up to eight GPIOs (pin interrupts) can be selected as edge-sensitive (rising or

falling edges or both) interrupt requests or level-sensitive (active low or active high)

interrupt requests. In addition, up to eight GPIOs can be selected to contribute a

boolean expression and interrupt generation using the pattern match engine block.

 Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

 CRC engine.

 Timers:

 Five 32-bit standard general purpose timers/counters, four of which support up to 4

capture inputs and 4 compare outputs, PWM mode, and external count input.

Specific timer events can be selected to generate DMA requests. The fifth timer

does not have external pin connections and may be used for internal timing

operations.

 One State Configurable Timer/PWM (SCT/PWM) with 8 inputs (6 external inputs

and 2 internal inputs) and 8 output functions (including capture and match). Inputs

and outputs can be routed to/from external pins and internally to/from selected

peripherals. Internally, the SCT supports 13 captures/matches, 13 events and 13

states.

 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes

including deep power-down, with 1 ms resolution.

 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

 Windowed Watchdog Timer (WWDT).

 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be

used to wake up the device from low power modes.

 Repetitive Interrupt Timer (RIT) for debug time-stamping and general-purpose use.

 Analog peripheral: 12-bit, 12-channel, Analog-to-Digital Converter (ADC) supporting

5.0 Msamples/s. The ADC supports two independent conversion sequences.

 Clock generation:

 12 MHz internal RC oscillator.

 External clock input for clock frequencies of up to 25 MHz.

 Internal low-power, watchdog oscillator (WDOSC) with a nominal frequency of 500

kHz.

 32 kHz low-power RTC oscillator.

 System PLL allows CPU operation up to the maximum CPU rate. May be run from

the internal RC oscillator, the external clock input CLKIN, or the RTC oscillator.

 Clock output function for monitoring internal clocks.

 Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

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LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

 Power-saving modes and wake-up:

 Integrated PMU (Power Management Unit) to minimize power consumption.

 Reduced power modes: sleep, deep sleep, power down, and deep power-down.

 Wake-up from deep sleep and power down modes via activity on the USART, SPI,

and I²C peripherals.

 Wake-up from sleep, deep sleep, power down, and deep power-down modes using

the RTC alarm.

 Single power supply 1.62 V to 3.6 V.

 Power-On Reset (POR).

 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.

 JTAG boundary scan supported.

 Unique device serial number (128 bit) for identification.

 Operating temperature range 40 °C to 105 °C.

 Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

4 of 95

LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC54102J512UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -

LPC54102J256UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -

LPC54101J512UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -

LPC54101J256UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -

LPC54102J512BD64 LQFP64

LPC54102J256BD64 LQFP64

LPC54101J512BD64 LQFP64

LPC54101J256BD64 LQFP64

plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm

SOT314-2

3.1 Ordering options

Table 2.

Ordering options

Type number

Device order part number Flash/kB Total SRAM/kB Core M4 w/ FPU Core

M0+

GPIO

LPC54102J512UK49 LPC54102J512UK49Z

LPC54102J256UK49 LPC54102J256UK49Z

LPC54101J512UK49 LPC54101J512UK49Z

LPC54101J256UK49 LPC54101J256UK49Z

LPC54102J512BD64 LPC54102J512BD64QL

LPC54102J256BD64 LPC54102J256BD64QL

LPC54101J512BD64 LPC54101J512BD64QL

LPC54101J256BD64 LPC54101J256BD64QL

512

256

512

256

512

256

512

256

104

1

0

1

0

39

50

[1] All of the parts include five 32-bit general-purpose timers, one State-Configurable Timer with PWM

capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed

Watchdog Timer (WWDT), four USARTs, two SPIs, three Fast-mode plus I2C-bus interfaces with

high-speed slave mode, and one 12-bit 5.0 Msamples/sec ADC.

4. Marking

Terminal 1

index area

n

Terminal 1 index area

1

aaa-011231

aaa-015675

Fig 1. LQFP64 package marking

Fig 2. WLCSP49 package marking

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

The LPC5410x LQFP64 package has the following top-side marking:

• First line: LPC5410xJyyy

– x: 2 = dual core (M4, M0+), 1 = single core (M4)

– yyy: flash size

• Second line: BD64

• Third line: xxxxxxxxxxxx

• Fourth line: xxxyywwx[R]z

– yyww: Date code with yy = year and ww = week.

– xR = boot code version and device revision.

The LPC5410x WLCSP49 package has the following top-side marking:

• First line: LPC5410x

– x: 2 = dual core (M4, M0+), 1 = single core (M4)

• Second line: JxxxUK49

– xxx: flash size

• Third line: xxxxxxxx

• Fourth line: xxxyyww

– yyww: Date code with yy = year and ww = week.

• Fifth line: xxxxx

• Sixth line: NXP x[R]z

– xR = boot code version and device revision.

Table 3.

Device revision table

Revision identifier (R)

Revision description

‘1B’

‘1C’

Initial device revision with boot code version 17.1.

Second device revision with boot code version 17.1.

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

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LPC5410x

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5. Block diagram

Serial Wire

Debug

JTAG boundary

scan

CLKIN

RESET

Debug Interface

FPU MPU

Power-on Reset

Brownout Detect

Internal RC osc.

System PLL

clock generation,

power control,

and other

CLKOUT

system functions

ARM

Cortex M0+

DMA

controller

Cortex M4

Flash

acclerator

Flash

512 kB

SRAM0

64 kB

SRAM1

32 kB

SCTimer/

PWM

Multilayer

AHB Matrix

SRAM2

8 kB

Boot and driver

ROM 64 kB

GPIO

CRC

engine

DMA

VFIFO

ADC

12 ch, 12-bit

Mailbox

registers registers

Sync APB

bridge

APB slave group 0

Async APB

bridge

Multi-rate Timer

Frequency Measurement Unit

3x 32-bit timers (T2, T3, T4)

APB slave group 1

USART 0, 1, 2, and 3

GPIO global interrupts 0 and 1

I/O configuration

System control

I2C0, 1, 2

SPI0, 1

2x 32-bit timers (T0, T1)

Fractional Rate Generator

Flash registers

PMU registers

Windowed Watchdog

Watchdog oscillator

MicroTick Timer

RTC Alarm

RTC Power Domain

32 kHz

divider

Real Time Clock

oscillator

aaa-015626

Gray-shaded peripheral blocks provide dedicated request lines or triggers for DMA transfers.

Fig 3. LPC5410x Block diagram

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

6. Pinning information

6.1 Pinning

G

F

E

D

C

B

A

1

2

3

4

5

6

7

ball A1 (pin #1)

index area

aaa-015470

Fig 4. WLCSP49 Pin configuration (bottom view)

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

PIO0_14 49

PIO0_15 50

PIO1_12 51

32 PIO0_1

31 PIO0_0

30 PIO1_10

29 PIO1_9

28 PIO1_8

27 PIO1_7

26 PIO1_6

SWCLK/ PIO0_16 52

SWDIO/ PIO0_17 53

PIO1_13 54

VSS 55

VDD 56

25 VSS

LPC5410x

PIO1_14 57

PIO0_18 58

PIO0_19 59

PIO0_20 60

PIO0_21 61

PIO1_15 62

PIO0_22 63

RESET 64

24 VDD

23 VDDA

22 VREFP

21 VREFN

20 VSSA

19 PIO1_5

18 PIO1_4

17 PIO1_3

aaa-013021

Fig 5. LQFP64 Pin configuration

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

6.2 Pin description

On the LPC5410x, digital pins are grouped into two ports. Each digital pin may support up

to four different digital functions and one analog function, including General Purpose I/O

(GPIO).

Table 4.

Symbol

Pin description

Description

[2]

PIO0_0

A6 31

PU I/O PIO0_0 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is the UART0 RXD function.

I

U0_RXD — Receiver input for USART0.

I/O SPI0_SSEL0 — Slave Select 0 for SPI0.

I

CT32B0_CAP0 — 32-bit CT32B0 capture input 0.

R — Reserved.

I

O

SCT0_OUT3 — SCT0 output 3. PWM output 3.

[2]

PIO0_1

B6 32

PU I/O PIO0_1 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is the UART0 TXD function.

O

U0_TXD — Transmitter output for USART0.

I/O SPI0_SSEL1 — Slave Select 1 for SPI0.

I

CT32B0_CAP1 — 32-bit CT32B0 capture input 1.

R — Reserved.

I

O

SCT0_OUT1 — SCT0 output 1. PWM output 1.

[2]

PIO0_2

PIO0_3

PIO0_4

-

36

37

PU I/O PIO0_2 — General-purpose digital input/output pin.

I

U0_CTS — Clear To Send input for USART0.

R — Reserved.

CT32B2_CAP1 — 32-bit CT32B2 capture input 1.

R — Reserved.

PU I/O PIO0_3 — General-purpose digital input/output pin.

O

I

U0_RTS — Request To Send output for USART0.

R — Reserved.

O

I

CT32B1_MAT3 — 32-bit CT32B1 match output 3.

R — Reserved.

C7 38

PU I/O PIO0_4 — General-purpose digital input/output pin.

I/O U0_SCLK — USART0 clock in synchronous USART mode.

I/O SPI0_SSEL2 — Slave Select 2 for SPI0.

I

CT32B0_CAP2 — 32-bit CT32B0 capture input 2.

R — Reserved.

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_5

PIO0_6

PIO0_7

C6 39

D7 40

D6 41

PU I/O PIO0_5 — General-purpose digital input/output pin.

I

U1_RXD — Receiver input for USART1.

SCT0_OUT6 — SCT0 output 6. PWM output 6.

CT32B0_MAT0 — 32-bit CT32B0 match output 0.

R — Reserved.

O

I

PU I/O PIO0_6 — General-purpose digital input/output pin.

O

I

U1_TXD — Transmitter output for USART1.

R — Reserved.

O

I

CT32B0_MAT1 — 32-bit CT32B0 match output 1.

R — Reserved.

PU I/O PIO0_7 — General-purpose digital input/output pin.

I/O U1_SCLK — USART1 clock in synchronous USART mode.

O

I

SCT0_OUT0 — SCT0 output 0. PWM output 0.

CT32B0_MAT2 — 32-bit CT32B0 match output 2.

R — Reserved.

I

CT32B0_CAP2 — 32-bit CT32B0 capture input 2.

[2]

PIO0_8

PIO0_9

D5 43

PU I/O PIO0_8 — General-purpose digital input/output pin.

I

U2_RXD — Receiver input for USART2.

SCT0_OUT1 — SCT0 output 1. PWM output 1.

CT32B0_MAT3 — 32-bit CT32B0 match output 3.

R — Reserved.

O

I

[2]

E7 44

PU I/O PIO0_9 — General-purpose digital input/output pin.

O

I

U2_TXD — Transmitter output for USART2.

SCT0_OUT2 — SCT0 output 2. PWM output 2.

CT32B3_CAP0 — 32-bit CT32B3 capture input 0.

R — Reserved.

I

I/O SPI0_SSEL0 — Slave Select 0 for SPI0.

[2]

PIO0_10

PIO0_11

E6 45

PU I/O PIO0_10 — General-purpose digital input/output pin.

I/O U2_SCLK — USART2 clock in synchronous USART mode.

O

I

SCT0_OUT3 — SCT0 output 3. PWM output 3.

CT32B3_MAT0 — 32-bit CT32B3 match output 0.

R — Reserved.

[2]

E5 46

PU I/O PIO0_11 — General-purpose digital input/output pin.

I/O SPI0_SCK — Serial clock for SPI0.

I

U1_RXD — Receiver input for USART1.

CT32B2_MAT1 — 32-bit CT32B2 match output 1.

R — Reserved.

O

I

LPC5410x

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Product data sheet

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LPC5410x

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32-bit ARM Cortex-M4/M0+ microcontroller

Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_12

PIO0_13

F7 47

PU I/O PIO0_12 — General-purpose digital input/output pin.

I/O SPI0_MOSI — Master Out Slave in for SPI0.

O

I

U1_TXD — Transmitter output for USART1.

CT32B2_MAT3 — 32-bit CT32B2 match output 3.

R — Reserved.

G7 48

PU I/O PIO0_13 — General-purpose digital input/output pin.

I/O SPI0_MISO — Master In Slave Out for SPI0.

O

I

SCT0_OUT4 — SCT0 output 4. PWM output 4.

CT32B2_MAT0 — 32-bit CT32B2 match output 0.

R — Reserved.

PIO0_14/TCK F6 49

PU I/O PIO0_14 — General-purpose digital input/output pin.

In boundary scan mode: TCK (Test Clock).

I/O SPI0_SSEL0 — Slave Select 0 for SPI0.

O

I

SCT0_OUT5 — SCT0 output 5. PWM output 5.

CT32B2_MAT1 — 32-bit CT32B2 match output 1.

R — Reserved.

[2]

PIO0_15/TDO G6 50

PU I/O PIO0_15 — General-purpose digital input/output pin.

In boundary scan mode: TDO (Test Data Out).

I/O SPI0_SSEL1 — Slave Select 1 for SPI0.

I/O SWO — Serial wire trace output.

O

I

CT32B2_MAT2 — 32-bit CT32B2 match output 2.

R — Reserved.

[2]

SWCLK/

PIO0_16

F5 52

PU I/O PIO0_16 — General-purpose digital input/output pin. After booting, this pin is

connected to the SWCLK.

I/O SPI0_SSEL2 — Slave Select 2 for SPI0.

I

U1_CTS — Clear To Send input for USART1.

CT32B3_MAT1 — 32-bit CT32B3 match output 1.

R — Reserved.

O

I

I/O SWCLK — Serial Wire Clock. This is the default function after booting.

[2]

SWDIO/

PIO0_17

G5 53

PU I/O PIO0_17 — General-purpose digital input/output pin. After booting, this pin is

connected to SWDIO.

I/O SPI0_SSEL3 — Slave Select 3 for SPI0.

O

I

U1_RTS — Request To Send output for USART1.

CT32B3_MAT2 — 32-bit CT32B3 match output 2.

R — Reserved.

I/O SWDIO — Serial Wire Debug I/O. This is the default function after booting.

LPC5410x

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Product data sheet

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO0_18/TRST G4 58

PU I/O PIO0_18 — General-purpose digital input/output pin. In boundary scan mode:

TRST (Test Reset).

O

I

U3_TXD — Transmitter output for USART3.

SCT0_OUT0 — SCT0 output 0. PWM output 0.

CT32B0_MAT0 — 32-bit CT32B0 match output 0.

R — Reserved.

PIO0_19/TDI

G3 59

PU I/O PIO0_19 — General-purpose digital input/output pin. In boundary scan mode: TDI

(Test Data In).

I/O U3_SCLK — USART3 clock in synchronous USART mode.

O

I

SCT0_OUT1 — SCT0 output 1. PWM output 1.

CT32B0_MAT1 — 32-bit CT32B0 match output 1.

R — Reserved.

PIO0_20/TMS F3 60

PU I/O PIO0_20 — General-purpose digital input/output pin. In boundary scan mode: TMS

(Test Mode Select).

I

U3_RXD — Receiver input for USART3.

I/O U0_SCLK — USART0 clock in synchronous USART mode.

I

CT32B3_CAP0 — 32-bit CT32B3 capture input 0.

R — Reserved.

[2]

[3]

PIO0_21

PIO0_22

PIO0_23

E3 61

PU I/O PIO0_21 — General-purpose digital input/output pin.

O

I

CLKOUT — Clock output pin.

U0_TXD — Transmitter output for USART0.

CT32B3_MAT0 — 32-bit CT32B3 match output 0.

R — Reserved.

G2 63

PU I/O PIO0_22 — General-purpose digital input/output pin.

I

CLKIN — Clock input.

I

U0_RXD — Receiver input for USART0.

CT32B3_MAT3 — 32-bit CT32B3 match output 3.

R — Reserved.

O

I

F2

1

Z

I/O PIO0_23 — General-purpose digital input/output pin.

I/O I2C0_SCL — I²C0 clock input/output.

I

R — Reserved.

CT32B0_CAP0 — 32-bit CT32B0 capture input 0.

R — Reserved.

LPC5410x

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Table 4.

Symbol

Pin description …continued

Description

[3]

PIO0_24

PIO0_25

F1

2

3

Z

I/O PIO0_24 — General-purpose digital input/output pin.

I/O I2C0_SDA — I²C0 data input/output.

I

R — Reserved.

I

CT32B0_CAP1 — 32-bit CT32B0 capture input 1.

R — Reserved.

I

O

CT32B0_MAT0 — 32-bit CT32B0 match output 0.

[3]

E2

I/O PIO0_25 — General-purpose digital input/output pin.

I/O I2C1_SCL — I²C1 clock input/output.

I

U1_CTS — Clear To Send input for USART1.

CT32B0_CAP2 — 32-bit CT32B0 capture input 2.

R — Reserved.

CT32B1_CAP1 — 32-bit CT32B1 capture input 1.

[3]

[4]

PIO0_26

PIO0_27

PIO0_28

E1

D2

D1

4

5

6

Z

I/O PIO0_26 — General-purpose digital input/output pin.

I/O I2C1_SDA — I²C1 data input/output.

I

R — Reserved.

CT32B0_CAP3 — 32-bit CT32B0 capture input 3.

R — Reserved.

I/O PIO0_27 — General-purpose digital input/output pin.

I/O I2C2_SCL — I²C2 clock input/output.

I

R — Reserved.

CT32B2_CAP0 — 32-bit CT32B2 capture input 0.

R — Reserved.

I/O PIO0_28 — General-purpose digital input/output pin.

I/O I2C2_SDA — I²C2 data input/output.

I

R — Reserved.

O

I

CT32B2_MAT0 — 32-bit CT32B2 match output 0.

R — Reserved.

PIO0_29/

ADC0_0

D3 11

PU I/O; PIO0_29/ADC0_0 — General-purpose digital input/output pin (default). ADC input

AI channel 0 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

O

I

SCT0_OUT2 — SCT0 output 2.

CT32B0_MAT3 — 32-bit CT32B0 match output 3.

R — Reserved.

I

CT32B0_CAP1 — 32-bit CT32B0 capture input 1.

CT32B0_MAT1 — 32-bit CT32B0 match output 1.

O

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO0_30/

ADC0_1

C1 12

PU I/O; PIO0_30/ADC0_1 — General-purpose digital input/output pin (default). ADC input

AI channel 1 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

O

I

SCT0_OUT3 — SCT0 output 3.

CT32B0_MAT2 — 32-bit CT32B0 match output 2.

R — Reserved.

I

CT32B0_CAP2 — 32-bit CT32B0 capture input 2.

[4]

PIO0_31/

ADC0_2

C2 13

PU I/O; PIO0_31/ADC0_2 — General-purpose digital input/output pin (default). ADC input

AI channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

Remark: This pin is also used to force In-System Programming mode (ISP) after

device reset. See the LPC5410x User Manual (Boot Process chapter) for details.

-

R — Reserved.

I

U2_CTS — Clear To Send input for USART2.

CT32B2_CAP2 — 32-bit CT32B2 capture input 2.

R — Reserved.

I

CT32B0_CAP3 — 32-bit CT32B0 capture input 3.

CT32B0_MAT3 — 32-bit CT32B0 match output 3.

O

[4]

PIO1_0/

ADC0_3

C3 14

PU I/O; PIO1_0/ADC0_3 — General-purpose digital input/output pin (default). ADC input

AI channel 3 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

O

I

U2_RTS — Request To Send output for USART2.

CT32B3_MAT1 — 32-bit CT32B3 match output 1.

R — Reserved.

I

CT32B0_CAP0 — 32-bit CT32B0 capture input 0.

[4]

PIO1_1/

ADC0_4

B1 15

PU I/O; PIO1_1/ADC0_4 — General-purpose digital input/output pin (default). ADC input

AI channel 4 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SWO — Serial wire trace output.

SCT0_OUT4 — SCT0 output 4.

O

[4]

PIO1_2/

ADC0_5

A1 16

PU I/O; PIO1_2/ADC0_5 — General-purpose digital input/output pin (default). ADC input

AI channel 5 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_SSEL3 — Slave Select 3 for SPI1.

O

SCT0_OUT5 — SCT0 output 5.

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO1_3/

ADC0_6

B2 17

A2 18

B3 19

A5 26

PU I/O; PIO1_3/ADC0_6 — General-purpose digital input/output pin (default). ADC input

AI channel 6 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_SSEL2 — Slave Select 2 for SPI1.

O

I

SCT0_OUT6 — SCT0 output 6.

R — Reserved.

I/O SPI0_SCK — Serial clock for SPI0.

CT32B0_CAP1 — 32-bit CT32B0 capture input 1.

I

PIO1_4/

ADC0_7

PU I/O; PIO1_4/ADC0_7 — General-purpose digital input/output pin (default). ADC input

AI channel 7 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_SSEL1 — Slave Select 1 for SPI1.

O

I

SCT0_OUT7 — SCT0 output 7.

R — Reserved.

I/O SPI0_MISO — Master In Slave Out for SPI0.

CT32B0_MAT1 — 32-bit CT32B0 match output 1.

O

PIO1_5/

ADC0_8

PU I/O; PIO1_5/ADC0_8 — General-purpose digital input/output pin (default). ADC input

AI channel 8 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_SSEL0 — Slave Select 0 for SPI1.

I

CT32B1_CAP0 — 32-bit CT32B1 capture input 0.

R — Reserved.

I

O

I

CT32B1_MAT3 — 32-bit CT32B1 match output 3.

R — Reserved.

PIO1_6/

ADC0_9

PU I/O; PIO1_6/ADC0_9 — General-purpose digital input/output pin (default). ADC input

AI channel 9 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_SCK — Serial clock for SPI1.

I

CT32B1_CAP2 — 32-bit CT32B1 capture input 2.

R — Reserved.

-

O

I

CT32B1_MAT2 — 32-bit CT32B1 match output 2.

R — Reserved.

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Table 4.

Symbol

Pin description …continued

Description

[4]

PIO1_7/

B5 27

PU I/O; PIO1_7/ADC0_10 — General-purpose digital input/output pin (default). ADC input

ADC0_10

AI channel 10 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_MOSI — Master Out Slave in for SPI1.

O

-

CT32B1_MAT2 — 32-bit CT32B1 match output 2.

R — Reserved.

I

CT32B1_CAP2 — 32-bit CT32B1 capture input 2.

R — Reserved.

I

[4]

PIO1_8/

C5 28

PU I/O; PIO1_8/ADC0_11 — General-purpose digital input/output pin (default). ADC input

ADC0_11

AI channel 11 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

-

R — Reserved.

I/O SPI1_MISO — Master In Slave Out for SPI1.

O

I

CT32B1_MAT3 — 32-bit CT32B1 match output 3.

R — Reserved.

I

CT32B1_CAP3 — 32-bit CT32B1 capture input 3.

R — Reserved.

I

[2]

PIO1_9

-

29

30

42

51

PU I/O PIO1_9 — General-purpose digital input/output pin.

R — Reserved.

I/O SPI0_MOSI — Master Out Slave In for SPI0.

CT32B0_CAP2 — 32-bit CT32B0 capture input 2.

PU I/O PIO1_10 — General-purpose digital input/output pin.

I

PIO1_10

PIO1_11

PIO1_12

I

R — Reserved.

O

U1_TXD — Transmitter output for USART1.

SCT0_OUT4 — SCT0 output 4.

PU I/O PIO1_11 — General-purpose digital input/output pin.

I

R — Reserved.

O

I

U1_RTS — Request To Send output for USART1.

CT32B1_CAP0 — 32-bit CT32B1 capture input 0.

PU I/O PIO1_12 — General-purpose digital input/output pin.

I

R — Reserved.

I

U3_RXD — Receiver input for USART3.

CT32B1_MAT0 — 32-bit CT32B1 match output 0.

O

I/O SPI1_SCK — Serial clock for SPI1.

[2]

PIO1_13

-

54

PU I/O PIO1_13 — General-purpose digital input/output pin.

I

R — Reserved.

O

U3_TXD — Transmitter output for USART3.

CT32B1_MAT1 — 32-bit CT32B1 match output 1.

I/O SPI1_MOSI — Master Out Slave In for SPI1.

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Table 4.

Symbol

Pin description …continued

Description

[2]

PIO1_14

PIO1_15

PIO1_16

-

57

62

7

PU I/O PIO1_14 — General-purpose digital input/output pin.

I

R — Reserved.

I

U2_RXD — Receiver input for USART2.

SCT0_OUT7 — SCT0 output 7.

O

I/O SPI1_MISO — Master In Slave Out for SPI1.

PU I/O PIO1_15 — General-purpose digital input/output pin.

I

R — Reserved.

O

I

SCT0_OUT5 — SCT0 output 5.

CT32B1_CAP3 — 32-bit CT32B1 capture input 3.

I/O SPI1_SSEL0 — Slave Select 0 for SPI1.

PU I/O PIO1_16 — General-purpose digital input/output pin.

I

R — Reserved.

O

I

CT32B0_MAT0 — 32-bit CT32B0 match output 0.

CT32B0_CAP0 — 32-bit CT32B0 capture input 0.

I/O SPI1_SSEL1 — Slave Select 1 for SPI1.

[2]

[5]

PIO1_17

RESET

10

PU I/O PIO1_17 — General-purpose digital input/output pin.

G1 64

PU I

External reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. Wakes up the part from deep power-down mode.

RTCXIN

RTCXOUT

VREFP

VREFN

VDDA

A7 33

B7 35

B4 22

-

RTC oscillator input.

RTC oscillator output.

ADC positive reference voltage.

ADC negative reference voltage.

Analog supply voltage.

-

21

A4 23

VDD

C4, 8,

F4 24,

56,

Single 1.62 V to 3.6 V power supply powers internal digital functions and I/Os.

34

VSS

D4, 9,

E4 25,

55

-

Ground.

VSSA

A3 20

Analog ground.

[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to V_DD). Z = high impedance; pull-up or pull-down disabled.

Reset state reflects the pin state at reset without boot code operation. For pin states in the different power modes, see Section 6.2.2 “Pin

states in different power modes”. For termination on unused pins, see Section 6.2.1 “Termination of unused pins”.

[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if V_DDpresent; if V_DDnot present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength. See Figure 27. Pulse width of spikes or glitches suppressed by input

filter is from 3 ns to 16 ns (simulated value).

[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not

disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

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[4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to

20 ns (simulated value)

[6] I = Input; AI = Analog input; O = Output

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6.2.1 Termination of unused pins

Table 5 shows how to terminate pins that are not used in the application. In many cases,

unused pins should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 5.

Termination of unused pins

Default Recommended termination of unused pins

state^[1]

RESET

I; PU

The RESET pin can be left unconnected if the application does not use it.

all PIOn_m (not open-drain) I; PU

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

RTCXIN

IA

-

Can be left unconnected if driven LOW and configured as GPIO output by software.

Connect to ground. When grounded, the RTC oscillator is disabled.

RTCXOUT

VREFP

-

Can be left unconnected.

Tie to VDD.

-

VREFN

-

Tie to VSS.

VDDA

-

Tie to VDD.

VSSA

-

Tie to VSS.

[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up.

6.2.2 Pin states in different power modes

Table 6.

Pin states in different power modes

Active

Sleep

Deep sleep/Power down Deep power-down

PIOn_m pins (not I2C)

As configured in the IOCON^[1]. Default: internal pull-up enabled. Floating.

PIO0_23 to PIO0_28 (open-drain As configured in the IOCON^[1].

I2C-bus pins)

Floating.

RESET

Reset function enabled. Default: input, internal pull-up enabled.

Reset function disabled.

[1] Default and programmed pin states are retained in sleep, deep sleep, and power down modes.

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7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and

D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is

dedicated for data access (D-code). The use of two core buses allows for simultaneous

operations if concurrent operations target different devices.

A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in

a flexible manner that optimizes performance by allowing peripherals on different slaves

ports of the matrix to be accessed simultaneously by different bus masters. Connections

in the multilayer matrix are shown in Figure 3.

APB peripherals are connected to the AHB matrix via two APB buses using separate

slave ports from the multilayer AHB matrix. This allows for better performance by reducing

collisions between the CPU and the DMA controller, and also for peripherals on the

asynchronous bridge to have a fixed clock that does not track the system clock.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M4 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root operations. It also provides conversions between fixed-point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 standard.

7.4 Memory Protection Unit (MPU)

The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

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The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4

The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• 37 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.6 ARM Cortex-M0+ co-processor

The ARM Cortex-M0+ co-processor offers high performance and very low power

consumption. This processor uses a 2-stage pipeline von Neumann architecture and a

small but powerful instruction set providing high-end processing hardware. The processor

includes an NVIC with 32 interrupts and a separate system tick timer. In LPC5410x, the

Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative

multiplier.

7.7 Nested Vectored Interrupt Controller (NVIC) for Cortex-M0+

The NVIC is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

7.7.1 Features

• Controls system exceptions and peripheral interrupts.

• 32 vectored interrupts.

• Four programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

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7.7.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.8 System Tick timer (SysTick)

The ARM Cortex-M4 and ARM Cortex-M0+ cores include a system tick timer (SysTick)

that is intended to generate a dedicated SYSTICK exception. The clock source for the

SysTick can be the system clock or the SYSTICK clock.

7.9 On-chip static RAM

The LPC5410x support 104 kB SRAM with separate bus master access for higher

throughput and individual power control for low-power operation.

7.10 On-chip flash

The LPC5410x supports 512 kB of on-chip flash memory.

7.11 On-chip ROM

The 64 kB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

programming.

• Power control API for configuring power consumption and PLL settings.

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7.12 Memory mapping

The LPC5410x incorporates several distinct memory regions. The APB peripheral area is

512 kB in size and is divided to allow for up to 32 peripherals.Each peripheral is allocated

16 kB of space simplifying the address decoding. The registers incorporated into the CPU,

such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.

Figure 6 shows the overall map of the entire address space from the user program

viewpoint following reset.

APB1 peripherals

0x400F FFFF

31-15

14

13

12

11

10

9

(reserved)

Timer 1

Memory space

(reserved)

0x400B C000

0x400B 8000

0x400B 4000

0x400B 0000

0x400A C000

0x400A 8000

0x400A 4000

0x400A 0000

0x4009 C000

0x4009 8000

0x4009 4000

0x4009 0000

0x4008 C000

0x4008 8000

0x4008 4000

0x4008 0000

4 GB

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x4400 0000

Timer 0

private peripheral bus

(reserved)

SPI 1

APB peripheral

bit-band addressing

SPI 0

0x4200 0000

0x4010 0000

(reserved)

APB peripheral group 1

APB peripheral group 0

(reserved)

8

(reserved)

I 2C 2

7

0x4008 0000

0x4000 0000

0x1C03 C000

0x1C03 8000

0x1C03 4000

0x1C03 0000

0x1C02 C000

0x1C01 C000

0x1C01 8000

0x1C01 4000

0x1C01 0000

0x1C00 8000

0x1C00 4000

0x1C00 0000

6

I2C 1

5

I2C 0

4

USART 3

USART 2

USART 1

USART 0

ASYNCHSYSCON

Peripheral FIFOs (VFIFO)

ADC0

3

2

(reserved)

1

Mailbox

0

(reserved)

APB0 peripherals

SCT0

0x4007 FFFF

0x4007 8000

0x4007 4000

0x4007 0000

0x4005 4000

0x4005 0000

0x4004 0000

0x4003 C000

0x4003 8000

31-30

(reserved)

MRT

reserved

29

28

CRC Engine

(reserved)

RIT

27-21

20

(reserved)

Input Mux

(reserved)

RTC

DMA registers

GPIO

19:16

15

reserved

14

13:12

Watchdog Timer

(reserved)

0x0340 2000

0x0340 0000

SRAM2 (8 kB)

(reserved)

Boot and Driver ROM

(reserved)

11

10

ADVSYSCON

reserved

0x4002 C000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

0x0301 0000

0x0300 0000

0x0201 8000

9

8

7

6

5

4

3

2

1

0

Flash controller

MicroTick Timer

IOCON

SRAM1 (up to 32 kB)

0x0201 0000

PINT

SRAM0 (up to 64 kB)

reserved

GINT 1

0x0200 0000

0x0008 0000

GINT 0

Timer

4

3

2

512 kB flash memory

0x0000 0000

Syscon

0x0000 00C0

0x0000 0000

active interrupt vectors

aaa-015472

Fig 6. LPC5410x Memory mapping

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7.13 General Purpose I/O (GPIO)

The LPC5410x provides two GPIO ports with a total of 50 GPIO pins.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The current level

of a port pin can be read back no matter what peripheral is selected for that pin.

See Table 4 for the default state on reset.

7.13.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set, clear and toggle registers allow a single instruction set, clear or toggle of

any number of bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt

request.

• One GPIO group interrupt can be triggered by a combination of any pin or pins.

7.14 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC. The pattern match engine can be used in

conjunction with software to create complex state machines based on pin inputs. Any

digital pin, independent of the function selected through the switch matrix can be

configured through the SYSCON block as an input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the I/O+ bus for fast single-cycle access.

7.14.1 Features

• Pin interrupts:

– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode, deep sleep mode, and

power down mode.

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• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

7.15 AHB peripherals

7.15.1 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional DMA

transfers for a single source and destination.

7.15.1.1 Features

• 22 channels, 21 of which are connected to peripheral DMA requests. These come

from the USART, SPI, and I²C peripherals. One spare channels has no DMA request

connected, and can be used for functions such as memory-to-memory moves.

• DMA operations can be triggered by on- or off-chip events. Each DMA channel can

select one trigger input from 20 sources. Trigger sources include ADC interrupts,

Timer interrupts, pin interrupts, and the SCT DMA request lines.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

7.16 Digital serial peripherals

7.16.1 USART

7.16.1.1 Features

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.

• Maximum supported bit rate of 24 Mbit/s for USART master and slave synchronous

modes.

• 7, 8, or 9 data bits and 1 or 2 stop bits.

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• Multiprocessor/multidrop (9-bit) mode with software address compare.

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• FIFO support from the System FIFO.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep sleep and power down

modes.

• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC

oscillator as the UART clock. This mode can be used while the device is in deep sleep

or power down mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

• Activity on the USART synchronous slave mode allows wake-up from deep sleep and

power down modes on any enabled interrupt.

7.16.2 SPI serial I/O controller

7.16.2.1 Features

• Master and slave operation.

• Maximum supported bit rate for SPI master mode is 48 Mbit/s, and the maximum

supported bit rate for SPI slave mode is 21 Mbit/s.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Up to four Slave Select input/outputs with selectable polarity and flexible usage.

• Supports DMA transfers: SPIn transmit and receive functions can operated with the

system DMA controller.

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• FIFO support from the System FIFO.

• Activity on the SPI in slave mode allows wake-up from deep sleep and power down

modes on any enabled interrupt.

7.17 I²C-bus interface

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I²C is a multi-master bus and

can be controlled by more than one bus master connected to it.

7.17.1 Features

• All I²Cs support standard (up to 100 Kbits/s), fast mode (up to 400 Kbits/s), and

Fast-mode Plus (up to 1 Mbit/s).

• All I²Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I²C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C-bus addresses.

• 10-bit addressing supported with software assist.

• Supports System Management Bus (SMBus).

• No chip clocks are required in order to receive and compare an address as a Slave,

so this event can wake up the device from power down mode.

• Supports the I²C-bus specification up to Fast-mode Plus (FM+, up to 1 MHz) in both

master and slave modes. High-speed (HS, up to 3.4 MHz) I²C is support in slave

mode only.

• Activity on the I²C in slave mode allows wake-up from deep sleep and power down

modes on any enabled interrupt.

7.18 Counter/timers

7.18.1 General-purpose 32-bit timers/external event counter

The LPC5410x includes five general-purpose 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

7.18.1.1 Features

• Each is a 32-bit counter/timer with a programmable 32-bit prescaler. Four of the

timers include external capture and match pin connections.

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• Counter or timer operation.

• For each timer with pin connections, up to 4 32-bit capture channels that can take a

snapshot of the timer value when an input signal transitions. A capture event may also

optionally generate an interrupt.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse-width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• For each timer with pin connections, up to 4 external outputs corresponding to match

registers with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• PWM: for each timer with pin connections, up to 3 match outputs can be used as

single edge controlled PWM outputs.

7.18.2 State Configurable Timer/PWM (SCTimer/PWM)

The SCTimer/PWM (SCT0) allows a wide variety of timing, counting, output modulation,

and input capture operations. The inputs and outputs of the SCTimer/PWM are shared

with the capture and match inputs/outputs of the 32-bit general-purpose counter/timers.

The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT, but the

last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

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7.18.2.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.

• Up counter(s) or up-down counter(s).

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs, interrupts, and the SCT states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected event(s) can limit, halt, start, or stop a counter.

• Supports:

– 8 inputs (6 GPIO pins, ADC0_THCMP_IRQ, DEBUG_HALTED)

– up to 8 outputs

– 13 match/capture registers

– 13 events

– 13 states

• PWM capabilities including dead time and emergency abort functions

7.18.3 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.18.3.1 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time-out period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (T_WDCLK 256  4) to over 67

million watchdog clocks (T_WDCLK 2²⁴ 4) in increments of 4 watchdog clocks.

• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog

reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be

changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.

• The Watchdog clock (WDCLK) source is the fixed 500 kHz clock (+/- 40%) provided

by the low-power watchdog oscillator.

• The Watchdog timer can be configured to run in deep sleep or power down mode.

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• Debug mode.

7.18.4 RTC timer

The RTC block has two timers: main RTC timer, and high-resolution/wake-up timer. The

main RTC timer is a 32-bit timer that uses a 1 Hz clock and is intended to run continuously

as a real-time clock. When the timer value reaches a match value, an interrupt is raised.

The alarm interrupt can also wake up the part from any low power mode, if enabled.

The high-resolution or wake-up timer is a 16-bit timer that uses a 1 kHz clock and

operates as a one-shot down timer. When the timer is loaded, it starts counting down to 0

at which point an interrupt is raised. The interrupt can wake up the part from any low

power mode, if enabled. This timer is intended to be used for timed wake-up from deep

sleep, power down, or deep power-down modes. The high-resolution wake-up timer can

be disabled to conserve power if not used.

The RTC timer uses the 32 kHz clock input to create a 1 Hz or 1 kHz clock

7.18.4.1 Features

• The RTC oscillator has the following clock outputs:

– 32 kHz clock, selectable for system clock and CLKOUT pin.

– 1 Hz clock for RTC timing.

– 1 kHz clock for high-resolution RTC timing.

• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.

• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution

with a more that one minute maximum time-out period.

• RTC alarm and high-resolution/wake-up timer time-out each generate independent

interrupt requests. Either time-out can wake up the part from any of the low power

modes, including deep power-down.

7.18.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

7.18.5.1 Features

• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.

• Repeat interrupt, one-shot interrupt, and one-shot bus stall modes.

7.18.6 Repetitive Interrupt Timer (RIT)

The Repetitive Interrupt Timer provides a versatile means of generating interrupts at

specified time intervals, without using a standard timer. It is intended for repeating

interrupts that are not related to Operating System interrupts. However, it could be used

as an alternative to the System Tick Timer if there are different system requirements.

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7.18.6.1 Features

• 48-bit counter running from the main clock. Counter can be free-running or be reset

by a generated interrupt.

• 48-bit compare value.

• 48-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

7.18.7 Micro-tick timer (UTICK)

The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used

to wake up the device from low power modes.

7.18.7.1 Features

• Ultra simple timer.

• Write once to start.

• Interrupt or software polling.

7.19 12-bit Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12-bit and fast conversion rates of up to 5.0

Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple

sources. Possible trigger sources are the SCT, external pins, and the ARM TXEV

interrupt.

The ADC supports a variable clocking scheme with clocking synchronous to the system

clock or independent, asynchronous clocking for high-speed conversions

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCT inputs for tight timing

control between the ADC and the SCT.

7.19.1 Features

• 12-bit successive approximation analog to digital converter.

• Input multiplexing among up to 12 pins.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and “zero crossing” detection.

• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage

level).

• 12-bit conversion rate of 5.0 MHz. Options for reduced resolution at higher conversion

rates.

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• Burst conversion mode for single or multiple inputs.

• Synchronous or asynchronous operation. Asynchronous operation maximizes

flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger

latency and can eliminate uncertainty and jitter in response to a trigger.

7.20 System control

7.20.1 Clock sources

The LPC5410x supports two external and three internal clock sources:

• The Internal RC (IRC).

• Watchdog oscillator (WDOSC).

• External clock source from the digital I/O pin CLKIN.

• External RTC 32 KHz clock.

• Output of the system PLL.

7.20.1.1 Internal RC oscillator (IRC)

The IRC can be used as the clock that drives the system PLL and subsequently the CPU.

The nominal IRC frequency is 12 MHz.

Upon power-up or any chip reset, the LPC5410x uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.20.1.2 Watchdog oscillator (WDOSC)

The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to

provide a clock to the WWDT and to the entire chip. The nominal output frequency is

500 kHz.

7.20.1.3 Clock input pin (CLKIN)

An external square-wave clock source (up to 25 MHz) can be supplied on the digital I/O

pin CLKIN.

7.20.2 System PLL

The system PLL accepts an input clock frequency in the range of 32 kHz to 12 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

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7.20.3 Clock Generation

irc_clk

CLKIN

wdt_clk

00

01

10

sysclk

Main clock select A

MAINCLKSELA[1:0]

00

01

10

11

to CPU, AHB

bus, Sync

irc_clk

00

APB, etc.

main clock

CPU Clock

pll_clk

32k_clk

CLKIN

Divider

System PLL

(PLL0)

01

32k_clk

11

System clock divider

AHBCLKDIV[7:0]

System PLL

settings

main clock

00

Main clock select B

MAINCLKSELB[1:0]

PLL clock select

SYSPLLCLKSEL[1:0]

CLKIN

to async

APB bridge

01

10

11

Async APB

Divider

pll_clk

Async APB clock divider

ASYNCAPBCLKDIV[7:0]

irc_clk

00

01

wdt_clk

APB clock select B

ASYNCAPBCLKSELB[1:0]

APB clock select A

ASYNCAPBCLKSELA[1:0]

main clock

pll_clk

00

01

10

to ADC

ADC Clock

Divider

irc_clk

AD C clock divider

ADCCLKDIV[7:0]

ADC clock select

ADCCLKSEL[1:0]

main clock

00

01

10

11

CLKOUTDIV[7:0]

CLKIN

wdt_clk

irc_osc

00

11

CLKOUT

Divider

32k_osc

CLKOUT select B

CLKOUTSELB[1:0]

CLKOUT select A

CLKOUTSELA[1:0]

aaa-015553

Fig 7. LPC5410x clock generation

7.20.4 Power control

The LPC5410x support a variety of power control features. In Active mode, when the chip

is running, power and clocks to selected peripherals can be optimized for power

consumption. In addition, there are four special modes of processor power reduction with

different peripherals running: Sleep mode, deep sleep mode, power down mode, and

deep power-down mode, activated by the power mode configure API.

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7.20.4.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped along with any unused

peripherals. Waking up from the sleep mode does not need any special sequence other

than re-enabling the clock to the ARM core.

In sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, internal

buses, and unused peripherals. The processor state and registers, peripheral registers,

and internal SRAM values are maintained, and the logic levels of the pins remain static.

7.20.4.2 Deep sleep mode

In deep sleep mode, all peripheral clocks and all clock sources are off with the option of

keeping the 32 kHz clock and the WDOSC running. In addition, all analog blocks are shut

down and the flash is put in stand-by mode. In deep sleep mode, the application can keep

some of the internal clocks and the BOD circuit running for self-timed wake-up and BOD

protection.

The LPC5410x can wake up from deep sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer reset interrupt,

BOD interrupt/reset, or an interrupt from the USART (in 32 kHz mode or synchronous

slave mode), the SPI, or any of the I2C peripherals. For wake-up from deep sleep mode,

the SPI, USART, and I2C peripherals must be configured in slave mode.

Any interrupt used for waking up from deep sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

In deep sleep mode, the processor state and registers, peripheral registers, and internal

SRAM values are maintained, and the logic levels of the pins remain static. deep sleep

mode allows for very low quiescent power and fast wake-up options.

7.20.4.3 Power down mode

In power down mode, all peripheral clocks and all clock sources are off with the option of

keeping the 32 kHz clock, and the WDOSC running. In addition, all analog blocks and the

flash are shut down. In power down mode, the application can keep the BOD circuit

running for BOD protection.

The LPC5410x can wake up from power down mode via a reset, digital pins selected as

inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer reset interrupt,

BOD interrupt/reset, or an interrupt from the USART (in 32 kHz mode or synchronous

slave mode), the SPI, or any of the I2C peripherals. For wake-up from power down mode,

the SPI, USART, and I2C peripherals must be configured in slave mode.

In power down mode, the processor state and registers, peripheral registers, and internal

SRAM values are maintained, and the logic levels of the pins remain static. Power down

mode reduces power consumption compared to deep sleep mode at the expense of

longer wake-up times.

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7.20.4.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain and the RESET pin. The LPC5410x can wake up from deep power down mode

via the RESET pin and the RTC alarm.

7.20.5 Brownout detection

The LPC5410x includes a monitor for the voltage level on the V_DDpin. If this voltage falls

below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In

addition, a separate threshold levels can be selected to cause chip reset and interrupt.

7.20.6 Safety

The LPC5410x includes a Windowed WatchDog Timer (WWDT), which can be enabled

by software after reset. Once enabled, the WWDT remains locked and cannot be modified

in any way until a reset occurs.

7.21 Code security (Code Read Protection - CRP)

This feature of the LPC5410x allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry can be invoked by pulling a pin on the LPC5410x LOW on reset.

This pin is called the ISP entry pin.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s

application to provide (if needed) flash update mechanism using IAP calls or a call to

reinvoke ISP command to enable a flash update via USART.

4. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code

can be disabled (No_ISP mode). For details, see the LPC5410x user manual.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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7.22 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M4 and ARM Cortex-M0+.

Serial wire debug and trace functions are supported. The ARM Cortex-M4 is configured to

support up to eight breakpoints and four watch points. The ARM Cortex-M0+ is configured

to support up to four breakpoints and two watch points. In addition, JTAG boundary scan

mode is provided.

The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

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8. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

Parameter

Conditions

Min

Max

Unit

[2]

V_DD

supply voltage (core and on pin VDD

external rail)

0.5

+4.6

V

V_DDA

V_ref

V_I

analog supply voltage

reference voltage

input voltage

on pin VDDA

-0.5

0.5

+4.6

5.0

V

on pin VREFP

-

[6][7]

only valid when the V_DD> 1.8 V;

5 V tolerant I/O pins

on I2C open-drain pins

[5]

V_I

input voltage

0.5

+5.0

V_DD

V

[8][9]

V_IA

analog input voltage

on digital pins configured for an

analog function

[3]

I_DD

total supply current

total ground current

I/O latch-up current

-

60

mA

I_SS

60

I_latch

(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 C

100

[2]

V_i(rtcx)

32 kHz oscillator input

voltage

-0.5

4.6

V

[10]

T_stg

storage temperature

65

+150

C

T_j(max)

maximum junction

temperature

-

P_tot(pack)

V_ESD

total power dissipation

(per package)

based on package heat transfer,

not device power consumption

-

1.5

W

V

[4]

electrostatic discharge

voltage

human body model; all pins

4000

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 16.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 16) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[5] V_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

[6] Applies to all 5 V tolerant I/O pins except true open-drain pins.

[7] Including the voltage on outputs in 3-state mode.

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[8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 10⁶s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

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9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T _j= T_amb+ P_D R_{th j – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 8.

Thermal resistance

Symbol Parameter

LQFP64 Package

Conditions

Max/Min

Unit

R_th(j-a)

thermal resistance from

JEDEC (4.5 in  4 in); still air

58 ± 15 % C/W

junction to ambient

Single-layer (4.5 in  3 in); still air 81 ± 15 % C/W

18 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

WLCSP49 Package

R_th(j-a)thermal resistance from

JEDEC (4.5 in  4 in); still air

41 ± 15 % C/W

0.3 ± 15 % C/W

junction to ambient

R_th(j-c)

thermal resistance from

junction to case

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10. Static characteristics

10.1 General operating conditions

Table 9.

General operating conditions

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

f_clk

Parameter

Conditions

Min

-

Typ

Max

150

3.6

Unit

MHz

V

clock frequency

internal CPU/system clock

-

V_DD

supply voltage (core

and external rail)

1.62

[1]

[2]

V_DDA

V_refp

analog supply voltage

1.62

2.0

-

3.6

V

ADC positive reference V_DDA2 V

V_DDA

voltage

V_DDA< 2 V

V_DDA

-

V_DDA

V

RTC oscillator pins

V_i(rtcx)32 kHz oscillator input

voltage

on pin RTCXIN

0.5

-

+3.6

V

V_o(rtcx)

32 kHz oscillator output on pin RTCXOUT

voltage

[1] The V_DDvoltage must be equal or lower than the voltage level on V_DDA

.

[2] The V_refpvoltage must not exceed the voltage level on V_DDA

.

10.2 CoreMark data

Table 10. CoreMark score

T_amb= 25C, V_DD= 3.3V

Parameter

Conditions

Typ

Unit

ARM Cortex-M4 in active mode; ARM Cortex-M0+ in sleep mode

CoreMark score

CoreMark code executed from SRAM;

CCLK = 12 MHz

[1][3][4][5]

[2][3][4][5]

2.6

(Iterations/s) / MHz

CCLK = 48 MHz

CCLK = 84 MHz

CCLK = 100 MHz

CCLK = 150 MHz

CoreMark score

CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock flash

access time.

[1][3][4][6]

[2][3][4][6]

2.6

2.4

(Iterations/s) / MHz

CCLK = 48 MHz; 3 system clock flash

access time.

[2][3][4][6]

CCLK = 84 MHz; 5 system clock flash

access time.

2.3

(Iterations/s) / MHz

CCLK = 100 MHz; 6 system clock flash

access time.

2.2

CCLK = 150 MHz; 7 system clock flash

access time.

1.94

[1] Clock source 12 MHz IRC. PLL disabled.

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[2] Clock source 12 MHz IRC. PLL enabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: Keil μVision v.5.12, optimization level 3, optimized for time on.

[5] SRAM0 and SRAM1 powered, SRAM2 powered down.

[6] See the FLASHCFG register in the LPC5410x User Manual for system clock flash access time settings.

aaa-015950

3

Coremark score

(iterations/s) / MHz)

M4 SRAM

2.6

M4 Flash

2.2

1.8

1.4

1

12

24

36

48

60

72

84

96

108

Frequency (MHz)

Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals except one UART; BOD

disabled; SRAM0 and SRAM1 powered, SRAM2 powered down. See the FLASHCFG register in

the LPC5410x User Manual for system clock flash access time settings. Measured with Keil

uVision 5.12. Optimization level 3, optimized for time on.

12 MHz: IRC enabled; PLL disabled. 24 MHz - 100 MHz: IRC enabled; PLL enabled.

Fig 8. Typical CoreMark score

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10.3 Power consumption

Power measurements in Active, sleep, deep sleep, and power down modes were

performed under the following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

• All peripherals disabled.

Table 11. Static characteristics: Power consumption in active and sleep modes

T_amb= 40 C to +105 C, unless otherwise specified.1.62 V  V_DD 3.6 V.

Symbol Parameter Conditions

ARM Cortex-M0+ in active mode; ARM Cortex-M4 in sleep mode

Min

Typ^[1]

Max

Unit

I_DD

supply current

CoreMark code executed from

SRAM; flash powered down

[2][4][6]

[3][4][6]

CCLK = 12 MHz

CCLK = 48 MHz

-

1.2

3.0

4.5

5.5

11.0

-

mA

CCLK = 84 MHz

CCLK = 100 MHz

CCLK = 150 MHz

I_DD

supply current

CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock

flash access time.

[2][4][6]

[3][4][6]

-

1.5

3.6

-

mA

CCLK = 48 MHz; 3 system clock

flash access time.

[3][4][6]

CCLK = 84 MHz; 6 system clock

flash access time.

-

5.4

-

mA

CCLK = 100 MHz; 7 system clock

flash access time.

6.6

CCLK = 150 MHz; 7 system clock

flash access time.

14.0

I_DD

supply current

Calculating Fibonacci numbers

executed from flash;

[2][4][5]

[3][4][5]

CCLK = 12 MHz

CCLK = 84 MHz

CCLK = 96 MHz

-

1.5

6.2

7.2

-

mA

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Table 11. Static characteristics: Power consumption in active and sleep modes

T_amb= 40 C to +105 C, unless otherwise specified.1.62 V  V_DD 3.6 V.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

ARM Cortex-M4 in active mode; ARM Cortex-M0+ in sleep mode

I_DD

supply current

CoreMark code executed from

SRAM; flash powered down

[2][4][6]

[3][4][6]

CCLK = 12 MHz

CCLK = 48 MHz

-

1.5

4.8

7.9

9.9

15.0

-

mA

CCLK = 84 MHz

CCLK = 100 MHz

CCLK = 150 MHz

I_DD

supply current

CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock

flash access time.

[2][4][6]

[3][4][6]

-

1.9

5.7

-

mA

CCLK = 48 MHz; 3 system clock

flash access time.

[3][4][6]

CCLK = 84 MHz; 6 system clock

flash access time.

-

8.8

-

mA

CCLK = 100 MHz; 7 system clock

flash access time.

10.7

17.0

CCLK = 150 MHz; 7 system clock

flash access time.

I_DD

supply current

Calculating Fibonacci numbers

executed from SRAM;

[2][4][5]

[3][4][5]

CCLK = 12 MHz

CCLK = 84 MHz

CCLK = 96 MHz

-

1.7

8.0

9.4

-

mA

I_DD

Calculating Fibonacci numbers

executed from flash;

[2][4][5]

[3][4][5]

CCLK = 12 MHz

CCLK = 84 MHz

CCLK = 96 MHz

-

1.7

8.0

9.4

-

mA

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Table 11. Static characteristics: Power consumption in active and sleep modes

T_amb= 40 C to +105 C, unless otherwise specified.1.62 V  V_DD 3.6 V.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

ARM Cortex-M4 in sleep mode; ARM Cortex-M0+ in sleep mode

[2][4][7]

[3][4][7]

I_DD

supply current

CCLK = 12 MHz

CCLK = 100 MHz

-

990

4.0

-

A

mA

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.

[2] Clock source 12 MHz IRC. PLL disabled.

[3] Clock source 12 MHz IRC. PLL enabled.

[4] Characterized through bench measurements using typical samples.

[5] Compiler settings: Keil μVision v.5.10, optimization level 0, optimized for time off.

[6] Prefetch disabled in FLASHCFG register. System clock flash access time set by power API. SRAM0 powered, SRAM1 and SRAM2

powered down.Compiler settings: Keil μVision v.5.12, optimization level 0, optimized for time off.

[7] First 8 kB in SRAM0 powered; Flash, SRAM1, and SRAM2 are powered down; all peripheral clocks disabled. Compiler settings: Keil

μVision v.5.12, optimization level 0, optimized for time off.

aaa-015966

170

μ/MHz

M4F Fllash

140

110

80

M4F SSRRAM

M0+ FFllash

M0+ SRAM

50

12

24

36

48

60

72

84

96

108

Frequency (MHz)

Conditions: V_DD= 3.3 V; T_amb= 25 °C; active mode; all peripherals disabled; BOD disabled;

Prefetch disabled in FLASHCFG register. System clock flash access time set by power API.

SRAM0 powered, SRAM1 and SRAM2 powered down. Measured with Keil uVision 5.12.

Optimization level 0, optimized for time off.

12 MHz: IRC enabled; PLL disabled. 24 MHz - 100 MHz: IRC enabled; PLL enabled.

Fig 9. CoreMark power consumption: typical A/MHz for M4 and M0+ cores

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Table 12. Static characteristics: Power consumption in deep sleep, power down, and deep power-down modes

T_amb= 40 C to +105 C, 1.62 V  V_DD 2.0 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1][2]Max^[3]

Unit

[2]

I_DD

supply current

Deep sleep mode; all SRAM

on:

T_amb= 25 C

T_amb= 105 C

-

235

-

380

1.9

A

mA

[2]

Power down mode;

first 8 kB in SRAM0

powered:

T_amb= 25 C

-

4

8

A

T_amb= 105 C

-

110

SRAM0 (64 kB) powered

-

6.7

7.8

-

SRAM0 (64 kB), SRAM1

(32 kB) powered

SRAM0 (64 kB), SRAM1

(32 kB), SRAM2 (8 kB)

powered

-

8.2

-

A

[2]

Deep power-down mode;

RTC oscillator input

grounded (RTC oscillator

disabled)

T_amb= 25 C

T_amb= 105 C

160

-

340

14

-

nA

A

nA

RTC oscillator running with

external crystal

-

240

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples. V_DD= 1.62 V

[3] Guaranteed by characterization, not tested in production. V_DD= 2.0 V

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Table 13. Static characteristics: Power consumption in deep sleep, power down, and deep power-down modes

T_amb= 40 C to +105 C, 2.7 V . V_DD 3.6 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1][2]Max^[3]

Unit

[2]

I_DD

supply current

Deep sleep mode; all SRAM

on:

-

T_amb= 25 C

T_amb= 105 C

306

-

480

2.3

A

-

mA

[2]

Power down mode;

first 8 kB in SRAM0

powered:

T_amb= 25 C

-

5

10

115

-

A

T_amb= 105 C

-

SRAM0 (64 kB) powered

7.3

8.6

SRAM0 (64 kB), SRAM1

(32 kB) powered

-

SRAM0 (64 kB), SRAM1

(32 kB), SRAM2 (8 kB)

powered

-

9

-

A

[2]

Deep power-down mode;

RTC oscillator input

grounded (RTC oscillator

disabled)

T_amb= 25 C

T_amb= 105 C

-

200

-

570

20

-

nA

A

nA

RTC oscillator running with

external crystal

280

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples. V_DD= 3.3 V

[3] Tested in production, V_DD= 3.6 V

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DDDꢀꢁꢂꢃꢄꢅꢁ

ꢆꢂꢂ

,

''

ꢉ$ꢊ

ꢌꢋꢇ9

ꢌꢋꢌ9

ꢃꢋꢆ9

ꢃꢋꢇꢄ9

ꢇꢂꢂ

ꢁꢂꢂ

ꢄꢂꢂ

ꢂ

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

7HPSHUDWXUHꢈꢉ&ꢊ

Conditions: BOD disabled; All SRAM blocks enabled.

Fig 10. Deep sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

DDDꢀꢁꢂꢃꢄꢅꢂ

ꢁꢂ

,

''

ꢉ$ꢊ

ꢌꢋꢇ9

ꢌꢋꢌ9

ꢃꢋꢆ9

ꢃꢋꢇꢄ9

ꢌꢂ

ꢄꢂ

ꢃꢂ

ꢂ

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

7HPSHUDWXUHꢈꢉ&ꢊ

Conditions: BOD disabled; all SRAM disabled except first 8 kB in SRAM0.

Fig 11. Power down mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

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DDDꢀꢁꢂꢃꢄꢅꢄ

ꢆ

ꢇ

ꢁ

ꢄ

ꢂ

,

''

ꢉ$ꢊ

ꢌꢋꢇ9

ꢌꢋꢌ9

ꢃꢋꢆ9

ꢃꢋꢇꢄ9

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

7HPSHUDWXUHꢈꢉ&ꢊ

RTC disabled (RTC oscillator input grounded)

Fig 12. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

Table 14. Typical peripheral power consumption^[1][2][3]

V_DD= 3.3 V; T_amb= 25 °C

Peripheral

IRC

I_DDin uA

262

WDT OSC

Flash

2.0

200.0

2.0

BOD

CLKOUT

37

[1] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using PDRUNCFG register. All other blocks are disabled

and no code accessing the peripheral is executed.

[2] The supply currents are shown for system clock frequencies of 12 MHz.

[3] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

Table 15. Typical AHB/APB peripheral power consumption^[3][4][5]

V_DD= 3.3 V; T = 25 °C

Peripheral

I_DDin A

I_DDin A/MHz

AHB peripheral

CPU: 12 MHz, sync APB

bus: 12 MHz

CPU: 96MHz, sync APB bus:

96 MHz

[1]

GPIO0

-

0.50

0.42

5.0

0.7

GPIO1

0.52

6.86

0.50

0.20

2.92

7.07

DMA

CRC

0.42

0.17

2.25

5.08

MAILBOX

ADC0

SCTimer/PWM

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Table 15. Typical AHB/APB peripheral power consumption^[3][4][5]

V_DD= 3.3 V; T = 25 °C

Peripheral

I_DDin A

I_DDin A/MHz

FIFO

-

3.17

4.49

Sync APB

peripheral

CPU: 12 MHz, sync APB

bus: 12 MHz

CPU: 96MHz, sync APB bus:

96 MHz

[1]

INPUTMUX

IOCON

PINT

-

0.83

1.25

0.83

0.50

0.17

0.50

0.08

0.50

0.17

0.58

0.42

0.50

0.96

1.55

1.05

0.61

0.28

0.65

0.09

0.71

0.11

0.67

0.42

0.57

GINT

WWDT

MRT

RTC

RIT

UTICK

Timer2

Timer3

Timer4

Async APB

peripheral

CPU: 12 MHz, Async APB CPU: 96MHz, Async APB

bus: 12 MHz

bus: 12 MHz^[2]

USART0

USART1

USART2

USART3

I2C0

-

0.67

0.11

0.75

0.07

0.67

0.11

0.75

0.07

0.92

0.10

I2C1

0.83

0.26

I2C2

0.83

0.25

SPIO0

SPIO1

CTimer0

CTimer1

0.92

0.21

0.83

0.25

0.58

0.18

0.42

0.14

Fractional Rate

Generator

4.17

0.73

[1] Turn off the peripheral when the configuration is done.

[2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a

higher frequency.

[3] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and

PDRUNCFG register. All other blocks are disabled and no code accessing the peripheral is executed.

[4] The supply currents are shown for system clock frequencies of 12 MHz and 96 MHz.

[5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

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10.4 Pin characteristics

Table 16. Static characteristics: pin characteristics

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

RESET pin

Conditions

Min

Typ^[1]Max

Unit

V_IH

V_IL

HIGH-level input voltage

0.8  V_DD

0.5

-

5.0

V

LOW-level input voltage

hysteresis voltage

0.3  V_DD

[9]

V_hys

0.05  V_DD

-

Standard I/O pins

Input characteristics

I_IL

I_IH

V_I

LOW-level input current

V_I= 0 V; on-chip pull-up resistor

disabled

-

3.0

180

nA

HIGH-level input current V_I= V_DD; V_DD= 3.6 V; for RESETN

HIGH-level input current V_I= V_DD; on-chip pull-down resistor

disabled

[3]

input voltage

pin configured to provide a digital

function;

V_DD 1.8 V

0

-

5.0

3.6

5.0

+0.4

+0.8

-

V

V_DD= 0 V

0

V_IH

V_IL

HIGH-level input voltage 1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

1.5

2.0

LOW-level input voltage 1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

0.5

0.1  V_DD

[9]

V_hys

hysteresis voltage

Output characteristics

V_O

I_OZ

output voltage

output active

0

-

V_DD

180

V

OFF-state output current V_O= 0 V; V_O= V_DD; on-chip

pull-up/pull-down resistors disabled

3

nA

V_OH

V_OL

I_OH

HIGH-level output voltage I_OH= 4 mA; 1.62 V  V_DD< 2.7 V

I_OH= 6 mA; 2.7 V  V_DD 3.6 V

V_DD 0.4

-

V

V_DD 0.4

LOW-level output voltage I_OL= 4 mA; 1.62 V  V_DD< 2.7 V

I_OL= 6 mA; 2.7 V  V_DD3.6 V

-

0.4

-

V

-

V

HIGH-level output current V_OH= V_DD 0.4 V;

1.62 V  V_DD< 2.7 V

4.0

mA

V_OH= V_DD 0.4 V;

2.7 V  V_DD 3.6 V

6.0

-

mA

I_OL

LOW-level output current V_OL= 0.4 V; 1.62 V  V_DD< 2.7 V

V_OL= 0.4 V; 2.7 V  V_DD 3.6 V

4.0

6.0

-

mA

-

[2][4]

I_OHS

HIGH-level short-circuit

output current

1.62 V  V_DD< 2.7 V

35

drive HIGH; connected to

ground;

2.7 V  V_DD 3.6 V

-

87

mA

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Table 16. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

I_OLSLOW-level short-circuit

Conditions

Min

Typ^[1]Max

Unit

[2][4]

1.62 V  V_DD< 2.7 V

-

30

mA

output current

drive LOW; connected to

V_DD

2.7 V  V_DD 3.6 V

-

77

mA

Weak input pull-up/pull-down characteristics

I_pd

pull-down current

V_I= V_DD

25

80

25

6

80

A

[2]

V_I= 5 V

100

80

30

I_pu

pull-up current

V_I= 0 V

[2][7]

V_DD< V_I< 5 V

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Table 16. Static characteristics: pin characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter

Open-drain I²C pins

Conditions

Min

Typ^[1]Max

Unit

V_IH

HIGH-level input voltage

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

1.62 V  V_DD< 2.7 V

2.7 V  V_DD 3.6 V

0.7  V_DD

-

V

0.7  V_DD

-

V

V_IL

LOW-level input voltage

0

-

0.3  V_DD

V

0

-

0.3  V_DD

V

V_hys

I_LI

hysteresis voltage

0.1  V_DD

-

V

[5]

input leakage current

V_I= V_DD

V_I= 5 V

-

2.5

5.5

-

3.5

10

-

A

mA

-

I_OL

LOW-level output

current

V_OL= 0.4 V; pin configured for

standard mode or fast mode

4.0

V_OL= 0.4V; pin configured for

Fast-mode Plus

20

-

mA

Pin capacitance

C_io

input/output capacitance I²C-bus pins

[8]

[6]

-

6.0

2.0

7.0

pF

pins with digital functions only

Pins with digital and analog

functions

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.

[2] Based on characterization. Not tested in production.

[3] With respect to ground.

[4] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[5] To V_SS

.

[6] The values specified are simulated and absolute values, including package/bondwire capacitance.

[7] The weak pull-up resistor is connected to the V_DDrail and pulls up the I/O pin to the V_DDlevel.

[8] The value specified is a simulated value, excluding package/bondwire capacitance.

[9] Guaranteed by design, not tested in production.

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V

DD

I

OL

pd

+

-

pin PIO0_n

A

I

OH

Ipu

-

+

A

aaa-010819

Fig 13. Pin input/output current measurement

10.4.1 Electrical pin characteristics

DDDꢀꢁꢂꢃꢆꢁꢇ

DDDꢀꢁꢂꢃꢆꢂꢁ

ꢇꢂ

ꢅꢂ

ꢁꢂ

ꢌꢂ

ꢄꢂ

ꢃꢂ

ꢂ

ꢇꢂ

ꢀꢁꢂ&

,

2/

ꢉP$ꢊ

2/

ꢄꢅ&

ꢉP$ꢊ

ꢍꢂ&

ꢃꢂꢅ&

ꢀꢁꢂ&

ꢄꢅ&

ꢁꢅ

ꢌꢂ

ꢃꢅ

ꢂ

ꢍꢂ&

ꢃꢂꢅ&

ꢂ

ꢂꢋꢃ

ꢂꢋꢄ

ꢂꢋꢌ

ꢂꢋꢁ

ꢂꢋꢅ

2/

ꢂꢋꢇ

ꢂ

ꢂꢋꢃ

ꢂꢋꢄ

ꢂꢋꢌ

ꢂꢋꢁ

ꢂꢋꢅ

ꢂꢋꢇ

9

ꢈꢉ9ꢊ

9

ꢈꢉ9ꢊ

2/

Conditions: V_DD= 1.8 V; on pins PIO0_23 to PIO0_28.

Conditions: V_DD= 3.3 V; on pins PIO0_23 to PIO0_28.

Fig 14. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

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DDDꢀꢁꢂꢃꢆꢂꢂ

DDDꢀꢁꢂꢃꢆꢂꢄ

ꢃꢄ

ꢃꢅ

ꢃꢄ

ꢍ

ꢀꢁꢂ&

ꢄꢅ&

,

2/

ꢉP$ꢊ

2/

ꢉP$ꢊ

ꢍꢂ&

ꢃꢂ

ꢆ

ꢃꢂꢅ&

ꢀꢁꢂ&

ꢍꢂ&

ꢄꢅ&

ꢃꢂꢅ&

ꢇ

ꢁ

ꢌ

ꢄ

ꢂ

ꢂꢋꢃ

ꢂꢋꢄ

ꢂꢋꢌ

ꢂꢋꢁ

ꢂꢋꢅ

ꢂꢋꢇ

ꢂ

ꢂꢋꢃ

ꢂꢋꢄ

ꢂꢋꢌ

ꢂꢋꢁ

ꢂꢋꢅ

ꢂꢋꢇ

9

ꢈꢉ9ꢊ

9

ꢈꢉ9ꢊ

2/

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 15. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

DDDꢀꢁꢂꢃꢆꢂꢆ

DDDꢀꢁꢂꢃꢆꢂꢈ

ꢃꢋꢆ

2+

ꢌꢋꢅ

9

2+

ꢉ9ꢊ

9

ꢉ9ꢊ

ꢃꢋꢎ

ꢃꢋꢇ

ꢃꢋꢅ

ꢃꢋꢁ

ꢃꢋꢌ

ꢃꢋꢄ

ꢌꢋꢄ

ꢄꢋꢍ

ꢄꢋꢇ

ꢄꢋꢌ

ꢄ

ꢀꢁꢂ&

ꢄꢅ&

ꢀꢁꢂ&

ꢄꢅ&

ꢍꢂ&

ꢃꢂꢅ&

ꢂ

ꢄꢋꢁ

ꢁꢋꢆ

ꢎꢋꢄ

ꢍꢋꢇ

ꢈꢉP$ꢊ

ꢃꢄ

ꢂ

ꢎ

ꢃꢁ

ꢄꢃ

ꢄꢆ

ꢈꢉP$ꢊ

ꢌꢅ

,

2+

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 16. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

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DDDꢀꢁꢂꢃꢆꢂꢉ

DDDꢀꢁꢂꢃꢆꢂꢊ

ꢁꢂ

ꢅꢂ

ꢌꢂ

ꢃꢂ

,

SX

ꢉ$ꢊ

SX

ꢉ$ꢊ

ꢄꢂ

ꢂ

ꢀꢃꢂ

ꢀꢌꢂ

ꢀꢅꢂ

ꢀꢎꢂ

ꢀꢁꢂ&

ꢄꢅ&

ꢀꢁꢂ&

ꢄꢅ&

ꢍꢂ&

ꢀꢄꢂ

ꢀꢁꢂ

ꢃꢂꢅ&

ꢂꢋꢂ

ꢂꢋꢅ

ꢃꢋꢂ

ꢃꢋꢅ

ꢄꢋꢂ

ꢄꢋꢅ

ꢌꢋꢂ

9 ꢈꢉ9ꢊ

ꢌꢋꢅ

ꢂꢋꢂ

ꢃꢋꢂ

ꢄꢋꢂ

ꢌꢋꢂ

ꢁꢋꢂ

9 ꢈꢉ9ꢊ

ꢅꢋꢂ

,

Conditions: V_DD= 1.8 V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 17. Typical pull-up current I_PUversus input voltage V_I

DDDꢀꢁꢂꢃꢆꢂꢃ

DDDꢀꢁꢂꢃꢆꢂꢅ

ꢎꢂ

ꢃꢂꢂ

,

SG

ꢉ$ꢊ

ꢅꢇ

ꢁꢄ

ꢄꢆ

ꢃꢁ

ꢂ

ꢆꢂ

ꢇꢂ

ꢁꢂ

ꢄꢂ

ꢂ

ꢄꢅ&

ꢃꢂꢅ&

ꢍꢂ&

ꢀꢁꢂ&

ꢍꢂ&

ꢄꢅ&

ꢃꢂꢅ&

ꢀꢁꢂ&

ꢂꢋꢂ

ꢂꢋꢎ

ꢃꢋꢁ

ꢄꢋꢃ

ꢄꢋꢆ

9 ꢈꢉ9ꢊ

ꢌꢋꢅ

ꢂ

ꢃ

ꢄ

ꢌ

ꢁ

ꢅ

9 ꢈꢉ9ꢊ

,

Conditions: V_DD= 1.8V; on standard port pins.

Conditions: V_DD= 3.3 V; on standard port pins.

Fig 18. Typical pull-down current I_PDversus input voltage V_I

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11. Dynamic characteristics

11.1 Power-up ramp conditions

Table 17. Power-up characteristics

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V

Symbol Parameter

Conditions

Min

0

Typ

Max

500

-

Unit

ms

s

[1][3]

[1][2]

[3]

t_r

rise time

at t = t₁: 0 < V_I 200 mV

-

t_wait

V_I

wait time

12

0

input voltage

at t = t₁on pin V_DD

200

mV

[1] See Figure 19.

[2] Based on simulation. The wait time specifies the time the power supply must be at levels below 200 mV

before ramping up.

[3] Based on characterization, not tested in production.

t

r

V

DD

200 mV

0

t

wait

t = t

1

aaa-017426

Condition: 0 < V_I 200 mV at start of power-up (t = t₁)

Fig 19. Power-up ramp

11.2 Flash memory

Table 18. Flash characteristics

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V

Symbol Parameter

N_enduendurance

Conditions

Min

Typ

Max

Unit

[1]

sector erase/program

10000

1000

-

cycles

page erase/program; page

in a sector

t_ret

retention time powered

unpowered

10

-

years

ms

-

t_er

erase time

page, sector, or multiple

consecutive sectors

100

[2]

t_prog

programming

time

-

1

-

ms

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[1] Number of erase/program cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash.

11.3 I/O pins

Table 19. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +85 C; 1.62 V  V_DD 3.6 V

Symbol Parameter Conditions

Min Typ Max Unit

Standard I/O pins - normal drive strength

[2][3]

t_r

t_f

t_r

t_f

rise time

fall time

rise time

fall time

pin configured as output; SLEW = 1 (fast

mode);

2.7 V  V_DD 3.6 V

1.0

1.6

-

2.5

3.8

ns

1.62 V  V_DD 1.98 V

pin configured as output; SLEW = 1 (fast

mode);

2.7 V  V_DD 3.6 V

1.62 V V_DD 1.98 V

0.9

1.7

-

2.5

4.1

ns

pin configured as output; SLEW = 0

(standard mode);

2.7 V  V_DD 3.6 V

1.9

2.9

-

4.3

7.8

ns

1.62 V  V_DD 1.98 V

pin configured as output; SLEW = 0

(standard mode);

2.7 V  V_DD 3.6 V

1.62 V  V_DD 1.98 V

pin configured as input

1.9

2.7

0.3

0.2

-

4.0

6.7

1.3

1.2

ns

[4]

t_r

t_f

rise time

fall time

[1] Simulated data.

[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between

80 % and 20 % of the full output signal level.

[3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC5410x user manual.

[4] C_L= 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

11.4 Wake-up process

Table 20. Dynamic characteristic: Typical wake-up times from low power modes

V_DD= 3.3 V;T_amb= 25 C; using IRC as the system clock.

Symbol Parameter Conditions

Min Typ^[1]

Max Unit

[2][3]

[2]

t_wake

wake-up

time

from sleep mode

-

1.6

18

-

s

from deep sleep mode with full

SRAM retention:

to code executing in flash or

SRAM

[2]

[4]

from power down mode

180

200

-

s

from deep power-down mode;

RTC disabled; using RESET pin.

-

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

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[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler. Measurements are based on using the power library provided in the LPC5410x LPCOpen

software platform version v.3.04.

[3] IRC enabled, all peripherals off.

[4] RTC disabled. Wake-up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between when the RESET pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

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11.5 System PLL

Table 21. PLL lock times and current

T_amb= 40 C to +105 C, unless otherwise specified. V_DD= 1.62 V to 3.6 V

Symbol Parameter Conditions Min Typ Max

Unit

PLL configuration: input frequency 12 MHz; output frequency 75 MHz

[2]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

PLL set-up procedure followed

when locked

400

550

s

[1][3]

-

A

PLL configuration: input frequency 12 MHz; output frequency 100 MHz

[2]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

PLL set-up procedure followed

when locked

-

400

750

s

[1][3]

A

PLL configuration: input frequency 32.768 kHz; output frequency 75 MHz

[1]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

-

6250

450

s

[1][3]

when locked

-

A

PLL configuration: input frequency 32.768 kHz; output frequency 100 MHz

[1]

t_lock(PLL)

I_DD(PLL)

PLL lock time

PLL current

-

6250

560

s

[1][3]

when locked

A

[1] Data based on characterization results, not tested in production.

[2] PLL set-up requires high-speed start-up and transition to normal mode. Lock times are only valid when

high-speed start-up settings are applied followed by normal mode settings. The procedure for setting up the

PLL is described in the LPC5410x user manual.

[3] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

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Table 22. Dynamic characteristics of the PLL^[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Reference clock input

F_in

input frequency

-

32.768 kHz

-

25 MHz

-

Clock output

[3]

[4]

f_o

output frequency

output duty cycle

CCO frequency

for PLL clkout output

1.2

46

-

150

54

MHz

%

d_o

f_CCO

150

MHz

Lock detector output

_lock(PFD)PFD lock criterion

1

2

4

ns

Dynamic parameters at f_out= f_CCO= 100 MHz; standard bandwidth settings

[5][6]

J_rms-interval

J_pp-period

RMS interval jitter

f_ref= 10 MHz

-

15

40

30

80

ps

[5][6]

peak-to-peak, period jitter f_ref= 10 MHz

[1] Data based on characterization results, not tested in production.

[2] Output jitter depends on the frequency of input jitter and is equal to or less than the input jitter.

[3] Excluding under- and overshoot which may occur when the PLL is not in lock.

[4] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[5] Actual jitter dependent on amplitude and spectrum of substrate noise.

[6] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.6 IRC

Table 23. Dynamic characteristic: IRC oscillator

1.62 V  V_DD 3.6 V.

Symbol Parameter

Conditions

Min

Typ^[1]Max

12 12 +1 %

12 +3 %

Unit

MHz

[2]

[3]

f_osc(RC)

internal RC oscillator frequency

T_amb= 25 C

12 1 %

40 C  T_amb +105 C

0 C  T_amb +85 C

12 3.5 % 12

12 2 % 12

12 +2.5 % MHz

[1] Typical ratings are not guaranteed. The value listed is at room temperature (25 C).

[2] Tested in production.

[3] Guaranteed by characterization, not tested in production.

11.7 RTC oscillator

See Section 13.5 for connecting the RTC oscillator to a crystal or an external clock

source.

Table 24. Dynamic characteristic: RTC oscillator

1.62 V  V_DD 3.6 V^[1]

Symbol Parameter

f_iinput frequency

Conditions

Min

Typ^[1]

Max

Unit

-

32.768

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

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11.8 Watchdog oscillator

Table 25. Dynamic characteristics: Watchdog oscillator

Symbol

Parameter

Min

Typ^[1]

Max

Unit

[2]

f_osc(int)

internal watchdog oscillator

frequency

-

500

-

kHz

D_clkout

J_PP-CC

t_start

clkout duty cycle

peak-peak period jitter

start-up time

48

-

52

20

-

%

[3][4]

[4]

1

4

ns

s

-

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Guaranteed by design. Not tested in production samples.

11.9 I²C-bus

Table 26. Dynamic characteristic: I²C-bus pins^[1]

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V.^[2]

Symbol Parameter

f_SCLSCL clock frequency

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

Standard-mode

Fast-mode

0

-

Fast-mode Plus

of both SDA and SCL signals

Standard-mode

Fast-mode

[4][5][6][7]

t_f

fall time

300

20 + 0.1  C_b

300

ns

s

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

data hold time

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

Fast-mode Plus

Standard-mode

Fast-mode

[3][4][8]

[9][10]

t_HD;DAT

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up time

250

100

50

Fast-mode Plus

[1] Guaranteed by design. Not tested in production.

[2] Parameters are valid over operating temperature range unless otherwise specified. See the I²C-bus specification UM10204 for details.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

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[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t_VD;DATor

t_VD;ACKby a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement t_SU;DAT= 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

t

SU;DAT

f

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 20. I²C-bus pins clock timing

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11.10 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 21 Mbit/s.

Table 27. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; C_L= 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50 %

level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Max

Unit

SPI master 1.62V  VDD  2.0 V

t_DS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

ns

0

-

0

-

t_DH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

14

12

9

-

t_v(Q)

data output valid time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

0

7

2

0

CCLK = 96 MHz

0

SPI slave 1.62V  VDD  2.0 V

t_DS

data set-up time

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

22

4

-

ns

-

4

-

t_DH

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

0

-

0

-

t_v(Q)

data output valid time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

46

30

70

37

36

CCLK = 96 MHz

SPI master 2.7 V  VDD  3.6 V

t_DS

data set-up time

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

ns

0

-

0

-

t_DH

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

10

8

-

7

-

t_v(Q)

data output valid time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

0

6

1

0

CCLK = 96 MHz

0

SPI slave 2.7V  VDD  3.6 V

t_DS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

21

4

-

ns

3

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Table 27. SPI dynamic characteristics^[1]

T_amb= 40 C to 105 C; C_L= 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50 %

level of the rising or falling edge.

Symbol Parameter

Conditions

Min

0

Max

-

Unit

ns

t_DH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

ns

0

-

ns

t_v(Q)

data output valid time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

36

21

20

61

22

21

ns

CCLK = 96 MHz

ns

[1] Based on characterization; not tested in production.

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

MISO (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MOSI (CPHA = 1)

MISO (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

IDLE

DATA VALID (LSB)

DATA VALID

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014969

Fig 21. SPI master timing

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

MOSI (CPHA = 0)

t

v(Q)

IDLE

DATA VALID (MSB)

DATA VALID

DATA VALID (MSB)

DATA VALID (LSB)

t

DH

DS

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

MISO (CPHA = 1)

MOSI (CPHA = 1)

t

v(Q)

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

IDLE

t

DH

DS

DATA VALID (MSB)

DATA VALID (LSB)

DATA VALID

aaa-014970

Fig 22. SPI slave timing

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11.11 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master and slave synchronous modes is 24 Mbit/s.

Table 28. USART dynamic characteristics^[1]

T_amb= 40 C to 105 C; 1.62 V  V_DD 3.6 V; C_L= 30 pF balanced loading on all pins; SLEW =

standard mode. Parameters sampled at the 50% level of the falling or rising edge.

Symbol Parameter

Conditions

Min

Max

Unit

USART master (in synchronous mode) 1.62V  VDD  2.0 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

65

-

ns

CCLK = 48 MHz to 60 MHz 35

-

CCLK = 96 MHz

34

0

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

8

2

0

USART slave (in synchronous mode) 1.62V  VDD  2.0 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

18

5

-

ns

-

CCLK = 96 MHz

4

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

50

65

40

36

CCLK = 48 MHz to 60 MHz 35

CCLK = 96 MHz

USART master (in synchronous mode) 2.7V  VDD  3.6V

30

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

61

-

ns

CCLK = 48 MHz to 60 MHz 22

-

CCLK = 96 MHz

21

0

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

7

2

1

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Table 28. USART dynamic characteristics^[1]

T_amb= 40 C to 105 C; 1.62 V  V_DD 3.6 V; C_L= 30 pF balanced loading on all pins; SLEW =

standard mode. Parameters sampled at the 50% level of the falling or rising edge.

Symbol Parameter

Conditions

Min

Max

Unit

USART slave (in synchronous mode) 2.7V  VDD  3.6 V

t_su(D)

t_h(D)

t_v(Q)

data input set-up time CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

21

5

-

ns

-

CCLK = 96 MHz

4

-

data input hold time

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

0

-

0

-

0

-

CCLK = 1 MHz to 12 MHz

37

62

25

21

CCLK = 48 MHz to 60 MHz 22

CCLK = 96 MHz 19

[1] Based on characterization; not tested in production.

T

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

t

vQ)

v(Q)

START

BIT0

BIT1

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-015074

Fig 23. USART timing

11.12 SCTimer/PWM output timing

Table 29. SCTimer/PWM output dynamic characteristics

T_amb= 40 C to 105 C; 1.62 V  V_DD 3.6 V C_L= 30 pF. Simulated skew (over process, voltage,

and temperature) of any two SCT fixed-pin output signals; sampled at 10 % and 90 % of the signal

level; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_sk(o)

output skew time

-

3.0

ns

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12. Analog characteristics

12.1 BOD

Table 30. BOD static characteristics

T_amb= 25 C; based on characterization; not tested in production.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 0

assertion

-

2.05

2.20

-

V

de-assertion

V_th

threshold voltage interrupt level 1

assertion

-

2.45

2.60

-

V

de-assertion

reset level 1

assertion

-

1.85

2.00

-

V

de-assertion

V_th

threshold voltage interrupt level 2

assertion

-

2.75

2.90

-

V

de-assertion

reset level 2

assertion

-

2.00

2.15

-

V

de-assertion

V_th

threshold voltage interrupt level 3

assertion

-

3.05

3.20

-

V

de-assertion

reset level 3

assertion

-

2.30

2.45

-

V

de-assertion

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12.2 12-bit ADC characteristics

Table 31. 12-bit ADC static characteristics

T_amb= 40 C to +105 C; 1.62 V  V_DD 3.6 V; VREFP = V_DDA; V_SSA= VREFN = GND. ADC

calibrated at T_amb= 25C.

Symbol Parameter

Conditions

Min

Typ^[2]Max

Unit

[3]

[4]

V_IA

C_ia

analog input

voltage

0

-

V_DDA

V

analog input

capacitance

5

-

pF

f_clk(ADC)ADC clock

frequency

80

5.0

-

MHz

f_s

sampling

frequency

-

Msamples/s

[1][5]

[1][6]

E_D

differential

linearity error

V_DDA= VREFP = 1.62 V

V_DDA= VREFP = 3.6 V

V_DDA= VREFP = 1.62 V

V_DDA= VREFP = 3.6 V

calibration enabled

3

2

5

2

5.6

3

-

LSB

mV

E_L(adj)

integral

non-linearity

-

[1][7]

[1][8]

E_O

offset error

-

V_err(FS)full-scale error V_DDA= VREFP = 1.62 V

-

LSB

k

voltage

V_DDA= VREFP = 3.6 V

-

[9][10]

Z_i

input

f_s= 5.0 Msamples/s

17.0

-

impedance

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.

[4] C_iarepresents the external capacitance on the analog input channel for sampling speeds of

5.0 Msamples/s. No parasitic capacitances included.

[5] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 24.

[6] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 24.

[7] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 24.

[8] The full-scale error voltage or gain error (E_G) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 24.

[9] T_amb= 25 C; maximum sampling frequency f_s= 5.0 Msamples/s and analog input capacitance C_ia= 5 pF.

[10] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including

C_iaand C_io: Z_i 1 / (f_s C_i). See Table 16 for C_io. See Figure 25.

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offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - VREFN

1 LSB =

4096

aaa-016908

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 24. 12-bit ADC characteristics

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Table 32. ADC sampling times^[1]

-40 C  T_amb 85 C; 1.62 V  V_DDA 3.6 V; 1.62 V  V_DD 3.6 V

Symbol Parameter Conditions

Min

Typ Max Unit

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

20

23

26

31

47

75

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

15

18

20

24

38

62

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

12

13

15

19

30

48

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

9

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

10

11

13

22

36

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

43

46

50

56

74

105

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

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Table 32. ADC sampling times^[1]…continued

-40 C  T_amb 85 C; 1.62 V  V_DDA 3.6 V; 1.62 V  V_DD 3.6 V

Symbol Parameter Conditions

Min

Typ Max Unit

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

35

38

40

46

61

86

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

27

29

32

36

48

69

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit

[3]

t_s

sampling time

Z_o< 0.05 kΩ

20

22

23

26

36

51

-

ns

0.05 kΩ  Z_o< 0.1 kΩ

0.1 kΩ  Z_o< 0.2 kΩ

0.2 kΩ  Z_o< 0.5 kΩ

0.5 kΩ  Z_o< 1 kΩ

1 kΩ  Z_o< 5 kΩ

[1] Characterized through simulation. Not tested in production.

[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output

impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum

sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.

[3] Z_o= analog source output impedance.

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12.2.1 ADC input impedance

Figure 25 shows the ADC input impedance. In this figure:

• ADCx represents slow ADC input channels 6 to 11.

• ADCy represents fast ADC input channels 0 to 5.

• R₁and R_sware the switch-on resistance on the ADC input channel.

• If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through

R_swto the sampling capacitor (C_ia).

• If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through

R₁+ R_swto the sampling capacitor (C_ia).

• Typical values, R₁= 487 , R_sw= 278 

• See Table 16 for C_io.

• See Table 31 for C_ia.

ADC

R

1

ADCx

ADCy

C

io

C

ia

R

sw

DAC

C

io

aaa-017600

Fig 25. ADC input impedance

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13. Application information

13.1 Start-up behavior

Figure 26 shows the start-up timing after reset. The IRC 12 MHz oscillator provides the

default clock at Reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

IRC

starts

IRC status

internal reset

V

DD

valid threshold

= 1.62 V

t

a

μs

t μs

b

GND

boot time

supply ramp-up

time

user code

t

c

μs

processor status

boot code

execution

finishes;

user code starts

aaa-024042

Fig 26. Start-up timing

Table 33. Typical start-up timing parameters

Parameter Description

Value

 20 s

151 s

68 s

t_a

t_b

t_c

IRC start time

Internal reset de-asserted

Boot time

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13.2 Standard I/O pin configuration

Figure 27 shows the possible pin modes for standard I/O pins:

• Digital output driver: with configurable open-drain output.

• Digital input: pull-up resistor (PMOS device) enabled/disabled.

• Digital input: pull-down resistor (NMOS device) enabled/disabled.

• Digital input: repeater mode enabled/disabled.

• Digital input: programmable input digital filter and input inverter.

• Analog input: selected through IOCON register.

The default configuration for standard I/O pins is input with pull-up resistor enabled. The

weak MOS devices provide a drive capability equivalent to pull-up and pull-down

resistors.

V

DD

open-drain enable

output enable

data output

strong

pull-up

ESD

pin configured

as digital output

strong

pull-down

ESD

V

DD

weak

pull-up

pull-up enable

weak

pull-down

repeater

mode enable

pin configured

as digital input

pull-down enable

digital

input

glitch filter

enable

input invert

enable

filter

enable

analog input

pin configured

as analog input

analog

input

aaa-017273

Fig 27. Standard I/O pin configuration

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13.3 Connecting power, clocks, and debug functions

3.3 V

SWD connector

Note 4

3.3 V

~10 kΩ - 100 kΩ

(6)

SWDIO/PIO0_17

1

2

3.3 V

~10 kΩ - 100 kΩ

SWCLK/PIO0_16

(6)

3

5

7

9

4

6

n.c.

8

RTCXIN

RESET

Note 1

DGND

C3

C4

10

RTCXOUT

V

SS

Note 2

3.3 V

DGND

V

DD

(2 to 4 pins)

DGND

0.1 ꢀF

0.01 ꢀF

V

SSA

LPC5410x

DGND

Note 3

3.3 V

AGND

V

DDA

PIO0_31

0.1 ꢀF

10 ꢀF

ISP select pins

Note 5

ADC0

DGND

Note 3

3.3 V

VREFP

0.1 ꢀF

10 ꢀF

0.1 ꢀF

VREFN

AGND

DGND

aaa-017247

(1) See Section 13.5 “RTC oscillator” for the values of C3 and C4.

(2) Position the decoupling capacitors of 0.1 ꢀF and 0.01 ꢀF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(3) Position the decoupling capacitors of 0.1 ꢀF as close as possible to the VREFN and V_DDApins. The 10 ꢀF bypass capacitor

filters the power line. Tie V_DDAand VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 3.

(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by

default.

Fig 28. Power, clock, and debug connections

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13.4 I/O power consumption

I/O pins can contribute to the overall static and dynamic power consumption of the part.

If pins are configured as digital inputs with the pull-up resistor enabled, a static current can

flow depending on the voltage level at the pin. This current can be calculated using the

parameters I_puand I_pdgiven in Table 16.

If pins are configured as digital outputs, the static current is derived from parameters IOH

and IOL shown in Table 16, and any external load connected to the pin.

When an I/O pin switches in an application, it contributes to the dynamic power

consumption because the VDD supply provides the current to charge and discharge all

internal and external capacitive loads connected to the pin.

The contribution from the I/O switching current I_swcan be calculated as follows for any

given switching frequency f_swif the external capacitive load (C_ext) is known (see Table 16

for the internal I/O capacitance):

I_sw= V_DDx f_swx (C_io+ C_ext

)

13.5 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances C_X1and C_X2

need to be connected externally on the RTCXIN and RTCXOUT pins. See Figure 29.

An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended

amplitude of the clock signal is V_i(RMS)= 100 mV to 200 mV with a coupling capacitance of

5 pF to 10 pF.

LPC5410x

L

RTCXIN

RTCXOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-016002

Fig 29. RTC oscillator components

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (C_L), series resistance (R_S), and drive level (D_L) are important

parameters to consider while choosing the crystal. After selecting the proper crystal, the

external load capacitor C_X1and C_X2values can also be generally determined by the

following expression:

C_X1= C_X2= 2C_L (C_Pad+ C_Parasitic

)

Where:

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C_L- Crystal load capacitance

C_Pad- Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).

C_Parasitic– Parasitic or stray capacitance of external circuit.

Although C_Parasiticcan be ignored in general, the actual board layout and placement of

external components influences the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, output the RTC Clock to one of

the GPIOs and optimize the values of external load capacitors for minimum frequency

deviation.

Table 34. Recommended values for the RTC external 32.768 kHz oscillator C_L, R_S, D_L, and

C

_X1/C_X2components

Maximum crystal

series resistance R_Sdrive level D_L

< 70 k 0.5 W

Crystal load

capacitance C_L

Maximum crystal

External load

capacitors C_X1/C_X2

12.5 pF

22 pF, 22 pF

Remark: The crystals with lower CL (< 12.5 pF) values are not recommended.

13.5.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible

(within 20 mm) to the oscillator input and output pins of the chip.

• The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

• Loops must be made as small as possible to minimize the noise coupled in through

the PCB and to keep the parasitics as small as possible.

• Lay out the ground (GND) pattern under crystal unit.

• Do not lay out other signal lines under crystal unit for multi-layered PCB.

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14. Package outline

WLCSP49: wafer level chip-scale package; 49 bumps; 3.29 x 3.29 x 0.54 mm (backside coating included)

LPC5410

D

B

A

E

ball A1

index area

A

2

A

1

detail X

e

C

1

Ø v

Ø w

C

A

B

y

e

b

G

e

F

E

D

C

B

A

e

2

1

2

3

4

5

6

7

X

ball A1

index area

0

3 mm

scale

w

Dimensions (mm are the original dimensions)

Unit

A

1

A

2

b

D

E

e

2

v

y

1

max 0.58 0.23 0.37 0.29 3.318 3.318

mm nom 0.54 0.20 0.34 0.26 3.288 3.288 0.4 2.4 2.4 0.05 0.015 0.03

min 0.50 0.17 0.31 0.23 3.258 3.258

Note

Backside coating 40 μm

wlcsp49_lpc5410_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

- - -

JEITA

13-09-16

14-11-03

LPC5410

Fig 30. WLCSP49 Package outline (Applies to LPC5410x Device Revision 1B)

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Fig 31. WLCSP49 Package outline (Applies to LPC5410x Device Revision 1C)

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LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 32. LQFP64 Package outline

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15. Soldering

Fig 33. WLCSP49 Soldering footprint (1 of 3)

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Fig 34. WLCSP49 Soldering footprint (2 of 3)

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Fig 35. WLCSP49 Soldering footprint (3 of 3)

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Footprint information for reflow soldering of LQFP64 package

SOT314-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550

sot314-2_fr

Fig 36. LQFP64 Soldering footprint

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16. Abbreviations

Table 35. Abbreviations

Acronym

AHB

APB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

Application Programming Interface

Direct Memory Access

API

DMA

GPIO

IRC

General Purpose Input/Output

Internal RC

LSB

Least Significant Bit

MCU

PLL

MicroController Unit

Phase-Locked Loop

SPI

Serial Peripheral Interface

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

TTL

USART

17. References

[1] LPC5410x User manual UM10850:

http://www.nxp.com/documents/user_manual/UM10850.pdf

[2] LPC5410x Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC5410X.pdf

[3] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

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18. Revision history

Table 36. Revision history

Document ID

LPC5410x v.2.11

Modification:

Release date Data sheet status

20190815 Product data sheet

• Maximum CPU frequency changed from 100 MHz to 150 MHz.

Change notice Supersedes

-

LPC5410x v2.10

LPC5410x v.2.10

20190205

Product data sheet

201901014F01 LPC5410x v2.9

May 22, 2014

Modification:

• Added package drawing for LPC5410x Device Revision 1C.

• Updated soldering diagram to new soldering diagram format.

LPC5410x v.2.9

Modification:

20180126

Product data sheet

-

LPC5410x v2.8

• Updated a feature in Section 7.16.2 “SPI serial I/O controller” Maximum supported bit

rate for SPI master mode is 48 Mbit/s. Was 71 Mbit/s.

• Updated Section 11.10 “SPI interfaces”: the maximum supported bit rate for SPI master

mode is 48 Mbit/s. Was 71 Mbit/s.

LPC5410x v.2.8

Modification:

20171219

• Updated Table 20 “Dynamic characteristic: Typical wake-up times from low power modes”.

20170426 Product data sheet LPC5410x v2.6

• Updated Figure 28 “Power, clock, and debug connections”.

20160926 Product data sheet LPC5410x v2.5

Product data sheet

-

LPC5410x v2.7

LPC5410x v.2.7

Modification:

-

LPC5410x v.2.6

Modification:

-

• Updated Table 13 “Static characteristics: Power consumption in deep sleep, power down,

and deep power-down modes”: in deep power-down mode, the RTC oscillator running with

external crystal typical value is 240 nA at: T_amb= 40 C to +105 C, 1.62 V  V_DD 2.0 V;

unless otherwise specified.

LPC5410x v.2.5

Modification:

20160913

Product data sheet

-

LPC5410x v2.4

• Updated Table 10 “CoreMark score”: changed CoreMark scoreCoreMark code executed

from flash; CCLK = 84 MHz; 4 system clock flash access time; CCLK = 100 MHz; 5 system

clock flash access time to CCLK = 84 MHz; 5 system clock flash access time; CCLK = 100

MHz; 6 system clock flash access time

LPC5410x v.2.4

20160711

Product data sheet

-

LPC5410x v2.3

LPC5410x

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Table 36. Revision history …continued

Document ID

Release date Data sheet status

Change notice Supersedes

Modification:

• Updated Table 27 “SPI dynamic characteristics[1]”:

–

Min values of SPI master 1.62V  VDD  2.0 V, t_DSand t_v(Q)

Min values of SPI slave 1.62V  VDD  2.0 V, t_DSHand t_v(Q)

Min values of SPI master 2.7 V  VDD  3.6 V, t_DS

Min values of SPI slave 2.7 V  VDD  3.6 V, t_DH

.

• Updated Table 28 “USART dynamic characteristics[1]”:

–

Min values of USART master (in synchronous mode) 1.62V  VDD  2.0 V, t_{h(D) and tv(Q).}

Min values of USART slave (in synchronous mode) 1.62V  VDD  2.0 V, t_h(D).

Min values of USART master (in synchronous mode) 2.7V  VDD  3.6V, t_h(D).

Min values of USART slave (in synchronous mode) 2.7V  VDD  3.6 V, t_h(D).

• Updated features of Section 7.16.2 “SPI serial I/O controller”: Maximum supported bit rate

for SPI master mode is 71 Mbit/s, and the maximum supported bit rate for SPI slave mode is

21 Mbit/s.

• Updated features of Section 7.16.1 “USART”: Maximum supported bit rate of 24 Mbit/s for

USART master and slave synchronous modes.

• Updated Table 22 “Dynamic characteristics of the PLL[1]”:

–

f_refchanged to F_in; reference frequency to input frequency.

–

removed f_refjitter

.

• Updated the description for Section 11.10 “SPI interfaces”.

20160524 Product data sheet LPC5410x v2.2

LPC5410x v2.3

Modification:

-

• Updated Table 18 “Flash characteristics”: For N_enduconditions, removed the row with page

erase/program; page in small sector 10000 and removed the word large so that it is "page

erase/program;page in a sector".

• Updated Section 7.16.1 “USART” features: changed maximum bit rates to 6.25 Mbit/s in

asynchronous mode.

LPC5410x v2.2

20151222

Product data sheet

201512007I

LPC5410x v2.1

LPC5410x

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Table 36. Revision history …continued

Document ID

Release date Data sheet status

Change notice Supersedes

Modification:

• Updated Section 11.6 “IRC”, Table 23 “Dynamic characteristic: IRC oscillator” for IRC

frequency tolerance improvement over temperature.

• Added boot code version and device revision. See Section 4 “Marking”.

• Added the abbreviation ISP to the Remark: This pin is also used to force In-System

Programming mode (ISP) after device reset. See the LPC5410x User Manual (Boot Process

chapter) for details to PIO0_31. See Table 4 “Pin description”.

• Removed 164 uA PLL spec in peripheral power consumption table, Table 15 “Typical

AHB/APB peripheral power consumption[3][4][5]”.

• Added Table 21 “PLL lock times and current”.

• Updated Figure 10 “Deep sleep mode: Typical supply current IDD versus temperature for

different supply voltages VDD”, Figure 11 “Power down mode: Typical supply current IDD

versus temperature for different supply voltages VDD”, and Figure 12 “Deep power-down

mode: Typical supply current IDD versus temperature for different supply voltages VDD”.

• Updated Table 12 “Static characteristics: Power consumption in deep sleep, power down,

and deep power-down modes”: added max values to Deep sleep mode at 25 °C and 105 °C,

Power down mode at 25 °C and 105 °C. Changed typ and max values for Deep power-down

mode RTC oscillator input grounded (RTC oscillator disabled) at 25 °C; was: typ = 84 nA,

max = 240 nA; now: typ = 160 nA, max = 340 nA.

• Updated Table 13 “Static characteristics: Power consumption in deep sleep, power down,

and deep power-down modes”: added max values to Deep sleep mode at 25 °C and 105 °C,

Power down mode at 25 °C and 105 °C. Changed typ and max values for Deep power-down

mode RTC oscillator input grounded (RTC oscillator disabled) at 25 °C; was: typ = 135 nA,

max = 470 nA; now: typ = 200 nA, max = 570 nA.

• Updated Table 7 “Limiting values”; VESD, electrostatic discharge voltage, human body

model; all pins value to 4000 V; was 5000 V.

• Updated Table 31 “12-bit ADC static characteristics”: ED differential linearity error, VDDA =

VREFP = 1.62 V and 3.6 V, typ value 3 and 2; EL_(adj)integral non-linearity, VDDA =

VREFP = 1.62 V, typ value 5; V_err(FS)full-scale error voltage VDDA = VREFP = 1.62 V and

3.6 V, typ value to 3

LPC5410x v2.1

Modification:

20150701

Product data sheet

-

LPC5410x v2.0

• Updated Figure 3 “LPC5410x Block diagram”. Corrected Sync APB bridge to Async APB

bridge.

• Updated external clock input for clock frequencies of up to 24 MHz to 25 MHz in Section 2

“Features and benefits”.

• Updated Table 12 “Static characteristics: Power consumption in deep sleep, power down,

and deep power-down modes”. Fixed the unit of the max value from nA to A for IDD in deep

power-down mode; RTC oscillator input grounded (RTC oscillator disabled), T_amb= 105 C.

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Table 36. Revision history …continued

Document ID

LPC5410x v2.0

Modification:

Release date Data sheet status

20150417 Product data sheet

Change notice Supersedes

-

LPC5410x v1.1

• Updated the ADC conversion rate from 4.8 Msamples/s to 5.0 Msamples/s.

• Added Section 7.14 “Pin interrupt/pattern engine”.

• Added Section 7.18.6 “Repetitive Interrupt Timer (RIT)”.

• Updated Table 12 “Static characteristics: Power consumption in deep sleep, power down,

and deep power-down modes” on page 44.

• Updated Table 15 “Static characteristics: pin characteristics” on page 49:

–

T_amb= 40 C to +105 C, unless otherwise specified. 1.62 V  V_DD 3.6 V.

–

updated min and max values.

• Added Section 11.1 “Power-up ramp conditions”.

• Added Section 11.9 “SPI interfaces”, Section 11.10 “USART interface”, and Section 11.11

“SCTimer/PWM output timing”.

• Updated Section 11.5 “IRC”:

–

added temperature conditions: T_{amb =}25 C, 40 C  T_amb +105 C

–

updated min and max values.

• Added Table 14 “Typical peripheral power consumption”.

• Added Table 28 “12-bit ADC static characteristics”:

–

T_amb= 40 C to +105 C.

–

Values for E_D, E_L(adj), E_O, and V_err(FS)

.

• Added Section 12.2.1 “ADC input impedance”

• Updated Figure 26 “Standard I/O pin configuration” on page 71

• Minor updates to Section 13.3 “I/O power consumption”.

LPC5410x v1.1

Modification:

20141117

• Minor editorial update in Section 1.

20141106 Product data sheet

Product data sheet

-

LPC5410x v1.0

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

LPC5410x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.11 — 19 September 2019

92 of 95

LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC5410x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.11 — 19 September 2019

93 of 95

LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.18.1

General-purpose 32-bit timers/external event

counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.2

3

3.1

4

State Configurable Timer/PWM

(SCTimer/PWM) . . . . . . . . . . . . . . . . . . . . . . 28

7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.18.3 Windowed WatchDog Timer (WWDT) . . . . . . 29

7.18.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.18.4 RTC timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.18.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.18.5 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 30

7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.18.6 Repetitive Interrupt Timer (RIT) . . . . . . . . . . . 30

7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.18.7 Micro-tick timer (UTICK). . . . . . . . . . . . . . . . . 31

7.18.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5

6

6.1

6.2

6.2.1

6.2.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

Termination of unused pins. . . . . . . . . . . . . . . 19

Pin states in different power modes . . . . . . . . 19

7

Functional description . . . . . . . . . . . . . . . . . . 20

Architectural overview. . . . . . . . . . . . . . . . . . . 20

ARM Cortex-M4 processor . . . . . . . . . . . . . . . 20

ARM Cortex-M4 integrated Floating Point Unit

(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Memory Protection Unit (MPU). . . . . . . . . . . . 20

Nested Vectored Interrupt Controller (NVIC) for

Cortex-M4. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21

ARM Cortex-M0+ co-processor . . . . . . . . . . . 21

Nested Vectored Interrupt Controller (NVIC) for

Cortex-M0+. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 22

System Tick timer (SysTick) . . . . . . . . . . . . . . 22

On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 22

On-chip flash. . . . . . . . . . . . . . . . . . . . . . . . . . 22

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 22

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 23

General Purpose I/O (GPIO) . . . . . . . . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pin interrupt/pattern engine . . . . . . . . . . . . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 25

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1

7.2

7.3

7.19

7.19.1

7.20

12-bit Analog-to-Digital Converter (ADC). . . . 31

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

System control . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock sources. . . . . . . . . . . . . . . . . . . . . . . . . 32

7.4

7.5

7.20.1

7.20.1.1 Internal RC oscillator (IRC) . . . . . . . . . . . . . . 32

7.20.1.2 Watchdog oscillator (WDOSC). . . . . . . . . . . . 32

7.20.1.3 Clock input pin (CLKIN) . . . . . . . . . . . . . . . . . 32

7.20.2

7.20.3

7.20.4

7.20.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.20.4.2 Deep sleep mode. . . . . . . . . . . . . . . . . . . . . . 34

7.20.4.3 Power down mode . . . . . . . . . . . . . . . . . . . . . 34

7.20.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 35

7.20.5

7.20.6

7.21

7.5.1

7.5.2

7.6

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock Generation . . . . . . . . . . . . . . . . . . . . . 33

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7

7.7.1

7.7.2

7.8

7.9

7.10

7.11

7.12

7.13

7.13.1

7.14

7.14.1

7.15

7.15.1

Brownout detection . . . . . . . . . . . . . . . . . . . . 35

Safety. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Code security (Code Read Protection - CRP) 35

Emulation and debugging . . . . . . . . . . . . . . . 36

7.22

8

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal characteristics . . . . . . . . . . . . . . . . . 39

10

Static characteristics . . . . . . . . . . . . . . . . . . . 40

General operating conditions . . . . . . . . . . . . . 40

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 40

Power consumption . . . . . . . . . . . . . . . . . . . . 42

Pin characteristics . . . . . . . . . . . . . . . . . . . . . 50

Electrical pin characteristics. . . . . . . . . . . . . . 53

10.1

10.2

10.3

10.4

10.4.1

7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.16

7.16.1

7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.16.2 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 26

7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.17

7.17.1

7.18

Digital serial peripherals . . . . . . . . . . . . . . . . . 25

USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11

Dynamic characteristics. . . . . . . . . . . . . . . . . 56

Power-up ramp conditions . . . . . . . . . . . . . . . 56

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 56

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 57

11.1

11.2

11.3

11.4

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 27

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 27

continued >>

LPC5410x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.11 — 19 September 2019

94 of 95

LPC5410x

NXP Semiconductors

32-bit ARM Cortex-M4/M0+ microcontroller

11.5

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 59

11.6

11.7

11.8

11.9

11.10

11.11

11.12

IRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 60

Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 61

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 63

USART interface. . . . . . . . . . . . . . . . . . . . . . . 66

SCTimer/PWM output timing . . . . . . . . . . . . . 67

12

Analog characteristics . . . . . . . . . . . . . . . . . . 68

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12-bit ADC characteristics . . . . . . . . . . . . . . . 69

ADC input impedance. . . . . . . . . . . . . . . . . . . 73

12.1

12.2

12.2.1

13

Application information. . . . . . . . . . . . . . . . . . 74

Start-up behavior . . . . . . . . . . . . . . . . . . . . . . 74

Standard I/O pin configuration . . . . . . . . . . . . 75

Connecting power, clocks, and debug

13.1

13.2

13.3

functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

I/O power consumption. . . . . . . . . . . . . . . . . . 77

RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 77

RTC Printed Circuit Board (PCB) design

13.4

13.5

13.5.1

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14

15

16

17

18

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 79

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 83

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 84

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 87

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 87

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 88

19.1

19.2

19.3

19.4

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 88

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 September 2019

Document identifier: LPC5410x


型号：	LPC54102J256BD64
厂家：	NXP
描述：	32-bit ARM Cortex-M4/M0 MCU; 104 kB SRAM; 512 kB flash, 3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC 时钟静态存储器外围集成电路
文件：	总95页 (文件大小：2142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LPC54102J256BD64 [NXP]

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