M68HC16ZEC20D [NXP]
20.97 MHz Electrical Characteristics;
| 型号： | M68HC16ZEC20D |
| 厂家： | 
NXP |
| 描述： | 20.97 MHz Electrical Characteristics |
| 文件： | 总28页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Order this document by: M68HC16ZEC20/D
M68HC16 Z Series
Technical Supplement
20.97 MHz Electrical Characteristics
Devices in the M68HC16 Modular Microcontroller Family are built up from a selection of standard
functional modules. Microcontrollers in the M68HC16 Z Series contain the same central processing
unit (CPU16) and system integration module (SIM), and thus have similar electrical characteristics.
M68HC16 devices that operate at clock frequencies of 20.97 MHz are now available. This publica-
tion contains a new electrical characteristics appendix that supplements the MC68HC16Z1 User's
Manual (MC68HC16Z1UM/AD) and the MC68HC16Z2 User's Manual (MC68HC16Z2UM/AD).
The supplement contains the following updated specifications:
Table
Page
Maximum Ratings ......................................................................................................2
Typical Ratings ..........................................................................................................3
Thermal Characteristics .............................................................................................3
Clock Control Timing .................................................................................................4
DC Characteristics .....................................................................................................5
AC Timing ..................................................................................................................8
Background Debugging Mode Timing .....................................................................19
ECLK Bus Timing ....................................................................................................20
QSPI Timing ............................................................................................................21
ADC Maximum Ratings ...........................................................................................24
ADC DC Electrical Characteristics (Operating) .......................................................25
ADC AC Characteristics (Operating) .......................................................................26
ADC Conversion Characteristics (Operating) ..........................................................26
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Table A–1 Maximum Ratings
Num
Rating
1,2,3
Symbol
Value
Unit
V
1
– 0.3 to + 6.5
V
Supply Voltage
1,2,3,4,5,7
DD
VIN
ID
2
3
– 0.3 to + 6.5
25
V
Input Voltage
Instantaneous Maximum Current
mA
1,3,5,6
Single Pin Limit (all pins)
Operating Maximum Current
Digital Input Disruptive Current
3,5,6,7,8
IiD
4
– 500 to 500
µA
V
– 0.3 V
NEGCLMAP
POSCLAMP
V
V
+ 0.3
DD
Operating Temperature Range
C Suffix
TL to TH
– 40 to 85
TA
5
6
°C
°C
Tstg
Storage Temperature Range
– 55 to 150
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltag-
es or currents in excess of recommended values affects device reliability. Device mod-
ules may not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high
static voltages or electrical fields, take normal precautions to avoid exposure to voltag-
es higher than maximum-rated voltages.
3. This parameter is periodically sampled rather than 100% tested.
4. All pins except TSC.
5. Input must be current limited to the value specified. To determine the value of the re-
quired current-limiting resistor, calculate resistance values for positive and negative
clamp voltages, then use the larger of the two values.
6. Power supply must maintain regulation within operating V
neous and operating maximum current.
range during instanta-
DD
7. All functional non-supply pins are internally clamped to V . All functional pins except
SS
EXTAL and XFC are internally clamped to V
.
DD
8. Total input current for all digital input-only and all digital input/output pins must not ex-
ceed 10 mA. Exceeding this limit can cause disruption of normal operation.
M68HC16ZEC20/D
2
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Table A–2 Typical Ratings
Num
Rating
Symbol
Value
Unit
V
1
Supply Voltage
Operating Temperature
Supply Current
5.0
V
DD
T
A
2
3
4
25
°C
V
DD
RUN
mA
µA
mA
113
125
3.75
I
DD
LPSTOP, VCO off
LPSTOP, External clock, max f
sys
V
Clock Synthesizer Operating Voltage
Supply Current
5.0
V
DDSYN
V
DDSYN
VCO on, maximum f
1.0
5.0
100
50
mA
mA
µA
sys
I
5
External Clock, maximum f
sys
DDSYN
LPSTOP, VCO off
µA
V
powered down
DD
RAM Standby Current
Normal RAM operation
Standby operation
I
6
7
7.0
40
µA
µA
SB
P
D
Power Dissipation
570
mW
Table A–3 Thermal Characteristics
Num
Characteristic
Symbol
Value
Unit
1
Thermal Resistance
Θ
1
Plastic 132-Pin Surface Mount
Plastic 144-pin Surface Mount
38
49
°C/W
JA
NOTES:
1. The average chip-junction temperature (T ) in C can be obtained from (1):
J
TJ = TA + (PD ΘJA
)
where:
T = Ambient Temperature, °C
A
Θ
= Package Thermal Resistance, Junction-to-Ambient, °C/W
JA
P = P
+ P
I/O
D
INT
P
P
= I × V , Watts — Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
INT DD
I/O
DD
For most applications P < P
and can be neglected. An approximate relationship between
I/O
INT
P
and T (if P is neglected) is (2):
D
J
I/O
PD = K + (TJ + 273°C)
Solving equations (1) and (2) for K gives (3):
2
K = P + (TA + 273°C) + ΘJA × PD
D
Where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T
D
A
D
J
can be obtained by solving equations (1) and (2) iteratively for any value of T .
A
M68HC16ZEC20/D
3
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Table A–4 Clock Control Timing
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Minimum
Maximum
Unit
1
PLL Reference Frequency Range
MC68HC16Z1
f
1
20
50
kHz
ref
3.2
5.2
MHz
MC68HC16Z2
dc
2
20.97
20.97
20.97
20.97
System Frequency
4 (f
)
ref
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
External Clock Operation
f
2
MHz
sys
4 (f ) /128
ref
dc
—
—
1,3,5,6,7
t
3
4
20
ms
PLL Lock Time
lpll
4
f
2 (f max)
sys
VCO Frequency
MHz
VCO
Limp Mode Clock Frequency
SYNCR X bit = 0
f
f
max /2
max
5
6
—
—
MHz
%
sys
limp
f
SYNCR X bit = 1
sys
1,5,6,7,8
CLKOUT Jitter
J
–1.0
–0.5
1.0
0.5
Short term (5 µs interval)
Long term (500 µs interval)
clk
NOTES:
1. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the
base configuration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can
be ordered with either reference as a mask option.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V
measured from the time V
is applied, and that the crystal oscillator is stable. Lock time is
DDSYN
and V
are valid until RESET is released. This specification
DD
DDSYN
also applies to the period required for PLL lock after changing the W and Y frequency control
bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period re-
quired for the clock to lock after LPSTOP.
4. Internal VCO frequency (f
) is determined by SYNCR W and Y bit values.
VCO
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
= f
= f
÷ 4.
÷ 2.
sys
VCO
sys
VCO
X must equal one when operating at maximum specified f
.
sys
5. This parameter is periodically sampled rather than 100% tested.
6. Assumes that a low-leakage external filter network is used to condition clock synthesizer input
voltage. Total external resistance from the XFC pin due to external leakage must be greater than
15 M Ω to guarantee this specification. Filter network geometry can vary depending upon operat-
ing environment.
7. Proper layout procedures must be followed to achieve specifications.
8. Jitter is the average deviation from the programmed frequency measured over the specified in-
terval at maximum f . Measurements are made with the device powered by filtered supplies
sys
and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V
DDSYN
and V
SS
and variation in crystal oscillator frequency increase the J percentage for a given in-
clk
terval. When jitter is a critical constraint on control system operation, this parameter should be
measured during functional testing of the final system.
M68HC16ZEC20/D
4
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Table A–5 DC Characteristics
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min Max
0.7 (V ) V + 0.3
DD
Unit
V
V
1
2
3
Input High Voltage
Input Low Voltage
IH
DD
V
V
– 0.3 0.2 (V
)
V
IL
SS
0.5
DD
1,2
V
—
V
Input Hysteresis
HYS
3,16
Input Leakage Current
= V or V
I
4
5
6
7
8
–2.5
2.5
2.5
—
µA
µA
V
in
V
in
DD SS
4,16
High Impedance (Off-State) Leakage Current
= V or V
I
–2.5
OZ
V
in
DD SS
5,6,16
CMOS Output High Voltage
= –10.0 µA
V
V
V
–0.2
DD
OH
I
OH
CMOS Output Low Voltage
= 10.0 µA
7,16
V
—
0.2
—
V
OL
I
OL
Output High Voltage
= –0.8 mA
6,7,16
V
–0.8
DD
V
OH
I
OH
7,16
Output Low Voltage
I
I
I
= 1.6 mA
= 5.3 mA
= 12 mA
OL
OL
OL
—
—
—
0.4
0.4
0.4
V
9
V
OL
V
1.6 (V )
DD
10 Three State Control Input High Voltage
8,9
9.1
V
IHTSC
Data Bus Mode Select Pull-up Current
V
= V
IMSP
—
–15
–120
—
µA
11
in
in
IL
V
= V
IH
10,11,12
Supply Current
MC68HC16Z1V
DD
—
—
—
140
350
5
mA
µA
mA
Run, crystal reference
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
I
12
DD
sys
10,11,12
MC68HC16Z2 V
DD
Supply Current
—
—
—
140
2
10
mA
mA
mA
Run, crystal reference
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
I
12A
DD
sys
V
13 Clock Synthesizer Operating Voltage
4.75
5.25
V
DDSYN
M68HC16ZEC20/D
5
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Table A–5 DC Characteristics (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max
Unit
6,12
MC68HC16Z1 V
DDSYN
Supply Current
VCO on, crystal reference, maximum f
—
—
—
—
2
6
150
100
mA
mA
µA
sys
I
14
External Clock, maximum f
sys
DDSYN
LPSTOP, crystal reference, VCO off (STSIM = 0)
powered down
µA
V
DD
6,12
Supply Current
MC68HC16Z2 V
DDSYN
VCO on, crystal reference, maximum f
—
—
—
—
2.5
8.75
2
mA
mA
mA
mA
sys
I
14A
External Clock, maximum f
sys
DDSYN
LPSTOP, crystal reference, VCO off (STSIM = 0)
powered down
2
V
DD
RAM Standby Voltage
Specified V applied
13
V
15
16
0.0
3.0
5.25
5.25
V
DD
SB
V
= V
SS
DD
11
MC68HC16Z1RAM Standby Current
Normal RAM operation
14
V
> V – 0.5 V
DD
DD
SB
—
—
—
10
3
50
µA
mA
µA
I
SB
Transient condition
V
V
− 0.5 V ≥ V
≥ V + 0.5 V
SB
SS
13
Standby operation
V
< V + 0.5 V
SS
DD
11
MC68HC16Z2RAM Standby Current
14
Normal RAM operation
V
> V – 0.5 V
SB
≥ V + 0.5 V
SS
DD
DD
—
—
—
10
3
100
µA
mA
µA
I
16A
SB
Transient condition
− 0.5 V ≥ V
SB
13
Standby operation
V
< V + 0.5 V
SS
DD
15
P
D
17 MC68HC16Z1 Power Dissipation
—
—
766
831
mW
mV
15
MC68HC16Z2 Power Dissipation
P
D
17A
M68HC16ZEC20/D
6
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Table A–5 DC Characteristics (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max
Unit
3,16
Input Capacitance
All input-only pins except ADC pins
All input/output pins
C
in
18
—
—
10
20
pF
16
Load Capacitance
—
—
—
—
90
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
C
L
19
100
130
200
pF
Group 4 I/O Pins
NOTES:
1. Applies to:
Port ADA[7:0] — AN[7:0]
Port E[7:4] — SIZ[1:0], AS, DS
Port F[7:0] — IRQ[7:1], MODCLK
Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC
EXTAL (when PLL enabled)
2. This parameter is periodically sampled rather than 100% tested.
3. Applies to all input-only pins except ADC pins.
4. Applies to all input/output and output pins
5. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS[7:0] (TXD,
PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
6. Applies to Group 1, 2, 4 input/output and all output pins
7. Applies to Group 1, 2, 3, 4 input/output pins, BG/CS, CLKOUT, CSBOOT, FREEZE/QUOT, and IPIPE0
8. Applies to DATA[15:0]
9. Use of an active pulldown device is recommended.
10. Total operating current is the sum of the appropriate I , I
, and I
SB
values, plus I values in-
. I
DD DDSYN
DDA DD
clude supply currents for device modules powered by V
and V
pins.
DDE DDI
11. Current measured at maximum system clock frequency, all modules active.
12. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the base configu-
ration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can be ordered with either
crystal reference as a mask option.
13. The SRAM module will not switch into standby mode as long as V
0.5 volts. The SRAM array cannot be accessed while the module is in standby mode.
does not exceed V
by more than
SB
DD
14. When V is more than 0.3 V greater than V , current flows between the V
and V
pins, which
DD
SB DD STBY
causes standby current to increase toward the maximum transient condition specification. System noise on
the V and V pin can contribute to this condition.
DD STBY
15. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can
be calculated using the expression:
P
= Maximum V
(I
+ I
+ I ) + Maximum V
(I
pins.
)
D
DD DD
DDSYN
SB DDA DDA
I
includes supply currents for all device modules powered by V
and V
DDI
DD
16. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD
DDE
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DS0/IPIPE0, PWMA, PWMB
Input/Output Pins:
Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], DSI/IPIPE1
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] — IRQ[7:1], MODCLK
Port QS[7:3] — TXD, PCS[3:1], PCS0/SS, ADDR23/CS10/ECLK
ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
M68HC16ZEC20/D
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Table A–6 AC Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
Max Unit
2
Frequency of Operation
MC68HC16Z1
4 (f
)
F1
f
20.97 MHz
ref
4 (f )/128 20.97
MC68HC16Z2
ref
t
1
Clock Period
ECLK Period
47.7
381
47.7
18.8
183
23.8
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
t
1A
1B
Ecyc
3
External Clock Input Period
t
Xcyc
t
2, 3 Clock Pulse Width
2A, 3A ECLK Pulse Width
CW
t
ECW
3
External Clock Input High/Low Time
t
2B, 3B
XCHL
t
4, 5 CLKOUT Rise and Fall Time
Crf
t
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
—
8
rf
4
t
4B, 5B External Clock Input Rise and Fall Time
—
5
XCrf
t
6
7
Clock High to ADDR, FC, SIZE Valid
0
23
47
—
23
10
—
23
—
—
—
—
—
47
—
23
23
—
—
23
—
—
—
CHAV
t
Clock High to ADDR, Data, FC, SIZE, High Impedance
Clock High to ADDR, FC, SIZE, Invalid
0
CHAZx
t
8
0
CHAZn
t
9
Clock Low to AS, DS, CS Asserted
0
CLSA
5
t
9A
11
12
13
14
AS to DS or CS Asserted (Read)
-10
10
2
STSA
t
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
AVSA
t
CLSN
t
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
10
80
36
32
32
—
SNAI
t
SWA
t
14A DS, CS Width Asserted (Write)
SWAW
t
14B AS, CS (and DS Read) Width Asserted (Fast Cycle)
6
SWDW
t
15
16
17
18
20
21
22
23
24
25
26
AS, DS, CS Width Negated
SN
t
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
Clock High to R/W High
CHSZ
t
10
0
SNRN
t
CHRH
t
Clock High to R/W Low
0
CHRL
t
R/W High to AS, CS Asserted
10
54
—
RAAA
t
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
RASA
t
CHDO
t
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
10
10
10
DVASN
t
SNDOI
t
DVSA
M68HC16ZEC20/D
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Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
5
Max Unit
t
27
Data In Valid to Clock Low (Data Setup)
—
—
60
—
48
—
72
46
23
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
DICL
t
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
15
0
BELCL
t
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
SNDN
7
t
DS, CS Negated to Data In Invalid (Data In Hold)
0
SNDI
7, 8
t
29A
30
—
10
—
—
—
1
DS, CS Negated to Data In High Impedance
SHDI
7
t
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLDI
7
t
30A
31
CLKOUT Low to Data In High Impedance
CLDH
9
t
DSACK[1:0] Asserted to Data In Valid
DADI
t
33
Clock Low to BG Asserted/Negated
CLBAN
10
t
t
t
t
t
35
BR Asserted to BG Asserted
BRAGA
cyc
cyc
cyc
cyc
ns
t
37
BGACK Asserted to BG Negated
BG Width Negated
1
GAGN
t
39
2
—
—
—
—
GH
t
39A BG Width Asserted
1
GA
t
46
R/W Width Asserted (Write or Read)
115
70
RWA
t
46A R/W Width Asserted (Fast Write or Read Cycle)
ns
RWAS
Asynchronous Input Setup Time
47A
t
5
—
ns
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
t
47B Asynchronous Input Hold Time
11
12
—
0
—
30
—
23
—
23
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AIHT
t
48
53
54
55
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
DABA
t
DOCH
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
—
32
0
CHDH
t
RADC
t
SCLDD
t
10
10
10
10
20
0
SCLDS
t
SCLDH
t
BKST
t
BKPT Input Hold Time
BKHT
t
t
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
MSS
cyc
ns
t
MSH
12
t
t
RESET Assertion Time
4
RSTA
cyc
cyc
13,14
t
t
—
RESET Rise Time
RSTR
M68HC16ZEC20/D
9
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Table A–6 AC Timing (Continued)
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
H
DD
DDSYN
SS
A
L
Num
Characteristic
Symbol
Min
3
Max Unit
15
t
100 CLKOUT High to Phase 1 Asserted
40
40
—
—
—
—
ns
ns
ns
ns
ns
ns
CHP1A
15
CLKOUT High to Phase 2 Asserted
t
101
102
103
104
105
3
CHP2A
15
15
t
10
10
10
10
Phase 1 Valid to AS or DS Asserted
P1VSA
t
Phase 2 Valid to AS or DS Asserted
P2VSN
15
AS or DS Valid to Phase 1 Negated
t
SAP1N
15
AS or DS Negated to Phase 2 Negated
t
SNP2N
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the base con-
figuration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can be ordered with
either crystal reference as a mask option.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The mini-
mum allowable t
between external clock input duty cycle and minimum t
Xcyc
period is reduced when the duty cycle of the external clock varies. The relationship
is expressed:
/ (50% – external clock input duty cycle tolerance).
Xcyc
Minimum t
period = minimum t
Xcyc
XCHL
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low
during reset). Does not pertain to an external reference applied while the PLL is enabled (MODCLK pin
held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of
the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are
not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the
relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and
DS to fall outside the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the nega-
tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated
specification between multiple chip selects does not apply to chip selects being used for synchronous
ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT
on fast cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (t
/ 2) + 25 ns.
cyc
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data
setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ig-
nored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following
clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the
following clock cycle.
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all
cycles of the current operand transfer are complete.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time
(specification 47A).
12. After external RESET negation is detected, a short transition period (approximately 2) t
elapses, then
cyc
the SIM drives RESET low for 512 t
.
cyc
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an exter-
nal reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
16.Address access time = (2.5 + WS) t
Chip select access time = (2 + WS) t
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
– t
– t
– t
– t
cyc
cyc
CHAV
CLSA
DICL
DICL
M68HC16ZEC20/D
10
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1
2
3
4
CLKOUT
5
16 CLKOUT TIM
16 EXT CLK INPUT TIM
16 ECLK OUTPUT TIM
Figure A–1 CLKOUT Output Timing Diagram
1B
2B
3B
4B
EXTAL
5B
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
.
DD
.
PULSE WIDTH SHOWN WITH RESPECT TO 50% V
DD
Figure A–2 External Clock Input Timing Diagram
1A
2A
3A
4A
ECLK
5A
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD.
Figure A–3 ECLK Output Timing Diagram
M68HC16ZEC20/D
11
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S0
S1
S2
S3
S4
S5
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
16
11
AS
DS
CS
13
9
9A
12
20
18
21
R/W
46
DSACK0
47A
31
28
DSACK1
29
DATA[15:0]
27
29A
BERR
HALT
48
27A
BKPT
47A
47B
ASYNCHRONOUS
INPUTS
105
100
101
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
102
16 RD CYC TIM
Figure A–4 Read Cycle Timing Diagram
M68HC16ZEC20/D
12
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S0
S1
S2
S3
S4
S5
CLKOUT
6
8
ADDR[23:20]
FC[2:0]
SIZ[1:0]
11
14
15
AS
DS
13
9
9
12
CS
22
20
14A
17
R/W
46
DSACK0
47A
28
DSACK1
55
25
DATA[15:0]
23
26
54
53
BERR
HALT
48
27A
73
74
BKPT
101
100
102
105
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
16 WR CYC TIM
Figure A–5 Write Cycle Timing Diagram
M68HC16ZEC20/D
13
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S0
S1
S4
S5
S0
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
AS
14B
12
9
DS
CS
20
18
46A
R/W
30
30A
27
DATA[15:0]
29A
73
29
BKPT
74
100
101
IPIPE0
IPIPE1
PHASE 1
102
PHASE 2
105
104
103
16 FAST RD CYC TIM
Figure A–6 Fast Termination Read Cycle Timing Diagram
M68HC16ZEC20/D
14
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S0
S1
S4
S5
S0
CLKOUT
6
8
ADDR[23:0]
FC[1:0]
SIZ[1:0]
14B
AS
DS
9
12
CS
20
46A
R/W
24
18
23
DATA[15:0]
27A
25
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
103
102
104
16 FAST WR CYC TIM
Figure A–7 Fast Termination Write Cycle Timing Diagram
M68HC16ZEC20/D
15
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S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
ADDR[23:0]
DATA[15:0]
7
AS
DS
16
R/W
DSACK0
DSACK1
47A
BR
BG
39A
35
33
33
BGACK
37
100
PHASE 1
102
101
IPIPE0
IPIPE1
PHASE 2
104
103
105
16 BUS ARB TIM
Figure A–8 Bus Arbitration Timing Diagram — Active Bus Case
M68HC16ZEC20/D
16
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A0
A5
A5
A2
A3
A0
CLKOUT
ADDR[23:0]
DATA[15:0]
AS
47A
47A
BR
BG
35
37
47A
33
33
BGACK
16 BUS ARB TIM IDLE
Figure A–9 Bus Arbitration Timing Diagram — Idle Bus Case
S0
S41
S42
S43
S0
S1
S2
CLKOUT
6
8
ADDR[23:0]
R/W
18
20
AS
9
12
15
DS
71
72
70
74
DATA[15:0]
73
BKPT
100
101
PHASE 1
102
IPIPE0
PHASE 2
105
PHASE 1
PHASE 2
IPIPE1
104
103
SHOW CYCLE
START OF EXTERNAL CYCLE
NOTE:
Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion.
16 SHW CYC TIM
Figure A–10 Show Cycle Timing Diagram
M68HC16ZEC20/D
17
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S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
11
11
14
13
AS
DS
15
9
9
9
12
17
17
21
12
CS
20
18
14A
18
46
R/W
46
25
29
55
DATA[15:0]
29A
53
23
27
54
16 CHIP SEL TIM
Figure A–11 Chip-Select Timing Diagram
77
78
RESET
75
DATA[15:0],
MODCLK,
BKPT
76
16 RST/MODE SEL TIM
Figure A–12 Reset and Mode Select Timing Diagram
Table A–7 Background Debugging Mode Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Characteristic
Num
Symbol
Min
Max
Unit
t
B0 DSI Input Setup Time
15
—
ns
DSISU
M68HC16ZEC20/D
18
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Table A–7 Background Debugging Mode Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
)
SS A L H
DD
DDSYN
Characteristic
Num
Symbol
Min
10
15
10
—
Max
—
Unit
ns
t
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
DSIH
t
—
ns
DSCSU
t
—
ns
DSCH
t
25
—
ns
DSOD
t
t
2
DSCCYC
cyc
t
B6 CLKOUT Low to FREEZE Asserted/Negated
B7 CLKOUT High to IPIPE1 High Impedance
B8 CLKOUT High to IPIPE1 Valid
—
50
50
50
—
ns
ns
ns
FRZAN
t
—
IPZ
t
—
IP
t
t
B9 DSCLK Low Time
1
DSCLO
cyc
t
t
B10 IPIPE1 High Impedance to FREEZE Asserted
TBD
TBD
—
IPFA
cyc
t
t
B11 FREEZE Negated to IPIPE[0:1] Active
NOTES:
—
FRIP
cyc
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
CLKOUT
FREEZE
B3
B2
BKPT/DSCLK
B9
B5
B1
B0
IPIPE1/DSI
B4
IPIPE0/DSO
16 BDM SER COM TIM
Figure A–13 BDM Serial Communication Timing Diagram
CLKOUT
FREEZE
B6
B6
B11
B7
B10
IPIPE1/DSI
B8
16 BDM FRZ TIM
Figure A–14 BDM Freeze Assertion Timing Diagram
M68HC16ZEC20/D
19
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Table A–8 ECLK Bus Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
SS A L H
DD
DDSYN
Num
Characteristic
Symbol
Min
—
10
—
10
25
25
5
Max
48
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
E1 ECLK Low to Address Valid
E2 ECLK Low to Address Hold
E3 ECLK Low to CS Valid (CS Delay)
E4 ECLK Low to CS Hold
EAD
tEAH
tECSD
tECSH
tECSN
tEDSR
tEDHR
tEDHZ
tECDH
tECDZ
120
—
E5 CS Negated Width
—
E6 Read Data Setup Time
—
E7 Read Data Hold Time
—
E8 ECLK Low to Data High Impedance
E9 CS Negated to Data Hold (Read)
E10 CS Negated to Data High Impedance
—
0
48
—
t
—
1
cyc
t
tEDDW
tEDHW
tEACC
tEACS
tEAS
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
—
10
2
cyc
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
308
236
1/2
4
E14 Chip-Select Access Time (Read)
t
E15 Address Setup Time
cyc
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
CLKOUT
ECLK
2A
3A
1A
R/W
E1
E2
ADDR[23:0]
E5
E3
E14
E13
E4
CS
E6
E15
E9
DATA[15:0]
READ
E7
WRITE
E8
E11
E10
DATA[15:0]
WRITE
E12
HC16 E CYCLE TIM
Figure A–15 ECLK Timing Diagram
M68HC16ZEC20/D
20
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Table A–9 QSPI Timing
1
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T
, 200 pF load on all QSPI pins)
DD
DDSYN
Function
SS
A
L
H
Num
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
f
1
DC
DC
1/4
1/4
sys
op
f
sys
Cycle Time
Master
Slave
t
t
t
2
3
4
5
4
4
510
—
cyc
cyc
qcyc
Enable Lead Time
Master
Slave
t
t
t
2
2
128
—
cyc
cyc
lead
Enable Lag Time
Master
Slave
t
SCK
—
2
1/2
—
lag
t
cyc
Clock (SCK) High or Low Time
Master
2 t
cyc
2 t
cyc
– 60
– n
t
255 t
cyc
ns
ns
sw
2
Slave
—
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
t
t
6
7
17
13
8192
—
cyc
td
t
cyc
Data Setup Time (Inputs)
Master
Slave
t
30
20
—
—
ns
ns
su
Data Hold Time (Inputs)
Master
Slave
t
8
9
0
20
—
—
ns
ns
hi
t
t
t
Slave Access Time
—
—
1
2
a
cyc
cyc
t
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
dis
t
11
Master
Slave
—
—
50
50
ns
ns
v
Data Hold Time (Outputs)
Master
Slave
t
12
0
0
—
—
ns
ns
ho
Rise Time
Input
Output
t
13
14
—
—
2
30
µs
ns
ri
t
ro
Fall Time
Input
Output
t
—
—
2
30
µs
ns
fi
t
fo
NOTES:
1. All AC timing is shown with respect to 20% V
and 70% V
levels unless otherwise noted.
DD
DD
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
M68HC16ZEC20/D
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3
2
PCS[3:0]
OUTPUT
5
13
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
12
6
4
13
7
MISO
INPUT
MSB IN
DATA
LSB IN
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
DATA
PORT DATA
12
MSB OUT
PD
13
16 QSPI MAST CPHA0
Figure A–16 QSPI Timing — Master, CPHA = 0
3
2
PCS[3:0]
OUTPUT
5
13
12
1
SCK
CPOL=0
OUTPUT
4
1
7
SCK
CPOL=1
OUTPUT
12
4
13
6
MISO
INPUT
DATA
DATA
LSB IN
MSB
MSB
MSB IN
11
10
LSB OUT
MOSI
OUTPUT
MSB OUT
PORT DATA
12
PORT DATA
13
16 QSPI MAST CPHA1
Figure A–17 QSPI Timing — Master, CPHA = 1
M68HC16ZEC20/D
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3
2
SS
INPUT
5
13
12
SCK
CPOL=0
INPUT
4
1
SCK
CPOL=1
INPUT
12
4
13
11
10
11
8
9
MISO
OUTPUT
MSB OUT
DATA
LSB OUT
PD
13
MSB OUT
MSB IN
7
6
MOSI
INPUT
MSB IN
DATA
LSB IN
16 QSPI SLV CPHA0
Figure A–18 QSPI Timing — Slave, CPHA = 0
SS
INPUT
5
1
13
4
12
SCK
CPOL=0
INPUT
4
3
2
SCK
CPOL=1
INPUT
12
13
11
10
9
10
8
SLAVE
LSB OUT
MISO
OUTPUT
PD
MSB OUT
DATA
DATA
PD
12
7
6
MOSI
INPUT
MSB IN
LSB IN
16 QSPI SLV CPHA1
Figure A–19 QSPI Timing — Slave, CPHA = 1
M68HC16ZEC20/D
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Table A–10 ADC Maximum Ratings
Num
Parameter
Symbol
Min
–0.3
–0.3
–0.3
–0.1
–6.5
–6.5
–6.5
–6.5
Max
6.5
6.5
6.5
0.1
6.5
6.5
6.5
6.5
Unit
V
V
1
2
3
4
5
6
7
8
Analog Supply
DDA
V
Internal Digital Supply, with reference to V
V
SSI
DDI
V
, V
Reference Supply, with reference to V
V
SSI
RH RL
V
V
–V
SSA
V
V
V
V
V
Differential Voltage
Differential Voltage
Differential Voltage
V
SS
DD
SSI
–V
DDA
V
DDI
V
–V
RL
V
REF
RH
V
–V
to V
Differential Voltage
Differential Voltage
V
RH
RL
DDA
RH
DDA
SSA
V
–V
NA
to V
V
SSA
RL
1 2 3 4 5 6 7
, , , , , ,
Disruptive Input Current
V
V
–0.3 V
8 V
I
9
–500
500
µA
NEGCLAMP
POSCLAMP
8
1,5,6,
K
K
10
11
2000
500
—
—
—
—
Positive Overvoltage Current Coupling Ratio
P
1,5,6
,8
Negative Overvoltage Current Coupling Ratio
N
3,4,6
Maximum Input Current
V
V
–0.3 V
8 V
I
12
–25
25
mA
NEGCLAMP
POSCLAMP
MA
NOTES:
1. Below disruptive current conditions, a stressed channel will store the maximum conversion value for
analog inputs greater than V and the minimum conversion value for inputs less than V . This as-
RH RL
RL SSA
are not affected by non-disruptive conditions
sumes that V
≤ V
and V ≥ V
due to the presence of the sample amplifier. Other channels
RH
DDA
2. Input signals with large slew rates or high frequency noise components cannot be converted accurate-
ly. These signals also interfere with conversion of other channels.
3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transi-
tions within the limit do not affect device reliability or cause permanent damage.
4. Input must be current limited to the value specified. To determine the value of the required current-lim-
iting resistor, calculate resistance values using positive and negative clamp values, then use the larger
of the calculated values.
5. This parameter is periodically sampled rather than 100% tested.
6. Applies to single pin only.
7. The values of external system components can change the maximum input current value, and affect
operation. A voltage drop may occur across the external source impedances of the adjacent pins, im-
pacting conversions on these adjacent pins. The actual maximum may need to be determined by test-
ing the complete design.
8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an
external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may
occur across the external source impedances of the adjacent pins, impacting conversions on these ad-
jacent pins
M68HC16ZEC20/D
24
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Table A–11 ADC DC Electrical Characteristics (Operating)
(VSS = 0 Vdc, ADCLK = 2.1 MHz, T = T to T )
A
L
H
Num
Parameter
Symbol
Min
Max
5.5
5.5
1.0
1.0
Unit
V
1
V
1
2
3
4
5
6
4.5
4.5
Analog Supply
Internal Digital Supply
DDA
1
V
V
DDI
V
V
V
V
Differential Voltage
Differential Voltage
– 1.0
– 1.0
mV
V
–
–
SS
DD
SSI
SSA
V
V
DDI
DDA
2,3
2,3
V
V
V
/ 2
DDA
V
Reference Voltage Low
RL
SSA
V
V
/ 2
V
DDA
V
Reference Voltage High
RH
DDA
4.5
V
3
V
V
RL
7
8
9
V
REF
Differential Voltage
5.5
V
V
V
V
–
RH
V
2
V
DDA
Input Voltage
INDC
SSA
V
0.7 (V
)
V
+ 0.3
DDA
Input High, Port ADA
IH
DDA
V
V
0.3
0.2 (V
)
10 Input Low, Port ADA
IL
SSA –
DDA
Analog Supply Current
4
I
11
—
—
1.0
mA
Normal Operation
Low-power stop
DDA
200
250
150
10
µA
I
I
12 Reference Supply Current
—
—
—
—
µA
nA
pF
pF
REF
5
13
Input Current, Off Channel
OFF
C
14 Total Input Capacitance, Not Sampling
INN
C
15 Total Input Capacitance, Sampling
NOTES:
15
I
NS
1. Refers to operation over full temperature and frequency range.
2. To obtain full-scale, full-range results, V ≤ V ≤ V ≤ V
≤ V
DDA.
SSA RL RH
INDC
3. Accuracy tested and guaranteed at V
– V = 5.0 V ± 5%.
RH
RL
4. Current measured at maximum system clock frequency with ADC active.
5. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately
one-half for each 10°C decrease from maximum temperature.
M68HC16ZEC20/D
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Table A–12 ADC AC Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA within operating temperature range)
Num
Parameter
ADC Clock Frequency
Symbol
Min
Max
Unit
f
1
0.5
2.1
MHz
ADCLK
1
8-bit Conversion Time
f
= 1.0 MHz
= 2.1 MHz
t
2
15.2
7.6
—
µs
ADCLK
CONV
f
K
ADCL
1
10-bit Conversion Time
f
= 1.0 MHz
= 2.1 MHz
t
3
4
17.1
8.6
—
µs
µs
ADCLK
ADCLK
CONV
f
t
Stop Recovery Time
—
10
SR
NOTES:
1. Conversion accuracy varies with f
rate. Reduced conversion accuracy occurs at maximum.
ADCLK
Table A–13 ADC Conversion Characteristics (Operating)
(VDD and VDDA = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH,
0.5 MHz ≤ f
≤ 1.0 MHz, 2 clock input sample time)
ADCLK
Num
Parameter
Symbol
1 Count
DNL
Min
—
Typical
20
Max
—
0.5
1
Unit
1
1
2
3
4
mV
8-bit Resolution
8-bit Differential Nonlinearity
8-bit Integral Nonlinearity
–0.5
–1
—
Counts
Counts
Counts
INL
—
2
AE
–1
—
1
8-bit Absolute Error
1
5
6
7
8
9
1 Count
DNL
INL
—
5
—
0.5
2.0
2.5
—
mV
10-bit Resolution
3
–0.5
–2.0
–2.5
—
—
—
—
20
Counts
Counts
Counts
kΩ
10-bit Differential Nonlinearity
3
10-bit Integral Nonlinearity
3,4
AE
10-bit Absolute Error
5
R
S
Source Impedance at Input
NOTES:
1. At V
–V = 5.12 V, one 10-bit count = 5 mV and one 8-bit count = 20 mV.
RL
RH
2. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2
count (10 mV) circuit (differential, integral, and offset) error.
3. Conversion accuracy varies with f
rate. Reduced conversion accuracy occurs at maximum f
ADCLK
AD-
. Assumes that minimum sample time (2 ADC Clocks) is selected.
CLK
4. 10-bit absolute error of 2.5 counts (12.5 mV) includes 1/2 count (2.5 mV) inherent quantization error
and 2 counts (10 mV) circuit (differential, integral, and offset) error.
5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on
junction leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Ex-
pected error in result value due to junction leakage is expressed in voltage (V
):
ERRJ
V
= R X I
OFF
ERRJ
S
where I
OFF
is a function of operating temperature, as shown in Table A–11.
Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage
between successive conversions, and the size of the decoupling capacitor used. Error levels are best
determined empirically. In general, continuous conversion of the same channel may not be compatible
with high source impedance.
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IDEAL TRANSFER CURVE
(NO CIRCUIT ERROR)
8-BIT TRANSFER CURVE
A
C
B
D GI TI A OL U T PU T
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
A – +1/2 COUNT (10 mV) INHERENT QUANTIZATION ERROR
B – CIRCUIT-CONTRIBUTED +10mV ERROR
– + 20 mV ABSOLUTE ERROR (ONE 8-BIT COUNT)
C
ADC 8-BIT ACCURACY
Figure A–20 8-Bit ADC Conversion Accuracy
IDEAL TRANSFER CURVE
10-BIT TRANSFER CURVE
(NO CIRCUIT ERROR)
C
B
A
0
20
40
INPUT IN mV, V – V = 5.120 V
60
RH
RL
– +.5 COUNT (2.5 mV) INHERENT QUANTIZATION ERROR
A
B – CIRCUIT-CONTRIBUTED +10 mV ERROR
C – +12.5 mV ABSOLUTE ERROR (2.5 10-BIT COUNTS)
ADC 10-BIT ACCURACY
Figure A–21 10-Bit ADC Conversion Accuracy
M68HC16ZEC20/D
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