MB2052 [NXP]
Dual octal registered transceiver 3-State; 双八进制登记收发器三态
| 型号： | MB2052 |
| 厂家： | 
NXP |
| 描述： | Dual octal registered transceiver 3-State |
| 文件： | 总7页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
The MB2052 is a dual octal registered
FEATURES
• Two 8-bit registered transceivers
• Latch-up protection exceeds 500mA per
transceiver. Two 8-bit registers store data
flowing in both directions between two
bidirectional buses. Data applied to the inputs
is entered and stored on the rising edge of
the Clock (nCPXX) provided that the Clock
Enable (nCEXX) is Low. The data is then
present at the 3-State output buffers, but is
only accessible when the Output Enable
(nOEXX) is Low. Data flow from A inputs to B
outputs is the same as for B inputs to A
outputs.
Jedec JC40.2 Std 17
• ESD protection exceeds 2000V per MIL
• Live insertion/extraction permitted
STD 883 Method 3015 and 200V per
• Power-up 3-State
Machine Model
• Power-up reset
DESCRIPTION
The MB2052 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
• Multiple V and GND pins minimize
CC
switching noise
• Independent registers for A and B buses
output drive.
• Output capability: +64mA/–32mA
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
Propagation delay
nCPBA to nAx or
nCPAB to nBx
t
t
PLH
PHL
C = 50pF; V = 5V
5.7
ns
L
CC
C
Input capacitance
I/O capacitance
V = 0V or V
CC
4
7
pF
pF
nA
IN
I
C
V = 0V or V ; 3-State
O CC
I/O
I
Total supply current
Outputs disabled; V = 5.5V
120
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
52-pin plastic Quad Flat Pack
–40°C to +85°C
MB2052BB
1418B
PIN CONFIGURATION
LOGIC SYMBOL
50 51
1
2
3
5
6
7
52 51 50 49 48 47 46 45 44 43 42 41 40
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1CPAB
48
49
1
1A2
1A3
39 1B2
38 1B3
37 1B4
36 1B5
1CEAB
1OEBA
1OEAB
46
47
2
3
4
45
44
1CPBA
1CEBA
1A4
GND
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
1A5
1A6
1A7
2A0
5
6
7
8
35 1B6
34 1B7
33 2B0
32 2B1
MB2052
52-pin PQFP
42 41 39 38 37 36 35 34
8
9
10
11 12 13 15 16
2A1
9
31 2B2
30 GND
29 2B3
28 2B4
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2CPAB
2A2 10
2A3 11
2A4 12
19
18
2CEAB
2OEBA
2OEAB
21
20
22
23
2CPBA
2CEBA
2A5 13
27 2B5
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
14 15 16 17 18 19 20 21 22 23 24 25 26
33 32 31 29 28 27 25 24
1
August 23, 1993
853-1712 10586
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
LOGIC SYMBOL (IEEE/IEC)
49
18
23
21
20
EN1
44
EN1
EN2
EN3
EN4
EN2
46
EN3
47
EN4
48
C5
45
C6
19
22
C5
C6
50
51
1
42
41
39
38
37
36
35
34
8
9
33
32
31
29
28
27
25
24
2, 3, 6 1, 4, 5
2, 3, 6 1, 4, 5
10
2
11
12
13
15
16
3
5
6
7
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
48, 45
19, 22
1CPAB / 1CPBA
2CPAB / 2CPBA
Clock input A to B / Clock input B to A
Clock enable input A to B / Clock enable input B to A
Data inputs/outputs (A side)
49, 44
18, 23
1CEAB / 1CEBA
2CEAB / 2CEBA
50, 51, 1, 2, 3, 5, 6, 7
8, 9, 10, 11, 12, 13, 15, 16
1A0 – 1A7
2A0 – 2A7
42, 41, 39, 38, 37, 36, 35, 34
33, 32, 31, 29, 28, 27, 25, 24
1B0 – 1B7
2B0 – 2B7
Data inputs/outputs (B side)
47, 46
20, 21
1OEAB / 1OEBA
2OEAB / 2OEBA
Output enable inputs
4, 17, 30, 43
14, 26, 40, 52
GND
Ground (0V)
V
CC
Positive supply voltage
FUNCTION TABLE for Register nAx or nBx
INPUTS
INTERNAL
OPERATING
nAx or nBx
nCPXX
nCEXX
Q
MODE
X
X
H
NC
Hold data
L
H
↑
↑
L
L
L
H
Load data
H =High voltage level
L
↑
X
=Low voltage level
=Low-to-High transition
=Don’t care
XX=AB or BA
NC=No change
2
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
FUNCTION TABLE for Output Enable
INPUTS
nOEXX
H
INTERNAL
nAx or nBx
OUTPUTS
Z
OPERATING
MODE
Q
X
Disable outputs
Enable outputs
L
L
L
H
L
H
H =High voltage level
L
X
=Low voltage level
=Don’t care
XX=AB or BA
=High impedance ”off” state
Z
LOGIC DIAGRAM
nCEAB
nCPAB
nOEAB
DETAIL A
CE
Q
nA0
D
CP
CE
Q
D
nB0
CP
nB1
nB2
nB3
nB4
nB5
nB6
nB7
nA1
nA2
nA3
DETAIL A X 7
nA4
nA5
nA6
nA7
nCEBA
nCPBA
nOEBA
3
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
0
MAX
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
4
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
MIN
TYP
–0.9
2.9
MAX
MIN
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
Low-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
2.4
OH
I
IL
IH
V
OL
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output low voltage
= 5.5V; I = 1mA; V = GND or V
OL I CC
I
I
Input leakage
current
Control pins
Data pins
V
V
= 5.5V; V = GND or 5.5V
±0.01 ±1.0
±1.0
µA
µA
CC
I
= 5.5V; V = GND or 5.5V
5
100
100
CC
I
I
Power-off leakage current
Power-up/down 3-State
V
= 0V; V or V ≤ 4.5V
±5.0
±100
±100
±50
µA
µA
OFF
CC
O
I
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
;
O
I
CC
I
±5.0
±50
PU/PD
4
output current
= Don’t care
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
IH
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
O I cc
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–70
120
39
–180
250
60
–50
–180
250
60
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3-State;
I
120
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
CC
mA
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω
R
F
L
L
LIMITS
T
V
= +25°C
= +5.0V
T
= –40°C to +85°C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V ±0.5V
CC
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
1
1
200
250
200
MHz
ns
MAX
t
t
Propagation delay
nCPBA to nAx, nCPAB to nBx
2.1
2.6
3.7
4.1
4.9
5.3
2.1
2.6
5.4
5.8
PLH
PHL
t
t
Output enable time
nOEBA to nAx, nOEAB to nBx
3
4
1.2
2.0
2.9
3.7
4.1
5.0
1.2
2.0
4.8
5.8
PZH
PZL
ns
ns
t
Output disable time
nOEBA to nAx, nOEAB to nBx
3
4
1.0
1.5
3.5
3.0
4.7
4.1
1.0
1.5
5.2
4.6
PHZ
t
PLZ
5
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
= +5.0V
T
= –40°C to +85°C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V ±0.5V
CC
MIN
TYP
MIN
t (H)
t (L)
s
Setup time
nAx to nCPAB or nBx to nCPBA
2.5
01.5
0.8
0.0
2.5
1.5
S
2
2
2
2
1
ns
ns
ns
ns
ns
t (H)
Hold time
nAx to nCPAB or nBx to nCPBA
1.5
0.5
0.0
–0.8
1.5
0.5
h
t (L)
h
t (H)
Setup time
nCEAB to nCPAB, nCEBA to nCPBA
3.0
2.0
1.4
0.7
3.0
2.0
s
t (L)
s
t (H)
Hold time
nCEAB to nCPAB, nCEBA to nCPBA
0.5
0.0
–0.7
–1.3
0.5
0.0
h
t (L)
h
t (H)
nCPAB or nCPBA pulse width,
High or Low
2.5
3.5
1.4
2.1
2.5
3.5
w
t (L)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1/f
MAX
nCPBA or
nCPAB
nAx, nBx
nCEAB, nCEBA
V
V
V
t
M
M
M
V
V
V
V
V
M
M
M
M
t
(H)
t (L)
w
t (H)
t
(H)
t (L)
t (L)
h
w
s
h
s
t
PHL
PLH
nCPAB, nCPBA
nAx or nBx
V
V
M
V
M
M
M
Waveform 2. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
nOEAB,
nOEBA
nOEAB,
nOEBA
V
V
V
V
M
M
t
M
M
t
t
t
PLZ
PZH
PHZ
PZL
V
–0.3V
0V
OH
nAx, nBx
nAx, nBx
V
V
M
M
V
+0.3V
0V
OL
Waveform 3. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
6
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal registered transceiver (3-State)
MB2052
TEST CIRCUIT AND WAVEFORMS
V
t
W
CC
AMP (V)
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
R
V
V
OUT
L
L
IN
0V
PULSE
GENERATOR
D.U.T
t
t
(t
(t
)
t
t
(t )
R
THL
F
TLH
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
Rep. Rate
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
MB
3.0V
1MHz
500ns 2.5ns 2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
7
August 23, 1993
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