MB2373 [NXP]
Dual octal transparent latch 3-State; 双八进制透明锁存器三态
| 型号： | MB2373 |
| 厂家： | 
NXP |
| 描述： | Dual octal transparent latch 3-State |
| 文件： | 总11页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
one setup time before the High-to-Low
enable transition.
FEATURES
• 16-bit transparent latch
DESCRIPTION
The MB2373 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls
eight 3-State buffers independent of the latch
operation.
• Multiple V and GND pins minimize
CC
switching noise
• Power-up 3-State
The MB2373 device is a dual octal
transparent latch coupled to two sets of eight
3-State output buffers. The two sections of
the device are controlled independently by
Enable (nE) and Output Enable (nOE) control
gates.
• Live insertion/extraction permitted
• Power-up reset
When nOE is Low, the latched or transparent
data appears at the outputs. When nOE is
High, the outputs are in the High–impedance
“OFF” state, which means they will neither
drive nor load the bus.
• 3-State output buffers
• Output capability: +64mA/–32mA
The data on each set of D inputs are
transferred to the latch outputs when the
Latch Enable (nE) input is High. The latch
remains transparent to the data inputs while
nE is High, and stores the data that is present
• Latch-up protection exceeds 500mA per
JEDEC JC40.2 Std 17
• ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per
Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
2.9
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
nA
IN
I
C
V
= 0V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
DRAWING NUMBER
52–pin plastic Quad Flat Pack
MB2373BB
1418B
PIN CONFIGURATION
LOGIC SYMBOL
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
V
V
CC
47
45
1E
CC
19
21
2E
1Q4
2
3
4
38 1D4
37 1D5
36 GND
1Q5
1OE
2OE
48
49
51
52
1Q0
1Q1
1Q2
1Q3
GND
44
43
41
40
1D0
1D1
1D2
1D3
8
9
2Q0
2Q1
2Q2
2Q3
32
31
29
28
2D0
1Q6
1Q7
GND
2Q0
5
6
7
8
35 1D6
34 1D7
33 GND
32 2D0
2D21
2D2
MB2373
52–pin PQFP
11
12
2D3
2
3
5
6
1Q4
1Q5
1Q6
1Q7
38
37
35
34
1D4
1D5
1D6
1D7
14
15
17
18
2Q4
2Q5
2Q6
2Q7
26
25
23
22
2D4
2D5
2D6
2D7
2Q1
9
31 2D1
30 GND
29 2D2
28 2D3
GND 10
2Q2 11
2Q3 12
13
27
V
V
CC
CC
14 15 16 17 18 19 20 21 22 23 24 25 26
1
August 23, 1993
853-1669 10587
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
44, 43, 41, 40,38, 37, 35, 34,
32, 31, 29, 28, 26, 25, 23, 22
1D0 – 1D7
2D0 – 2D7
Data inputs
48, 49, 51, 52, 2, 3, 5, 6,
8, 9, 11, 12, 14, 15, 17, 18
1Q0 – 1Q7
2Q0 – 2Q7
Data outputs
47, 19
45, 21
1OE, 2OE
1E, 2E
Output enable inputs (active–Low)
Enable inputs (active–High)
4, 7, 10, 16, 20, 24, 30,
33, 36, 42, 46, 50
GND
Ground (0V)
1, 13, 27, 39
V
CC
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
47
45
19
EN
C1
EN
21
C1
44
43
41
40
38
37
35
34
32
31
29
28
26
25
23
22
48
49
51
52
2
8
9
1D
1D
11
12
14
15
17
18
3
5
6
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
E
D
D
E
D
E
D
D
E
D
E
D
Q
E
Q
Q
Q
E
Q
Q
Q
E
Q
nE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
2
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
FUNCTION TABLE
INPUTS
INTERNAL
REGISTER
OUTPUTS
nQ0 – nQ7
OPERATING MODE
nOE
nE
nDx
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
i
h
L
H
L
H
Latch and read register
Hold
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
0
MAX
5.5
V
DC supply voltage
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5V; I = 1mA; V = GND or V
O I CC
I
Input leakage current
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±100
±100
OFF
CC
O
I
Power-up/down 3-State
output current
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
= GND
;
O
I
CC
I
±5.0
±50
±50
µA
PU/PD
4
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
–70
5.0
50
–50
–180
50
50
–50
–180
50
µA
µA
mA
µA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
OZL
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–50
O
I
Output High leakage current
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
CCH
I
= 5.5V; Outputs High, V = GND or V
120
44
250
60
250
60
I
CC
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
= 5.5V; Outputs 3-State;
I
120
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
4
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
MIN
TYP
MIN
MAX
t
t
Propagation delay
nDx to nQx
1.3
1.3
2.8
2.9
4.1
4.1
1.3
1.3
4.8
4.8
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
nE to nQx
1.8
2.0
3.5
3.5
4.9
4.9
1.8
2.0
5.7
5.5
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.2
2.1
2.9
3.8
4.1
5.3
1.2
2.1
5.1
6.1
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
1.4
2.0
3.7
3.6
5.0
4.6
1.4
2.0
5.5
5.1
PHZ
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, High or Low
nDx to nE
1.0
1.0
0.0
0.3
1.0
1.0
s
3
3
1
ns
ns
ns
t (H)
Hold time, High or Low
nDx to nE
0.5
0.5
–0.2
0.0
0.5
0.5
h
t (L)
h
Enable pulse width
High
t (H)
w
2.5
1.0
2.5
5
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
AC WAVEFORMS
nE
V
V
V
t
V
V
M
M
t
M
M
M
t
nDx
nQx
(H)
t
w
PLH
PHL
t
PHL
PLH
V
V
M
M
nQx
V
V
M
M
Waveform 1. Propagation Delay, Enable to
Output, and Enable Pulse Width
Waveform 2. Propagation Delay for Data to Outputs
V
V
V
V
nDx
M
M
M
M
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
nE
V
V
M
M
Waveform 3. Data Setup and Hold Times
nOE
V
V
V
V
M
nOE
M
t
M
M
t
t
t
PLZ
PZH
PHZ
PZL
V
–0.3V
OH
nQx
V
V
M
M
nQx
V
+0.3V
0V
OL
0V
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE: For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
6
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
TEST CIRCUIT AND WAVEFORM
V
t
W
CC
AMP (V)
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
V
V
R
R
IN
OUT
L
L
0V
PULSE
GENERATOR
D.U.T
t
t
(t
(t
)
t
t
(t )
R
THL
F
TLH
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
Rep. Rate
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
MB
3.0V
1MHz
500ns 2.5ns 2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
7
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
t
vs Temperature (T
)
Adjustment of t
for
PLH
amb
PLH
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nDx to nQx
L
nDx to nQx
6
5
4
3
2
1
0
4
3
2
MAX
4.5V
16 switching
8
1
switching
switching
CC
1
5.5V
CC
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
amb
Adjustment of t
for
PHL
PHL
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nDx to nQx
L
nDx to nQx
6
5
4
3
2
1
0
4
3
2
16 switching
MAX
4.5V
8
1
switching
switching
1
CC
5.5V
CC
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
Adjustment of t
for
PLH
amb
PLH
C = 50pF, 1 Output Switching
L
Load Capacitance and # of Outputs Switching
nE to nQx
nE to nQx
7
6
5
4
3
2
1
4
3
2
16 switching
MAX
4.5V
8
switching
1
switching
1
CC
5.5V
CC
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
8
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
t
vs Temperature (T
)
Adjustment of t
for
PHL
amb
PHL
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nE to nQx
L
nE to nQx
7
6
5
4
3
2
1
4
3
2
16 switching
8
1
switching
switching
MAX
4.5V
1
CC
5.5V
CC
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
Adjustment of t for
PZH
PZH
amb
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nOE to nQx
L
nOE to nQx
6
5
4
3
2
1
0
5
4
3
MAX
4.5V
16 switching
8
1
switching
switching
CC
2
1
5.5V
MIN
CC
0
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
Adjustment of t for
PZL
PZL
amb
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nOE to nQx
L
nOE to nQx
7
6
5
4
3
2
1
4
3
2
MAX
4.5V
16 switching
8
switching
1
switching
CC
1
5.5V
CC
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
9
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
t
vs Temperature (T
)
Adjustment of t
for
PHZ
amb
PHZ
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nOE to nQx
L
nOE to nQx
7
6
5
4
3
2
1
0
5
4
3
16 switching
8
1
switching
switching
MAX
4.5V
2
CC
5.5V
CC
1
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
Adjustment of t for
PLZ
PLZ
amb
C = 50pF, 1 Output Switching
Load Capacitance and # of Outputs Switching
nOE to nQx
L
nOE to nQx
6
5
4
3
2
1
6
5
4
16 switching
MAX
4.5V
8
1
switching
switching
3
CC
5.5V
2
CC
1
0
MIN
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
t
vs Temperature (T
)
Adjustment of t for
TLH
TLH
amb
C = 50pF, 1 Output Switching
L
Load Capacitance and # of Outputs Switching
5
4
3
2
1
9
7
16 switching
8
1
switching
switching
5
4.5V
5.5V
CC
CC
3
1
–1
–3
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
10
August 23, 1993
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
t
vs Temperature (T
)
Adjustment of t
for
THL
amb
THL
C = 50pF, 1 Output Switching
L
Load Capacitance and # of Outputs Switching
4
3
2
1
0
4
3
16 switching
8
switching
switching
1
2
1
4.5V
5.5V
CC
CC
0
–1
–2
–55 –35 –15
5
25
45
65
85
105 125
0
50
100
150
200
°C
pF
V
OHV
and V
vs Load Capacitance
V
OHP
and V
vs Load Capacitance
OLP
OLV
V
CC
= 5V, V = 0 to 3V
V = 5V, V = 0 to 3V
CC IN
IN
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
5
125°C
25°C
–55°C
4
3
125°C
25°C
–55°C
2
1
125°C
25°C
–55°C
0
125°C
25°C
–55°C
–1
–2
0
50
100
150
200
0
50
100
150
200
pF
pF
11
August 23, 1993
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