MC100ES8111ACR2_技术文档

Document Number: MC100ES8111

Rev 3, 09/2005

Freescale Semiconductor

Technical Data

Low Voltage 1:10 Differential HSTL

Clock Fanout Buffer

MC100ES8111

The MC100ES8111 is a bipolar monolithic differential clock fanout buffer.

Designed for most demanding clock distribution systems, the MC100ES8111

supports various applications that require the distribution of precisely aligned

differential clock signals. Using SiGe technology and a fully differential

architecture, the device offers very low skew outputs and superior digital signal

characteristics. Target applications for this clock driver are high performance

clock distribution in computing, networking and telecommunication systems.

LOW-VOLTAGE 1:10

DIFFERENTIAL

HSTL CLOCK

FANOUT BUFFER

Features

•

1:10 differential clock fanout buffer

80 ps maximum device skew

SiGe technology

Supports DC to 625 MHz operation of clock or data signals

HSTL compatible differential clock outputs

PECL and HSTL compatible differential clock inputs

3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply

Supports industrial temperature range

Standard 32 lead LQFP package

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

32-lead Pb-free package available

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

Functional Description

The MC100ES8111 is designed for low skew clock distribution systems and

supports clock frequencies up to 625 MHz. The device accepts two clock

sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts

PECL compatible signals. The selected input signal is distributed to 10 identical,

differential HSTL compatible outputs.

In order to meet the tight skew specification of the device, both outputs of a

differential output pair should be terminated, even if only one output is used. In

the case where not all 10 outputs are used, the output pairs on the same package

side as the parts being used on that side should be terminated.

The HSTL compatible output levels are generated with an open emitter

architecture. This minimizes part-to-part and output-to-output skew. The

open-emitter outputs require a 50 Ω DC termination to GND (0 V). The output

supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The

output enable control is synchronized internally preventing output runt pulse

generation. Outputs are only disabled or enabled when the outputs are already

in logic low state (true outputs logic low, inverted outputs logic high). The internal

synchronizer eliminates the setup and hold time requirements for the external

clock enable signal. The device is packaged in a 7x7 mm²32-lead LQFP

package.

ORDERING INFORMATION

Device

Package

LQFP-32

MC100ES8111FA

MC100ES8111FAR2

MC100ES8111AC

MC100ES8111ACR2

LQFP-32

LQFP-32 (Pb-Free)

Q0

V_CC

Q1

Q2

24 23 22 21 20 19 18 17

CLK0

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

V

CC0

V

CCO

Q2

Q7

Q8

Q3

Q4

0

1

Q2

Q1

MC100ES8111

Q5

OE

V_CC

Q1

Q0

Q8

Q9

CLK1

Q6

Q7

Q8

Q9

V

CCO

CLK_SEL

1

2

3

4

5

6

7

8

Q9

OE

Figure 1. MC100ES8111 Logic Diagram

Table 1. Pin Configuration⁽¹⁾

Figure 2. 23-Lead Package Pinout (Top View)

CLK0, CLK0

CLK1, CLK1

CLK_SEL

OE

I/O

Input

Type

Function

HSTL

PECL

Differential HSTL reference clock signal input

Differential PECL reference clock signal input

Reference clock input select

Input

LVCMOS

Output enable/disable. OE is synchronous to tlhe input reference clock which

eliminates possible output runt pulses when the OE state is changed.

Q[0-9], Q[0-9]

GND

Output

Supply

HSTL

Differential clock outputs

Negative power supply

V_CC

Positive power supply of the device core (3.3 V)

V_CCO

Positive power supply of the HSTL outputs. All V_CCOpins must be connected to the

positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.

1. Input pull-up/pull-down resistors have a value of 75 kΩ.

Table 2. Function Table

Control

Default

0

1

CLK_SEL

0

CLK0, CLK0 (HSTL) is the active differential clock

input

CLK1, CLK1 (PECL) is the active differential clock

input

OE

0

Q[0-9], Q[0-9] are active. Deassertion of OE can be Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of

asynchronous to the reference clock without

generation of output runt pulses.

OE can be asynchronous to the reference clock

without generation of output runt pulses.

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

2

Table 3. Absolute Maximum Ratings⁽¹⁾

Symbol

V_CC

Characteristics

Min

–0.3

Max

3.6

Unit

V

Condition

Supply Voltage

DC Input Voltage

V_CCO

V_IN

3.1

V

V_CC+ 0.3

±20

V

V_OUT

I_IN

I_OUT

T_S

DC Output Voltage

V

DC Input Current

mA

°C

DC Output Current

±50

Storage Temperature

Functional Temperature Range

–65

125

T_Func

T_A= –40

T_J= +110

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Table 4. General Specifications

Symbol

V_TT

Characteristics

Output termination voltage

Min

Typ

Max

Unit

V

Condition

0

MM

ESD Protection (Machine model)

ESD Protection (Human body model)

ESD Protection (Charged device model)

Latch-up Immunity

200

2000

200

V

HBM

CDM

LU

V

mA

pF

C_IN

Input Capacitance

4.0

Inputs

θ_JA

Thermal resistance junction to ambient

JESD 51-3, single layer test board

83.1

73.3

68.9

63.8

57.4

86.0

75.4

70.9

65.3

59.6

°C/W Natural convection

°C/W 100 ft/min

°C/W 200 ft/min

°C/W 400 ft/min

°C/W 800 ft/min

JESD 51-6, 2S2P multilayer test board

59.0

54.4

52.5

50.4

47.8

60.6

55.7

53.8

51.5

48.8

°C/W Natural convection

°C/W 100 ft/min

°C/W 200 ft/min

°C/W 400 ft/min

°C/W 800 ft/min

θ_JC

Thermal Resistance Junction to Case

23.0

26.3

°C/W MIL-SPEC 883E

Method 1012.1

T_J

Operating Junction Temperature⁽¹⁾

(continuous operation)

MTBF = 9.1 years

110

°C

1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected

according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more

information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES8111 to be used

in applications requiring industrial temperature range. It is recommended that users of the MC100ES8111 employ thermal modeling

analysis to assist in applying the junction temperature specifications to their particular application.

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

3

Table 5. DC Characteristics (V_CC= 3.3 V ± 5%, V_CCO= 1.5 V ± 0.1 V or V_CCO= 1.8 V ± 0.1 V), T_J= 0°C to +110°C

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Clock Input Pair CLK0, CLK0 (HSTL differential signals)

V_DIF

V_{X, IN}

V_IH

Differential Input Voltage⁽¹⁾

Differential Cross Point Voltage⁽²⁾

Input High Voltage

0.2

0.25

V

0.68 - 0.9

V_CC-1.3

V_X+0.1

V_IL

Input Low Voltage

V_X-0.1

±150

I_IN

Input Current

µA V_IN= V_X± 0.1 V

Clock Input Pair CLK1, CLK1 (PECL differential signals)

V_PP

V_CMR

V_IH

Differential Input Voltage⁽³⁾

Differential Cross Point Voltage⁽⁴⁾

Input Voltage High

0.15

1.0

V

Differential operation

V_CC-0.6

V_CC-0.880

V_CC-1.475

±150

V_CC-1.165

V_CC-1.810

V_IL

Input Voltage Low

I_IN

Input Current

µA V_IN= V_IHor V_IN

LVCMOS Control Inputs OE, CLK_SEL

V_IL

V_IH

I_IN

Input Voltage Low

Input Voltage High

Input Current

0.8

±150

0.9

V

2.0

V

µA V_IN= V_IHor V_IN

HSTL Clock Outputs (Q[0-9], Q[0-9])

V_{X, OUT}Output Differential Crosspoint

0.68

1.0

0.75

V

V_OH

V_OL

Output High Voltage

Output Low Voltage

0.4

Supply Current

I_CCMaximum Supply Current without output

80

105

410

mA V_CCpin (core)

termination current

(5)

I_CCO

Maximum Supply Current, outputs

350

mA V_CCOpins (outputs)

terminated 50 Ω to V_TT

1. V_DIF(DC) is the minimum differential HSTL input voltage swing required for device functionality.

2. V_X(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V_X(DC)

range and the input swing lies within the V_PP(DC) specification.

3. V_PP(DC) is the minimum differential input voltage swing required to maintain device functionality.

4. V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMR(DC)

range and the input swing lies within the V_PP(DC) specification.

5. I_CCincludes current through the output resistors (all outputs terminated to V_TT). See also “Power Consumption and Junction Temperature”

on page 6.

MC100ES8111

Advanced Clock Drivers Devices

4

Freescale Semiconductor

Table 6. AC Characteristics (V_CC= 3.3 V ± 5%, V_CCO= 1.5 V ± 0.1 V or V_CCO= 1.8 V ± 0.1 V), T_J= 0°C to +110°C⁽¹⁾

Symbol Characteristics

Min

Typ

Max

Unit

Condition

REF_SEL= 0, Active Clock Input Pair CLK0, CLK0 (HSTL differential signals)

V_DIF

V_{X, IN}

f_CLK

t_PD

Differential Input Voltage⁽²⁾(Peak-to-Peak)

Differential Cross Point Voltage⁽³⁾

Input Frequency

0.4

0.68

0

V

0.9

625

MHz

Propagation Delay CLK0 to Qn

V_CCO= 1.8 V

_CCO= 1.5 V

700

990

1030

1270

1420

ps

Differential

V

t_SK(PP)Output-to-Output Skew (Part-to-Part)

t_SK(P)

Output Pulse Skew⁽⁴⁾

V_CCO= 1.8 V

_CCO= 1.5 V

570

720

ps

V

V_CCO= 1.8 V

_CCO= 1.5 V

100

150

ps

V

REF_SEL = 1, Active Clock Input Pair CLK1, CLK1 (PECL differential signals)

V_PP

V_CMR

f_CLK

t_PD

Differential Input Voltage⁽⁵⁾(Peak-to-Peak)

Differential Input Crosspoint Voltage⁽⁶⁾

Input Frequency

0.2

1.0

0

1.0

V_CC-0.6

625

V

MHz

Differential

Propagation Delay CLK1 to Qn

V_CCO= 1.8 V

_CCO= 1.5 V

590

860

910

1220

1360

ps

V

t_SK(PP)Output-to-Output Skew (Part-to-Part)

t_SK(P)

Output Pulse Skew⁽⁷⁾

V_CCO= 1.8 V

_CCO= 1.5 V

630

770

ps

Differential

V

V_CCO= 1.8 V

_CCO= 1.5 V

150

200

ps

V

HSTL Clock Outputs (Qn, Qn)

V_{X, OUT}Output Differential Crosspoint

0.68

0.91

1.1

V

V_OH

Output High Voltage

V_CCO= 1.8 V

_CCO= 1.5 V

V_CCO-0.8 V

1.5

V

_CCO-0.5 V

V_OL

Output Low Voltage

0.2

0.8

V

V_O(P-P)Differential Output Voltage (Peak-to-Peak) V_CCO= 1.8 V

_CCO= 1.5 V

0.45

0.40

1.0

V

t_SK(O)

Output-to-Output Skew

V_CCO= 1.8 V

_CCO= 1.5 V

37

60

80

105

ps

Differential

V

t_JIT(CC)Output Cycle-to-Cycle Jitter RMS (1 σ)

1.0

ps

ns

t_r, t_f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

150

800

20% to 80%

T=CLKn period

(8)

t_PDL

2.5·T + t_PD

3.0·T + t_PD

3.5·T + t_PD

4.0·T + t_PD

(9)

t_PLE

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT(GND).

2. V_DIF(DC) is the minimum differential HSTL input voltage swing required for device functionality.

3. V_X(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V_X(DC)

range and the input swing lies within the V_DIF(DC) specification.

4. Output duty cycle is DC = (0.5 ± 150 ps · f_OUT) · 100%. E.g. the DC range at f_OUT= 100 MHz is 48.5% < DC < 51.5%.

5. V_PP(AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device

skew.

6. V_CMR(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V_CMR

(AC) range and the input swing lies within the V_PP(AC) specification. Violation of V_CMR(AC) or V_PP(AC) impacts the device propagation

delay, device and part-to-part skew.

7. Output pulse skew is the absolute difference of the propagation delay times: | t_PLH- t_PHL|. The output duty cycle is DC = (0.5 ± 200 ps ·

f

_OUT) · 100%. E.g. the DC range at f_OUT= 100 MHz and V_CCO= 1.5 V is 48.0% < DC < 52.0%.

8. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).

9. Propagation delay OE assertion to output enabled (active).

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

5

APPLICATIONS INFORMATION

GND, with the termination resistor located as close as

Test Reference and Output Termination

possible to the end of the clock transmission line. All DC and

AC specifications apply to this termination method (see the

reference circuit shown in Figure 3 “MC100ES8111 AC Test

Reference”). The MC100ES8111 does not support an output

termination to V_TT= V_X= 0.75 V (center voltage termination).

The MC100ES8111 is designed for high-frequency and

low-skew clock distribution. The high-speed differential

outputs are capable of driving 50 Ω transmission lines and

always require a DC termination to V_TT(GND). In order to

maintain the tight skew and timing specifications, it is

recommend to terminate the differential outputs by 50 Ω to

V_CC= 3.3 V ± 5%

V_CCO= 1.8 V ± 0.1 V or 1.5 V ± 0. 1 V

Z = 50 Ω

Oscilloscope

Differential Pulse

or Tester

Generator

Z = 50 Ω

DUT

MC100ES8111

R_T= 50 Ω

V_TT= GND

Figure 3. MC100ES8111 AC Test Reference

Power Consumption and the Junction Temperature

typical power consumption of 575 mW (all outputs terminated

50 ohms to GND, V_CCO= 1.8 V), the junction temperature of

the MC100ES8111 is approximately T_A+ 31°C, and the

minimum ambient temperature in this example case

calculates to -31°C (the maximum ambient temperature

is 79°C. See Table 8). Exceeding the minimum junction

temperature specification of the MC100ES8111 does not

have a significant impact on the device functionality.

However, the continuous use the MC100ES8111 at high

ambient temperatures requires thermal management to not

exceed the specified maximum junction temperature.

The power consumption P_TOTof the MC100ES8111

depends on the supply voltages and the DC output

termination. The clock frequency has a negligible effect on

P_TOT. If all outputs are terminated by 50 Ω to GND, the device

power consumption is calculated by:

P_TOT= V_CC· I_CC+ I_CCO· (V_CCO- V_X)

For instance, at a supply voltage of V_CC= 3.3 V and a

termination of 50 Ω to GND, the typical device power

consumption is 579 mW at V_CCO= 1.8 V and 474 mW at

V_CCO= 1.5 V.

Table 8. Ambient Temperature Ranges (P_tot= 575 mW)

Table 7. Power Consumption

(1)

R_thja(2s2p board)

Natural convection

T_{A, max}

T_{A, min}

(1)

(2)

MC100ES8111

P_{TOT, TYP}

P_{TOT, MAX}

59.0°C/W

54.4°C/W

52.5°C/W

50.4°C/W

47.8°C/W

-34°C

-31°C

-30°C

-29°C

-27.5°C

76°C

79°C

V_CCO= 1.5 V

V_CCO= 1.8 V

470 mW

575 mW

647 mW

769 mW

100 ft/min

200 ft/min

400 ft/min

800 ft/min

80°C

81°C

1. Typical case: V_CC, V_CCOat nominal values and using typical

_CC, I_CCOdata.

I

82.5°C

2. Worst case: V_CC, V_CCat max. values and using max. I_CC, I_CCO

limits.

1. The MC100ES8111 device function is guaranteed from

T_A= -40°C to T_J= 110°C.

To make the optimum use of high clock frequency and low

skew capabilities of the MC100ES8111, the device is

specified, characterized and tested for the junction

temperature range of T_J= 0°C to +110°C. Because the exact

thermal performance depends on the PCB type, design,

thermal management and natural or forced air convection,

the junction temperature provides an exact way to correlate

the application specific conditions to the published

performance data of this datasheet. The correlation of the

junction temperature range to the application ambient

temperature range and vice versa can be done by

calculation:

Maintaining Lowest Device Skew

The MC100ES8111 guarantees low output-to-output skew

of max. 80 ps and a part-to-part skew of max. 630 ps

(V_CCO= 1.8 V). To ensure low skew clock signals in the

application, both outputs of any differential output pair need

to be terminated identically, even if only one output is used.

When fewer than all ten output pairs are used, identical

termination of all output pairs within the output bank (same

package side) is recommended. If an entire output bank is not

used, it is recommended to leave all of these outputs open

and unterminated. This will reduce the device power

consumption while maintaining minimum output skew.

T_J= T_A+ R_thja· P_tot

Assuming a thermal resistance (junction to ambient) of

54.4°C/W (2s2p board, 100 ft/min airflow, see Table 8) and a

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

6

Power Supply Bypassing

Output Enable/Disable Control

The MC100ES8111 is a mixed analog/digital product. The

differential architecture of the MC100ES8111 supports low

noise signal operation at high frequencies. In order to

maintain its superior signal quality, all V_CCpins should be

bypassed by high-frequency ceramic capacitors connected

to GND. If the spectral frequencies of the internally

generated switching noise on the supply pins cross the series

resonant point of an individual bypass capacitor, its overall

impedance begins to look inductive and thus increases with

increasing frequency. The parallel capacitor combination

shown ensures that a low impedance path to ground exists

for frequencies well above the noise bandwidth.

The MC100ES8111 enables and disables outputs

synchronously to the input clock signal. The user may enable

and disable the outputs by using the OE control regardless of

any hold and setup time constraints. Output runt pulses are

prevented in any case. Outputs are disabled in logic low state

(Qn=Low, Qn=High) without a change of the output

impedance.

V_CC

3.3 V ± 5%

MC100ES8111

33...100 nF

0.1 nF

1.8 V ± 0.1 V or

1.5 V ± 0. 1V

V_CCO

4

33...100 nF

Figure 4. V_CC, V_CCOPower Supply Bypass

CLKn

50%

OE

t_PDL(OE to Qn)

t_PLE(OE to Qn)

Qn

Outputs Disabled

Figure 5. MC100ES8111 Output Disable/Enable Timing

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

7

AC MEASUREMENT REFERENCES

Q0

CLK0

Qn

V_DIF= 1.0 V

V_X,IN= 0.75 V

Q0

QN

V_OH

V_O(P-P)

V_X;OUT

V_OL

QN

Qn

t_SK(O)

t_PD(CLK0 to Qn)

Figure 8. Output-to-Output Skew

REF_SEL = 0

The output-to-output skew is defined as the worst case

difference in propagation delay between any two similar

delay paths within a single device.

Figure 6. MC100ES8111 AC Reference

Measurement Waveform (HSTL Input)

CLK1

Qn

V_PP= 0.8 V

V_CMR= V_CC-1.3 V

80%

V_O(PP)

V_OH

20%

V_O(P-P)

V_X;OUT

t_R

t_F

V_OL

Qn

t_PD(CLK1 to Qn)

REF_SEL = 1

Figure 9. HSTL Output Rise/Fall Time

Figure 7. MC100ES8111 AC Reference

Measurement Waveform (PECL Input)

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

8

PACKAGE DIMENSIONS

PAGE 1 OF 3

CASE 873A-04

ISSUE C

32-LEAD LQFP PACKAGE

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

9

PACKAGE DIMENSIONS

PAGE 2 OF 3

CASE 873A-04

ISSUE C

32-LEAD LQFP PACKAGE

MC100ES8111

Advanced Clock Drivers Devices

Freescale Semiconductor

10

PACKAGE DIMENSIONS

PAGE 3 OF 3

CASE 873A-04

ISSUE C

32-LEAD LQFP PACKAGE

MC100ES8111

11

Advanced Clock Drivers Devices

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MC100ES8111

Rev. 3

09/2005


型号：	MC100ES8111ACR2
厂家：	NXP
描述：	100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 驱动输出元件逻辑集成电路
文件：	总12页 (文件大小：343K)
中文：	中文翻译
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MC100ES8111ACR2 [NXP]

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