MC12430FN [NXP]
IC,MISCELLANEOUS CLOCK GENERATOR,LDCC,28PIN,PLASTIC;型号: | MC12430FN |
厂家: | NXP |
描述: | IC,MISCELLANEOUS CLOCK GENERATOR,LDCC,28PIN,PLASTIC 时钟 局域网 外围集成电路 晶体 |
文件: | 总12页 (文件大小:323K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
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SEMICONDUCTOR TECHNICAL DATA
Order Number: MC12430/D
Rev. 5, 09/2001
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The MC12430 is a general purpose synthesized clock source. Its internal
VCO will operate over a range of frequencies from 400 to 800 MHz. The
differential PECL output can be configured to be the VCO frequency divided
by 1, 2, 4 or 8. With the output configured to divide the VCO frequency by 2,
and with a 16.000 MHz external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1 MHz steps. The PLL
loop filter is fully integrated so that no external components are required.
The synthesizer output frequency is configured using a parallel or serial
interface.
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HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
• 50 to 800 MHz Differential PECL Outputs
•
25 ps Peak–to–Peak Output Jitter
• Fully Integrated Phase–Locked Loop
• Minimal Frequency Over–Shoot
• Synthesized Architecture
• Serial 3–Wire Interface
• Parallel Interface for Power–Up
• Quartz Crystal Interface
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776–02
• 28–Lead PLCC and 32–Lead LQFP Packages
• Operates from 3.3 V or 5.0V Power Supply
Functional Description
The internal oscillator uses the external quartz crystal as the basis of its
frequency reference. The output of the reference oscillator is divided by 16
before being sent to the phase detector. With a 16 MHz crystal, this provides
a reference frequency of 1 MHz. Although this data sheet illustrates
functionality only for a 16 MHz crystal, any crystal in the 10–20 MHz range
can be used.
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either the
serial or parallel interfaces. The output of this loop divider is applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M x 2 times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4 or 8).
This divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated in
50Ω to VCC – 2.0 V. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs
to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial
interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the
chip.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
ꢀ
Motorola, Inc. 2001
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
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N[1:0]
Output Division
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28–Lead PLCC
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XTAL_SEL
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FREF_EXT
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XTAL
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Figure 1. Figure 1. 28–Lead Pinout (Top
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32–Lead LQFP
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Figure 2. Figure 2. 32–Lead Pinout (Top
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2
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
PIN DESCRIPTIONS
Pin Name
Function
Inputs
XTAL1, XTAL2
These pins form an oscillator when connected to an external series–resonant crystal.
S_LOAD
(Int. Pulldown) This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when
this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.
S_DATA
(Int. Pulldown) This pin acts as the data input to the serial configuration shift registers.
S_CLOCK (Int. Pulldown) This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
P_LOAD
(Int. Pullup)
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when
this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper
operation. P_LOAD is state sensitive.
M[8:0]
N[1:0]
OE
(Int. Pullup)
(Int. Pullup)
(Int. Pullup)
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of
P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition
of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the F
output.
OUT
Outputs
F , F
OUT OUT
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
TEST
The function of this output is determined by the serial configuration bits T[2:0]. The output is single–ended ECL.
Power
V
CC
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V
(V = PLL_V ). Current drain through V ≈ 85 mA.
CC
CC
CC
PLL_V
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply
is connected to +3.3V or 5.0V (V = PLL_V ). Current drain through PLL_V ≈ 15 mA.
CC
CC
CC
CC
GND
These pins are the negative supply for the chip and are normally all connected to ground.
Other
FREF_EXT (Int. Pulldown) LVCMOS/CMOS input which can be used as the PLL reference.
XTAL_SEL (Int. Pullup)
LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal.
A HIGH selects the crystal input.
3
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
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Figure 3. MC12430 Block Diagram (28–Lead PLCC Pinout)
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:
Output Frequency Range
N
FOUT
OUTPUT FREQUENCY RANGE
1
2
4
8
2 x M
M
M ÷ 2
M ÷ 4
400 – 800 MHZ
200 – 400 MHZ
100 – 200 MHZ
50 – 100 MHZ
FOUT = (FXTAL ÷ 16) x M x 2 ÷ N
(1)
From these ranges, the user will establish the value of N
required, then the value of M can be calculated based on the
appropriate equation above. For example, if an output
frequency of 131 MHz was desired, the following steps would
be taken to identify the appropriate M and N values. 131MHz
falls within the frequency range set by an N value of 4 so N
[1:0] = 01. For N = 4, FOUT = M ÷ 2 and M = 2 x FOUT.
Therefore, M = 131 x 2 = 262, so M[8:0] = 100000110.
Following this same procedure, a user can generate any
whole frequency desired between 50 and 800MHz. Note that
for N > 2 fractional values of FOUT can be realized. The size of
the programmable frequency steps (and thus the indicator of
the fractional output frequencies achievable) will be equal to
FXTAL ÷ 8 ÷ N.
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 ≤ M ≤ 400 for any input reference.
Assuming that a 16 MHz reference frequency is used, the
above equation reduces to:
FOUT = 2 x M ÷ N
For input reference frequencies other than 16 MHz, the set
of appropriate equations can be deduced from equation 1. For
computer applications, another useful frequency base would
Substituting the four values for N (1, 2, 4, 8) yields:
4
MOTOROLA
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Freescale Semiconductor, Inc.
MC12430
be 16.666 MHz. From this reference, one can generate a
family of output frequencies at multiples of the 33.333 MHz
PCI clock. As an example, to generate a 133.333 MHz clock
from a 16.666 MHz reference, the following M and N values
would be used:
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. The T2, T1 and T0 control bits are preset to ‘000’
when P_LOAD is LOW so that the PECL FOUT outputs are as
jitter–free as possible. Any active signal on the TEST output
pin will have detrimental affects on the jitter of the PECL output
pair. In normal operations, jitter specifications are only
guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin.
FOUT = 16.666 ÷ 16 x M x 2 ÷ N = 1.04166 x M x 2 ÷ N
Let N = 4, M = 133.3333 ÷ 1.04166 x 2 = 256
The value for M falls within the constraints set for PLL stability,
therefore, N[1:0] = 01 and M[8:0] = 10000000. If the value for
M fell outside of the valid range, a different N value would be
selected to try to move M in the appropriate direction.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MC12430 itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110 the
MC12430 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The N
divider drives the FOUT differential pair and the M counter
drives the TEST output pin. In this mode the S_CLOCK input
could be used for low speed board level functional test or
debug. Bypassing the PLL and driving FOUT directly gives the
user more control on the test clocks sent through the clock
tree. Figure 5 shows the functional setup of the PLL bypass
mode. Because the S_CLOCK is a CMOS level, the input
frequency is limited to 250 MHz or less. This means the fastest
the FOUT pin can be toggled via the S_CLOCK is 250MHz as
the minimum divide ratio of the N counter is 1. Note that the M
counter output on the TEST output will not be a 50% duty cycle
due to the way the divider is implemented.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition will
latch the information present on the M[8:0] and N[1:0] inputs
into the M and N counters. When the P_LOAD signal is LOW,
the input latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output pair. To
use the serial port, the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and the
M register with the final eight bits of the data stream on the
S_DATA input. For each register, the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figure 4 illustrates the timing diagram for both a parallel and a
serial load of the MC12430 synthesizer.
T2
T1
T0
TEST (Pin 20)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT/2
FOUT
LOW
M COUNTER/2 in
PLL Bypass Mode
FOUT/4
M[8:0] and N[1:0] are normally specified once at power–up
through the parallel interface, and then possibly again through
the serial interface. This approach allows the application to
come up at one frequency and then change or fine–tune the
clock as the ability to control the serial interface becomes
available.
1
1
1
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Figure 4. Timing Diagram
5
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
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ꢒ
ꢅꢗ ꢁ
ꢗ
ꢤ
ꢙ
ꢣ
ꢖ
ꢊ
ꢜ
ꢇ
ꢄ
ꢅ
ꢎ
ꢍ
ꢌ
ꢗ
ꢤ
ꢌꢑ ꢐ ꢌ
ꢅꢞ ꢋ
ꢘ
ꢞ
ꢌ
ꢌ
ꢠ
ꢤ
ꢌꢑ ꢐ ꢌ
ꢓ
ꢳ
ꢯ
ꢳ
ꢰ
ꢅ
ꢁ
ꢣ
ꢌ
ꢟ
ꢜ
ꢐ ꢤꢣ ꢒꢌ
ꢓ ꢑꢟ
ꢀꢊ ꢕꢢ ꢣꢌ
ꢐ
ꢎ
ꢘ
ꢍ
ꢙ
ꢐ
ꢙ
ꢍ
ꢌ
ꢍ
ꢔ
ꢎ
ꢘ
ꢍ
ꢙ
ꢢ
ꢌ
ꢌ
ꢌ
ꢄ
ꢀ
ꢜ
ꢙ
ꢑ
ꢗ
ꢘ
ꢙ
ꢑ
•ꢴ ꢌ ꢜꢵ ꢌ ꢀ ꢵꢀ ꢧ ꢌ ꢄ ꢵꢄ ꢭ ꢌꢳ ꢯ ꢰ ꢅ ꢫ ꢶꢳ ꢦ ꢔꢎ ꢎ ꢢ ꢷ ꢸ ꢱ ꢯꢯ ꢨ
•ꢴ ꢐꢗ ꢎ ꢘ ꢗ ꢚ ꢮ ꢯ ꢯ ꢳ ꢹꢳ ꢡ ꢰ ꢳ ꢶꢧ ꢅ ꢗ ꢁꢌ ꢠ ꢜ ꢮ ꢯ ꢫ ꢺ ꢌ ꢑ ꢐ ꢌ ꢫ ꢻ ꢰ ꢸ ꢻꢰ ꢧ ꢐ ꢗ ꢎ ꢘꢗ ꢚ ꢙ ꢣ ꢖ ꢣ ꢙ ꢑ ꢢ ꢼ ꢁ ꢮ ꢯ ꢫ ꢺ ꢒ ꢘ ꢞ ꢌ ꢸ ꢮ ꢺ
ꢔ
ꢎ
ꢘ
ꢍ
ꢙ
ꢢ
ꢱ
ꢡ
ꢰ
ꢯ
ꢱ
ꢯ
ꢬ
ꢳ
ꢯ
ꢳ
ꢰ
ꢽ
ꢫ
ꢬ
ꢰ
ꢳ
ꢯ
ꢰ
ꢸ
ꢮ
ꢺ
ꢹ
ꢱ
ꢰ
ꢡ
ꢾ
ꢪ
ꢲ
ꢾ
ꢳ
ꢺ
ꢹ
ꢱ
ꢰ
ꢡ
ꢾ
ꢬ
ꢳ
ꢯ
ꢳ
ꢰ
ꢌ
ꢜ
ꢶ
ꢱ
ꢰ
ꢱ
ꢮ
ꢯ
ꢯ
ꢾ
ꢮ
ꢽ
ꢰ
ꢳ
ꢶ
ꢫ
ꢻ
ꢰ
ꢌ
ꢑ
ꢐ
ꢌ
ꢸ
ꢮ
ꢺ
ꢪ
Figure 5. Serial Test Clock Block Diagram
DC CHARACTERISTICS (VCC = 3.3V 5%)
0°C
25°C
70°C
Symbol
Characteristic
Input HIGH Voltage
Min Typ Max Min Typ Max Min Typ Max Unit
Condition
V
2.2
2.2
2.5
2.2
2.5
V
V
IH
IL
V
Input LOW Voltage
Input Current
0.8
1.0
0.8
1.0
0.8
1.0
I
IN
mA
V
V
OH
V
OL
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
TEST 2.5
TEST
I
I
= –0.8mA
OH
0.4
0.4
0.4
2.565
1.70
V
= 0.8mA
OL
1.
1.
2.3.
FOUT, FOUT 2.28
FOUT, FOUT 1.35
2.60 2.32
1.67 1.35
2.49 2.38
1.67 1.35
V
V
= 3.3V
= 3.3V
CCO
CCO
2.3.
Output LOW Voltage
Power Supply Current
V
V
I
V
90
15
110
20
90
15
110
20
90
15
110
20
mA
CC
CC
CC
PLL_V
1. See applications information section for output level versus frequency information.
2. Output levels will vary 1:1 with V
variation.
CC0
3. 50 Ω to V – 2.0 V termination.
CC
DC CHARACTERISTICS (VCC = 5.0V 5%)
0°C
25°C
70°C
Symbol
Characteristic
Input HIGH Voltage
Min Typ Max Min Typ Max Min Typ Max Unit
Condition
V
3.5
3.5
3.5
V
V
IH
IL
V
Input LOW Voltage
Input Current
0.8
1.0
0.8
1.0
0.8
1.0
I
IN
mA
V
V
OH
V
OL
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
TEST 2.5
TEST
2.5
2.5
I
I
= –0.8 mA
OH
0.4
0.4
0.4
4.265
3.40
V
= 0.8 mA
OL
1.
1.
2.3.
FOUT, FOUT 3.98
FOUT, FOUT 3.05
4.30 4.02
3.37 3.05
4.19 4.08
3.37 3.05
V
V
= 5.0 V
= 5.0 V
CCO
CCO
2.3.
Output LOW Voltage
Power Supply Current
V
V
I
V
90
15
110
20
90
15
110
20
90
15
110
20
mA
CC
CC
CC
PLL_V
1. See applications information section for output level versus frequency information.
2. Output levels will vary 1:1 with V
variation.
CC0
3. 50 Ω to V – 2.0V termination.
CC
6
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V 5%)
Symbol
Characteristic
Maximum Input Frequency
Min
Max
Unit
Condition
F
S_CLOCK
Xtal Oscillator
FREF_EXT
10
20
Note 5.
MHz
Note 4.
Note 7.
MAXI
10
10
F
Maximum Output Frequency
Maximum PLL Lock Time
VCO (Internal)
FOUT
400
50
800
800
MHz
MAXO
t
t
10
ms
ps
LOCK
Period Deviation (Peak–to–Peak) Note 6.
25
65
N = 2, 4, 8; Note 7.
N = 1; Note 7.
jitter
t
s
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
t
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
ps
h
tpw
Minimum Pulse Width
Output Rise/Fall
S_LOAD
P_LOAD
50
50
MIN
t , t
r
FOUT
300
800
20%–80%; Note 7.
f
4. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test
clock in TEST_MODE 6.
5. Maximum frequency on FREF_EXT is a function of the internal M counter limitations. The phase detector can handle up to 100MHz on the input,
but the M counter must remain in the valid range of 200 ≤ M ≤ 400. See the Programming Interface section on page 4 of this data sheet for more
details.
6. See Applications Information below for additional information.
7. 50Ω to V – 2.0 V pull–down.
CC
APPLICATIONS INFORMATION
Using the On–Board Crystal Oscillator
hundred ppm lower than specified, a few hundred ppm
translates to kHz inaccuracies. In a general computer
application, this level of inaccuracy is immaterial. Table 1
below specifies the performance requirements of the crystals
to be used with the MC12430.
The MC12430 features a fully integrated on–board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is advised
to mount the crystal as close to the MC12430 as possible to
avoid any board level parasitics. To facilitate co–location
surface mount crystals are recommended, but not required.
1. Recommended Crystal Specifications
Parameter
Value
Fundamental AT Cut
Series Resonance*
75ppm at 25°C
150ppm 0 to 70°C
0 to 70°C
Crystal Cut
Resonance
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
The oscillator circuit is a series resonant circuit and thus for
optimum performance a series resonant crystal should be
used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the MC12430 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
Shunt Capacitance
5–7 pF
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
50 to 8 0Ω
100 µW
5 ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
7
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
Power Supply Filtering
voltage that must be maintained on the PLL_VCC pin, a low
DC resistance inductor is required (less than 15 Ω). Generally,
the resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering.
The MC12430 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen on
the power supply pins. The MC12430 provides separate
power supplies for the digital circuitry (VCC) and the internal
PLL (PLL_VCC) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the PLL_VCC pin for the MC12430.
The MC12430 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 7 shows a representative board layout for the
MC12430. There exists many different potential board layouts
and the one pictured is but one. The important aspect of the
layout in Figure 7 is the low impedance connections between
VCC and GND for the bypass capacitors. Combining good
quality general purpose chip capacitors with good PCB layout
techniques will produce effective capacitor resonances at
frequencies adequate to supply the instantaneous switching
current for the 12430 outputs. It is imperative that low
inductance chip capacitors are used; it is equally important
that the board layout does not introduce back all of the
inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors.
Figure 6 illustrates a typical power supply filter scheme.
The MC12430 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore, the filter should
be designed to target this range. The key parameter that
needs to be met in the final filter design is the DC voltage drop
that will be seen between the VCC supply and the PLL_VCC
pin of the MC12430. From the data sheet, the IPLL_VCC current
(the current sourced through the PLL_VCC pin) is typically
15mA (20mA maximum), assuming that a minimum of 3.0 V
must be maintained on the PLL_VCC pin, very little DC
voltage drop can be tolerated when a 3.3 V VCC supply is
used. The resistor shown in Figure 6 must have a resistance
of 10–15 Ω to meet the voltage drop criteria. The RC filter
pictured will provide a broadband filter with approximately
100:1 attenuation for noise whose spectral content is above
20KHz. As the noise frequency crosses the series resonant
point of an individual capacitor its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
ꢗꢀ
ꢗ ꢀ
ꢓꢀ
ꢀ
ꢗꢛ
ꢗ
ꢜ
ꢓꢀ
ꢗꢀ
ꢗꢜ
ꢗꢛ
ꢵ
ꢵ
ꢵ
ꢵ
ꢀ
ꢄ
ꢜ
ꢄ
ꢄꢕꢀ ꢉ Ω
ꢪ
ꢄ
ꢀ µ
ꢜµ
ꢀ µ
ꢒ
ꢒ
ꢛꢪ ꢛ ꢖ ꢫꢬ
ꢉꢪ ꢄ ꢖ
ꢪꢄ
ꢒ
ꢋ ꢰ ꢱꢹ
ꢵ
ꢖ
ꢗ ꢗ
ꢓ ꢵ ꢀꢄ ꢕꢀ ꢉ Ω
ꢐ
ꢵ
ꢟ
ꢁ
ꢱ
ꢙ
ꢔ
ꢎ
ꢎ
ꢏ
ꢖ
ꢗ
ꢗ
ꢗ
ꢵ ꢖꢮ
ꢜ
ꢜ
µ
ꢒ
ꢄ
ꢪ
ꢄ
ꢀ
µ
ꢒ
MC12430
Figure 7. PCB Board Layout for MC12430 (28 PLCC)
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals cross
under the crystal as crosstalk energy coupled to these lines
could significantly impact the jitter of the device. Special
attention should be paid to the layout of the crystal to ensure a
stable, jitter free interface between the crystal and the
on–board oscillator.
ꢖ
ꢗ
ꢄ
ꢪ
ꢄ
ꢀ
µ
ꢒ
Figure 6. Power Supply Filter
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. A 1000µH
choke will show a significant impedance at 10 KHz
frequencies and above. Because of the current draw and the
Although the MC12430 has several design features to
minimize the susceptibility to power supply noise (isolated
8
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
power and grounds and fully differential PLL), there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
importance. The flat line represents an RMS jitter value that
corresponds to an 8 sigma 25 ps peak–to–peak long term
period jitter. The graph shows that for output frequencies from
87.5 to 400 MHz the jitter falls within the 25 ps peak–to–peak
specification. The general trend is that as the output frequency
is decreased the output edge jitter will increase.
The jitter data from Figure 8 and Figure 9 do not include the
performance of the 12430 when the output is in the divide by 1
mode. In divide by one mode, the MC12430 output jitter
distribution is bimodal. Since a bimodal distribution cannot be
accurately represented with an rms value, peak–to–peak
values of jitter for the divide by one mode are presented.
Jitter Performance of the MC12430
The MC12430 exhibits long term and cycle–to–cycle jitter
which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility one gets with a
synthesizer over a fixed frequency oscillator.
ꢜ
ꢜ
ꢀ
ꢀ
ꢉ
ꢄ
ꢉ
ꢄ
ꢉ
ꢄ
Figure 10 shows the peak–to–peak jitter of the 12430
output in divide by one mode as a function of output frequency.
Notice that as with the other modes the jitter improves with
increasing frequency. The 65 ps shown in the data sheet
table represents a conservative value of jitter, especially for
the higher VCO, and thus output frequencies.
ꢁ
ꢁ
ꢁ
ꢵ
ꢵ
ꢵ
ꢜ
ꢊ
ꢆ
ꢀ ꢊꢄ
ꢀ ꢜꢄ
ꢀ ꢄꢄ
ꢆ ꢄ
ꢈ ꢄ
ꢊ ꢄ
ꢊ
ꢄꢄ
ꢉ
ꢄ
ꢄ
ꢈ
ꢄ
ꢄ
ꢇꢄ
ꢄ
ꢆ ꢄꢄ
ꢐ ꢸ ꢳ ꢡ ꢎ ꢮꣂꢮꢰ
ꢁꢵ ꢀ
ꢖ ꢗꢘ ꢒꢬꢳ ꢿꢻ ꢳꢺꢡꢷ ꢦꢅ ꢤꢥꢨ
Figure 8. RMS PLL Jitter versus VCO Frequency
Figure 8 illustrates the RMS jitter performance of the
MC12430 across its specified VCO frequency range. Note that
the jitter is a function of both the output frequency as well as
the VCO frequency, however the VCO frequency shows a
much stronger dependence. The data presented has not been
compensated for trigger jitter, this fact provides a measure of
guardband to the reported data.
ꢊ
ꢄꢄ
ꢉ
ꢄꢄ
ꢈ
ꢄꢄ
ꢇ
ꢄ
ꢄ
ꢆ
ꢄ
ꢄ
ꢘ ꢻ ꢰꢸ ꢻ ꢰ ꢒꢬ ꢳꢿ ꢻ ꢳꢺ ꢡꢷ ꢦ ꢅꢤꢥꢨ
Figure 10. Peak–to–Peak Jitter versus
Output Frequency
The typical method of measuring the jitter is to accumulate
a large number of cycles, create a histogram of the edge
placements and record peak–to–peak as well as standard
deviations of the jitter. Care must be taken that the measured
edge is the edge immediately following the trigger edge. The
oscilloscope cannot collect adjacent pulses, rather it collects
pulses from a very large sample of pulses.
The jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
ꢜ
ꢜ
ꢀ
ꢀ
ꢉ
ꢄ
ꢉ
ꢄ
ꢉ
ꢄ
Output Voltage Swing vs Frequency
In the divide by one mode, the output rise and fall times will
limit the peak to peak output voltage swing. For a 400 MHz
output, the peak to peak swing of the 12430 output will be
approximately 700 mV. This swing will gradually degrade as
the output frequency increases, at 800 MHz the output swing
will be reduced to approximately 500 mV. For a worst case
analysis, it would be safe to assume that the 12430 output will
always generate at least a 500mV output swing. Note that
most high speed ECL receivers require only a few hundred
millivolt input swings for reliable operation. As a result, the
output generated by the 12430 will, under all conditions, be
sufficient for clocking standard ECL devices. Note that if a
larger swing is required the MC12430 could drive a clock
fanout buffer like the MC100EP111.
ꢈ
ꢪ
ꢜ
ꢉ
ꢸ
ꢯ
ꢓ
ꢳ
ꢽ
ꢳ
ꢬ
ꢳ
ꢺ
ꢡ
ꢳ
ꢜ
ꢉ
ꢉ
ꢄ
ꢇ
ꢉ
ꢀ
ꢄ
ꢄ
ꢀ
ꢜ
ꢉ
ꢀ
ꢉ
ꢄ
ꢀ
ꢇ
ꢉ
ꢜ
ꢄ
ꢳ
ꢄ
ꢜ
ꢜ
ꢉ
ꢜ
ꢉ
ꢄ
ꢜ
ꢇ
ꢉ
ꢛ
ꢄ
ꢄ
ꢛ
ꢜ
ꢉ
ꢛ
ꢉ
ꢄ
ꢛ
ꢇ
ꢉ
ꢊ
ꢄ
ꢄ
ꢘ
ꢻ
ꢰ
ꢸꢻ
ꢰ
ꢒ
ꢬ
ꢿ
ꢻ
ꢳ
ꢺ
ꢡ
ꢷ
ꢦ
ꢅ
ꢤ
ꢥ
ꢨ
Figure 9. RMS Jitter versus Output Frequency
Figure 9 shows the jitter as a function of the output
frequency. For the 12430, this information is probably of more
9
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC12430
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
ꢅ
ꢐ
ꢐ
ꢄ
ꢪ
ꢄ
ꢄ
ꢇ
ꢦ
ꢄ
ꢪ
ꢀ
ꢆ
ꢄ
ꢨ
ꢦ
ꢌ
ꢎ
ꢕ
ꢅ
ꢁ
B
Z
Y BRK
D
ꢅ
ꢐ
ꢐ
ꢁ
–N
–
ꢄ
ꢪ
ꢄ
ꢄ
ꢇ
ꢄ
ꢪ
ꢀ
ꢆ
ꢄ
ꢨ
ꢌ
ꢎ
ꢕ
ꢅ
U
–L
–
–M
–
D
W
X
G1
ꢐ
ꢐ
ꢐ
ꢄ
ꢪ
ꢄꢀ
ꢄ
ꢦ
ꢄ
ꢪ
ꢜ
ꢉꢄ
ꢨ
ꢌ
ꢎ
ꢕꢅ
ꢁ
V
28
1
VIEW D–D
ꢅ
ꢅ
ꢐ
ꢐ
ꢐ
ꢄ
ꢄ
ꢪ
ꢪ
ꢄ
ꢄ
ꢄ
ꢄ
ꢇ
ꢇ
ꢦ
ꢦ
ꢄ
ꢪ
ꢀ
ꢀ
ꢆ
ꢆ
ꢄ
ꢄ
ꢨ
ꢨ
ꢌ
ꢌ
ꢎ
ꢎ
ꢕ
ꢕ
ꢅ
ꢅ
ꢁ
A
R
H
ꢅ
ꢐ
ꢐ
ꢁ
ꢄ
ꢪ
ꢄ
ꢄ
ꢇ
ꢦ
ꢄ
ꢪ
ꢀ
ꢆ
ꢄ
ꢨ
ꢌ
ꢎ
ꢕ
ꢅ
Z
ꢐ
ꢄ
ꢪ
ꢁ
K1
C
E
ꢄꢪ ꢄ ꢄꢊ ꢦ ꢄꢪ ꢀ ꢄꢄ ꢨ
SEATING
PLANE
G
K
–T
–
J
ꢅ
ꢐ
ꢐ
ꢁ
ꢄ
ꢪ
ꢄ
ꢄ
ꢇ
ꢦ
ꢄ
ꢪ
ꢀ
ꢆ
ꢄ
ꢨ
ꢌ
ꢎ
ꢕ
ꢅ
F
VIEW S
G1
VIEW S
ꢐ
ꢐ
ꢐ
ꢄ
ꢪ
ꢄ
ꢀ
ꢄ
ꢦ
ꢄ
ꢪ
ꢜ
ꢉ
ꢄ
ꢨ
ꢌ
ꢎ
ꢕ
ꢅ
ꢁ
ꢁ
ꢘ
ꢌ
ꢑ
ꢐ
ꢭ
ꢀ ꢪ ꢙ ꢍꢌꢞ ꢅ ꢐ ꢕꢎ ꢕꢧ ꢕꢅ ꢕꢧ ꢍꢁ ꢙ ꢕꢁ ꢕ ꢙ ꢑꢌ ꢑ ꢓ ꢅꢣꢁ ꢑ ꢙ
ꢲꢤ ꢑꢓ ꢑ ꢌ ꢘ ꢔ ꢘ ꢒ ꢎꢑ ꢍꢙ ꢐꢤ ꢘ ꢞ ꢎꢙ ꢑ ꢓ ꢑ ꢋꢣ ꢌꢐ
ꢔꢎ ꢍꢐꢌꢣꢗ ꢢꢘ ꢙ ꢼ ꢍ ꢌ ꢅ ꢘꢎ ꢙ ꢔꢍ ꢓꢌ ꢣꢁ ꢟ ꢎꢣ ꢁ ꢑꢪ
ꢜꢪ ꢙ ꢣꢅ ꢟ ꢀꢧ ꢌꢓ ꢞ ꢑ ꢔꢘ ꢐꢣꢌ ꢣꢘ ꢁ ꢌ ꢘ ꢢ ꢑ ꢅꢑ ꢍꢐ ꢞ ꢓ ꢑꢙ
ꢍꢌ ꢙ ꢍꢌꢞ ꢅ ꢕꢌ ꢕꢧ ꢐꢑꢍꢌꢣꢁ ꢟ ꢔ ꢎꢍꢁ ꢑ ꢪ
ꢛꢪ ꢙ ꢣꢅ ꢓ ꢍꢁ ꢙ ꢞ ꢙ ꢘ ꢁ ꢘ ꢌ ꢣꢁ ꢗ ꢎꢞ ꢙ ꢑ ꢅꢘ ꢎꢙ ꢒ ꢎꢍꢐ ꢤ ꢪ
ꢍꢎ ꢎꢘ ꢲꢍꢢꢎ ꢑ ꢅ ꢘꢎ ꢙ ꢒꢎ ꢍꢐꢤ ꢣ ꢐ ꢄꢪ ꢄꢀꢄ ꢦ ꢄꢪ ꢜꢉꢄ ꢨ
ꢔꢑꢓ ꢐꢣꢙ ꢑꢪ
INCHES
MIN MAX
MILLIMETERS
MIN MAX
DIM
A
ꢄꢪ ꢊꢆꢉ ꢄꢪ ꢊꢝꢉ ꢀꢜꢪ ꢛꢜ ꢀꢜꢪ ꢉꢇ
ꢄꢪ ꢊꢆꢉ ꢄꢪ ꢊꢝꢉ ꢀꢜꢪ ꢛꢜ ꢀꢜꢪ ꢉꢇ
ꢄꢪ ꢀꢈꢉ ꢄꢪ ꢀꢆꢄ
ꢄꢪ ꢄꢝꢄ ꢄꢪ ꢀꢀꢄ
ꢄꢪ ꢄꢀꢛ ꢄꢪ ꢄꢀꢝ
ꢄꢪ ꢄꢉꢄ ꢢ ꢐꢗ
B
ꢊꢪ ꢙ ꢣ ꢅꢑ ꢁꢐ ꢣ ꢘ ꢁꢣ ꢁ ꢟ ꢍꢁ ꢙ ꢌꢘ ꢎꢑ ꢓ ꢍꢁ ꢗ ꢣ ꢁ ꢟ ꢔ ꢑꢓ ꢍ ꢁ ꢐꢣ
ꢼꢀ ꢊꢪꢉ ꢅ ꢧ ꢀꢝ ꢆ ꢜꢪ
C
ꢊꢪ ꢜꢄ
ꢜꢪ ꢜꢝ
ꢄꢪ ꢛꢛ
ꢊꢪ ꢉꢇ
ꢜꢪ ꢇꢝ
ꢄꢪ ꢊꢆ
E
ꢉꢪ ꢗ ꢘꢁ ꢌ ꢓꢘ ꢎꢎꢣ ꢁ ꢟ ꢙ ꢣꢅ ꢑꢁ ꢐꢣꢘ ꢁ ꢭ ꢣ ꢁ ꢗꢤ ꢪ
ꢈꢪ ꢌ ꢤ ꢑ ꢔꢍꢗ ꢚꢍꢟ ꢑ ꢌ ꢘ ꢔ ꢅ ꢍꢼ ꢢ ꢑ ꢐ ꢅꢍꢎ ꢎꢑ ꢓ ꢌ ꢤ ꢍꢁ
ꢌꢤ ꢑ ꢔꢍꢗ ꢚꢍꢟ ꢑ ꢢꢘ ꢌꢌꢘ ꢅ ꢢꢼ ꢞ ꢔ ꢌꢘ ꢄꢪ ꢄꢀꢜ
ꢦ ꢄꢪ ꢛꢄ ꢄꢨ ꢪ ꢙ ꢣꢅ ꢑꢁ ꢐꢣꢘ ꢁ ꢐ ꢓ ꢍꢁꢙ ꢞ ꢍ ꢓ ꢑ
ꢙ ꢑꢌꢑꢓ ꢅ ꢣꢁ ꢑꢙ ꢍ ꢌ ꢌꢤ ꢑ ꢘ ꢞ ꢌꢑ ꢓ ꢅꢘ ꢐ ꢌ
ꢑꢋꢌ ꢓꢑ ꢅꢑꢐ ꢘ ꢒ ꢌꢤ ꢑ ꢔꢎ ꢍꢐꢌ ꢣꢗ ꢢ ꢘꢙ ꢼ
ꢑꢋꢗ ꢎ ꢞ ꢐꢣꢖꢑ ꢘ ꢒ ꢅ ꢘꢎ ꢙ ꢒꢎ ꢍꢐꢤ ꢧ ꢌ ꢣꢑ ꢢ ꢍꢓ
ꢢꢞ ꢓ ꢓ ꢐꢧ ꢟꢍ ꢌ ꢑ ꢢꢞ ꢓ ꢓ ꢐ ꢍꢁ ꢙ ꢣ ꢁ ꢌꢑ ꢓ ꢎꢑ ꢍꢙ
ꢒꢎ ꢍꢐꢤ ꢧ ꢢꢞ ꢌ ꢣꢁ ꢗ ꢎꢞ ꢙ ꢣꢁ ꢟ ꢍꢁ ꢼ ꢅꢣ ꢐꢅ ꢍꢌ ꢗ ꢤ
ꢢꢑꢌ ꢲꢑꢑꢁ ꢌꢤ ꢑ ꢌ ꢘ ꢔ ꢍꢁ ꢙ ꢢ ꢘꢌ ꢌꢘ ꢅ ꢘ ꢒ ꢌ ꢤ ꢑ
ꢔꢎ ꢍꢐꢌꢣꢗ ꢢꢘ ꢙ ꢼꢪ
ꢇ ꢪ ꢙꢣ ꢅ ꢑꢁ ꢐꢣ ꢘꢁ ꢤ ꢙ ꢘ ꢑꢐ ꢁ ꢘ ꢌ ꢣ ꢁ ꢗꢎ ꢞ ꢙ ꢑ ꢙ ꢍ ꢅꢢꢍ ꢓ
ꢔꢓ ꢘ ꢌꢓ ꢞ ꢐꢣꢘ ꢁ ꢘ ꢓ ꢣꢁ ꢌꢓ ꢞ ꢐꢣ ꢘ ꢁ ꢪ ꢌ ꢤ ꢑ ꢙ ꢍ ꢅꢢꢍ ꢓ
ꢔꢓ ꢘ ꢌꢓ ꢞ ꢐꢣꢘ ꢁ ꢦ ꢐꢨ ꢐꢤ ꢍꢎ ꢎ ꢁ ꢘꢌ ꢗ ꢍ ꢞꢐ ꢑ ꢌ ꢤ ꢑ ꢤ
ꢙ ꢣꢅ ꢑꢁ ꢐꢣꢘ ꢁ ꢌ ꢘ ꢢꢑ ꢟ ꢓ ꢑꢍꢌꢑꢓ ꢌ ꢤ ꢍꢁ ꢄꢪ ꢄꢛꢇ
ꢦ ꢄꢪ ꢝꢊ ꢄꢨ ꢪ ꢌꢤ ꢑ ꢙ ꢍꢅ ꢢꢍꢓ ꢣꢁ ꢌꢓ ꢞ ꢐ ꢣꢘ ꢁ ꢦ ꢐ ꢨ ꢐ ꢤꢍ ꢎꢎ
ꢁ ꢘ ꢌ ꢗ ꢍꢞ ꢐꢑ ꢌꢤ ꢑ ꢤ ꢙ ꢣꢅ ꢑꢁ ꢐꢣꢘ ꢁ ꢌꢘ ꢢ ꢑ
ꢐꢅ ꢍꢎꢎ ꢑꢓ ꢌꢤ ꢍꢁ ꢄꢪ ꢄꢜ ꢉ ꢦ ꢄꢪ ꢈꢛꢉ ꢨꢪ
F
G
H
ꢀ
ꢪ
ꢜ
ꢇ
ꢢ
ꢐ
ꢗ
ꢄ
ꢪ
ꢄ
ꢜ
ꢈ
ꢄ
ꢪ
ꢄ
ꢛ
ꢜ
ꢄꢪ ꢈꢈ
ꢄꢪ ꢉꢀ
ꢄꢪ ꢈꢊ
ꢄꢪ ꢆꢀ
꣄
꣄
J
ꢄꢪ ꢄꢜꢄ
ꢄꢪ ꢄꢜꢉ
꣄
꣄
K
R
ꢄꢪ ꢊꢉꢄ ꢄꢪ ꢊꢉꢈ ꢀꢀꢪ ꢊꢛ
ꢄꢪ ꢊꢉꢄ ꢄꢪ ꢊꢉꢈ ꢀꢀꢪ ꢊꢛ
ꢄꢪ ꢄꢊꢜ ꢄꢪ ꢄꢊꢆ
ꢄꢪ ꢄꢊꢜ ꢄꢪ ꢄꢊꢆ
ꢄꢪ ꢄꢊꢜ ꢄꢪ ꢄꢉꢈ
ꢀꢀꢪ ꢉꢆ
ꢀꢀꢪ ꢉꢆ
ꢀꢪ ꢜꢀ
ꢀꢪ ꢜꢀ
ꢀꢪ ꢊꢜ
ꢄꢪ ꢉꢄ
ꢀꢄ°
U
V
ꢀꢪ ꢄꢇ
ꢀꢪ ꢄꢇ
ꢀꢪ ꢄꢇ
꣄
W
X
Y
꣄
ꢜ°
ꢄꢪ ꢄꢜꢄ
ꢀꢄ°
Z
ꢜ
°
G1
K1
ꢄ
ꢪ
ꢊ
ꢀ
ꢄ
ꢄ
ꢪ
ꢊ
ꢛ
ꢄ
ꢀ
ꢄ
ꢪ
ꢊ
ꢜ
ꢀ
ꢄ
ꢪ
ꢝ
ꢜ
ꢄ
ꢪ
ꢄ
ꢊ
ꢄ
꣄
ꢴ
ꢀ
ꢪ
ꢄ
ꢜ
꣄
ꢴ
10
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OUTLINE DIMENSIONS
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A
A1
ꢄꢪ
ꢜꢄ
ꣀꢦ
ꢄ
ꢪ
ꢄ
ꢄ
ꢆ
ꢨ
ꢍ
ꢢ
ꢌꢕ
ꢞ
ꣅ
32
25
1
–U–
–T–
B
V
AE
AE
P
B1
DETAIL Y
V1
17
8
DETAIL Y
9
4X
–Z–
ꢄ
ꢪ
ꢜ
ꢄ
ꣀ
ꢦ
ꢄ
ꢪ
ꢄ
ꢄ
ꢆ
ꢨ
ꢍ
ꢗ
ꢌ
ꢕ
ꢞ
ꣅ
9
ꢁ ꢘ ꢌꢑ ꢐ ꢭ
ꢀ
S1
ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣ ꢘꢁ ꢣ ꢁ ꢟ ꢍ ꢁ ꢙ ꢌꢘ ꢎꢑ ꢓ ꢍꢁ ꢗ ꢣ ꢁ ꢟ ꢔ ꢑꢓ ꢍ ꢁꢐ ꢣ
ꢼ ꢀꢊꢪ ꢉꢅꢧ ꢀꢝꢆ ꢜꢪ
S
ꢜ
ꢛ
ꢗ ꢘ ꢁ ꢌꢓ ꢘ ꢎꢎ ꢣꢁ ꢟ ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣꢘ ꢁ ꢭ ꢅꢣ ꢎꢎꢣ ꢅꢑ ꢌꢑ ꢓ ꢪ
ꢙ ꢍꢌ ꢞ ꢅ ꢔ ꢎꢍꢁ ꢑ ꢕ ꢍꢢ ꢕ ꢣ ꢐ ꢎꢘ ꢗ ꢍꢌ ꢑꢙ ꢍ ꢌ ꢢ ꢘꢌ ꢌꢘ ꢅ ꢘ ꢒ
ꢎꢑ ꢍꢙ ꢍ ꢁꢙ ꢣ ꢐ ꢗ ꢘ ꢣꢁ ꢗ ꢣ ꢙ ꢑ ꢁꢌ ꢲꢣ ꢌꢤ ꢌ ꢤ ꢑ ꢎꢑ ꢍꢙ
ꢲꢤ ꢑ ꢓ ꢑ ꢌ ꢤ ꢑ ꢎꢑ ꢍꢙ ꢑ ꢋꢣ ꢌꢐ ꢌ ꢤ ꢑ ꢔ ꢎꢍꢐ ꢌ ꢣꢗ ꢢ ꢘꢙ ꢼ ꢍꢌ
ꢌ ꢤ ꢑ ꢢ ꢘꢌ ꢌꢘ ꢅ ꢘ ꢒ ꢌ ꢤ ꢑ ꢔꢍ ꢓꢌ ꢣꢁ ꢟ ꢎꢣ ꢁ ꢑꢪ
ꢙ ꢍꢌ ꢞ ꢅꢐ ꢕ ꢌꢕ ꢧ ꢕ ꢞ ꢕꢧ ꢍ ꢁ ꢙ ꢕ ꣅꢕ ꢌꢘ ꢢ ꢑ ꢙ ꢑ ꢌꢑ ꢓ ꢅꢣꢁ ꢑ ꢙ
ꢍ ꢌ ꢙ ꢍꢌ ꢞ ꢅ ꢔ ꢎꢍꢁ ꢑ ꢕ ꢍꢢ ꢕꢪ
DETAIL AD
ꢊ
ꢉ
ꢈ
G
ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣ ꢘꢁ ꢐ ꢐ ꢍ ꢁꢙ ꢖ ꢌꢘ ꢢ ꢑ ꢙ ꢑ ꢌꢑ ꢓ ꢅꢣꢁ ꢑ ꢙ ꢍ ꢌ
ꢐ ꢑꢍꢌ ꢣꢁ ꢟ ꢔ ꢎꢍꢁ ꢑ ꢕ ꢍꢗ ꢕ ꢪ
–AB–
–AC–
ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣꢘ ꢁ ꢐ ꢍ ꢍ ꢁꢙ ꢢ ꢙ ꢘ ꢁ ꢘ ꢌ ꢣ ꢁ ꢗꢎ ꢞ ꢙ ꢑ ꢅꢘ ꢎꢙ
ꢔ ꢓ ꢘꢌ ꢓ ꢞ ꢐꢣ ꢘ ꢁ ꢪ ꢍ ꢎꢎꢘ ꢲꢍ ꢢꢎꢑ ꢔ ꢓꢘ ꢌ ꢓ ꢞ ꢐꢣ ꢘ ꢁ ꢣ ꢐ
ꢄꢪ ꢜꢉꢄ ꢦ ꢄꢪ ꢄꢀꢄ ꢨ ꢔ ꢑꢓ ꢐ ꢣꢙ ꢑ ꢪ ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣꢘ ꢁ ꢐ ꢍ ꢍ ꢁꢙ ꢢ
ꢙ ꢘ ꢣ ꢁ ꢗꢎ ꢞ ꢙ ꢑ ꢅꢘ ꢎꢙ ꢅꢣ ꢐꢅ ꢍꢌ ꢗ ꢤ ꢍ ꢁ ꢙ ꢍ ꢓꢑ
ꢙ ꢑ ꢌꢑ ꢓ ꢅꢣꢁ ꢑ ꢙ ꢍ ꢌ ꢙ ꢍꢌ ꢞ ꢅ ꢔ ꢎꢍꢁ ꢑ ꢕ ꢍꢢ ꢕ ꢪ
ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣꢘ ꢁ ꢙ ꢙ ꢘ ꢑꢐ ꢁ ꢘ ꢌ ꢣ ꢁ ꢗꢎ ꢞ ꢙ ꢑ ꢙ ꢍꢅ ꢢꢍ ꢓ
ꢔ ꢓꢘ ꢌ ꢓ ꢞ ꢐꢣ ꢘ ꢁ ꢪ ꢙ ꢍ ꢅꢢꢍ ꢓ ꢔ ꢓ ꢘꢌ ꢓ ꢞ ꢐꢣ ꢘ ꢁ ꢐ ꢤꢍ ꢎꢎ
ꢁ ꢘ ꢌ ꢗ ꢍ ꢞꢐ ꢑ ꢌ ꢤ ꢑ ꢙ ꢙ ꢣ ꢅꢑꢁ ꢐ ꢣ ꢘꢁ ꢌꢘ ꢑ ꢋꢗ ꢑ ꢑꢙ
ꢄꢪ ꢉꢜꢄ ꢦ ꢄꢪ ꢄꢜꢄ ꢨꢪ
SEATING
PLANE
ꢄ
ꢪ
ꢀ
ꢄ
ꣀ
ꢦ
ꢄ
ꢪ
ꢄ
ꢄ
ꢊ
ꢨ
ꢍ
ꢗ
BASE
METAL
ꢇ
N
ꢆ
ꢝ
ꢅꢣ ꢁ ꢣꢅ ꢞ ꢅ ꢐ ꢘꢎ ꢙ ꢑꢓ ꢔ ꢎꢍꢌ ꢑ ꢌ ꢤ ꢣꢗ ꢚ ꢁ ꢑꢐ ꢐ ꢐ ꢤꢍ ꢎꢎ ꢢꢑ
ꢄꢪ ꢄꢄꢇ ꢈ ꢦ ꢄꢪ ꢄꢄꢄ ꢛꢨ ꢪ
ꢑ ꢋꢍ ꢗ ꢌ ꢐ ꢤ ꢍꢔ ꢑ ꢘ ꢒ ꢑ ꢍꢗ ꢤ ꢗ ꢘ ꢓ ꢁ ꢑꢓ ꢅꢍꢼ ꢖ ꢍ ꢓ ꢼ
ꢒ ꢓ ꢘꢅ ꢙ ꢑꢔ ꢣ ꢗ ꢌꢣ ꢘ ꢁ ꢪ
F
D
ꢁ
8X M
MILLIMETERS
DIM MIN MAX
ꢇꢪ ꢄꢄꢄ ꣀꢢ ꢐꢗ
INCHES
MIN MAX
R
J
A
A1
B
ꢄꢪ ꢜꢇꢈ ꣀꢢ ꢐꢗ
ꢄꢪ ꢀꢛꢆ ꣀꢢ ꢐꢗ
ꢄꢪ ꢜꢇꢈ ꣀꢢ ꢐꢗ
ꢄꢪ ꢀꢛꢆ ꣀꢢ ꢐꢗ
ꢛꢪ ꢉꢄꢄ ꣀꢢ ꢐꢗ
ꢇꢪ ꢄꢄꢄ ꣀꢢ ꢐꢗ
ꢛꢪ ꢉꢄꢄ ꣀꢢ ꢐꢗ
SECTION AE–AE
E
C
B1
C
ꢀ
ꢪ
ꢊ
ꢄ
ꢄ
ꢀꢪ ꢈꢄꢄ
ꢄꢪ ꢊꢉꢄ
ꢀꢪ ꢊꢉꢄ
ꢄꢪ ꢊꢄꢄ
ꢄ
ꢪ
ꢄ
ꢉ
ꢉ
ꢄꢪ ꢄꢈꢛ
ꢄꢪ ꢄꢀꢆ
ꢄꢪ ꢄꢉꢇ
ꢄꢪ ꢄꢀꢈ
D
ꢄꢪ ꢛꢄꢄ
ꢀꢪ ꢛꢉꢄ
ꢄꢪ ꢛꢄꢄ
ꢄꢪ ꢄꢀꢜ
ꢄꢪ ꢄꢉꢛ
ꢄꢪ ꢄꢀꢜ
E
F
W
G
H
ꢄ
ꢪ
ꢆ
ꢄ
ꢄ
ꣀ
ꢢ
ꢐ
ꢗ
ꢄ
ꢪ
ꢄ
ꢛ
ꢀ
ꣀ
ꢢ
ꢐ
ꢗ
ꢁ
Q
H
K
ꢄꢪ ꢄꢉꢄ
ꢄꢪ ꢄꢝꢄ
ꢄꢪ ꢉꢄꢄ
ꢄꢪ ꢀꢉꢄ
ꢄꢪ ꢜꢄꢄ
ꢄꢪ ꢇꢄꢄ
ꢄꢪ ꢄꢄꢜ
ꢄꢪ ꢄꢄꢊ
ꢄꢪ ꢄꢜꢄ
ꢄꢪ ꢄꢄꢈ
ꢄꢪ ꢄꢄꢆ
ꢄꢪ ꢄꢜꢆ
J
X
K
ꢁ
ꢁ
M
N
ꢀꢜꣀ ꣀ ꣀꢓ ꢑ ꢒ
ꢄꢪ ꢄꢝꢄ ꢄꢪ ꢀꢈꢄ
ꢄꢪ ꢊꢄꢄ ꣀꢢ ꢐꢗ
ꢀꢜꣀ ꣀ ꣀꢓ ꢑ ꢒ
ꢄꢪ ꢄꢄꢊ ꢄꢪ ꢄꢄꢈ
ꢄꢪ ꢄꢀꢈ ꣀꢢ ꢐꢗ
DETAIL AD
P
Q
R
ꢀꢁꣀ ꣀ
ꢄꢪ ꢀꢉꢄ
ꢉꣀꢁꣀ
ꢄꢪ ꢜꢉꢄ
ꢀꢁꣀ ꣀ
ꢄꢪ ꢄꢄꢈ
ꢉꣀꢁꣀ
ꢄꢪ ꢄꢀꢄ
S
ꢝ
ꢪ
ꢄ
ꢄ
ꢄ
ꣀ
ꢢ
ꢐ
ꢗ
ꢄ
ꢪ
ꢛ
ꢉ
ꢊ
ꣀ
ꢢ
ꢐ
ꢗ
S1
V
ꢊꢪ ꢉꢄꢄ ꣀꢢ ꢐꢗ
ꢝꢪ ꢄꢄꢄ ꣀꢢ ꢐꢗ
ꢊꢪ ꢉꢄꢄ ꣀꢢ ꢐꢗ
ꢄꢪ ꢜꢄꢄ ꣀꢓ ꢑ ꢒ
ꢀꢪ ꢄꢄꢄ ꣀꢓ ꢑ ꢒ
ꢄꢪ ꢀꢇꢇ ꣀꢢ ꢐꢗ
ꢄꢪ ꢛꢉꢊ ꣀꢢ ꢐꢗ
ꢄꢪ ꢀꢇꢇ ꣀꢢ ꢐꢗ
ꢄꢪ ꢄꢄꢆ ꣀꢓ ꢑ ꢒ
ꢄꢪ ꢄꢛꢝ ꣀꢓ ꢑ ꢒ
V1
W
X
11
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MC12430
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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