MC13193FCR2 [NXP]
IC,RF MODULATOR/DEMODULATOR,BICMOS,LLCC,32PIN,PLASTIC;
| 型号： | MC13193FCR2 |
| 厂家： | 
NXP |
| 描述： | IC,RF MODULATOR/DEMODULATOR,BICMOS,LLCC,32PIN,PLASTIC 信息通信管理 |
| 文件： | 总22页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC13192/D
Rev. 2.7, 12/2004
Freescale Semiconductor
Technical Data
MC13192/MC13193
(Scale 1:1)
Package Information
Plastic Package
Case 1311-03
(QFN-32)
MC13192/MC13193
2.4 GHz Low Power Transceiver
Ordering Information
for the IEEE® 802.15.4 Standard
Device
Device Marking
Package
MC13192
MC13193
13192
13193
QFN-32
QFN-32
Contents
1 Introduction
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 3
4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 3
5 Electrical Characteristics . . . . . . . . . . . . . . . 8
6 Functional Description . . . . . . . . . . . . . . . . 11
7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14
8 Applications Information . . . . . . . . . . . . . . . 17
9 Packaging Information . . . . . . . . . . . . . . . . . 21
The MC13192 and MC13193 are short range, low
power, 2.4 GHz Industrial, Scientific, and Medical
(ISM) band transceivers. The MC13192/MC13193
contain a complete 802.15.4 physical layer (PHY)
modem designed for the IEEE 802.15.4 wireless
standard which supports peer-to-peer, star, and mesh
networking.
®
The MC13192 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13193 also
includes the 802.15.4 PHY/MAC plus the ZigBee
Protocol Stack for use with the HCS08 Family of MCUs.
With the exception of the addition of the ZigBee Protocol
Stack, the MC13193 functionality is the same as the
MC13192.
When combined with an appropriate microcontroller
(MCU), the MC13192/MC13193 provide a
cost-effective solution for short-range data links and
networks. Interface with the MCU is accomplished using
a four wire serial peripheral interface (SPI) connection
and an interrupt request output which allows for the use
of a variety of processors. The software and processor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Features
can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee™
networking.
For more detailed information about MC13192/MC13192 operation, refer to the MC13192/MC13193
Reference Manual, part number MC13192RM/D.
Applications include, but are not limited to, the following:
•
•
•
•
Remote control and wire replacement in industrial systems such as wireless sensor networks
Factory automation and motor control
Energy Management (lighting, HVAC, etc.)
Asset tracking and monitoring
Potential consumer applications include:
•
•
•
•
Home automation and control (lighting, thermostats, etc.)
Human interface devices (keyboard, mice, etc.)
Remote entertainment control
Wireless toys
The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator
(VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device
supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with
5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output
are used for receive (RX) and transmit (TX) data transfer and control.
2 Features
•
•
•
•
•
Recommended power supply range: 2.0 to 3.4 V
16 Channels
0 dBm nominal, programmable up to 4 dBm typical maximum output power
Buffered transmit and receive data packets for simplified use with low cost MCUs
Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode
(compatible with IEEE Standard 802.15.4)
•
Three power down modes for power conservation:
— < 1 µA Off current
— 2.3 µA Typical Hibernate current
— 35 µA Typical Doze current (no CLKO)
•
•
•
•
•
RX sensitivity of -92 dBm (typical) at 1.0% packet error rate
Four internal timer comparators available to reduce MCU resource requirements
Programmable frequency clock output for use by MCU
Seven general purpose input/output (GPIO) signals
Operating temperature range: -40 °C to 85 °C
MC13192/MC13193 Technical Data, Rev. 2.7
2
Freescale Semiconductor
Block Diagrams
•
Small form factor QFN-32 Package
— Meets moisture sensitivity level (MSL) 3
— 260 °C peak reflow temperature
— Meets lead-free requirements
3 Block Diagrams
Figure 3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard
802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY)
specification. Figure 4 shows the basic system block diagram for the MC13192/MC13193 in an
application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request
line. The media access control (MAC), drivers, and network and application software (as required) reside
on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor
depending on application requirements.
4 Data Transfer Modes
The MC13192/MC13193 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1 Packet Structure
Figure 5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported.
The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
3
Data Transfer Modes
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is
notified that an entire packet has been received via an interrupt.
If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word
basis.
Figure 1 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure 2 shows
energy detection/LQI reported level versus input power. Note that for both graphs the required IEEE
802.15.4 Standard accuracy and range limits are shown.
-50
-60
-70
-80
802.15.4 Accuracy
and range Requirements
-90
-100
-90
-80
-70
-60
-50
Input Pow er (dBm)
Figure 1. Reported Power Level versus Input Power in Clear Channel Assessment Mode
MC13192/MC13193 Technical Data, Rev. 2.7
4
Freescale Semiconductor
Data Transfer Modes
-25
-35
-45
-55
-65
-75
-85
802.15.4 Accuracy
and Range Requirements
-85
-75
-65
-55
-45
-35
-25
-15
Input Power Level (dBm)
Figure 2. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
5
Data Transfer Modes
4.3 Transmit Path Description
For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX
data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then
up-converted to the transmit frequency.
If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is
notified via an interrupt when the whole packet has successfully been transmitted.
In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt
serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the
whole packet is transmitted.
VDDA
Analog
Dec im ation Baseband M atc hed
F ilter M ix er F ilter
R egulator
VBAT T
2nd IF M ix er
IF = 1 M Hz PM A
1st IF M ix er
IF 65 M Hz
Pow er-U p
C ontrol
Logic
Digital
R egulator
VDDIN T
=
LN A
L
R F IN +
R F IN -
Pack et
Proc es sor
DC D
C C A
Digital
R egulator
VDDD
H
C ry stal
R egulator
VC O
R egulator
VDDVC O
R XT XEN
R eceiv e
Pack et R AM
R ec eiv e R AM
Arbiter
AGC
Sequenc e
M anager
(C ontrol Logic )
Program m able
Presc aler
÷ 4
24 Bit Ev ent T im er
V DDLO2
256 M Hz
C E
M OSI
M ISO
SPIC LK
4
Program m able
T im er C om parators
AT T N
R ST
Crystal
Oscillator
XT AL1
XT AL2
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
16 M Hz
T rans m it
Pac ket R AM
Sy nthesizer
2
1
T rans m it
Pac ket R AM
2.45 GHz
V CO
VDDLO1
IR Q
Arbiter
T rans m it R AM
Arbiter
Sy m bol
Generation
IR Q
C LKO
PAO+
PAO-
PA
Phase Shift M odulator
F C S
Header
Generation
Generation
Figure 3. MC13192 Simplified Block Diagram
MC13192/MC13193 Technical Data, Rev. 2.7
6
Freescale Semiconductor
Data Transfer Modes
MC13192/MC13193
Microcontroller
ROM
(Flash)
Control
Logic
SPI
and GPIO
Analog Receiver
SPI
RAM
Frequency
Generation
CPU
Application
A/D
Analog
Transmitter
Network
MAC
Voltage
Regulators
Power Up
Management
Buffer RAM
PHY Driver
Figure 4. System Level Block Diagram
4 bytes
1 byte
SFD
1 byte
FLI
125 bytes maximum
Payload Data
2 bytes
FCS
Preamble
Figure 5. MC13192/MC13193 Packet Structure
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
7
Electrical Characteristics
5 Electrical Characteristics
5.1 Maximum Ratings
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Power Supply Voltage
RF Input Power
VBATT, VDDINT
3.6
TBD
Vdc
dBm
°C
Pmax
TJ
Junction Temperature
Storage Temperature Range
125
Tstg
-55 to 125
°C
Note: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
or Recommended Operating Conditions tables.
Note: Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN± = 100 V MM,
PAO± = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection.
5.2 Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (VBATT = VDDINT
)
VBATT,
2.0
2.7
3.4
Vdc
VDDINT
Input Frequency
fin
TA
VIL
2.405
-40
0
-
25
-
2.480
85
GHz
°C
Ambient Temperature Range
Logic Input Voltage Low
30%
V
VDDINT
Logic Input Voltage High
VIH
70%
-
VDDINT
V
VDDINT
SPI Clock Rate
RF Input Power
fSPI
Pmax
fref
-
-
-
-
8.0
10
MHz
dBm
Crystal Reference Oscillator Frequency (±40 ppm over
operating conditions to meet the 802.15.4 standard.)
16 MHz Only
MC13192/MC13193 Technical Data, Rev. 2.7
8
Freescale Semiconductor
Electrical Characteristics
5.3 DC Electrical Characteristics
Table 3. DC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 °C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Power Supply Current (VBATT + VDDINT
)
Off
-
-
-
-
-
-
0.2
2.3
35
500
30
1.0
-
-
800
35
42
µA
µA
µA
µA
mA
mA
Ileakage
ICCH
ICCD
ICCI
ICCT
ICCR
Hibernate
Doze (No CLKO)
Idle
Transmit Mode
Receive Mode
37
Input Current (VIN = 0 V or VDDINT) (All digital inputs)
Input Low Voltage (All digital inputs)
IIN
-
-
-
±1
µA
VIL
0
30%
V
VDDINT
Input High Voltage (all digital inputs)
VIH
VOH
VOL
70%
VDDINT
-
-
-
VDDINT
V
V
V
Output High Voltage (IOH = -1 mA) (All digital outputs)
Output Low Voltage (IOL = 1 mA) (All digital outputs)
80%
VDDINT
VDDINT
0
20%
VDDINT
5.4 AC Electrical Characteristics
Table 4. Receiver AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C)
Sensitivity for 1% Packet Error Rate (PER) (+25 °C)
Saturation (maximum input level)
SENSper
-
-
-92
-92
10
-
dBm
dBm
dBm
dB
-87
SENSmax
0
0
Adjacent Channel Interference for 1% PER
(desired signal -82 dBm)
23
-
-
Alternate Channel Interference for 1% PER
(desired signal -82 dBm)
0
35
dB
Frequency Error Tolerance (total)
Symbol Rate Error Tolerance
± 100
± 40
± 175
± 70
-
-
kHz
ppm
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
9
Electrical Characteristics
Table 5. Transmitter AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Power Spectral Density (-40 to +85 °C) Absolute limit
Power Spectral Density (-40 to +85 °C) Relative limit
-
-47
40
0
-30
-
dBm
20
-3
Nominal Output Power
Pout
3
dBm
(2405-2480 MHz with Register 12 set to {[default],BC})
Error Vector Magnitude
Power Control Range (10dB steps)
Over the Air Data Rate
Spurious Emissions
2nd Harmonic
EVM
-
-
-
-
-
-
20
20
35
%
-
dB
250
-56
-42
-44
-
-40
-
kbps
dBm
dBc
dBc
3rd Harmonic
-
MC13192/MC13193 Technical Data, Rev. 2.7
10
Freescale Semiconductor
Functional Description
6 Functional Description
6.1 MC13192/MC13193 Operational Modes
The MC13192/MC13193 has a number of operational modes that allow for low-current operation.
Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is
used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are
summarized, along with the transition times, in Table 6. Current drain in the various modes is listed in
Table 3, DC Electrical Characteristics.
Table 6. MC13192/MC13193 Mode Definitions and Transition Times
Transition Time
To or From Idle
Mode
Definition
Off
All IC functions Off, Leakage only. RST asserted. Digital outputs are
tri-stated including IRQ
25 ms to Idle
Hibernate
Doze
Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to
ATTN. Data is retained.
20 ms to Idle
Crystal Reference Oscillator On but CLKO output available only if Register (300 + 1/CLKO) µs
7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to Idle
to ATTN and can be programmed to enter Idle Mode through an internal
timer comparator.
Idle
Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive
Transmit
Crystal Reference Oscillator On. Receiver On.
Crystal Reference Oscillator On. Transmitter On.
144 µs from Idle
144 µs from Idle
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13192/MC13193, checks its status, and reads/writes data to the
device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction
between the host and the MC13192/MC13193 occurs as multiple 8-bit bursts on the SPI. The SPI signals
are:
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192/MC13193. Data is
clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and
data out changes state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
11
Functional Description
4. Master In/Slave Out (MISO) - The MC13192/MC13193 presents data to the master on the MISO
output.
A typical interconnection to a microcontroller is shown in Figure 6.
MCU
MC13192/MC13193
Shift Register
RxD
TxD
MISO
MOSI
Shift Register
Sclk
SPICLK
CE
Baud Rate
Generator
Chip Enable (CE)
Figure 6. SPI Interface
Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock
(CLK ), derived from the crystal reference oscillator, to communicate from the SPI registers to internal
core
registers and memory.
6.2.1
SPI Burst Operation
The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master
(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the
master on the MISO line. Although an MC13192/MC13193 transaction is three or more SPI bursts long,
the timing of a single SPI burst is shown in Figure 7.
SPI Burst
CE
1
2
3
4
5
6
7
8
SPICLK
T4
Valid
T3
T2
T6
T7
Valid
Valid
T1
T5
T0
MISO
MOSI
Figure 7. SPI Single Burst Timing Diagram
MC13192/MC13193 Technical Data, Rev. 2.7
12
Freescale Semiconductor
Functional Description
Table 7. SPI Timing Specifications
Symbol
Parameter
Min
Typ
Max
Unit
T0
T1
T2
T3
SPICLK period
125
62.5
62.5
ns
ns
ns
ns
Pulse width, SPICLK low
Pulse width, SPICLK high
Delay time, MISO data valid from falling
SPICLK
15
T4
T5
T6
T7
Setup time, CE low to rising SPICLK
Delay time, MISO valid from CE low
Setup time, MOSI valid to rising SPICLK
Hold time, MOSI valid from rising SPICLK
15
15
15
15
ns
ns
ns
ns
6.2.2 SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192/MC13193 requires that
a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The
assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to
the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the
MC13192/MC13193 and a read is data written to the SPI master. The following SPI bursts will be either
the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the
MC13192/MC13193 never uses this mode. The number of data bytes (payload) will be a minimum of 2
bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is
negated to high to signal the end of the transaction. Refer to the MC13192/MC13193 Reference Manual,
part number MC13192RM/D for more details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in Figure 8.
CE
Clock Burst
SPICLK
MISO
MOSI
Valid
Valid
Valid
Header
Read data
Figure 8. SPI Read Transaction Diagram
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
13
Pin Connections
7 Pin Connections
Table 8. Pin Function Description
Description
Pin #
Pin Name
RFIN-
Type
Functionality
1
2
3
4
5
RF Input
RF Input
LNA negative differential input.
LNA positive differential input.
Tie to Ground.
RFIN+
Not Used
Not Used
PAO+
Tie to Ground.
RF Output /DC Input Power Amplifier Positive Output. Open
drain. Connect to VDDA
.
6
PAO-
RF Output/DC Input Power Amplifier Negative Output. Open
drain. Connect to VDDA
.
7
8
Not used
GPIO4
GPIO3
GPIO2
Tie to Ground.
Digital Input/ Output General Purpose Input/Output 4.
Digital Input/ Output General Purpose Input/Output 3.
9
10
Digital Input/ Output General Purpose Input/Output 2. When
gpio_alt_en, Register 9, Bit 7 = 1, GPIO2
functions as a “CRC Valid” indicator.
11
12
GPIO1
RST
Digital Input/ Output General Purpose Input/Output 1. When
gpio_alt_en, Register 9, Bit 7 = 1, GPIO1
functions as an “Out of Idle” indicator.
Digital Input
Active Low Reset. While held low, the IC
is in Off Mode and all internal information
is lost from RAM and SPI registers.
When high, IC goes to IDLE Mode, with
SPI in default state.
13
RXTXEN
Digital Input
Active High. Low to high transition
initiates RX or TX sequence depending
on SPI setting. If held high (e.g., tied to
VDDINT), SPI programming starts RX or
TX sequence. When held low, forces Idle
Mode.
14
15
ATTN
CLKO
Digital Input
Active Low Attention. Transitions IC from
either Hibernate or Doze Modes to Idle.
Digital Output
Clock output to host MCU.
Programmable frequencies of:
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz,
62.5 kHz, 32.786+ kHz (default),
and 16.393+ kHz.
16
17
SPICLK
MOSI
Digital Clock Input
Digital Input
External clock input for the SPI interface.
Master Out/Slave In. Dedicated SPI data
input.
18
MISO
Digital Output
Master In/Slave Out. Dedicated SPI data
output.
MC13192/MC13193 Technical Data, Rev. 2.7
14
Freescale Semiconductor
Pin Connections
Table 8. Pin Function Description (continued)
Pin #
Pin Name
CE
Type
Description
Functionality
19
Digital Input
Active Low Chip Enable. Enables SPI
transfers.
20
IRQ
Digital Output
Active Low Interrupt Request.
Open drain device.
Programmable 40 kΩ internal
pull-up.
Interrupt can be serviced every
6 µs with <20 pF load.
Optional external pull-up must
be >4 kΩ.
21
22
VDDD
Power Output
Power Input
Digital regulated supply bypass.
Decouple to ground.
VDDINT
Digital interface supply & digital regulator 2.0 to 3.4 V. Decouple to
input. Connect to Battery.
ground.
23
24
25
26
GPIO5
GPIO6
GPIO7
XTAL1
Digital Input/Output General Purpose Input/Output 5.
Digital Input/Output General Purpose Input/Output 6.
Digital Input/Output General Purpose Input/Output 7.
Input
Crystal Reference oscillator input.
Connect to 16 MHz crystal and
load capacitor.
27
XTAL2
Input/Output
Crystal Reference oscillator output
Connect to 16 MHz crystal and
Note: Do not load this pin by using it as load capacitor.
a 16 MHz source. Measure 16 MHz
output at Pin 15, CLKO, programmed for
16 MHz. See the MC13192/MC13193
Reference Manual for details.
28
29
VDDLO2
VDDLO1
Power Input
Power Input
LO2 VDD supply. Connect to VDDA
externally.
LO1 VDD supply. Connect to VDDA
externally.
30
31
VDDVCO
VBATT
Power Output
Power Input
VCO regulated supply bypass.
Decouple to ground.
Analog voltage regulators Input. Connect Decouple to ground.
to Battery.
32
VDDA
Power Output
Analog regulated supply Output.
Connect to directly VDDLO1 and
VDDLO2 externally and to PAO± through
a frequency trap.
Decouple to ground.
Connect to ground.
EP
Ground
External paddle / flag ground.
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
15
Pin Connections
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
RFIN-
GPIO6
GPIO5
VDDINT
VDDD
IRQ
RFIN+
NC
NC
EP
PAO+
PAO-
NC
MC13192/
MC13193
CE
MISO
MOSI
GPIO4
9
10 11 12 13 14 15 16
Figure 9. Pin Connections (Top View)
MC13192/MC13193 Technical Data, Rev. 2.7
16
Freescale Semiconductor
Applications Information
8 Applications Information
8.1 Crystal Oscillator Reference Frequency
The IEEE 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy.
This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable
performance. The primary determining factor in meeting this specification is the tolerance of the crystal
oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal
specification will quantify each of them:
1. The initial (or make) tolerance of the crystal resonant frequency itself.
2. The variation of the crystal resonant frequency with temperature.
3. The variation of the crystal resonant frequency with time, also commonly known as aging.
4. The variation of the crystal resonant frequency with load capacitance, also commonly known as
pulling. This is affected by:
a) The external load capacitor values - initial tolerance and variation with temperature.
b) The internal trim capacitor values - initial tolerance and variation with temperature.
c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package
capacitance and stray board capacitance; and its initial tolerance and variation with
temperature.
Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. The
MC13192/MC13193 does not contain a reference divider, so 16 MHz is the only frequency that can be
used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier
circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that
total external capacitance seen across the two terminals of the crystal. The oscillator amplifier
configuration used in the MC13192/MC13193 requires two balanced load capacitors from each terminal
of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be
<18 pF for proper loading.
In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with
a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray
capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance
was determined empirically assuming the default internal trim capacitor value and for a specific board
layout. A different board layout may require a different external load capacitor value. The on-chip trim
capability may be used to determine the closest standard value by adjusting the trim value via the SPI and
observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately
± 2.5 pF in 20 µF steps.
Initial tolerance for the internal trim capacitance is approximately ±15%.
Since the MC13192/MC13193 contains an on-chip reference frequency trim capability, it is possible to
trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a
board-by-board basis.
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
17
Applications Information
A tolerance analysis budget may be created using all the previously stated factors. It is an engineering
judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if
the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging
factor is usually specified in ppm/year and the product designer can determine how many years are to be
assumed for the product lifetime. Taking all of the factors into account, the product designer can determine
the needed specifications for the crystal and external load capacitors to meet the IEEE 802.15.4
specification.
8.2 Design Example
Figure 10 shows a basic application schematic for interfacing the MC13192/MC13193 with an MCU.
Table 9 lists the Bill of Materials (BOM).
The MC13192/MC13193 has differential RF inputs and outputs that are well suited to balanced printed
wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna,
or other single-ended structures can be used with commercially available chip baluns or microstrip
equivalents. PAO+ and PAO- require connection to VDDA, the analog regulator output. This is
accomplished through the baluns in the referenced design.
The 16 MHz crystal should be mounted close to the MC13192/MC13193 because the crystal trim default
assumes that the listed KDS Daishinku crystal (see Table 10) and the 6.8 pF load capacitors shown are
used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of
9 pF or less. Bypassing capacitors are critical and should be placed close to the device. Unused pins should
be grounded as shown.
The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency
of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is
programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven
by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter
approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line
wakes up the MC13192/MC13193. RXTXEN can be used to initiate receive or transmit sequences under
MCU control. In this case, RXTXEN must be controlled by an MCU GPIO with the connection shown.
Otherwise, RXTXEN is held high and receive or transmit sequences are initiated by an SPI command.
Device reset (RST) is controlled through a connection to an MCU GPIO.
When the MC13192/MC13193 is used in Stream Mode, as with 802.15.4 MAC/PHY software, the
MC13192/MC13193 GPIO1 functions as an “Out of Idle” indicator and GPIO2 functions as a “CRC
Valid”, Clear Channel Assessment (CCA) result indicator and are not available for general purpose use.
MC13192/MC13193 Technical Data, Rev. 2.7
18
Freescale Semiconductor
Applications Information
1
Figure 10. MC13192/MC13193 Configured With an MCU
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
19
Applications Information
Table 9. MC13192/MC13193 to MCU Bill of Materials (BOM)
Item
Quantity
Reference
Part
Manufacturer
1
2
3
4
5
1
1
3
2
5
ANT1
C1
F_Antenna
1 µF
Printed wire
C2, C3, C4
C5, C6
220 nF
6.8 pF
10 pF
C7, C8, C9, C10,
C11
6
7
8
9
1
1
1
1
C12
IC1
IC2
J1
0.5 pF
MC13192/MC13193
µPG2012TK-E2
Freescale Semiconductor
NEC
SMA Receptacle,
Female
10
11
12
13
14
1
2
1
2
1
L1
L2, L3
R1
6.8 nH
8.2 nH
470 kΩ
0 Ω
R2, R3
X1
16.000 MHz, Type
DSX321G, ZD00882
KDS, Daishinku Corp
Murata
15
2
Z1, Z2
LDB212G4020C-001
Table 10. Daishinku, KDS - DSX321G, ZD00882 Crystal Specifications
Parameter
Value
Unit
Condition
surface mount
Type
DSX321G
16
Frequency
MHz
ppm
Ω
Frequency tolerance
Equivalent series resistance
Temperature drift
Load capacitance
Drive level
± 20
100
± 20
8.0
at 25 °C ± 3 °C
max
ppm
pF
-10 °C to +60 °C
10
µW
pF
± 2 µW
Shunt capacitance
Mode of oscillation
2
max
fundamental
MC13192/MC13193 Technical Data, Rev. 2.7
20
Freescale Semiconductor
Packaging Information
9 Packaging Information
PIN 1
INDEX AREA
0.1
C
2X
5
A
M
0.1
C
0.1
C
2X
G
1.00
0.75
1.0
0.8
0.05
C
5
5
(0.25)
0.05
(0.5)
0.00
SEATING PLANE
C
DETAIL G
VIEW ROTATED 90° CLOCKWISE
M
B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
0.1
C
A
B
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
DETAIL M
PIN 1 INDEX
3.25
2.95
EXPOSED DIE
ATTACH PAD
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
25
32
5. COPLANARITY APPLIES TO LEADS, CORNER
LEADS, AND DIE ATTACH PAD.
24
1
6. FOR ANVIL SINGULATED QFN PACKAGES,
MAXIMUM DRAFT ANGLE IS 12°.
0.25
3.25
2.95
0.1
C
A
B
0.217
0.137
28X
0.5
0.217
8
17
0.137
N
16
9
0.30
0.18
0.5
0.3
32X
32X
(0.25)
(0.1)
M
M
0.1
C
C
A
B
VIEW M-M
0.05
DETAIL S
PREFERRED BACKSIDE PIN 1 INDEX
5
)
(45
DETAIL S
0.60
0.24
(1.73)
0.60
0.24
0.065
0.015
32X
(0.25)
DETAIL N
DETAIL N
DETAIL M
CORNER CONFIGURATION OPTION
PREFERRED CORNER CONFIGURATION
PREFERRED BACKSIDE PIN 1 INDEX
4
4
1.6
BACKSIDE
PIN 1 INDEX
(90 )
1.5
DETAIL T
0.475
0.425
0.39
0.31
2X
0.25
0.15
R
0.1
0.0
2X
DETAIL T
DETAIL M
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
BACKSIDE PIN 1 INDEX OPTION
BACKSIDE PIN 1 INDEX OPTION
Figure 11. Outline Dimensions for QFN-32, 5x5 mm
(Case 1311-03, Issue E)
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
21
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MC13192/D
Rev. 2.7
12/2004
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