MC13237CHTR [NXP]
SPECIALTY ANALOG CIRCUIT, BGA48;
| 型号： | MC13237CHTR |
| 厂家： | 
NXP |
| 描述： | SPECIALTY ANALOG CIRCUIT, BGA48 |
| 文件： | 总430页 (文件大小：3416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC13234/MC13237
ZigBee™- Compliant Platform
2.4 GHz Low Power Transceiver for the
IEEE® 802.15.4 Standard plus Microcontroller
Reference Manual
Document Number: MC13237RM
Rev. 1.8
9/2013
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
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suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer’s technical experts. Freescale does not convey any
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC13237RM
Rev. 1.8
9/2013
Contents
About This Book
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
Chapter 1
MC13237 Introduction
1.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
1.3
1.4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Software Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Simple Media Access Controller (SMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
IEEE 802.15.4 2006 Standard-Compliant MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
BeeStack Consumer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
ZigBee-Compliant Network Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
SynkroRF Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Integrated IEEE 802.15.4 Transceiver (Radio and Modem) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
RF Interface and Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Transceiver Register Interface and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
IEEE 802.15.4 Acceleration Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Unique Partial Power Down (PPD_RX) or “Listen” Receive Mode . . . . . . . . . . . . . . . . . . 1-9
HCS08 8-Bit Central Processing Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
System and Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.6
1.7
1.8
1.9
1.9.1
1.9.2
1.9.3
1.10 MCU Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.11 12-Bit Analog-to-Digital Conversion (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.12 Development Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Chapter 2
Pins and Connections
2.1
2.2
Device Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Chapter 3
System Considerations
3.1
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
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3.3
Special Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Hardware RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Signal PTA2 (Factory Test Mode Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
MCU Background/Mode Select (PTA7/BKGD/MS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
32 MHz Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
32 MHz Crystal Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
32 MHz Crystal Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
32.768 kHz Crystal Oscillator (Optional). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
32.768 kHz Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Device Version ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
MC13234/MC13237 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
GPIO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Transceiver RF Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.1
3.3.2
3.3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
3.7
3.8
3.8.1
3.8.2
3.9
3.10 Transceiver Indirect Access Register Application Functions. . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.11 General System Considerations for Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.11.1
3.11.2
3.11.3
Run Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Low Power Mode Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Entering/Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Chapter 4
Memory
4.1
MC13234/MC13237 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.5
Reset and Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Register Addresses and Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Memory Management Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Chapter 5
System Management and Control
5.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
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5.3
5.4
Management Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
System Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Main System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Clock Distribution Network Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Managing Clock Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Management of Timer Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
RTC Timer Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Computer Operating Properly (COP) Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Interrupt Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
External Interrupt Request (IRQ) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Interrupt Vectors, Sources, and Local Masks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Low Power Run Mode (LPRun). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Active Background Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Low Power Wait Mode (LPWait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Stop3 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
On-Chip Peripheral Modules in Stop and Low Power Modes . . . . . . . . . . . . . . . . . . . . . . 5-19
System Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Interrupt Pin Request Status and Control Register (IRQSC) . . . . . . . . . . . . . . . . . . . . . . . 5-20
System Reset Status Register (SRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
System Background Debug Force Reset Register (SBDFR) . . . . . . . . . . . . . . . . . . . . . . . 5-22
System Options Register 1 (SOPT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
System Options Register 2 (SOPT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
System Device Identification Register (SDIDH, SDIDL) . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
System Power Management Status & Control 1 (SPMSC1) . . . . . . . . . . . . . . . . . . . . . . . 5-25
System Power Management Status & Control 2 (SPMSC2) . . . . . . . . . . . . . . . . . . . . . . . 5-26
System Power Management Status & Control 3 (SPMSC3) . . . . . . . . . . . . . . . . . . . . . . . 5-27
System Oscillator Management and Control Register 1 (SOMC1) . . . . . . . . . . . . . . . . . . 5-29
System Oscillator Management and Control Register 2 (SOMC2) . . . . . . . . . . . . . . . . . . 5-30
System Clock Gating Control 1 Register (SCGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
System Clock Gating Control 2 Register (SCGC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.6.3
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
5.8.7
5.8.8
5.8.9
5.8.10
5.8.11
5.8.12
5.8.13
Chapter 6
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.1
6.2
6.3
6.3.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Transceiver Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
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6.3.2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.5.3
6.6
Direct Memory Access (DMA) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
IEEE 802.15.4 Standard PHY Packet and Frame Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
PHY Protocol Data Unit (PPDU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
MAC Frame Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Basic PHY Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Clear Channel Assessment (CCA) Operation (including ED and Link Quality Indication) 6-8
Packet Transmission (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Packet Reception (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
VCO Frequency Synthesizer (Channel Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Event Timer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Event Timer Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Setting Current Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Reading Current Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Receive Packet Timestamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Event Timer Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Control Model Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Supported Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Initiating a Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Aborting a Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Sequence I (IDLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Basic Receive Sequence – Sequence R (Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Basic Transmit Sequence – Sequence T (Transmit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Basic Sequence C (Standalone CCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Sequence T/R (Transmit/Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Sequence CCCA (Continuous CCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Effect of Timer TC3 on Sequence Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.8
6.8.1
6.8.2
6.8.3
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.9.7
6.9.8
6.9.9
6.10 Transmitter Power Amplifier (PA) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.11 Hardware Pseudo-Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.12 Transceiver Interrupt Requests (IRQs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
6.13 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
6.13.6
6.13.7
6.13.8
Transmit Data Pointer Registers (TXD_ADR_PNTR0 and TXD_ADR_PNTR1) . . . . . . 6-38
Receive Data Pointer Registers (RXD_ADR_PNTR0 and RXD_ADR_PNTR1). . . . . . . 6-40
Transceiver Control Register 1 (CNTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
Transceiver Control Register 2 (CNTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
Transceiver Control Register 3 (CNTRL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
Transceiver Control Register 4 (CNTRL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
Transceiver Source Address Control Register (SRC_CNTRL) . . . . . . . . . . . . . . . . . . . . . 6-47
Transceiver Source Address Sum Data Registers (SRC_ADDRS_SUM_DATA0 and
SRC_ADDRS_SUM_DATA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Receiver Byte Count Watermark Threshold (RX_WTR_MARK). . . . . . . . . . . . . . . . . . . 6-49
6.13.9
6.13.10 Receiver Byte Count (RX_BYTE_COUNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.13.11 Status Register 1 (STATUS1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
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6.13.12 Status Register 2 (STATUS2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
6.13.13 Clear Channel Assessment Final Value (CCAFNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
6.13.14 Event Timer Registers (EVENT_TMR0, EVENT_TMR1, and EVENT_TMR2). . . . . . . 6-54
6.13.15 Time Stamp Registers (TIMESTAMP0, TIMESTAMP1, and TIMESTAMP2) . . . . . . . . 6-55
6.13.16
Event Timer Comparator 3 Registers (T3CMP0, T3CMP1, and T3CMP2) . . . . . . . . . . . 6-56
6.13.17 Time Comparator 2 Prime Registers (TC2_PRIME0 and TC2_PRIME1) . . . . . . . . . . . . 6-57
6.13.18 MAC Short Address Registers (MACSHORTADDRS0 and MACSHORTADDRS1). . . 6-58
6.13.19 MAC Pan ID Registers (MACPANID0 and MACPANID1) . . . . . . . . . . . . . . . . . . . . . . . 6-59
6.13.20
6.13.21
6.13.22
Event Timer Comparator 1 Registers (T1CMP0, T1CMP1, and T1CMP2) . . . . . . . . . . . 6-60
Event Timer Comparator 2 Registers (T2CMP0, T2CMP1, and T2CMP2) . . . . . . . . . . . 6-61
Event Timer Comparator 4 Registers (T4CMP0, T4CMP1, and T4CMP2) . . . . . . . . . . . 6-62
6.13.23 LO1 FracN Numerator Value Registers (LO1_FRAC0 and LO1_FRAC1) . . . . . . . . . . . 6-63
6.13.24 LO1 Integer Register (LO1_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64
6.13.25 Power Amplifier (PA) Power Control Register (PA_PWR_CNTL) . . . . . . . . . . . . . . . . . 6-64
6.13.26 MAC Long Address Registers (MACLONGADDRS0 – MACLONGADDRS7). . . . . . . 6-65
6.13.27 Max Frame Length Register (MAXFRAMELENGTH) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
6.13.28 Receive Frame Filter (RX_FRAME_FILTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67
6.13.29 MAC Frame Version Compatibility and Timer Prescale Register (FMR_REV_TMR) . . 6-69
6.13.30 CCA Energy Threshold (CCA_THRESHOLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
6.13.31 CCA Power Compensation (CCA_OFFSET_CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
6.13.32 Finite State Machine Register (FSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71
6.13.33 Transceiver Indirect Access Registers (INDEX and DATA). . . . . . . . . . . . . . . . . . . . . . . 6-73
Chapter 7
Advanced Security Module (ASM)
7.1
7.1.1
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Module Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
ASM Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Counter (CTR) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Cipher Block Chaining (CBC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Counter With CBC-MAC (CCM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Plain AES Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
ASM Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AES 128 Control 1 Register (CONTROL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AES 128 Control Register 2 (CONTROL2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
AES 128 Data Registers (ASMDATA0 - ASMDATAF). . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.5.1
7.5.2
7.5.3
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Chapter 8
CPU
8.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Programmer’s Model and CPU Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Inherent Addressing Mode (INH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Relative Addressing Mode (REL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Immediate Addressing Mode (IMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Direct Addressing Mode (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Extended Addressing Mode (EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Special Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
BGND Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Chapter 9
Parallel Input and Output
9.1
9.2
9.3
9.3.1
9.4
9.4.1
9.4.2
9.4.3
9.5
9.6
9.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
IO Port Pin Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Port Data and Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Pullup, Slew Rate, and Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Port Internal Pullup Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Port Slew Rate Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Port Drive Strength Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Pin Behavior in Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Interrupt Request Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Parallel I/O and Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Port C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Port D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.7.1
9.7.2
9.7.3
9.7.4
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Chapter 10
Real-Time Counter (RTC)
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4.1
10.4.2
10.4.3
10.4.4
Clock Source and Prescale Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Compare Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Interrupt Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Module Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.5.1
10.5.2
10.5.3
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Stop3 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Active Background Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.6 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.7 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.7.1
10.7.2
10.7.3
RTC Status and Control Register (RTCSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
RTC Counter Registers (RTCCNTH and RTCCNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
RTC Modulo Registers (RTCMODH and RTCMODL) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Chapter 11
Modules (KBIx)
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.1.7
KBI Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Chapter 12
Analog-to-Digital Converter (ADC)
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1
12.1.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
ADC Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
Analog Power (V
Analog Ground (V
Voltage Reference High (V
Voltage Reference Low (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
DDA_ADC
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
SSA_ADC
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
REFL
Analog Channel Inputs (ADx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
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12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
Status and Control Register 1 (ADCSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Status and Control Register 2 (ADCSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Data Result High Register (ADCRH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Data Result Low Register (ADCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Compare Value High Register (ADCCVH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Compare Value Low Register (ADCCVL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Configuration Register (ADCCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Pin Control 1 Register (APCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
Clock Select and Divide Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Input Select and Pin Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Asynchronous and Alternate Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Software Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Conversion Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Automatic Compare Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
MCU Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.4.10 MCU Stop3 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.5.1
ADC Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.6.1
12.6.2
External Pins and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
Chapter 13
Inter-integrate Circuit (IIC)
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1
13.1.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
IIC Address Register (IIC1A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
IIC Frequency Divider Register (IIC1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
IIC Control Register (IIC1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
IIC Status Register (IIC1S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
IIC Data I/O Register (IIC1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
IIC Control Register 2 (IIC1C2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
IIC Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
10-bit Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
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13.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Chapter 14
Serial Communications Interface (SCI)
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.4.1
14.4.2
TXD — Transmit Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
RXD — Receive Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Transmitter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Receiver Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Interrupts and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Additional SCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.6 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
14.6.6
14.6.7
14.6.8
SCI Baud Rate Registers (SCI1BDH, SCI1BDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
SCI Control Register 1 (SCI1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
SCI Control Register 2 (SCI1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
SCI Status Register 1 (SCI1S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
SCI Status Register 2 (SCI1S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
SCI Control Register 3 (SCI1C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20
SCI Data Register (SCI1D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
SCI Control Register 4 (SCI1C4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Chapter 15
Serial Peripheral Interface (SPI) Module
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3.1
15.3.2
SPI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4.1
15.4.2
15.4.3
15.4.4
SPICLK — SPI Serial Clock (SPSCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
MOSI — Master Data Out, Slave Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
MISO — Master Data In, Slave Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
SS — Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.5.1
15.5.2
15.5.3
15.5.4
Bit Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Basic Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
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Mode Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.7 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.7.1
15.7.2
15.7.3
15.7.4
15.7.5
SPI Control Register 1 (SPI1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
SPI Control Register 2 (SPI1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
SPI Baud Rate Register (SPI1BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
SPI Status Register (SPI1S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
SPI Data Register (SPI1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Chapter 16
Timer/PWM (TPM Module)
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2.1
16.2.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
External Signals (TPM3:TPM0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3.1
16.3.2
16.3.3
16.3.4
TPM Counter Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
Channel Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Center-Aligned PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.4 TPM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.4.1
16.4.2
16.4.3
16.4.4
Clearing Timer Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Timer Overflow Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Channel Event Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
PWM End-of-Duty-Cycle Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.6 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
Timer x Status and Control Register (TPMxSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Timer x Counter Registers (TPMxCNTH:TPMxCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL). . . . . . . . . . . . . . . . . 16-12
Timer x Channel 0 Status and Control Register (TPM1C0SC) . . . . . . . . . . . . . . . . . . . . 16-13
Timer x Channel Value Registers (TPMxC0VH:TPMxC0VL) . . . . . . . . . . . . . . . . . . . . 16-14
Chapter 17
Carrier Modulator Timer (CMT) Module
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.4 External Signal (IRO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.5.1
17.5.2
17.5.3
17.5.4
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Operating Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
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17.5.5
17.5.6
17.5.7
Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
CMT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.7 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.7.1
Carrier Generator Data Registers ( CMTCGH1, CMTCGL1, CMTCGH2, and
CMTCGL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
CMT Output Control Register (CMTOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
CMT Modulator Status and Control Register (CMTMSC) . . . . . . . . . . . . . . . . . . . . . . . 17-17
CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3, and
17.7.2
17.7.3
17.7.4
CMTCMD4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
Chapter 18
Development Support
18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1
18.1.2
18.1.3
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Forcing Active Background Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
Debug Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2 Background Debug Controller (BDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.1
18.2.2
18.2.3
18.2.4
18.2.5
BDC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Standard Debug (BDM) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
BKGD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Serial Interface Communication Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.3.1
18.3.2
BDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
DBG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32
18.4.1
18.4.2
BDC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32
DBG Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38
Appendix A
IEEE 802.15.4 PHY Messaging Overview
A.1
A.2
A.3
A.3.1
A.3.2
A.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Basic PHY Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Non-beacon-Enabled versus Beacon-Enabled Communication. . . . . . . . . . . . . . . . . . . . . . . . . A-1
Non-beacon-Enabled Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Beacon-Enabled Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
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Freescale Semiconductor
About This Book
™
This manual describes Freescale’s fourth-generation ZigBee platform (the MC13234/MC13237), which
incorporates a low power 2.4 GHz radio frequency transceiver and an 8-bit microcontroller into a single
7x7x1 mm 48-pin LGA package. The MC13234/MC13237 solution can be used for wireless applications
from simple proprietary point-to-point connectivity, to a complete ZigBee mesh network. The combination
of the radio and a microcontroller in a small footprint package allows for a cost-effective solution.
Audience
This manual is intended for system designers.
Organization
This document is organized into 18 chapters and one appendix.
Chapter 1
Introduction — Briefly introduces the MC13234/MC13237. The
MC13234/MC13237 is Freescale’s fourth-generation ZigBee device. It
™
incorporates a low power 2.4 GHz radio frequency transceiver and an 8-bit
microcontroller into a single 7x7x1 mm 48-pin LGA package.
Chapter 2
Chapter 3
Pins and Connections — Describes device pinout and functionality.
System Considerations — Describes system level considerations of the
MC13234/MC13237 modem and MCU.
Chapter 4
Memory — Describes on-chip memory in the HCS08 series of MCUs and shows
that it consists of RAM, flash program memory for non-volatile data storage, plus
I/O and control/status registers.
Chapter 5
Chapter 6
System Management — Describes the various elements that manage and control
operation of the HCS08.
IEEE 802.15.4 2.4 GHz Transceiver — Provides an overview and general
description for the radio and the modem and details the sequence manager, timer
resources, and control functions.
Chapter 7
Chapter 8
Advanced Security Module (ASM) — Details how the ASM engine encrypts
using the Advanced Encryption Standard (AES).
Central Processor Unit (CPU) — Provides summary information about the
registers, addressing modes, and instruction set of the CPU of the HCS08 Family.
This section provides summary information about the registers, addressing modes,
and instruction set of the CPU of the HCS08 Family.
Chapter 9
Parallel Input/Output — Explains software controls related to parallel
input/output (I/O).This section explains software controls related to parallel
input/output (I/O).
Chapter 10
Real Time Counter (RTC) — Details the 16-bit counter, a 16-bit comparator,
several binary-based and decimal-based prescaler dividers, three clock sources,
and a programmable periodic interrupt request.
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Chapter 11
Chapter 12
Keyboard Interrupt (KBI) — Describes the KBI module. Eight keyboard
interrupt inputs are shared with port B pins.
Analog-to-Digital Converter (ADC) Module — Describes the ADC module.
The 12-bit ADC is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
Chapter 13
Chapter 14
Inter Integrated Circuit (IIC) Module — Describes how the IIC bus standard
compatible IIC module functions the same in normal and monitor modes. A brief
description of the IIC in the various MCU modes is provided in this chapter.
Serial Communications Interface (SCI) — This chapter describes the SCI
which allows full-duplex, asynchronous, NRZ serial communication among the
MCU and remote devices, including other MCUs.
Chapter 15
Chapter 16
Serial Peripheral Interface — This chapter details the serial peripheral interface
(SPI).
Timer Pulse Width Modulator (PWM) — Describes how the
MC13234/MC13237 uses its internal Event Timer block to manage system
timing.
Chapter 17
Chapter 18
Appendix A
Carrier Modulator Timer (CMT) — The CMT module is an IR LED driver. The
module can transmit data to IRO pin either in baseband or in FSK mode.
Debug — Describes the MC13234/MC13237 comprehensive debug/development
capability for the HCS08 MCU.
IEEE 802.15.4 PHY Messaging Overview— Provides a simple overview of the
sequence manager.
Revision History
The following table summarizes revisions to this document since the previous release (Rev 1.7).
Revision History
Location
Revision
Chapter 5
Throughout
Added a new Section 5.7.6.6, “Stop3 and LPRun Mode Transition”
Minor typos.
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Definitions, Acronyms, and Abbreviations
The following list defines the acronyms and abbreviations used in this document.
ACK
API
Acknowledgement Frame
Application Programming Interface
Baseband
BB
CCA
CRC
DCD
DME
FCS
Clear Channel Assessment
Cyclical Redundancy Check
Differential Chip Decoding
Device Management Entity
Frame Check Sequence
Full Function Device
Full Function Device Coordinator
First In, First Out
FFD
FFD-C
FIFO
FLI
Frame Length Indicator
Guaranteed Time Slot
Hardware
GTS
HW
IRQ
Interrupt Request
ISR
Interrupt Service Routine
Local Oscillator
LO
MAC
MCPS
MCU
MLME
MSDU
NWK
PA
Medium Access Control
MAC Common Part Sublayer
Microcontroller Unit
MAC Sublayer Management Entity
MAC Service Data Unit
Network
Power Amplifier
PAN
PANID
PHY
PIB
Personal Area Network
PAN Identification
PHYsical Layer
PAN Information Base
PHY Protocol Data Unit
PHY Service Data Unit
Radio Frequency
PPDU
PSDU
RF
RFD
SAP
Reduced Function Device
Service Access Point
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xvii
SFD
SPI
Start of Frame Delimiter
Serial Peripheral Interface
Service Specific Convergence Layer
Software
SSCS
SW
VCO
Voltage Controlled Oscillator
References
The following sources were referenced to produce this book:
1. IEEE 802.15.4 Standard
2. Freescale MC9S08GB/GT60 Data Sheet
3. Freescale MC13237 Data Sheet
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Chapter 1
MC13237 Introduction
1.1
Overview
®
The MC13234/MC13237 is Freescale’s low-cost System-on-Chip (SoC) for the IEEE 802.15.4 Standard
that incorporates a complete, low power, 2.4 GHz radio frequency transceiver with TX/RX switch, an 8-bit
HCS08 CPU, and a functional set of MCU peripherals into a 48-pin LGA package. This solution is targeted
for wireless RF remote control and other cost-sensitive applications ranging from home TV and
entertainment systems such as ZigBee BeeStack Consumer (RF4CE) to low cost, low power, IEEE
802.15.4 and ZigBee end nodes. The MC13234/MC13237 is a highly integrated solution, with very low
power consumption.
The MC13234/MC13237 contains an RF transceiver which is an 802.15.4 Standard - 2006 compliant radio
that operates in the 2.4 GHz ISM frequency band. The transceiver includes a low noise amplifier, 1 mW
nominal output power amplifier (PA), internal voltage controlled oscillator (VCO), integrated
transmit/receive switch, on-board power supply regulation, 12-bit Analog-to-Digital Converter (ADC)
and full spread-spectrum encoding and decoding.
The on-chip CPU is based on the Freescale HCS08 family of Microcontroller Units (MCU) and has 128
kilobyte (KB) of flash memory and 8 KB of RAM. The onboard MCU peripheral set has been defined to
support the targeted applications. A dedicated DMA block transfers packet data between RAM and the
transceiver to off-load the CPU and allow higher efficiency and increased performance.
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1-1
MC13237 Introduction
1.2
Block Diagram
Figure 1-1 shows a simplified block diagram of the MC13234/MC13237.
32 MHz
32.768 KHz
(Optional)
Clock &
Reset
Module
Timer
RF Oscillator/PLL
Module
&
(4 Timers,
Each w/1Ch)
Clock Generation
(CRM)
12
12 x 12
Keyboard
Interface
Digital
Modem
Analog
TX
CPU Complex
802.15.4
PHY
Sequence
Manager
HCS08
Core
SCI/UART
Interface
Modem
TX
TX/RX
Switch
Balun
Bus
Modem
RX
Interface &
Memory
Arbitrator
Analog
RX
I2C
Module
®
IEEE
802.15.4 Transceiver
Interrupt
Controller
Advanced
Security
Module
SPI
Interface
128KB
FLASH
CMT
Analog Pwr
Management
& Voltage Reg
(IR)
Module
8 KB
RAM
Low
Battery
Debug
Module
12-Bit ADC
Module
Figure 1-1. MC13234/MC13237 Simplified Block Diagram
1.3
Features Summary
•
Fully compliant IEEE 802.15.4 Standard 2006 transceiver supports 250 kbps O-QPSK data in
5.0 MHz channels and full spread spectrum encode and decode
— 2.4 GHz
— Operates on one of 16 selectable channels per IEEE 802.15.4
— Programmable output power with 0 dBm nominal output power, programmable from –30 dBm
to +2 dBm typical
— Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE
802.15.4 Standard of –85 dBm
— Partial Power Down “listen” mode (PPD_RX) available to reduce current while in receive
mode and waiting for an incoming frame
•
Small RF footprint
— Integrated transmit/receive switch
— Differential input/output port (typically used with a balun)
— Low external component count
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MC13237 Introduction
®
•
Hardware acceleration for IEEE 802.15.4 applications
— DMA interface
— AES-128 Security module
— 16-Bit random number generator
— 802.15.4 Auto-sequence support
— 802.15.4 Receiver Frame filtering
•
•
•
32 MHz crystal reference oscillator; onboard load trim capability supplements external load
capacitors
Onboard 1 kHz oscillator for wake-up timing or an optional 32.768 kHz crystal for accurate low
power timing.
Transceiver Event Timer module has 4 timer comparators available to help manage the
auto-sequencer and to supplement MCU TPM resources
•
•
HCS08 8-bit, 32 MHz CPU
Flash memory
— 131072 Bytes organized as 128 segments by 1024 bytes
dec
— Programmable over the full power supply range of 1.8–3.6 V
— Automated program and erase algorithms
— Flexible protection scheme to prevent accidental program or erase
— Security feature to prevent unauthorized access to the Flash
RAM
•
•
— 8 KBytes RAM
Powerful In-circuit debug and flash programming available via on-chip module (BDM)
— Two comparator and 9 trigger modes
— Eight deep FIFO for storing change-of-flow addresses and event-only data
— Tag and force breakpoints
— In-circuit debugging with single breakpoint
Multiple low power modes (less than 1 A in Stop3)
Keyboard interrupt (KBI) module
•
•
— MC13234
– Two keyboard control modules capable of supporting up to a 12 x 12 keyboard matrix
– 12 dedicated KBI pins support a 6 x 6 matrix without impacting other IO resources
– 12 KBI interrupts with selectable polarity
— MC13237
– One keyboard control module capable of supporting up to a 8 x 8 keyboard matrix
– 8 dedicated KBI pins support a 4 x 4 matrix without impacting other IO resources
– 8 KBI interrupts with selectable polarity
•
Serial communication interface (SCI)
— Full duplex non-return to zero (NRZ)
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1-3
MC13237 Introduction
— Baud rates as high as 1 Mbps can be supported
— LIN master extended break generation
— LIN slave extended break detection
— Wake-up on active edge
•
•
Serial peripheral interface (SPI)
— Full-duplex or single-wire bidirectional
— Double-buffered transmit and receive
— Master or Slave mode; MSB-first or LSB-first shifting
Inter-integrated circuit (IIC) interface
— Up to 100 kbps baud rate with maximum bus loading
— Baud rates as high as 800 kbps can be programmed
— Multi-master operation
— Programmable slave address
— Interrupt driven byte-by-byte data transfer;
— Supports broadcast mode and 10-bit addressing
•
•
Four 16-bit timer/pulse width modulators (TMP[4:1]) — each TPM module has an assigned GPIO
pin and provides
— Single channel capability
— Input capture
— Output compare
— Buffered edge-aligned or center-aligned PWM
8-Channel, 12-bit resolution ADC
— 2.5 s conversion time
— Internal 1.7 mV/C temperature sensor
— Internal bandgap reference
— Operation in Stop3
— Fully functional from 1.8 V to 3.6 V
Carrier Modulator Timer (CMT) — IR Remote carrier generator, modulator, and transmitter.
Real-time counter (RTC)
•
•
— 16-bit modulus counter with binary or decimal based prescaler;
— External clock source for precise time base, time-of-day, calendar or task scheduling functions
— Capable of greater than one day interrupt.
System protection features
•
•
— Programmable low voltage warning and interrupt (LVI)
— Optional watchdog timer (COP)
— Illegal opcode detection
1.8 V to 3.6 V operating voltage with on-chip voltage regulators.
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MC13237 Introduction
•
Up to 32 GPIO
— MC13234: 32 GPIOs
— MC13237: 28 GPIOs
— Hysteresis and configurable pull up resistors on all input pins
— Configurable slew rate and drive strength on all output pins
–40°C to +85°C temperature range
•
•
RoHS-compliant 7x7 mm 48-pin LGA package
Table 1-1. MC13234 and MC13237 Comparison
Feature
Radio
MC13234
MC13237
IEEE 802.15.4 compliant
CPU
32 MHz HCS08
Flash memory
128K
8K
RAM
BDM
Yes
Yes
Low power modes
KBI
SCI
Two (12 interrupts)
One (8 interrupts)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SPI
IIC
TPM
CMT
RTC
LVD
COP
ADC
GPIO
No
32
Yes
28
1.4
Software Solutions
Freescale provides a powerful software environment called the Freescale BeeKit Wireless Connectivity
Toolkit. BeeKit is a comprehensive codebase of wireless networking libraries, application templates, and
sample applications. The BeeKit Graphical User Interface (GUI), part of the BeeKit Wireless Connectivity
Toolkit, allows users to create, modify, and update various wireless networking implementations. A wide
range of software functionality is available to complement the MC13234/MC13237 and these are provided
as codebases within BeeKit. The following sections describe the available tools.
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1-5
MC13237 Introduction
1.4.1
Simple Media Access Controller (SMAC)
The Freescale Simple Media Access Controller (SMAC) is a simple ANSI C based code stack available
as sample source code. The SMAC can be used for developing proprietary RF transceiver applications
using the MC13234/MC13237.
•
•
•
Supports point-to-point and star network configurations
Proprietary networks
Source code and application examples provided
1.4.2
IEEE 802.15.4 2006 Standard-Compliant MAC
The Freescale 802.15.4 Standard-Compliant MAC is a code stack available as object code. The 802.15.4
MAC can be used for developing MC13234/MC13237 networking applications based on the full IEEE®
802.15.4 Standard that use custom Network Layer and application software.
•
•
•
•
•
•
•
Supports star, mesh and cluster tree topologies
Supports beaconed networks
Supports GTS for low latency
Multiple power saving modes
AES-128 Security module
802.15.4 Sequence support
802.15.4 Receiver Frame filtering
1.4.3
BeeStack Consumer
Freescale’s ZigBee RF4CE stack, called BeeStack Consumer, is a networking layer that sits on top of the
®
IEEE 802.15.4 MAC and PHY layers. It is designed for standards-based Wireless Personal Area
Networks (WPANs) of home entertainment products and conveys information over short distances among
the participants in the network. It enables small, power efficient, inexpensive solutions to be implemented
for a wide range of applications. Targeted applications include DTV, set top box, A/V receivers, DVD
players, security, and other consumer products.
Some key characteristics of a BeeStack Consumer network are:
•
•
•
•
•
•
An over the air data rate of 250 kbps in the 2.4 GHz band
3 independent communication channels in the 2.4 GHz band
2 network node types, controller node and target node
Channel Agility mechanism
Provides robustness and ease of use
Includes essential functionality to build and support a CE network
The BeeStack Consumer layer uses components from the standard HCS08 Freescale platform, which is
also used by the Freescale implementations of 802.15.4. MAC or ZigBee™ layers. For more details about
the platform components, see the Freescale Platform Reference Manual.
MC13234/MC13237 Reference Manual, Rev. 1.8
1-6
Freescale Semiconductor
MC13237 Introduction
1.4.4
ZigBee-Compliant Network Stack
Freescale’s BeeStack architecture builds on the ZigBee protocol stack. Based on the OSI Seven-Layer
model, the ZigBee stack ensures inter-operability among networked devices. The physical (PHY), media
access control (MAC), and network (NWK) layers create the foundation for the application (APL) layers.
BeeStack defines additional services to improve the communication between layers of the protocol stack.
At the Application Layer, the application support layer (ASL) facilitates information exchange between
the Application Support Sub-Layer (APS) and application objects. Finally, ZigBee Device Objects (ZDO),
in addition to other manufacturer-designed applications, allow for a wide range of useful tasks applicable
to home and industrial automation.
BeeStack uses the IEEE 802.15.4-compliant MAC/PHY layer that is not part of ZigBee itself. The NWK
layer defines routing, network creation and configuration, and device synchronization. The application
framework (AF) supports a rich array of services that define ZigBee functionality. ZigBee Device Objects
(ZDO) implement application-level services in all nodes via profiles. A security service provider (SSP) is
available to the layers that use encryption (NWK and APS), i.e., Advanced Encryption Standard (AES)
128-bit security.
The complete Freescale BeeStack protocol stack includes the following components:
•
•
•
•
•
•
ZigBee Device Objects (ZDO) and ZigBee Device Profile (ZDP)
Application Support Sub-Layer (APS)
Application Framework (AF)
Network (NWK) Layer
Security Service Provider (SSP)
IEEE 802.15.4-compliant MAC and Physical (PHY) Layer
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
1-7
MC13237 Introduction
1.4.5
SynkroRF Platform
®
The SynkroRF Network is a general purpose, proprietary networking layer that sits on top of the IEEE
802.15.4 MAC and PHY layers. It is designed for Wireless Personal Area Networks (WPANs) and
conveys information over short distances among the participants in the network. It enables small, power
efficient, inexpensive solutions to be implemented for a wide range of applications. Some key
characteristics of an SynkroRF Network are:
•
•
•
•
•
•
An over the air data rate of 250 kbps in the 2.4 GHz band.
3 independent communication channels in the 2.4 GHz band (15, 20, and 25).
2 network node types: controller and controlled nodes.
Channel Agility mechanism.
Low Latency TX mode automatically enabled in conditions of radio interference.
Fragmented mode transmission and reception, automatically enabled in conditions of radio
interference.
•
•
Robustness and ease of use.
Essential functionality to build and support a CE network.
The SynkroRF Network layer uses components from the standard HC(S)08 Freescale platform, which is
also used by the Freescale’s implementations of 802.15.4. MAC and ZigBee™ layers. For more details
about the platform components, see the Freescale Platform Reference Manual.
1.5
Integrated IEEE 802.15.4 Transceiver (Radio and Modem)
The MC13234/MC13237 IEEE 802.15.4 is a fully-compliant transceiver. It provides a complete 2.4 GHz
radio with 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 5.0 MHz channels with a
full spread-spectrum encode and decode. The modem supports the full requirement of the IEEE 802.15.4
Standard functionality to transmit, receive, and do clear channel assessment (CCA), Energy Detect (ED),
and Link Quality Indication (LQI).
•
Programmable output power with 0 dBm nominal output power, programmable from –30 dBm to
+2 dBm typical
•
•
•
•
Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet
Differential bidirectional RF input/output port
Integrated transmit/receive switch
Receive current can be reduced while waiting or “listening” for an incoming frame using partial
power down (PPD) mode
1.5.1
RF Interface and Usage
The MC13234/MC13237 RF interface provides a bidirectional, differential port that connects directly to
a balun. The balun connects directly to a single-ended antenna and converts that interface to a full
differential, bidirectional, on-chip interface with transmit/receive switch, LNA, and complementary PA
outputs.This combination allows for a small footprint and low cost RF solution to be realized.
MC13234/MC13237 Reference Manual, Rev. 1.8
1-8
Freescale Semiconductor
MC13237 Introduction
1.5.2
Transceiver Register Interface and Operation
The transceiver is controlled by set of interface registers that are memory-mapped into the CPU address
space. The transceiver is capable of independent operation to transmit, receive, or perform CCA/ED
operations. Additional features of the transceiver include:
•
DMA function moves data directly between RAM and transceiver buffers during transmit and
receive on a cycle-steal basis. This off loads the data transfer from the CPU and provides higher
performance, and can also allow lower power during TX/RX.
•
Interrupt capability dependent on RX packet data availability. An interrupt can be generated based
on a programmed count of RX data bytes that have been received and moved to RAM. This allows
CPU filtering of RX data before completion of the packet reception to accelerate response to the
packet.
•
Four (4) transceiver Event Timer comparators are available to supplement MCU peripheral timer
resources for PHY and MAC timing requirements.
1.5.3
IEEE 802.15.4 Acceleration Hardware
The MC13234/MC13237 802.15.4 transceiver has several hardware features that reduce the software stack
size, off load the function from the CPU, and improve performance. A list of features supported is provided
below:
®
•
•
•
•
•
•
•
2003 & 2006 versions of the IEEE 802.15.4 standard is full supported
Slotted and unslotted modes
Beacon enabled and non-beacon enabled networks
DMA data transfer between RAM and radio
Separate AES-128 Security Module
16-bit Random Number Generator
802.15.4 Sequence support
— RX (conditionally followed by TXAck)
— TX
— CCA (used for CCA and ED cycles)
— TX/RX (TX followed by unconditional RX or RCACK)
— Continuous CCA
•
802.15.4 Receiver Frame filtering.
1.5.4
Unique Partial Power Down (PPD_RX) or “Listen” Receive Mode
The MC13234/MC13237 provides a unique Partial Power Down receive (PPD_RX) mode. A summary of
PPD_RX mode of operation when selected is described below:
•
Whenever a receive cycle is initiated, the receiver is not turned fully on to save current until receive
energy of a preset level is detected
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
1-9
MC13237 Introduction
•
•
The receiver will turn fully on only when triggered by energy at a pre-determined preset level thus
enabling reception of the expected frame. Afterwards, the receiver will begin operating in the
full-on state that is considered to be the same as the standard receive state
The preset level can be programmed for various RX input power levels
Use of the PPD_RX mode provides two distinct advantages:
•
Reduced Listen mode current — The receive current is significantly reduced while waiting for a
frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its
RF-active time waiting for incoming frames from clients or other devices, the net power savings
can be significant.
•
Reduced sensitivity as a desired effect — The PPD_RX mode provides different levels of reduced
sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the
receiver such that the device does not respond to incoming frames with an energy level below the
desired threshold. This could be useful for security, net efficiency, reduced noise triggering and
many other purposes.
1.6
HCS08 8-Bit Central Processing Unit (CPU)
The onboard CPU is a 32 MHz 8-bit HCS08 CPU. It executes the HC08 instruction set with added BGND
instruction and supports for up to 32 interrupt/reset sources. The HCS08 CPU is fully source and object
code compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes are added
to improve C compiler efficiency and to support a new background debug system. It has an 8-bit data bus,
a 16-bit address bus and a 2-stage instruction pipe that facilitates the overlapping of instruction fetching
and execution. There are 29 vectors for internal interrupt sources and one vector for an external interrupt
pin. The debug or BDM module provides a serial one-wire interface for non-intrusive debugging of
application programs.
Features of the HCS08 CPU include:
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 and M68HC08 Families
64-KB CPU address space with banked memory management unit for greater than 64 KB
16-bit stack pointer (any size stack anywhere in 64-KB CPU address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-KB address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
MC13234/MC13237 Reference Manual, Rev. 1.8
1-10
Freescale Semiconductor
MC13237 Introduction
•
•
Memory-to-memory data move instructions with four address mode combinations
Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
•
•
•
Efficient bit manipulation instructions
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
STOP and WAIT instructions to invoke low-power operating modes
1.7
System Clocks
The primary system reference frequency is a 32 MHz crystal oscillator. The crystal requirements for the
oscillator and oscillator performance must support a +/-40 ppm frequency accuracy to meet the IEEE
802.15.4 Standard requirements. All system clocks are generated from this source. Features of the clock
system include:
•
The 32 MHz reference oscillator has onboard programmable capacitive loading that allows
software tuning of frequency accuracy
•
•
•
•
CPU clock as high as 32 MHz
Bus clock (and peripheral clock) equals 1/2 CPU clock
Clocks to individual peripherals can be independently disabled for best power management.
CPU clock can be lowered to 500 kHz for lower power (250 kHz bus clock)
An optional 32.768 kHz crystal oscillator is available for accurate low power timing and the Real Time
Clock (RTC). Also, an onboard, low accuracy 1 kHz oscillator is available for sleep timing wake-up.
1.8
Memory
The MC13234/MC13237 memory resources consist of RAM, flash program memory for nonvolatile data
storage, and control/status registers for I/O, peripherals, management, and the transceiver. Features
include:
•
•
•
128 Kbytes flash
8 Kbytes RAM
Security circuitry to prevent unauthorized access to RAM and flash contents
1.9
System and Power Management
The MC13234/MC13237 is inherently a low power device, but it also has extensive system control and
power management to maximize battery life and provide system protection.
1.9.1
Modes of Operation
The MC13234/MC13237 modes of operation include:
•
•
Active background mode for code development
Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
1-11
MC13237 Introduction
•
•
•
•
LPRun mode — CPU clock is set to 500 kHz and peripheral clocks (bus clock) to 250 kHz and the
internal voltage regulator is in standby
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
LPWait mode — CPU shuts down to conserve power; peripheral clocks are restricted to 250 kHz
and the internal voltage regulator is in standby
Stop3 mode — System clocks are stopped and voltage regulator is in standby. All internal circuits
are powered for fast recovery (32 MHz oscillator on-off optional)
1.9.2
Power Management
The MC13234/MC13237 power management is controlled through programming of the modes of
operation. Different modes allow for different levels of power-down. Additional features include:
•
•
•
The transceiver is powered as required
The analog radio is only powered-up as required to do a TX, RX, or CCA/ED operation
Peripheral control clock gating can be disabled on a module-by-module basis to provide lowest
power
•
Programmed mode manages
— Degree of chip power down
— Retention of programmed parameters
— Clock management
•
•
•
•
Power-down and wake-up (clocks and analog blocks) are gracefully controlled
RTC can be used as wake-up timer
Wake-up available through KBI and UART RX asynchronous interrupts
Real-time counter (RTC) module
— 16-bit modulus counter with binary or decimal based prescaler for precise time base,
time-of-day, calendar or task scheduling functions.
— Capable of greater than one day interrupt.
— Can also be used for device wake-up.
1.9.3
System Protection
The MC13234/MC13237 provides several vehicles to maintain security or a high level of system
robustness:
•
Watchdog computer operating properly (COP) reset with option to run from dedicated internal
clock source or bus clock
•
•
•
Low-voltage warning and detection with reset or interrupt; selectable trip points
Illegal opcode detection with reset
Flash block protection
MC13234/MC13237 Reference Manual, Rev. 1.8
1-12
Freescale Semiconductor
MC13237 Introduction
1.10 MCU Peripherals
The MC13234/MC13237 has a functional set of MCU peripherals focused for intended applications:
•
Keyboard interrupt module (KBI) — MC13234 has two (2) KBI modules; KBI1 shares eight (8)
port B pins and KBI2 shares four (4) port C pins. MC13237 has one (1) KBI module; KBI1 shares
eight (8) port B pins. Any KBI pin can be enabled as a keyboard input that can act as an interrupt
request. As a result, the total 12 KBI inputs (MC13234) allows as large as a 12x12 keyboard
matrix. The total 8 KBI inputs (MC13237) allows as large as a 8x8 keyboard matrix with use of
other GPIO pins as outputs to the matrix.
•
•
Serial communication interface (SCI) / UART module
Serial peripheral interface (SPI) module — Fully programmable for full-duplex or single-wire
bidirectional operation, as well as, master or slave mode
•
•
Inter-integrated circuit (IIC) interface — With up to 100 kbps bit-rate
Four (4) timer/pulse width modulators (TMP[4:1]) — With input capture, output compare, and
PWM modes.
•
•
Carrier Modulator Timer (CMT) module — IR remote carrier generator, modulator, and
transmitter.
Real-time counter (RTC) module — 16-bit modulus counter with binary or decimal based prescaler
for precise time base, time-of-day, calendar or task scheduling functions. Capable of greater than
one day interrupt. Can also be used for device wake-up.
•
Up to 32 GPIO — With hysteresis and a pullup device that can be configured on all input pins and
slew rate and drive strength that can be configured on all output pins.
1.11 12-Bit Analog-to-Digital Conversion (ADC) Module
The MC13237 integrates a multi-channel (12 channel), 12-bit resolution Successive Approximation
Register (SAR) analog-to-digital conversion (ADC) module. (The ADC module is not available on the
MC13234.) The analog input channels are shared/multiplexed with standard GPIO pins.
Features of the ADC module include:
•
•
•
•
•
•
•
•
•
•
•
•
Linear successive approximation algorithm with 12-bits resolution
Operational in Stop3 mode
2.5 s conversion time
Internal bandgap reference
Operation over full VBATT voltage range
Internal 1.7 mV/°C temperature sensor
Output data can be formatted in 8-, 10-, or 12-bit justified format
Single or continuous conversion
Configurable sample time and conversion speed / power.
Auto compare for less-than, greater than, or equal to programmable value
Converter subsystem shut-down
Real-time clock conversion trigger
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
1-13
MC13237 Introduction
1.12 Development Environment
Development support for the HCS08 on the MC13234/MC13237 includes the background debug
controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface
to the MCU that provides a convenient interface for programming the on-chip flash and other storage. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
Address and data bus signals are not available on external pins. Debug is done through commands fed into
the MCU via the single-wire background debug interface. The debug module provides a means to
selectively trigger and capture bus information so an external development system can reconstruct what
happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data
signals. Features include:
•
•
Single-wire background debug interface
Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two
more breakpoints in on-chip debug module)
•
•
On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger
modes.
Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module
supports both tag and force breakpoints.
MC13234/MC13237 Reference Manual, Rev. 1.8
1-14
Freescale Semiconductor
Chapter 2
Pins and Connections
2.1
Device Pin Assignment
46
44
41 40
45
48 47
43 42
39 38 37
36
PTA0/XTAL_32K
PTA1/EXTAL_32K
RESET
1
2
3
EXTAL_32M
XTAL_32M
35
34
33
32
31
PTD7
4
PTA2
PTA3/IRQ
PTD6/RXD
PTD5/TXD
5
6
7
PTA4/XTAL_32KOUT
PTA5/SDA
PTD4/CMT
PTD3/TPM3
PTD2/TPM2
MC13234CHT
30
29
PTA6/SCL
PTA7/BKGD/MS
PTB0/KBI1P0
8
9
PTD1/TPM1
28
27
26
25
10
11
12
PTD0/TPM0
PTC7/MOSI
PTB1/KBI1P1
PTB2/KBI1P2
PTC6/MISO
19
13
16
18
20
23 24
14 15
21 22
17
Figure 2-1. MC13234 Pinout
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
2-1
Pins and Connections
48
46
44
41 40
45
47
43 42
39 38 37
36
PTA0/XTAL_32K
1
2
3
EXTAL_32M
XTAL_32M
PTA1/EXTAL_32K
RESET
35
34
33
32
31
PTD7/AD6
4
PTA2
PTA3/IRQ
PTD6/RXD/AD5
PTD5/TXD/AD4
5
6
7
PTA4/XTAL_32KOUT
PTA5/SDA
PTD4/CMT/AD3
PTD3/TPM3/AD2
PTD2/TPM2/AD1
MC13237CHT
30
29
PTA6/SCL
PTA7/BKGD/MS
PTB0/KBI1P0
8
9
PTD1/TPM1/AD0
28
27
26
25
10
11
12
PTD0/TPM0
PTC7/MOSI
PTB1/KBI1P1
PTB2/KBI1P2
PTC6/MISO
19
13
16
18
20
23 24
14 15
21 22
17
Figure 2-2. MC13237 Pinout
MC13234/MC13237 Reference Manual, Rev. 1.8
2-2
Freescale Semiconductor
Pins and Connections
2.2
Pin Definitions
Table 2-1 details the MC13234 pinout and functionality.
Table 2-1. MC13234 Pin Function Description
Pin #
Pin Name
Type Description
Functionality
1
PTA0/XTAL_32K
Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator
output
2
3
4
PTA1/EXTAL_32K
RESET
Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator input For normal use, 10 kOhm resistor
to ground recommended
Digital Input/Output Device asynchronous hardware reset. Normally input; gets driven low for
Active low. Onboard Pullup
a period after a reset
PTA2
Digital Output
Port A Bit 2 / Test Mode enable.
TM mode input. Must be biased
low exiting POR for normal
operation
5
6
PTA3/IRQ
Digital Input/Output Port A Bit 3 / IRQ.
PTA4/
Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz clock Optional 32.768 kHz output clock
XTAL_32KOUT
output
for measuring 32 kHz oscillator
accuracy (ppm)
7
8
9
PTA5/SDA
Digital Input/Output Port A Bit 5 / IIC Bus data
Digital Input/Output Port A Bit 6 / IIC Bus clock
Defaults to open drain for IIC
Defaults to open drain for IIC
PTA6/SCL
PTA7/BKGD/MS
Digital Input/Output Port A Bit 7 / Background / Mode Select Debug signal
10 PTB0/KBI1P0
11 PTB1/KBI1P1
12 PTB2/KBI1P2
13 PTB3/KBI1P3
14 PTB4/KBI1P4
15 PTB5/KBI1P5
16 PTB6/KBI1P6
17 PTB7/KBI1P7
18 PTC0/KBI2P0
19 VBATT_4
Digital Input/Output Port B Bit 0 / KBI1 Input Bit 0
Digital Input/Output Port B Bit 1 / KBI1 Input Bit 1
Digital Input/Output Port B Bit 2 / KBI1 Input Bit 2
Digital Input/Output Port B Bit 3 / KBI1 Input Bit 3
Digital Input/Output Port B Bit 4 / KBI1 Input Bit 4
Digital Input/Output Port B Bit 5 / KBI1 Input Bit 5
Digital Input/Output Port B Bit 6 / KBI1 Input Bit 6
Digital Input/Output Port B Bit 7 / KBI1 Input Bit 7
Digital Input/Output Port C Bit 0 / KBI2 Input Bit 0
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Power Input
VDD supply input 1
Connect to system VDD supply
20 PTC1/KBI2P1
21 PTC2/KBI2P2
22 PTC3/KBI2P3
23 PTC4/SPICLK
24 PTC5/SS
Digital Input/Output Pot C Bit 1 / KBI2 Input Bit 1
Digital Input/Output Pot C Bit 2 / KBI2 Input Bit 2
Digital Input/Output Pot C Bit 3 / KBI2 Input Bit 3
Digital Input/Output Port C Bit 4 / SPI clock
Digital Input/Output Port C Bit 5 / SPI slave select
Digital Input/Output Port C Bit 6 / SPI MISO
Digital Input/Output Port C Bit 7 / SPI MOSI
Digital Input/Output Port D Bit 0 / TPM0 signal
25 PTC6/MISO
26 PTC7/MOSI
27 PTD0/TPM0
TPM0 timer output / gate input
signal
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
2-3
Pins and Connections
Table 2-1. MC13234 Pin Function Description (continued)
Type Description
Pin #
Pin Name
Functionality
28 PTD1/TPM1
Digital Input/Output Port D Bit 1/ TPM1 signal
Digital Input/Output Port D Bit 2 / TPM2 signal
Digital Input/Output Port D Bit 3 / TPM3 signal
TPM1 timer output / gate input
signal.
29 PTD2/TPM2
30 PTD3/TPM3
TPM2 timer output / gate input
signal.
TPM3 timer output / gate input
signal.
31 PTD4/CMT
32 PTD5/TXD
Digital Input/Output Port D Bit 4 / CMT output
Hi drive output for IR diode.
Digital Input/Output Port D Bit 5 / UART TXD output
UART has no hardware flow
control.
33 PTD6/RXD
Digital Input/Output Port D Bit 6 / UART RXD input / AD5
signal
UART has no hardware flow
control.
34 PTD7
Digital Input/Output Port D Bit 7
35 XTAL_32M
36 EXTAL_32M
37 VBATT_3
38 VREG_VCO
Analog Output
Analog input
32 MHz reference oscillator output
32 MHz reference oscillator input
VDD supply input1
Power Input
Connect to system VDD supply
VCO Reg Out / in
VCO regulator output and input to VCO Bypass to ground with 220 nF
1.8 Vdc VDD
capacitor.
39 VDD_ANA
40 NC
Analog Power Input Analog 1.8 Vdc Input
No connection to device
Connect to VREG_ANA
May be left open or connect to
ground
41 RF_N
42 RF_P
RF Input/Output
RF Input/Output
Modem RF input/output negative
Modem RF input/output positive
Bi-directional RF port for the
internal LNA and PA
Bi-directional RF port for the
internal LNA and PA
43 RF_BIAS
44 VBATT_2
45 NC
RF Voltage Output Switched RF bias voltage (1.8 Vdc)
High for TX; low for RX
Power Input
VDD supply input1
Connect to system VDD supply
May be left open or connect to
ground
46 VREG_LO2
47 VREG_ANA
LO2 Reg Out
ANA Reg Out
LO2 regulator output @ 1.8 Vdc
Analog regulator output @ 1.8 Vdc
Bypass to ground with 220 nF
capacitor.
Bypass to ground with 220 nF
capacitor. Connect to VDD_ANA
48 VBATT_1
Flag GND
Power Input
Power Input
VDD supply to Analog regulator1
System ground
Connect to system VDD supply
1
VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13234/MC13237.
MC13234/MC13237 Reference Manual, Rev. 1.8
2-4
Freescale Semiconductor
Pins and Connections
Table 2-2 details the MC13237 pinout and functionality.
Table 2-2. MC13237 Pin Function Description
Pin #
Pin Name
Type Description
Functionality
1
PTA0/XTAL_32K
Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator
output
2
3
4
PTA1/EXTAL_32K
RESET
Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator
input
For normal use, 10 kOhm resistor
to ground recommended
Digital Input/Output Device asynchronous hardware reset. Normally input; gets driven low for
Active low. Onboard Pullup
a period after a reset
PTA2
Digital Output
Port A Bit 2 / Test Mode enable.
TM mode input. Must be biased
low exiting POR for normal
operation
5
6
PTA3/IRQ
Digital Input/Output Port A Bit 3 / IRQ.
PTA4/
XTAL_32KOUT
Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz
clock output
Optional 32.768 kHz output clock
for measuring 32 kHz oscillator
accuracy (ppm)
7
8
9
PTA5/SDA
Digital Input/Output Port A Bit 5 / IIC Bus data
Digital Input/Output Port A Bit 6 / IIC Bus clock
Defaults to open drain for IIC
Defaults to open drain for IIC
Debug signal
PTA6/SCL
PTA7/BKGD/MS
Digital Input/Output Port A Bit 7 / Background / Mode
Select
10 PTB0/KBI1P0
11 PTB1/KBI1P1
12 PTB2/KBI1P2
13 PTB3/KBI1P3
14 PTB4/KBI1P4
15 PTB5/KBI1P5
16 PTB6/KBI1P6
17 PTB7/KBI1P7
18 PTC5/SS/AD7
Digital Input/Output Port B Bit 0 / KBI1 Input Bit 0
Digital Input/Output Port B Bit 1 / KBI1 Input Bit 1
Digital Input/Output Port B Bit 2 / KBI1 Input Bit 2
Digital Input/Output Port B Bit 3 / KBI1 Input Bit 3
Digital Input/Output Port B Bit 4 / KBI1 Input Bit 4
Digital Input/Output Port B Bit 5 / KBI1 Input Bit 5
Digital Input/Output Port B Bit 6 / KBI1 Input Bit 6
Digital Input/Output Port B Bit 7 / KBI1 Input Bit 7
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Digital Input/Output Port C Bit 5 / SPI Slave Select / AD7
Signal
19 VBATT_4
20 VSSA_ADC
21 VREFL
Power Input
VDD supply input 1
Connect to system VDD supply
Digital Input/Output ADC analog ground
Digital Input/Output ADC low reference voltage
Digital Input/Output ADC high reference voltage
Digital Input/Output ADC analog power supply
Digital Input/Output Port C Bit 4 / SPI Clock
Digital Input/Output Port C Bit 6 / SPI MISO
Digital Input/Output Port C Bit 7 / SPI MOSI
Digital Input/Output Port D Bit 0 / TPM0 signal
22 VREFH
23 VDDA_ADC
24 PTC4/SPICLK
25 PTC6/MISO
26 PTC7/MOSI
27 PTD0/TPM0
TPM0 timer output / gate input
signal
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
2-5
Pins and Connections
Table 2-2. MC13237 Pin Function Description (continued)
Type Description
Pin #
Pin Name
Functionality
28 PTD1/TPM1/AD0
29 PTD2/TPM2/AD1
30 PTD3/TPM3/AD2
31 PTD4/CMT/AD3
32 PTD5/TXD/AD4
33 PTD6/RXD/AD5
Digital Input/Output Port D Bit 1/ TPM1 signal /AD0 signal TPM1 timer output / gate input
signal. ADC input 0
Digital Input/Output Port D Bit 2 / TPM2 signal /AD1 signal TPM2 timer output / gate input
signal. ADC input 1
Digital Input/Output Port D Bit 3 / TPM3 signal /AD2 signal TPM3 timer output / gate input
signal. ADC input 2
Digital Input/Output Port D Bit 4/ CMT output / AD3 signal Hi drive output for IR diode. ADC
input 3
Digital Input/Output Port D Bit 5 / UART TXD output / AD4 UART has no hardware flow
signal
control. ADC input 4
Digital Input/Output Port D Bit 6 / UART RXD input / AD5 UART has no hardware flow
signal
control. ADC input 5
ADC input 6
34 PTD7/AD6
35 XTAL_32M
36 EXTAL_32M
37 VBATT_3
Digital Input/Output Port D Bit 7 / AD6 signal
Analog Output
Analog input
32 MHz reference oscillator output
32 MHz reference oscillator input
VDD supply input1
Power Input
Connect to system VDD supply
38 VREG_VCO
VCO Reg Out / in
VCO regulator output and input to
VCO 1.8 Vdc VDD
Bypass to ground with 220 nF
capacitor.
39 VDD_ANA
40 NC
Analog Power Input Analog 1.8 Vdc Input
No connection to device
Connect to VREG_ANA
May be left open or connect to
ground
41 RF_N
42 RF_P
RF Input/Output
RF Input/Output
Modem RF input/output negative
Modem RF input/output positive
Bi-directional RF port for the
internal LNA and PA
Bi-directional RF port for the
internal LNA and PA
43 RF_BIAS
44 VBATT_2
45 NC
RF Voltage Output Switched RF bias voltage (1.8 Vdc)
High for TX; low for RX
Power Input
Input
VDD supply input1
Connect to system VDD supply
No connection to device
May be left open or connect to
ground
46 VREG_LO2
47 VREG_ANA
LO2 Reg Out
ANA Reg Out
LO2 regulator output @ 1.8 Vdc
Analog regulator output @ 1.8 Vdc
Bypass to ground with 220 nF
capacitor.
Bypass to ground with 220 nF
capacitor. Connect to VDD_ANA
48 VBATT_1
Flag GND
Power Input
Power Input
VDD supply to Analog regulator1
System ground
Connect to system VDD supply
1
VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13234/MC13237.
MC13234/MC13237 Reference Manual, Rev. 1.8
2-6
Freescale Semiconductor
Chapter 3
System Considerations
3.1
Introduction
This chapter presents information on application and operation of the MC13234/MC13237 from a system
level. The areas considered here are also covered in greater detail in the following sections of the book.
The book is organized such that the first three chapters present the top-level view of the
MC13234/MC13237 device and the following chapters present individual functions in detailed
descriptions.
3.2
Power Connections
The MC13234/MC13237 power connections are listed in Table 3-1.
Table 3-1. Power Pin Descriptions
Pin #
Pin Name
VBATT_4
Type
Description
VDD supply input 1
Functionality
19
20
23
Power Input
Connect to system VDD supply
ADC ground
VSSA_ADC2
VDDA_ADC2
Digital Input/Output ADC analog ground
Power Input
ADC analog power supply
Connect to system VDD supply
or dedicated supply for ADC
block
37
38
VBATT_3
Power Input
VDD supply input1
Connect to system VDD supply
VREG_VCO
VCO Reg Out / In
VCO regulator output and input to
VCO 1.8 Vdc VDD
Bypass to ground with 220 nF
capacitor.
39
43
44
46
VDD_ANA
RF_BIAS
Analog Power Input Analog 1.8 Vdc Input
Connect to VREG_ANA
High for TX; low for RX
RF Voltage Output Switched RF bias voltage (1.8 Vdc)
VBATT_2
VREG_LO2
Power Input
VDD supply input1
Connect to system VDD supply
LO2 Reg Out
LO2 regulator output @ 1.8 Vdc
Bypass to ground with 220 nF
capacitor.
47
VREG_ANA
ANA Reg Out
Analog regulator output @ 1.8 Vdc
Bypass to ground with 220 nF
capacitor. Connect to VDD_ANA
48
VBATT_1
Power Input
Power Input
VDD supply to Analog regulator1
System ground
Connect to system VDD supply
Flag GND
1
2
VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13237.
VSSA_ADC, VDDA_ADC are available only in the MC13237.
When designing power to the MC13234/MC13237 LGA, the following points need to be considered:
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-1
System Considerations
•
•
The LGA package has a single common ground flag (VSS).
The device has four primary power inputs that include VBATT_1, VBATT_2, VBATT_3 and
VBATT_4 signals
— These are not connected onboard.
— These must be connected to a common source supply of 1.8–3.6 Vdc.
NOTE
Although the MC13234/MC13237 can operate at VDD supply as low as 1.8
Vdc, it is not recommended to be a regulated supply at 1.8 Vdc. The
low-voltage detect (LVD) reset is enabled out of POR and the power supply
voltage must rise and exceed the LVD rising-edge threshold or the device
will be held in reset. After the rising edge threshold is exceeded, the reset is
released.
•
•
•
•
VREG_ANA must be tied to VDD_ANA and bypassed with a 220 nF capacitor.
VREG_LO2 and VREG_VCO must each be bypassed by a 220 nF capacitor.
The LGA FLAG is the device ground connection and must be tied to supply GND.
RF_BIAS is a bias voltage for the RF balun that switches between 1.8 Vdc for transmit and ground
for receive.
Power supply connections are shown in Figure 3-1.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-2
Freescale Semiconductor
System Considerations
Figure 3-1. MC13234 Power Supply Connections
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-3
System Considerations
Figure 3-2. MC13237 Power Supply Connections
NOTE
The 220 nF bypass capacitors are required by onboard series voltage
regulators
3.3
Special Pin Usage
The following signal pins have special usage.
3.3.1
Hardware RESET Pin
Device signal RESET is a dedicated IO pin with a built-in pullup device. It has input hysteresis, a high
current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset
circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the
standard 6-pin background debug connector so a development system can directly reset the MCU system.
If desired, a manual external reset can be added by supplying a simple switch to ground.
A system reset can be initiated externally or internally:
•
External reset — the RESET pin can be driven low from an external switch to ground or driven
from a device output. If RESET is driven from an external IO (such as a master MCU), the IO
MC13234/MC13237 Reference Manual, Rev. 1.8
3-4
Freescale Semiconductor
System Considerations
should be open drain or buffered in such a manner as to not drive RESET active high at the same
time that the onboard circuitry is driving the pin active low during an internally generated reset. A
Schottky diode in series between a standard active high output and the RESET input can be used
to block the output from driving high.
NOTE
If RESET is held active for more than 69 bus clock cycles, the reference
oscillator will be disabled. See Section 5.4.1, “Clock Sources”.
•
Internal reset — if reset is initiated internally the RESET pin is driven low for about 34 cycles of
the default bus clock (16 MHz); this equates to approximately 2 microseconds. The output low
condition can be used to reset any external system components. As stated previously, an external
driver must not hold the signal high to prevent this internally initiated low condition. The onboard
output drive is open drain and relies on the pullup to pull the RESET pin high again. The reset pin
is sampled approximately 38 cycles later and expects reset to return high. The reset circuitry
decodes the onboard cause of reset and records it by setting a corresponding bit in the system
control reset status register (SRS).
NOTE
A reset initiated by the RESET pin or any other operation condition does not
cycle the POR circuit. The POR reset is only cycled by transitions on the
VDD supply.
Figure 3-3 illustrates RESET signal timing. If reset is driven externally, the active low time is set by the
source and can be held indefinitely. Upon release, the rise time should be the RC time constant as
determined by the total pin load capacitance and the pullup (the external driver should not actively drive
the pin high). An external pullup is not required as an onboard pullup is present. If the reset is driven by
the onboard driver, the active low time will be approximately 2 µs, and once released, the rise time is again
determined by the RC time constant.
Set by source
~2 us
RC
RESET
Externally driven
Internally driven
Figure 3-3. RESET Signal Timing
When RESET is active, the current is very low, but the MC13234/MC13237 is not totally disabled as in a
programmed low power state.
3.3.2
Signal PTA2 (Factory Test Mode Enable)
Signal PTA2 is also an enable for a reserved factory test mode (see Section 9.3, “IO Port Pin Functional
Description”). During a POR reset, signal PTA2 is an input and should not be driven high or test mode will
be entered when POR is released. Good design practice is to tie PTA to ground through an external
pulldown resistor.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-5
System Considerations
Although I/O signal PTA2 is controlled as any other Port A signal it is suggested that PTA2 be limited to
use as an output and be used only when required by applications needing the extra GPIO output.
3.3.3
MCU Background/Mode Select (PTA7/BKGD/MS)
The Background/Mode Select (BKGD/MS) shares its function with the MCU I/O port pin PTA7. While in
reset, the pin functions as a mode select pin. Immediately after RESET rises, the pin functions as the
background pin and can be used for background debug communication. While functioning as a
Background/Mode Select pin, the pin includes an internal pullup device, input hysteresis, a standard output
driver, and no output slew rate control. When used as an I/O port is becomes PTA7.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to Active Background Mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCUs BDC clock per bit time. The target MCUs BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
3.4
External Clock Connections
The MC13234/MC13237 provides the following clock sources:
•
32 MHz Reference Oscillator - all active clocks for the radio, CPU, and peripherals are derived
from the reference oscillator. An external 32 MHz crystal is most commonly used with the
reference oscillator, although an external clock source can be used.
•
•
Onboard 1 kHz RC Oscillator - low power oscillator used for RTC and to wake-up from low power
Optional 32.768 kHz Crystal Oscillator - used in place of the onboard 1 kHz oscillator for the RTC
and to wake-up from low power.
The reference oscillator and the optional 32.768 kHz crystal oscillator require external connections which
are shown in Figure 3-5.
MC1323x
EXTAL_32K
XTAL_32K
EXTAL_32M
XTAL_32M
36
35
1
2
X1
CL2
12pF
CL4
22pF
CL1
12pF
CL3
22pF
X2
32.000 MHz
32.768 KHz
Figure 3-4. MC13234/MC13237 External Clock Connections
MC13234/MC13237 Reference Manual, Rev. 1.8
3-6
Freescale Semiconductor
System Considerations
3.5
32 MHz Reference Oscillator
The reference oscillator must always be functional and can use an external crystal or an external source.
3.5.1
Description
The reference oscillator is shown in Figure 3-5. It has an amplifier block with Amplitude Level Control
(ALC) to optimize power consumption and help startup. It uses an off-chip 32 MHz crystal and has internal
programmable trim load capacitors. The primary load capacitors are external.
The external load capacitors CL1 and CL2 are typically in the 5 pF to 15 pF range and are determined by
the requirements of the specific crystal. The manufacturer will specify the load capacitance and the
external capacitors selected for CL1 and CL2 are used to match the stray circuit capacitance (the pin and
PCB capacitance) to the required load capacitance. The onboard capacitors consist of two arrays on each
pin, each trimmable by a 4-bit control field. The larger or coarse array can be from 0 - 4.215 pF with steps
of 281 fF. The smaller or fine array can be from 0 - 300 fF with steps of 20 fF.
REFERENCE
OSCILLATOR
32 MHz
MC1323x
Coarse Tune [3:0]
Coarse Tune [3:0]
0-4.215 pF
0-4.215 pF
with steps of 281 fF.
with steps of 281 fF.
Fine Tune [3:0]
Fine Tune [3:0]
0-300 fF
0-300 fF
with steps of 20 fF.
with steps of 20 fF.
EXTAL_32M
XTAL_32M
Y1
CRYSTAL
CL1
Cstray
Cstray
CL2
Figure 3-5. 32MHz Reference Oscillator Model
3.5.2
32 MHz Crystal Specifications
The IEEE 802.15.4 Standard requires a frequency tolerance less than or equal to +/- 40 ppm. With a
suitable crystal (see Table 3-2), the device frequency tolerance can typically be trimmed to be less than +/-
30 ppm over all conditions.
Table 3-2. Recommended 32 MHz Crystal Specifications
Parameter
Value
Unit
Condition
Frequency
Frequency tolerance (cut tolerance)
32.000000
± 10
MHz
ppm
max at 25 °C
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-7
System Considerations
Table 3-2. Recommended 32 MHz Crystal Specifications (continued)
Parameter
Value
Unit
Condition
Frequency stability (temperature drift)
Aging
± 16-18
± 2
60
ppm
ppm
Over desired temperature range
max
Equivalent series resistance
Load capacitance
max
9
pF
max
Shunt capacitance
<2
pF
max
Mode of oscillation
fundamental
3.5.3
32 MHz Crystal Trimming
The MC13234/MC13237 reference oscillator frequency can be trimmed (via changing the load
capacitance) through programming the System Oscillator Management and Control Register 2
(XTAL1_TRIM[7:0]) as described in Section 5.8.11, “System Oscillator Management and Control
Register 2 (SOMC2)”. The XTAL1_TRIM[7:0] field has two control fields that set the trimming.
•
XTAL1_TRIM[7:4] — selects course load capacitance; selects from 0–4.215 pF in 15 steps of
approximately 281 fF
•
XTAL_FTUNE[3:0] — selects fine tuning for load capacitance; selects from 0–300 fF in 15 steps
of approximately 20 fF
The trimming procedure varies the frequency where as the trim value is increased, the frequency is
decreased. This feature is useful to set the crystal frequency for the radio accuracy as required by the IEEE
802.15.4 specification.
Figure 3-6 and Figure 3-7 illustrate the variation is oscillator frequency vs. capacitive loading for a 9pF
C crystal.
L
•
For Figure 3-6 the external load capacitors are present and the fine tune is centered while the course
tune array is varied. The rate of frequency change is about 125 Hz per step.
•
For Figure 3-7 the external load capacitors are present and the course tune is centered while the
fine tune array is varied. The rate of frequency change is about 11 Hz per step.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-8
Freescale Semiconductor
System Considerations
32 MHz Reference Oscillator Frequency vs Coarse Trim
32001500
32001000
32000500
32000000
31999500
31999000
0
2
4
6
8
10
12
14
16
Coarse Trim
Figure 3-6. Typical MC13234/MC13237 Reference Oscillator Variation vs. XTAL1_TRIM[7:4]
(XTAL1_TRIM[3:0] = 0x7 and external load capacitors are present)
32 MHz Reference Oscillator Frequency vs Fine Tune
32000140
32000120
32000100
32000080
32000060
32000040
32000020
32000000
31999980
31999960
31999940
0
2
4
6
8
10
12
14
16
Fine Tune
Figure 3-7. Typical MC13234/MC13237 Reference Oscillator Variation vs. XTAL1_TRIM[3:0]
(XTAL1_TRIM[7:4] = 0x7 and external load capacitors are present)
A MC13234/MC13237 timer module (TPMx) output can be enabled by software to make measurements
via a frequency counter to trim the reference oscillator.
NOTE
•
•
Good design practice dictates that external capacitors be selected to
nominally center the reference frequency with the trim capacitance set
for mid-range
Good design practice also dictates that a user characterize their board to
find nominal trim settings based on their crystal, layout, and pcb
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-9
System Considerations
characteristics. This should be done with a number of board examples to
center the trim values across board variation
•
With device-to-device and crystal variation, individual module trim at
manufacture and test may be required.
3.6
32.768 kHz Crystal Oscillator (Optional)
The 32.768 kHz oscillator is strictly optional. The 32 kHz oscillator adds cost to a design, but is much more
accurate than the onboard 1kHz oscillator.
The use of the 32.768 kHz oscillator versus the onboard 1 kHz oscillator is controlled via a register in the
CRM (see Chapter 5, “System Management and Control”).
3.6.1
Description
The MC13234/MC13237 has a built-in 32 kHz crystal oscillator with an ALC feature. It uses an external
32.768 kHz crystal with a load capacitance of 12–16 pF. The load capacitors are external.
Figure 3-8 shows the user oscillator model. The model shows that there are external load capacitors for the
oscillator crystal. On each leg of the oscillator (XTAL_32K and EXTAL_32K) there is:
•
•
A fixed C capacitor
L
Stray capacitance - sum of pad, package, and trace capacitance (typically ~1.5pF)
The load capacitance C to the crystal is symmetric and equals 1/2 (C + C
). Target load capacitance
L
L
stray
is 12–16 pF and is determined by the crystal specification.
32.768 kHz
OSCILLATOR
MC1323x
Feedback
OSC_IN
OSC_OUT
Y1
CRYSTAL
Cstray1
CL1
CL2
Cstray2
Figure 3-8. MC13234/MC13237 32.768 kHz Oscillator Model
3.6.2
32.768 kHz Crystal Specifications
Table 3-3 lists the recommended crystal specifications.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-10
Freescale Semiconductor
System Considerations
Table 3-3. 32.768 kHz Recommended Crystal Specification
Parameter Name
Crystal frequency
Minimum
Typical
Maximum
Units
32.768
± 20
kHz
ppm
ppm
Frequency tolerance @ 25 °C1
Frequency tolerance with temperature1
Load capacitance
12
12.5
16
35
pF
k
pF
Equivalent series resistance (ESR)
Shunt capacitance
1.35
1
Tolerated drive level
W
1
Determined by customer desired frequency accuracy
3.7
Device Version ID
Bit[1,0] of SOPT2 register provide the device IDs for MC13234 and MC13237. See Section 5.8.5,
“System Options Register 2 (SOPT2)” for details.
3.8
MC13234/MC13237 GPIO
The MC13234/MC13237 supports up to a total of 32 GPIO pins:
•
•
•
•
•
•
MC13234: 32 GPIO pins; MC13237: 28 GPIO pins
Pins have hysteresis inputs and configurable pullup device on all input pins
Configurable slew rate and drive strength on all output pins.
PTA2 is also a factory test mode enable.
PTA3 is unavailable if used as IRQ
If a 32.768 kHz crystal is used, PTA0/XTAL_32K and PTA1/EXTAL_32K pins cannot be used as
GPIO.
•
•
PTA4/XTAL_32KOUT is an optional 32 kHz clock output signal
PTA7/BKGD/MS is not commonly used as GPIO because it is dedicated to the MCU debug port
(BDM) and is an output only when used as GPIO
3.8.1
GPIO Characteristics
The GPIO hardware consists of four ports, A, B, C, and D. Each port consists of 8 signals (except for
MC13237, port C only has 4 signals). With RESET active and immediately after exiting reset, all I/O pins
default to high-impedance inputs with internal pullup devices disabled.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-11
System Considerations
NOTE
To avoid extra current drain from floating input pins, the device
initialization routine in the application program should either enable
on-chip pullup devices or change the direction of unused pins to outputs
(programmed low) so the pins do not float. See Section Chapter 9, “Parallel
Input and Output”).
Most of these pins share functionality with MCU peripheral functions. For information about controlling
these pins as general-purpose I/O pins, see Section Chapter 9, “Parallel Input and Output”. For information
about how and when on-chip peripheral systems use these pins, see the appropriate section from Table 3-4.
Table 3-4. MC13234/MC13237 Pin Sharing References
1
Port Pins
Alternate Function
Reference
PTA1–PTA0
PTA3
XTAL_32K–EXTAL_32K Chapter 3, “System Considerations”
IRQ
Chapter 3, “System Considerations”
Chapter 5, “System Management and Control”
Chapter 13, “Inter-integrate Circuit (IIC)”
Chapter 18, “Development Support”
Chapter 11, “Modules (KBIx)”
PTA4
XTAL_32KOUT
SDA–SCL
PTA5–PTA6
PTA7
BKGD/MS
PTB0–PTB7
PTC0–PTC3
KBI1P0–KBI1P7
KBI2P0–KBI2P3
MC13234 only
PTC4
PTC5
PTC6
PTC7
SPICLK
SS_B
MISO
MOSI
Chapter 15, “Serial Peripheral Interface (SPI) Module”
PTD0–PTD3
PTD4
TPM0–TPM3
CMT
Chapter 16, “Timer/PWM (TPM Module)”
Chapter 17, “Carrier Modulator Timer (CMT) Module”
Chapter 14, “Serial Communications Interface (SCI)”
PTD5–PTD6
TXD-RXD
PTD1–PTD7,
PTC5
AD0–AD7
Chapter 12, “Analog-to-Digital Converter (ADC)”
1
See this section for information about modules that share these pins.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See Chapter 9, “Parallel Input and Output” for details.
pullup and pulldown control consists of:
•
pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever
the pin is acting as an input even if it is being controlled by an on-chip peripheral module.
•
When the PTB7–PTB0, PTC3–PTC0 (MC13234 only), pins are controlled by the related KBI
module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits
enable pulldown devices rather than pullup devices.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-12
Freescale Semiconductor
System Considerations
•
When IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control
bit enables a pulldown device rather than a pullup device.
3.8.2
Signal Properties Summary
Table 3-5 summarizes digital I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hard-wired to internal circuits.
.
Table 3-5. MC13234/MC13237 Digital Signal Properties
Pin
Name
High
Current Pin
Output
Slew 1
Dir
pullup2
Comments
MCU SIGNALS
RESET
I
—
N
—
Y
Pin contains integrated pullup.
PTA0/XTAL_32K
I/O
Analog
SWC
SWC
Pullup and slew rate disabled when XTAL pin function.
Pullup and slew rate disabled when EXTAL pin function.
PTA1/EXTAL_32K
PTA2
I/O
Analog
N
N
SWC
SWC
SWC
Y
SPECIAL PIN - ENABLES TEST MODE. Should be
pulled low when exiting POR.
I/O
I/O
I/O
PTA3/IRQ
Enable bit IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to VDD. IRQ should
not be driven above VDD
.
N
N
SWC
SWC
SWC
SWC
Pullup/pulldown active when IRQ pin function enabled.
Pullup forced on when IRQ enabled for falling edges;
pulldown forced on when IRQ enabled for rising edges.
Internal connection.
PTA4/
XTAL_32KOUT
PTA5/SDA
PTA6/SCL
I/O
I/O
O
N
N
N
SWC
SWC
SWC
SWC
SWC
SWC
PTA7/BKGD/MS
Pullup enabled and slew rate disabled when BDM
function enabled.
PTB0/KBI1P0
PTB1/KBI1P1
PTB2/KBI1P2
PTB3/KBI1P3
PTB4/KBI1P4
PTB5/KBI1P5
PTB6/KBI1P6
PTB7/KBI1P7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N
N
N
N
N
N
N
N
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
Pullup/pulldown active when KBI pin function enabled.
Pull-p forced on when KBI1Px enabled for falling edges;
pulldown forced on when KBI1Px enabled for rising
edges.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-13
System Considerations
Table 3-5. MC13234/MC13237 Digital Signal Properties (continued)
Pin
Name
High
Current Pin
Output
Slew 1
Dir
pullup2
Comments
PTC0/KBI2P0
PTC1/KBI2P1
PTC2/KBI2P2
PTC3/KBI2P3
PTC4/SPICLK
PTC5/SS_B
PTC6/MISO
PTC7/MOSI
PTD0/TPM0
PTD1/TPM1
PTD2/TPM2
PTD3/TPM3
PTD4/CMT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
MC13234 only.
20 mA drive high or low
PTD5/TXD
PTD6/RXD
PTD7
1
SWC is software controlled slew rate, the register is associated with the respective port.
SWC is software controlled pullup resistor, the register is associated with the respective port.
2
3.9
Transceiver RF Operation
The MC13234/MC13237 transceiver provides a simple RF interface with the following characteristics:
•
•
•
Onboard Transmit/Receive (T/R) switch and LNA
Two-pin bidirectional, differential RF port
RF_Bias — switched 1.8 Vdc (VREG_ANA) bias reference for use with an external balun.
An internal integrated RX switch and TX power amplifier (PA) are used, and pins RF_P and RF_N are
bidirectional and connect both for TX and RX. When receiving, the RX switch is enabled to the internal
LNA and the TX PA is disabled. When transmitting, the RX switch is disabled (isolating the LNA) and the
TX PA is enabled. RF_Bias pin provides a reference or bias voltage which is at 1.8 V for transmit and is
at ground for receive. This signal can be used to provide the proper bias voltage to a balun that converts a
single-ended antenna to the differential interface required by the RF device port.
Figure 3-9 shows a typical example with a balun. The RF_Bias is connected to the balun center-tap
providing the proper DC bias voltage to the balun depending on RX or TX.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-14
Freescale Semiconductor
System Considerations
NOTE
Figure 3-9 provides a simple example of an MC13234/MC13237 RF
circuit. For detailed design information, Freescale recommends using
provided reference designs as a starting point.
L1
L2
RF_P
C1
1
1
2
2
Z1
C3
3
2
4
1
5
6
RF_50
C2
RF_ANT
42
41
RF_P
RF_N
10PF
RF_BIAS
L3
ANT1
F_Antenna
43
RF_N
RF_BIAS
RF_BIAS
C6
10PF
MC13233
HARMONIC TRAP
Figure 3-9. RF Operation with a Balun
3.10 Transceiver Indirect Access Register Application Functions
Operation of the indirect access register is described in Section 6.13.33, “Transceiver Indirect Access
Registers (INDEX and DATA)”. These registers are generally reserved, but are used to provide three
application functions:
1. 16-Bit Pseudo-Random Number Generator - see Section 6.11, “Hardware Pseudo-Random
Number Generator”.
2. Set transmit power - the desired transmit power level of the transceiver power amplifier (PA) is set
across three indirect access registers plus the direct access PA_PWR_CNTL Register. This is
described in Section 6.13.25, “Power Amplifier (PA) Power Control Register (PA_PWR_CNTL)”
and Freescale provides a software utility that is called to set desired output power.
3. Controlling the analog voltage regulator for low power operation - the MC13234/MC13237 has
several onboard series voltage regulators, and the primary analog regulator for the radio must be
controlled when entering and exiting lower power modes. Three indirect registers are involved:
— Indirect Address 0x1D - disable default mode of analog regulator; set to value 0x00. This needs
be done only once as part of initialization after a system reset of any kind.
— Indirect Address 0x61 - enable direct control of analog regulator; set value to 0x01. This needs
be done only once as part of initialization after a system reset of any kind.
— Indirect Address 0x60 - provide direct control (on/off) of analog regulator. Set to value 0x01
(enable) to enable analog regulator before normal operation. Set to value 0x00 (disable) before
entering low power operation.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-15
System Considerations
3.11 General System Considerations for Low Power Operation
Low power is most important for battery operated applications such as 802.15.4 End Devices. Although
the MC13234/MC13237 is inherently a low power device, both normal “run” as well as low power or
“sleep” modes can be optimized for lowest net energy usage, i.e., longest battery life. The following
descriptions give guidelines for optimizing lowest power.
NOTE
This discussion is simply an overview of run and low power mode
considerations. The user should become familiar with the referenced
document material to understand detailed control and operation of the
MC13234/MC13237 when running and entering/exiting low power modes.
3.11.1 Run Mode Considerations
Run mode current is dominated by the operating frequency of the MCU and its peripherals and the
transceiver (radio) over-the-air RF activity (transmit, receive, and CCA/ED cycles). To minimize current
usage:
1. Disable bus clocks to all unused peripherals - see Section 5.8.12, “System Clock Gating Control 1
Register (SCGC1)” and Section 5.8.13, “System Clock Gating Control 2 Register (SCGC2)”.
2. Consider running at a lower CPU/bus clock frequency - see Section 5.8.10, “System Oscillator
Management and Control Register 1 (SOMC1)”.
— Programming a lower run frequency impacts peripheral baud rates and speeds, as well as
application performance. It is the user’s responsibility to account for these changes when
operating at the lower frequency.
— Flash can be erased and programmed only at full CPU/bus clock rate (32MHz/16MHz)
3. If possible, minimize transceiver “on” time - this is most likely to be receiver “on” time. Evaluate
protocol usage to minimize receiver activity if possible.
3.11.2 Low Power Mode Considerations
NOTE
This discussion is primarily an overview of low power mode considerations.
The user is directed to Section 5.7.6, “Stop3 Mode” and Section 5.7.7,
“Mode Selection” for additional detailed information.
Depending on use model, the low power mode can dominate overall current usage. Low power
considerations include:
1. All GPIO must be configured for low power operation -
— Configure all unused GPIO - see Section 3.8.1, “GPIO Characteristics”
— Some GPIO may need to be re-configured when entering/exiting low power mode - this is to
assure that there is no excess current usage.
2. Wake-up is possible from -
— Push button operation via KBI interrupt request
MC13234/MC13237 Reference Manual, Rev. 1.8
3-16
Freescale Semiconductor
System Considerations
— Timer operation using the Real Time Counter (RTC)
— UART receive activity via an RXD transition interrupt request
3. When using the RTC -
— If the wake-up time period can vary by approximately +/-40% use the internal 1 kHz oscillator.
This has lowest power and lowest cost
— If the wake-up time period must be crystal accurate, use the external clock option for the RTC
timer with a 32.768 kHz crystal. This has the advantage of crystal accuracy and the
disadvantage of higher cost.
4. Stop3 mode - see Section 5.7.6, “Stop3 Mode”
— Actual wake-up time from low power to run mode is less than 1 ms - see data sheet
(MC13237.pdf)
— The analog regulator must be disabled for lowest power in Stop3 - see Section 3.10,
“Transceiver Indirect Access Register Application Functions”
5. Best practice is to disable the MCU low voltage detect (LVD) during low power mode. Transition
between Low-Power Run mode and Stop3 mode needs extra steps. See Section 5.7.6.6, “Stop3 and
LPRun Mode Transition”
— LVD is only available for Stop3 mode
— Use LVD only if required.
— LVD current usage penalty is significant - see data sheet (MC13237.pdf)
3.11.3 Entering/Exiting Low Power Mode
The following flow summarizes application steps for entering low power from a run condition:
1. Exit any stack/application gracefully - save any required parameters, shut down any tasks that are
affected.
2. As required configure any GPIO for low power operation -it is assumed that during system
initialization, any unused GPIO are configured properly so as to not cause excess leakage current.
At this point, re-configure any GPIO in use that may special handling during low power so as to
not cause excess leakage.
3. Disable the transceiver analog regulator if required - see Section 3.10, “Transceiver Indirect
Access Register Application Functions”.
4. Disable any active peripheral clocks.
5. Initiate any required wake-up sources / interrupts - choosing means and clocks as previously
recommended.
6. Clear LVW/LVD as required.
7. Prepare “Stop” mode conditions in System Control Registers, see Section 5.8, “System Control
Register Definitions”. This includes setting the Stop Enable bit.
8. Execute a STOP instruction.
Recovery from Stop3 is from a “suspended” state (registers and RAM were retained) and resumes as an
interrupt service routine as triggered by the wake-up source. In this situation, recovery code typically does
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
3-17
System Considerations
not use normal system initialization. The recovery code must restore any conditions (such as GPIO usage)
to pre-sleep operation.
MC13234/MC13237 Reference Manual, Rev. 1.8
3-18
Freescale Semiconductor
Chapter 4
Memory
4.1
MC13234/MC13237 Memory Map
As shown in Figure 4-1, MC13234/MC13237 on-chip memory consists of RAM, flash program memory
for nonvolatile program and data storage, and I/O and control/status registers:
•
•
•
8064 Bytes of RAM, divided into two blocks (6016 Bytes and 2048 Bytes)
131072 Bytes of flash — organized as eight 16384-byte pages.
Control/Status Registers — see Section 4.3, “Register Addresses and Bit Assignments”
Extended Address
CPU Address
0x0000
DIRECT PAGE
REGISTERS
128 BYTES
0x00000
PPAGE=0
When the CPU accesses
PPAGE 0 directly, RAM and
registers, when present,
take priority over flash
memory.
0x007F
0x0080
RAM
When PPAGE 0 is
accessed through the
linear address pointer
or through the paging
window, the flash
6016 BYTES
0x17FF
0x1800
FLASH
16384 BYTES
HIGH
PAGE REGISTERS
128 BYTES
0x187F
0x1880
0x207F
0x2080
memory is read.
RAM
2048 BYTES
PPAGE=7
PPAGE=6
PPAGE=5
FLASH
8064 BYTES
0x3FFF
0x03FFF
0x4000
0x04000
PPAGE=4
PPAGE=1
FLASH
PPAGE=3
16384 BYTES
PPAGE=2
PPAGE=1
PPAGE=0
0x7FFF
0x8000
0x07FFF
0x08000
Paging Window
-
Extended
addresses
formed with
FLASH
16384 BYTES
0xBFFF
0xC000
0x0BFFF
0x0C000
PPAGE=3
FLASH
16384 BYTES
0xFFFF
0x0FFFF
Figure 4-1. MC13234/MC13237 Memory Map
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
4-1
Memory
4.2
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. These vectors are located at the top
of Page 3 of the flash because they are accessed at the top of the CPU direct address space.
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
0xFFCA:0xFFCB
0xFFCC:0xFFCD
0xFFCE:0xFFCF
0xFFD0:0xFFD1
0xFFD2:0xFFD3
0xFFD4:0xFFD5
0xFFD6:0xFFD7
0xFFD8:0xFFD9
0xFFDA:0xFFDB
0xFFDC:0xFFDD
0xFFDE:0xFFDF
0xFFE0:0xFFE1
0xFFE2:0xFFE3
0xFFE4:0xFFE5
0xFFE6:0xFFE7
0xFFE8:0xFFE9
0xFFEA:0xFFEB
0xFFEC:0xFFED
0xFFEE:0xFFEF
0xFFF0:0xFFF1
0xFFF2:0xFFF3
0xFFF4:0xFFF5
ADC (MC13237 only)
Vadc
Vrtc
RTC
KBI1 Interrupt
KBI2 Interrupt (MC13234 only)
IIC
Vkeyboard1
Vkeyboard2
Viicx
CMT
Vcmt
SCI Transmit
SCI Receive
SCI Error
Vscitx
Vscirx
Vscierr
SPI
Vspi
TPM4 Overflow
TPM4 Channel 0
TPM3 Overflow
TPM3 Channel 0
TPM2 Overflow
TPM2 Channel 0
TPM1 Overflow
TPM1 Channel 0
AES 128
Vtpm4ovf
Vtpm4ch0
Vtpm3ovf
Vtpm3ch0
Vtpm2ovf
Vtpm2ch0
Vtpm1ovf
Vtpm1ch0
Vaes128
8
7
802.15.4 RX watermark
802.15.4 Timers
Vrx_watermark_802_15_4
Vtimers_802_15_4
Vtx_802_15_4
6
5
802.15.4 Transmit
(SEQIRQ,LO1_UNLOCK_IRQ,TXIRQ)
4
0xFFF6:0xFFF7
802.15.4 Receive
Vrx_802_15_4
(SEQIRQ,CCAIRQ,FILTERFAIL_IRQ,LO1_U
NLOCK_IRQ,RXIRQ)
3
2
1
0
0xFFF8:0xFFF9
0xFFFA:0xFFFB
0xFFFC:0xFFFD
0xFFFE:0xFFFF
Low Voltage Detect or Low Voltage Warning
Vlvd
Virq
IRQ
SWI
Vswi
Vreset
Reset
MC13234/MC13237 Reference Manual, Rev. 1.8
4-2
Freescale Semiconductor
Memory
4.3
Register Addresses and Bit Assignments
The various control and status registers in MC13234/MC13237 are divided into the following groups:
•
Direct-page registers (Address 0x0000-0x007F) - are located in the first 128 locations in the
memory map; these are accessible with efficient direct addressing mode instructions.
— Direct-page registers can be accessed with efficient direct addressing mode instructions
— Bit manipulation instructions can be used to access any bit in any direct-page register
— Table 4-2 shows a summary of all user-accessible direct-page registers and control bits.
•
High-page registers (Address 0x1800-0x187F) - are used much less often, so they are located
above 0x1800 in the memory map. This leaves more room in the direct page for more frequently
used registers and RAM. Table 4-3 shows a summary of all high-page registers and control bits.
The high-page registers have two use models:
— Conventional direct access - these are the majority of registers
— Indirect access - addresses 0x185B and 0x185C are used to access a block of transceiver
register using an indirect access method. See Section 6.13.33, “Transceiver Indirect Access
Registers (INDEX and DATA)” for details.
•
Flash control registers (Address 0xFFB0–0xFFBF) - this nonvolatile register area consists of a
block of 16 locations in flash memory and includes:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte back door comparison key that optionally allows a user to gain controlled access to
secure memory
NOTE
Because the flash nonvolatile register locations are flash memory, they must
be erased and programmed like other flash memory locations.
Table 4-2 shows a summary of all user-accessible direct-page registers and control bits, Table 4-3 shows
a summary of all high-page registers and control bits, and Table 4-4 shows reserved flash memory
addresses. For these tables:
•
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which
requires only the lower byte of the address. Because of this, the lower byte of the address in column
one is shown in bold text.
•
•
In Table 4-3 and Table 4-4, the whole address in column one is shown in bold.
In Table 4-2, Table 4-3, and Table 4-4 -
— The register names in column two are shown in bold to set them apart from the bit names to the
right
— Cells that are not associated with named bits are shaded.
– A shaded cell with a 0 indicates this unused bit always reads as a 0
– Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or
0s. When writing to these bits, write a 0 unless otherwise specified.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
4-3
Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 4)
Register
Name
Address
Bit 7
6
5
4
3
2
1
Bit 0
0x0000 PTAD
PTAD7
PTADD7
PTBD7
PTBDD7
PTCD7
PTCDD7
PTDD7
PTDDD7
TOF
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PTADD0
PTBD0
PTBDD0
PTCD0
PTCDD0
PTDD0
PTDDD0
PS0
0x0001 PTADD
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
0x0002 PTBD
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
0x0003 PTBDD
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
0x0004 PTCD
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
0x0005 PTCDD
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
0x0006 PTDD
PTDD6
PTDD5
PTDD4
PTDD3
PTDD2
PTDD1
0x0007 PTDDD
PTDDD6
PTDDD5
PTDDD4
PTDDD3
PTDDD2
PTDDD1
0x0008 TPM1SC
0x0009 TPM1CNTH
0x000A TPM1CNTL
0x000B TPM1MODH
0x000C TPM1MODL
0x000D TPM1C0SC
0x000E TPM1C0VH
0x000F TPM1C0VL
0x0010 TPM2SC
0x0011 TPM2CNTH
0x0012 TPM2CNTL
0x0013 TPM2MODH
0x0014 TPM2MODL
0x0015 TPM2C0SC
0x0016 TPM2C0VH
0x0017 TPM2C0VL
0x0018 TPM3SC
0x0019 TPM3CNTH
0x001A TPM3CNTL
0x001B TPM3MODH
0x001C TPM3MODL
0x001D TPM3C0SC
0x001E TPM3C0VH
0x001F TPM3C0VL
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
9
Bit 15
Bit 7
14
13
12
11
10
Bit 8
6
14
5
4
3
2
1
Bit 0
Bit 15
Bit 7
13
12
11
10
9
Bit 8
6
5
4
3
2
ELS0A
10
1
Bit 0
CH0F
Bit 15
Bit 7
CH0IE
14
MS0B
MS0A
ELS0B
0
0
13
12
11
9
Bit 8
6
5
4
3
2
1
Bit 0
TOF
TOIE
14
CPWMS
CLKSB
CLKSA
PS2
10
PS1
9
PS0
Bit 15
Bit 7
13
12
11
Bit 8
6
5
4
3
2
1
Bit 0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
6
5
4
MS0A
12
3
2
1
Bit 0
CH0F
Bit 15
Bit 7
CH0IE
14
MS0B
ELS0B
ELS0A
10
0
0
13
11
9
Bit 8
6
5
4
3
2
1
Bit 0
TOF
TOIE
14
CPWMS
CLKSB
12
CLKSA
PS2
10
PS1
9
PS0
Bit 15
Bit 7
13
5
11
Bit 8
6
4
3
2
1
Bit 0
Bit 15
Bit 7
14
13
5
12
11
10
9
Bit 8
6
4
3
ELS0B
11
2
1
Bit 0
CH0F
Bit 15
Bit 7
CH0IE
14
MS0B
13
5
MS0A
12
ELS0A
10
0
0
9
Bit 8
6
4
3
2
1
Bit 0
0x0020 802.15.4 AES
LOAD_
MAC
CLEAR
START
SELFTST
CTR
—
CBC
—
CLEAR
AES_MSK
—
CONTROL1
0x0021 802.15.4 AES
DATA_REG_TYPE_SELECT
IRQ_FLAG TSTPAS
CONTROL2
0x0022 802.15.4 ASM
DATA[127:120]
DATA[119:112]
DATA[111:104]
Data_0
0x0023 802.15.4 ASM
Data_1
0x0024 802.15.4 ASM
Data_2
MC13234/MC13237 Reference Manual, Rev. 1.8
4-4
Freescale Semiconductor
Memory
Bit 0
Table 4-2. Direct-Page Register Summary (Sheet 2 of 4)
Register
Name
Address
Bit 7
6
5
4
3
2
1
0x0025 802.15.4 ASM
DATA[103:96]
DATA[95:88]
DATA[87:80]
DATA[79:72]
DATA[71:64]
DATA[63:56]
DATA[55:48]
DATA[47:40]
DATA[39:32]
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
Data_3
0x0026 802.15.4 ASM
Data_4
0x0027 802.15.4 ASM
Data_5
0x0028 802.15.4 ASM
Data_6
0x0029 802.15.4 ASM
Data_7
0x002A 802.15.4 ASM
Data_8
0x002B 802.15.4 ASM
Data_9
0x002C 802.15.4 ASM
Data_A
0x002D 802.15.4 ASM
Data_B
0x002E 802.15.4 ASM
Data_C
0x002F 802.15.4 ASM
Data_D
0x0030 802.15.4 ASM
Data_E
0x0031 802.15.4 ASM
Data_F
0x0032 KBI1SC
0x0033 KBI1PE
0x0034 KBI1ES
0x00351 KBI2SC
0x0036 KBI2PE
0x0037 KBI2ES
0x0038 SCI1BDH
0x0039 SCI1BDL
0x003A SCI1C1
0x003B SCI1C2
0x003C SCI1S1
0x003D SCI1S2
0x003E SCI1C3
0x003F SCI1D
0
0
0
KBIPE5
KBEDG5
0
0
KBIPE4
KBEDG4
0
KBF
KBACK
KBIPE2
KBIE
KBIMOD
KBIPE0
KBIPE7
KBEDG7
0
KBIPE6
KBEDG6
0
KBIPE3
KBIPE1
KBEDG3 KBEDG2 KBEDG1 KBEDG0
KBF
KBACK
KBIPE2
KBIE
KBIMOD
KBIPE0
KBIPE7
KBEDG7
LBKDIE
SBR7
LOOPS
TIE
KBIPE6
KBEDG6
RXEDGIE
SBR6
SCISWAI
TCIE
KBIPE5
KBEDG5
0
KBIPE4
KBEDG4
SBR12
SBR4
M
KBIPE3
KBIPE1
KBEDG3 KBEDG2 KBEDG1 KBEDG0
SBR11
SBR3
WAKE
TE
SBR10
SBR2
ILT
SBR9
SBR1
PE
SBR8
SBR0
PT
SBR5
RSRC
RIE
ILIE
RE
RWU
FE
SBK
PF
TDRE
LBKDIF
R8
TC
RDRF
0
IDLE
OR
NF
RXEDGIF
T8
RXINV
TXINV
4
RWUID
ORIE
3
BRK13
NEIE
2
LBKDE
FEIE
1
RAF
PEIE
Bit 0
TXDIR
5
Bit 7
6
0x0040 802.15.4 PHY
TXD_ADR_P
NTR0
—
—
—
TXD_ADR_PNTR[12:8]
0x0041 TXD_ADR_P
TXD_ADR_PNTR[7:0]
NTR1
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
4-5
Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 4)
Register
Name
Address
Bit 7
6
5
4
3
2
1
Bit 0
0x0042 RXD_ADR_P
—
—
—
RXD_ADR_PNTR[12:8]
RXD_ADR_PNTR[7:0]
TMRTRIGEN SLOTTED CCABFRTX RXACKRQD AUTOACK
NTR0
0x0043 RXD_ADR_P
NTR1
0x0044 CNTRL1
0x0045 CNTRL2
XCVSEQ
TRCV_MSK
PANCORD
NTR
PROMISC
UOUS
TC3TMOUT
CCATYPE
TMRLOAD
RXMSK
TC2’EN
0x0046 CNTRL3
0x0047 CNTRL4
0x0048 SRC_CNTRL
LO1_UNLO FILTERFAIL RX_WMRK_
CK_MSK
CRC_MSK
CCAMSK
TXMSK
SEQMSK
_MSK
MSK
TMR4CMP TMR3CMP TMR2CMP TMR1CMP
TMR4MSK TMR3MSK TMR2MSK TMR1MSK
INDEX
_EN
_EN
_EN
_EN
ACK_FRM SRCADDR
INDEX_DI
SABLE
INDEX_EN
_PND
_EN
0x0049 SRC_ADDRS
_SUM_DATA
0
SRC_ADDRS_SUM_DATA[15:8]
SRC_ADDRS_SUM_DATA[7:0]
0x004A SRC_ADDRS
_SUM_DATA
1
0x004B RX_WTR_
RX_WTR_MARK[7:0]
MARK
0x004C RX_BYTE_
RX_BYTE_COUNT[7:0]
COUNT
0x004D STATUS1
0x004E STATUS2
CRCVALID
RX_FRM_P LO1_UNLO FILTERFAIL RXWTRMR
END CK_IRQ _IRQ KIRQ
CCA
SRCADDR
PI
TMR4IRQ TMR3IRQ TMR2IRQ TMR1IRQ
CCAIRQ RXIRQ TXIRQ SEQIRQ
0x004F Reserved
0x0050 CCAFNL
CCAFNL[7:0]
0x0051 EVENT_TMR
EVENT_TMR[23:16]
0
0x0052 EVENT_TMR
EVENT_TMR[15:8]
EVENT_TMR[7:0]
1
0x0053 EVENT_TMR
2
0x0054 TIMESTAMP0
0x0055 TIMESTAMP1
0x0056 TIMESTAMP3
0x0057 T3CMP0
TIMESTAMP[23:16]
TIMESTAMP[15:8]
TIMESTAMP[7:0]
T3CMP[23:16]
T3CMP[15:8]
T3CMP[7:0]
0x0058 T3CMP1
0x0059 T3CMP2
0x005A TC2 PRIME0
0x005B TC2 PRIME1
TC2’[15:8]
TC2’[7:0]
0x005C MACSHORT
MACSHORTADDRS[15:8]
ADDRS0
0x005D MACSHORT
MACSHORTADDRS[7:0]
ADDRS1
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Memory
Bit 0
Table 4-2. Direct-Page Register Summary (Sheet 4 of 4)
Register
Name
Address
Bit 7
6
5
4
3
2
1
0x005E MACPANID0
0x005F MACPANID1
0x0060 CMTCGH1
0x0061 CMTCGL1
0x0062 CMTCGH2
0x0063 CMTCGL2
0x0064 CMTOC
0x0065 CMTMSC
0x0066 CMTCMD1
0x0067 CMTCMD2
0x0068 CMTCMD3
0x0069 CMTCMD4
0x006A IIC1A
MACPANID[15:8]
MACPANID[7:0]
PH7
PL7
PH6
PL6
PH5
PL5
PH4
PL4
PH3
PH2
PL2
SH2
SL2
0
PH1
PL1
PH0
PL0
SH0
SL0
0
PL3
SH3
SL3
SH7
SH6
SH5
SH4
SH1
SL1
SL7
SL6
SL5
SL4
IROL
EOCF
MB15
MB7
SB15
SB7
CMTPOL
IROPEN
CMTDIV2
EXSPC
MB12
MB4
0
0
CMTDIV1 CMTDIV0
BASE
MB11
MB3
SB11
SB3
AD3
FSK
MB10
MB2
SB10
SB2
AD2
EOCIE
MB9
MB1
SB9
SB1
AD1
MCGEN
MB8
MB0
SB8
SB0
0
MB14
MB6
SB14
SB6
MB13
MB5
SB13
SB5
SB12
SB4
AD7
AD6
AD5
AD4
0x006B IIC1F
MULT
TAP2 TAP1 ICR
0x006C IIC1C1
0x006D IIC1S
IICEN
TCF
IICIE
IAAS
MST
TX
TXAK
0
RSTA
0
0
BUSY
ARBL
SRW
IICIF
RXAK
0x006E IIC1D
DATA
0x006F IIC1C2
0x0070 SPIC1
0x0071 SPIC2
0x0072 SPIBR
0x0073 SPIS
GCAEN
SPIE
0
ADEXT
0
0
MSTR
MODFEN
SPPR0
MODF
0
0
AD10
CPHA
0
AD9
SSOE
SPISWAI
SPR1
0
AD8
LSBFE
SPC0
SPR0
0
SPE
SPTIE
CPOL
0
0
BIDIROE
0
SPPR2
SPPR1
0
0
SPR2
0
SPRF
0
0
SPTEF
0x0074 Reserved
0x0075 SPID
0
6
0
0
0
0
0
Bit 7
0
5
IRQEDG
0
4
3
2
1
Bit 0
IRQMOD
0
0x0076 IRQSC
0x0077 Reserved
0x0078 PPAGE
0x0079 LAP2
IRQPDD
0
IRQPE
0
IRQF
0
IRQACK
0
IRQIE
0
0
0
0
0
0
0
XA16
0
XA15
0
XA14
LA16
LA8
LA0
D0
0
0
0
0
0
0x007A LAP1
LA15
LA7
D7
D7
D7
D7
LA14
LA6
D6
LA13
LA5
D5
LA12
LA4
D4
LA11
LA3
D3
D3
D3
D3
LA10
LA2
D2
LA9
LA1
D1
0x007B LAP0
0x007C LWP
0x007D LBP
D6
D5
D4
D2
D1
D0
0x007E LB
D6
D5
D4
D2
D1
D0
0x007F LAPAB
D6
D5
D4
D2
D1
D0
1
Address 0x0035 to 0x0037, KBI2 registers are available in MC13234 only.
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
4-7
Memory
2
Table 4-3. High-Page Register Summary (Sheet 1 of 4)
Address Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x1800
0x1801
0x1802
0x1803
0x1804
0x1805
0x1806
0x1807
0x1808
0x1809
0x180A
0x180B
0x180C
SRS
POR
0
PIN
COP
0
ILOP
0
ILAP
0
LVD
0
0
BDFR
0
SBDFR
SOPT1
SOPT2
SCIC4
0
COPT
0
0
0
0
0
COPE
COPCLKS
0
STOPE
0
ADCHT
ADCCG1
0
BKGDPE
0
PID
0
0
BRFA[4:0]
Reserved
SDIDH
—
—
—
—
—
—
ID11
ID3
—
ID10
ID2
LVDE
0
—
ID9
ID1
0
—
ID8
ID0
0
—
—
—
SDIDL
ID7
ID6
ID5
ID4
SPMSC1
SPMSC2
Reserved
SPMSC3
SOMC1
LVDF
LPR
—
LVDACK
LPRS
—
LVDIE
LPWUI
—
LVDRE
0
LVDSE
—
PPDE
—
PPDC
—
—
—
—
LVWF
LVWACK
LVDV
LVWV
LVWIE
0
0
0
XTAL0-
STEN
XTAL1-
STEN
XTAL0_
TST_OUT
RDIV
XTAL0EN
—
0x180D
0x180E
0x180F
0x1810
0x1811
0x1812
0x1813
0x1814
0x1815
0x1816
0x1817
0x1818
0x1819
0x181A
0x181B
0x181C
0x181D
0x181E
0x181F
0x1820
0x1821
0x1822
0x1823
0x1824
0x1825
0x1826
0x1827
0x1828
0x1829
SOMC2
SCGC1
SCGC2
DBGCAH
DBGCAL
DBGCBH
DBGCBL
DBGCCH
DBGCCL
DBGFH
DBGFL
DBGCAX
DBGCBX
DBGCCX
DBGFX
DBGC
XTAL1_TRIM[7:0]
1
—
TPM4
DBG
14
TPM3
TPM2
TPM1
CMT
—
10
2
IIC
RTC
9
SCI
SPI
FLS
IRQ
KBI1
11
3
Bit 15
Bit 7
13
12
Bit 8
6
5
4
1
Bit 0
Bit 15
Bit 7
14
13
12
11
3
10
2
9
Bit 8
6
5
4
1
Bit 0
Bit 15
Bit 7
14
13
12
11
3
10
2
9
Bit 8
6
5
4
1
Bit 0
Bit 15
Bit 7
14
13
12
11
3
10
2
9
Bit 8
6
5
4
1
Bit 0
RWAEN
RWBEN
RWCEN
PPACC
DBGEN
TRGSEL
AF
RWA
RWB
RWC
0
PAGSEL
0
0
0
0
Bit 16
Bit 16
Bit 16
Bit 16
LOOP1
PAGSEL
0
0
0
0
PAGSEL
0
0
0
0
0
0
0
0
0
ARM
BEGIN
BF
TAG
BRKEN
0
0
0
DBGT
0
0
0
TRG
CNT
DBGS
CF
0
0
0
ARMF
—
DBGCNT
Reserved
FOPT
0
0
0
0
—
—
—
—
0
—
0
—
0
—
KEYEN
0
—
SEC
Reserved
FCNFG
FPROT
—
0
—
0
—
0
—
0
—
0
—
0
—
KEYACC
0
FPOPEN
0
FPS
FSTAT
FCBEF
0
FCCF
FPVIOL FACCERR
0
FCMD
—
FBLANK
0
FCMD
Reserved
RTCSC
RTCCNTL
—
—
—
—
—
—
—
RTIF
RTCLKS
RTIE
RTCPS
RTCCNTL[7:0]
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Memory
Bit 0
Table 4-3. High-Page Register Summary (Sheet 2 of 4)
Address Register Name
Bit 7
6
5
4
3
2
1
0x182A
0x182B
0x182C
0x182D
0x182E
0x182F
0x1830
0x1831
0x1832
0x1833
0x1834
0x1835
0x1836
0x1837
0x1838
0x1839
0x183A
0x183B
0x183C
0x183D
0x183E
0x183F
0x1840
0x1841
0x1842
0x1843
0x1844
0x1845
0x1846
0x1847
0x1848
0x1849
0x184A
0x184B
0x184C
0x184D
RTCMODL
RTCCNTH
RTCMODH
Reserved
Reserved
Reserved
PTAPE
RTCMODL[7:0]
RTCCNTH[7:0]
RTCMODH[7:0]
PTAPE7
PTASE7
PTADS7
—
PTAPE6
PTASE6
PTADS6
—
PTAPE5
PTASE5
PTADS5
—
PTAPE4
PTAPE3
PTASE3
PTADS3
—
PTAPE2
PTASE2
PTADS2
—
PTAPE1
PTASE1
PTADS1
—
PTAPE0
PTASE0
PTADS0
—
PTASE
PTASE4
PTADS4
—
PTADS
Reserved
PTBPE
PTBPE7
PTBSE7
PTBPE6
PTBSE6
PTBPE5
PTBSE5
PTBPE4
PTBSE4
PTBPE3
PTBSE3
PTBPE2
PTBSE2
PTBPE1
PTBSE1
PTBPE0
PTBSE0
PTBSE
PTBDS
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
Reserved
PTCPE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTCPE7 PTCPE6 PTCPE5
PTCSE7 PTCSE6 PTCSE5
PTCDS7 PTCDS6 PTCDS5
PTCPE0
PTCSE0
PTCDS0
—
PTCSE
PTCDS
Reserved
PTDPE
—
—
—
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
PTDSE
PTDDS
Reserved
T1CMP0
T1CMP1
T1CMP2
T2CMP0
T2CMP1
T2CMP2
T4CMP0
T4CMP1
T4CMP2
LO1_FRAC0
LO1_FRAC1
LO1_INT
PA PWR CNTL
T1CMP[23:16]
T1CMP[15:8]
T1CMP[7:0]
T2CMP[23:16]
T2CMP[15:8]
T2CMP[7:0]
T4CMP[23:16]
T4CMP[15:8]
T4CMP[7:0]
LO1_FRAC[15:8]
LO1_FRAC[7:0]
LO1_INT[7:0]
Reserved[7:0]
MACLONG
ADDRS0
MACLONGADDRS[63:56]
MACLONGADDRS[55:48]
MACLONGADDRS[47:40]
MACLONGADDRS[39:32]
0x184E
0x184F
0x1850
MACLONG
ADDRS1
MACLONG
ADDRS2
MACLONG
ADDRS3
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Freescale Semiconductor
4-9
Memory
Table 4-3. High-Page Register Summary (Sheet 3 of 4)
Address Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x1851
0x1852
0x1853
0x1854
0x1855
0x1856
0x1857
MACLONG
ADDRS4
MACLONGADDRS[31:24]
MACLONGADDRS[23:16]
MACLONGADDRS[15:8]
MACLONGADDRS[7:0]
MAXFRAMELENGTH[7:0]
MACLONG
ADDRS5
MACLONG
ADDRS6
MACLONG
ADDRS7
MAXFRAME
LENGTH
RX FRAME
FILTER
BEACON_
FT
—
—
—
NS_FT
—
CMD_FT ACK_FT DATA_FT
MAC FRAME
VER
TMR_PRESCALE[2:0]
—
—
FRM_VER
FMR REV&TMR
0x1858
0x1859
CCA_
THRESHOLD
CCA_THRESHOLD[7:0]
CCA_OFFSET_CMP[7:0]
CCA_OFFSET_
CMP
0x185A
0x185B
FSM
--
--
FSM[5:0]
INDIRECT
ACCESS
INDEX
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
0x185C
INDIRECT
ACCESS
DATA
0x185D
0x185E
0x185F
0x1860
0x1861
0x1862
0x1863
0x1864
0x1865
0x1866
0x1867
0x1868
0x1869
0x186A
0x186B
0x186C
0x186D
0x186E
0x186F
Reserved
Reserved
Reserved
TPM4SC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PS1
9
—
—
—
—
—
—
—
—
TOF
Bit 15
Bit 7
Bit 15
Bit 7
CH0F
Bit 15
Bit 7
—
TOIE
14
6
CPWMS
13
CLKSB
12
4
CLKSA
11
PS2
10
2
PS0
Bit 8
Bit 0
Bit 8
Bit 0
0
TPM4CNTH
TPM4CNTL
TPM4MODH
TPM4MODL
TPM4C0SC
TPM4C0VH
TPM4C0VL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
3
1
14
6
13
12
4
11
10
2
9
5
3
1
CH0IE
14
6
MS0B
13
MS0A
12
4
ELS0B
11
ELS0A
10
2
0
9
Bit 8
Bit 0
—
5
3
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC13234/MC13237 Reference Manual, Rev. 1.8
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Memory
Bit 0
Table 4-3. High-Page Register Summary (Sheet 4 of 4)
Address Register Name
Bit 7
6
5
4
3
2
1
0x18702 ADCSC1
COCO
ADACT
0
AIEN
ADTRG
0
ADCO
ACFE
0
ADCH
0
0x1871
0x1872
0x1873
0x1874
0x1875
0x1876
0x1877
0x1878
0x1879
0x187A
0x187B
0x187C
0x187D
0x187E
0x187F
ADCSC2
ADCRH
ACFGT
0
REFSEL
0
ADR4
0
ADR11
ADR3
—
ADR10
ADR2
—
ADR9
ADR1
ADR8
ADR0
ADCRL
ADR7
0
ADR6
0
ADR5
0
ADCCVH
ADCCVL
ADCCFG
APCTL1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADCV9
ADCV1
ADCV8
ADCV0
ADCV7
ADLPC
ADPC7
—
ADCV6
ADCV5
ADCV4
ADLSMP
ADPC4
—
ADCV3
ADCV2
ADIV
MODE
ADICLK
ADPC6
—
ADPC5
—
ADPC3
—
ADPC2
—
ADPC1
—
ADPC0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
ADCCG is available in MC13237 only.
Address 0x1870 to 0x1877, ADC registers are available in MC13237 only.
2
Several reserved flash memory locations, shown in Table 4-4, are used for storing values used by several
registers. These registers include an 8-byte back door key, NVBACKKEY, which can be used to gain
access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the
reserved flash memory are transferred into corresponding FPROT and FOPT registers in the high-page
registers area to control security and block protection options.
Table 4-4. Reserved Flash Memory Addresses
Address Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0xFFAE Reserved
0xFFAF Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0xFFB0 NVBACKKEY
8-Byte Comparison Key
–
0xFFB7
0xFFB8 Reserved
–
0xFFBC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPS
—
FPOPEN
—
0xFFBD NVPROT
0xFFBE Reserved
0xFFBF NVOPT
—
—
—
0
—
0
—
0
—
KEYEN
0
SEC
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
4-11
Memory
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the flash if needed (normally through the background
debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).
4.4
Memory Management Unit
The memory management unit (MMU) allows the program and data space for the CPU to be extended
beyond the 64K byte CPU addressable memory map. The MMU uses a paging scheme where the extended
flash memory is accessed within a 16-kilobyte window located between addresses 0x8000 and 0xBFFF of
the standard 64-kilobyte address range. The window can access the entire extended address range of the
128-kilobyte flash memory block. The extended memory when used for data can also be accessed linearly
using a linear address pointer and data access registers.
4.4.1
Features
Key features of the MMU module are:
•
Memory Management Unit extends the HCS08 memory space
— up to 4M bytes for program and data space
Extended program space using paging scheme
— PPAGE register used for page selection
— fixed 16K byte memory window
•
— architecture supports up to 256, 16K pages
Extended data space using linear address pointer
— up to 22-bit linear address pointer
•
— linear address pointer and data register provided in direct page allows access of complete flash
memory map using direct page instructions
— optional auto increment of pointer when data accessed
— supports an 2s complement addition/subtraction to address pointer without using any math
instructions or memory resources
— supports word accesses to any address specified by the linear address pointer when using
LDHX, STHX instructions
4.4.2
Register Definition
The following figure shows a summary of MMU registers.
Table 4-5. MMU Register Summary
Name
7
6
5
4
3
2
1
0
R
0
0
0
0
0
PPAGE
XA16
XA15
XA14
W
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Table 4-5. MMU Register Summary (continued)
Name
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
LAP2
LA16
LAP1
LAP0
LWP
LBP
LA15
LA7
D7
LA14
LA6
D6
LA13
LA5
D5
LA12
LA4
D4
LA11
LA3
D3
LA10
LA2
D2
LA9
LA1
D1
LA8
LA0
D0
W
R
W
R
W
R
D7
D6
D5
D4
D3
D2
D1
D0
W
R
LB
D7
D6
D5
D4
D3
D2
D1
D0
W
R
0
0
0
0
0
0
0
0
LAPAB
W
D7
D6
D5
D4
D3
D2
D1
D0
4.4.2.1
Program Page Register (PPAGE)
The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The address space
can be extended to 128K bytes using a paging window scheme. The Program Page (PPAGE) allows for
selecting one of the 16K byte blocks to be accessed through the Program Page Window located at
0x8000-0xBFFF. The CALL and RTC instructions can load or store the value of PPAGE onto or from the
stack during program execution. After any reset, PPAGE is set to PAGE 2.
PPAGE
0x0078
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
XA16
XA15
XA14
Reset:
0
0
0
0
0
0
1
0
Figure 4-2. Program Page Register (PPAGE)
Table 4-6. Program Page Register Field Descriptions
Description
Field
2:0
PPAGE — When the CPU addresses the paging window, 0x8000-0xBFFF, the value in the PPAGE register along
XA16:XA14 with the CPU addresses A13:A0 are used to create a 17-bit extended address.
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4.4.2.2
Linear Address Pointer Registers 2:0 (LAP2:LAP0)
The three registers, LAP2:LAP0 contain the 17-bit linear address that allows the user to access any flash
location in the extended address map. This register is used in conjunction with the data registers, linear
byte (LB), linear byte post increment (LBP) and linear word post increment (LWP). The contents of
LAP2:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of
LAP2:LAP0 can be increased by writing an 8-bit value to LAPAB.
LAP2:LAP0
0x0079-0x007B
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
LA16
R
LA15
LA14
LA13
LA12
LA11
LA10
LA9
LA8
W
R
LA7
0
LA6
0
LA5
0
LA4
0
LA3
0
LA2
0
LA1
0
LA0
0
W
Reset:
Figure 4-3. Linear Address Pointer Registers 2:0 (LAP2:LAP0)
Table 4-7. Linear Address Pointer Registers 2:0 Field Descriptions
Description
Field
16:0
Linear Address — The values in LAP2:LAP0 are used to create a 17-bit linear address pointer. The value in
LA16:LA0 these registers are used as the extended address when accessing any of the data registers LB, LBP and LWP.
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4.4.2.3
Linear Word Post Increment Register (LWP)
This register is one of three data registers that the user can use to access any flash memory location in the
extended address map. When LWP is accessed the contents of LAP2:LAP0 make up the extended address
of the flash memory location to be addressed. When accessing data using LWP, the contents of
LAP2:LAP0 will increment after the read or write is complete.
Accessing LWP does the same thing as accessing LBP. The MMU register ordering of LWP followed by
LBP, allow the user to access data by words using the LDHX or STHX instructions of the LWP register.
LWP
0x007C
7
6
5
4
3
2
1
0
R
W
D7
D6
0
D5
D4
D3
D2
D1
D0
Reset:
0
0
0
0
0
0
0
Figure 4-4. Linear Word Post Increment Register (LWP)
Table 4-8. Linear Word Post Increment Register Field Descriptions
Description
Field
7:0
D7:D0
Linear Word Post — Reads of this register will first return the data value pointed to by the linear address pointer,
LAP2:LAP0 and then will increment LAP2:LAP0. Writes to this register will first write the data value to the memory
location specified by the linear address pointer and then will increment LAP2:LAP0. Writes to this register are
most commonly used when writing to the flash block(s) during programming.
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4.4.2.4
Linear Byte Post Increment Register (LBP)
This register is one of three data registers that the user can use to access any flash memory location in the
extended address map. When LBP is accessed the contents of LAP2:LAP0 make up the extended address
of the flash memory location to be addressed. When accessing data using LBP, the contents of LAP2:LAP0
will increment after the read or write is complete.
Accessing LBP does the same thing as accessing LWP. The MMU register ordering of LWP followed by
LBP, allow the user to access data by words using the LDHX or STHX instructions with the address of the
LWP register.
LBP
0x007D
7
6
5
4
3
2
1
0
R
W
D7
D6
0
D5
D4
D3
D2
D1
D0
Reset:
0
0
0
0
0
0
0
Figure 4-5. Linear Byte Post Increment Register (LBP)
Table 4-9. Linear Byte Post Increment Register Field Descriptions
Description
Field
7:0
D7:D0
Linear Byte Post — Reads of this register will first return the data value pointed to by the linear address pointer,
LAP2:LAP0 and then will increment LAP2:LAP0. Writes to this register will first write the data value to the memory
location specified by the linear address pointer and then will increment LAP2:LAP0. Writes to this register are
most commonly used when writing to the flash block(s) during programming.
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4.4.2.5
Linear Byte Register (LB)
This register is one of three data registers that the user can use to access any flash memory location in the
extended address map. When LB is accessed the contents of LAP2:LAP0 make up the extended address
of the flash memory location to be addressed.
LB
0x007E
7
6
5
4
3
2
1
0
R
W
D7
D6
0
D5
D4
D3
D2
D1
D0
Reset:
0
0
0
0
0
0
0
Table 4-10. Linear Data Register Field Descriptions
Description
Field
7:0
D7:D0
Linear Byte — Reads of this register returns the data value pointed to by the linear address pointer, LAP2:LAP0.
Writes to this register will write the data value to the memory location specified by the linear address pointer.
Writes to this register are most commonly used when writing to the flash block(s) during programming.
4.4.2.6
Linear Address Pointer Add Byte Register (LAPAB)
The user can increase or decrease the contents of LAP2:LAP0 by writing a 2s complement value to
LAPAB. The value written will be added to the current contents of LAP2:LAP0.
LAPAB
0x007F
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset:
Figure 4-6. Linear Address Pointer Add Byte Register (LAPAB)
Table 4-11. Linear Address Pointer Add Byte Register Field Descriptions
Description
Field
7:0
D7:D0
Linear Address Pointer Add Byte — The 2s complement value written to LAPAB will be added to contents of
the linear address pointer register, LAP2:LAP0. Writing a value of 0x7f to LAPAB will increase LAP by 127, a
value of 0xff will decrease LAP by 1, and a value of 0x80 will decrease LAP by 128.
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Memory
4.4.3
Functional Description
Memory Expansion
4.4.3.1
The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The Program Page
(PPAGE) allows for integrating up to 4M byte of flash into the system by selecting one of the 16K byte
blocks to be accessed through the Paging Window located at 0x8000-0xBFFF. The MMU module also
provides a linear address pointer that allows extension of data access up to 4M bytes.
4.4.3.1.1
Program Space
The PPAGE register holds the page select value for the Paging Window. The value in PPAGE can be
manipulated by using normal read and write instructions as well as the CALL and RTC instructions. The
user should not change PPAGE directly when running from paged memory, only CALL and RTC should
be used.
When the MMU detects that the CPU is addressing the Paging Window, the value currently in PPAGE will
be used to create an extended address that the MCU’s decode logic will use to select the desired flash
location.
As seen in Figure 4-1, the flash blocks in the CPU addressable memory can be accessed directly or using
the Paging Window and PPAGE register. For example, the flash from location 0x4000-0x7FFF can be
accessed directly or using the paging window, PPAGE = 1, address 0x8000-0xBFFF.
4.4.3.1.2
CALL and RTC (Return from Call) Instructions
CALL and RTC are instructions that perform automated page switching when executed in the user
program. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere
in the normal 64K byte address space or on any page of program memory.
During the execution of a CALL instruction, the CPU:
•
•
•
•
Stacks the return address.
Pushes the current PPAGE value onto the stack.
Writes the new instruction-supplied PPAGE value into the PPAGE register.
Transfers control to the subroutine of the new instruction-supplied address.
This sequence is not interruptible; there is no need to inhibit interrupts during CALL execution. A CALL
can be executed from any address in memory to any other address.
The new PPAGE value is provided by an immediate operand in the instruction along with the address
within the paging window, 0x8000-0xBFFF.
RTC is similar to an RTS instruction.
The RTC instruction terminates subroutines invoked by a CALL instruction.
During the execution of an RTC instruction, the CPU:
•
Pulls the old PPAGE value from the stack and loads it into the PPAGE register
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•
•
Pulls the 16-bit return address from the stack and loads it into the PC
Resumes execution at the return address
This sequence is not interruptible; there is no need to inhibit interrupts during RTC execution. An RTC
can be executed from any address in memory.
4.4.3.1.3
Data Space
The linear address pointer registers, LAP2:LAP0 along with the linear data register allow the CPU to read
or write any address in the extended flash memory space. This linear address pointer may be used to access
data from any memory location while executing code from any location in extended memory, including
accessing data from a different PPAGE than the currently executing program.
To access data using the linear address pointer, the user would first setup the extended address in the 17-bit
address pointer, LAP2:LAP0. Accessing one of the three linear data registers LB, LBP and LWP will
access the extended memory location specified by LAP2:LAP0. The three linear data registers access the
memory locations in the same way, however the LBP and LWP will also increment LAP2:LAP0.
Accessing either the LBP or LWP registers allows a user program to read successive memory locations
without re-writing the linear address pointer. Accessing LBP or LWP does the exact same function.
However, because of the address mapping of the registers with LBP following LWP, a user can do word
accesses in the extended address space using the LDHX or STHX instructions to access location LWP.
The MMU supports the addition of a 2s complement value to the linear address pointer without using any
math instructions or memory resources. Writes to LAPAB with a 2s complement value will cause the
MMU to add that value to the existing value in LAP2:LAP0.
4.4.3.1.4
PPAGE and Linear Address Pointer to Extended Address
See Figure 4-1, on how the program PPAGE memory pages and the Linear Address Pointer are mapped to
extended address space.
4.5
RAM
The HCS08 includes static RAM. The locations in RAM below 0x0100 can be accessed using the more
efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation
instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program
variables in this area of RAM is preferred.
At power-on, the contents of RAM are not initialized. RAM data is unaffected by any reset provided that
the supply voltage does not drop below the minimum value for RAM retention (V
).
RAM
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC13234/MC13237, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in the reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP<-(H:X-1)
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Memory
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.6.5, “Flash Module Security”,
for a detailed description of the security feature.
4.6
Flash
The flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths.
The flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The flash module includes a
memory controller that executes commands to modify flash memory contents.
For flash memory, an erased bit reads 1 and a programmed bit reads 0. It is not possible to read from a flash
block while any command is executing on that specific flash block.
CAUTION
•
•
A flash block address must be in the erased state before being
programmed. Cumulative programming of bits within a flash block
address is not allowed except for status field updates required in
EEPROM emulation applications.
The flash can be written and erased only with the CPU/Bus clocks
programmed for maximum frequency, i.e., 32 MHz and 16 MHz
respectively.
For more details about in-circuit and in-application programming, see the HCS08 Family Reference
Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D.
4.6.1
Features
Features of the flash memory include:
•
•
•
•
•
•
•
•
•
Flash size - 131072 bytes (128 sectors of 1024 bytes each)
Single power supply program and erase
Automated program and erase algorithm
Fast program and erase operation
Burst program command for faster flash array program times
Up to 10,000 program/erase cycles at typical voltage and temperature
Flexible protection scheme to prevent accidental program or erase
Security feature to prevent unauthorized access to the flash and RAM
Auto power-down for low-frequency read accesses
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4.6.2
Register Descriptions
The flash module contains a set of 16 control and status registers. Detailed descriptions of each register bit
are provided in the following sections.
4.6.2.1
Flash Options Register (FOPT and NVOPT)
The FSEC register holds all bits associated with the security of the MCU and flash module.
FOPT
0x1821
7
6
5
4
3
2
1
0
R
W
KEYEN
0
0
0
0
SEC
Reset
F
F
0
0
0
0
F
F
= Unimplemented or Reserved
Figure 4-7. Flash Options Register (FOPT)
All bits in the FSEC register are readable but are not writable. To change the value in this register, erase
and reprogram the NVSEC location in flash memory as usual and then issue an MCU reset.
The FSEC register is loaded from the flash location, NVSEC, during the reset sequence, indicated by F in
Table 4-13.
Table 4-12. FSEC Field Descriptions
Field
Description
7:6
Back Door Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of back door key access to
KEYEN[1:0] the flash module as shown in Table 4-13.
1:0
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 4-13, Table 4-14
SEC[1:0]
and Table 4-15. If the flash module is unsecured using back door key access, the SEC[1:0] bits are forced to the
unsecured state.
Table 4-13. Flash KEYEN States
KEYEN[1:0]
Status of Back door Key Access
00
011
10
DISABLED
DISABLED
ENABLED
DISABLED
11
1
Preferred KEYEN state to disable Back door Key Access.
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Table 4-14. Flash Security States for S08FTSR
SEC[1:0]
Status of Security
00
011
10
SECURED
SECURED
UNSECURED
SECURED
11
1
Preferred SEC state to set MCU to secured state.
Table 4-15. Flash Security States
SEC[1:0]
Status of Security
00
011
10
SECURED
SECURED
UNSECURED
SECURED
11
1
Preferred SEC state to set MCU to secured state.
The security feature in the flash module is described in Section 4.6.5, “Flash Module Security””.
4.6.2.2
Flash Configuration Register (FCNFG)
The FCNFG register enables the flash interrupts and gates the security back door writes.
FCNFG
0x1823
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
KEYACC
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-8. Flash Configuration Register (FCNFG)
NVM User Mode: KEYACC bit is readable and writable while all remaining bits read 0 and are not
writable. KEYACC is writable only if KEYEN is set to the enabled state (see Section 4.6.2.1, “Flash
Options Register (FOPT and NVOPT)”.
Table 4-16. FCNFG Field Descriptions
Field
Description
5
Enable Security Key Writing
KEYACC
0 Writes to the flash block are interpreted as the start of a command write sequence.
1 Writes to the flash block are interpreted as keys to open the back door.
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NOTE
Flash array reads are allowed while KEYACC is set. However, the MCU
core will be held off for one bus clock cycle during key fetch from the flash
array.
4.6.2.3
Flash Protection Register (FPROT and NVPROT)
The FPROT register defines which flash sectors are protected against program or erase operations.
FPROT
0x1824
7
6
5
4
3
2
1
0
R
W
FPS
FPOPEN
Reset
F
F
F
F
F
F
F
F
Figure 4-9. Flash Protection Register (FPROT)
The FPROT bits are readable and writable as long as the size of the protected flash memory is being
increased. Any write to FPROT that attempts to decrease the size of the protected flash memory will be
ignored and the PVIOL flag in the FSTAT register will not be set (see Section 4.6.2.4).
During the reset sequence, the FPROT register is loaded from the flash protection byte, NVPROT. To
change the flash protection that will be loaded during the reset sequence, the flash sector containing
NVPROT must be unprotected and erased (FPS=0x7F and FPOP=0 for S08FTSR, FPHS=0x1F and
FPLS!=0x0 for S12SFTSR, FPS=0x7F and FPOP=0 for CFV1FTSR), then NVPROT can be
reprogrammed.
Trying to alter data in any protected area in the flash memory will result in a protection violation error and
the FPVIOL flag will be set in the FSTAT register. The mass erase of the flash array is not possible in NVM
user mode if any of the flash sectors contained in the flash array are protected.
Table 4-17. FPROT Field Descriptions for MC13234/MC13237
Field
Description
7:1
Flash Protection Size — With FPOPEN set, the FPS bits determine the size of the protected flash address
FPS[6:0]
range as shown in Table 4-18
0
Flash Protection Open
FPOPEN 0 Flash array fully protected.
1 Flash array protected address range determined by FPS bits.
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Memory
Table 4-18. Flash Protection Address Range for MC13234/MC13237
Protected Address Range
Protected
Relative to Flash Array Base
FPS[6:0]
FPOPEN
Size
Flash Array 0
Flash Array 1
-
0
1
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
...
0x1_0000–0x1_FFFF
0x1_0400–0x1_FFFF
0x1_0800–0x1_FFFF
0x1_0C00–0x1_FFFF
0x1_1000–0x1_FFFF
0x1_1400–0x1_FFFF
0x1_1800–0x1_FFFF
0x1_1C00–0x1_FFFF
...
128 Kbytes
127 Kbytes
126 Kbytes
125 Kbytes
124 Kbytes
123 Kbytes
122 Kbytes
121 Kbytes
...
0x00
0x01
0x02
0x03
0x04
0x05
0x06
...
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
...
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0000–0x0_FFFF
0x0_0400–0x0_FFFF
0x0_0800–0x0_FFFF
0x0_0C00–0x0_FFFF
0x0_1000–0x0_FFFF
0x0_1400–0x0_FFFF
0x0_1800–0x0_FFFF
0x0_1C00–0x0_FFFF
...
0x1_E000–0x1_FFFF
0x1_E400–0x1_FFFF
0x1_E800–0x1_FFFF
0x1_EC00–0x1_FFFF
0x1_F000–0x1_FFFF
0x1_F400–0x1_FFFF
0x1_F800–0x1_FFFF
0x1_FC00–0x1_FFFF
72 Kbytes
71 Kbytes
70 Kbytes
69 Kbytes
68 Kbytes
67 Kbytes
66 Kbytes
65 Kbytes
64 Kbytes
63 Kbytes
62 Kbytes
61 Kbytes
60 Kbytes
59 Kbytes
58 Kbytes
57 Kbytes
...
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x0_E000–0x0_FFFF
0x0_E400–0x0_FFFF
0x0_E800–0x0_FFFF
0x0_EC00–0x0_FFFF
0x0_F000–0x0_FFFF
0x0_F400–0x0_FFFF
0x0_F800–0x0_FFFF
0x0_FC00–0x0_FFFF
No Protection
8 Kbytes
7 Kbytes
6 Kbytes
5 Kbytes
4 Kbytes
3 Kbytes
2 Kbytes
1 Kbyte
0 Kbytes
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4.6.2.4
Flash Status Register (FSTAT)
The FSTAT register defines the operational status of the flash module. NVM User Mode: In normal mode,
FCCF, FPVIOL, and FACCERR are readable and writable, FCCF and FBLANK are readable and not
writable, remaining bits read 0 and are not writable.
FSTAT (User Mode)
0x1825
7
6
5
4
3
2
1
0
R
W
FCCF
0
FBLANK
0
0
FCBEF
FPVIOL
0
FACCERR
Reset
1
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-10. Flash Status Register (FSTAT)
Table 4-19. FSTAT Field Descriptions
Description
Field
7
Flash Command Buffer Empty Flag — The FCBEF flag indicates that the command buffer is empty so that a
new command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF
flag has no effect on FCBEF. Writing a 0 to FCBEF after writing an aligned address to the flash array memory,
but before FCBEF is cleared, will abort a command write sequence and cause the FACCERR flag to be set.
Writing a 0 to FCBEF outside of a command write sequence will not set the FACCERR flag. The FCBEF flag is
cleared by writing a 1 to FCBEF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to
generate an interrupt request (see Figure 4-2).
FCBEF
0 Command buffers are full.
1 Command buffers are ready to accept a new command.
6
Flash Command Complete Interrupt Flag — The FCCF flag indicates that there are no more commands
pending. The FCCF flag is cleared when FCBEF is cleared and sets automatically upon completion of all active
and pending commands. The FCCF flag does not set when an active program command completes and a
pending burst program command is fetched from the command buffer. Writing to the FCCF flag has no effect on
FCCF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request
(see Figure 4-2).
FCCF
0 Command in progress.
1 All commands are completed.
5
Flash Protection Violation Flag —The FPVIOL flag indicates an attempt was made to program or erase an
address in a protected area of the flash memory or flash IFR during a command write sequence. Writing a 0 to
the FPVIOL flag has no effect on FPVIOL. The FPVIOL flag is cleared by writing a 1 to FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected.
FPVIOL
1 Protection violation has occurred.
4
Flash Access Error Flag — The FACCERR flag indicates an illegal access has occurred to the flash memory
FACCERR or flash IFR caused by either a violation of the command write sequence (see Section 4.6.3.1.2, “Command
Write Sequence”), issuing an illegal flash command (see Table 4-21), or the execution of a CPU STOP instruction
while a command is executing (FCCF = 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. The
FACCERR flag is cleared by writing a 1 to FACCERR.While FACCERR is set, it is not possible to launch a
command or start a command write sequence.
0 No access error detected.
1 Access error has occurred.
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Table 4-19. FSTAT Field Descriptions
Description
Field
2
Flash Flag Indicating the Erase Verify Operation Status — When the FCCF flag is set after completion of an
erase verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is
cleared by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to
the FBLANK flag has no effect on FBLANK.
FBLANK
0 flash block verified as not erased.
1 flash block verified as erased.
1
FAIL
Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (flash block
verified as not erased) or other read operation fails, if an attempt to send an invalid command is made, or if the
flash pulse register is improperly loaded. Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is
cleared by writing a 1 to FAIL.
0 Flash operation completed without error or the flash module is not in NVM Special/Test mode.
1 Flash operation failed.
4.6.2.5
Flash Command Register (FCMD)
The FCMD register is the flash command register.
FCMD
0x1826
7
6
5
4
3
2
1
0
R
W
0
FCMD
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-11. Flash Command Register (FCMD)
All FCMD bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
Table 4-20. FCMD Field Descriptions
Field
Description
6:0
Flash Command — Valid flash commands in NVM user/normal mode are shown in Table 4-21. Writing any
FCMD[6:0] command other than those listed in Table 4-21 in NVM user/normal mode sets the FACCERR flag in the FSTAT
register. flash commands available in NVM test mode are listed in Table 4-11.
Table 4-21. Valid Flash Command List (NVM User Mode)
FCMD[6:0]
NVM Command
0x05
0x20
0x25
0x40
0x41
Erase Verify
Program
Burst Program
Sector Erase
Mass Erase
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4.6.3
Functional Description
The following describes operation of the flash block.
4.6.3.1 Flash Command Operations
Flash command operations are used to execute program, erase, and erase verify algorithms described in
this section. The program and erase algorithms are controlled by the flash memory controller whose time
base, FCLK, is derived from the bus clock via a programmable divider.
The next sections describe:
1. Command write sequences to program, erase, and erase verify operations on the flash memory
2. Valid flash commands
3. Effects resulting from illegal flash command write sequences or aborting flash operations
4.6.3.1.1
Flash Program and Erase Timing
The flash can be programmed on a byte or burst basis, and can be erased on a sector or mass (total flash)
basis as controlled by the command mode. All program or erase operations must be done at the default or
max CPU clock (32 MHz) / bus clock (16 MHz) rate.
Table 4-22. Flash Program and Erase Times
Cycles
Parameter
of
Time
32 MHz Clock
Byte program
1280
640
40 s
20 s / byte1
20 ms
Byte program (burst)
Sector erase
640320
643360
Mass erase
20.1 ms
1
Excluding start/end overhead
4.6.3.1.2
Command Write Sequence
The flash command controller is used to supervise the command write sequence to execute program, erase,
and erase verify algorithms.
Before starting a command write sequence, the FACCERR and FPVIOL flags in the FSTAT register must
be clear and the FCBEF flag must be set (see Section 4.6.2.4, “Flash Status Register (FSTAT)”).
A command write sequence consists of three steps which must be strictly adhered to with writes to the flash
module not permitted between the steps. However, flash register and array reads are allowed during a
command write sequence. The basic command write sequence is as follows:
1. Write to a valid address in the flash array memory.
2. Write a valid command to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the command.
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After a command is launched, the completion of the command operation is indicated by the setting of the
FCCF flag in the FSTAT register with an interrupt generated, if enabled. The FCCF flag will set upon
completion of all active and buffered burst program commands.
A command write sequence can be aborted prior to clearing the CBEIF flag by writing a 0 to the CBEIF
flag and will result in the ACCERR flag in the FSTAT register being set. The ACCERR flag in the FSTAT
register must be cleared prior to starting a new command write sequence.
4.6.3.2
Flash Commands
Table 4-23 summarizes the valid flash commands along with the effects of the commands on the flash
block.
Table 4-23. Flash Command Description
NVM
Command
FCMDB
Function on Flash Memory
0x05
Erase
Verify
Verify all memory bytes in the flash array memory are erased.
If the flash array memory is erased, the FBLANK flag in the FSTAT register will set upon
command completion.
0x20
0x25
Program
Program an address in the flash array.
Burst
Program
Program an address in the flash array with the internal address incrementing after the
program operation.
0x40
0x41
Sector
Erase
Erase all memory bytes in a sector of the flash array.
Mass
Erase
Erase all memory bytes in the flash array.
A mass erase of the full flash array is only possible when no protection is enabled prior
to launching the command.
CAUTION
A flash block address must be in the erased state before being programmed.
Cumulative programming of bits within a flash block address is not allowed
except for status field updates required in EEPROM emulation applications.
4.6.3.2.1
Erase Verify Command
The erase verify operation will verify that a flash block is erased.
An example flow to execute the erase verify operation is shown in Figure 4-12. The erase verify command
write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the erase verify
command. The address and data written will be ignored.
2. Write the erase verify command, 0x05, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the erase verify
command.
After launching the erase verify command, the FCCF flag in the FSTAT register will set after the operation
has completed. The number of bus cycles required to execute the erase verify operation is equal to the
number of addresses in the flash array memory plus several bus cycles as measured from the time the
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FCBEF flag is cleared until the FCCF flag is set. Upon completion of the erase verify operation, the
FBLANK flag in the FSTAT register will be set if all addresses in the flash array memory are verified to
be erased. If any address in the flash array memory is not erased, the erase verify operation will terminate
and the FBLANK flag in the FSTAT register will remain clear.
START
Read: FSTAT register
FCBEF
Set?
no
Command
Buffer Empty Check
yes
yes
Access Error and
Protection Violation
Check
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
FACCERR/FPVIOL
Set?
no
Write: Flash Block Address
and Dummy Data
1.
2.
Write: FCMD register
Erase Verify Command 0x05
Write: FSTAT register
Clear FCBEF 0x80
3.
Read: FSTAT register
Bit Polling for
Command Completion
Check
no
no
FCCF
Set?
yes
Erase Verify
Status
FBLANK
Set?
yes
Flash Block
Erased
Flash Block
EXIT
EXIT
Not Erased
Figure 4-12. Example Erase Verify Command Flow
4.6.3.2.2
Program Command
The program operation will program a previously erased address in the flash memory using an embedded
algorithm.
An example flow to execute the program operation is shown in Figure 4-13. The program command write
sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the program
command. The data written will be programmed to the address written.
2. Write the program command, 0x20, to the FCMD register.
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3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program
command.
If an address to be programmed is in a protected area of the flash block, the FPVIOL flag in the FSTAT
register will set and the program command will not launch. After the program command has successfully
launched, the FCCF flag in the FSTAT register will set after the program operation has completed.
Figure 4-13 shows the timing diagram for programming a single flash address using the program
command.
START
Read: FSTAT register
FCBEF
Set?
no
Command
Buffer Empty Check
yes
yes
Access Error and
Protection Violation
Check
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
FACCERR/FPVIOL
Set?
no
Write: Flash Array Address
and Program Data
1.
2.
Write: FCMD register
Program Command 0x20
Write: FSTAT register
Clear FCBEF 0x80
3.
Read: FSTAT register
Bit Polling for
Command Completion
Check
no
FCCF
Set?
yes
EXIT
Figure 4-13. Example Program Command Flow
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4.6.3.2.3
Burst Program Command
The burst program operation will program previously erased data in the flash memory using an embedded
algorithm.
While burst programming, two internal data registers operate as a buffer and a register (2-stage FIFO) so
that a second burst programming command along with the necessary data can be stored to the buffers while
the first burst programming command is still in progress. This pipe lined operation allows a time
optimization when programming more than one consecutive address on a specific row in the flash array as
the high voltage generation can be kept active in between two programming commands.
An example flow to execute the burst program operation is shown in Figure 4-14. The burst program
command write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the burst program
command. The data written will be programmed to the address written.
2. Write the program burst command, 0x25, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program burst
command.
4. After the FCBEF flag in the FSTAT register returns to a 1 (interrupt generated, if enabled), repeat
steps 1 through 3. The address written is ignored but increments internally.
The burst program procedure can be used to program the entire flash memory even while crossing row
boundaries within the flash array. If data to be burst programmed falls within a protected area of the flash
array, the FPVIOL flag in the FSTAT register will set and the burst program command will not launch.
After the burst program command has successfully launched, the FCCF flag in the FSTAT register will set
after the burst program operation has completed unless a new burst program command write sequence has
been buffered. By executing a new burst program command write sequence on sequential addresses after
the FCBEF flag in the FSTAT register has been set, greater than 50% faster programming time for the
entire flash array can be effectively achieved when compared to using the basic program command.
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START
Read: FSTAT register
FCBEF
Set?
no
Command
Buffer Empty Check
yes
yes
Access Error and
Protection Violation
Check
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
FACCERR/FPVIOL
Set?
no
Write: Flash Array Address
and Program Data
1.
2.
Write: FCMD register
Burst Program Command 0x25
Write: FSTAT register
Clear FCBEF 0x80
3.
Read: FSTAT register
Bit Polling for
Command Buffer Empty
Check
no
FCBEF
Set?
yes
Sequential
Programming
Decision
yes
Next
Address?
no
Read: FSTAT register
Bit Polling for
Command Completion
Check
no
FCCF
Set?
yes
EXIT
Figure 4-14. Example Burst Program Command Flow
4.6.3.2.4
Sector Erase Command
The sector erase operation will erase all addresses in a 1 Kbyte sector of flash memory using an embedded
algorithm.
An example flow to execute the sector erase operation is shown in Figure 4-15. The sector erase command
write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the sector erase
command. The flash address written determines the sector to be erased while global address bits
[8:0] and the data written are ignored.
2. Write the sector erase command, 0x40, to the FCMD register.
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3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase
command.
If a flash sector to be erased is in a protected area of the flash block, the FPVIOL flag in the FSTAT register
will set and the sector erase command will not launch. After the sector erase command has successfully
launched, the FCCF flag in the FSTAT register will set after the sector erase operation has completed.
START
Read: FSTAT register
FCBEF
Set?
no
Command
Buffer Empty Check
yes
yes
Access Error and
Protection Violation
Check
Write: FSTAT register
FACCERR/FPVIOL
Clear FACCERR/FPVIOL 0x30
Set?
no
Write: Flash Sector Address
and Dummy Data
1.
Write: FCMD register
2.
3.
Sector Erase Command 0x40
Write: FSTAT register
Clear FCBEF 0x80
Read: FSTAT register
Bit Polling for
no
FCCF
Set?
Command Completion
Check
yes
EXIT
Figure 4-15. Example Sector Erase Command Flow
4.6.3.3
Illegal Flash Operations
Flash Access Violations
4.6.3.3.1
The FACCERR flag will be set during the command write sequence if any of the following illegal steps
are performed, causing the command write sequence to immediately abort:
1. Writing a byte or misaligned word to a valid flash address for S12SFTSR.
2. Writing a byte, word, or misaligned double word to a valid flash address for CFV1FTSR.
3. Writing to any flash register other than FCMD after writing to a flash address.
4. Writing to a second flash address in the same command write sequence.
5. Writing an invalid command to the FCMD register unless the address written was in a protected
area of the flash array.
6. Writing a command other than burst program while FCBEF is set and FCCF is clear.
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7. When security is enabled, writing a command other than mass erase to the FCMD register when
the write originates from a non-secure memory location or from the background debug mode.
8. Writing to a flash address after writing to the FCMD register.
9. Writing to any flash register other than FSTAT (to clear FCBEF) after writing to the FCMD
register.
10. Writing a 0 to the FCBEF flag in the FSTAT register to abort a command write sequence.
The FACCERR flag will also be set if the MCU enters stop mode while a program or erase operation is
active. The operation is aborted immediately and, if burst programming, any pending burst program
command is purged (see Section 4.6.4.2, “Stop Mode”).
The FACCERR flag will not be set if any flash register is read during a valid command write sequence.
If the flash memory is read during execution of an algorithm (FCCF = 0), the read operation will return
invalid data in NVM user mode and the FACCERR flag will not be set.
If the FACCERR flag is set in the FSTAT register, the user must clear the FACCERR flag before starting
another command write sequence (see Section 4.6.2.4, “Flash Status Register (FSTAT)”).
4.6.3.3.2
Flash Protection Violations
The FPVIOL flag will be set after the command is written to the FCMD register during a command write
sequence if any of the following illegal operations are attempted, causing the command write sequence to
immediately abort:
1. Writing the program command if the address written in the command write sequence was in a
protected area of the flash array.
2. Writing the sector erase command if the address written in the command write sequence was in a
protected area of the flash array.
3. Writing the mass erase command while any flash protection is enabled.
4. Writing an invalid command if the address written in the command write sequence was in a
protected area of the flash array. In NVM user and test modes, unimplemented commands started
through array writes, with the given address pointing to a protected area, will always return a
protection violation instead of a FAIL flag. For valid commands, protection is checked prior to
command execution.
If the FPVIOL flag is set in the FSTAT register, the user must clear the FPVIOL flag before starting another
command write sequence (see Section 4.6.2.4, “Flash Status Register (FSTAT)”).
4.6.4
Operating Modes
Wait Mode
4.6.4.1
If a command is active (FCCF = 0) when the MCU enters wait mode, the active command and any buffered
command will be completed.
The flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled.
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4.6.4.2
Stop Mode
If a command is active (FCCF = 0) when the MCU enters stop mode, the operation will be aborted and, if
the operation is program or erase, the flash array data being programmed or erased may be corrupted and
the FCCF and FACCERR flags will be set. If active, the high voltage circuitry to the flash array will
immediately be switched off when entering stop mode. Upon exit from stop mode, the FCBEF flag is set
and any buffered command will not be launched. The FACCERR flag must be cleared before starting a
command write sequence (see Section 4.6.3.1.2, “Command Write Sequence”).
NOTE
As active commands are immediately aborted when the MCU enters stop
mode, it is strongly recommended that the user does not use the STOP
instruction during program or erase operations.
4.6.4.3
Background Debug Mode
In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all flash
commands listed in Table 4-23 can be executed. If the MCU is secured and is in special mode, only the
erase verify and mass erase commands can be executed.
4.6.5
Flash Module Security
The HCS08 includes circuitry to prevent unauthorized access to the contents of flash and RAM memory.
When security is engaged, flash and RAM are considered secure resources. Direct-page registers,
high-page registers, and the background debug controller are considered unsecured resources. Programs
executing within secure memory have normal access to any MCU memory locations and resources.
Attempts to access a secure memory location with a program executing from an unsecured memory space
or through the background debug interface are blocked (writes are ignored and reads return all 0s).
The flash module provides the necessary security information to the MCU. During each reset sequence,
the flash module determines the security state of the MCU as defined in Section 4.6.2.1, “Flash Options
Register (FOPT and NVOPT)””.
The contents of the flash security byte in NVSEC must be changed directly by programming the NVSEC
location when the MCU is unsecured and the sector containing NVSEC is unprotected. If NVSEC is left
in a secured state, any reset will cause the MCU to initialize into a secure operating mode.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands of unsecured resources.
4.6.5.1
Unsecuring the MCU using Back Door Key Access
The MCU may be unsecured by using the back door key access feature which requires knowledge of the
contents of the back door keys (NVBACKKEY through NVBACKKEY+7, see Table 4-4 for specific
addresses). If the KEYEN[1:0] bits are in the enabled state (see Section 4.6.2.1, “Flash Options Register
(FOPT and NVOPT)”) and the KEYACC bit is set, a write to a back door key address in the flash memory
triggers a comparison between the written data and the back door key data stored in the flash memory. If
all back door keys are written to the correct addresses in the correct order and the data matches the back
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door keys stored in the flash memory, the MCU will be unsecured. The data must be written to the back
door keys sequentially. Values 0x0000 and 0xFFFF are not permitted as back door keys. While the
KEYACC bit is set, reads of the flash memory will return invalid data.
The user code stored in the flash memory must have a method of receiving the back door keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 4.6.2.1, “Flash Options Register (FOPT and
NVOPT)”), the MCU can be unsecured by the back door key access sequence described below:
1. Set the KEYACC bit in the flash configuration register (FCNFG).
2. Sequentially write the correct eight 8-bit bytes to the flash addresses containing the back door keys
for S08FTSR.
3. Sequentially write the correct four 16-bit words to the flash addresses containing the back door
keys for S12SFTSR.
4. Sequentially write the correct two 32-bit double words to the flash addresses containing the back
door keys for CFV1FTSR.
5. Clear the KEYACC bit. Depending on the user code used to write the back door keys, a wait cycle
(NOP) may be required before clearing the KEYACC bit.
6. If all data written match the back door keys, the MCU is unsecured and the SEC[1:0] bits in the
FSEC register are forced to the unsecure state of 1:0.
The back door key access sequence is monitored by an internal security state machine. An illegal operation
during the back door key access sequence will cause the security state machine to lock, leaving the MCU
in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and
allow a new back door key access sequence to be attempted. The following operations during the back door
key access sequence will lock the security state machine:
1. If any of the keys written does not match the back door keys programmed in the flash array.
2. If the keys are written in the wrong sequence.
3. If more keys than are required are written.
4. If any of the keys written are all 0’s or all 1’s.
5. If the KEYACC bit does not remain set while the keys are written.
6. If any of the keys are written on successive MCU clock cycles.
7. Executing a STOP instruction while the KEYACC bit is set.
After the back door keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the flash security byte can be programmed to the unsecure state, if desired.
In the unsecure state, the user has full control of the contents of the back door keys by programming the
associated addresses in NVBACKKEY through NVBACKKEY+7.
The security as defined in the flash security byte is not changed by using the back door key access sequence
to unsecure. The stored back door keys are unaffected by the back door key access sequence. After the next
reset of the MCU, the security state of the flash module is determined by the flash security byte. The back
door key access sequence has no effect on the program and erase protections defined in the flash protection
register (FPROT).
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It is not possible to unsecure the MCU in special mode by using the back door key access sequence in
background debug mode (BDM) as the BDM will not allow flash array writes to the flash module.
4.6.6
Resets
If a reset occurs while any flash command is in progress, that command will be immediately aborted. The
state of the flash array address being programmed or the sector/block being erased is not guaranteed.
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Chapter 5
System Management and Control
5.1
Introduction
This chapter brings together and describes the various elements that manage and control operation of the
MC13234/MC13237. Topics include reset, clock resources and control, control timer resources, interrupts,
modes of operation, power management, and control register descriptions.
5.2
Management Features
•
System reset and available software initiated system reset
Power management of internal regulated voltage sources
Real-Time Clock (RTC)
•
•
•
•
•
Computer Operating Properly (COP) timer
Interrupt control and management
Mode management
— Active background mode for code development
— Run mode — CPU running at full speed and the internal supply is fully regulated, radio
optionally active. CPU clock can be run at divided values of: 1, 2, 4, 8, 16, and 64.
— LPRun mode — CPU clock is set to 500 kHz and peripheral clock set (bus clock) to 250 kHz
and the internal voltage regulator is in standby.
— Wait mode — CPU shuts down to conserve power; system clocks are running and full
regulation is maintained, radio optionally active.
— LPWait mode — CPU shuts down to conserve power; peripheral clocks are restricted to
250 kHz and the internal voltage regulator is in standby.
— Stop3 mode — System clocks are stopped and voltage regulator is in standby. All internal
circuits are powered for fast recovery, (full regulation set before entering stop).
•
Wake-up mode management
— Chip is gracefully powered up.
— Clocks are automatically turned on.
— Wake-up available by programmable RTC timer.
— Wake-up available by external interrupts from KBI pads, IRQ, or UART RX.
Management of 1 kHz ring oscillator and optional 32.768 kHz oscillator
Management of 32 MHz reference oscillator
•
•
•
Management of MCU core and peripheral clocks
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System Management and Control
5.3
System Reset
The MC13234/MC13237 provides complete management of system reset and recovery/initialization from
reset. Resetting the MCU provides a way to start processing from a known set of initial conditions.
During reset:
•
•
Most control and status registers are forced to initial values
The program counter is loaded from the reset vector (0xFFFE:0xFFFF) so that at release of reset
the CPU starts executing instructions from this address
•
•
On-chip peripheral modules are disabled
I/O pins are initially configured as general-purpose high-impedance inputs with pullup devices
disabled.
•
The I bit in the condition code register (CCR) is set to block maskable interrupts so the user
program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced
to 0x00FF at reset.
The sources of reset for the MC13234/MC13237 can be loosely divided into the power-on reset circuit
(POR) and all others:
•
Power-on reset
— The POR is only activated or cycled by the main VDD supply. If a reset is initiated by any other
source than a power cycle or the low-voltage detect, the POR is not involved.
— Factory test mode is enabled via POR and is not desired for normal operation. Signal PTA2
must be held low during release of POR to allow the device to enter normal operation.
— The low-voltage detect reset is enabled out of POR and the power supply voltage must rise and
exceed the LVD rising-edge threshold or the device will be held in reset. After the rising edge
threshold is exceeded, the reset is released.
•
Other reset sources
— External asynchronous RESET pin - holding RESET asserted for an extended period affects
the reference oscillator, see Section 5.4.1, “Clock Sources”.
— Computer operating properly (COP) timer
— Illegal opcode detect (ILOP)
— Illegal Address detect (ILAP)
— Low-voltage detect (LVD)
— Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the System Reset Status Register (SRS).
Reset or a partial reset is also affected by exit from low power modes.
5.4
System Clocks
This section provides a brief overview of the system clocks.
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5.4.1
Clock Sources
The HCS08 has 3 possible clock sources, i.e., the 32 MHz reference oscillator, an on board self-contained
1 kHz ring oscillator, and an optional 32.768 kHz crystal oscillator.
•
Reference oscillator - is the primary clock source for the device
— 32 MHz is the required frequency.
— A crystal is used with the onboard amplifier.
— Frequency accuracy of +/-40 ppm or better for IEEE 802.15.4 compatibility must be
maintained over all conditions.
— See Chapter 3, “System Considerations” for more information about this oscillator.
— Trim the crystal oscillator frequency accuracy by changing the on board load capacitance.
— The reference oscillator can be disabled when the hardware RESET pin is enabled (active low)
if RESET is held active for more than 69 bus clock cycles then the oscillator will be disabled.
•
•
1 kHz ring oscillator - is the default oscillator source for the Real Time Clock (RTC) which can be
used as a wake-up source and for the COP timer. The 1 kHz oscillator is disabled only if not
selected for use by the RTC or the COP.
Optional 32.768 kHz crystal oscillator - is available with the addition of an external 32.768 kHz
crystal (see Chapter 3, “System Considerations”). This oscillator typically replaces the use of the
ring oscillator if a low power, high accuracy source is desired for wake-up and the RTC.
5.4.2
Main System Clock Distribution
Figure 5-1 shows a simplified diagram of the HCS08 clock distribution.
Figure 5-1. MC13234/MC13237 Simplified Clock Distribution
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5.4.3
Clock Distribution Network Features
•
•
•
The primary reference oscillator is 32 MHz
The 32 MHz reference drives the transceiver 802.15.4 PHY block directly.
The CPU and bus clocks are all derived from the reference oscillator and a programmable divider
(prescaler)
— The CPU clock is determined by the prescaler divide ratio as set by the RDIV[2:0] field of the
System Oscillator Management and Control Register 1 (SOMC1 )- divide ratios are
programmable from 1 to 64 (default = 1). Lower core clock rates reduce power, but also reduce
performance.
— The bus clock is always the CPU clock divided-by-2. All MCU peripherals are driven by the
bus clock.
•
•
The Real Time Clock (RTC) source clock is selected from the reference oscillator, the onboard 1
kHz RC oscillator or the optional 32.768 kHz crystal oscillator
The COP is optionally driven from the onboard 1 kHz RC oscillator or the bus clock.
5.4.4
Managing Clock Resources
The HCS08 provides the following for managing the clock resources:
1. System Oscillator Management and Control Register 1, see Section 5.8.10, “System Oscillator
Management and Control Register 1 (SOMC1)”- this register sets the CPU clock prescale integer,
enables the 32.768 kHz oscillator, controls the Stop mode oscillator, and enables the optional clock
out pin for the 32.768 kHz oscillator.
2. System Oscillator Management and Control Register 2, see Section 5.8.11, “System Oscillator
Management and Control Register 2 (SOMC2)”- this register controls the trim capacitance that
adjusts the reference oscillator frequency.
3. System Clock Gating Control Registers, see Section 5.8.12, “System Clock Gating Control 1
Register (SCGC1)” and Section 5.8.13, “System Clock Gating Control 2 Register (SCGC2)” -
these registers provide control bits to disable the bus clock to the various peripheral modules. For
power sensitive applications, the current can be minimized by disabling the bus clock to non-used
circuitry.
4. The 1 kHz RC oscillator is disabled if not selected as a source for either the RTC or the COP.
5.5
Management of Timer Resources
To help control operational modes and provide wake-up services to the HCS08, there are the Real-Time
Counter (RTC) and COP blocks.
5.5.1
RTC Timer Resource
The RTC provides a resource for low power wake-up and time “ticks” applicable for software use. The
RTC is described in a separate Chapter 10, “Real-Time Counter (RTC)”.
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5.5.2
Computer Operating Properly (COP) Timer
The COP is a watchdog timer for the MCU and is intended to force a system reset when the application
software fails to execute as expected. To prevent a system reset caused by the COP timer (when it is
enabled), application software must reset the COP counter periodically. If the application program gets lost
and fails to reset the COP counter before it times out, a system reset is generated to force the system back
to a known starting point.
NOTE
The COP is enabled by default when exiting reset. If COP operation is
undesired, it should be disabled as part of the device initialization.
Features of the COP include:
•
•
•
Clock sources include bus clock and the 1 kHz RC clock
Two time-out periods are available for each clock source
The COP is controlled the following bits -
— COPE - COP enable bit, Register SOPT1
— COPT - COP time-out bit, Register SOPT1
— COPCLKS - COP clock source select bit, Register SOPT2
•
The SRS Register (see Section 5.8.1, “Interrupt Pin Request Status and Control Register
(IRQSC)”) also relates to COP operation
— Writing the SRS register address resets the COP timer
— If the COP times-out causing a system reset, the status is reported in the SPS COP status bit.
The COPE bit is the primary enable for the COP (see Section 5.8.4, “System Options Register 1
(SOPT1)”):
•
•
After any reset, the COPE bit becomes set in SOPT1 enabling the COP watchdog.
If the COP watchdog is not used in an application, it can be disabled by clearing COPE.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2)” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1 kHz clock source.
With each clock source, there is an associated short and long time-out controlled by COPT in SOPT1.
Table 5-1 summaries the control functions of the COPCLKS and COPT bits. The COP watchdog defaults
8
to operation from the 1 kHz clock source and the associated long time-out (2 cycles).
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Table 5-1. COP Configuration Options
Control Bits
COPCLKS
COP Overflow
Count
Clock Source
COPT
0
0
1
1
0
1
0
1
~1 kHz
~1 kHz
Bus
25 cycles (32 mS)
28 cycles (256 ms)
213 cycles
Bus
218 cycles
NOTE
Even if the application uses the reset default settings of COPE, COPCLKS,
and COPT, the user must write to the write-once SOPT1 and SOPT2
registers during reset initialization to lock in the settings. That way, the
settings cannot be changed accidentally if the application program gets lost.
The initial writes to SOPT1 and SOPT2 will reset the COP counter.
The COP counter is reset by writing any value to the address of SRS. This write does not affect the data in
the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP
counter.
NOTE
The write to SRS that services (clears) the COP counter must not be placed
in an interrupt service routine (ISR) because the ISR could continue to be
executed periodically even if the main application program fails.
With regard to operation during Stop mode:
•
When the bus clock source is selected, the COP counter does not increment while the system is in
Stop mode. The COP counter resumes as soon as the MCU exits stop mode.
•
When the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to
Stop mode. The COP counter begins from zero after the MCU exits stop mode.
In background debug mode, the COP counter will not increment.
5.6
Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated status flag will become set. The CPU will
not respond unless the local interrupt enable is set to enable the interrupt and the I bit in the CCR is 0 to
allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which prevents all
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maskable interrupt sources. The user program initializes the stack pointer and performs other system setup
before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction
and consists of:
•
•
•
•
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of
another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is
restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit
can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other
interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle
program errors that are difficult to debug.
NOTE
In order for the ISR to be available in the memory map regardless of the
PPAGE value, ISRs should be located in Pages 0, 1, or 3.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-2).
5.6.1
Interrupt Stack Frame
Figure 5-2 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
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UNSTACKING
ORDER
TOWARD LOWER ADDRESSES
0
²
7
SP AFTER
INTERRUPT STACK
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
*
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
SP BEFORE
THE INTERRUPT
²
²
STACKING
ORDER
TOWARD HIGHER ADDRESSES
²
* High byte (H) of index register is not automatically stacked.
Figure 5-2. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning
from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is
generated by this same source, it will be registered so it can be serviced after completion of the current ISR.
5.6.2
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
Stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ pin (if
enabled) can wake the MCU. The external IRQ pin is shared with I/O PTA3.
5.6.2.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software (IRQIE).
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pullup
or pulldown depending on the polarity chosen. If the user desires to use an external pullup or pulldown,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
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NOTE
This pin does not contain a clamp diode to V and should not be driven
DD
above V
.
DD
NOTE
The voltage measured on the internally pulled up RESET pin will not be
pulled to V . The internal gates connected to this pin are pulled to V
.
DD
DD
The RESET pullup should not be used to pullup components external to the
MCU.
5.6.2.2
Edge and Level Sensitivity
The IRQMOD control bit configures the detection logic so it detects edge events and pin levels. In the edge
and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the de-asserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.6.3
Interrupt Vectors, Sources, and Local Masks
Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is set, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Table 5-2. Vector Summary
Vector Vector
Address
(High/Low)
Vector
Name
Module
Source
Enable
Description
Priority
No
Lowest
261
0xFFCA/0xFFCB
Vadc
ADC
COCO
AIEN
Analog-to-digital
converter
25
24
0xFFCC/0xFFCD
Vrtc
RTC
KBI1
KBI2
IIC
RTIF
KBF1
RTIE
KBIE1
KBIE2
IICIE
Real-time clock
Keyboard1 x pins
Keyboard2 x pins
IICx control
0xFFCE/0xFFCF Vkeyboard1
0xFFD0:0xFFD1 Vkeyboard2
232
22
21
KBF2
0xFFD2/0xFFD3
0xFFD4/0xFFD5
0xFFD6/0xFFD7
Viicx
Vcmt
Vscitx
IICIS
CMT
SCI
EOCF
TDRE,TC
EOCIE
TIE,TCIE
CMT
20
SCI transmit
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Table 5-2. Vector Summary
Vector Vector
Address
(High/Low)
Vector
Name
Module
Source
Enable
Description
Priority
No
19
0xFFD8/0xFFD9
Vscirx
SCI
IDLE,
LBKDIF,
RDRF,
ILIE, LBKDIE, RIE,
RXEDGIE
SCI receive
RXEDGIF
18
17
0xFFDA/0xFFDB
0xFFDC/0xFFDD
Vscierr
Vspi
SCI
SPI
OR, NF,
FE, PF
ORIE, NFIE,
FEIE, PFIE
SCI error
SPI
SPIF, MODF,
SPTEF
SPIE SPTIE
16
15
14
13
12
11
10
9
0xFFDE/0xFFDF
0xFFE0/0xFFE1
0xFFE2/0xFFE3
0xFFE4/0xFFE5
0xFFE6/0xFFE7
0xFFE8/0xFFE9
0xFFEA/0xFFEB
Vtpm4ovf
Vtpm4ch0
Vtpm3ovf
Vtpm3ch0
Vtpm2ovf
Vtpm2ch0
Vtpm1ovf
TPM4
TPM4
TOF
CH0F
TOF
TOIE
CH0IE
TPM4 overflow
TPM4 channel 0
TPM3 overflow
TPM3 channel 0
TPM2 overflow
TPM2 channel 0
TPM1 overflow
TPM1 channel 0
AES 128 Cipher
TPM3
TOIE
TPM3
CH0F
TOF
CH0IE
TPM2
TOIE
TPM2
CH0F
TOF
CH0IE
TPM1
TOIE
0xFFEC/0xFFED Vtpm1ch0
0xFFEE/0xFFEF
TPM1
CH0F
AES
CH0IE
8
AES128
802.15.4
AES_MASK
RX_WMRK_MSK
7
0xFFF0/0xFFF1
802.15.4
RX DMA
802.15.4 PHY
RX WTR MRK
6
0xFFF2/0xFFF3
802.15.4
802.15.4
Event
Timers
TMR4MSK
TMR3MSK
TMR2MSK
TMR1MSK
802.15.4 PHY TIMERS
5
4
0xFFF4/0xFFF5
0xFFF6/0xFFF7
802.15.4
802.15.4
802.15.4
TX
TXMSK
LO1_UNLOCK_MSK
SEQMSK
802.15.4 PHY TX
802.15.4 PHY RX
802.15.4
RX/CCA
RX_RCVD_MSK
LO1_UNLOCK_MSK
CCAMSK
FLITERFAIL_MSK
SEQMSK
3
2
0xFFF8/0xFFF9
0xFFFA/0xFFFB
Vlvd
Virq
System LVDF, LVWF
control
LVDIE, LVWIE
Low-voltage detect,
Low-voltage warning
IRQ
IRQF
IRQIE
IRQ pin
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Table 5-2. Vector Summary
Vector Vector
Address
(High/Low)
Vector
Name
Module
Source
Enable
Description
Priority
No
1
0xFFFC/0xFFFD
0xFFFE/0xFFFF
Vswi
Core
SWI
Instruction
—
Software interrupt
Highest
0
Vreset
System
control
COP,
LVD,
RESET pin,
Illegal
COPE
LVDRE
—
Watchdog timer
Low-voltage detect
External pin
—
Illegal opcode
opcode,
1
2
ADC interrupt (vector 26) is available only in MC13237.
KBI2 interrupt (vector 23) is available only in MC13234.
5.7
Modes of Operation
The HCS08 provides the following modes of operation:
•
•
Active background mode for code development
Run mode — CPU running at full speed and the internal supply is fully regulated, radio optionally
active.
•
•
•
•
LPRun mode — CPU clock is set to 500 kHz and peripheral clocks (bus clock) to 250 kHz and the
internal voltage regulator is in standby, radio optionally active.
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained, radio optionally active.
LPWait mode — CPU shuts down to conserve power; peripheral clocks are set to 250 kHz and the
internal voltage regulator is in standby, radio optionally active.
Stop3 mode — System clocks are stopped and voltage regulator is in standby. All internal circuits
are powered for fast recovery, radio optionally active, (full regulation set before entering stop).
5.7.1
Run Mode
This is the normal operating mode for the HCS08. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
The 802.15.4 transceiver is available for any transmit or receive operations. The clock CPU frequency is
controlled through the RDIV register to yield: 32, 16, 8, 4, 2, 1, and 0.5 MHz.
5.7.2
Low Power Run Mode (LPRun)
In the low power run mode, the bus clock is modified such that the 32MHz reference clock is divided by
64. In this state, the 802.15.4 transceiver is available for any transmit or receive operations. Power
consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the
corresponding bits in the SCGC1 and SCGC2 registers. The digital regulator is held in standby mode.
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Before entering this mode, the following conditions must be met:
•
The LVDE or LVDSE bit in SPMSC1 register must be clear. LVD and LVW will automatically be
disabled.
•
•
Flash programming/erasing is not allowed.
The MCU cannot be in active background mode.
After these conditions are met, low power run mode can be entered by setting the LPR bit in the SPMSC2
register.
To exit LPRun and re-enter standard run mode, simply clear the LPR bit:
•
The LPRS bit in the SPMSC2 register is a read-only status bit that can be used to determine when
the regulator has returned to full regulation mode.
•
When LPRS is cleared to ‘0’, the regulator is in full regulation mode and the MCU has
automatically returned to full CPU clock speed (RDIV = 0x0). If the application was using a lower
CPU clock rate before entering LPRun, this condition must be re-initiated by writing RDIV field.
5.7.2.1
Interrupts in Low Power Run Mode
Low power run mode provides the option to return to full regulation if any interrupt occurs. This is done
by setting the LPWUI bit in the SPMSC2 register. The bus clock returns to full speed immediately in the
interrupt service routine.
If the LPWUI bit is clear, interrupts will be serviced in low power run mode.
5.7.2.2
Resets in Low Power Run Mode
Any reset will exit low power run mode, clear the LPR and LPRS bits and return the device to normal run
mode.
5.7.3
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of six ways:
•
•
When the BKGD/MS pin is low during POR
When the BKGD/MS pin is low immediately after issuing a background debug force reset (see
Section 5.8.3, “System Background Debug Force Reset Register (SBDFR)”)
•
•
•
•
When a BACKGROUND command is received through the BKGD/MS pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
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Background commands are of two types:
•
Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
•
Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the flash
program memory before the MCU is operated in run mode for the first time. When the HCS08 is shipped
from the Freescale Semiconductor factory, the flash program memory is erased by default unless
specifically noted, so there is no program that could be executed in run mode until the flash memory is
initially programmed. The active background mode can also be used to erase and reprogram the flash
memory after it has been previously programmed.
For additional information about the active background mode, see Chapter 18, “Development Support”.
5.7.4
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The 802.15.4 transceiver can be active during this
mode; completing a transmit or receive operation initiated during Run mode.The I bit in CCR is cleared
when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits
the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt
service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
5.7.5
Low Power Wait Mode (LPWait)
Low power wait mode is entered by executing a WAIT instruction while the MCU is in low power run
mode. The 802.15.4 transceiver can be active during this mode; completing a transmit or receive operation
initiated during LPRun mode. In the low power wait mode, the on-chip voltage regulator remains in its
active state as in the low power run mode and the bus clock is 250 kHz. In this state, the power
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consumption is reduced to a minimum that still allows most modules to maintain functionality. Power
consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the
corresponding bits in the SCGC register.
The same restrictions from the low power run mode apply to low power wait mode.
5.7.5.1
Interrupts in Low Power Wait Mode
If the LPWUI bit is set, then the voltage regulator will return to full regulation. LPWait mode is exited to
Run mode. The LPR and LPRS bits will be cleared and the MCU will be clock from the XOSC2 oscillator
(32MHz).
If the LPWUI bit is clear an interrupt will return the device to low power run (LPRun) mode.
5.7.5.2
Resets in Low Power Wait Mode
Any reset will exit low power wait mode, clear LPR and LPRS bit, and return the device to normal run
mode.
5.7.6
Stop3 Mode
Stop3 is entered upon execution of a STOP instruction when the STOPE bit in the System Option 1
Register (SOPT1) is set. In Stop3 mode, the CPU and bus clocks are halted. The regulator can be
configured for standby or active mode. The 32 kHz and 32 MHz crystal oscillators can be configured as
active or in standby in Stop3 mode.
If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter Stop3 mode
and an illegal opcode reset is forced. Stop3 mode is selected by setting the appropriate bits in the
Section 5.8.8, “System Power Management Status & Control 2 (SPMSC2)”.
Table 5-3 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 5-3. Stop Mode Selection
Register SOPT1 BDCSCR
SPMSC1
SPMSC2
Stop Mode
Bit
name
STOPE ENBDM 1
LVDE
LVDSE
PPDC
0
x
x
x
Stop modes disabled; illegal opcode reset if STOP
instruction executed
1
1
1
1
0
0
x
x
x
0
Stop3 with BDM enabled 2
Stop3 with voltage regulator active
Stop3
Both bits must be 1
Either bit to 0
1
2
ENBDM is located in the BDCSCR which is only accessible through BDC commands.
When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled.
MC13234/MC13237 Reference Manual, Rev. 1.8
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System Management and Control
5.7.6.1
Description
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 5-3. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the RTC,
LVD, LVW, IRQ, SCI or the KBI.
If Stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
The 802.15.4 transceiver will be off in this mode. In Stop3 mode the digital regulator will be in standby
mode.
5.7.6.2
Active BDM Enabled in Stop3 Mode
The advantage of Stop3 mode is the low current consumption of the device. While MC13234/MC13237
is in Stop3 mode, circuit blocks are turned off to reduce consumption. BDM (Background Debug Module)
is also disabled. For debug purpose, BDM can be enabled to let the external BDM module communicate
to MC13234/MC13237. To enable BDM in Stop3 mode, the following bits should be set prior the STOP
command is issued:
SOPT1 bit 1: BKGDPE
SCGC2 bit 6: DBG
5.7.6.3
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in Stop3 mode (LVDE and LVDSE bits in SPMSC1 both set), the
voltage regulator remains active during stop mode.
5.7.6.4
Stop3 Mode in Low Power Run Mode
Stop3 mode can be entered from low power run mode by executing the STOP instruction while in low
power run. Exiting Stop3 with a reset will put the device back into normal run mode. If LPWUI is clear,
interrupts will exit Stop3 mode, return the device to low power run mode, and then service the interrupt.
If LPWUI is set, interrupts will exit Stop3 mode, put the device into normal run mode, clear LPR and LPRS
bits, and then service the interrupt.
5.7.6.5
Wake-up Time from Stop3 Mode
The dominating factor for Stop3 wake-up time is the reference oscillator start-up time. In Stop3 mode, the
reference oscillator can optionally be running. If the reference oscillator is off in Stop3 mode, the startup
time is specified at 800 µs typical. This will determine the wakeup time from Stop3 mode. If the reference
oscillator is running in Stop3 mode, the wake up time will be significantly less.
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Freescale Semiconductor
5-15
System Management and Control
When the reference oscillator must start, it is specified at 800 s typical startup time and this will
determine the wake-up. It the reference oscillator is already running, the wake-up time will be significantly
less.
5.7.6.6
Stop3 and LPRun Mode Transition
In both MC13234 and MC13237, transition between Stop3 and LPRUN mode needs extra steps when the
LPWUI bit is used. In Run mode, going to LPRun mode (LPR = 1), if LPWUI is set before entering Stop3.
The device will exit Stop3 with full regulation (Run mode) when an interrupt is received. However, it will
not enter LPRun mode even LPR is set. Until the device enters Stop3 mode again. Then it will enter LPRun
again with LPR = 1. The following diagram illustrates this transition.
Figure 5-3. LPRun-to-Stop3 Diagram
5.7.7
Mode Selection
Several control signals are used to determine the current operating mode of the device. Table 5-4 shows
the conditions for each of the device’s operating modes.
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
System Management and Control
Affects on Sub-System
Table 5-4. Power Mode Selections
XXCSR
BDM
SPMSC1
PMC
SPMSC2
PMC
CPU & Peripheral
CLKs
Mode of Operation
BDM
Voltage
ENBDM 1 LVDE LVDSE LPR
PPDC
Clock
Regulator
Run mode
0
x
1
x
0
1
x
1
x
0
1
x
1
x
x
0
x
1
x
x
0
0
1
x
1
x
on.
off
on
1
0
on
off
LPRun mode
0
x
32MHz osc clock
divided by 64
standby
on
Wait mode - (Assumes WAIT
instruction executed.)
0
0
1
x
1
CPU clock is off;
peripheral clocks
on.
off
1
0
on
off
LPWait mode - (Assumes WAIT
instruction executed.)
0
CPU clock is off;
peripheral clocks
at low speed
standby
(250 kHz).
Stop3 - (Assumes STOPE bit is
set and STOP instruction
executed.)
0
0
0
1
0
1
1
x
x
0
1
x
x
x
x
x
0
0
x
x
CPUandperipheral
clocks are off.
32 MHz Osc and 32
kHz Osc optionally
on
off
off
off
on
standby
on - stop
currents will
be increased
1
Design Interlock: If STOP was issued from LPRun, then Stop3 will be entered
Table 5-5. MCU Allowable Power Mode Transitions for MC13234/MC13237
Mode
Digital Regulator State
Run
Wait
Full on
Full on
LPRun
LPWait
Stop3
Standby
Standby
Standby
Figure 5-4 shows mode state transitions allowed between the legal states.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
5-17
System Management and Control
Figure 5-4. Stop Mode State Diagram
Table 5-6 defines triggers for the various state transitions shown in Figure 5-4.
Table 5-6. Triggers for Transitions.
Transition #
From
To
Trigger
1
2
Run
LPRun
Run
Configure settings shown in Table 5-3, switch LPR=1 last
Clear LPR
LPRun
Interrupt when LPWUI=1
3
Run
Stop3
Run
STOP instruction and STOPE=1
Stop3
Interrupt IF LPR = 0
or LPR=1 AND LPWUI=1
or reset
4
5
6
Stop3
LPRun
LPWait
LPRun
LPWait
Wait
LPRun
Stop3
LPRun
LPWait
Run
Interrupt when LPWUI=0
STOP instruction and STOPE=1
Interrupt when LPWUI=0
WAIT instruction
7
8
9
Interrupt when LPWUI=1
Interrupt or reset
10
11
Run
Run
Wait
WAIT instruction
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System Management and Control
5.7.8
On-Chip Peripheral Modules in Stop and Low Power Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. See Section 5.7.6, “Stop3
Mode”, for specific information on system behavior in Stop3 mode.
When the MCU enters LPWait or LPRun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1 and SCGC2).
Table 5-7. Stop and Low Power Mode Behavior
Mode
Peripheral
Stop3
LPWait
LPRun
802.15.4 Transceiver (transceiver)
Off
Optionally On1
Off
Optionally On
Optionally On
Off
Optionally On
Optionally On
On during PHY active
On
802.15.4 Transceiver Timers
Voltage Regulators Analog
CPU
Standby
Standby
RAM
Standby
Standby
On
Flash
Standby
Standby
On
Port I/O Registers
Standby
Standby
On
Port I/O Pins
Peripheral Control
Optionally On
Off
Peripheral Control
Off2
On
Off2
BDM
COP
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
On
AES
Off
IIC
Standby
KBIx
Optionally On
Optionally On
Optionally On
Optionally On
Standby
LVD/LVW
RTC
IRQ
SCI
SPI
Standby
TPMx
Standby
CMT
Standby
Voltage Regulator Digital
XOSC_32M
XOSC_32K
1KHz_RC
Partial Power down
Optionally On
Optionally On
Optionally On
On
On
Optionally On
Optionally On
Optionally On
Optionally On
1
2
Requires the digital regulator to be in high accuracy mode during Stop3.
If ENBDM is set when entering LPRun or LPWait, the MCU will actually stay in run mode or enter wait
mode, respectively.
5.8
System Control Register Definitions
The registers that manage system control are detailed in the following sections.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
5-19
System Management and Control
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
IRQSC
0x0076
7
6
5
4
3
2
1
0
R
W
0
IRQF
0
IRQPDD
0
IRQEDG
IRQPE
IRQIE
IRQMOD
IRQACK
0
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-5. Interrupt Request Status and Control Register (IRQSC)
Table 5-8. IRQSC Register Field Descriptions
Field
Description
6
Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pullup/pulldown device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
IRQPDD
1 IRQ pull device disabled if IRQPE = 1.
5
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When IRQEDG = 1 and the internal pull device is enabled, the
pullup device is configured as an optional pulldown device.
IRQEDG
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
IRQPE
0 IRQ pin function is disabled pin PTA3 enable.
1 IRQ pin function is enabled.
3
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
IRQF
0 No IRQ request.
1 IRQ event detected.
2
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQACK
1
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
IRQIE
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.6.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
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System Management and Control
5.8.2
System Reset Status Register (SRS)
All bits in the SRS register are read only. The SRS register is updated whenever a reset occurs and indicates
the cause of the last system reset. Every active reset source has its corresponding bit set. Every inactive
reset source has its corresponding bit cleared.
Writes to this address affect the COP function.
SRS
0x1800
7
6
5
4
3
2
1
0
R
W
POR
PIN
COP
ILOP
ILAD1
0
LVD
0
Writing any value to SRS register clears the COP watchdog timer
POR Reset:
LVD Reset:
Other Resets:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Note2
Note2
Note2
Figure 5-6. System Reset Status Register (SRS)
Illegal address detection is dependent on memory map usage.
1
2
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set: bits
corresponding to sources that are not active at the time of reset entry will not be set
Table 5-9. SRS Register Field Descriptions
Field
Description
7
POR
Power-On Reset — The POR bit indicates a power-on reset has been detected.
0 Power-on reset not detected.
1 Power-on reset detected
6
PIN
External PIN Reset — The PIN bit indicates an external reset has been detected.
0 External reset not detected.
1 External reset detected.
5
Computer Operating Properly Reset— The COP bit indicates a COP reset has been detected.
COP
0 COP reset not detected.
1 COP reset detected.
4
Illegal Opcode Reset — The ILOP bit indicates an illegal opcode reset has been detected.
0 Illegal opcode reset not detected.
ILOP
1 Illegal opcode reset detected
4
ILAD
Illegal Address Reset — The ILAD bit indicates an illegal address reset has been detected.
0 Illegal address reset not detected.
1 Illegal address reset detected.
1
LVD
Low Voltage Reset — The LVD bit indicates a low voltage reset or a POR reset has been detected.
0 Low voltage reset not detected.
1 Low voltage reset detected.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
5-21
System Management and Control
5.8.3
System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
SBDFR
0x1801
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
BDFR1
0
Reset:
0
0
0
0
0
0
0
= Unimplemented or Reserved
1
BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-7. System Background Debug Force Reset Register (SBDFR)
Table 5-10. SBDFR Register Field Descriptions
Description
Field
0
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.To enter user mode, PTD7/BKGD/MS must be high immediately after issuing
WRITE_BYTE command. To enter BDM, PTD7/BKGD/MS must be low immediately after issuing WRITE_BYTE
command.
BDFR
NOTE
Forcing a system reset using the BDFR results in a reload of the SRS
register. Resetting by this method is directly controlled by the user and does
not result in the set of any bits of the SRS register unless they become
pending on the same cycle.
5.8.4
System Options Register 1 (SOPT1)
All bits of the SOPT1 register are write-once after any system reset.
SOPT1
0x1802
7
6
5
4
3
2
1
0
R
W
0
0
0
COPE
COPT
STOPE
ADCHT
BKGDPE
POR/LVD Resets:
All other Resets:
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
u1
= Unimplemented or Reserved
Figure 5-8. System Options Register 1 (SOPT1)
MC13234/MC13237 Reference Manual, Rev. 1.8
5-22
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System Management and Control
1
u = unaffected
Table 5-11. SOPT1 Register Field Descriptions
Description
Field
7
COP Enable — The COPE bit enables the COP.
COPE
0 COP disabled.
1 COP enabled.
6
COP Time-out — The COPT bit selects the COP time-out period. See 5.5.2, “Computer Operating Properly
(COP) Timer” for additional details of operation.
COPT
0 COP short time-out period selected.
1 COP long time-out period selected.
5
STOP Enable — The STOPE bit enables the STOP instruction. If the STOP instruction is disabled and a STOP
STOPE
instruction is executed, then an illegal opcode reset occurs. See Section 5.7.6, “Stop3 Mode” for details on reset
handling.
0 STOP instruction disabled
1 STOP instruction enabled
4
ADC Hardware Trigger
ADCHT
0 ADC hardware trigger source is RTC
1 ADC hardware trigger source is PTC[6]
1
BKGD Pin Enable — When BKGD/MS is shared with general-purpose I/O through chip-level hookup, The
BKGDPE BKGDPE bit enables the BKGD/MS pin to function as BKGD. When the BKGDPE bit is clear, the pin functions
as general-purpose I/O, which must be implemented as output-only.
0 BKGD pin disabled.
1 BKGD pin enabled.
5.8.5
System Options Register 2 (SOPT2)
The COPCLKS bit in the SIMOPT2 register is a write-once field after any system reset.
SOPT2
0x1803
7
6
5
4
3
2
1
0
R
W
0
0
0
0
PID
COPCLKS1
ADCCG
Reset:
0
0
0
0
0
0
PID2
= Unimplemented or Reserved
Figure 5-9. SIM Options Register 2 (SIMOPT2)
1
2
This bit can be written only one time after reset. Additional writes are ignored.
See Table 5-12 for reset values.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
5-23
System Management and Control
Table 5-12. SOPT2 Register Field Descriptions
Description
Field
7
COP Clock Source Select — The COPCLKS bit selects the COP clock source.{See 5.5.2, “Computer Operating
COPCLKS Properly (COP) Timer” for additional details of operation.
0 COP logic runs from independent on-chip 1kHz clock source.
1 COP logic runs from system bus clock.
4
ADC Clock Gating — The ADCCG bit must be set for the ADC to be enabled. This is only applicable to
ADCCG
MC13237.
0 ADC not enabled
1 ADC enabled
1:0
Product ID — The read-only field PID identifies which part you are using.
PID
00 MC13234
11 MC13237
5.8.6
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the
MC13234/MC13237 version. This allows the development software to recognize where specific memory
blocks, registers, and control bits are located in the MCU.
SDIDH
0x1806
7
6
5
4
3
2
1
0
R
W
ID11
ID10
ID9
ID8
Reset:
x
x
x
x
0
0
0
0
= Unimplemented or Reserved
Figure 5-10. System Device Identification Register — High (SDIDH)
Table 5-13. SDIDH Register Field Descriptions
Description
Field
3:0
Part Identification Number — MC13234/MC13237 identification number. See ID bits in Table 5-15.
ID[11:8]
SDIDL
0x1807
7
6
5
4
3
2
1
0
R
W
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Reset:
0
1
0
0
0
1
0
0
= Unimplemented or Reserved
Figure 5-11. System Device Identification Register — Low (SDIDL)
MC13234/MC13237 Reference Manual, Rev. 1.8
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System Management and Control
Table 5-14. SDIDL Register Field Descriptions
Description
Field
7:0
Part Identification Number — MC13234/MC13237 identification number. See ID bits in Table 5-15.
ID[7:0]
Table 5-15. Device ID Lookup
Device
SIDIDH
SIDIDL
MC13234
MC13237
0x20
0x30
0x44
0x44
5.8.7
System Power Management Status & Control 1 (SPMSC1)
SPMSC1 contains the status and control bits associated with the PMC Voltage Regulator (VREG) and
Low Voltage Detect (LVD) functions.
SPMSC1
0x1808
7
6
0
5
LVDIE
0
4
LVDRE2
1
3
LVDSE
1
2
11
0
0
R
LVDF
LVDE2
1
W
LVDACK
RESET:
0
0
0
= Unimplemented or Reserved
U = Unaffected by MCU Reset
1
2
Bit 1 is a reserved bit that must always be written to 0.
Write once only after any system reset
Figure 5-12. System Power Management Status & Control 1 Register (SPMSC1)
Table 5-16. SPMSC1 Register Field Descriptions
Description
Field
LVDF
Low-Voltage Detect Flag. This bit indicates the Low-Voltage Detect status if LVDE is set.
1 = Low voltage is being or has been detected.
0 = Low voltage has not been detected.
LVDACK
LVDIE
Low-Voltage Detect Interrupt Acknowledge.
Writing a logic 1 to LVDACK clears the LVD interrupt request and clears LVDF to a logic 0 if low voltage is not
currently being detected.
Low-Voltage Detect Interrupt Enable. This bit enables hardware interrupt requests for LVDF.
1 = LVD interrupt enabled when LVDF=1.
0 = LVD interrupt disabled (use polling).
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
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System Management and Control
Table 5-16. SPMSC1 Register Field Descriptions (continued)
Field
Description
LVDRE
Low-Voltage Detect Reset Enable. This write-once bit enables LVDF events to generate a hardware reset. LVD
reset has priority over LVD interrupt, if both are enabled. In all test modes, the LVDRE bit value is ignored and
functions as if the LVDRE bit value is equal to 0.
1 = Force an MCU reset when LVDF=1.
0 = LVDF does not generate hardware resets.
LVDSE
LVDE
Low-Voltage Detect Stop Enable. Provided LVDE=1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
1 = Low-voltage detect enabled during stop mode.
0 = Low-voltage detect disabled during stop mode.
Low-Voltage Detect Enable Bit. This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
1 = Low-Voltage Detect logic is enabled.
0 = Low-Voltage Detect logic is disabled.
5.8.8
System Power Management Status & Control 2 (SPMSC2)
SPMSC2 contains status and control bits associated with the PMC power down modes.
SPCSC2
0x1809
7
6
5
4
0
3
2
0
1
0
R
W
LPRS
PPDE1
LPR
LPWUI
PPDC
RESET:
0
0
0
0
0
0
0
0
U
0
0
0
1
1
0
0
POR and LVD:
= Unimplemented or Reserved
1Write once only after any system reset.
U = Unaffected by MCU Reset
Figure 5-13. System Power Management Status & Control 2 Register (SPMSC2)
Table 5-17. SPMSC2 Register Field Descriptions
Description
Field
LPR
Low Power Regulator Control. This bit controls entry into the low power run and wait modes in which the voltage
regulator is put into loose regulation. This bit cannot be set if PPDC is set. If PPDC and LPR are set in a single
write instruction, then only PPDC will be set.
1 = Low power run and wait modes are enabled.
0 = Low power run and wait modes are disabled.
LPRS
Low Power Regulator Status. This read-only status bit indicates that the voltage regulator has entered into loose
regulation for the low power run or wait mode. Low power run mode cannot be entered if ENBDM is asserted or
if ICS_SAFE_FOR_LPRUN_MODE is clear.
1 = The voltage regulator is currently in loose regulation.
0 = The voltage regulator is not currently in loose regulation.
MC13234/MC13237 Reference Manual, Rev. 1.8
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System Management and Control
Table 5-17. SPMSC2 Register Field Descriptions (continued)
Field
Description
LPWUI
Low Power Wake Up on Interrupt. This bit controls whether or not the voltage regulator exits loose regulation
when any active MCU interrupt occurs.
1 = The voltage regulator will exit loose regulation on an interrupt and clear LPR.
0 = The voltage regulator will remain in loose regulation on an interrupt.
PPDE
PPDC
Partial Power Down Enable. This write-once bit enables the partial power down feature.
0 = Stop3 mode enabled
Partial Power Down Control. This bit controls which power down mode is selected. This bit cannot be set if LPR
is set. If LPR and PPDC are set in a single write instruction, then only PPDC will be set. PPDE must be set to
set PPDC.
0 = Stop3 low power mode enabled.
5.8.9
System Power Management Status & Control 3 (SPMSC3)
SPMSC3 contains status and control bits associated with the PMC Low Voltage Warning (LVW) and with
selecting the low voltage trip point levels .
SPCSC3
0x180B
7
6
5
4
3
2
0
1
0
0
0
R
W
LVWF
0
LVDV
LVWV
LVWIE
LVWACK
RESET:
POR:
LVD:
01
01
01
0
0
0
U
0
U
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
= Unimplemented or Reserved
U = Unaffected by MCU Reset
1 LVWF will be set not just in the case when Vsupply transitions below the trip point but also after reset and Vsupply is
already below VLVW. So, LVWF value for RESET and POR will be logic 1 if Vsupply is already below VLVW
.
Figure 5-14. System Power Management Status & Control 3 Register (SPMSC3)
Table 5-18. SPMSC3 Register Field Descriptions
Field
LVWF
Description
Low-Voltage Warning Flag. This bit indicates the Low Voltage Warning status if LVDE is set.
1 = Low voltage warning is present or was present.
0 = Low voltage warning not present.
LVWACK Low-Voltage Warning Acknowledge. Writing a logic 1 to LVWACK clears LVWF to a logic 0 if a low voltage
warning is not currently present.
LVDV
Low-Voltage Detect Voltage Select. This bit selects the low voltage detect trip point voltage (VLVD). See
Table 5-19 for definition of these voltages.
1 = High trip point selected (VLVD = VLVDH).
0 = Low trip point selected (VLVD = VLVDL).
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System Management and Control
Table 5-18. SPMSC3 Register Field Descriptions (continued)
Field
Description
LVWV
Low-Voltage Warning Voltage Select. This bit selects the low voltage warning trip point voltage (VLVW). See
Table 5-19 for definition of these voltages.
1 = High trip point selected (VLVW = VLVWH).
0 = Low trip point selected (VLVW = VLVWL).
LVWIE
Low-Voltage Warning Interrupt Enable. This bit enables hardware interrupt requests for LVWF.
1 = LVW interrupt enabled when LVWF=1.
0 = LVW interrupt disabled (use polling).
1
Table 5-19. LVD and LVW Trip Point Table
Parameter
Symbol
Min
Typ
Max
Unit
High LVD trip point (VSUPPLY falling, LVDV=1)
High LVD trip point (VSUPPLY rising, LVDV=1)
Low LVD trip point (VSUPPLY falling, LVDV=0)
Low LVD trip point (VSUPPLY rising, LVDV=0)
High LVW trip point (VSUPPLY falling, LVWV=1)
High LVW trip point (VSUPPLY rising, LVWV=1)
Low LVW trip point (VSUPPLY falling, LVWV=0)
Low LVW trip point (VSUPPLY rising, LVWV=0)
VLVDH
VLVDH
VLVDL
VLVDL
VLVWH
VLVWH
VLVWL
VLVWL
2.23
2.23
1.67
1.74
2.29
2.33
1.78
1.81
2.26
2.26
1.7
2.29
2.29
1.73
1.8
V
V
V
V
V
V
V
V
1.77
2.32
2.36
1.81
1.84
2.35
2.39
1.84
1.81
1
Not measured on test; checked periodically.
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System Management and Control
Figure 5-15. LVD and LVW Illustration
5.8.10 System Oscillator Management and Control Register 1 (SOMC1)
This register contains control bits for the 32 kHz (XTAL0) and 32 MHz (XTAL1) oscillators.
SOMC1
0x180C
7
6
5
4
3
2
1
0
R
W
XTAL0_TS
T_OUT
RDIV
XTAL0EN XTAL0STEN1 XTAL1STEN1 Reserved
PoR Exit:
Other Reset:
0
u
0
u
0
u
0
u
1
u
1
u
0
0
0
0
= Unimplemented or Reserved
These bits are write-once till next reset
1
Figure 5-16. System Oscillator Management and Control Register 1 (SOMC1)
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System Management and Control
Table 5-20. SOMC1 Register Field Descriptions
Description
Field
[7:5]
Bus Frequency Divider — This controls the CPU clock rate. It sets the ratio to divide down the
RDIV[2:0]
32 MHz reference clock. See Table 5-21.
4
Crystal 0 Oscillator (32.768 kHz) Enable
0 Oscillator disabled.
XTAL0EN
1 Oscillator enabled.
3
Crystal 0 Oscillator (32.768 kHz) Stop3 Mode Enable
0 Oscillator disabled in Stop3 mode.
XTAL0STEN
1 Oscillator enabled in Stop3 mode.
2
Crystal 1 Oscillator (32MHz) Stop3 Mode Enable
0 Oscillator disabled in Stop3 mode.
XTAL1STEN
1 Oscillator enabled in Stop3 mode.
1
Reserved
Reserved
0
Crystal 0 Test Out (32 kHz) Enable
XTAL0_TST_OUT 0 Oscillator output not available at pin.
1 Oscillator output available at GPIO pin.
Table 5-21. CPU Clock vs. RDIV[2:0] Field
RDIV[2:0]
Divide Ratio
CPU Clock
000
001
010
011
100
101
110
111
1 (Default)
32 MHz
16 MHz
8 MHz
2
4
8
4 MHz
16
32
64
64
2 MHz
1 MHz
500 kHz
500 kHz
5.8.11 System Oscillator Management and Control Register 2 (SOMC2)
This register controls the trim capacitance value for the 32 MHz reference oscillator. The primary
capacitive loading for the crystal oscillator is discrete external capacitors and the on board capacitance can
be used to trim the crystal load and thus center the oscillator frequency. There are two capacitor arrays
(course and fine tune) that are controlled by the XTAL1_TRIM field. See Section 3.5.3, “32 MHz Crystal
Trimming”.
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System Management and Control
0x180D
SOMC2
7
6
5
4
3
2
1
0
R
W
XTAL1_TRIM
PoR Exit:
Other Reset:
0
u
0
u
0
u
0
1
u
1
u
1
u
1
u
u
= Unimplemented or Reserved
Figure 5-17. System Oscillator Management and Control Register 2 (SOMC2)
This register controls the trim value for the 32 MHz osc.
Field
Description
Crystal Oscillator 1 Capacitor Trim: Warps the crystal frequency:
[7:0]
XTAL_TRIM[7:0] • XTAL_TRIM[7:4] is the coarse tune field
• XTAL_TRIM[3:0] is the fine tune field
5.8.12 System Clock Gating Control 1 Register (SCGC1)
This register contains control bits to enable or disable the bus clock to the TPMx, CMT, IIC, and SCI
modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s run and wait currents.
SCGC1
0x180E
7
6
5
4
3
2
1
0
R
W
1
TPM4
1
TPM3
TPM2
TPM1
CMT
IIC
SCI
Reset:
1
1
1
1
1
1
1
Figure 5-18. System Clock Gating Control 1 Register (SCGC1)
Table 5-22. SCGC1 Register Field Descriptions
Description
Field
6
TPM4 Clock Gate Control — This bit controls the clock gate to the TPM4 module.
0 Bus clock to the TPM4 module is disabled.
TPM4
1 Bus clock to the TPM4 module is enabled.
5
TPM3 Clock Gate Control — This bit controls the clock gate to the TPM3 module.
0 Bus clock to the TPM3 module is disabled.
TPM3
1 Bus clock to the TPM3 module is enabled.
4
TPM2 Clock Gate Control — This bit controls the clock gate to the TPM2 module.
0 Bus clock to the TPM2 module is disabled.
TPM2
1 Bus clock to the TPM2 module is enabled.
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System Management and Control
Table 5-22. SCGC1 Register Field Descriptions (continued)
Field
Description
3
TPM1 Clock Gate Control — This bit controls the clock gate to the TPM1 module.
0 Bus clock to the TPM1 module is disabled.
TPM1
1 Bus clock to the TPM1 module is enabled.
2
CMT
CMT Clock Gate Control — This bit controls the clock gate to the CMT module.
0 Bus clock to the CMT module is disabled.
1 Bus clock to the CMT module is enabled.
1
IIC
IIC Clock Gate Control — This bit controls the clock gate to the IIC module.
0 Bus clock to the IIC module is disabled.
1 Bus clock to the IIC module is enabled.
0
SCI
SCI Clock Gate Control — This bit controls the clock gate to the SCI module.
0 Bus clock to the SCI module is disabled.
1 Bus clock to the SCI module is enabled.
5.8.13 System Clock Gating Control 2 Register (SCGC2)
This high page register contains control bits to enable or disable the bus clock to the Debug, Flash, IRQ,
KBIx, RTC and SPI modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s run
and wait currents.
SCGC2
0x180F
7
6
5
4
3
2
1
0
R
W
DBG
1
FLS
IRQ
KBI1
KBI2
RTC
SPI
Reset:
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 5-19. System Clock Gating Control 2 Register (SCGC2)
Table 5-23. SCGC2 Register Field Descriptions
Description
Field
6
DBG
Debug Clock Gate Control — This bit controls the bus clock gate to the Debug module.
0 Bus clock to the Debug module is disabled.
1 Bus clock to the Debug module is enabled.
5
FLS
Flash Clock Gate Control — This bit controls the bus clock gate to the Flash Interface (FTSR) module.
0 Bus clock to the Flash interface module is disabled.
1 Bus clock to the Flash interface module is enabled.
4
IRQ
IRQ Clock Gate Control — This bit controls the bus clock gate to the IRQ module.
0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
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System Management and Control
Table 5-23. SCGC2 Register Field Descriptions (continued)
Field
Description
3
KBI1
KBI1 Clock Gate Control — This bit controls the bus clock gate to the KBI1 module.
0 Bus clock to the KBI1 module is disabled.
1 Bus clock to the KBI1 module is enabled.
2
KBI2 Clock Gate Control — This bit controls the bus clock gate to the KBI2 module. Available only on the
KBI2
MC13234.
0 Bus clock to the KBI2 module is disabled.
1 Bus clock to the KBI2 module is enabled.
1
RTC
RTC Clock Gate Control — This bit controls the clock gate to the RTC module. Only the bus clock is gated, the
ICSERCLK and LPOCLK are still available to the RTC.
0 Bus clock to the RTC module is disabled.
1 Bus clock to the RTC module is enabled.
0
SPI
SPI Clock Gate Control — This bit controls the bus clock gate to the SPI module.
0 Bus clock to the SPI module is disabled.
1 Bus clock to the SPI module is enabled.
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MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
Chapter 6
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.1
Introduction
The MC13234/MC13237 provides a complete on board system solution for the IEEE 802.15.4 Standard
from the RF Physical Layer requirements through a complete MAC Layer implemented via dedicated
hardware as well as flash-based code. Key characteristics of the MC13234/MC13237 802.15.4
implementation include:
•
•
•
•
•
•
2.4 GHz ISM Band operation
Over-the-air data rate of 250 kbps
16 Standard independent channels
Programmable transmitter output power
Uses carrier sense multiple access with collision avoidance (CSMA-CA) protocol
Provides Energy Detection (ED), Clear Channel Assessment (CCA), and Link Quality Indication
(LQI) through MAC services
•
Dedicated hardware to off load 802.15.4 services from CPU
— PHY Layer sequence Manager
— Direct memory access (DMA) hardware to move data between transceiver and RAM
•
•
Hardware acceleration for AES security services of combined counter with CBC-MAC (cipher
block chaining message authentication code)
Special partial power down “listen” receive mode (PPD_RX) for lower current or to reduce
receiver sensitivity.
The MC13234/MC13237 transceiver implementation consists of the 2.4 GHz radio, modem functions,
sequence manager, and control registers. These elements combined with the flash-resident MAC services
running on the CPU provide the complete 802.15.4 MAC service. In addition, a dedicated timer block is
available to supplement the MCU TPM timer resources.
This chapter first provides an overview and general description for the radio and the modem. Following
the overview, the sequence manager, timer resources, and control functions are described. The descriptions
of control interface registers are then provided.
NOTE
Although this chapter is provided for use of the transceiver and knowledge
of the IEEE 802.15.4 Standard services, the user is directed to Freescale’s
stacks and codebases for complete MAC services.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-1
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.2
Features
Features of the MC13234/MC13237 transceiver and IEEE 802.15.4 services implementation include:
•
•
•
Receive sensitivity of -94 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE
802.15.4 Standard of -85 dBm
Programmable output power with 0 dBm nominal output power, programmable from –30 dBm to
+2 dBm typical
Small RF footprint
— Integrated transmit/receive switch
— Differential input/output port used with balun
— Low external component count
•
•
DMA interface to move packet data between transceiver and RAM
Separate hardware AES-128 Security module; see Chapter 7, “Advanced Security Module
(ASM)”
•
•
16-Bit random number generator
802.15.4 Auto-sequence support
— Automated sequence management requires no software intervention
— Standard packet sequences (transmission, reception, CCA services)
— Software or timer-initiated sequences
— Supports both 2003 and 2006 versions of IEEE 802.15.4 Standard
— Supports slotted and unslotted modes
— Supports beacon-enabled and non-beacon-enabled networks
802.15.4 Receiver frame filtering.
•
•
Four additional 24-bit transceiver timer comparators available for MAC operations
6.3
Transceiver Overview
The MC13234/MC13237 transceiver is capable of complete standalone operation. After it has been
programmed through the transceiver control registers, the sequence manager has the highest level control
to the radio and modem, and the DMA passes packet data to/from the RAM during a transmit or receive
operation. The CPU is released to do other parallel tasks, and this also eliminates any timing dependency
required to move data between the transceiver and memory. Also, the DMA works on a cycle-steal basis
from the CPU bus, and data are transferred on a byte-by-byte, as-required basis.
6.3.1
Transceiver Block Diagram
Figure 6-1 shows a simplified block diagram of the MC13234/MC13237 IEEE 802.15.4 transceiver. As
the diagram shows, the transceiver is loosely divided between the analog (radio) and digital functions.
•
The radio contains all the analog circuitry used to transmit and receive an RF signal.
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Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
— On transmission, the radio is provided the encoded serial data stream from header and symbol
generator blocks (transmit modem function), uses it to phase-shift modulate the carrier signal
from the synthesizer, and then drives the programmable power amplifier (PA)
— On reception, the radio transfers the RF signal through the transmit/receive switch (T/R SW),
amplifies it through the low noise amplifier (LNA), down converts and produces “I” and “Q”
channels through a 2-stage mixer chain, and then samples the resulting I and Q signals through
high-speed analog-to-digital (ADC) converters.
•
•
The main VCO and synthesizer block provides the proper RF LO1 frequencies required by the
radio to carry the modulated transmit signal while supporting the receiver's front end and signal
down conversion path.
The “802.15.4 Module” includes all the control/status logic, modem logic, and Event Timer –
Within the digital modem logic, the transmit and receive paths are separate and are controlled by
the control register logic block. Also, with the sequence manager and DMA functions to supervise
the actual radio operation and packet transfers, the transceiver is capable of standalone operation
allowing the CPU to run independent application code.
MIXERS & I/Q
GENERATOR
PMA &
DECIMATION
FILTER
DIGITAL
MIXER
MATCH
FILTER
FILTERING (I)
PMA
I
MIXERS & I/Q
GENERATOR
ADC
RF_BIAS
DEMOD,
CCA,
&
PACKET
PROCESSOR
RF_P
RF_N
T/R
SW
DIGITAL
LO
LNA
PMA &
FILTERING (Q)
PMA
ADC
Q
DECIMATION
FILTER
DIGITAL
MIXER
MATCH
FILTER
CLOCK
GEN
TIMER
MODULE
SEQUENCE
MANAGER
PRESCALER
MAIN VCO
&
SYNTHESIZER
32 MHz
REF
OSC
CONTROL
REGISTERS
&
BUS
INTERFACE
SYMBOL
GENERATOR
PHASE
SHIFT
MODULATOR
M
U
X
MCU
BUS
PA
FCS & HEADER
GENERATOR
VOLTAGE REG’S
&
RADIO / ANALOG
DIGITAL
CONTROL
Figure 6-1. MC13234/MC13237 IEEE 802.15.4 Transceiver Block Diagram
6.3.2
Direct Memory Access (DMA) Controller
A simple cycle-stealing DMA controller moves packet data between the transceiver and memory during a
transmit or receive operation. This off-loads the data transfer task from the CPU and improves
performance. The DMA operates as follows:
•
During a receive operation –
— The DMA receive address pointer is loaded from the RXD_ADR_PNTR[[23:0] field, see
Section 6.13.2, “Receive Data Pointer Registers (RXD_ADR_PNTR0 and
RXD_ADR_PNTR1)”.
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6-3
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
— As the data are received, they are directly placed into RAM buffer starting at the pointer
address. The received FCS data is included in the data transferred to the RAM buffer. The
receiver will transfer the data as one byte (octet) at a time (every 32 uS) into RAM. When a
new byte is received the destination address will increment accordingly.
– The first element of the received packet to be placed in the buffer will be the Frame Length
field.
– The last element will the Frame Check Sequence.
– The length field defines the number of bytes in the MPDU. Per definition the MPDU does
not include the length field count itself but includes the Frame Check Sequence (FCS). Thus
the user must allocate a buffer 1 byte larger than the expected MPDU length.
— As the receive buffer is loaded, the byte count is shown in the Receiver Byte Count Register,
see Section 6.13.10, “Receiver Byte Count (RX_BYTE_COUNT)”. The receive byte counter
can be used to generate an interrupt request as the frame is received. When the byte count
matches a preset level or “watermark”, see Section 6.13.9, “Receiver Byte Count Watermark
Threshold (RX_WTR_MARK)”, a status is set and can be enabled to generate the IRQ.
•
During transmit operations -
— The transmit packet must have been pre-assembled and available in the memory buffer.
— The data is automatically retrieved from the memory buffer starting from the address specified
by the TXD_ADR_ PNTR[[23:0] field, see Section 6.13.1, “Transmit Data Pointer Registers
(TXD_ADR_PNTR0 and TXD_ADR_PNTR1)”.
— The first byte retrieved is the FLI (see Section 6.4.1, “PHY Protocol Data Unit (PPDU)”) and
the DMA controller uses this value to determine how many bytes to fetch for the complete
packet
— The memory buffer does not include the two FCS (see Section 6.4.1, “PHY Protocol Data Unit
(PPDU)”) bytes, as these are calculated by the hardware generator and appended to the payload
data sourced from memory.
6.4
IEEE 802.15.4 Standard PHY Packet and Frame Structures
A basic knowledge of the PHY packet and frame structure is important to best understand basic operation
of the transceiver and sequence manager.
The MC13234/MC13237 transceiver supports the IEEE 802.15.4 2450 MHz Physical Layer (PHY)
specification. This standard uses serial 250 kbps offset quadrature phase-shift keying (O-QPSK) data in
5.0 MHz channels and full spread-spectrum encode and decode. It operates on one of 16 selectable
channels in the 2.4 GHz ISM band. The data are transmitted least significant symbol first within a byte
(octet), and least significant byte first within a data field.
NOTE
The following descriptions only provide an overview of the IEEE 802.15.4
PHY protocol data unit and frame structures. For more information see the
IEEE 802.15.4 Standard, “Part 15.4: Wireless Medium Access Control
(MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless
Personal Area Networks (WPANs)”, IEEE Std 802.15.4™-2006
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6-4
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.4.1
PHY Protocol Data Unit (PPDU)
The basic unit of the PHY transmission is the PHY protocol data unit (PPDU), see Figure 6-2. Each PPDU
consists of three basic components:
•
A synchronization header (SHR), which allows a receiving device to synchronize and lock onto the
bit stream. The SHR is composed of -
— Preamble – is a minimum of 4 bytes in length and allows the receiver to synchronize to the
incoming packet
— Start Frame Delimiter (SFD) – is a 1-byte field with a unique bit pattern that indicates start of
packet data
•
•
A PHY header (PHR), which contains frame length information; it is a 1-byte field composed of -
— 7-bit Frame Length Field (FLI) – specifies total number of following bytes of the payload data
(127 bytes maximum)
— 1-bit Reserved Field
PHY Payload – is a variable length field which carries the MAC sublayer frame. Designated as the
PHY Service Data Unit (PSDU) -
— Maximum length is127 bytes
— Last two bytes are always Frame Check Sequence (FCS) data
— Total length (FLI) is actual payload data plus FCS data
Figure 6-2 shows two views of the packet / PPDU structure. The first view reflects the PPDU field
definitions, and the second view is a simplified view emphasizing field byte lengths.
Octets (bytes)
1
Variable
PSDU
Frame Length
(7 bits)
Reserved
(1 bit)
Preamble
SFD
SHR
PHR
PHY payload
4 bytes
1 byte
SFD
1 byte
FLI
125 bytes max
Payload data
2 bytes
FCS
Preamble
PSDU
Figure 6-2. IEEE 802.15.4 PPDU / Basic Packet Structure
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Freescale Semiconductor
6-5
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.4.2
MAC Frame Structures
Understanding the MAC frame structures is useful to understanding operation of the Sequence Manager.
In the MAC frame structure, The MAC Protocol Data Unit (MPDU) which originates from the MAC
sublayer and makes up the PSDU of the PPDU is the MAC sublayer frame. Maximum length is 127 bytes.
The MPDU can consist of three fields -
•
MAC header (MHR) – is always present and can contain
— MAC Frame Control field – 2 bytes in length and contains information defining the frame type,
addressing fields, and other control flags. Required field.
— Sequence Number field – 1 byte in length and specifies the sequence identifier for the frame
(either a beacon sequence number (BSN) or a data sequence number (DSN). Optional field as
required by frame type.
— Addressing Fields – Destination PAN Identifier (0/2 bytes), Destination Address (0/2/8 bytes),
Source Address (0/2/8). Use as required by frame type.
— Auxiliary Security Header – (0/5/6/10/14 bytes). Optional field as required by security use.
•
•
Mac Payload – Variable length. Specific information to the frame. Optional field as required by
frame type.
MAC footer (MFR) – Frame check sequence (FCS) field (2 bytes). Required field.
Table 6-1 shows the general MAC frame format.
Table 6-1. General MAC Frame Format
Octets:2
1
0/2
0/2
0/2/8
0/2
0/5/6/10/14
Variable
Frame
2
Frame
Control
Sequence Destination Destination Source
Number
Source
Address
Auxiliary
Security
Header
FCS
MFR
PAN
Address
PAN
Identifier
Payload
Identifier
Addressing Fields
MHR
MAC
Payload
The IEEE 802.15.4 Standard defines four frame structures as described in Table 6-2.
NOTE
Table 6-2 shows only the PSDU field contents. The complete PPDU or PHY
packet also contains the Preamble, SFD, and FLI fields.
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Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-2. MAC Frame Format
Field
Description
Beacon Frame
The Beacon Frame is used by a coordinator to transmit beacons. A coordinator can transmit network
beacons in a beacon-enabled PAN. The frame contains:
• The MHR – contains the MAC Frame Control field, beacon sequence number (BSN), addressing
fields, and optionally the auxiliary security header.
• The MAC payload – contains the superframe specification, GTS fields, pending address fields, and
beacon payload.
• The MFR – contains a 16-bit frame check sequence (FCS).
Data Frame
The Data Frame is used for all transfers of data and originates from the upper layers. The data payload
is passed to the MAC sublayer and becomes the MPDU. The frame contains:
• The MHR – contains the MAC Frame Control field, data sequence number (DSN), addressing fields,
and optionally the auxiliary security header.
• The MAC payload – upper layer data payload
• The MFR – contains a 16-bit frame check sequence (FCS).
Acknowledgment The Acknowledgment Frame originates within the MAC sublayer and is used for confirming successful
Frame
frame reception. Having no MAC payload, the frame contains:
• The MHR – contains the MAC Frame Control field and data sequence number (DSN)
• The MFR – contains a 16-bit frame check sequence (FCS).
MAC Command
Frame
The MAC Command Frame originates within the MAC sublayer and is used for handling all MAC peer
entity control transfers. The frame contains:
• The MHR – contains the MAC Frame Control field, data sequence number (DSN), addressing fields,
and optionally the auxiliary security header.
• The MAC payload – MAC command payload.
• The MFR – contains a 16-bit frame check sequence (FCS).
6.5
Basic PHY Operations
Using a simplistic approach, all 802.15.4 PHY transactions are built around three basic 802.15.4 PHY
operations:
•
Clear Channel Assessment (CCA) / Energy Detect (ED) – testing for energy on the selected
channel:
— CCA cycle – Looking for an idle channel condition as part of the collision avoidance protocol,
before executing a transmission.
– For a CCA Mode 1 operation – the channel energy is compared to a preset threshold
– For a CCA Mode 2 operation – if a 802.15.4 modulated signal is found, the channel is
considered busy
— Observing individual channel energy (ED) as part of a channel scan for the MAC services
— Measuring energy of a received packet to report LQI
•
•
Packet transmission (TX) – transmitting or sending a PHY protocol data unit using one of the frame
structures previously defined
Packet reception (RX) – receiving a PHY protocol data unit.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-7
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.5.1
Clear Channel Assessment (CCA) Operation (including ED and Link
Quality Indication)
A CCA operation is a broad designation for any form of measuring channel energy. The measurement is
done using the receiver and uses different algorithms or modes.
6.5.1.1
CCA Modes, Energy Detect, and Link Quality Detect Algorithms
The Clear Channel Assessment (CCA) mode and energy detect algorithms described here are consistent
with the IEEE 802.15.4 Standard definitions.
6.5.1.1.1
CCA Mode 1 Algorithm
The CCA Mode 1 algorithm measures an average energy in any received baseband signal (on the pro-
grammed channel). For a Mode 1 operation, the receiver moves from an IDLE condition to a RECEIVE
condition (designated as a 144 µs RX Warm-up) and then does an RSSI measurement for 128 µs (as
defined by the 802.15.4 standard and equals 8 symbol times). Figure 6-3 shows the operation timing.
144 µs
128 µs
CCA
(Averaging)
RX Warm-up
Time
Figure 6-3. CCA Sequence Timing
For CCA Mode 1, the RSSI measurement is done by calculating a 128µs (8 symbol) average of:
I 2 Q2
CCA Mode 1 is used to report an “energy above threshold” status for a CCA cycle. The threshold level is
provided by the CCA_THRESHOLD Register, and if the detected energy is above the threshold the CCA
status is set to “Busy”
6.5.1.1.2
CCA Mode 2 Algorithm
The CCA Mode 2 algorithm looks for the presence of an 802.15.4 compliant received signal (on the pro-
grammed channel) and signal strength is unimportant. For a Mode 2 operation, the receiver first executes
a 144 µs RX Warm-up, similar to Mode 1. However, Mode 2 differs in that the preamble detect function
is activated for the 128 µs, 8 symbol time period, and looks for correlation of an 802.15.4 signal.
CCA Mode 2 can be used to report a “carrier sense” status for a CCA cycle. The CCA status will be set to
“Busy” is a carrier is detected.
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Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.5.1.1.3
Energy Detect (ED) Algorithm
The energy detect algorithm also measures an average energy in any received baseband signal (on the
programmed channel). The difference from the Mode 1 algorithm is that a 64 µs AGC settling time is
inserted between the RX Warm-up cycle and the 128 µs signal strength measurement. Figure 6-4 shows
the operation timing.
144 µs
64 µs
128 µs
Signal Strength
Measurement
(Averaging)
AGC
Settling
RX Warm-up
Time
Figure 6-4. ED Sequence Timing
ED mode is typically used to report a status for channel scan.
6.5.1.1.4
Link Quality Indication (LQI) Algorithm
LQI is a measurement of average energy of the received baseband signal during a packet reception. The
energy measurement is similar to the ED measurement except that the sample time is delayed until the
packet preamble detect. Figure 6-5 shows the operation timing.
Preamble
Detect
144 µs
128 µs
Signal Strength
Measurement
(Averaging)
RX Warm-up
Time
Figure 6-5. LQI Measurement Timing
The LQI value is reported with the receive packet.
6.5.1.2 CCA-Associated Control Register Fields
The execution of CCA/energy measurement functions is controlled by the Sequence Manager, and their
use and status related to a given sequence is associated with the following registers and register fields:
•
CNTRL1 Register – see Section 6.13.3, “Transceiver Control Register 1 (CNTRL1)”
— CCABFRTX Bit : this bit enables/disables a CCA operation before a transmit in a Transmit or
a Transmit/Receive sequence.
•
•
CNTRL2 Register – see Section 6.13.4, “Transceiver Control Register 2 (CNTRL2)”
— CCATYPE[1:0] : this 2-bit field selects the CCA algorithm used during a sequence (if enabled)
CNTRL3 Register – see Section 6.13.5, “Transceiver Control Register 3 (CNTRL3)”
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
— CCAMSK : this enables/disables an interrupt request due to a “CCAIRQ” status
•
•
•
STATUS1 Register – see Section 6.13.11, “Status Register 1 (STATUS1)”
— CCA : this bit reports the result of a CCA/ED operation
STATUS2 Register – see Section 6.13.12, “Status Register 2 (STATUS2)”
— CCAIRQ : this bit reports completion of an CCA/ED operation
CCAFNL Register – see Section 6.13.3, “Transceiver Control Register 1 (CNTRL1)”
— CCAFNL[7:0] : this 7-bit field is the reported value of the energy measurement from a CCA,
ED, or LQI operation
•
•
CCA_THRESHOLD Register – see Section 6.13.30, “CCA Energy Threshold
(CCA_THRESHOLD)”
— CCA_THRESHOLD[7:0] : this 7-bit field is the energy threshold value used during a CCA
cycle to compare for a clear channel
CCA_OFFSET_CMP Register – see Section 6.13.31, “CCA Power Compensation
(CCA_OFFSET_CMP)”
— CCA_OFFSET_CMP[7:0] : this 7-bit field is an offset correction value that is added to trim the
measured energy level
6.5.1.3
Reported Energy Values
The average value of the signal power is calculated and stored in field CCA_FINAL[7:0] for a CCA, ED,
or LQI indication. The reported 8-bit binary value is an indication of the signal strength in dBm. However,
to determine the decimal equivalent of the value stored in CCA_FINAL[7:0], one must convert the hex
value to its decimal value, divide by two, and change the sign; where this calculated value is equivalent to
the received signal strength in dBm:
Signal strength in dBm = – (dec (CCA_FINAL[7:0] / 2))
The value stored in CCA_FINAL[7:0] is also affected by an offset stored in field
CCA_OFFSET_CMP[7:0]. The default value of CCA_OFFSET_CMP[7:0] = 0x8D and is added to the
measured value during the CCA/ED/LQI function to give the stored value in CCA_FINAL[7:0].
The compensation number added to the internal measured value is CCA_OFFSET_CMP[7:0] / 2 and the
resulting addition is shown in Figure 6-6.
internal[8:0]
{cca_final[7:0],0}
Binary
Adder
{0,CCA_OFFSET_CMP[7:0]}
Figure 6-6. Compensation Factor Added to Internal CCA Value to Produce Corrected Final Value
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
The resulting formula for dBm means that the CCA_OFFSET_CMP[7:0] value must increment or
decrement by 4 to cause a 1 dBm change, which equates to a 1/4 dBm resolution for the
CCA_OFFSET_CMP correction.
The CCA_OFFSET_CMP[7:0] default value is 0x8D and the value must increment to set a lower final
CCA value. As an example, if one were putting in a -30 dBm signal and the CCA_FINAL[7:0] was
reporting -26 dBm, then the correction value in power_comp[7:0] should be increased by (4 * delta) or (4
* 4) in this case. The new compensated value of power_comp[7:0] = 0x8D + 0x10 = 0x9D.
NOTE
As previously stated, the default value for power_comp[7:0] = 0x8D. For
the MC13234/MC13237 device, an offset of 3.5 dBm is needed to center the
reported CCA/LQI value over temperature. As a result, it is suggested that
a value of 0x9B be programmed into CCA_OFFSET_CMP[7:0] for best
accuracy.
Because the AGC is set to a fixed gain during the CCA procedure, input signals above -65 dBm will not
be reflected correctly due to saturation. This is not a problem because the purpose of this measurement is
to detect a signal above a threshold that is not to exceed -75 dBm. See the 802.15.4 Standard for details.
-50
-60
-70
-80
802.15.4 Accuracy
and range Requirements
-90
-100
-90
-80
-70
-60
-50
Input Pow er (dBm)
Figure 6-7. CCA Reported Power Level vs. Input Power
6.5.1.3.1
CCA Result
For a CCA operation, the value contained in CCA_FINAL[7:0] is compared to the preset threshold of field
CCA_THRESHOLD[7:0]. If CCA_FINAL[7:0] is equal to or less than the threshold, then status CCA is
set to 1, indicating a busy channel. If CCA_FINAL[7:0] is greater than the threshold, CCA remains at 0.
After the CCA operation is complete, CCAIRQ is asserted.
The value of CCA_THRESHOLD[7:0] is calculated:
Threshold value = hex (| (Threshold Power in dBm) * 2 |)
A suggested threshold is -82 dBm or 0xA4 = CCA_THRESHOLD[7:0].
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.5.1.3.2
Energy Detect Function
With the energy detect algorithm, the same energy results are reported, but the operation is done without
the threshold comparison.
NOTE
For the following graph, the required 802.15.4 Standard accuracy and range
limits are shown. A 3.5 dBm offset has been programmed into the ED/LQI
reporting level to center the level over temperature in the graph.
-15
-25
-35
-45
-55
-65
802.15.4 Accuracy
and Range Requirements
-75
-85
-85
-75
-65
-55
-45
-35
-25
-15
Input Power Level (dBm)
Figure 6-8. ED and LQI Reported Power vs. Input Power
Status bit CCA is unaffected by energy detect. After the energy detect operation is complete, CCAIRQ is
asserted.
6.5.1.3.3
Link Quality Indication
Link Quality Indication is a measure of the signal quality during an actual receive operation. Its value is
also stored in field CCA_FINAL[7:0].
NOTE
In Figure 6-8, the required 802.15.4 Standard accuracy and range limits are
shown. A 3.5 dBm offset has been programmed into the LQI reporting level
to center the level over temperature. Typical values of LQI returned from an
RX operation are from about -95 dBm to about -18 dBm giving a
CCA_FINAL[7:0] range of decimal values 190 (0xBE) to 36 (0x24). When
used in an 802.15.4 application, the LQI must be scaled and limited to have
a range of decimal 0 to 255. Values of LQI above approximately -30 to -25
dBm can be non-linear and should not be used as an indication of absolute
received power.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.5.2
Packet Transmission (TX)
A packet transmission sends a PHY packet as shown in Figure 6-2. The packet consists of (in order) the
preamble, SFD, FLI, payload data, and last, the FCS. In the transceiver, the transmit operation is automated
through use of the DMA and the Sequence Manager:
•
•
•
•
•
The DMA pointer must be preloaded
The data buffer must be preloaded in RAM (includes the FLI and payload data, not including FCS)
The Sequence Manager options/controls must be initiated.
The transmit may or may not be preceded by a CCA operation
Transmit results as the execution of a Sequence T or Sequence T/R operation
For either transmit sequence, a very simple overview consists of (for more detail, see Section 6.9.5, “Basic
Transmit Sequence – Sequence T (Transmit)”):
1. Transmitter warm-up
2. Preamble transmitted (4 octets from hardware)
3. SFD transmitted (octet from hardware)
4. FrameLength octet transmitted -fetched from from RAM
5. Payload data transmitted – fetched from RAM on byte-by-byte basis as determined by FLI
6. FCS transmitted (2 octets generated in hardware)
7. Transmitter warm-down
6.5.3
Packet Reception (RX)
Packet reception is more complex and includes hardware filtering for accepting/rejecting packets.
6.5.3.1
Basic RX Operation
Packet reception is enabled either as a simple receive sequence or as part of a longer sequence.
•
•
•
•
The receive DMA pointer must be preloaded
The data buffer area in RAM should be reserved.
The filtering options must be preset
The Sequence Manager options/controls must be initiated.
For a simple receive sequence, an overview for a successful receive consists of :
1. Receiver warm-up
2. Receiver enters receive mode and waits for signal
3. Preamble detected
4. SFD detected
5. FrameLength octet received – saved to check byte count as well as saved to RAM
6. Payload data received and transferred to RAM on byte-by-byte basis as determined by FLI
(includes received CRC bytes)
7. Frame filtering checked as received and CRC checked
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
8. Frame ready for examination.
6.5.3.2
Receive Operating Modes
The MC13234/MC13237 is unique in that it supports two operational receive modes:
•
•
Standard receive (RX) mode – the default receive mode sets the receiver to maximum sensitivity
and operates in a “normal” mode. The receiver is fully on and stays active until a frame is received
or a time-out occurs (if enabled).
Partial Power Down receive (PPD_RX) – this mode can be enabled as an option.
— Whenever a receive cycle is initiated, the receiver is not fully on to save current until energy of
a preset level is detected.
— The receiver turns on fully upon being triggered by energy at the preset level, and then receives
the expected frame. The full-on state is the same as the standard receive state.
Use of the PPD_RX mode can provide two distinct advantages:
1. Reduced “listen” mode current – the receive current is significantly reduced while waiting for a
frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its
RF-active time waiting for incoming frames from clients or other devices, the net power savings
can be significant. There is a cost of reduced sensitivity.
2. Reduced sensitivity as a desired effect – the PPD_RX mode can provide different levels of reduced
sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the
receiver such that the device does not respond to incoming frames with an energy level below the
desired threshold. This could be useful for security, net efficiency, reduced noise triggering, as well
as other purposes.
NOTE
Freescale Codebases provide function calls for enabling, disabling and
configuring the PPD_RX mode.
6.5.3.3
Receive Packet Filtering and Responses
The MC13234/MC13237 transceiver hardware has the ability to accept/reject a received frame and enable
“auto” sequence features based on the frame attributes.
As briefly described in Section 6.4.2, “MAC Frame Structures”, each data packet contains a MAC header
that can contain a MAC Frame Control Field (2 bytes), Sequence Number Field (1 byte), Address Fields
(variable length), and an auxiliary security header (variable). Table 6-1 shows this structure. To further
describe the filtering features, the Frame Control Field (FCF) format is shown in Table 6-3. The
transceiver filtering and response mechanisms are gated by these FCF sub-fields and the Addressing
Fields.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-3. Frame Control Field Format
9-7
Bits:
15-14
13-12
Frame
11-10
6
5
4
3
2-0
Source
Addressing Version
Mode
Destination Reserved
Addressing
PAN ID
Compression Request
Ack
Frame
Pending
Security
Enabled
Frame
Type
Mode
When receiving a packet, the following capabilities are possible:
1. Promiscuous Mode – this mode will receive ALL frames with no filtering except for Frame Length
checking and optional CRC checking.
— Mode is enabled by PROMISCUOUS bit, CNTRL2 Register – see Section 6.13.4,
“Transceiver Control Register 2 (CNTRL2)”
— CRC is disabled by CRC_MSK bit, CNTRL3 Register – see Section 6.13.5, “Transceiver
Control Register 3 (CNTRL3)”
2. Hardware generated Ack response – for the Receive and Transmit/Receive sequences, this feature
will follow a received frame that passes required filtering and that requests an Ack (FCF “Ack
Request” sub-field = 1) with a transmitted Ack frame. The Ack frame uses the Sequence Number
from the received frame. Promiscuous mode disables this feature.
3. Programmable frame filtering – based on FCF sub-fields, Sequence Number field, and Addressing
Fields.
— Pan Coordinator enable – the PANCORDNTR bit of CNTRL2 enables the device as Pan
Coordinator. This enables reception of MAC command or data frames with no destination
address
— Frame Type FCF sub-field – as defined in Table 6-4, the frame type is used to help determine
the filter characteristics. See paragraphs below.
— RX_FRAME_FILTER Register control bits (see Section 6.13.28, “Receive Frame Filter
(RX_FRAME_FILTER)”- as summarized in Table 6-5 set the accept/reject criteria, See
paragraphs below.
4. IEEE 802.15.4 Standard Version control
Table 6-4. IEEE 802.15.4 Frame Type Subfield
Frame Type [2:0]
Frame Type Designation
Beacon
000
001
Data
010
Acknowledgement
MAC command
Reserved
011
100-111
Frame filtering uses the 3-bit Frame Type subfield (Table 6-4) value within the receive frame 2-byte FCF
to determine rejection of the incoming receive frame. Control bits in the RX_FRAME_FILTER Register
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
set the accept/reject options as shown in Table 6-5. The frame type is further qualified by the address
field(s).
Table 6-5. Frame Filter Control Bits
Control
Bit
Frame Type
(FT[2:0])
Filter Option Description
NS_FT
Not Specified (100-111) When set to 1, non-specified frames are accepted
CMD_FT
Command (011)
Ack (010)
When set to 1, Command frames are accepted
When set to 1, Ack frames are accepted
When set to 1, Data frames are accepted
When set to 1, Beacon frames are accepted
ACK_FT
DATA_FT
BEACON_FT
Data (001)
Beacon (000)
The receive operation will complete only if the following conditions are met:
1. Destination address:
a) If PAN ID is included other than the broadcast, it must match the MACPANID[15:0] field (see
Section 6.13.19, “MAC Pan ID Registers (MACPANID0 and MACPANID1)”) else the PAN
ID must be the broadcast value (0xFFFF)
b) If a short destination address is included in the frame, it must match the
MACSHORTADDRESS[15:0] field (see Section 6.13.18, “MAC Short Address Registers
(MACSHORTADDRS0 and MACSHORTADDRS1)”) else the broadcast address (0xFFFF)
c) If a long destination address is include in the frame, it must match the
MACSLONGADDRESS[63:0] field (see Section 6.13.26, “MAC Long Address Registers
(MACLONGADDRS0 – MACLONGADDRS7)”)
d) If only source addressing fields are included in a Data or MAC Command frame, the frame
shall be accepted only if the device is enabled as a PAN coordinator (PANCOORD = 1) and the
source PAN identifier matches MACPANID[15:0].
2. Illegal Frame types are rejected, unless the NS_FT bit is set.
3. Beacon frames are accepted under the following conditions
a) Beacon frames enabled; the BEACON_FT bit is set.
b) The source PAN ID matches MACPANID[15:0] or it equals 0xFFFF
c) Length >= 9
d) The Destination Addressing Mode sub-field is 0 (no destination address)
e) The Source Addressing Mode sub-field is 2 or 3 (i.e. a source address is included)
4. Data frames are accepted under the following conditions:
a) Data frames are enabled; the DATA_FT bit is set.
b) Length >= 9
c) If the device is a PAN coordinator (PANCOORD bit) and the source PAN identifier matches
MACPANID[15:0]. This means that if the destination address is not present, the frame will be
accepted only if the PANCOORD = 1 and the PANID in the source address field is equal to the
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
receiving device MACPANID[15:0]. If the device is NOT a PAN coordinator, the Destination
Address Mode must be 2 or 3, and destination address-matching rules apply.
5. Acknowledgement Frames are accepted under the following conditions:
a) Acknowledge Frames are enabled; the ACK_FT bit is set.
b) Length == 5
c) Sequence Number has to match the previously sent TX frame from this device.
6. Command Frames are accepted under the following conditions:
a) Command Frames are enabled; the CMD_FT bit is set.
b) Length >= 9
c) Source or Destination Address are included, else it must be a coordinator (PANCOORD = 1)
in which case the PANID must equal MACPANID[15:0]. If the device is NOT a PAN
coordinator, the Destination Addressing Mode must be 2 or 3, and destination
address-matching rules apply.
If a frame is rejected, the transceiver will stay enabled as a receiver, and start searching for a new frame
after the rejected frame has been received.
6.6
VCO Frequency Synthesizer (Channel Frequency)
The VCO frequency synthesizer uses a Fractional-N (Frac-N) PLL divider chain. The MC13237 operates
in the 2.4 GHz ISM band, covering 16 channels and uses 5 MHz of spacing between each channel. The
synthesizer VCO output frequency is referenced as LO1 and must be programmed to the channel
frequency. The Frac-N has fractional and integer components that must be programmed properly to
perform a transceiver operation on a particular channel.
•
•
The integer setting is LO1_INT[7:0], Register LO1_INT
The fractional setting is LO1_FRAC[15:0] Registers LO1_FRAC0 – LO1_FRAC1
Table 6-6 lists LO1_INT and LO1_FRAC settings for the sixteen standard 802.15.4 Channels.
Table 6-6. 802.15.4 Channel LO1 Settings
802.15.4
Channel
Number
Integer Setting
LO1_INT[7:0]
(Dec / Hex)
Fractional Setting
LO1_FRAC[15:0]
(Dec / Hex)
Frequency
(MHz)
([N+1].frac)dec
11
12
13
14
15
16
17
18
19
75.15625
75.31250
75.46875
75.62500
75.78125
75.93750
76.09375
76.25000
76.40625
74 / 0x4A (default)
74 / 0x4A
10241 / 0x2801 (default)
20481 / 0x5001
30721 / 0x7801
40961 / 0xA001
51201 / 0xC801
61441 / 0xF001
06145 / 0x1801
16385 / 0x4001
26625 / 0x6801
74 / 0x4A
74 / 0x4A
74 / 0x4A
74 / 0x4A
75 / 0x4B
75 / 0x4B
75 / 0x4B
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Freescale Semiconductor
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-6. 802.15.4 Channel LO1 Settings
802.15.4
Channel
Number
Integer Setting
LO1_INT[7:0]
(Dec / Hex)
Fractional Setting
LO1_FRAC[15:0]
(Dec / Hex)
Frequency
(MHz)
([N+1].frac)dec
20
21
22
23
24
25
26
76.56250
76.71875
76.87500
77.03125
77.18750
77.34375
77.50000
75 / 0x4B
75 / 0x4B
75 / 0x4B
76 / 0x4C
76 / 0x4C
76 / 0x4C
76 / 0x4C
36865 / 0x9001
47105 / 0xB801
57345 / 0xE001
02049 / 0x0801
12289 / 0x3001
22529 / 0x5801
32769 / 0x8001
6.7
Event Timer Block
The MC13237 transceiver contains an Event Timer block that provides programmable timer delays and is
also used in conjunction with the sequence manager. A simplified block diagram is shown in Figure 6-9.
EVENT_TMR[23:0]
TMR_PRESCALE[2:0]
Event Timer Counter
(24-bit)
16 MHz
Prescale
TIMESTAMP[23:0]
T1CMP[23:0]
=?
YES
YES
YES
T2CMP[23:0]
TC2_PRIME[15:0]
T3CMP[23:0]
M
U
X
=?
=?
CONTROL
REGISTERS
T4CMP[23:0]
=?
YES
Figure 6-9. Event Timer Block Diagram
The Event Timer consists of a prescaler and a 24-bit counter which increment whenever the reference
clock is operating. Interrupts to the MCU may be generated when the “current time” of the counter
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
(EVENT_TMR[23:0]) matches several timer comparator registers. The current time (counter value) is
accessible at any time and can also be over-programmed.
The Event Timer provides the following functions:
•
•
•
•
Timer to generate current system time
Interrupt generation at pre-determined system times or delays
Latches “timestamp” value during packet reception
Initiates timer-triggered sequences
6.7.1
Event Timer Time Base
The Event Timer’s base clock is derived from a programmable prescaler which is clocked at 16 MHz
derived from the 32 MHz reference source. The prescaler provides different counter input frequencies
from 500 kHz down to 15.625 kHz. The prescaler and the Event Timer only increment when the reference
oscillator is active. The field TMR_PRESCALE[2:0] in the MACFRAMEVER Register 9
(Section 6.13.29, “MAC Frame Version Compatibility and Timer Prescale Register (FMR_REV_TMR)”)
establishes the base clock frequency as shown in Table 6-7.
Table 6-7. Event Timer Prescaler Settings
MACFRAMEVER[7:5],
TMR_PRESCALE[2:0]
Event Timer
Base Clock
Maximum Event
Timer Duration
000
001
reserved
reserved
500 kHz
NA
NA
010
33.554 seconds
67.109 seconds
134.218 seconds
268.436 seconds
536.871 seconds
1073.742 seconds
011 (default)
100
250 kHz
125 kHz
101
62.5 kHz
31.25 kHz
15.625 kHz
110
111
The 24-bit counter automatically rolls over upon reaching its maximum value, and the corresponding
maximum possible Event Timer durations are also provided in Table 6-7.
6.7.2
Setting Current Time
“Current Time” is defined as the value of the Event Timer internal counter. The current time is
programmable, and is set to zero by a reset condition. Current time advances from zero at the selected
prescale clock rate and the counter rolls over to zero after reaching its maximum value.
To set current time, the T1CMP[23:0] Registers are used (see Section 6.13.20, “Event Timer Comparator
1 Registers (T1CMP0, T1CMP1, and T1CMP2)”. Programming “current time” is accomplished by:
1. Programming the desired 24-bit value value into the T1CMP[23:0] field
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
2. Writing a one to the TMRLOAD bit of the CNTRL1 Register (see Section 6.13.3, “Transceiver
Control Register 1 (CNTRL1)”. The TMRLOAD bit is self-clearing and always reads as zero.
6.7.3
Reading Current Time
The current value of the Event Timer can be read from the Event Timer [23:0] Registers (see
Section 6.13.14, “Event Timer Registers (EVENT_TMR0, EVENT_TMR1, and EVENT_TMR2)”.
Reading the EVENT_TMR2 Register (least significant byte) latches the “current time” in the 24-bit field.
This register should be read first, followed by reads of EVENT_TMR1 Register (next most significant),
and EVENT_TMR0 Register (most significant), in that order. The read of EVENT_TMR0 releases the
latched value.
6.7.4
Receive Packet Timestamp
The MC13234/MC13237 latches a “Timestamp” of current time whenever a packet is received and the
value is stored in the TIMESTAMP [23:0] Registers (see Section 6.13.15, “Time Stamp Registers
(TIMESTAMP0, TIMESTAMP1, and TIMESTAMP2)”. This timestamp value is latched at the beginning
of a receive packet after detect of the SFD. The timestamp remains latched until another packet is received,
at which point value is updated and re-latched.
6.7.5
Event Timer Comparators
The MC13237 incorporates four 24-bit programmable fields that compare to the Event Timer’s “current
time”. The intent of these compares is to enable the host to schedule events relative to the “current time”.
When a match between the “current time” and any one of the four timer compare values occurs (when
enabled), a corresponding status flag is set. An interrupt request can be generated from the valid status.
Table 6-8 lists the applicable registers and control bits for the comparators. A typical procedure for
programming a compare operation includes:
1. Disable comparator (TMRxCMP_EN = 0) if required – this is the default condition.
2. Read current time from Registers EVENT_TIMER0 – EVENT_TIMER2.
3. Add desired offset to current time to get “compare time”- the offset value will be determined by
the prescale rate and the desired time delay.
4. Load TxCMP0 – TxCMP2 registers with “compare time”
5. Enable interrupt request if required (TMRxIRQ = 0) – disabled is the default condition
6. Enable comparator and interrupt; set TMRxCMP_EN = 1.
7. Count reaches TxCMP value – status becomes valid and interrupt request asserted.
8. Comparator should be disabled as part of interrupt service routine.
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Table 6-8. Event Timer Comparator Registers
Mask
Bit
(CNTRL4
Reg)
Enable
Bit
(CNTRL4 Reg)
Status
Bit
Comp
Field
Registers
Comments
1
2
T1CMP[23:0]
T2CMP[23:0]
T1CMP0
T1CMP2
TMR1CMP_EN TMR1IRQ TMR1MSK Use to load new counter value.
UseTMRLOAD bit
T2CMP0
T2CMP2
TMR2CMP_EN TMR2IRQ TMR2MSK Basic 24-bit mode
TC2_PRIME[15:0] TC2_PRIME0 TMR2CMP_EN TMR2IRQ TMR2MSK Optional 16-bit mode. Use
TC2_PRIME1
TC2’EN
3
4
T3CMP[23:0]
T4CMP[23:0]
T3CMP0
T3CMP2
TMR3CMP_EN TMR3IRQ TMR3MSK Optional sequence abort function.
Use TC3TMOUT bit
T4CMP0
T4CMP2
TMR4CMP_EN TMR4IRQ TMR4MSK
There are additional special features for the comparators:
1. Timer Comparator 1 (T1CMP[23:0]) is also used to set the current time counter – the comparator
function should be disabled. After T1CMP[23:0] is written for the desired current time, writing a
one to the TMRLOAD bit of the CNTRL1 Register loads the counter with the new time.
2. Timer Comparator 2 / TC2_PRIME[15:0] Registers – the two TC2_PRIME registers hold a 16-bit
compare value used by Event Timer Comparator 2 for a special sequences. The TC2’EN control
bit in register CNTRL2 enables or disables the 16-bit versus the 24-bit mode for Comparator 2; this
bit must be a “1” to enable TC2_PRIME.
3. Timer Comparator 3 – T3CMP can be used as a “bracketing” timer, i.e., to abort certain sequences
after a software-determined time-out period. See Section 6.7.5.1, “Timer-Triggered Transceiver
Sequence Events”.
6.7.5.1
Timer-Triggered Transceiver Sequence Events
The event timer comparators T2CMP and T3CMP can optionally be used with the Sequence Manager:
1. TC2CMP can be used to initiate a sequence at a precise time – This operation is controlled by the
TMRTRIGEN control bit, see Section 6.9, “Supported Sequences”.
2. T3CMP can be used to abort transceiver sequences – This time-out mechanism is enabled by
setting the TC3TMOUT control bit in CNTRL2 register to 1. If TC3TMOUT = 0, then the abort
mechanism is disabled, and timer TC3 functions merely as a software timer. The T3CMP
hardware-abort functions are summarized in the Table 6-9.
Table 6-9. T3CMP Comparator Sequence Abort Function
SEQUENCE
TC3TMOUT=0
S/W timer
TC3TMOUT=1
I
S/W timer
R
T
C
S/W timer
S/W timer
S/W timer
Abort sequence
S/W timer
S/W timer
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-9. T3CMP Comparator Sequence Abort Function
SEQUENCE
TR
CCCA
TC3TMOUT=0
S/W timer
S/W timer
TC3TMOUT=1
Abort sequence, (during receive operation only)
Abort sequence
6.8
Sequence Manager
The Sequence Manager is a hardware state machine which controls the transceiver timing and
management for all transmit, receive, and CCA operations which minimizes the application memory
footprint, off loads the CPU, and allows operations not otherwise possible.
Sequences can be initiated by software directly, or can be initiated via a hardware timer. The sequence
parameters are programmed prior to initiating the sequences and include:
•
•
•
•
•
Whether CCA is required ahead of a transmit sequence
Whether an automatic Ack frame should be transmitted after a receive sequence
Slotted vs. unslotted mode
Type of CCA (e.g., Energy Detect, CCA Mode 1, or CCA Mode 2)
Whether the device is a PAN Coordinator or not
NOTE
The sequence manager supports some of the more complex features of the
IEEE 802.15.4 Standard including beacon-enabled communication and
guaranteed time slots. It is important that the user be familiar with these
concepts:
•
See Appendix A, “IEEE 802.15.4 PHY Messaging Overview” for a
brief overview of beacon-enabled communication.
•
For more in-depth information , reference the IEEE 802.15.4 Standard,
“Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer
(PHY) Specifications for Low-Rate Wireless Personal Area Networks
(WPANs)”, IEEE Std 802.15.4™-2006
6.8.1
Features
The sequence manager provides the following features:
•
•
•
•
•
•
•
•
Supports complex sequences
Unburdens software by automating many transceiver operations
New data-polling hardware enables critical-timing sequences
Includes new continuous CCA for low-latency-transmit applications
Includes capability to conditionally perform CCA prior to every transmit operation
Includes capability to conditionally transmit an Ack frame after every receive operation
Supports software- or timer-initiated sequences
Fully supports 2003 and 2006 versions of the 802.15.4 standard
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
•
•
•
•
Supports slotted and unslotted modes
Supports beacon-enabled and non-beacon-enabled networks
Supports orderly transceiver shutdown on PLL unlock event
Supports timer-based sequence abort
6.8.2
Functional Overview
The Sequence Manager controls and automates all transceiver sequences.
•
•
•
Software selects the desired sequence, sets the general parameters, and optionally configures a
hardware timer to trigger the sequence at a precise time in the future.
Subsequently, the MCU can enter a low-power state, or tend to other activities, while the sequence
manager state machine conducts the programmed transceiver operations.
When the sequence completes and a status is set, an interrupt request can alert the MCU. At this
point the MCU can check the completion status of the sequence, fetch received data from RAM (if
any), and then prepare the next sequence.
Sequences can be simple transceiver operations. For example, transmit one frame or perform a CCA
operation on a channel. Alternatively, the sequence manager supports complex sequences, which use
simple operations as building blocks, strung together in a back-to-back fashion, with precise timing
intervals between operations. For example, a “TR” sequence calls for a transmit frame followed by a
receive frame. For complex sequences, interrupts can optionally be generated at the completion of each
stage of the sequence, providing greater visibility for the MCU into the time line of the sequence. Software
can opt to abort a sequence at any time; when this happens, the sequence manager will return to its IDLE
state in an orderly fashion.
The sequence manager is responsible for the implementation of the Wireless Physical Layer (PHY)
specifications described in the IEEE 802.15.4 Standard. The timing of the basic operations is hard wired
and fixed. The higher-level timing parameters, such as the interval between operations in a complex
sequence, are largely programmable, except for those defined as constants in the IEEE 802.15.4 standard.
NOTE
Implementation of the full IEEE 802.15.4 Standard MAC sublayer services
requires software applications code that interfaces to and builds upon the
embedded hardware services. Freescale provides the complete MAC
solution as part of its BeeKit codebases. As a result, the descriptions for the
control and use of the sequence manager are presented primarily for
understanding as opposed to an in-depth applications guide. The user is
directed to use the supplied codebase(s).
6.8.3
Control Model Summary
The control and status fields associated with the sequence manager are shown in Table 6-10.
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Table 6-10. Sequence Control Model
Description
Register
Field
Register
Name
Control Fields
XCVSEQ[2:0]
CNTRL1 [2:0] Sequence select field — writing a command to this field will start execution of the
sequence unless a timer-triggered mode is enabled. See Table 6-11 for coding and
supported sequences
TMRTRIGEN
CNTRL1 [7] Timer 2 Trigger Enable — this bit enables the timer-triggered mode. When enabled,
execution of the sequence is delayed until a Timer Comparator 2 match is valid to initial
the sequence
CCABFRTX
SLOTTED
CNTRL1 [5] CCA Before TX — this bit enables a CCA cycle prior to a transmit. Applies only to T and
T/R sequences
CNTRL1 [6] Slotted Mode — this bit enables slotted mode for beacon-enabled networks. Applies
only to T, T/R, and R sequences.
RXACKRQD
CNTRL1 [4] Receive Acknowledgement Required — used only with the T/R sequence, this bit
enables the option where an Ack frame is expected to be received immediately
following a transmission.
AUTOACK
CNTRL1 [3] Auto Acknowledge Enable — used only with the R and T/R sequences, this bit enables
the option where the sequence manager will send (transmit) a hardware generated Ack
frame following a received frame that requires an immediate Ack response
TC3TMOUT
CCATYPE [1:0]
PANCORDNTR
PROMISCUOUS
TC2’EN
CNTRL2 [6] Timer Comparator 3 Time-out — this bit enables using T3CMP as a time-out for a
receive cycle. Applies only to R and T/R sequences
CNTRL2 [4:3] CCA Type Select — this field selects the algorithm used during a CCA cycle. Used with
T, T/R, C and CCCA sequences
CNTRL2 [5] Pan Coordinator Enable — this bit enables the device as a Pan Coordinator and
impacts receive filtering during an R or T/R sequence
CNTRL2 [1] Promiscuous Mode Enable — this bit disables all receive filtering except length and
CRC checking during a R or T/R sequence
CNTRL2 [0] TC2’ Enable — this bit selects 24-bit (T2CMP) versus 16-bit (TC2’) compare when
Timer 2 is used to initiate start of a sequence
CRC_MSK
Status Fields
CRCVALID
CNTRL3 [7] CRC Redundancy Check — this bit can disable the CRC on a received frame
STATUS1 [7] Code Redundancy Check Valid — this flag indicates the compare result between the
FCS field, in the just received frame, and the internally calculated CRC value
CCA
STATUS1 [6] CCA Valid — this flag reports the result of a CCA operation
SRCADDR
STATUS1 [5] Source Address Indication — this flag reports a valid incoming data request frame with
matching source address and valid source address check sum
PI
STATUS1 [4] Poll Indication — this flag reports a valid incoming data request frame
TMR3IRQ1
STATUS1 [2] Timer Comparator 3 Flag — indicates a valid T3CMP compare. Can be used with using
T3CMP for read sequence time-out
TMR2IRQ1
STATUS1 [1] Timer Comparator 2 Flag — indicates a valid T2CMP compare. Can be used with using
T2CMP for timer-triggered sequence execution
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Table 6-10. Sequence Control Model
Description
Register
Field
Register
Name
RX_FRM_PEND
STATUS2 [7] Status of the frame pending bit of the frame control field for the just received packet
LO1_UNLOCK_IRQ STATUS2 [6] Local Oscillator Unlock — this flag A indicates an unlock condition in the RF PLL
FILTERFAIL_IRQ
STATUS2 [5] Receiver Packet Filter Fail — this flag indicates that the just received packet has been
rejected due to filtered elements within the packet
Clear Channel Assessment — this flag indicates completion of a CCA operation.
Receive — this flag indicates the completion of a receive operation
Transmit — this flag indicates the completion of a transmit operation
Sequence — this flag indicates the completion of a sequence operation
CCAIRQ
RXIRQ
TXIRQ
STATUS2 [3]
STATUS2 [2]
STATUS2 [1]
STATUS2 [0]
SEQIRQ
CCAFNL[7:0]
CCAFNL [7:0] Clear Channel Assessment Average — final result of a CCA operation or LQI from a
receive operation. In a T/R sequence, the final value is the LQI, not CCA.
1
TMR1IRQ and TMR4IRQ also are present but do not interact with the Sequence Manager
6.9
Supported Sequences
The following sections describe the control and execution of supported sequences in more detail.
The supported sequences are shown in Table 6-11.
Table 6-11. Transceiver Sequences
XCVSEQ
Sequence
Description
0
1
2
3
4
I
R
Idle
Receive Sequence – conditionally followed by a TxAck
Transmit Sequence
T
C
Standalone CCA
TR
Transmit /Receive Sequence – transmit unconditionally followed by either an R or
RxAck
5
6
7
CCCA
Continuous CCA – sequence completes when channel is idle
Reserved
Reserved
NOTE
In the sequence descriptions, status bits are set as appropriate to the
completion of a condition. Although not specifically stated, an interrupt
request can be initiated with setting of a given status, the the IRQ is enabled.
6.9.1
Initiating a Sequence
A sequence can be initiated directly (non-timer mode) or using a timer-triggered mode:
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•
For non-timer mode (TMRTRIGEN bit must be 0) – All sequences can be initiated immediately by
writing the desired sequence command to XCVSEQ (CNTRL1) during IDLE state to activate each
new sequence. Hardware detects the write to this register during IDLE, and initiates the sequence.
The XCVSEQ bits of CNTRL1 always read back what was previously written, they do not
necessarily reflect the state of the Sequence Manager. Because hardware detects the write to the
XCVSEQ register during IDLE, the XCVSEQ field must be set to IDLE after the sequence
completes (SEQIRQ interrupt), before initiating a new sequence.
•
For timer-trigger mode, the initiation of a sequence at a precise time in the future can be
programmed via Timer Comparator 2 (TMRTRIGEN bit must be 1) -
— The desired start time is determined by the Timer Comparator 2 and enabled by setting the
TMRTRIGEN bit.
— Either the 24-bit T2CMP register or the 16-bit TC2PRIME register can be used for the compare
value (this is determined by the TC2’EN bit of the CNTRL2 register, see Section 6.13.4,
“Transceiver Control Register 2 (CNTRL2)”). The desired start time is written to the selected
register.
— The desired sequence command is written to the XCVSEQ field and the sequence will
commence when the timer compare is valid.
— After the sequence completes (SEQIRQ interrupt), the XCVSEQ field must be set to IDLE
(0x0), before initiating a new sequence and the Timer Comparator 2 register must be re-written
to arm a new sequence. To be specific, at least the LS byte of either T2CMP or TC2PRIME
must be written to re-arm the sequence manager for a new sequence. The order of writing the
command to CNTRL1 or the timer register is not important, as long as a timer-match does not
occur prior to the completion of this programming.
6.9.2
Aborting a Sequence
Several means can abort a sequence.
6.9.2.1
Writing an IDLE Command to XCVSEQ
While a sequence is ongoing, software can abort the sequence at any time by writing IDLE (0x0) to
XCVSEQ, and the sequence manager state machine will respond with an orderly return to the SEQ_IDLE
state, and a SEQIRQ status will be generated.
While a sequence is underway, software should not attempt to change XCVSEQ (other than aborting the
sequence as previously described); the sequence manager will ignore all mid-sequence attempts to change
XCVSEQ.
NOTE
The sequence manager control logic is designed such that the command
field XCVSEQ must always be written to IDLE between sequences. This is
true for both successful completion of a sequence and an aborted sequence.
Upon end of the sequence, the XCVSEQ must be written to IDLE before
writing the next desired sequence.
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6.9.2.2
Timer Comparator 3 Time-out
Timer Comparator 3 can be used as a “bracketing” timer, i.e., to abort certain sequences after a
software-determined time-out period. This time-out mechanism is enabled by setting the TC3TMOUT
control bit in CNTRL2 Register to 1, and the comparator must be enabled by the TMR3CMP_EN control
bit in CNTRL4 Register.
6.9.2.3
RF PLL Unlock Condition (LO1 Unlock)
All sequences can be aborted by an RF PLL unlock detection; referred as LO1 unlock. After the operation
warm-up time, an unlock detection aborts the sequence at that point and an unlock status is set.
6.9.3
Sequence I (IDLE)
When the IDLE command is written to XCVSEQ, the sequence manager goes to its IDLE state. If not
already in idle, the sequence manager executes an orderly return to IDLE state. A SEQIRQ status is then
issued.
•
•
Writing IDLE value to XCVSEQ is the proper way to abort a sequence.
A write of IDLE to XCVSEQ should always be issued between two consecutive sequences
including the back-to-back execution of the same sequence.
6.9.4
Basic Receive Sequence – Sequence R (Receive)
Sequence R is the basic receive sequence and can be used to receive all types of 802.15.4 PHY- and
MAC-compliant frames, including reserved frame types. Using Sequence R, all receive frames which pass
frame-filtering rules and CRC check, are transferred to RAM.
6.9.4.1
Sequence R Basic Execution
The basic execution of a successful Sequence R is as follows:
1. Optional timer initiated -
— MCU writes T2CMP compare value to the desired initiation time
— Sets TMRTRIGEN
2. MCU initializes RXD_ADR_PNTR to desired start of RX buffer
3. MCU writes XCVSEQ = R
4. Optional timer initiated – Wait for T2CMP match (if TMRTRIGEN=1)
5. SEQ_MGR executes RxWarmup and enters receive mode.
6. Preamble Detected
7. SFD Detected
8. DMA RX Address Pointer initialized to RXD_ADR_PNTR
9. FrameLength (FLI) octet received and transferred to RAM
10. N additional octets received (N = FrameLength) and transferred to RAM.
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NOTE
If FrameLength > MAXFRAMELENGTH (127), then N =
MAXFRAMELENGTH.
11. If frame-filtering rules and CRC check pass:
— RXIRQ status issued
— SEQ_MGR executes RxWarmdown
— If received Frame Control Field indicates AckRequest = 1
– SEQ_MGR executes TxWarmup
– an Ack frame is transmitted using the received Sequence Number
– SEQ_MGR executes TxWarmdown
12. If frame-filtering rules or CRC check fail:
13. SEQIRQ status issued
NOTE
Reception of Acknowledge frames is not recommended using Sequence R.
This is because reception of an Acknowledge frame, usually follows a
transmitted frame, with a designated Sequence Number, so that the received
Acknowledge frame can be verified for the matching Sequence Number. In
a standalone Sequence R, there is no Sequence Number to verify against, so
any Acknowledge frame is merely transferred (DMAed) to RAM. The
appropriate way to receive Acknowledge frames is with Sequence TR with
the RXACKRQD bit asserted.
6.9.4.2
Sequence R T3CMP Time-out
After the Sequence R receiver warm-up, timer T3CMP can be enabled as a “bracketing” timer. If enabled
and a T3CMP timer match occurs (no incoming frame is detected), the sequence manager will warm down
the receiver and return to SEQ_IDLE state.
6.9.4.3
Sequence R Exceptions
Programmed options and incoming RX frame parameters affect Sequence R execution. Programmed
options that impact Sequence R include:
1. AUTOACK – when enabled, Sequence R transmits a hardware generated TX Ack frame after the
received frame if all necessary conditions are met.
2. PROMISCUOUS – when enabled, all filtering is disabled except for frame length check, and CRC
check is conditional on the CRCMSK. This mode also disables TxACK if enabled.
Frame filtering is programmable and the RX frame will normally be accepted or rejected on the basis of
the filter options. The above options provide exceptions and additions to the normal flow as shown in
Table 6-12.
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Table 6-12. Sequence R Execution versus Programmed Options
Option Select
Description
PROMIS-
CUOUS
AUTOACK
Enabled
Don’t Care
Promiscuous mode enabled —
• Disables all filtering except frame length check, and CRC check is conditional
• AUTOACK option is disabled – ro received frame will be acknowledged
Disabled
Disabled
Disabled
Enabled
Standard reception; no TxACK— when a frame is received, it is validated against all enabled
filtering, and no TxAck will be returned.
Standard reception; TxACK enabled —
• When a frame is received, it is validated against all enabled filtering
• Hardware-generated TxAck is returned if required (uses Rx frame Sequence Number). See
Table 6-13.
- AckRequest bit in Rx frame FrameControlField = 1 (ack requested)
- No CCA cycle is executed before the TxAck
- SLOTTED not enabled – RX-to-TX turnaround time is 192 µs max
- SLOTTED enabled; TxAck meets required symbol timing
When a TxAck frame is transmitted, its Frame Control Field is generated in hardware as defined in
Table 6-13. The Sequence Number for the Ack packet, will be the Sequence Number obtained from the
previously received frame.
Table 6-13. Frame Control Field for Hardware-generated Auto-TxAck Frame
FCF Field
FrameType
Value
Acknowledge
0
SecurityEnabled
FramePending
• If SRCADDR_EN=1, FramePending gets the value of FramePendingFlag from Source
Address Matching hardware
• If SRCADDR_EN=0, FramePending gets the value of ACK_FRM_PND.
AckRequest
0
PanIDCompression
Reserved (bits 7-9)
DstAddrMode
0
000
0
FrameVersion
SrcAddrMode
copy FrameVersion from the previously-received frame
0
6.9.5
Basic Transmit Sequence – Sequence T (Transmit)
Sequence T is the basic, standalone transmit sequence and can be used to transmit all types of 802.15.4
PHY- and MAC-compliant frames. However, it is not recommended for transmitting an Ack frame nor for
transmitting frames that expect a return Ack, see NOTE.
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NOTE
Sequence T is not recommended for transmission of Acknowledge frames.
This is because transmission of an Ack frame usually follows a received
frame with a designated Sequence Number. The recommended method is
use of Sequence R with the AUTOACK bit asserted where the sequence
manager automates the transmission of an Ack frame generated by
hardware following a received frame. However, the sequence manager
hardware does not prohibit generation of Ack frames using Sequence T.
Sequence T is not recommended for transmitting frames that expect a return
Acknowledge frame. Use a T/R sequence instead.
Sequence T allows for the insertion of 1 or 2 CCA (clear channel assessment) measurements prior to
transmission, to ensure that the selected channel is idle. The CCA-before-TX feature is governed by two
register bits, CCABFRTX and SLOTTED. All CCA measurements must indicate channel-idle, in order for
the sequence manager to initiate the transmission; if the channel is determined by CCA to be busy, the
sequence manager will terminate the sequence without a transmission. The number of CCA measurements
attempted by the sequence manager, and the timing of the measurements, is shown in Table 6-14.
Table 6-14. CCA Cycle Control and Timing
Timing of
Initiation of CCA
measurement #2
Timing of First Bit of
Transmitted Frame
(assumes channel idle)
Number of CCA Timing of Initiation of
measurements CCA measurement #1
CCABFRTX SLOTTED
0
1
X
0
0
Immediately follows TxWarmup
1
2
Immediately follows
RxWarmup
Immediately follows
RxPartialWarmdown and
TxPartialWarmup
1
1
Immediately follows
RxWarmup
320us after
Initiation of CCA
measurement #1
320us after Initiation of CCA
measurement #2
Only CCA Type 1 or CCA Type 2 should be used with Sequence T (and Sequence TR). Software must
configure the CCATYPE bits prior to initiating the auto sequence.
6.9.5.1
Sequence T Basic Execution
The basic execution of a successful Sequence T is as follows:
1. Optional timer initiated -
— MCU writes T2CMP compare value to the desired initiation time
— Sets TMRTRIGEN
2. Optional use of CCA cycle(s):
— MCU sets CCABFRTX if one or more CCA’s are required prior to transmit
— MCU sets SLOTTED if in slotted mode (2 CCA’s will be attempted)
3. MCU initializes TXD_ADR_PNTR to start of stored TX buffer
4. MCU writes XCVSEQ = T
5. Optional timer initiated – Wait for T2CMP match (if TMRTRIGEN=1)
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6. If CCABFRTX=1:
— SEQ_MGR executes RxWarmup
— SEQ_MGR initiates CCA measurement (takes 128us)
— if CCA indicates channel busy: sequence terminates and CCAIRQ & SEQIRQ status issued
— otherwise, if CCA indicates channel idle:
a) if SLOTTED=0, SEQ_MGR issues a CCAIRQ status and executes a RxPartialWarmdown
b) if SLOTTED=1, SEQ_MGR initiates a 2nd CCA, 320us after initiating 1st CCA.
– if SLOTTED=1, and channel busy, sequence terminates, CCAIRQ status & SEQIRQ status
issued
– if SLOTTED=1, and channel idle, SEQ_MGR issues a CCAIRQ status and executes a
RxPartialWarmdown
7. If SLOTTED=1, SEQ_MGR waits until 320us elapses after 2nd CCA initiation
8. SEQ_MGR executes TxPartialWarmup.
9. DMA TX Address Pointer initialized to TXD_ADR_PNTR
10. Preamble transmitted
11. SFD transmitted
12. FrameLength octet is fetched from first byte of TX buffer from RAM and transmitted
13. CRC engine is reset
14. N additional octets are fetched from RAM and transmitted (N = FrameLength – 2)
15. Each octet that is transmitted, is shifted through the CRC engine
16. After Nth octet transmitted, FCS is available from CRC engine.
17. FCS lower octet transmitted
18. FCS upper octet transmitted
19. SEQ_MGR issues TXIRQ status
20. SEQ_MGR executes TxWarmdown
21. SEQ_MGR issues SEQIRQ status
NOTE
Timer T3CMP is not used with Sequence T.
6.9.5.2
Sequence T Exceptions
The programmed CCA and slotted options affect Sequence T execution.
•
•
•
•
•
The use of one or two CCA cycles is determined by the options
The timing of the CCA cycles is impacted by the slotted option
The slotted option is used in beacon-enabled networks
The CCAIRQ status is always issued at completion of the CCA cycle(s)
A “busy” result for a CCA cycle terminates the sequence; any retries are controlled via software.
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6.9.6
Basic Sequence C (Standalone CCA)
Sequence C is the basic standalone CCA sequence where the sequence manager executes a Clear Channel
Assessment (CCA) cycle(s).
•
•
Any of the CCA algorithms can be selected
A CCA status is not reported for an ED CCA cycle, it has no meaning as an ED cycle is meant as
a channel scan function
•
This sequence does not support slotted CCA timing for beacon-enabled mode
The result of the CCA measurement is reported back to software in the CCA bit. The CCA bit indicates
either a busy channel (1), or an idle channel (0).
6.9.6.1
Sequence C Basic Execution
The basic execution of a successful Sequence C is as follows:
1. Optional timer initiated -
— MCU writes T2CMP compare value to the desired initiation time
— Sets TMRTRIGEN
2. MCU initializes CCATYPE
3. MCU writes XCVSEQ = C
4. Optional timer initiated – Wait for T2CMP match (if TMRTRIGEN=1)
5. SEQ_MGR executes RxWarmup
6. SEQ_MGR initiates CCA (using selected CCATYPE) by signalling the receiver
7. SEQ_MGR waits for CCA to complete
8. CCA bit is set to the CCA status (1 = Busy, 0 = Idle) except for CCATYPE = ED
9. CCAIRQ status issued
10. SEQ_MGR executes RxWarmdown
11. SEQIRQ status issued
NOTE
•
•
Timer T3CMP is not used with Sequence C.
The CCA cycle timing is consistent with Figure 6-3 and Figure 6-4.
6.9.7
Sequence T/R (Transmit/Receive)
Sequence TR is a very useful combination Transmit/Receive sequence. The sequence is executed as a
concatenation of a transmit operation followed by a receive operation, with a minimum TX-to-RX
turnaround time in between.
6.9.7.1
Sequence T/R Execution
There are 2 permutations of Sequence TR, depending on the RXACKRQD bit. For both permutations, the
Sequence T which constitutes the first half of a Sequence TR, is identical to the standalone Sequence T
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(XCVSEQ=2). This means that the transmit operation can be slotted or unslotted, and can be preceded by
1 or 2 CCA measurements, depending on the state of the CCABFRTX and SLOTTED bits.
The permutations are differences in the R sequence as determined by RXACKRQD control bit:
•
RXACKRQD = 0 – then Sequence TR is executed as a Sequence T followed by a Sequence R, with
a minimum TX-to-RX turnaround time in between. The Sequence R is identical to the standalone
Sequence R (XCVSEQ = 1). This means that the receive operation can be followed by an
automatic, hardware-generated transmit Acknowledge frame, if all the necessary conditions are
met.
•
RXACKRQD = 1 – then Sequence TR is executed as a Sequence T followed by a
Receive-Acknowledge-Only frame. This type of receive operation is special, and not the same as
a standalone Sequence R. The Ack-only receive operation filters all incoming frames, looking only
for an Acknowledge frame whose Sequence Number matches the Sequence Number which was
transmitted in the Sequence T portion of the sequence. All non-matching frames are discarded, and
after each non-matching frame, the sequence manager will return the receiver to preamble-detect
mode. This receive operation will continue until the matching Ack frame is received. Because this
is a Receive-Acknowledge-Only operation, and not a Sequence R, no receive octets are transferred
to RAM. The sequence ends with a RXIRQ interrupt, which indicates that the matching Ack frame
was successfully received.
If the transmit operation of a Sequence TR is requesting an Acknowledge frame of the receiving end device
(Frame Control Field: AckRequest=1), then Sequence TR with RXACKRQD=1 is the appropriate
procedure. Using Sequence TR with RXACKREQ = 0 is not recommended for this scenario, because there
is no Sequence Number matching.
Conversely, if the transmit operation of a Sequence TR is not requesting an Acknowledge frame of the
receiving end device (Frame Control Field: AckRequest = 0), then Sequence TR with RXACKRQD = 1
should never be used, because a receive acknowledge frame will not be forthcoming. Instead, use
Sequence TR with RXACKRQD = 0, or simply Sequence T, if no follow-up receive frame is expected.
6.9.7.2
Sequence T/R T3CMP Time-out
Similar to the Sequence R usage, after the Sequence T/R receiver warm-up, timer T3CMP can be enabled
as a “bracketing” timer. If enabled and a T3CMP timer match occurs (no incoming frame is detected), the
sequence manager will warm down the receiver and return to SEQ_IDLE state.
6.9.7.3
Sequence T/R Exceptions
See Section 6.9.4.3, “Sequence R Exceptions” and Section 6.9.5.2, “Sequence T Exceptions” for the
appropriate execution for the transmit or receive exceptions.
6.9.8
Sequence CCCA (Continuous CCA)
Sequence CCCA is the Continuous CCA sequence. This sequence is designed to accommodate situations
where channel availability may be infrequent, or low-duty-cycle, and a device needs to be able to transmit
at the earliest available opportunity. During Sequence CCCA, the sequence manager repeats CCA
measurements continuously until a channel-idle condition is found.
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6.9.8.1
Sequence CCCA Execution
For the CCAA operation:
•
•
Only CCA Mode 1 and Mode 2 may be used.
There is a 54us delay between CCA iterations. The actual interval between consecutive CCA
measurements, in the CCCA sequence, is exactly 188us.
•
•
After each CCA iteration, the CCA bit is set to the result of the measurement. As long as the CCA
bit is high (busy) at the end of the iteration, the sequence manager will initiate a new measurement.
Unlike Sequence C (standalone CCA), there is no CCAIRQ interrupt generated at the end of each
CCA measurement, until the channel-idle condition is detected, at which point CCAIRQ is issued.
•
•
The SLOTTED bit has no effect on this sequence.
A Sequence CCCA is aborted by the Sequence Manager if a TMR3 match occurs, and
TC3TMOUT=1.
The basic execution of a Sequence CCCA is as follows:
1. Optional timer initiated -
— MCU writes T2CMP compare value to the desired initiation time
— Sets TMRTRIGEN
2. MCU initializes CCATYPE to desired algorithm
3. MCU writes XCVSEQ = CCCA
4. Optional timer initiated – Wait for T2CMP match (if TMRTRIGEN=1)
5. SEQ_MGR executes RxWarmup and enters receive mode.
6. SEQ_MGR initiates CCA by signalling the receiver
7. SEQ_MGR waits for CCA to complete
8. CCA bit is set to the CCA status (1 = Busy 0 = Idle)
9. If CCA=1, initiate a new CCA measurement immediately and repeat the previous 3 steps
10. If CCA=0, CCAIRQ status is issued
11. SEQ_MGR executes RxWarmdown
12. SEQIRQ status issued
6.9.8.2
Sequence CCCA T3CMP Time-out
Timer T3CMP can be enabled as a “bracketing” timer. If enabled and a T3CMP timer match occurs (no
incoming frame is detected), the sequence manager will warm down the receiver and return to SEQ_IDLE
state.
6.9.8.3
Sequence CCCA Exceptions
Because of the repeated CCA operations:
•
The CCA bit (STATUS1 register) and the CCAFNL register will change dynamically during the
CCA measurement, and are only considered valid (and sampled by the Sequence Manager), at the
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end of the CCA measurement; therefore the user should not continuously poll CCA and CCAFNL
and expect continuously-valid results, because they are not latched.
•
The user can continuously monitor the Sequence CCCA status by reading the CCAIRQ status
6.9.9
Effect of Timer TC3 on Sequence Manager
Timer TC3 can be used as a “bracketing” timer, to abort certain sequences after a software-determined
time-out period. This time-out mechanism is enabled by setting the TC3TMOUT bit to 1. If
TC3TMOUT=0, then the abort mechanism is disabled, and timer TC3 functions merely as a software
timer.
Timer TC3’s hardware-abort functions are summarized in the following table.
Table 6-15. TC3 Hardware Abort Functions
SEQUENCE
TC3TMOUT=0
S/W timer
TC3TMOUT=1
I
S/W timer
R
T
C
S/W timer
S/W timer
S/W timer
S/W timer
S/W timer
Abort sequence
S/W timer
S/W timer
TR
Abort sequence, (during receive operation only)
Abort sequence
CCCA
6.10 Transmitter Power Amplifier (PA) Control
The on board differential power amplifier (PA) can be programmed to set output power, see
Section 6.13.25, “Power Amplifier (PA) Power Control Register (PA_PWR_CNTL)”. The PA outputs are
enabled via hardware when a transmit operation occurs.
6.11 Hardware Pseudo-Random Number Generator
To assist in generating seeds/keys for the AES security, the MC13234/MC13237 provides hardware
generation of a pseudo-random 16-bit number. The accumulator of the FracN counter used in the LO1
synthesizer is read to provide this number. Access to the FracN hardware uses an indirect addressing
technique that is normally reserved for chip test using the indirect access registers described in
Section 6.13.33, “Transceiver Indirect Access Registers (INDEX and DATA)”
NOTE
To generate the pseudo-random 16-bit number, a software function activates
the synthesizer for a random time from between 1 – 10 ms and then read
accesses the FracN accumulator. Freescale provides this function call as part
of its various software stacks. The user is directed to use this function.
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6.12 Transceiver Interrupt Requests (IRQs)
The transceiver components can be programmed to generate an interrupt request from a number sources
and status flags. Table 6-16 lists source status bits, mask bits, and interrupt vector numbers for transceiver
IRQs.
Table 6-16. Transceiver Interrupt Request Sources
Interrupt
Vector
No.
Status
Flag
Mask
Bit
Source
Description
Interrupt Clear
Mechanism
Item
General IRQ Disable
1
TRCV_MSK
General control that allows
status flags from the modem
(transmitter/ receiver) to
generate an interrupt request.
This bit disables all IRQs
RX DMA
2
RXWTRMRKIRQ RX_WMRK_MSK
Received DMA byte count
matches “watermark” level
Write “1” to status flag
Write “1” to status flag
7
6
Event Timer Block
3
TMR1IRQ
TMR1MSK
TMR2MSK
Timer Comparator 1 value
matched event timer counter
TMR2IRQ
Timer Comparator 2 value
matched event timer counter
Write “1” to status flag. This
flag is shared between
T2CMP and TC2’
TMR3IRQ
TMR4IRQ
TMR3MSK
TMR4MSK
Timer Comparator 3 value
matched event timer counter
Write “1” to status flag
Timer Comparator 4 value
matched event timer counter
Write “1” to status flag
Transmit Function
4
LO1_LOCK_IRQ LO1_UNLOCK_MSK Local Oscillator 1 (RF PLL) has Write “1” to status flag
5
experienced an unlock
condition
TXIRQ
TXMSK
Flag indicates completion of a
transmit operation
Write “1” to status flag
SEQIRQ
SEQMSK
Flag indicates completion of the Write “1” to status flag
programmed sequence
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Table 6-16. Transceiver Interrupt Request Sources (continued)
Interrupt
Vector
No.
Status
Flag
Mask
Bit
Source
Description
Interrupt Clear
Mechanism
Item
Receive / CCA Function
5
LO1_LOCK_IRQ LO1_UNLOCK_MSK Local Oscillator 1 (RF PLL) has Write 1 to status flag
4
experienced an unlock
condition
RXIRQ
RXMSK
Flag indicates completion of a
receive operation
Write 1 to status flag
Write 1 to status flag
FILTERFAIL_IRQ FILTERFAIL_MSK
Received packet has been
rejected due to enabled filtering
elements
CCAIRQ
SEQIRQ
CCAMSK
SEQMSK
Flag indicates completion of a
CCA operation
Write 1 to status flag
Flag indicates completion of the Write 1 to status flag
programmed sequence
NOTE
The LO1 unlock and SEQIRQ status vector to a different Interrupt Vector
Number based on the enabled sequence:
•
•
For a T or T/R sequence — these use vector No. 5
For an R, C, or CCCA sequence — these use vector No. 4
6.13 Register Definitions
The following sections describe the transceiver control and status registers. The transceiver registers are
organized in two blocks;
•
•
Direct Page registers – more commonly accessed registers, always directly accessible
High-Page registers – less commonly accessed registers, located at Page 0x1800
Table 6-17 lists both Direct and High Page register addresses. The register descriptions are organized by
address.
Table 6-17. Transceiver Register Addresses
Direct Page
Address
High Page
Address
Register Name
TXD_ADR_PNTR0
Register Name
0x0040
0x0041
0x0042
0x0043
0x0044
0x1840
0x1841
0x1842
0x1843
0x1844
T1CMP0
T1CMP1
T1CMP2
T2CMP0
T2CMP1
TXD_ADR_PNTR1
RXD_ADR_PNTR0
RXD_ADR_PNTR1
CNTRL1
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Table 6-17. Transceiver Register Addresses (continued)
Direct Page
Address
High Page
Address
Register Name
Register Name
0x0045
0x0046
0x0047
0x0048
0x0049
0x004A
0x004B
0x004C
0x004D
0x004E
0x004F
0x0050
0x0051
0x0052
0x0053
0x0054
0x0055
0x0056
0x0057
CNTRL2
CNTRL3
CNTRL4
0x1845
0x1846
0x1847
0x1848
0x1849
0x184A
0x184B
0x184C
0x184D
0x184E
0x184F
0x1850
0x1851
0x1852
0x1853
0x1854
0x1855
0x1856
0x1857
T2CMP2
T4CMP0
T4CMP1
T4CMP2
SRC_CNTRL
SRC_ADDRS_SUM_DATA0
SRC_ADDRS_SUM_DATA1
RX_WTR_MARK
RX_BYTE_COUNT
STATUS1
LO1_FRAC0
LO1_FRAC1
LO1_INT
PA PWR CNTL
MACLONGADDRS0
MACLONGADDRS1
MACLONGADDRS2
MACLONGADDRS3
MACLONGADDRS4
MACLONGADDRS5
MACLONGADDRS6
MACLONGADDRS7
MAXFRAMELENGTH
RX FRAME FILTER
STATUS2
Reserved
CCAFNL
EVENT_TMR0
EVENT_TMR1
EVENT_TMR2
TIMESTAMP0
TIMESTAMP1
TIMESTAMP3
T3CMP0
MAC FRAME VER FMR
REV&TMR
0x0058
0x0059
0x005A
0x005B
0x005C
0x005D
0x005E
0x005F
T3CMP1
0x1858
0x1859
0x185A
0x185B
0x185C
0x185D
0x185E
0x185F
CCA_THRESHOLD
CCA_OFFSET_CMP
FSM
T3CMP2
TC2 PRIME0
TC2 PRIME1
MACSHORTADDRS0
MACSHORTADDRS1
MACPANID0
MACPANID1
INDIRECT ACCESS INDEX
INDIRECT ACCESS DATA
Reserved
Reserved
Reserved
6.13.1 Transmit Data Pointer Registers (TXD_ADR_PNTR0 and
TXD_ADR_PNTR1)
The Transmit Data Pointer [12:0] Register holds the base address of the RAM buffer from which data is
to be supplied for packet transmit. The 13-bit address pointer is composed of two registers:
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•
•
TXD_ADR_PNTR0 – which contains the most significant 5 bits (TXD_ADR_PNTR[12:8])
TXD_ADR_PNTR1 – which contains the least significant 8bits (TXD_ADR_PNTR[7:0])
The DMA uses this base address to start fetching payload data for a packet transmission.
TXD_ADR_PNTR0
0x0040
7
6
5
4
3
2
1
0
R
W
—
—
0
—
TXD_ADR_PNTR[12:8]
0
Reset
0
0
0
0
0
0
TXD_ADR_PNTR1
0x0041
7
6
5
4
3
2
1
0
R
W
TXD_ADR_PNTR[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-10. Transmit Data Pointer Registers
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6.13.2 Receive Data Pointer Registers (RXD_ADR_PNTR0 and
RXD_ADR_PNTR1)
The Receive Data Pointer [12:0] Register holds the base address of the RAM buffer to which data is to be
sent for a packet reception. The 13-bit address pointer is composed of two registers:
•
•
RXD_ADR_PNTR0 – which contains the most significant 5 bits (RXD_ADR_PNTR[12:8])
RXD_ADR_PNTR1 – which contains the least significant 8bits (RXD_ADR_PNTR[7:0])
The DMA uses this base address to start writing payload data from a packet reception.
RXD_ADR_PNTR0
0x0042
7
6
5
4
3
2
1
0
R
W
—
—
0
—
RXD_ADR_PNTR[12:8]
0
Reset
0
0
0
0
0
0
RXD_ADR_PNTR1
0x0043
7
6
5
4
3
2
1
0
R
W
RXD_ADR_PNTR[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-11. Receive Data Pointer Registers
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6.13.3 Transceiver Control Register 1 (CNTRL1)
CNTRL1 is one of several registers that control basic operation of the transceiver. Included in this register
are fields for:
•
•
•
•
•
•
Direct versus timer-initiated operation
Slotted versus normal timing operation
CCA operation before transmit
Auto ACK during a T/R sequence
Transmit auto ACK
Transceiver operation – sets sequence manager operation mode
CNTRL1
0x0044
7
6
5
4
3
2
1
0
R
TMRTRIGEN SLOTTED CCABFRTX RXACKRQD AUTOACK
XCVSEQ
0
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-12. Transceiver Control Register 1
Table 6-18. CNTRL1 Field Descriptions
Description
Field
TMRTRIGEN Timer Trigger Enable — enables timer-triggered sequences using Timer Comparator 2
0 Selected transceiver operation initiated manually upon write of XCVSEQ command
1 Selected transceiver operation initiated via Event Timer Comparator 2 or TC2_PRIME (see TC2’EN)
SLOTTED
Slotted Mode — enables slotted mode for beacon-enabled networks. Applies only to Sequences T, TR, and
R, ignored during all other sequences. Used in concert with CCABFRTX to determine how many CCA cycles
are required prior to a transmit operation. Also used during R sequence to determine whether the ensuing
transmit acknowledge frame (if any) needs to be synchronized to a back off slot boundary.
0 Normal operation
1 Slotted mode – specifies to the TX, CCA and AutoAck mechanism that an auto back off needs to be
computed and applied to their timing.
• For AutoAck operations, this computed back off is only applied to the TxAck transmissions when both the
SLOTTED and AUTOACK bits are enable (set to '1').
• In the case of a CCA sequence a SLOTTED bit setting of '1' will cause the CCA to be executed two times,
with the second CCA occurring 20 symbols after the beginning of the first one.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-18. CNTRL1 Field Descriptions
Field
Description
CCABFRTX
Clear Channel Assessment Before Transmit — this bit controls the introduction of a CCA operation prior
to the start of transmit operation. Applies only to Sequences T and TR, ignored during all other
sequences.
This bit only affects sequences in which the transmit operation is the first element of the sequence. For
instance a Transmit only sequence will begin with a CCA followed by TX when this bit is enabled.
The CCA operation will start the sequence in accordance to the result by the CCA operation. If the CCA flag
indicates a clear channel (set to 0), the sequence continues to the transmit operation; otherwise it is
terminated.
0 Disabled – no CCA executed, transmit operation begins immediately.
1 Enabled – at least one CCA measurement is required prior to the transmit operation (see also
SLOTTED)
RXACKRQD RX Acknowledge Required — Applies only to Sequence TR, ignored during all other sequences.
0 Disabled – an ordinary receive frame (not an Ack frame) follows the transmit frame; thus a simple
Receive operation is executed in the TR sequence.
1 Enabled – a receive Ack frame follows the transmit frame.
AUTOACK
Auto Acknowledge Enable — applies only to Receive (R) sequence or T/R Sequence (ignored
otherwise).
0 Disabled – sequence manager will not follow a receive frame with a Tx Ack frame under any conditions;
the sequence will terminate after the receive frame
1 Enabled – sequence manager will follow a receive frame with an automatic hardware-generated TX Ack
frame, assuming other necessary conditions are met.
[2:0]
XCVSEQ
Transceiver Sequence — Writing a command selects one of six possible transceiver operations.
• Writing a new command while in the IDLE state initiates a new sequence.
• The sequence start can be optionally delayed through a timer-triggered mode (see TMRTRIGEN)
• Writing an IDLE command aborts any ongoing sequence.
• Writing of an IDLE command must always be performed after a sequence is complete, before a new
sequence is programmed or the new command will be ignored.
• Any write to XCVSEQ other than XCVSEQ = IDLE during an ongoing sequence, shall be ignored.
See Table 6-19 for the available operations.
Table 6-19. Transceiver Field XCVSEQ[2:0] Operations
XCVSEQ[2:0]
Sequence Name
Description
000
IDLE (I)
Idle State (default) – should be set after completed sequence. Setting IDLE during a
sequence aborts the sequence.
001
010
011
100
Receive (R)
Transmit (T)
CCA (C)
TR
Receive Sequence – may be conditionally followed by a TxAck
Transmit Sequence – a proceeding CCA can be optionally executed
Clear Channel Assessment – standalone sequence
Transmit / Receive Sequence – transmit sequence (conditional CCA) followed by a
frame receive or if the RXACKRQRD bit is set, an RxAck will also be performed.
101
CCCA (C)
Continuos CCA – CCA operations are executed back-to-back in a continuos stream
until an idle channel status is found or the sequence is aborted by an IDLE command.
110
111
Reserved
Reserved
Not used
Not Used
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6.13.4 Transceiver Control Register 2 (CNTRL2)
CNTRL2 is one of several registers that control basic operation of the transceiver. Included in this register
are fields for:
•
•
•
•
•
•
•
Master mask bit for enabling transceiver interrupt requests
Timer Comparator 3 mode control
PAN Coordinator enable
CCA type selection
Loading Event Timer counter (current time)
Receiver promiscuous mode enable
Event Timer TC2 Comparator mode control
CNTRL2
0x0045
7
6
5
4
3
2
1
0
R
0
TRCV_MSK TC3TMOUT PANCORDNTR
CCATYPE
PROMISCUOUS
0
TC2’EN
W
TMRLOAD
0
Reset
0
0
0
0
1
0
= Unimplemented or Reserved
Figure 6-13. Transceiver Control Register 2
Table 6-20. CNTRL2 Field Descriptions
Description
Field
TRCV_MSK Modem Interrupt Mask — this bit is the general interrupt request mask for the transceiver. IRQs must be
enabled via this bit for the other masks to have effect
0 Interrupt requests enabled
1 Interrupt requests disabled
Timer Comparator 3 Time-out — this bit selects use of the Timer Comparator 3 when it is enabled
TC3TMOUT 0 Event Timer Comparator 3 used as standard Event Timer.
1 Event Timer Comparator 3 is dedicated to RX time-out.
PAN-
CORDNTR 0 Device is not a Pan Coordinator
1 Device is a Pan Coordinator, packet filtering can accept MAC command or data frames with no destination
Pan Coordinator Enable — this bit enables the node as a PAN coordinator
address.
[1:0]
CCA Type — this field selects one of three possible types of CCA algorithms. See Table 6-21 for details.
CCATYPE
TMRLOAD Timer Load — A low to high transition of this bit causes the value of field 'T1CMP[23:0]' to be loaded into the
Event Timer Counter. This is a self-clearing bit, always reads zero.
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Table 6-20. CNTRL2 Field Descriptions (continued)
Description
PROMIS- Promiscuous Mode Enable — enable a “promiscuous” receiver mode; also prevents auto-TxAck on
Field
CUOUS
received packets
0 Normal operation
1 All filtering disabled except for length checking. CRC checking determined by CRCMSK bit; prevents
auto-TxAck
TC2’EN
TC2 Prime Enable — This bit is used to select whether the TC2' or the TC2CMP comparator starts the
sequence.
0 Use TC2 (24-bit compare)
1 Use TC2' (16-bit compare)
Table 6-21. CCATYPE Select Options
CCATYPE[1:0]
Type
Description
00
01
ED – energy detect
Use only with Sequence C as part of channel scan
CCA 802.15.4 Mode 1
Measures any energy on the channel. Use with
Sequences T, T/R, C, and CCA
10
11
CCA 802.15.4 Mode 2
Reserved
Measures only 802.15.4 modulated energy on the
channel. Use with Sequences T, T/R, C, and CCA
Not used
6.13.5 Transceiver Control Register 3 (CNTRL3)
CNTRL3 is one of several registers that control basic operation of the transceiver. Included in this register
are fields for:
•
•
CRC disable for reception
Masks for enabling interrupt requests
— LO1 unlock
— RX packet filtering
— RX DMA “water mark”
— CCA complete
— RX complete
— TX complete
— Sequence complete
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0x0046
CNTRL3
7
6
5
4
3
2
1
0
R
W
LO1_UNLOC FILTERFAIL RX_WMRK_
CRC_MSK
CCAMSK
RXMSK
TXMSK
SEQMSK
K_MSK
_MSK
MSK
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-14. Transceiver Control Register 3
Table 6-22. CNTRL3 Field Descriptions
Description
Field
CRC_MSK
Cyclic Redundancy Check
0 CRC result ignore by sequence manager.
1 Normal operation
LO1_UNLOCK_MSK Local Oscillator 1 Unlock Interrupt Mask Enable
0 allows lo1_lock_irq to generate an interrupt pin.
1 lo1_lock_irq status bit is set, but an interrupt is not generated. The operation is aborted.
FLITERFAIL_MSK FLITERFAIL Interrupt Mask Enable
0 Allows for RX Packet filtering to set the FILTERFAIL_IRQ flag
1 FILTERFAIL_IRQ not generated but filtering will take place. If filtering is not wanted enable
Promiscuous mode.
RX_WMRK_MSK
CCAMSK
Receiver Water Mark Interrupt Mask Enable
0 Allows for Received Count Water Mark interrupt to occur.
1 Received Count Water Mark interrupts inhibited
Clear Assessment Interrupt Mask
0 Allows generation of CCA Interrupts and setting of CCAIRQ flag after CCA operation is completed.
1 Interrupt is masked, CCA is completed and CCA status is set accordingly after completion, but the
interrupt is not generated.
RXMSK
TXMSK
Receiver Interrupt Mask
0 Allows generation of Receiver Interrupts and setting of RXIRQ flag after RX operation is completed.
1 Receiver Interrupt Mask, disables interrupt generation from the receiver operation
Transmitter Interrupt Mask
0 Allows generation of Transmitter Interrupts and setting of TXIRQ flag after TX operation is completed.
1 Transmitter Interrupt Mask, disables interrupt generation from the transmit operation
SEQMSK
Sequence Interrupt Mask
0 Allows generation of Receiver Interrupts and setting of SEQIRQ flag after Sequence is completed.
1 Sequence Interrupt Mask, disables interrupt generation from the sequence completion.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-45
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.6 Transceiver Control Register 4 (CNTRL4)
CNTRL4 is one of several registers that control basic operation of the transceiver. Included in this register
are fields for:
•
•
Mask for enabling Event Timer Comparators 1-4
Enable bits for Event Timer Comparators 1-4
CONTROL4
0x0047
0x0047
7
6
5
4
3
2
1
0
R
TMR4CMP_ TMR3CMP_ TMR2CMP_ TMR1CMP_
TMR4MSK
TMR3MSK
TMR2MSK
TMR1MSK
EN
EN
EN
EN
W
Reset
1
1
1
1
0
0
0
0
= Unimplemented or Reserved
Figure 6-15. Transceiver Control Register 4
Table 6-23. CNTRL4 Field Descriptions
Description
Field
TMR4MSK Timer Comparator 4 Interrupt Mask
0 allows interrupt when comparator matches event timer count.
1 Interrupt generation is disable, but an TMR4IRQ flag it set.
TMR3MSK Timer Comparator 3 Interrupt Mask
0 allows interrupt when comparator matches event timer count.
1 Interrupt generation is disable, but an TMR3IRQ flag it set.
TMR2MSK Timer Comparator 2 Interrupt Mask
0 allows interrupt when comparator matches event timer count.
1 Interrupt generation is disable, but an TMR2IRQ flag it set.
TMR1MSK Timer Comparator 1Interrupt Mask
0 allows interrupt when comparator matches event timer count.
1 Interrupt generation is disable, but an TMR1IRQ flag it set.
TMR4CMP_ Timer Comparator 4 Enable
EN
0 Interrupt is disabled and TMR4IRQ status bit flag is cleared.
1 Standard operation
TMR3CMP_ Timer Comparator 3 Enable
EN 0 Interrupt is disabled and TMR3IRQ status bit flag is cleared.
1 Standard operation
TMR2CMP_ Timer Comparator 2 Enable
EN 0 Interrupt is disabled and TMR2IRQ status bit flag is cleared.
1 Standard operation
TMR1CMP_ Timer Comparator 1 Enable
EN 0 Interrupt is disabled and TMR1IRQ status bit flag is cleared.
1 Standard operation
MC13234/MC13237 Reference Manual, Rev. 1.8
6-46
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.7 Transceiver Source Address Control Register (SRC_CNTRL)
The SRC_CNTRL register enables and controls the the Source Address Matching function in the sequence
manager.
SRC_CNTRL
0x0048
0x0048
7
6
5
4
3
2
1
0
R
ACK_FRM_ SRCADDR_
INDEX_DISA
BLE
INDEX
INDEX_EN
PND
EN
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-16. Transceiver Source Address Control Register
Table 6-24. SRC_CNTRL Field Descriptions
Description
Field
INDEX
Index — The index field selects one of 12 table entries to be updated. The match state machine will return
the index of the element whose value matches the incoming frame. If there was no match, the Index will
be b1111 (0xF).
ACK_FRM_PND Frame Pending Acknowledge — If SRCADDR_EN enable field is a 0, then ACK_FRM_PND gets copied
into the TXACK frame.
SRCADDR_EN Source Address Matching Enable — This bit enables the Source Address Matching function. If this bit is
equal to zero, the pend bin in the TxAck frame will be taken from ACK_FRM_PND.
Note: AUTOACK enable bit must be set to send any auto-TxAck frame
INDEX_EN
Index Enable — Setting this bit to a '1' enables the selected index.
Write only (read operations return '0')
INDEX_DISABLE Index Disable— Setting this bit to a '1' the disables the selected index.
Write only (read operations return '0')
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-47
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.8 Transceiver Source Address Sum Data Registers
(SRC_ADDRS_SUM_DATA0 and SRC_ADDRS_SUM_DATA1)
The Source Address Sum Data [15:0] Register holds the 16-bit sum data compare value as calculated from
the enabled IEEE 802.15.4 address mode:
•
•
SRC_ADDRS_SUM_DATA0 – the most significant 8 bits (SRC_ADDRS_SUM_DATA[15:8])
SRC_ADDRS_SUM_DATA1 – the least significant 8 bits (SRC_ADDRS_SUM_DATA[7:0])
SRC_ADDRS_SUM_DATA0
0x0049
7
6
5
4
3
2
1
0
R
SRC_ADDRS_SUM_DATA[15:8]
W
Reset
0
0
0
0
0
0
0
0
SRC_ADDRS_SUM_DATA1
0x004A
7
6
5
4
3
2
1
0
R
W
SRC_ADDRS_SUM_DATA [7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-17. Transceiver Source Address Sum Data Registers
Table 6-25. SRC_ADDRS_SUM_DATA Field Description
Description
Field
SRC_
Source Address Sum Data— The Source Address Sum register is composed of 2 8-bit registers. These
ADDRS_
registers are loaded by the MCU software with the sum of address elements. The software must compute this
SUM_DATA 16-bit data field in accordance with the following:
Short Address:
SourcePanID[15:0] (if intra-pan substitutes Destination Pan ID)
+ SourceAddr[15:0]
Calculated Value to be placed in Table and Compare Against
Long Address sum data is calculated:
SrcPanID[15:0]
SourceAddr[15: 0]
SourceAddr[31:16]
SourceAddr[47:32]
+ SourceAddr[63:48]
Calculated Value to be place in Table and Compare Against
MC13234/MC13237 Reference Manual, Rev. 1.8
6-48
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.9 Receiver Byte Count Watermark Threshold (RX_WTR_MARK)
The RX_WTR_MARK register holds an 8-bit field that sets the level of received packet bytes needed to
enable a receive interrupt request.
•
•
Maximum usable count is 125 bytes.
A count of 126 or larger (default 0xFF) will never generate an interrupt request
RX_WTR_MARK
0x004B
7
6
5
4
3
2
1
0
R
RX_WTR_MARK[7:0]
W
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-18. Receiver Byte Count Watermark Threshold
Table 6-26. RX_WTR_MARK Field Description
Description
Field
[7:0]
Receiver Byte Count Interrupt Watermark— Receive byte count (octets) needed to trigger a RX interrupt.
RX_WTR_MARK The count is started at the beginning after the SFD field. A setting of 0 generates an interrupt at end of the
SFD field.
6.13.10 Receiver Byte Count (RX_BYTE_COUNT)
The read-only RX_BYTE_COUNT register reports the present number of received bytes in a packet.
RX_BYTE_COUNT
0x004C
7
6
5
4
3
2
1
0
R
RX_BYTE_COUNT[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-19. Receiver Byte Count
Table 6-27. RX_BYTE_COUNT Field Description
Description
Field
[7:0]
Receiver Byte Count — Received byte count (octets) after the SFD field.
RX_BYTE_COUNT Read only.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-49
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.11 Status Register 1 (STATUS1)
STATUS1 is one of two status registers for the transceiver. Included in this register are fields for:
•
•
•
•
•
CRC valid status
CCA result
Received packet Source Address test result
Poll Indication status
Event timer Comparator 1-4 compare status
STATUS1
0x004D
7
6
5
4
3
2
1
0
R
CRCVALID
CCA
SRCADDR
PI
TMR4IRQ
TMR3IRQ
0
TMR2IRQ
TMR1IRQ
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-20. Status Register 1
Table 6-28. STATUS1 Field Descriptions
Description
Field
CRCVALID Code Redundancy Check Valid — This flag indicates the compare result between the FCS field, in the just
received frame, and the internally calculated CRC value. This flag is clear at receiver warm up.
0 RX FCS <> CRC (incorrect)
1 RX FCS = CRC (correct)
CCA
Clear Channel Assessment Result — This flag works in conjunction with the CCA type selected
CCA Type 0:
Not used.
CCA Type 1:
This flag is set as the result of comparison between the Energy measured (ED) and the CCA threshold register
(CCA_THRESHOLD).
If ED <= CCA_THRESHOLD, channel busy detected, CCA = 1
If ED > CCA_THRESHOLD, channel idle detected, CCA = 0
CCA Type 2:
This flag is set as the result of comparison between number of correlation peaks (NUM_CORR_PEAKS) that
exceeded the threshold value and the CCA Mode 2 threshold register (CCA2_MIN_NUM_CORR_TH)
If NUM_CORR_PEAKS ? CCA2_MIN_NUM_CORR_TH, channel busy detected, CCA = 1
If NUM_CORR_PEAKS < CCA2_MIN_NUM_CORR_TH, channel idle detected, CCA = 0
CCA Type 3:
Reserved.
MC13234/MC13237 Reference Manual, Rev. 1.8
6-50
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-28. STATUS1 Field Descriptions (continued)
Description
Field
SRCADDR Source Address Checksum — Part of the source address feature. Indicates that:
1 – The incoming packet was a data request;
2 – Source address matching is enabled, SRCADDR_EN = 1
3 – Source address check sum computed by packet processor matched at least one entry in the source address
table.
This is a read only bit.
PI
Poll Indication —
1 the received packet was a data request, regardless of whether a source address table match occurred, or
whether source address matching is enabled (See SRCADDR_EN bit)
0 the received packet was not a data request.
TMR4IRQ Timer Comparator 4 Interrupt
1 Indicates comparator value matched event timer counter. This is write 1 to clear bit.
TMR3IRQ Timer Comparator 3 Interrupt
1 Indicates comparator value matched event timer counter. This is write 1 to clear bit.
TMR2IRQ Timer Comparator 2 Interrupt
1 Indicates comparator value matched event timer counter. This is write 1 to clear bit.
This flag is shared between TC2’ and TC2.
TMR1IRQ Timer Comparator 1 Interrupt
1 Indicates comparator value matched event timer counter. This is write 1 to clear bit.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-51
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.12 Status Register 2 (STATUS2)
STATUS2 is the second of two status registers for the transceiver. Included in this register are fields for:
•
•
•
•
•
•
•
•
Frame pending status
LO1 unlock status
Receiver Packet Filter Fail status
RX watermark status
CCA completion status
RX completion status
TX completion status
Sequence completion status
STATUS2
0x004E
7
6
5
4
3
2
1
0
R
RX_FRM_PE LO1_UNLOC FILTERFAIL_ RXWTRMRK
CCAIRQ
RXIRQ
TXIRQ
SEQIRQ
ND
K_IRQ
IRQ
IRQ
W2C
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-21. Status Register 2
Table 6-29. STATUS2 Field Descriptions
Description
Field
RX_FRM_PEND
Receiver Frame Pending — Status of the frame pending bit of the frame control field for the just
received packet
LO1_UNLOCK_IRQ Local Oscillator Unlock — A 1 indicates an unlock condition in the PLL.This is write a 1 to clear bit
FILTERFAIL_IRQ Receiver Packet Filter Fail — A 1 indicates that the just received packet has been rejected due to
elements within the packet. This is write a 1 to clear bit.
RXWTRMRKIRQ Receiver Byte Count Water Mark — A 1 indicates that the number of bytes specified in the
RX_WTR_MARK register has been reached.This is write a 1 to clear bit.
CCAIRQ
RXIRQ
Clear Channel Assessment flag. A 1 indicates completion of CCA operation. This is write a 1 to clear bit.
Receiver flag. A '1' indicates the completion of a received operation. This is write a 1 to clear bit.
Transmitter flag. A '1' indicates the completion of a transmit operation. This is write a 1 to clear bit.
Sequence flag. A '1' indicates the completion of a sequence operation. This is write a 1 to clear bit.
TXIRQ
SEQIRQ
MC13234/MC13237 Reference Manual, Rev. 1.8
6-52
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.13 Clear Channel Assessment Final Value (CCAFNL)
The read-only CCAFNL register reports either of two values:
•
The final CCA value as averaged over the selected CCA type-appropriate sample time (after a
CCA cycle)
•
The LQI value for a received frame.
CCAFNL
0x0050
7
6
5
4
3
2
1
0
R
CCAFNL[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-22. Clear Channel Assessment Final Value
Table 6-30. CCAFNL Field Description
Description
Field
[7:0]
Clear Channel Assessment Average — Average result of the selected CCA algorithm selected through the
CCAFNL CCATYPE field.
00 CCA calculated over 4 symbols – 4*16uS = 64uS
01 CCA calculated over 8 symbols – 8*16uS = 128uS
10 CCA calculated over 8 symbols – 8*16uS = 128uS
11 Reserved
At the end of any received packet, this field contains the Link Quality Indicator (LQI) value; which is the
measurement of the received energy that occurs during the received frame, immediately the preamble, and over
4 symbol period (64uS)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-53
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.14 Event Timer Registers (EVENT_TMR0, EVENT_TMR1, and
EVENT_TMR2)
The read-only Event_Timer [23:0] Registers holds the current value of the event timer counter. The 24-bit
counter value is composed of three registers:
•
•
•
EVENT_TMR0 – the most significant 8 bits (EVENT_TMR[23:16])
EVENT_TMR1 – the next most significant 8 bits (EVENT_TMR[15:8])
EVENT_TMR2 – the least significant 8 bits (EVENT_TMR[7:0])
EVENT_TMR0
0x0051
7
6
5
4
3
2
1
0
R
EVENT_TMR[23:16]
W
Reset
0
0
0
0
0
0
0
0
EVENT_TMR1
0x0052
7
6
5
4
3
2
1
0
R
W
EVENT_TMR[15:8]
Reset
0
0
0
0
0
0
0
0
EVENT_TMR2
0x0053
7
6
5
4
3
2
1
0
R
W
EVENT_TMR[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-23. Event Timer Registers
Table 6-31. EVENT_TMR Field Description
Description
Field
[23:0]
Event Timer — Holds the current value of the event timer counter.
EVENT_TMR • The hardware latches on a read of least significant byte
• The latched value is released on the read of the most significant byte
MC13234/MC13237 Reference Manual, Rev. 1.8
6-54
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.15 Time Stamp Registers (TIMESTAMP0, TIMESTAMP1, and
TIMESTAMP2)
The read-only Timestamp [23:0] Registers hold the latched event timer counter value (current time)
corresponding to the beginning of the last received RX packet. The value is latched at the SFD detect. The
24-bit timestamp value is composed of three registers:
•
•
•
TIMESTAMP0 — the most significant 8 bits (TIMESTAMP[23:16])
TIMESTAMP1 — the next most significant 8 bits (TIMESTAMP[15:8])
TIMESTAMP2 — the least significant 8 bits (TIMESTAMP[7:0])
TIMESTAMP0
0x0054
0x0054
7
6
5
4
3
2
1
0
R
TIMESTAMP[23:16]
W
Reset
0
0
0
0
0
0
0
0
TIMESTAMP1
0x0055
7
6
5
4
3
2
1
0
R
W
TIMESTAMP[15:8]
Reset
0
0
0
0
0
0
0
0
TIMESTAMP2
0x0056
7
6
5
4
3
2
1
0
R
W
TIMESTAMP[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-24. Time Stamp Registers
Table 6-32. TIMESTAMP Field Description
Description
Field
[23:0]
Time Stamp — Holds the latched value of the Event Timer current time corresponding to the beginning of
TIMESTAMP the just received RX packet, at SFD detect. Software should read only at idle state of sequence manager.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-55
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.16 Event Timer Comparator 3 Registers (T3CMP0, T3CMP1, and
T3CMP2)
The T3CMP[23:0] Registers hold the compare value used by Event Timer Comparator 3. The 24-bit
compare value is composed of three registers:
•
•
•
T3CMP0 – the most significant 8 bits (T3CMP[23:16])
T3CMP1 – the next most significant 8 bits (T3CMP[15:8])
T3CMP2 – the least significant 8 bits (T3CMP[7:0])
T3CMP0
0x0057
0x0058
0x0059
23
22
21
20
19
18
17
16
R
T3CMP[23:16]
W
Reset
1
1
1
1
1
1
1
1
T3CMP1
15
14
13
12
11
10
9
8
R
W
T3CMP[15:8]
Reset
1
1
1
1
1
1
1
1
T3CMP2
7
6
5
4
3
2
1
0
R
W
T3CMP[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-25. Event Timer Comparator 3 Registers
Table 6-33. T3CMP Field Description
Description
Field
[23:0]
T3CMP
Event Timer Comparator 3 — Event Timer 3 absolute time compare value. In addition to standard use as an
event timer, TC3 can also be used as a time-out timer for the receiver. This is controlled through bit TC3TMOUT
in Control Reg 2. Software must clear the TMR3CMP_EN bit prior to updating this register.
MC13234/MC13237 Reference Manual, Rev. 1.8
6-56
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.17 Time Comparator 2 Prime Registers (TC2_PRIME0 and
TC2_PRIME1)
The TC2_PRIME[15:0] Registers hold the 16-bit compare value used by Event Timer Comparator 2 for a
special sequence. The 16-bit compare value is composed of two registers:
•
•
TC2_PRIME0 – the most significant 8 bits (TC2_PRIME[15:8])
TC2_PRIME1 – the least significant 8 bits (TC2_PRIME[7:0])
TC2_PRIME0
0x005A
15
14
13
12
11
10
9
8
R
TC2_PRIME[15:8]
W
Reset
1
1
1
1
1
1
1
1
TC2_PRIME1
0x005B
7
6
5
4
3
2
1
0
R
W
TC2_PRIME[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-26. Time Comparator 2 Prime Registers
Table 6-34. TC2_PRIME Field Description
Description
Field
[15:0]
Event Timer Comparator 2 Prime — Event Timer 2 absolute time compare value (lower 16 bits only). Matches
TC2_PRIME the lower 16 bits of the Event Timer counter against the programmed value.
• Works in conjunction with TMRTRIGEN to initiate a particular transceiver sequence (XCVSEQ) at the matched
point.
• Software must clear the TMR2CMP_EN bit prior to updating this register.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-57
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.18 MAC Short Address Registers (MACSHORTADDRS0 and
MACSHORTADDRS1)
The MACSHORTADDRS[15:0] Registers hold the 16-bit MAC Short Address value used by the device
when Short Address Mode is used. The 16-bit address value is composed of two registers:
•
•
MACSHORTADDRS0 — the most significant 8 bits (MACSHORTADDRS[15:8])
MACSHORTADDRS1 — the least significant 8 bits (MACSHORTADDRS[7:0])
MACSHORTADDRS0
0x005C
7
6
5
4
3
2
1
0
R
MACSHORTADDRS[15:8]
W
Reset
1
1
1
1
1
1
1
1
MACSHORTADDRS1
0x005D
7
6
5
4
3
2
1
0
R
W
MACSHORTADDRS[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-27. MAC Short Address Registers
Table 6-35. MACSHORTADDRS Field Description
Description
Field
[15:0]
Mac Short Address — Value used as device MAC Short Address when that mode is enabled
MACSHORTADDRS
MC13234/MC13237 Reference Manual, Rev. 1.8
6-58
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.19 MAC Pan ID Registers (MACPANID0 and MACPANID1)
The MACPANID[15:0] Registers hold the 16-bit MAC PAN ID value used by the device. The 16-bit PAN
ID value is composed of two registers:
•
•
MACPANID0 – the most significant 8 bits (MACPANID[15:8])
MACPANID1 – the least significant 8 bits (MACPANID[7:0])
MACPANIDS0
0x005E
7
6
5
4
3
2
1
0
R
MACPANID[15:8]
W
Reset
1
1
1
1
1
1
1
1
MACPANID1
0x005F
7
6
5
4
3
2
1
0
R
W
MACPANID[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-28. MAC Pan ID Registers
Table 6-36. MACPANID Field Description
Description
Field
[15:0]
Mac Short Address — Value used as device PAN ID
MACPANID
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
6-59
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.20 Event Timer Comparator 1 Registers (T1CMP0, T1CMP1, and
T1CMP2)
The T1CMP[23:0] Registers hold the compare value used by Event Timer Comparator 1. The 24-bit
compare value is composed of three registers:
•
•
•
T1CMP0 – the most significant 8 bits (T1CMP[23:16])
T1CMP1 – the next most significant 8 bits (T1CMP[15:8])
T1CMP2 – the least significant 8 bits (T1CMP[7:0])
T1CMP0
0x1840
0x1841
0x1842
7
6
5
4
3
2
1
0
R
T1CMP[23:16]
W
Reset
1
1
1
1
1
1
1
1
T1CMP1
7
6
5
4
3
2
1
0
R
W
T1CMP[15:8]
Reset
1
1
1
1
1
1
1
1
T1CMP2
7
6
5
4
3
2
1
0
R
W
T1CMP[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-29. Event Timer Comparator 1 Registers
Table 6-37. T1CMP Field Description
Description
Field
[23:0]
Event Timer Comparator 1 — Event Timer 1 absolute time compare value. Software must clear the
T1CMP
TMR1CMP_EN bit prior to updating this register.
MC13234/MC13237 Reference Manual, Rev. 1.8
6-60
Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.21 Event Timer Comparator 2 Registers (T2CMP0, T2CMP1, and
T2CMP2)
The T2CMP[23:0] Registers hold the compare value used by Event Timer Comparator 2. The 24-bit
compare value is composed of three registers:
•
•
•
T2CMP0 – the most significant 8 bits (T2CMP[23:16])
T2CMP1 – the next most significant 8 bits (T2CMP[15:8])
T2CMP2 – the least significant 8 bits (T2CMP[7:0])
T2CMP0
0x1843
0x1844
0x1845
23
22
21
20
19
18
17
16
R
T2CMP[23:16]
W
Reset
1
1
1
1
1
1
1
1
T2CMP1
15
14
13
12
11
10
9
8
R
W
T2CMP[15:0]
Reset
1
1
1
1
1
1
1
1
T2CMP2
7
6
5
4
3
2
1
0
R
W
T2CMP[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-30. Event Timer Comparator 2 Registers
Table 6-38. T2CMP Field Description
Description
Field
[23:0]
Event Timer Comparator 2 — Event Timer 2 absolute time compare value. Software must clear the
T2CMP
TMR2CMP_EN bit prior to updating this register.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.22 Event Timer Comparator 4 Registers (T4CMP0, T4CMP1, and
T4CMP2)
The T4CMP[23:0] Registers hold the compare value used by Event Timer Comparator 4. The 24-bit
compare value is composed of three registers:
•
•
•
T4CMP0 – the most significant 8 bits (T4CMP[23:16])
T4CMP1 – the next most significant 8 bits (T4CMP[15:8])
T4CMP2 – the least significant 8 bits (T4CMP[7:0])
T4CMP0
0x1846
0x1847
0x1848
23
22
21
20
19
18
17
16
R
T4CMP[23:16]
W
Reset
1
1
1
1
1
1
1
1
T4CMP1
15
14
13
12
11
10
9
8
R
W
T4CMP[15:8]
Reset
1
1
1
1
1
1
1
1
T4CMP2
7
6
5
4
3
2
1
0
R
W
T4CMP[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-31. Event Timer Comparator 4 Registers
Table 6-39. T4CMP Field Description
Description
Field
[23:0]
Event Timer Comparator 4 — Event Timer 4 absolute time compare value. Software must clear the
T4CMP
TMR4CMP_EN bit prior to updating this register.
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Freescale Semiconductor
IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.23 LO1 FracN Numerator Value Registers (LO1_FRAC0 and
LO1_FRAC1)
The LO1_FRAC[15:0] Registers hold the 16-bit LO1 FracN Numerator value used by the VCO
synthesizer. The LO1_FRAC value is composed of two registers:
•
•
LO1_FRAC0 – the most significant 8 bits (LO1_FRAC[15:8])
LO1_FRAC1 – the least significant 8 bits (LO1_FRAC[7:0])
To calculate the FracN Numerator, see Section 6.6, “VCO Frequency Synthesizer (Channel Frequency)”.
LO1_FRAC0
0x1849
7
6
5
4
3
2
1
0
R
W
LO1_FRAC[15:8]
Reset
0
0
1
0
1
0
0
0
LO1_FRAC1
0x184A
7
6
5
4
3
2
1
0
R
W
LO1_FRAC[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-32. LO1 FracN Numerator Value Registers
Table 6-40. LO1_FRAC Field Description
Description
Field
LO1_FRAC LO1 FracN Divide Value — used by the VCO synthesizer. LO1 FREQUENCY = 32e6 * (L01_INT + 1 +
(LO1_FRAC / 65536)). Set frequency on channel
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.24 LO1 Integer Register (LO1_INT)
The LO1_INT[7:0] Register hold the 8-bit LO1 Integer divide value used by the VCO synthesizer.
To calculate the LO1 Integer, see Section 6.6, “VCO Frequency Synthesizer (Channel Frequency)”.
LO1_INT
0x184B
7
6
5
4
3
2
1
0
R
W
LO1_INT
Reset
0
1
0
0
1
0
1
0
= Unimplemented or Reserved
Figure 6-33. LO1 Integer Register
Table 6-41. LO1_INT Field Description
Description
Field
[7:0]
LO1 Integer Divide Value — used by the VCO synthesizer. LO1 FREQUENCY = 32e6 * (L01_INT + 1 +
LO1IDIV
(LO1_FRAC / 65536)). Set frequency on channel
6.13.25 Power Amplifier (PA) Power Control Register (PA_PWR_CNTL)
The PA_PWR_CNTL Register is one of four registers that sets the RF PA power out during a transmission.
The additional three registers are accessed through the Transceiver Indirect Access Registers (see
Section 6.13.33, “Transceiver Indirect Access Registers (INDEX and DATA)”). The indirect access
addresses are 0x410, 0x411, and 0x4020).
NOTE
Use Freescale provided software utilities for setting TX RF output power.
The utilities provide 15 power steps where the typical output power is
shown in Table 6-42.
Table 6-42.
Power Step
(Dec)
Typical Output Power
(dBm)
0
1
2
3
4
5
6
-30
-29
-25
-23
-21
-19
-16
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-42.
Power Step
(Dec)
Typical Output Power
(dBm)
7
-14
-13
-9
8
9
10
11
12
13
14
-7
-4
-2
0
+1
PA_PWR_CNTL
0x184C
7
6
5
4
3
2
1
0
R
W
Reserved
Reset
0
0
1
1
0
1
0
0
= Unimplemented or Reserved
Figure 6-34. Power Amplifier (PA) Power Control Register
Table 6-43. PA_PWR_CNTL Field Descriptions
Description
Field
7:0
Reserved — use default value
Reserved
6.13.26 MAC Long Address Registers (MACLONGADDRS0 –
MACLONGADDRS7)
The MAC Long Address Registers supply the 64-bit IEEE 802.15.4 Long Device Address
MACLONGADDRS [63:0] :
•
•
•
•
•
•
Register MACLONGADDRS0 – field MACLONGADDRS [63:56] most significant byte
Register MACLONGADDRS1 – field MACLONGADDRS [55:48]
Register MACLONGADDRS2 – field MACLONGADDRS [47:40]
Register MACLONGADDRS3 – field MACLONGADDRS [39:32]
Register MACLONGADDRS4 – field MACLONGADDRS [31:24]
Register MACLONGADDRS5 – field MACLONGADDRS [23:16]
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
•
•
Register MACLONGADDRS6 – field MACLONGADDRS [15:8]
Register MACLONGADDRS7 – field MACLONGADDRS [7:0] least significant byte
7
6
5
4
3
2
1
0
0x184D
0x184E
0x184F
0x1850
0x1851
0x1852
0x1853
0x1854
R/W
MACLONGADDRS[63:56]
MACLONGADDRS[55:48]
MACLONGADDRS[47:40]
MACLONGADDRS[39:32]
MACLONGADDRS[31:24]
MACLONGADDRS[23:16]
MACSHORTADDRS[15:8]
MACLONGADDRS[7:0]
Reset
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-35. MAC Long Address Registers
Table 6-44. MACLONGADDRS Field Description
Description
Field
MACLONG- Mac Long Address — Device 64-bit IEEE 802.15.4 Long Address.
ADDRS
[63:0]
6.13.27 Max Frame Length Register (MAXFRAMELENGTH)
The MAXFRAMELENGTH Register provides the programmed maximum byte count.
MAXFRAMELENGTH
0x1855
7
6
5
4
3
2
1
0
R
W
MAXFRAMELENGTH[7:0]
Reset
0
1
1
1
1
1
1
1
Figure 6-36. Max Frame Length Register
Table 6-45. MAXFRAMELENGTH Field Description
Description
Field
maxFrameLength Maximum Frame Length Accepted — Used by frame filtering to limit maximum byte count of
[7:0] frames to be received.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.28 Receive Frame Filter (RX_FRAME_FILTER)
Within the receive frame 2-byte Frame Control field, there is a 3-bit Frame Type subfield. Frame filtering
allows rejection of the incoming receive frame based on the value of this subfield. Frame type as defined
by the Frame Type subfield are listed in
Table 6-46. IEEE 802.15.4 Frame Type Subfield
Frame Type [2:0]
Frame Type Designation
Beacon
000
001
Data
010
Acknowledgement
MAC command
Reserved
011
100–111
Control bits in the RX_FRAME_FILTER Register set the accept/reject option
The receive will only complete if the following conditions are met:
1. Destination address:
a) If PAN ID is included other than the broadcast, it must match the macPANID else the PAN ID
must be the broadcast value (0xFFFF)
b) If a short destination address is include in the frame, it must match the macShortAddress field
else the broadcast address (0xFFFF)
c) If a long destination address is include in the frame, it must match the aExtendedAddress.field
d) If only source addressing fields are included in a Data or MAC command frame, the frame shall
be accepted only if the device is a PAN coordinator (PANCOORD = 1) and the source PAN
identifier matches macPANId.
2. Illegal Frame types are rejected, unless the NS_FT field is set.
3. Beacon frames are accepted under the following conditions
a) Beacon frames enable
b) The source PAN ID matches macPANID or it equals 0xFFFF
c) Length >= 9
d) The destination address mode is 0 (no destination address)
e) The source address mode is 2 or 3 (i.e. a source address is included)
4. Data frames are accepted under the following conditions:
a) Data frames are enabled
b) Length >= 9
c) If the device is a PAN coordinator (PANCOORD bit) and the source PAN identifier matches
macPANId. This means that if the destination address is not present, the frame will be accepted
only if the PANCOORD = 1 and the PANID in the source address field is equal to the receiving
device macPANID. If the device is NOT a PAN coordinator, the destination address mode must
be 2 or 3, and destination address-matching rules apply.
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
5. Acknowledgement Frames are accepted under the following conditions:
a) Acknowledge Frames are enabled
b) Length == 5
c) Sequence number has to match.
6. Command Frames are accepted under the following conditions:
a) Command Frames are enabled
b) Length >= 9
c) Source or Destination Address are included, else it must be a coordinator (PANCOORD = 1)
in which case the PANID must equal macPANID. If the device is NOT a PAN coordinator, the
destination address mode must be 2 or 3, and destination address-matching rules apply.
Packet Rejection:
If a frame is rejected, the transceiver will start searching for a new frame after the rejected frame has been
received.
RX_FRAME_FILTER
0x1856
7
6
5
4
3
2
1
0
R
W
NS_FT
CMD_FT
ACK_FT
1
DATA_FT BEACON_FT
Reset
0
0
0
0
1
1
1
= Unimplemented or Reserved
Figure 6-37. Receive Frame Filter Register
Table 6-47. RX_FRAME_FILTER Field Description
Description
Field
NS_FT
Not Specified FT — Defines whether non-specified frames (4,5,6, and 7) are rejected or not
0 Reject
1 Accept
CMD_FT
MAC Command Frame Type — Defines whether MAC command frames are accepted or not. MAC
command frames have frame type = 011.
0 Reject
1 Accept
ACK_FT
Acknowledge Frame Type — Defines whether Ack frames are accepted or not. MAC acknowledge
frames have frame type = 010.
0 Reject
1 Accept
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-47. RX_FRAME_FILTER Field Description (continued)
Field
Description
DATA_FT
Data Frame Type — Defines whether Data frames are accepted or not. MAC data frames have frame
type = 001.
0 Reject
1 Accept
BEACON_FT
Beacon Frame Type — Defines whether Beacon frames are accepted or not. MAC beacon frames
have frame type = 000.
0 Reject
1 Accept
6.13.29 MAC Frame Version Compatibility and Timer Prescale Register
(FMR_REV_TMR)
The FMR_REV_TMR register provides the Event Timer prescaler control field as well as the Frame
Version select which determines which version of IEEE 802.15.4 Standard frames that filtering will allow.
FMR_REV_TMR
0x1857
7
6
5
4
3
2
1
0
R
W
0
0
0
TMR_PRES TMR_PRES TMR_PRES
FRM_VER
CALE2
CALE1
CALE0
Reset
0
1
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-38. MAC Frame Version Compatibility and Timer Prescale Register
Table 6-48. FMR_REV_TMR Field Descriptions
Description
Field
[2:0]
Timer Prescaler Select — sets Event Timer pre scale ratio. See Section Table 6-7., “Event Timer
TMR_PRESCALE Prescaler Settings”
FRM_VER
[1:0]
802.15.4 Frame Version Selection
00 All Frame Versions accepted (0,1,2 and 3)
01 Only accept FrameVersion 0 packets (2003 compliant)
10 Only accept FrameVersion 1 packets (2006 compliant)
11 Accept FrameVersion 0 and 1 packets, reject all others
Note: Frames received with FrameVersion 2 or 3 will be treated identically to FrameVersion 1, with
respect to parsing of the Auxiliary Security Header. Other than this Header, all 4 frame versions will be
treated identically
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.30 CCA Energy Threshold (CCA_THRESHOLD)
The CCA_THRESHOLD Register provides the threshold value for comparison during a CCA cycle. See
Section 6.5.1.3, “Reported Energy Values”
CCA_THRESHOLD
0x1858
7
6
5
4
3
2
1
0
R
W
CCA_THRESHOLD[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-39. CCA Energy Threshold
Table 6-49. CCA_THRESHOLD Field Description
Description
Field
[7:0]
CCA Energy Threshold Detection— Threshold value for the Clear Channel Assessment in
CCA_THRESHOLD
dB-linear format
6.13.31 CCA Power Compensation (CCA_OFFSET_CMP)
The CCA_OFFSET_CMP Register provides the offset value used to adjust/compensate the CCA and LQI
calculation. See Section 6.5.1.3, “Reported Energy Values”
CCA_OFFSET_CMP
0x1859
7
6
5
4
3
2
1
0
R
W
CCA_OFFSET_CMP[7:0]
Reset
1
0
0
0
1
1
0
1
= Unimplemented or Reserved
Figure 6-40. CCA Power Compensation
Table 6-50. CCA_OFFSET_CMP Field description
Description
Field
[7:0]
CCA Power Compensation — Offset added to the calculated RSSI.
CCA_OFFSET_CMP
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.32 Finite State Machine Register (FSM)
The FSM Register reports the state of the Sequence Manager Finite State Machine and can be used to
monitor a sequence.
FSM
0x185A
7
6
5
4
3
2
1
0
R
W
0
0
FSM[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-41. Finite State Machine Register
Table 6-51. FSM Field Description
Description
Field
[5:0]
FSM
Finite State Machine — This register reflects the sequence manager internal state
Table 6-52. FSM State Codes
FSM[5:0]
State
00
IDLE
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX WARMUP
RX
RX
RX-TO-TX TRANSITION
30
CCA
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
Table 6-52. FSM State Codes
FSM[5:0]
State
31
32
33
34
CCA
WAIT BETWEEN 1ST & 2ND CCA
CCA
RX-TO-TX TRANSITION
01
02
03
04
05
06
07
08
09
10
14
18
1C
1D
1E
1F
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX WARMUP
TX
TX
CCA-TO-TX TRANSITION
TX WARMDOWN
TX WARMDOWN
TX WARMDOWN
TX-TO-RX TRANSITION
3F
TRANSPARENT MODE
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IEEE 802.15.4 Transceiver (including 802.15.4 Module)
6.13.33 Transceiver Indirect Access Registers (INDEX and DATA)
The transceiver Indirect Access Registers are normally reserved and are used to access a block of
transceiver test radio functions. The only times this interface is used for application purposes are:
•
•
•
Pseudo-random number generation
Setting transmit power
Controlling the analog voltage regulator for low power operation
NOTE
Refer to Section 3.10, “Transceiver Indirect Access Register Application
Functions” for information on using these functions.
The interface is composed of two registers:
•
INDEX – writing this register provides an address to an internal register block that is used for read
or write of the selected register
•
DATA – writing data to this register causes a write of the same data to the internal register that is
addressed by the INDEX register. A read access of the DATA register returns the contents of the
internal register that is addressed by the INDEX register.
INDEX
0x185B
7
6
5
4
3
2
1
0
R
INDEX[7:0]
W
Reset
0
0
0
0
0
0
0
0
DATA
0x185C
7
6
5
4
3
2
1
0
R
W
DATA[7:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-42. Transceiver Indirect Access Registers
Table 6-53. Indirect Access Register Field Descriptions
Description
Field
INDEX[7:0] Register Index — provides a 7-bit register address index (Bit[6:0]) and an auto-increment control Bit 7. If Bit 7
is set, each access to the DATA register increments the index in the Bit [6:0] field.
DATA[7:0] Data — writing this register causes a write of the same data to the indirect register addressed by the INDEX
register. A read of this register accesses the data from the indirect register addressed by the INDEX register.
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Freescale Semiconductor
Chapter 7
Advanced Security Module (ASM)
7.1
Introduction
The Advanced Security Module (ASM) is a hardware engine that encrypts using the 128-bit version of the
Advanced Encryption Standard (AES). It can perform Counter (CTR), Cipher Block Chaining (CBC), and
plain AES mode encryption. The combination of CTR and CBC modes of encryption is known as Counter
with CBC-MAC (CCM) mode encryption. CCM is a generic authenticate and encrypt block cipher mode.
CCM is only defined for use with 128-bit block ciphers, such as AES.
NOTE
•
The encryption structures are briefly described in the modes below,
however, users are directed to external resources for an in-depth
understanding of the AES standard
•
•
An in-depth definition of CCM mode encryption is documented in the
NIST publication SP800-38C.
The IEEE 802.15.4 Standard and the ZigBee specification deal only
with encryption, not decryption. The ASM does not support all modes
of decryption. The user is directed to the referenced standards and
specifications for more information.
•
The ASM block supports simple AES Mode encryption, but does NOT
support simple AES decryption.
7.1.1
Features
The ASM has the following features:
•
•
•
•
•
•
CTR encryption in 11 bus clock cycles.
CBC encryption in 11 bus clock cycles
AES encryption in 11 bus clock cycles.
Encrypts 128 bits as a unit.
All 128-bit data values accessed through a single block of 16 8-bit registers
All accesses are on an 8-bit basis.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
7-1
Advanced Security Module (ASM)
7.2
Block Diagram
A simple block diagram of the ASM module is shown in Figure 7-1.
Control
Self-Test
Encryption
SM
Register
Block
SM
ASM Block
128 Bits
AES
Encryption
Engine
Figure 7-1. ASM Module Block Diagram
7.3
Functional Overview
The ASM block consists of an iterative encryption engine that is sequenced by an encryption state machine
(SM) state machine or a self-test state machine. The block is controlled by mode bits that determine the
encryption algorithm and data is exchanged between the MCU and the ASM Block via a single 128-bit
buffer in the register block. Supporting the actual encryption engine is a register block that consists of two
control/status registers and a bidirectional 16-byte data interface to provide data and constants. The ASM
is clocked by the bus clock which always 1/2 the CPU clock rate (typically bus clock is 16 MHz).
7.3.1
Control Flow
The encryption or self-test process is sequenced by the appropriate SM. The general flow for the different
encryption modes is:
1. Set desired encryption mode
2. Load required data components
3. Initiate the sequence
4. Wait for sequence completion
5. Read the resultant data component
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Freescale Semiconductor
Advanced Security Module (ASM)
7.3.1.1
Setting Encryption Mode
The encryption mode is based on the control bits listed in Figure 7-1. The defined mode of encryption is
determined by setting the appropriate bit. Use of these bits during the encryption process is described in
sub-sections of Section 7.4.
Table 7-1. ASM Mode Control Bits
Bit
Description
SELFTEST Enables self test
CTR
CBC
AES
Enables Counter Mode encryption
Enables CBC-MAC Mode encryption/generation
Enables simple AES Mode encryption
7.3.1.2
Using the 128-Bit Data Interface
All required input data components and encryption results use a single 128-bit data interface buffer (16
byte-wide registers). The registers are described in Section 7.5.3, “AES 128 Data Registers (ASMDATA0
- ASMDATAF)” as to their organization and addresses. The use of the registers is controlled by the
following fields:
•
CLEAR Bit, AES Control Register 1 - writing a “1” to this bit clears all memory in the ASM, and
the bit is self-clearing.
•
Load_MAC Bit, AES Control Register 1 - writing a “1” to this bit loads the contents of the 128-bit
data buffer into the ASM as the component selected by the “Data Register Type Select” field, and
the bit is self-clearing.
•
Data Register Type Select Field [2:0], AES Control Register 2 - this 3-bit field selects the target
encryption component for a data write to the ASM (by writing a “1” to Load_MAC Bit), and also
selects the encryption result component for an ASM data read. Table 7-2 lists use of data buffer
versus the select field.
Table 7-2. Data Buffer Use vs. Data_Reg_ype_Sel Field
Data_Reg_
Type_Sel[2:0]
Type
Mode
Description
0
1
2
3
4
5
Key
Data
Write to ASM Data buffer holds “Key” to be written for encryption
Write to ASM Data buffer holds “Data” to be written for encryption
Write to ASM Data buffer holds “Counter” to be written for encryption
CTR
CTR Result
CBC Result
MAC
Read ASM
Read ASM
Write ASM
Reading buffer returns counter mode encryption result
Reading buffer returns CBC-MAC mode encryption result
Data buffer holds “Start Value” to be written for CBC-MAC
encryption
6
7
AES Result
N.A.
Read ASM
N.A.
Reading buffer returns AES mode encryption result
Reserved (not used)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
7-3
Advanced Security Module (ASM)
For a write operation, the 128-bit buffer must first be loaded, the Data Register Type Select set, and finally
the Load_MAC Bit written. For a read operation, the Data Register Type Select is first set, and a read of
the 16 buffer registers yields the128-bit selected result.
7.3.1.3
Initiating the Sequence and Getting Sequence Results
After the desired encryption mode is selected and the required encryption components are loaded, the
sequence is initiated by writing the START Bit, AES Control Register 1. Other than self-test, all encryption
sequences require 11 bus clock cycles. Completion of the encryption is signified by setting of the
IRQ_FLAG status bit, AES Control Register 1.
The status flag can be enabled to generate an interrupt request or can be simply monitored by the CPU.
The encryption results are read as described in Section 7.3.1.2. The ASM has been assigned Interrupt
Vector No. 8.
7.3.2
Module Initialization
The ASM is unique in that it has a self-test mode, and it exits system reset disabled until the self-test mode
has been run. After the self-test has been run and passes, the ASM is available for normal use. See
Section 7.4.1 the description for self-test.
7.4
ASM Modes of Operation
The ASM performs Counter (CTR), Cipher Block Chaining (CBC), Counter with CBC-MAC (CCM), and
plain AES encryption modes as well as self-test.
NOTE
In the following example flows for executing an encryption cycle:
•
•
Writing a Key, Counter, MAC/Start, or Data value to the ASM implies
a three step process; 1) Write the proper code to the Data_Reg_Type_Sel
field, 2) Write the 128-bit value to the data interface registers, and 3) the
Write Load_MAC bit to load the value from the buffer into the ASM.
Reading an encryption result from the ASM implies a two step process;
1) Write the proper code to the Data_Reg_Type_Sel field, 2) Read the
128-bit return value from the data interface registers
7.4.1
Self-Test
As described, the ASM exits reset disabled and remains disabled until the self-test is run and is passed.
Typical usage would require that this test be run only once after reset. This test can re-run at any time it
becomes necessary to verify the operation of the encryption engine.
Self-test is run by:
1. Initialize - write SELFTEST bit to “1”
2. Start test - write START bit to “1” (bit is self-clearing)
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3. Self-test runs - requires 3330 clocks to complete
4. Test completes:
— Passes test: TSTPAS status flag is set and IRQ_FLAG status flag is set. An IRQ is asserted if
it is enabled. The ASM is ready for normal use.
— Fails test: TSTPAS remains low (clear) and IRQ_FLAG status flag is set. An IRQ is asserted
if it is enabled. The ASM module is disabled and all outputs will be held to constant “0”. The
self-test mode can be re-run.
NOTE
•
•
Be sure to clear the SELFTEST bit before trying any other mode.
It is also good practice to clear the ASM registers by writing to the
CLEAR Bit of Control Register 1 immediately after self-test so that the
ASM module is ready for any encryption mode.
7.4.2
Counter (CTR) Mode
Counter mode encryption (CTR) is done by using the AES engine as shown in the functional block
diagram of Figure 7-2. Three 128-bit variables consisting of a Key, plain Text, and Counter values are each
written to the encryption engine using the data buffer interface. The encryption cycle is initiated and
requires 11 bus clocks to complete. The IRQ_FLAG status flag is set and an IRQ is asserted if it is enabled.
The encrypted data can be then read from the data register.
Plain Text data/Encrypted data
Key
Encrypted data/Plan text data
AES
Encryption
Engine
Encrypted Counter
Counter
Figure 7-2. CTR Mode Functional Block Diagram
Decryption is possible for CTR mode and uses the same AES encryption engine configuration. The Key
and Counter values remain the same, however, data to be decrypted is written to the data register. The
decrypted result can be read from the data register similar to the encryption cycle.
A simple flow for CTR encryption consists of:
1. Write the Key value to the ASM.
2. Set the CTR bit in Control Register 1 - all other mode control bits must be clear
3. Write the Counter value to the ASM.
4. Write the plain Text value to the ASM.
5. Set the START bit in Control Register 1- this bit is a self clearing.
6. The Counter encryption runs to completion (11 bus clock cycles) -
— The IRQ_FLAG status bit, AES Control Register 1 is set - an IRQ is generated is enabled.
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— The software may poll the status flag or wait for the interrupt
7. Read the encrypted CTR Result from the ASM
Steps 3-7 are repeated for each additional 128-bits plain text block. The Key value is re-used, and the
Counter and plain Text values are new for each block. The IRQ_STATUS flag must be cleared after each
iteration.
The decryption process is the same with the exception that the previously encoded 128-bit block is loaded
in Step 4 and the results of Step 7 are now the plain text decrypted block.
7.4.3
Cipher Block Chaining (CBC) Mode
Cipher block chaining message authentication code (CBC or CBC-MAC) generation is done by using the
AES engine as shown in the functional block diagram of Figure 7-3. Two 128-bit variables consisting of
a Key and plain Text values are each written to the encryption engine using the data buffer interface. The
encryption cycle is initiated and requires 11 bus clocks to complete. The IRQ_FLAG status flag is set and
an IRQ is asserted if it is enabled. Additional blocks are encrypted as they are chained together. The final
encrypted MAC result can be then read from the data register.
Key
CBC MAC value
AES
Encryption
Engine
Plain text data
Figure 7-3. CBC Mode Functional Block Diagram
A simple flow for CBC-MAC encryption consists of:
1. Clear MAC accumulator as required - see NOTE below. This is required after self-test.
2. Write the Key value to the ASM.
3. Set the CBC bit in Control Register 1 - all other mode control bits must be clear
4. Write the plain Text value to the ASM.
5. Set the START bit in Control Register 1- this bit is a self clearing.
6. The CBC encryption runs to completion (11 bus clock cycles) -
— The IRQ_FLAG status bit, AES Control Register 1 is set - an IRQ is generated is enabled.
— The software may poll the status flag or wait for the interrupt
7. Repeat Steps 4-6 for each additional 128-bit plain text block - the Key value is re-used, and the
plain Text value is new for each block. The IRQ_STATUS flag must be cleared before each
iteration. This sequence accomplishes the block chaining.
8. Read the encrypted 128-bit MAC (authentication code) Result (Data_Reg_Type_Sel field to 0x4)
from the ASM
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NOTE
•
•
The MAC accumulator must be cleared to prepare for a new encryption
payload. Writing a 1 to the CLEAR bit will set the MAC accumulator
back to all zeroes. The clear bit is self clearing.
If for some reason the software needs to continue a MAC calculation
from a previously saved value, the MAC accumulator can be pre-loaded
with a initial value. Program Control register2[7:5] to 3’b101 now the
value that must be loaded into the accumulator is written to data
registers and then a 1 is written to the load_mac bit. The load_mac bit is
self clearing.
7.4.4
Counter With CBC-MAC (CCM) Mode
CCM mode is the combination of using CTR mode for protecting the privacy of data, and using CBC mode
to generate a MAC to protect the data from unauthorized modifications. In this mode both CTR and CBC
mode bits are set and the ASM first performs a CTR encryption followed by a CBC conversion. The results
of CTR and CBC conversion are stored in separate registers which can be read separately from another.
A simple flow for CCM encryption consists of:
1. Clear MAC accumulator as required - see NOTE below. This is required after self-test.
2. Write the Key value to the ASM.
3. Set the CTR and CBC bits in Control Register 1 - all other mode control bits must be clear
4. Write the Counter value to the ASM.
5. Write the plain Text value to the ASM.
6. Set the START bit in Control Register 1- this bit is a self clearing.
7. The CTR/CBC-MAC encryption runs to completion -
— The IRQ_FLAG status bit, AES Control Register 1 is set - an IRQ is generated is enabled.
— The software may poll the status flag or wait for the interrupt
8. Read the encrypted CTR Result from the ASM
9. Clear the IRQ_FLAG status bit.
10. Repeat Steps 4-9 for each additional 128-bit plain text block - the Key value is re-used, and the
Counter and plain Text values are new for each block.
11. Read the encrypted 128-bit MAC (authentication code) Result (Data_Reg_Type_Sel field to 0x4)
from the ASM
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7.4.5
Plain AES Mode
AES mode is done by using the AES engine as shown in the functional block diagram of Figure 7-4. This
mode is the most simple method of encryption in that there is no feedback of results back to modify the
input in any form. Two 128-bit variables consisting of a Key and plain Text, values are each written to the
encryption engine using the data buffer interface. The encryption cycle is initiated and requires 11 bus
clocks to complete. The IRQ_FLAG status flag is set and an IRQ is asserted if it is enabled. The encrypted
data can be then read from the data register.
Data
Plain text data
AES
AES
Encryption
Engine
Text_out
Key
Figure 7-4. Plain AES Mode Functional Block Diagram
A simple flow for AES encryption consists of:
1. Write the Key value to the ASM.
2. Set the AES bit in Control Register 1 - all other mode control bits must be clear
3. Write the plain Text value to the ASM.
4. Set the START bit in Control Register 1- this bit is a self clearing.
5. The AES encryption runs to completion (11 bus clock cycles) -
— The IRQ_FLAG status bit, AES Control Register 1 is set - an IRQ is generated is enabled.
— The software may poll the status flag or wait for the interrupt
6. Read the encrypted AES Result from the ASM
Steps 3-6 are repeated for each additional 128-bit plain text block. The Key value is re-used, and the plain
Text value is new for each block. The IRQ_STATUS flag must be cleared after each iteration.
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7.5
ASM Register Definition
AES128 register block consists of two control/status registers and a 16-byte block of data registers for
128-bit data values. These are described below. The ASM registers are all located in the Direct-Page
Register Map.
7.5.1
AES 128 Control 1 Register (CONTROL1)
Control Register 1 contains various control bits for the ASM.
CONTROL1
0x0020
7
6
5
4
3
2
1
0
R
W
CLEAR
START
SELFTST
CTR
CBC
AES
LOAD_MAC AES_MSK
Reset
0
0
0
0
0
0
0
0
self clear
yes
yes
no
no
no
no
yes
no
= Unimplemented or Reserved
Figure 7-5. AES Address Register CONTROL1
Table 7-3. AES128 Field Descriptions
Description
Field
7
Clear ASM — Write 1 to this bit to clear all memory in ASM. Writing a 0 does nothing; the bit is self-clearing
Start — Write 1 to start any encryption or self-test sequence. Writing a 0 does nothing; the bit is self-clearing
Self-Test Mode — This bit enables self-test mode. Sequence is initiated by writing START bit.
CLEAR
6
START
5
SELFTST 1 = Self-test mode enabled
0 = Self-test mode not enabled
4
Counter Mode — This bit enables Counter encryption mode. Sequence is initiated by writing START bit.
CTR
1 = Counter mode encryption enabled
0 = Counter mode encryption not enabled
3
CBC
CBC Mode — This bit enables CBC-MAC encryption mode. Sequence is initiated by writing START bit
1 = CBC-MAC generation enabled.
0 = CBC-MAC generation not enabled
2
AES
AES Mode — This bit enables simple AES encryption mode. Sequence is initiated by writing START bit.
1 = AES mode encryption enabled
0 = AES mode encryption not enabled
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Table 7-3. AES128 Field Descriptions (continued)
Description
Field
1
Load ASM Data — Writing this bit to “1” loads the contents of the 128-bit data buffer into the destination selected
Load_Mac by the Data_Reg_Type_Select[2:0] field. See Section 7.3.1.2, “Using the 128-Bit Data Interface”. Writing a “0”
does nothing; the bit is self-clearing
0
AES128 Interrupt Mask — This bit enables generation of an ASM interrupt request if the IRQ_FLAG is set upon
AES_MSK completion of an ASM operation
0 = IRQ enabled
1 = IRQ disabled
7.5.2
AES 128 Control Register 2 (CONTROL2)
Control Register 2 contains the data register type select field and status flags for the ASM
CONTROL2
0x0021
7
6
5
4
3
2
1
0
R
W
0
0
0
DATA_REG_TYPE_SELECT
IRQ_FLAG
0
TSTPAS
Reset
0
0
0
0
0
0
0
Figure 7-6. AES Control 2 Register
Table 7-4. AES Control 2 Field Descriptions
Description
Field
7:5
Data Register Type Select — This register selects the destination type of data to be written or the
DATA_REG_
source of read data from the 16x8 Data register field. For coding see Section 7.3.1.2, “Using the
TYPE_SELECT 128-Bit Data Interface” and Table 7-2.
[2:0]
2
ASM Completion Status Flag — A 1 indicates the completion of a ASM operation (self-test or
IRQ_FLAG
encryption cycle). After it set, the status must be cleared by writing a 1
1
Self Test Pass — This bit is set to 1 upon correct completion of the self test. If self-test fails then
the module is not usable and the outputs will be set to all 0. The default state for this bit is 0. The
software must initiate a self-test before the module can be used.
1 = Self-test has passed
TSTPAS
0 = Self-test has failed
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7.5.3
AES 128 Data Registers (ASMDATA0 - ASMDATAF)
The 16x8-bit AES Data registers (128 bits) block serve as the interface between the ASM’s internal
memory segments and the MCU. The destination or source of the data in these registers is controlled
through the Data_Reg_Type_Select field in AES Control 2 Register. See Section 7.3.1.2, “Using the
128-Bit Data Interface”. The maps is as follows:
Table 7-5. AES Data Registers
Register
Field Data
ASMDATA_0
[127:120] most significant
byte
ASMDATA_1
ASMDATA_2
ASMDATA_3
ASMDATA_4
ASMDATA_5
ASMDATA_6
ASMDATA_7
ASMDATA_8
ASMDATA_9
ASMDATA_A
ASMDATA_B
ASMDATA_C
ASMDATA_D
ASMDATA_E
ASMDATA_F
[119:112]
[111:104]
[103:96]
[95:88]
[87:80]
[79:72]
[71:64]
[63:56]
[55:48]
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0] least significant byte
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ADDRESS
7
6
5
4
3
2
1
0
0x0022
DATA[127:120]
DATA[119:112]
DATA[111:104]
DATA[103:96]
DATA[95:88]
DATA[87:80]
DATA[79:72]
DATA[70:64]
DATA[63:56]
DATA[55:48]
DATA[47:40]
DATA[39:32]
DATA[31:24]
DATA[23:16]
DATA[15:8]
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
0x0030
0x0031
DATA[7:0]
Reset
R/W
0
0
0
0
0
0
0
0
Figure 7-7. AES 128 Data Registers [Data_0:Data_F]
Table 7-6. AES 128 Data Registers Field Description
Description
Field
DATA
AES 128 Data — 128-bit AES data interface.
[127:0]
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Chapter 8
CPU
8.1
Introduction
This chapter provides summary information about the registers, addressing modes, and instruction set of
the CPU which executes a superset of the 68HC08 instruction set. It has an 8-bit data bus, a 16-bit address
bus and a 2-stage instruction pipe that facilitates the overlapping of instruction fetching and execution. For
a more detailed description, see the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor
document order number HCS08RMV1/D
The HCS08 CPU is fully source and object code compatible with the M68HC08 CPU. Several instructions
and enhanced addressing modes were added to improve C compiler efficiency and to support a new
background debug system which replaces the monitor mode of earlier M68HC08 MCU.
8.1.1
Features
Features of the HCS08 CPU include:
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 and M68HC08 Families
64-KB CPU address space with banked memory management unit for greater than 64 KB
16-bit stack pointer (any size stack anywhere in 64-KB CPU address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
Memory-to-memory data move instructions with four address mode combinations
•
•
Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
•
•
Efficient bit manipulation instructions
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
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CPU
•
STOP and WAIT instructions to invoke low-power operating modes
8.1.2
Modes of Operation
The CPU is affected by the device mode of operation:
•
Run mode - normal operation. The CPU clock is set by the prescaler, programmed by the
RDIV[2:0] field of the System Oscillator Management and Control Register 1 (SOMC1)
•
LPRun modes - CPU clock is reduce to 32 MHz reference oscillator divided by 64 (500 kHz).
Reduced clock affects operation of time based peripherals.
•
•
•
•
Wait and Stop modes - the CPU clock is disabled and the CPU does not run.
Background Debug mode. The CPU is halted in BDM mode.
CPU can be suspended by flash (reset, BIST mode and system security word access)
DMA <> RAM accesses - DMA cycles work on a cycle steal basis and take bus clocks from the
CPU.
8.2
Programmer’s Model and CPU Register Definition
Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map.
7
0
ACCUMULATOR
16-BIT INDEX REGISTER H:X
INDEX REGISTER (HIGHIN) DEX REGISTER (LOWX)
A
H
15
8
7
0
0
0
SP
PC
STACK POINTER
15
PROGRAM COUNTER
7
CONDITION CODE REGIST
1 1 H I N Z C CCR
V
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVER
Figure 8-1. CPU Registers
8.2.1
Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
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memory using various addressing modes to specify the address where data from A will be stored. Reset
has no effect on the contents of the A accumulator.
8.2.2
Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, increment, decrement, be complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
8.2.3
Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
8.2.4
Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at $FFFE and $FFFF. The
vector stored there is the address of the first instruction that will be executed after exiting the reset state.
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CPU
8.2.5
Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, see the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1.
7
0
CONDITION CODE REGISTE
V
1
1 H
I
N Z C CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
Figure 8-2. Condition Code Register
Table 8-1. CCR Register Field Descriptions
Description
Field
7
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs.
V
The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1 Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
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Table 8-1. CCR Register Field Descriptions (continued)
Field
Description
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
8.3
Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, memory, status and
control registers, and input/output (I/O) ports share a single 64-Kbyte CPU address space. This
arrangement means that the same instructions that access variables in RAM can also be used to access I/O
and control registers or nonvolatile program space.
The HCS08 has larger than 64-Kbytes of memory so it has a memory management unit (MMU) to support
extended memory space. A PPAGE register is used to manage 16-Kbyte pages of memory which can be
accessed by the CPU through a 16-Kbyte window from 0x8000 through 0xBFFF. The CPU includes two
special instructions (CALL and RTC). CALL operates like the JSR instruction except that CALL saves the
current PPAGE value on the stack and provides a new PPAGE value for the destination. RTC works like
the RTS instruction except RTC restores the old PPAGE value in addition to the PC during the return from
the called routine. The MMU also includes a linear address pointer register and data access registers so
that the extended memory space operates as if it was a single linear block of memory.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
A summary of the addressing modes used by the core is given in Table 8-2.
Table 8-2. Addressing Mode Summary
Addressing Mode Abbreviation
Description
Operands (if any) are in CPU registers.
Inherent
INH
Operand is included in byte(s) following the opcode; 8-bit or 16-bit size implied by
context.
Immediate
IMM
The operand is fetched from a direct page address given by the byte following the
opcode.
Direct
DIR
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CPU
Table 8-2. Addressing Mode Summary (continued)
Addressing Mode Abbreviation
Description
The operand is fetched from an address given by the 2 bytes following the
opcode (most significant first).
Extended
EXT
Byte following the opcode is an 8-bit signed offset that is added to PC to obtain
the effective address.
Relative
REL
IX
Indexed, no offset
Effective address is contained in H:X.
Indexed, no offset,
post increment
Effective address is contained in H:X, which is incremented after the operand is
accessed.
IX+
Byte following the opcode is an 8-bit offset that is added to H:X to obtain the
effective address.
Indexed, 8-bit offset
IX1
IX1+
IX2
Indexed, 8-bit offset,
post increment
Same as above, but H:X is incremented after the operand is accessed.
The 2 bytes following the opcode form a 16-bit offset (most significant first) that is
added to H:X to obtain the effective address.
Indexed, 16 bit offset
Direct to direct
Used to move data inside direct page. First byte following the opcode is the
source address. Second byte is the destination address.
DD
Used to move an 8-bit constant to a direct page location. First byte following the
opcode is the constant. Second byte is the destination address.
Immediate to direct
IMD
Accesses a source operand addressed by H:X and a destination location within
the direct page addressed by the byte following the opcode. H:X is then
incremented.
Indexed to direct,
post increment
IX+D
Direct to indexed,
post increment
Accesses a source operand addressed by the byte following the opcode and a
destination location addressed by H:X, which is then incremented.
DIX+
SP1
SP2
Stack Pointer, 8-bit offset
Effective address is the value in SP added to the byte following the opcode.
Effective address is the value in SP added to the word formed by the 2 bytes
following the opcode (most significant first).
Stack Pointer, 16-bit offset
8.3.1
Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
8.3.2
Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
8.3.3
Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
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CPU
8.3.4
Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
8.3.5
Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
8.3.6
Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair
and two that use the stack pointer as the base reference.
8.3.6.1
Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
8.3.6.2
Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair increments (H:X = H:X + 0x0001)
after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions.
8.3.6.3
Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.4
Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair increments (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
8.3.6.5
Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
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Freescale Semiconductor
8-7
CPU
8.3.6.6
SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.7
SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.4
Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
8.4.1
Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event).
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
8.4.2
Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
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Freescale Semiconductor
CPU
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. Do not save H if the interrupt service routine does not use any instructions or
if auto-increment addressing modes may change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
8.4.3
Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
8.4.4
Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode.
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Freescale Semiconductor
8-9
CPU
8.4.5
BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active
background mode rather than continuing the user program.
The CALL is similar to a jump-to-subroutine (JSR) instruction, but the subroutine that is called can be
located anywhere in the normal 64-Kbyte address space or on any page of program expansion memory.
When CALL is executed, a return address is calculated, then it and the current program page register value
are stacked, and a new instruction-supplied value is written to PPAGE. The PPAGE value controls which
of the possible 16-Kbyte pages is visible through the window in the 64-Kbyte memory map. Execution
continues at the address of the called subroutine.
The actual sequence of operations that occur during execution of CALL is:
1. CPU calculates the address of the next instruction after the CALL instruction (the return address)
and pushes this 16-bit value onto the stack, low byte first.
2. CPU reads the old PPAGE value and pushes it onto the stack.
3. CPU writes the new instruction-supplied page select value to PPAGE. This switches the destination
page into the program overlay window in the CPU address range 0x8000 0xBFFF.
4. Instruction queue is refilled starting from the destination address, and execution begins at the new
address.
This sequence of operations is an uninterruptable CPU instruction. There is no need to inhibit interrupts
during CALL execution. In addition, a CALL can be performed from any address in memory to any other
address. This is a big improvement over other bank-switching schemes, where the page switch operation
can be performed only by a program outside the overlay window.
For all practical purposes, the PPAGE value supplied by the instruction can be considered to be part of the
effective address. The new page value is provided by an immediate operand in the instruction.
The RTC instruction is used to terminate subroutines invoked by a CALL instruction. RTC unstacks the
PPAGE value and the return address, the queue is refilled, and execution resumes with the next instruction
after the corresponding CALL.
The actual sequence of operations that occur during execution of RTC is:
1. The return value of the 8-bit PPAGE register is pulled from the stack.
2. The 16-bit return address is pulled from the stack and loaded into the PC.
3. The return PPAGE value is written to the PPAGE register.
4. The queue is refilled and execution begins at the new address.
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Freescale Semiconductor
CPU
Because the return operation is implemented as a single uninterruptable CPU instruction, the RTC can be
executed from anywhere in memory, including from a different page of extended memory in the overlay
window.
The CALL and RTC instructions behave like JSR and RTS, except they have slightly longer execution
times. Because extra execution cycles are required, routinely substituting CALL/RTC for JSR/RTS is not
recommended. JSR and RTS can be used to access subroutines that are located outside the program overlay
window or on the same memory page. However, if a subroutine can be called from other pages, it must be
terminated with an RTC. In this case, because RTC unstacks the PPAGE value as well as the return address,
all accesses to the subroutine, even those made from the same page, must use CALL instructions.
8.5
HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-3.
Operators
( )
&
|
:
+
–
=
=
=
=
=
=
=
=
=
=
Contents of register or memory location shown inside parentheses
Is loaded with (read: “gets”)
Boolean AND
Boolean OR
Boolean exclusive-OR
Multiply
Divide
Concatenate
Add
Negate (two’s complement)
CPU registers
A
CCR
H
X
PC
PCH
PCL
SP
=
Accumulator
Condition code register
=
=
=
=
=
=
=
Index register, higher order (most significant) 8 bits
Index register, lower order (least significant) 8 bits
Program counter
Program counter, higher order (most significant) 8 bits
Program counter, lower order (least significant) 8 bits
Stack pointer
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
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Freescale Semiconductor
8-11
CPU
Condition code register (CCR) bits
V
H
I
N
Z
C
=
=
=
=
=
=
Two’s complement overflow indicator, bit 7
Half carry, bit 4
Interrupt mask, bit 3
Negative indicator, bit 2
Zero indicator, bit 1
Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
–
0
1
=
=
=
=
=
Bit not affected
Bit forced to 0
Bit forced to 1
Bit set or cleared according to results of operation
Undefined after the operation
Þ
U
Machine coding notation
dd
ee
ff
ii
jj
kk
hh
ll
pg
rr
=
=
=
=
=
=
=
=
=
=
Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)
Upper 8 bits of 16-bit offset
Lower 8 bits of 16-bit offset or 8-bit offset
One byte of immediate data
High-order byte of a 16-bit immediate data value
Low-order byte of a 16-bit immediate data value
High-order byte of 16-bit extended address
Low-order byte of 16-bit extended address
Page
Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n — Any label or expression that evaluates to a single integer in the range 0–7
opr8i — Any label or expression that evaluates to an 8-bit immediate value
opr16i — Any label or expression that evaluates to a 16-bit immediate value
opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
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CPU
oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
page — Any label or expression that evaluates to a valid bank number for the PPAGE register.
For a 128-Kbyte derivative, any value between 0 and 7 is valid.
rel — Any label or expression that refers to an address that is within –128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes
INH
IMM
=
=
Inherent (no operands)
8-bit or 16-bit immediate
DIR
EXT
IX
IX+
IX1
=
=
=
=
=
=
8-bit direct
16-bit extended
16-bit indexed no offset
16-bit indexed no offset, post increment (CBEQ and MOV only)
16-bit indexed with 8-bit offset from H:X
16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX1+
IX2
REL
SP1
SP2
=
=
=
=
16-bit indexed with 16-bit offset from H:X
8-bit relative offset
Stack pointer with 8-bit offset
Stack pointer with 16-bit offset
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Freescale Semiconductor
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CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 1 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
Add with Carry
A (A) + (M) + (C)
Þ
Þ
–
Þ
Þ
Þ IMM
DIR
EXT
IX2
A9
B9
C9
D9
E9
F9
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
IX1
IX
SP2
SP1
ADC oprx16,SP
ADC oprx8,SP
9ED ee ff
9
ff
9EE9
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
Add without Carry
A (A) + (M)
Þ
Þ
–
Þ
Þ
Þ
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
9ED ee ff
B
9EE
B
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
ADD oprx16,SP
ADD oprx8,SP
SP2
SP1
ff
ii
ii
AIS #opr8i
AIX #opr8i
Add Immediate
Value (Signed) to
Stack Pointer
SP (SP) + (M)
M is sign extended to a 16-bit
value
–
–
0
–
–
–
–
–
–
–
–
Þ
–
–
Þ
–
–
–
IMM
IMM
A7
AF
2
2
Add Immediate
Value (Signed) to
Index Register (H:X) value
H:X (H:X) + (M)
M is sign extended to a 16-bit
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
Logical AND
A (A) & (M)
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
AND oprx16,SP
AND oprx8,SP
SP2
SP1
9ED ee ff
4
ff
9EE4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
Þ
Þ
–
–
–
–
Þ
Þ
Þ
Þ
Þ
Þ
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
5
1
1
5
4
6
C
0
b7
b0
ff
SP1
9E68 ff
C
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
5
1
1
5
4
6
b7
b0
ff
SP1
9E67 ff
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CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 2 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
BCC rel
Branch if Carry Bit
Clear
Branch if (C) = 0
–
–
–
–
–
–
REL
24
rr
3
BCLR n,opr8a
Clear Bit n in
Memory
Mn 0
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
11
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
13
15
17
19
1B
1D
1F
–
–
–
–
–
–
BCS rel
Branch if Carry Bit
Set (Same as BLO)
Branch if (C) = 1
REL
25
rr
3
–
–
–
–
–
–
–
–
–
–
–
BEQ rel
BGE rel
Branch if Equal
Branch if (Z) = 1
– REL
27
90
rr
rr
3
3
Branch if Greater
Than or Equal To
(Signed Operands)
Branch if (N V
REL
–
–
–
–
–
–
–
–
–
–
–
BGND
Enter Active
Background if
ENBDM = 1
Waits For and Processes BDM
Commands Until GO, TRACE1,
or TAGGO
INH
–
82
92
5+
3
BGT rel
Branch if Greater
Than (Signed
Operands)
Branch if (Z)| (N V
REL
–
rr
–
–
–
–
–
–
–
–
–
–
BHCC rel
BHCS rel
Branch if Half Carry Branch if (H) = 0
Bit Clear
REL
–
28
29
rr
rr
3
3
Branch if Half Carry Branch if (H) = 1
Bit Set
REL
–
–
–
–
–
–
–
–
–
–
–
BHI rel
Branch if Higher
Branch if (C) | (Z) = 0
Branch if (C) = 0
– REL
22
24
rr
rr
3
3
BHS rel
Branch if Higher or
Same (Same as
BCC)
REL
–
–
–
–
–
–
BIH rel
BIL rel
Branch if IRQ Pin
High
Branch if IRQ pin = 1
Branch if IRQ pin = 0
REL
–
2F
2E
rr
rr
3
3
–
–
–
–
–
–
–
–
–
–
Branch if IRQ Pin
Low
REL
–
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CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 3 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
Bit Test
(A) & (M)
(CCR Updated but Operands
Not Changed)
IMM
DIR
EXT
IX2
A5
B5
C5
D5
E5
F5
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
Þ
0
–
–
– IX1
IX
BIT oprx16,SP
BIT oprx8,SP
SP2
SP1
9ED ee ff
5
ff
9EE5
BLE rel
Branch if Less Than Branch if (Z)| (N V 1
or Equal To
REL
–
93
rr
3
–
–
–
–
–
(Signed Operands)
BLO rel
BLS rel
BLT rel
Branch if Lower
(Same as BCS)
Branch if (C) = 1
REL
–
25
23
91
2C
rr
rr
rr
rr
3
3
3
3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Branch if Lower or
Same
Branch if (C) | (Z) = 1
REL
–
Branch if Less Than Branch if (N V 1
(Signed Operands)
REL
–
BMC rel
Branch if Interrupt
Mask Clear
Branch if (I) = 0
REL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BMI rel
Branch if Minus
Branch if (N) = 1
Branch if (I) = 1
– REL
2B
2D
rr
rr
3
3
BMS rel
Branch if Interrupt
Mask Set
REL
–
BNE rel
BPL rel
BRA rel
Branch if Not Equal Branch if (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
26
2A
20
rr
rr
rr
3
3
3
Branch if Plus
Branch Always
Branch if (N) = 0
No Test
BRCLR
n,opr8a,rel
Branch if Bit n in
Memory Clear
Branch if (Mn) = 0
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
(b3)
DIR
–
–
–
–
–
Þ
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
MC13234/MC13237 Reference Manual, Rev. 1.8
8-16
Freescale Semiconductor
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 4 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
BRN rel
Branch Never
Uses 3 Bus Cycles
Branch if (Mn) = 1
–
–
–
–
–
– REL
21
rr
3
BRSET
n,opr8a,rel
Branch if Bit n in
Memory Set
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
(b3)
DIR
Þ
–
–
–
–
–
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
BSET n,opr8a
Set Bit n in Memory Mn 1
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
(b3)
DIR
–
–
–
–
–
–
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
BSR rel
Branch to Subroutine PC (PC) + 0x0002
REL
–
AD
AC
rr
5
push (PCL); SP (SP) – 0x0001
push (PCH); SP (SP) –
0x0001
–
–
–
–
–
–
–
–
–
–
PC (PC) + rel
CALL page,
opr16a
Call Subroutine
PC PC + 4
EXT
pghll 8
Push (PCL); SP (SP) –
0x0001
Push (PCH); SP (SP) –
0x0001
–
Push (PPAGE); SP (SP) –
0x0001
PPAGE page
PC Unconditional Address
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-17
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 5 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
CBEQ opr8a,rel Compare and
CBEQA #opr8i,rel Branch if Equal
CBEQX #opr8i,rel
CBEQ
oprx8,X+,rel
CBEQ ,X+,rel
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
31
41
51
61
71
dd rr
ii rr
ii rr
ff rr
rr
5
4
4
5
5
6
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
–
–
–
–
–
–
SP1
9E61 ff rr
CBEQ
oprx8,SP,rel
CLC
CLI
Clear Carry Bit
C 0
–
–
–
–
–
0
–
–
–
–
0 INH
98
9A
1
1
Clear Interrupt Mask I 0
Bit
INH
–
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
Clear
M 0x00
DIR
INH
INH
3F
4F
5F
8C
6F
7F
dd
ff
5
1
1
1
5
4
6
A 0x00
X 0x00
H 0x00
M 0x00
M 0x00
M 0x00
0
–
–
0
1
– INH
IX1
IX
SP1
CLR oprx8,SP
9E6F ff
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
Compare
Accumulator with
Memory
(A) – (M)
(CCR Updated But Operands
Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
–
–
Þ
Þ
Þ
CMP oprx16,SP
CMP oprx8,SP
SP2
SP1
9ED ee ff
1
ff
9EE1
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One’s Complement) A (A) = 0xFF – (A)
X (X) = 0xFF – (X)
M (M)= 0xFF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
5
1
1
5
4
6
Þ
Þ
Þ
Þ
0
–
–
–
–
1
M (M) = 0xFF – (M)
M (M) = 0xFF – (M)
M (M) = 0xFF – (M)
ff
SP1
9E63 ff
CPHX opr16a
CPHX #opr16i
CPHX opr8a
Compare Index
Register (H:X) with
Memory
(H:X) – (M:M + 0x0001)
(CCR Updated But Operands
Not Changed)
EXT
IMM
DIR
SP1
3E
65
75
9EF3 dd
ff
hh ll
jj
kk
6
3
5
6
Þ
Þ
CPHX oprx8,SP
MC13234/MC13237 Reference Manual, Rev. 1.8
8-18
Freescale Semiconductor
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 6 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
Compare X (Index
Register Low) with
Memory
(X) – (M)
(CCR Updated But Operands
Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
2
dd
hh ll
ee ff
ff
3
4
4
3
3
5
4
Þ
Þ
Þ
Þ
–
–
CPX oprx16,SP
CPX oprx8,SP
SP2
SP1
9ED ee ff
3
ff
9EE3
DAA
Decimal Adjust
Accumulator After
ADD or ADC of BCD
Values
(A)10
INH
72
1
Þ
Þ
Þ
U
–
–
–
–
–
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ
Decrement and
Branch if Not Zero
Decrement A, X, or M
Branch if (result) 0
DBNZX Affects X Not H
DIR
INH
INH
3B
4B
5B
6B
7B
dd rr
rr
rr
ff rr
rr
7
4
4
7
6
8
–
–
– IX1
IX
SP1
9E6B ff rr
oprx8,SP,rel
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement
M (M) – 0x01
A (A) – 0x01
X (X) – 0x01
M (M) – 0x01
M (M) – 0x01
M (M) – 0x01
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
1
1
5
4
6
Þ
–
–
–
–
Þ
Þ
Þ
–
SP1
9E6A ff
DIV
Divide
A (H:A)(X)
H Remainder
INH
52
6
–
–
Þ
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
Exclusive OR
Memory with
Accumulator
A (A M)
IMM
DIR
EXT
IX2
A8
B8
C8
D8
E8
F8
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
0
–
–
Þ
Þ
– IX1
IX
EOR oprx16,SP
EOR oprx8,SP
SP2
SP1
9ED ee ff
8
ff
9EE8
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M (M) + 0x01
A (A) + 0x01
X (X) + 0x01
M (M) + 0x01
M (M) + 0x01
M (M) + 0x01
DIR
INH
INH
3C
4C
5C
6C
7C
dd
5
1
1
5
4
6
Þ
Þ
Þ
–
–
– IX1
IX
ff
SP1
9E6 ff
C
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-19
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 7 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump
PC Jump Address
DIR
EXT
– IX2
IX1
BC
CC
DC
EC
FC
dd
3
4
4
3
3
hh ll
ee ff
ff
–
–
–
–
–
IX
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) –
0x0001
DIR
EXT
IX2
IX1
BD
CD
DD
ED
FD
dd
5
6
6
5
5
hh ll
ee ff
ff
–
0
–
–
–
–
–
–
–
Push (PCH); SP (SP) –
0x0001
PC Unconditional Address
IX
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
Load Accumulator
from Memory
A (M)
IMM
DIR
EXT
IX2
A6
B6
C6
D6
E6
F6
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
Þ
– IX1
IX
LDA oprx16,SP
LDA oprx8,SP
SP2
SP1
9ED ee ff
6
ff
9EE6
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register H:X M:M+ 0x0001
(H:X) from Memory
IMM
DIR
EXT
IX
45
55
32
jj
kk
dd
3
4
5
5
6
5
5
9EA hh ll
E
9EB ee ff
IX2
Þ
Þ
0
–
–
– IX1
SP1
E
ff
9EC ff
E
9EF
E
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
Load X (Index
Register Low) from
Memory
X (M)
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
0
–
–
Þ
Þ
–
LDX oprx16,SP
LDX oprx8,SP
SP2
SP1
9ED ee ff
E
ff
9EE
E
C
0
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
1
1
5
4
6
b7
b0
Þ
Þ
Þ
Þ
–
–
SP1
9E68 ff
MC13234/MC13237 Reference Manual, Rev. 1.8
8-20
Freescale Semiconductor
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 8 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
0
C
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
b7
b0
1
1
5
4
6
Þ
Þ
Þ
–
–
0
SP1
9E64 ff
MOV opr8a,opr8a Move
MOV opr8a,X+
MOV
#opr8i,opr8a
MOV ,X+,opr8a
(M)destination (M)source
DIR/DI 4E
5E
DIR/IX+ 6E
IMM/DI 7E
R
dd
dd
dd
ii
dd
dd
5
5
4
5
R
H:X (H:X) + 0x0001 in
IX+/DIR and DIR/IX+ Modes
Þ
–
Þ
Þ
–
Þ
0
–
Þ
–
0
–
–
–
–
–
IX+/DIR
MUL
Unsigned multiply
Negate
(Two’s Complement) A – (A) = 0x00 – (A)
X – (X) = 0x00 – (X)
X:A (X) (A)
0 INH
42
5
NEG opr8a
NEGA
NEGX
M – (M) = 0x00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
5
1
1
5
4
6
Þ
NEG oprx8,X
NEG ,X
NEG oprx8,SP
M – (M) = 0x00 – (M)
M – (M) = 0x00 – (M)
M – (M) = 0x00 – (M)
SP1
9E60 ff
NOP
NSA
No Operation
Uses 1 Bus Cycle
–
–
–
–
–
–
–
–
–
–
– INH
9D
1
1
Nibble Swap
Accumulator
A (A[3:0]:A[7:4])
INH
–
62
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
Inclusive OR
Accumulator and
Memory
A (A) | (M)
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
Þ
0
–
–
–
ORA oprx16,SP
ORA oprx8,SP
SP2
SP1
9ED ee ff
A
ff
9EE
A
PSHA
PSHH
Push Accumulator
onto Stack
Push (A); SP (SP) – 0x0001
Push (H); SP (SP) – 0x0001
INH
–
87
2
2
–
–
–
–
–
–
–
–
–
–
Push H (Index
Register High) onto
Stack
INH
–
8B
PSHX
PULA
Push X (Index
Register Low) onto
Stack
Push (X); SP (SP) – 0x0001
SP (SP + 0x0001); PullA
INH
–
89
86
2
3
–
–
–
–
–
–
–
–
–
–
Pull Accumulator
from Stack
INH
–
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-21
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 9 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
PULH
PULX
Pull H (Index
Register High) from
Stack
SP (SP + 0x0001); PullH
INH
INH
8A
88
3
3
–
–
–
–
–
–
Pull X (Index
Register Low) from
Stack
SP (SP + 0x0001); PullX
–
–
–
–
–
–
–
–
C
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through
Carry
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
5
1
1
5
4
6
b7
b0
Þ
Þ
Þ
Þ
SP1
9E69 ff
C
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through
Carry
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
5
1
1
5
4
6
b7
b0
Þ
Þ
Þ
Þ
–
–
ff
SP1
9E66 ff
RSP
Reset Stack Pointer SP 0xFF
INH
9C
1
–
–
–
–
–
–
–
–
–
–
–
–
(High Byte Not Affected)
RTC
Return fom CALL
SP (SP) + 0x0001; Pull
(PPAGE)
INH
8D
80
7
SP (SP) + 0x0001; Pull (PCH)
SP (SP) + 0x0001; Pull (PCL)
RTI
Return from Interrupt SP (SP) + 0x0001; Pull (CCR)
SP (SP) + 0x0001; Pull (A)
INH
INH
9
6
Þ
Þ
Þ
Þ
Þ
Þ
SP (SP) + 0x0001; Pull (X)
SP (SP) + 0x0001; Pull (PCH)
SP (SP) + 0x0001; Pull (PCL)
RTS
Return from
Subroutine
SP SP + 0x0001PullPCH)
SP SP + 0x0001; Pull (PCL)
81
–
–
–
–
–
–
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
Subtract with Carry A (A) – (M) – (C)
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
–
–
Þ
Þ
Þ
SBC oprx16,SP
SBC oprx8,SP
SP2
SP1
9ED ee ff
2
ff
9EE2
SEC
SEI
Set Carry Bit
C 1
I 1
–
–
–
–
–
1
–
–
–
–
1 INH
99
9B
1
1
Set Interrupt Mask
Bit
INH
–
MC13234/MC13237 Reference Manual, Rev. 1.8
8-22
Freescale Semiconductor
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 10 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
STA opr8a
Store Accumulator in M (A)
Memory
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
3
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
hh ll
ee ff
ff
4
4
3
2
5
4
Þ
Þ
0
–
–
–
SP2
SP1
9ED ee ff
7
ff
9EE7
STHX opr8a
STHX opr16a
STHX oprx8,SP
Store H:X (Index
Reg.)
(M:M + 0x0001) (H:X)
I bit 0; Stop Processing
DIR
– EXT
SP1
35
96
9EFF ff
dd
hh ll
4
5
5
Þ
Þ
0
–
–
–
–
0
STOP
Enable Interrupts:
Stop Processing
see MCU
INH
–
8E
2+
–
–
Documentation
STX opr8a
Store X (Low 8 Bits M (X)
of Index Register)
in Memory
DIR
EXT
IX2
BF
CF
DF
EF
FF
dd
3
4
4
3
2
5
4
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
hh ll
ee ff
ff
IX1
Þ
Þ
0
–
–
– IX
SP2
SP1
9ED ee ff
F
ff
9EE
F
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
Subtract
A (A) – (M)
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
2
3
4
4
3
3
5
4
dd
hh ll
ee ff
ff
Þ
–
–
Þ
Þ
Þ
SUB oprx16,SP
SUB oprx8,SP
SP2
SP1
9ED ee ff
0
ff
9EE0
SWI
Software Interrupt
PC (PC) + 0x0001
Push (PCL); SP (SP) –
0x0001
INH
83
11
Push (PCH); SP (SP) –
0x0001
Push (X); SP (SP) – 0x0001
Push (A); SP (SP) – 0x0001
Push (CCR); SP (SP) –
0x0001
–
–
1
–
–
–
I 1;
PCH Interrupt Vector High
Byte
PCL Interrupt Vector Low Byte
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-23
CPU
Table 8-3. HCS08 Instruction Set Summary (Sheet 11 of 11)
Effect
on CCR
Source
Form
Operation
Description
V
H
I
N
Z
C
TAP
TAX
Transfer
Accumulator to CCR
CCR (A)
INH
INH
84
97
1
1
Þ
Þ
Þ
Þ
Þ
Þ
Transfer
X (A)
Accumulator to X
(Index Register Low)
–
–
–
–
–
–
–
–
–
–
–
–
TPA
Transfer CCR to
Accumulator
A (CCR)
INH
85
1
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or (M) – 0x00
DIR
INH
INH
3D
4D
5D
6D
7D
dd
ff
4
1
1
4
3
5
Zero
(A) – 0x00
(X) – 0x00
(M) – 0x00
(M) – 0x00
(M) – 0x00
Þ
Þ
0
–
–
– IX1
IX
SP1
9E6 ff
D
TSX
TXA
Transfer SP to Index H:X (SP) + 0x0001
Reg.
INH
–
95
2
1
–
–
–
–
–
–
–
–
–
–
Transfer X (Index
Reg. Low) to
A (X)
INH
–
9F
Accumulator
TXS
Transfer Index Reg. SP (H:X) – 0x0001
to SP
INH
–
94
8F
2
–
–
–
–
–
0
–
–
–
–
WAIT
Enable Interrupts;
Wait for Interrupt
I bit 0; Halt CPU
INH
–
2+
1
Bus clock frequency is one-half of the CPU clock frequency.
MC13234/MC13237 Reference Manual, Rev. 1.8
8-24
Freescale Semiconductor
CPU
Table 8-4. Opcode Map (Sheet 1 of 3)
Read-Modify-Write Control
Bit-
Manipulation
Branch
Register/Memory
005
BRSET0
3DIR
105
BSET0
2DIR
203
BRA
2REL
305
NEG
2DIR
401
NEGA
1INH
501
NEGX
1INH
605
NEG
2IX1
704
NEG
1IX
809
RTI
903
A02
B03
SUB
2DIR
C04
SUB
3EXT
D04
SUB
3IX2
E03
SUB
2IX1
F03
SUB
1X
BGE
SUB
1INH 2REL 2IMM
015
BRCLR0
3DIR
115
BCLR0
2DIR
213
BRN
2REL
315
414
514
615
715
816
913
BLT
A12
B13
CMP
2DIR
C14
CMP
3EXT
D14
CMP
3IX2
E13
CMP
2IX1
F13
CMP
1IX
CBEQ CBEQA CBEQX
CBEQ
3IX1+
CBEQ RTS
CMP
3DIR
3IMM
3IMM
2IX+
1INH 2REL 2IMM
025
BRSET1
3DIR
125
BSET1
2DIR
223
BHI
325
425
MUL
1INH
526
DIV
621
NSA
1INH
721
DAA
1INH
825+
BGN
D
923
A22
B23
SBC
2DIR
C24
SBC
3EXT
D24
SBC
3IX2
E23
SBC
2IX1
F23
SBC
1IX
LDHX
3EXT
BGT
SBC
2REL
1INH
2REL 2IMM
1INH
035
BRCLR1
3DIR
135
BCLR1
2DIR
233
BLS
335
431
531
635
COM
2IX1
734
COM
1IX
8311
SWI
933
A32
B33
CPX
2DIR
C34
CPX
3EXT
D34
CPX
3IX2
E33
CPX
2IX1
F33
CPX
1IX
COM
2DIR
COMA COMX
BLE
CPX
2REL
1INH
1INH
1INH 2REL 2IMM
045
BRSET2
3DIR
145
BSET2
2DIR
243
BCC
2REL
345
LSR
2DIR
441
LSRA
1INH
541
LSRX
1INH
645
LSR
2IX1
744
LSR
1IX
841
942
A42
AND
2IMM
B43
AND
2DIR
C44
AND
3EXT
D44
AND
3IX2
E43
AND
2IX1
F43
AND
1IX
TAP
TXS
1INH 1INH
055
BRCLR2
3DIR
155
BCLR2
2DIR
253
BCS
2REL
354
STHX
2DIR
453
554
LDHX
2DIR
653
755
CPHX
2DIR
851
952
A52
BIT
B53
BIT
C54
BIT
D54
BIT
E53
BIT
F53
BIT
1IX
LDHX
3IMM
CPHX
3IMM
TPA
TSX
1INH 1INH
2IMM
2DIR
3EXT
3IX2
2IX1
065
BRSET3
3DIR
165
BSET3
2DIR
263
BNE
2REL
365
ROR
2DIR
461
RORA
1INH
561
RORX
1INH
665
ROR
2IX1
764
863 965
A62
LDA
B63
LDA
2DIR
C64
LDA
D64
LDA
3IX2
E63
LDA
2IX1
F63
LDA
1IX
ROR PULA STHX
1IX
1INH 3EXT 2IMM
3EXT
075
BRCLR3
3DIR
175
BCLR3
2DIR
273
BEQ
2REL
375
ASR
2DIR
471
ASRA
1INH
571
ASRX
1INH
675
ASR
2IX1
774
872
971
A72
AIS
B73
STA
2DIR
C74
STA
D74
STA
3IX2
E73
STA
2IX1
F72
STA
1IX
ASR PSHA TAX
1IX
1INH 1INH
2IMM
3EXT
085
BRSET4
3DIR
185
BSET4
2DIR
283
385
LSL
481
581
LSLX
1INH
685
LSL
2IX1
784
LSL
1IX
883 981
A82
EOR
2IMM
B83
EOR
2DIR
C84
EOR
3EXT
D84
EOR
3IX2
E83
EOR
2IX1
F83
EOR
1IX
BHCC
2REL
LSLA
1INH
PULX CLC
1INH 1INH
2DIR
095
BRCLR4
3DIR
195
BCLR4
2DIR
293
395
ROL
2DIR
491
ROLA
1INH
591
ROLX
1INH
695
ROL
2IX1
794
892
991
A92
ADC
2IMM
B93
ADC
2DIR
C94
ADC
3EXT
D94
ADC
3IX2
E93
ADC
2IX1
F93
ADC
1IX
BHCS
2REL
ROL PSHX SEC
1IX
1INH 1INH
0A5
BRSET5
3DIR
1A5
BSET5
2DIR
2A3
BPL
3A5
DEC
2DIR
4A1
DECA
1INH
5A1
DECX
1INH
6A5
DEC
2IX1
7A4
8A3
9A1
CLI
AA2
ORA
2IMM
BA3
ORA
2DIR
CA4
ORA
3EXT
DA4
ORA
3IX2
EA3
ORA
2IX1
FA3
ORA
1IX
DEC PULH
2REL
1IX
1INH 1INH
0B5
BRCLR5
3DIR
1B5
BCLR5
2DIR
2B3
BMI
3B7
4B4
5B4
6B7
DBNZ
3IX1
7B6
8B2 9B1
AB2
ADD
2IMM
BB3
ADD
2DIR
CB4
ADD
3EXT
DB4
ADD
3IX2
EB3
ADD
2IX1
FB3
ADD
1IX
DBNZ DBNZA DBNZX
DBNZ PSHH SEI
2REL
3DIR
2INH
2INH
2IX
1INH 1INH
0C5
BRSET6
3DIR
1C5
BSET6
2DIR
2C3
BMC
2REL
3C5
INC
4C1
INCA
1INH
5C1
INCX
1INH
6C5
INC
7C4
INC
1IX
8C1 9C1
AC8
CALL
4EXT
BC3
JMP
2DIR
CC4
JMP
DC4
JMP
3IX2
EC3
JMP
2IX1
FC3
JMP
1IX
CLRH RSP
1INH 1INH
2DIR
2IX1
3EXT
0D5
BRCLR6
3DIR
1D5
BCLR6
2DIR
2D3
BMS
2REL
3D4
TST
2DIR
4D1
TSTA
1INH
5D1
TSTX
1INH
6D4
TST
2IX1
7D3
TST
1IX
8D7
9D1
AD5
BSR
2REL
BD5
JSR
CD6
JSR
DD6
JSR
3IX2
ED5
JSR
2IX1
FD5
JSR
1IX
RTC
NOP
1INH 1INH
2DIR
3EXT
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-25
CPU
Table 8-4. Opcode Map (Sheet 2 of 3)
Read-Modify-Write Control
Bit-
Manipulation
Branch
Register/Memory
0E5
BRSET7
3DIR
1E5
BSET7
2DIR
2E3
BIL
3E6
4E5
MOV
3DD
5E5
MOV
2DIX+
6E4
MOV
3IMD
7E5
8E2+
9E
AE2
LDX
BE3
LDX
2DIR
CE4
LDX
DE4
LDX
3IX2
EE3
LDX
2IX1
FE3
LDX
1IX
CPHX
3EXT
MOV STOP Page
2REL
2IX+D 1INH
2
2IMM
3EXT
0F5
BRCLR7
3DIR
1F5
BCLR7
2DIR
2F3
BIH
3F5
CLR
2DIR
4F1
CLRA
1INH
5F1
CLRX
1INH
6F5
CLR
2IX1
7F4
CLR
1IX
8F2+
9F1
AF2
AIX
BF3
STX
2DIR
CF4
STX
DF4
STX
3IX2
EF3
STX
2IX1
FF2
STX
1IX
WAIT TXA
1INH 1INH
2REL
2IMM
3EXT
INHInherentRELRelativeSP1Stack Pointer, 8-Bit Offset
Opcode in
IMMImmediateIXIndexed, No OffsetSP2Stack Pointer, 16-Bit Offset
DIRDirectIX1Indexed, 8-Bit OffsetIX+Indexed, No Offset with
EXTExtendedIX2Indexed, 16-Bit OffsetPost Increment
DDDIR to DIRIMDIMM to DIRIX1+Indexed, 1-Byte Offset with
IX+DIX+ to DIR DIX+DIR to IX+Post Increment
Hexadecimal
Number of Bytes
F03
SUB
1IX
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
9E606
NEG
9ED05 9EE04
SUB
SUB
3SP1
4SP2
3SP1
9E616
CBEQ
4SP1
9ED15 9EE14
CMP
CMP
4SP2
3SP1
9ED25 9EE24
SBC
SBC
4SP2
3SP1
9E636
COM
3SP1
9ED35 9EE34 9EF36
CPX
CPX
CPHX
3SP1
4SP2
3SP1
9E646
LSR
9ED45 9EE44
AND
AND
3SP1
4SP2
3SP1
9ED55 9EE54
BIT
BIT
4SP2
3SP1
9E666
ROR
9ED65 9EE64
LDA
LDA
3SP1
4SP2
3SP1
9E676
ASR
9ED75 9EE74
STA
STA
3SP1
4SP2
3SP1
9E686
LSL
9ED85 9EE84
EOR
EOR
3SP1
4SP2
3SP1
MC13234/MC13237 Reference Manual, Rev. 1.8
8-26
Freescale Semiconductor
CPU
Table 8-4. Opcode Map (Sheet 3 of 3)
Bit-
Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
9ED9 9EE9
9E696
ROL
5
4
3 SP1
ADC ADC
4
3
SP2 SP1
9E6A6
DEC
9EDA 9EEA
5
4
3 SP1
ORA ORA
4
3
SP2 SP1
9E6B8
DBNZ
4 SP1
9EDB 9EEB
5
4
ADD ADD
4
3
SP2 SP1
9E6C6
INC
3 SP1
9E6D5
TST
3 SP1
9EAE 9EBE 9ECE 9EDE 9EEE 9EFE
5
6
5
5
4
5
LDHX LDHX LDHX LDX LDX LDHX
2 IX 4 IX2 3 IX1 4
3
3
SP2 SP1 SP1
9E6F6
CLR
9EDF 9EEF 9EFF
5
4
5
3 SP1
STX STX STHX
4
3
3
SP2 SP1 SP1
INHInherentRELRelativeSP1Stack Pointer, 8-Bit Offset
IMMImmediateIXIndexed, No OffsetSP2Stack Pointer, 16-Bit Offset
DIRDirectIX1Indexed, 8-Bit OffsetIX+Indexed, No Offset with
EXTExtendedIX2Indexed, 16-Bit OffsetPost Increment
DDDIR to DIRIMDIMM to DIRIX1+Indexed, 1-Byte Offset with
IX+DIX+ to DIRDIX+DIR to IX+Post Increment
Prebyte (9E) and
Opcode in
Hexadecimal
Number of Bytes
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
9E606 HCS08 Cycles
NEG Instruction Mnemonic
3
Addressing Mode
SP1
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
8-27
CPU
MC13234/MC13237 Reference Manual, Rev. 1.8
8-28
Freescale Semiconductor
Chapter 9
Parallel Input and Output
9.1
Introduction
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC13237 has 3 parallel 8-bit and 1 parallel 4-bit I/O ports, which include a total of 28 I/O pins. The
MC13234 has four parallel 8-bit I/O ports, which include a total of 32 I/O pins. See Chapter 2, “Pins and
Connections” for more information about pin assignments.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
keyboard interrupts. The peripheral modules have priority over the general-purpose I/O functions so that
when a peripheral is enabled, the I/O functions associated with the shared pins are disabled.
After reset, the shared peripheral functions are disabled and the pins default to:
•
•
•
•
Inputs
Slew rate control enabled
Low drive strength selected
Internal pullups disabled.
NOTE
•
•
To avoid extra current drain from floating input pins, the user should
initialize any unused/unconnected GPIO as either the default inputs with
on-chip pullups enabled or to outputs set to low. See Chapter 3, “System
Considerations” for more details.
I/O signal PTA2 is a special pin that can enable a special reserved factory
test mode. See Section 3.3.2, “Signal PTA2 (Factory Test Mode
Enable)” for more information.
9.2
Features
Parallel I/O features include:
•
•
•
•
•
•
•
A total of 28/32 general-purpose I/O pins in four ports
Hysteresis input buffers
Software-controlled pullups on each input pin
Software-controlled slew rate output buffers
Port A pins shared with IIC Bus and 32.768 kHz oscillator
PTA2 enables a reserved factory test mode
PTA7 is shared as serial debug port pin
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-1
Parallel Input and Output
•
•
•
•
Eight Port B pins shared with KBI1
MC13234: Four Port C pins shared with KBI2
MC13234: Four Port C pins shared with SPI port
MC13234: Eight Port D pins share with four TPM I/O pins, CMT high current output, and two SCI
pins
•
•
MC13237: Four Port C pins shared with SS_B, SPICLK/AD7, MISO, and MOSI
MC13237: Eight Port D pins shared with four TPM I/O pins, CMT high current output, two SCI
pins
•
GPIO have no interrupt request capability other than that provided by the shared functions
9.3
IO Port Pin Functional Description
The following description provides an overview of an individual port pin. Figure 9-1 shows a simple block
diagram of a port pin.
Most pins reset to the conditions stated in Section 9.1, “Introduction”, however, there are the following
exceptions:
•
PTA2 (factory test enable) — This signal should not be forced low while VDD is ramping-up.
— As VDD ramps, the POR circuit holds a reset condition until the voltage exceeds the POR
threshold. This pin is an input and must be in the low state when the POR exits reset or a factory
chip test mode is enabled.
— PTA2 is otherwise a standard GPIO port pin, however, best practice is to tie the pin low through
a resistor to assure a low state when exiting POR
— A reset initiated by the RESET pin or any operational condition other than POR does not affect
PTA2 or factory test.
•
PTA7/BKGD/MS (shared debug port) — upon exiting reset, BKGD/MS is enabled and therefore
is not usable as an output pin until BKGDPE in SOPT Register is cleared.
Each pin has the programmable attributes of input mode versus output mode:
•
•
Input mode with optional pullup
Output mode
— Slew rate control
— Drive strength control
— Output state - as determined by output register
MC13234/MC13237 Reference Manual, Rev. 1.8
9-2
Freescale Semiconductor
Parallel Input and Output
PTxDDn
Output Enable
Output Data
D
Q
PTxDn
D
Q
1
0
Port Read
Data
Input Data
Synchronizer
BUSCLK
Figure 9-1. Parallel Port Pin Block Diagram
9.3.1
Port Data and Data Direction
Reading and writing of the parallel I/O are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers.
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
9.4
Pullup, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive
strength for the pins and may be used in conjunction with the peripheral functions on these pins.
9.4.1
Port Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTxPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup is also disabled for an analog function.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-3
Parallel Input and Output
9.4.2
Port Slew Rate Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition to reduce
EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
9.4.3
Port Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
9.5
Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the Stop3 mode follows:
•
In Stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
Pins behavior is unaffected by LPRun, Wait, and Background mode operation.
9.6
Interrupt Request Capability
The parallel IO ports have no interrupt request generation capability.
9.7
Parallel I/O and Pin Control Registers
Each port has an independent set of control registers. These registers are located both in the Direct-Page
and High-Page Register Maps:
•
•
The data and data direction registers are located in the Direct-Page Map.
The pullup, slew rate, and drive strength registers are located in the High-Page Map.
9.7.1
Port A Registers
Port A is controlled by the registers listed below.
9.7.1.1 Port A Data Register (PTAD)
PTAD is the Port A data register. The register contents drive the Port A pads when they are configured as
outputs. A read of this register returns the register contents for a programmed output and returns the state
of the pad for a programmed input.
MC13234/MC13237 Reference Manual, Rev. 1.8
9-4
Freescale Semiconductor
Parallel Input and Output
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the PTADD bit will continue to control the source for reads of the PTAD register.
NOTE
PTA2 is a special pin. If the VDD supply voltage is applied (or recycled),
the POR circuit is activated and tests the PTA2 input state as the POR
releases. If PTA2 is at a high state the device enters a factory test mode, and
if PTA2 is at a low state, normal operation ensues.
PTAD
0x0000
7
6
5
4
3
2
1
0
R
W
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Reset:
0
0
0
0
0
0
0
0
Figure 9-2. Port A Data Register (PTAD)
Table 9-1. PTAD Register Field Descriptions
Description
Field
7:0
Port A Data Register Bits — For Port A pins:
PTAD[7:0]
• For pins configured as inputs, reads return the logic level on the pin.
• For pins that are configured as outputs, reads return the last value written to this register.
• Writes are latched into all bits of this register. For Port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
• Reset forces PTAD to all 0s, but these 0s are not driven out to the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
9.7.1.2
Port A Data Direction Register (PTADD)
PTADD is the read/write Port A data direction register. The register controls the direction of the Port A
pins and also controls the read function of PTAD.
PTADD
0x0001
7
6
5
4
3
2
1
0
R
W
PTADD7
PTADD6
0
PTADD5
PTADD4
PTADD3
PTADD2
0
PTADD1
PTADD0
Reset:
0
0
0
0
0
0
Figure 9-3. Port A Data Direction Register (PTADD)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-5
Parallel Input and Output
Table 9-2. PTADD Register Field Descriptions
Description
Field
7:0
PTADD[7:0] PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
Data Direction for Port A Bits — These read/write bits control the direction of Port A pins and what is read for
1 Output driver enabled for Port A bit n and PTAD reads return the contents of PTADn.
9.7.1.3
Port A Pull Enable Register (PTAPE)
PTAPE is the read/write Port A pullup enable register. The register enables onboard pullups for pins that
are enabled as inputs. These bits have no effect on Port A pins programmed as outputs.
When pins are controlled by peripheral functions, this bits can also enable a pullup on input pins. The
pullups are disabled for an analog function such as the 32 kHz oscillator.
PTAPE
0x1830
7
6
5
4
3
2
1
0
R
W
PTAPE7
PTAPE6
0
PTAPE5
PTAPE4
PTAPE3
PTAPE2
0
PTAPE1
PTAPE0
Reset:
0
0
0
0
0
0
Figure 9-4. Port A Pull Enable Register (PTAPE)
Table 9-3. PTAPE Register Field Descriptions
Description
Field
7:0
Internal Pull Enable for Port A Bits — Each of these control bits determines whether the internal pullup is
PTAPE[7:0] enabled for the associated PTA pin. For Port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for Port A bit n.
1 Internal pullup device enabled for Port A bit n.
9.7.1.4
Port A Slew Rate Enable Register (PTASE)
PTASE is the read/write Port A output slew rate enable register. The register controls the slew rate of Port
A outputs.
PTASE
0x1831
7
6
5
4
3
2
1
0
R
W
PTASE7
PTASE6
1
PTASE5
PTASE4
PTASE3
PTASE2
1
PTASE1
PTASE0
Reset:
1
1
1
1
1
1
Figure 9-5. Port A Slew Rate Enable Register (PTASE)
MC13234/MC13237 Reference Manual, Rev. 1.8
9-6
Freescale Semiconductor
Parallel Input and Output
Table 9-4. PTASE Register Field Descriptions
Description
Field
7:0
Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew rate
PTASE[7:0] control is enabled for the associated PTA pin. For Port A pins that are configured as inputs, these bits have no
effect.
0 Output slew rate control disabled for Port A bit n.
1 Output slew rate control enabled for Port A bit n.
9.7.1.5
Port A Drive Strength Selection Register (PTADS)
PTADS is the read/write Port A output drive strength control register. The register controls the drive
strength of Port A outputs.
PTADS
0x1832
7
6
5
4
3
2
1
0
R
W
PTADS7
PTADS6
0
PTADS5
PTADS4
PTADS3
PTADS2
0
PTADS1
PTADS0
Reset:
0
0
0
0
0
0
Figure 9-6. Port A Drive Strength Selection Register (PTADS)
Table 9-5. PTADS Register Field Descriptions
Description
Field
7:0
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
PTADS[7:0] output drive for the associated PTA pin. For Port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port A bit n.
1 High output drive strength selected for Port A bit n.
9.7.2
Port B Registers
Port B is controlled by the registers listed below.
9.7.2.1 Port B Data Register (PTBD)
PTBD is the Port Bdata register. The register contents drive the PORT Bpads when they are configured as
outputs. A read of this register returns the register contents for a programmed output and returns the state
of the pad for a programmed input.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the PTBDD bit will continue to control the source for reads of the PTBD register
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-7
Parallel Input and Output
PTBD
0x0002
7
6
5
4
3
2
1
0
R
PTBD7
W
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
Reset:
0
0
0
0
0
0
0
0
Figure 9-7. Port B Data Register (PTBD)
Table 9-6. PTBD Register Field Descriptions
Description
Field
7:0
Port B Data Register Bits — For Port Bpins:
PTBD[7:0]
• For pins configured as inputs, reads return the logic level on the pin.
• For pins that are configured as outputs, reads return the last value written to this register.
• Writes are latched into all bits of this register. For Port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
• Reset forces PTBD to all 0s, but these 0s are not driven out to the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
9.7.2.2
Port B Data Direction Register (PTBDD)
PTBDD is the read/write Port B data direction register. The register controls the direction of the Port B
pins and also controls the read function of PTBD.
PTBDD
0x0003
7
6
5
4
3
2
1
0
R
W
PTBDD7
PTBDD6
0
PTBDD5
PTBDD4
PTBDD3
PTBDD2
0
PTBDD1
PTBDD0
Reset:
0
0
0
0
0
0
Figure 9-8. Port B Data Direction Register (PTBDD)
Table 9-7. PTBDD Register Field Descriptions
Description
Field
7:0
Data Direction for Port B Bits — These read/write bits control the direction of Port B pins and what is read for
PTBDD[7:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for Port B bit n and PTBD reads return the contents of PTBDn.
9.7.2.3
Port B Pull Enable Register (PTBPE)
PTBPE is the read/write Port B pullup enable register. The register enables onboard pullups for pins that
are enabled as inputs. These bits have no effect on Port B pins programmed as outputs.
MC13234/MC13237 Reference Manual, Rev. 1.8
9-8
Freescale Semiconductor
Parallel Input and Output
When pins are controlled by peripheral functions, this bits can also enable a pullup on input pins.
PTBPE
0x1834
7
6
5
4
3
2
1
0
R
W
PTBPE7
PTBPE6
0
PTBPE5
PTBPE4
PTBPE3
PTBPE2
0
PTBPE1
PTBPE0
Reset:
0
0
0
0
0
0
Figure 9-9. Port B Pull Enable Register (PTBPE)
Table 9-8. PTBPE Register Field Descriptions
Description
Field
7:0
Internal Pull Enable for Port B Bits — Each of these control bits determines whether the internal pullup is
PTBPE[7:0] enabled for the associated PTB pin. For Port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for Port B bit n.
1 Internal pullup device enabled for Port B bit n.
9.7.2.4
Port B Slew Rate Enable Register (PTBSE)
PTBSE is the read/write Port B output slew rate enable register. The register controls the slew rate of Port
B outputs.
PTBSE
0x1835
7
6
5
4
3
2
1
0
R
W
PTBSE7
PTBSE6
1
PTBSE5
PTBSE4
PTBSE3
PTBSE2
1
PTBSE1
PTBSE0
Reset:
1
1
1
1
1
1
Figure 9-10. Port B Slew Rate Enable Register (PTBSE)
Table 9-9. PTBSE Register Field Descriptions
Description
Field
7:0
Output Slew Rate Enable for Port B Bits — Each of these control bits determines whether the output slew rate
PTBSE[7:0] control is enabled for the associated PTB pin. For Port B pins that are configured as inputs, these bits have no
effect.
0 Output slew rate control disabled for Port B bit n.
1 Output slew rate control enabled for Port B bit n.
9.7.2.5
Port B Drive Strength Selection Register (PTBDS)
PTBDS is the read/write Port B output drive strength control register. The register controls the drive
strength of Port B outputs.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-9
Parallel Input and Output
PTBDS
0x1836
7
6
5
4
3
2
1
0
R
PTBDS7
W
PTBDS6
0
PTBDS5
PTBDS4
PTBDS3
PTBDS2
0
PTBDS1
PTBDS0
Reset:
0
0
0
0
0
0
Figure 9-11. Port B Drive Strength Selection Register (PTBDS)
Table 9-10. PTBDS Register Field Descriptions
Description
Field
7:0
Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
PTBDS[7:0] output drive for the associated PTB pin. For Port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port B bit n.
1 High output drive strength selected for Port B bit n.
9.7.3
Port C Registers
Port C is controlled by the registers listed below.
9.7.3.1 Port C Data Register (PTCD)
PTCD is the Port C data register. The register contents drive the PORT C pads when they are configured
as outputs. A read of this register returns the register contents for a programmed output and returns the
state of the pad for a programmed input.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the PTCDD bit will continue to control the source for reads of the PTCD register
PTCD
0x0004
7
6
5
4
3
2
1
0
R
W
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
Reset:
0
0
0
0
0
0
0
0
Figure 9-12. Port C Data Register (PTCD)
MC13234/MC13237 Reference Manual, Rev. 1.8
9-10
Freescale Semiconductor
Parallel Input and Output
Table 9-11. PTCD Register Field Descriptions
Description
Field
7:0
Port C Data Register Bits — For Port C pins:
PTCD[7:0] • For pins configured as inputs, reads return the logic level on the pin.
• For pins that are configured as outputs, reads return the last value written to this register.
• Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
• Reset forces PTCD to all 0s, but these 0s are not driven out to the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
• In the MC13237, only PTC4, PTC5, PTC6, and PTC7 are available.
9.7.3.2
Port C Data Direction Register (PTCDD)
PTCDD is the read/write Port A data direction register. The register controls the direction of the Port C
pins and also controls the read function of PTCD.
PTCDD
0x0005
7
6
5
4
3
2
1
0
R
W
PTCDD7
PTCDD6
0
PTCDD5
PTCDD4
PTCDD3
PTCDD2
0
PTCDD1
PTCDD0
Reset:
0
0
0
0
0
0
Figure 9-13. Port C Data Direction Register (PTCDD)
Table 9-12. PTCDD Register Field Descriptions
Description
Field
7:0
Data Direction for Port C Bits — These read/write bits control the direction of Port C pins and what is read for
PTCDD[7:0] PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for Port C bit n and PTCD reads return the contents of PTCDn.
In the MC13237, only PTC4, PTC5, PTC6, and PTC7 are available.
9.7.3.3
Port C Pull Enable Register (PTCPE)
PTAPE is the read/write Port A pullup enable register. The register enables onboard pullups for pins that
are enabled as inputs. These bits have no effect on Port A pins programmed as outputs.
When pins are controlled by peripheral functions, this bits can also enable a pullup on input pins.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-11
Parallel Input and Output
PTCPE
0x1838
7
6
5
4
3
2
1
0
R
PTCPE7
W
PTCPE6
0
PTCPE5
PTCPE4
PTCPE3
PTCPE2
0
PTCPE1
PTCPE0
Reset:
0
0
0
0
0
0
Figure 9-14. Port C Pull Enable Register (PTCPE)
Table 9-13. PTCPE Register Field Descriptions
Description
Field
7:0
Internal Pull Enable for Port C Bits — Each of these control bits determines whether the internal pullup device
PTCPE[7:0] is enabled for the associated PTC pin. For Port C pins that are configured as outputs, these bits have no effect
and the internal pull devices are disabled.
0 Internal pullup device disabled for Port C bit n.
1 Internal pullup device enabled for Port C bit n.
In the MC13237, only PTC4, PTC5, PTC6, and PTC7 are available.
9.7.3.4
Port C Slew Rate Enable Register (PTCSE)
PTCSE is the read/write Port C output slew rate enable register. The register controls the slew rate of Port
C outputs.
PTCSE
0x1839
7
6
5
4
3
2
1
0
R
W
PTCSE7
PTCSE6
1
PTCSE5
PTCSE4
PTCSE3
PTCSE2
1
PTCSE1
PTCSE0
Reset:
1
1
1
1
1
1
Figure 9-15. Port C Slew Rate Enable Register (PTCSE)
Table 9-14. PTCSE Register Field Descriptions
Description
Field
7:0
Output Slew Rate Enable for Port C Bits — Each of these control bits determines whether the output slew rate
PTCSE[7:0] control is enabled for the associated PTC pin. For Port C pins that are configured as inputs, these bits have no
effect.
0 Output slew rate control disabled for Port C bit n.
1 Output slew rate control enabled for Port C bit n.
In the MC13237, only PTC4, PTC5, PTC6, and PTC7 are available.
9.7.3.5
Port C Drive Strength Selection Register (PTCDS)
PTCDS is the read/write Port C output drive strength control register. The register controls the drive
strength of Port C outputs.
MC13234/MC13237 Reference Manual, Rev. 1.8
9-12
Freescale Semiconductor
Parallel Input and Output
PTCDS
0x183A
7
6
5
4
3
2
1
0
R
W
PTCDS7
PTCDS6
0
PTCDS5
PTCDS4
PTCDS3
PTCDS2
0
PTCDS1
PTCDS0
Reset:
0
0
0
0
0
0
Figure 9-16. Port C Drive Strength Selection Register (PTCDS)
Table 9-15. PTCDS Register Field Descriptions
Description
Field
7:0
Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
PTCDS[7:0] output drive for the associated PTC pin. For Port C pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port C bit n.
1 High output drive strength selected for Port C bit n.
In the MC13237, only PTC4, PTC5, PTC6, and PTC7 are available.
9.7.4
Port D Registers
Port D is controlled by the registers listed below.
9.7.4.1 Port D Data Register (PTDD)
PTDD is the Port D data register. The register contents drive the PORT D pads when they are configured
as outputs. A read of this register returns the register contents for a programmed output and returns the
state of the pad for a programmed input.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the PTDDD bit will continue to control the source for reads of the PTDD register
PTDD
0x0006
7
6
5
4
3
2
1
0
R
W
PTDD7
PTDD6
PTDD5
PTDD4
PTDD3
PTDD2
PTDD1
PTDD0
Reset:
0
0
0
0
0
0
0
0
Figure 9-17. Port D Data Register (PTDD)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-13
Parallel Input and Output
Table 9-16. PTDD Register Field Descriptions
Description
Field
7:0
Port D Data Register Bits — For Port D pins:
PTDD[7:0] • For pins configured as inputs, reads return the logic level on the pin.
• For pins that are configured as outputs, reads return the last value written to this register.
• Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
• Reset forces PTDD to all 0s, but these 0s are not driven out to the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
9.7.4.2
Port D Data Direction Register (PTDDD)
PTDDD is the read/write Port D data direction register. The register controls the direction of the Port D
pins and also controls the read function of PTDD.
PTDDD
0x0007
7
6
5
4
3
2
1
0
R
W
PTDDD7
PTDDD6
0
PTDDD5
PTDDD4
PTDDD3
PTDDD2
0
PTDDD1
PTDDD0
Reset:
0
0
0
0
0
0
Figure 9-18. Port D Data Direction Register (PTDDD)
Table 9-17. PTDDD Register Field Descriptions
Description
Field
7:0
Data Direction for Port D Bits — These read/write bits control the direction of Port D pins and what is read for
PTDDD[7:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for Port D bit n and PTDD reads return the contents of PTDDn.
9.7.4.3
Port D Pull Enable Register (PTDPE)
PTDPE is the read/write Port D pullup enable register. The register enables onboard pullups for pins that
are enabled as inputs. These bits have no effect on Port D pins programmed as outputs.
When pins are controlled by peripheral functions, this bits can also enable a pullup on input pins.
PTDPE
0x183C
7
6
5
4
3
2
1
0
R
W
PTDPE7
PTDPE6
0
PTDPE5
PTDPE4
PTDPE3
PTDPE2
0
PTDPE1
PTDPE0
Reset:
0
0
0
0
0
0
Figure 9-19. Port D Pull Enable Register (PTDPE)
MC13234/MC13237 Reference Manual, Rev. 1.8
9-14
Freescale Semiconductor
Parallel Input and Output
Table 9-18. PTDPE Register Field Descriptions
Description
Field
7:0
Internal Pull Enable for Port D Bits — Each of these control bits determines whether the internal pullup device
PTDPE[7:0] is enabled for the associated PTD pin. For Port D pins that are configured as outputs, these bits have no effect
and the internal pull devices are disabled.
0 Internal pullup device disabled for Port D bit n.
1 Internal pullup device enabled for Port D bit n.
9.7.4.4
Port D Slew Rate Enable Register (PTDSE)
PTDSE is the read/write Port D output slew rate enable register. The register controls the slew rate of Port
D outputs.
PTDSE
0x183D
7
6
5
4
3
2
1
0
R
W
PTDSE7
PTDSE6
1
PTDSE5
PTDSE4
PTDSE3
PTDSE2
1
PTDSE1
PTDSE0
Reset:
1
1
1
1
1
1
Figure 9-20. Port D Slew Rate Enable Register (PTDSE)
Table 9-19. PTDSE Register Field Descriptions
Description
Field
7:0
Output Slew Rate Enable for Port D Bits — Each of these control bits determines whether the output slew rate
PTDSE[7:0] control is enabled for the associated PTD pin. For Port D pins that are configured as inputs, these bits have no
effect.
0 Output slew rate control disabled for Port D bit n.
1 Output slew rate control enabled for Port D bit n.
9.7.4.5
Port D Drive Strength Selection Register (PTDDS)
PTDDS is the read/write Port D output drive strength control register. The register controls the drive
strength of Port D outputs.
PTDDS
0x183E
7
6
5
4
3
2
1
0
R
W
PTDDS7
PTDDS6
0
PTDDS5
PTDDS4
PTDDS3
PTDDS2
0
PTDDS1
PTDDS0
Reset:
0
0
0
0
0
0
Figure 9-21. Port D Drive Strength Selection Register (PTDDS)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
9-15
Parallel Input and Output
Table 9-20. PTDDS Register Field Descriptions
Description
Field
7:0
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
PTDDS[7:0] output drive for the associated PTD pin. For Port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port D bit n.
1 High output drive strength selected for Port D bit n.
MC13234/MC13237 Reference Manual, Rev. 1.8
9-16
Freescale Semiconductor
Chapter 10
Real-Time Counter (RTC)
10.1 Introduction
The real-time counter (RTC) consists of a 16-bit counter, a 16-bit comparator, several binary-based and
decimal-based prescaler dividers, three clock sources, and a programmable periodic interrupt request. This
module can be used for time-of-day, calendar or task scheduling functions. It can also serve as a cyclic
wake-up from low power modes without the need of external components.
RTC can be clocked from the 32 MHz reference clock, the optional 32.768 kHz clock or the on board
1 kHz RC clock.
10.2 Features
Features of the RTC module include:
•
16-bit up-counter
— 16-bit modulo match limit
— Software controllable periodic interrupt on match
Three software selectable clock sources for input to prescaler
— Optional 32.768 kHz oscillator (XOSC1).
— 32MHz reference oscillator (XOSC2).
— 1 kHz RC oscillator (default)
•
•
•
Wide range of prescale options include binary and decimal divide-by ratios
For lowest operating power, the RTC can be disabled via system clock gating control (Register
SCGC2, Bit 1)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
10-1
Real-Time Counter (RTC)
10.3 Block Diagram
The block diagram for the RTC module is shown in Figure 10-1.
XOSC1
CLOCK
SOURCE
SELECT
XOSC2
1KHz
VDD
16-BIT MODULO
(RTCMOD)
RTCLKS
RTC
INTERRUPT
REQUEST
RTIF
Q
D
E
BACKGROUND
MODE
RTCPS
RTCLKS[0]
16-BIT COMPARATOR
R
RTIE
RTC
CLOCK
Write 1 to
RTIF
PRESCALER
DIVIDE-BY
16-BIT COUNTER
(RTCCNT)
Figure 10-1. Real-Time Counter (RTC) Block Diagram
10.4 Functional Description
The RTC is built around a main 16-bit up-counter (RTCCNT) driven by the internal RTC Clock that is
derived from a clock select multiplexer that, in turn, feeds a programmable prescaler with binary and
decimal divide-by options. The up-counter value is then compared to a 16-bit modulo register (RTCMOD)
that provides status (RTIF) and resets the up-counter upon a valid compare. The RTIF can be enabled to
provide an interrupt request.
After any MCU reset, the counter is stopped and reset to 0x00, the modulus register is set to 0x00, and the
prescaler is off. The 1kHz internal oscillator clock is selected as the default clock source. To start the
prescaler, any value other than zero is written to the prescaler select bits (RTCPS).
10.4.1 Clock Source and Prescale Value
Three clock sources are software selectable:
•
•
•
The optional 32.768 kHz oscillator (XOSC1)
1 kHz RC oscillator (default)
32 MHz reference oscillator (XOSC2)
The RTC clock select bits (RTCLKS[1:0]) are used to select the desired clock source to the prescaler
dividers. If a different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00.
NOTE
The selected RTC clock source impacts operation of the 1 kHz oscillator and
power down of the RTC:
MC13234/MC13237 Reference Manual, Rev. 1.8
10-2
Freescale Semiconductor
Real-Time Counter (RTC)
•
•
•
The RTC must be enabled by the Register SCGC2, Bit 1 to switch the
RTC clock source to one other than the 1 kHz oscillator
The 1 kHz oscillator must not be the selected RTC clock source to allow
the 1 kHz oscillator to be disabled. See Section 5.4.1, “Clock Sources”.
The 1 kHz oscillator CANNOT be the selected RTC clock source if it is
desired to disable the RTC block via Register SCGC2, Bit 1. See
Section 10.5.2, “Stop3 Mode”
The RTC prescaler select bits (RTCPS[3:0]) in combination with the RTCLKS[0] bit select the desired
prescaler divide-by value. If a new value is written to RTCPS, the prescaler and RTCCNT counters are
reset to 0x00. Table 10-1 shows available prescaler period values.
Table 10-1. RTC Prescaler Period Values
1 kHz RC Osc Source
Prescale Ratio /
Prescaler Period
(RTCLKS = 00)
32-MHz Osc Source 32.768-kHz Osc Source 32.768-kHz Osc Source
Prescale Ratio /
Prescaler Period
(RTCLKS = 01)
Prescale Ratio /
Prescaler Period
(RTCLKS = 10)
Prescale Ratio /
Prescaler Period
(RTCLKS = 11)
RTCPS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Off
Off
Off
Off
23 / 8 ms
210 / 0.032 ms
211 / 0.064 ms
212 / 0.128 ms
213 / 0.256 ms
214 / 0.512 ms
215 / 1.024 ms
216 / 2.048 ms
103 / 0.03125 ms
2x103 / 0.0625 ms
5x103 / 0.15625 ms
104 / 0.3125 ms
2x104 / 0.625 ms
5x104 / 1.5625 ms
105 / 3.125 ms
2x105 / 6.25 ms
23 / 0.244 ms
25 / 0.976 ms
26 / 1.95 ms
210 / 31.25 ms
211 / 62.5 ms
212 / 125 ms
25 / 32 ms
26 / 64 ms
27 / 128 ms
28 / 256 ms
29 / 512 ms
210 / 1024 ms
1 / 1 ms
27 / 3.9 ms
213 / 250 ms
28 / 7.8125 ms
29 / 15.625 ms
210 / 31.25 ms
1 / 0.030517 ms
2 / 0.06103 ms
22 / 0.12207 ms
10 / 0.30517 ms
24 / 0.48828 ms
102 / 3.0517 ms
5x102 / 15.2588 ms
103 / 30.517 ms
214 / 500 ms
215 / 1 S
216 / 2 S
103 / 30.518 ms
2x103 / 61.035 ms
5x103 / 152.59 ms
104 / 305.18 ms
2x104 / 610.35 ms
5x104 / 1.5259 s
105 / 3.0518 s
2x105 / 6.1035 s
2 / 2 ms
22 / 4 ms
10 / 10 ms
24 / 16 ms
102 / 100 ms
5x102 / 500 ms
103 / 1 s
10.4.2 Compare Function
The compare function is used to set a time base for generating a periodic interrupt that can be used for
walk-up or as a timetick. The time period is determined by:
•
•
The frequency of the selected clock source
The prescaler setting
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
10-3
Real-Time Counter (RTC)
•
The RTC modulo register
10.4.2.1 RTC Modulo Register
The RTC modulo register (RTCMOD) provides the compare value which can be set to any value from
0x0000 to 0xFFFF. When the counter is active, the counter increments at the selected prescale rate until
the count matches the modulo value. When the values match, on the next clock the counter resets to
0x0000 and then continues counting. The real-time interrupt flag (RTIF) is set whenever a match occurs.
The flag sets on the transition from the modulo value to 0x00. Writing to RTCMOD resets the prescaler
and the RTCCNT counter to 0x0000.
10.4.2.2 RTC Accuracy with 1 kHz RC Oscillator
The RTC time period is only as accurate as the selected clock source. The 32.768 kHz and 32 MHz sources
are crystal-based and as such are very accurate. The 1 kHz RC oscillator frequency is typically accurate to
within ± 40% at room temperate and can vary even more with temperature.
It is possible to do a simple form of trimming for a 1 kHz oscillator based RTC application:
•
Select an RTC prescale option that allows for the largest possible modulo register setting for the
desired timebase
•
In software, provide a utility that creates a TPM timer function with a delay long enough to loosely
calibrate the RTC count.
— Use an interrupt from the TPM to read the RTC Counter Registers.
— This counter value can then be used to calculate a difference from an expected value.
— The difference can then be used to modify the Modulo register value to trim the RTC counter
period closer to an accurate value.
10.4.3 Interrupt Request
The RTC allows for an interrupt request to be generated whenever RTIF is set. To enable the real-time
interrupt, set the real-time interrupt enable bit (RTIE) in RTCSC. RTIF is cleared by writing a 1 to RTIF.
10.4.4 Module Clock Disable
The RTC compare logic and registers are driven by the bus clock. To disable the module for lowest
operating power, the module clock can be disabled by the RTC Bit of Register SCGC2.
10.5 Modes of Operation
The operational mode of the RTC is affected by the present mode of the MC13234/MC13237. The RTC is
unaffected in Run or LPRun modes.
MC13234/MC13237 Reference Manual, Rev. 1.8
10-4
Freescale Semiconductor
Real-Time Counter (RTC)
10.5.1 Wait Mode
The RTC continues to run in Wait mode if it was enabled before executing the WAIT instruction.
Therefore, the RTC can be used to bring the MCU out of Wait mode if the real-time interrupt is enabled.
For lowest possible current consumption, the RTC should be stopped by software if not needed as an
interrupt source during Wait mode.
10.5.2 Stop3 Mode
The RTC continues to run in Stop3 mode if the RTC is enabled before executing the STOP instruction.
Therefore, the RTC can be used to bring the MCU out of stop modes, if the real-time interrupt is enabled.
•
For lowest power, the RTC block can be disabled before entering Stop mode -
— The RTC clock source must first be programmed as the 32 MHz or the 32.768 kHz (not using
the 1 kHz source) before disabling the RTC block. The RTC clock must be enabled to allow
this operation.
— The RTC block is then disabled by writing RTC Clock Date Control (Bit 1, Register SCGC2)
to a zero.
•
Power consumption is lower when the RTC is disabled, but in that case the real-time interrupt
cannot wake up the MCU from Stop modes.
10.5.3 Active Background Mode
The RTC suspends all counting during active background mode until the microcontroller returns to normal
user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not
written and the RTCPS and RTCLKS bits are not altered.
10.6 External Signal Description
The only external signals which affect the RTC are the 32.768 kHz oscillator crystal pins XTAL_32K and
EXTAL_32K when the oscillator is in use.
10.7 Register Definitions
The RTC includes a status and control register, an 16-bit counter register, and an 16-bit modulo register.
The register addresses are located in the High-Page Register map, and Table 10-2 lists address versus
register mnemonic.
Table 10-2. RTC Register Address Map
Register
Address
RTCCSC
0x1828
0x1829
RTCCNTL
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
10-5
Real-Time Counter (RTC)
Table 10-2. RTC Register Address Map (continued)
Register
Address
RTCMODL
RTCCNTH
RTCMODH
0x182A
0x182B
0x182C
NOTE
The RTC register map for the MC13234/MC13237 is an anomaly to
68HC08 standard address mapping. Normally for two-byte wide registers
such as the RTCCNT and RTCMOD, the most significant byte of the
variable is located at the lower address of two adjacent locations and the
least significant byte is at the higher address. Both the RTCCNT and
RTCMOD violate this model as observed in Table 10-2.
10.7.1 RTC Status and Control Register (RTCSC)
RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time
interrupt enable bit (RTIE), and the prescaler select bits (RTCPS).
RTCSC
0x1828
7
6
5
4
3
2
1
0
R
W
RTIF
RTCLKS
RTIE
RTCPS
Reset:
0
0
0
0
0
0
0
0
Figure 10-2. RTC Status and Control Register (RTCSC)
Table 10-3. RTCSC Field Descriptions
Description
Field
7
RTIF
Real-Time Interrupt Flag— This status bit indicates the RTC counter register reached the value in the RTC
modulo register. Writing a logic 0 has no effect. Writing a logic 1 clears the bit and the real-time interrupt request.
0 RTC counter has not reached the value in the RTC modulo register
1 RTC counter has reached the value in the RTC modulo register.
6:5
Real-Time Clock Source Select — These two read/write bits select the clock source input to the RTC
RTCLKS[1:0] prescaler. Changing the clock source clears the prescaler and RTCCNT counters.
00 Real-time clock source is 1kHz
01 Real-time clock source is XOSC2 (32.MHz)
10 Real-time clock source is XOSC1 (32.768kHz)
11 Real-time clock source is XOSC1 (32.768kHz)
MC13234/MC13237 Reference Manual, Rev. 1.8
10-6
Freescale Semiconductor
Real-Time Counter (RTC)
Table 10-3. RTCSC Field Descriptions (continued)
Description
Field
4
Real-Time Interrupt Enable — This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt
is generated when RTIF is set.
RTIE
0 Real-time interrupt requests are disabled.
1 Real-time interrupt requests are enabled.
3:0
Real-Time Clock Prescaler Select — These four read/write bits and RTCLKS[0] select binary-based or
RTCPS[3:0] decimal-based divide-by values for the clock source. See Table 10-4. Changing the prescaler value clears the
prescaler and RTCCNT counters.
Table 10-4. RTC Prescaler Divide-By Values
RTCPS
RTCLKS[0]
0
1
2
3
4
5
6
7
8
9
10
22
11
10
12
24
13
102
14
5x102 103
2x105
15
0
1
OFF 23
25
211
26
212
27
213
28
29
210
1
2
OFF 210
214 215 216 103 2x103 5x103 104 2x104 5x104 105
10.7.2 RTC Counter Registers (RTCCNTH and RTCCNTL)
RTCCNT[15:0], which is equal to {RTCCNTH[7:0], RTCCNTL[7:0]}, is the read-only value of the
current count of the 16-bit RTC counter.
Figure 10-3. RTC Counter Register (RTCCNT)
RTCCNTH
0x182B
7
6
5
4
3
2
1
0
R
W
RTCCNTH[7:0]
Reset:
0
0
0
0
0
0
0
0
RTCCNTL
0x1829
7
6
5
4
3
2
1
0
R
W
RTCCNTL[7:0]
Reset:
0
0
0
0
0
0
0
0
Figure 10-4. RTC Counter Register (RTCCNT)
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
10-7
Real-Time Counter (RTC)
Table 10-5. RTCCNT Field Description
Description
Field
RTCCNT[15:0] RTC Count — These sixteen read-only bits contain the current value of the 16-bit RTC counter. Writes have
no effect to this register. Writing to RTCMOD or writing different values to RTCLKS and RTCPS clear the
count to 0x0000.
10.7.3 RTC Modulo Registers (RTCMODH and RTCMODL)
RTCMOD[15:0], which is equal to {RTCMODH[7:0], RTCMODL[7:0]}, is the modulo value against
which the RTC counter is compared. The RTCMOD is loaded as a 16-bit value and requires that both
registers be written before the 16-bit value is updated. The RTCMODH (high byte) should be written first
and it gets latched. The RTCMODL (low byte) should then be written and causes the 2-byte value to be
written to the RTCMOD register.
RTCMODH
0x182C
7
6
5
4
3
2
1
0
R
W
RTCMODH
Reset:
0
0
0
0
0
0
0
0
RTCMODL
0x182A
7
6
5
4
3
2
1
0
R
W
RTCMODL
Reset:
0
0
0
0
0
0
0
0
Figure 10-5. RTC Modulo Register (RTCMOD)
Table 10-6. RTCMOD Field Descriptions
Description
Field
RTC Modulo — These sixteen read/write bits contain the modulo value used to reset the count to
RTCMOD[15:0] 0x0000 upon a compare match and set the RTIF status bit. A value of 0x0000 sets the RTIF bit on each
rising edge of the prescaler output. Writing to RTCMOD resets the prescaler and the RTCCNT counters
to 0x0000.
MC13234/MC13237 Reference Manual, Rev. 1.8
10-8
Freescale Semiconductor
Chapter 11
Modules (KBIx)
11.1 Introduction
There are two KBI modules. One has eight keyboard interrupt inputs that share port B pins. The other KBI
module has four inputs that are shared on the four (4) port C pins. See the Pins and Connections chapter
for more information about the logic and hardware aspects of these pins.
Port B is an 8-bit port that is shared between the KBI1 keyboard interrupt inputs and general-purpose I/O.
The eight KBI1PEn control bits in the KBI1PE register allow selection of any combination of port B pins
to be assigned as KBI1 inputs. Any pins that are enabled as KBI1 inputs will be forced to act as inputs and
the remaining port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD),
data direction (PTBDD) and pullup enable (PTBPE) registers. The eight PTBPEn control bits in the PTBPE
register allow the user to select whether an internal pullup device is enabled on each port B pin that is
configured as a port input or a KBI1 input.
KBI1 inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of
port B are falling-edge/low-level sensitive and bits 7 through 4 can be configured for rising-edge /
high-level or for falling-edge/low-level sensitivity.
Port C is an 8-bit port with its four pins shared between the KBI2 keyboard interrupt inputs and
general-purpose I/O. The four KBI2PEn control bits in the KBI2PE register allow selection of any
combination of the lower four port C pins to be assigned as KBI2 inputs. Any pins that are enabled as KBI2
inputs will be forced to act as inputs and the remaining port C pins are available as general-purpose I/O
pins controlled by the port C data (PTCD), data direction (PTCDD) and pullup enable (PTCPE) registers.
The eight PTCPEn control bits in the PTCPE register allow the user to select whether an internal pullup
device is enabled on each port C pin that is configured as a port input or a KBI2 input.
Any enabled keyboard interrupt can be used to wake the MCU from wait or standby (STOP3). Either KBI1
or KBI2 can be used to wake the MCU from wait or standby (STOP3). The KBF bits for both KBI modules
must be cleared before entering Stop3 mode, regardless of whether the interrupt is enabled.
Note that MC13237 contains only the KBI1 module. MC13234 contains both KBI1 and KBI2.
11.1.1 KBI Clock Gating
The bus clock to the KBI can be gated on and off using the KBI1/KBI2 bits in SCGC2. These bits are set
after any reset, which enables the bus clock to these modules. To conserve power, the KBI1/KBI2 bits can
be cleared to disable the clock to these modules when not in use.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
11-1
Modules (KBIx)
11.1.2 Features
The KBI features include:
•
•
•
KBI1 with up to eight keyboard interrupt pins with individual pin enable bits.
KBI2 with four keyboard interrupt pins with individual pin enable bits.
Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling
edge and low level (or both rising edge and high level) interrupt sensitivity.
•
•
Independent software enabled keyboard interrupt for both KBI1 and KBI2.
Exit from low-power modes.
11.1.3 Modes of Operation
This section defines the KBI operation in wait, stop, and background debug modes.
11.1.3.1 KBI in Wait Mode
The KBIx continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore,
an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is
enabled (KBIE = 1).
11.1.3.2 KBI in Stop Modes
The KBIx operates asynchronously in STOP3 mode if enabled before executing the STOP instruction.
Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of STOP3 mode if the KBI
interrupt is enabled (KBIE = 1).
11.1.3.3 KBI in Active Background Mode
When the microcontroller is in active background mode, the KBI will continue to operate normally.
11.1.4 Block Diagram
The block diagram for the keyboard interrupt module is shown Figure 11-1.
MC13234/MC13237 Reference Manual, Rev. 1.8
11-2
Freescale Semiconductor
Modules (KBIx)
BUSCLK
KBACK
VDD
1
0
RESET
KBF
KBIP0
CLR
Q
S
KBIPE0
KBIPEn
D
SYNCHRONIZER
STOP BYPASS
CK
KBEDG0
KEYBOARD
INTERRUPT FF
KBI
STOP
INTERRU
PT
1
0
KBIPn
KBMOD
S
KBIE
KBEDGn
Figure 11-1. Havasu USB Architectural Definition Document Block Diagram
11.1.5 External Signal Description
The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt
requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high
level interrupt requests.
Table 11-1. KBI1 Pin Mapping
Port pin PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
KBI1 pin KBI1P7
KBI1P6
KBI1P5
KBI1P4
KBI1P3
KBI1P2
KBI1P1
KBI1P0
Table 11-2. KBI2 Pin Mapping
Port pin
KBI2 pin
PTC3
PTC2
PTC1
PTC0
KBI2P3
KBI2P2
KBI2P1
KBI2P0
11.1.6 Register Definition
Each KBI includes three registers:
•
•
•
An 8-bit pin status and control register.
An 8-bit pin enable register.
An 8-bit edge select register.
KBI2 has four ports (KBI2P0–KBI2P3). These are available only in MC13234.
Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments
for all KBI registers. This section refers to registers and control bits only by their names and relative
address offsets.
Some MCUs may have more than one KBI, so register names include placeholder characters to identify
which KBI is being referenced.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
11-3
Modules (KBIx)
11.1.6.1 KBI Interrupt Status and Control Register (KBIxSC)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
KBF
0
KBIE
KBIMOD
KBACK
0
Reset:
0
0
0
0
0
0
0
Figure 11-2. KBI Interrupt Status and Control Register (KBIxSC)
Table 11-3. KBIxSC Register Field Descriptions
Field
Description
3
KBI Interrupt Flag — KBF indicates when a KBI interrupt is detected. Writes have no effect on KBF.
KBF
0 No KBI interrupt detected.
1 KBI interrupt detected.
2
KBI Interrupt Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always
KBACK
reads as 0.
1
KBI Interrupt Enable — KBIE determines whether a KBI interrupt is requested.
0 KBI interrupt request not enabled.
KBIE
1 KBI interrupt request enabled.
0
KBI Detection Mode — KBIMOD (along with the KBIES bits) controls the detection mode of the KBI interrupt
KBIMOD
pins.
0 KBI pins detect edges only.
1 KBI pins detect both edges and levels.
11.1.6.2 KBI Interrupt Pin Select Register (KBIxPE)
7
6
5
4
3
2
1
0
R
W
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
Reset:
0
0
0
0
0
0
0
0
Figure 11-3. KBI Interrupt Pin Select Register (KBIxPE)
Table 11-4. KBIxPE Register Field Descriptions
Field
Description
7:0
KBI Interrupt Pin Selects — Each of the KBIPEn bits enable the corresponding KBI interrupt pin.
KBIPE[7:0] 0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
MC13234/MC13237 Reference Manual, Rev. 1.8
11-4
Freescale Semiconductor
Modules (KBIx)
11.1.6.3 KBI Interrupt Edge Select Register (KBIxES)
7
6
5
4
3
2
1
0
R
W
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBEDG3
KBEDG2
KBEDG1
KBEDG0
Reset:
0
0
0
0
0
0
0
0
Figure 11-4. KBI Edge Select Register (KBIxES)
Table 11-5. KBIxES Register Field Descriptions
Field
Description
7:0
KBI Edge Selects — Each of the KBEDGn bits serves as selecting a pull-up or pull-down device if enabled.
KBEDG[7:0] 0 A pull-up device is connected to the associated pin.
1 A pull-down device is connected to the associated pin.
11.1.7 Functional Description
Writing to the KBIPEn bits in the keyboard x interrupt pin enable register (KBIxPE) independently enables
or disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based
on the KBIMOD bit in the keyboard interrupt status and control register (KBIxSC). Edge sensitivity can
be software programmed to be either falling or rising; the level can be either low or high. The polarity of
the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge
select register (KBIxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
11.1.7.1 Edge Only Sensitivity
A valid edge on an enabled port pin will set KBF in KBIxSC. If KBIE in KBIxSC is set, an interrupt
request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in
KBIxSC.
11.1.7.2 Edge and Level Sensitivity
A valid edge or level on an enabled port pin will set KBF in KBIxSC. If KBIE in KBIxSC is set, an
interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK
in KBIxSC provided all enabled port inputs are at their deasserted levels. KBF will remain set if any
enabled port pin is asserted while attempting to clear by writing a 1 to KBACK.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
11-5
Modules (KBIx)
11.1.7.3 Pull-up/Pull-down Resistors
The keyboard interrupt pins can be configured to use an internal pull-up/pull-down resistor using the
associated I/O port pull-up enable register. If an internal resistor is enabled, the KBIxES register is used to
select whether the resistor is a pull-up (KBEDGn = 0) or a pull-down (KBEDGn = 1).
11.1.7.4 Keyboard Interrupt Initialization
When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt
request during pin interrupt initialization, the user should do the following:
1. Mask interrupts by clearing KBIE in KBIxSC.
2. If using internal pull-up/pull-down device, configure the associated pull enable bits in KBIxPE.
3. Enable the interrupt pins by setting the appropriate KBIPEn bits in KBIxPE.
4. Write to KBACK in KBIxSC to clear any false interrupts.
Set KBIE in KBIxSC to enable interrupts.
MC13234/MC13237 Reference Manual, Rev. 1.8
11-6
Freescale Semiconductor
Chapter 12
Analog-to-Digital Converter (ADC)
12.1 Introduction
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip. The ADC module is available only in MC13237.
NOTE
The ADCCG bit in SOPT2 must be set for the ADC module to be enabled.
See Section 5.8.5, “System Options Register 2 (SOPT2).”
12.1.1 Features
Features of the ADC module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Linear successive approximation algorithm with 12-bit resolution
Up to 8 analog inputs
Output formatted in 12-, 10-, or 8-bit right-justified unsigned format
Single or continuous conversion (automatic return to idle after single conversion)
Configurable sample time and conversion speed/power
Conversion complete flag and interrupt
Input clock selectable from up to four sources
Operation in wait or Stop3 modes for lower noise operation
Asynchronous clock source for lower noise operation
Selectable asynchronous hardware conversion trigger
Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value
Temperature sensor
Converter subsystem shut-down capability
12.1.2 ADC Module Block Diagram
Figure 12-1 provides a block diagram of the ADC module.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-1
Analog-to-Digital Converter (ADC)
Compare true
3
ADCSC1
ADCCFG
Async
Clock Gen
1
2
ADACK
Bus Clock
ALTCLK
MCU STOP
ADHWT
ADCK
Clock
Divide
Control Sequencer
AD0
AD7
1
2
AIEN
Interrupt
COCO
ADVIN
SAR Converter
VREFH
VREFL
Data Registers
Compare true
ADCSC2
3
Compare
Logic
Compare Value Registers
Figure 12-1. ADC Block Diagram
12.2 External Signal Description
The ADC module supports up to 8 separate analog inputs. It also requires four supply/reference/ground
connections.
Table 12-1. Signal Properties
Name
Function
AD7–AD0
VREFH
Analog Channel inputs
High reference voltage
Low reference voltage
Analog power supply
Analog ground
VREFL
VDDA_ADC
VSSA_ADC
MC13234/MC13237 Reference Manual, Rev. 1.8
12-2
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
12.2.1 Analog Power (VDDA_ADC
)
The ADC analog portion uses V
as its power connection. In some packages, V
is connected
DDA
DDA
internally to V . If externally available, connect the V
pin to the same voltage potential as V
.
DD
DDA
DD
External filtering may be necessary to ensure clean V
for better results.
DDA
12.2.2 Analog Ground (VSSA_ADC
)
The ADC analog portion uses V
as its ground connection. In some packages, V
is connected
SSA
SSA
internally to V . If externally available, connect the V
pin to the same voltage potential as V .
SS
SSA
SS
12.2.3 Voltage Reference High (VREFH
)
V
V
is the high reference voltage for the converter. In some packages, V
is connected internally to
REFH
REFH
. If externally available, V
may be connected to the same potential as V
or may be driven
DDA
REFH
DDA
by an external source between the minimum V
spec and the V
potential (V
must never
DDA
DDA
REFH
exceed V
).
DDA
12.2.4 Voltage Reference Low (VREFL
)
V
V
is the low-reference voltage for the converter. In some packages, V
is connected internally to
REFL
REFL
. If externally available, connect the V
pin to the same voltage potential as V
.
SSA
REFL
SSA
12.2.5 Analog Channel Inputs (ADx)
The ADC module supports up to 8 separate analog inputs. An input is selected for conversion through the
ADCH channel select bits.
12.3 Register Definition
These memory-mapped registers control and monitor operation of the ADC:
•
•
•
•
•
•
Status and control register, ADCSC1
Status and control register, ADCSC2
Data result registers, ADCRH and ADCRL
Compare value registers, ADCCVH and ADCCVL
Configuration register, ADCCFG
1
Pin control registers, APCTLx
1. Number of APCTLx registers depends on the number of external analog inputs available on the device. Please refer to the
introduction of this module for external analog input assignments.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-3
Analog-to-Digital Converter (ADC)
12.3.1 Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).
ADCSC1
0x1870
7
6
5
4
3
2
1
0
R
W
COCO
AIEN
0
ADCO
ADCH
1
Reset:
0
0
1
1
1
1
Figure 12-2. Status and Control Register (ADCSC1)
Table 12-2. ADCSC1 Field Descriptions
Description
Field
7
Conversion Complete Flag — The COCO flag is a read-only bit set each time a conversion is completed when
the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO flag
is set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is
written or when ADCRL is read.
COCO
0 Conversion not completed
1 Conversion completed
6
Interrupt Enable — AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is
high, an interrupt is asserted.
AIEN
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
5
Continuous Conversion Enable — ADCO enables continuous conversions.
ADCO
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
4:0
ADCH
Input Channel Select — The ADCH bits form a 5-bit field that selects one of the input channels. The input
channels are detailed in Table 12-3.
The successive approximation converter subsystem is turned off when the channel select bits are all set. This
feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating
continuous conversions this way prevents an additional, single conversion from being performed. It is not
necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
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Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Table 12-3. ADC Channel Assignment
ADCH
Channel
Input
Pin Control
ADCH
Channel
Input
Pin Control
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
PTD1
PTD2
ADPC0
ADPC1
ADPC2
ADPC3
ADPC4
ADPC5
ADPC6
ADPC7
N/A
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PTD3
PTD4
PTD5
PTD6
PTD7
PTC5
Reserved
Reserved
Reserved
N/A
N/A
Temperature
Sensor1
01011
01100
01101
01110
01111
AD11
AD12
AD13
AD14
AD15
Reserved
Reserved
Reserved
Reserved
Reserved
N/A
N/A
N/A
N/A
N/A
11011
11100
11101
11110
11111
AD27
—
Internal Bandgap
Reserved
VREFH
N/A
N/A
N/A
N/A
N/A
VREFH
VREFL
VREFL
Module
None
Disabled
1
For information, see Section 12.4.8, “Temperature Sensor.”
12.3.2 Status and Control Register 2 (ADCSC2)
The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the
ADC module.
ADCSC2
0x1871
7
6
5
4
3
2
1
0
R
ADACT
0
0
0
0
ADTRG
ACFE
ACFGT
W
Figure 12-3. Status and Control Register 2 (ADCSC2)
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Freescale Semiconductor
12-5
Analog-to-Digital Converter (ADC)
Table 12-4. ADCSC2 Register Field Descriptions
Description
Field
7
Conversion Active — Indicates that a conversion is in progress. ADACT is set when a conversion is initiated
and cleared when a conversion is completed or aborted.
0 Conversion not in progress
ADACT
1 Conversion in progress
6
Conversion Trigger Select — Selects the type of trigger used for initiating a conversion. Two types of triggers
are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated
following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion
of the ADHWT (PTC[6]) input.
ADTRG
0 Software trigger selected
1 Hardware trigger selected
5
Compare Function Enable — Enables the compare function.
0 Compare function disabled
ACFE
1 Compare function enabled
4
Compare Function Greater Than Enable — Configures the compare function to trigger when the result of the
conversion of the input being monitored is greater than or equal to the compare value. The compare function
defaults to triggering when the result of the compare of the input being monitored is less than the compare value.
0 Compare triggers when input is less than compare value
ACFGT
1 Compare triggers when input is greater than or equal to compare value
12.3.3 Data Result High Register (ADCRH)
In 12-bit operation, ADCRH contains the upper four bits of 12-bit conversion data. In 10-bit operation,
ADCRH contains the upper two bits of 10-bit conversion data. In 12-bit and 10-bit mode, ADCRH is
updated each time a conversion completes except when automatic compare is enabled and the compare
condition is not met. When configured for 10-bit mode, ADR[11:10] are cleared. When configured for
8-bit mode, ADR[11:8] are cleared.
When automatic compare is not enabled, the value stored in ADCRH are the upper bits of the conversion
result. When automatic compare is enabled, the conversion result is manipulated as described in
Section 12.4.7, “Automatic Compare Function” prior to storage in ADCRH:ADCRL registers.
In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion
data into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is
completed, the intermediate conversion data is lost. In 8-bit mode, there is no interlocking with ADCRL.
If the MODE bits are changed, any data in ADCRH becomes invalid.
ADCRH
0x1872
7
6
5
4
3
2
1
0
R
W
0
0
0
0
ADR11
ADR10
ADR9
ADR8
Reset:
0
0
0
0
0
0
0
0
Figure 12-4. Data Result High Register (ADCRH)
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12-6
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
12.3.4 Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of a 12-bit or 10-bit conversion data, and all eight bits of 8-bit
conversion data. ADCRL is updated each time a conversion completes except when automatic compare is
enabled and the compare condition is not met.
When automatic compare is not enabled, the value stored in ADCRL is the lower eight bits of the
conversion result. When automatic compare is enabled, the conversion result is manipulated as described
in Section 12.4.7, “Automatic Compare Function” prior to storage in ADCRH:ADCRL registers.
In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion
data into the result registers until ADCRL is read. If ADCRL is not read until the after next conversion is
completed, the intermediate conversion data is lost. In 8-bit mode, there is no interlocking with ADCRH.
If the MODE bits are changed, any data in ADCRL becomes invalid.
ADCRL
0x1873
7
6
5
4
3
2
1
0
R
W
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Reset:
0
0
0
0
0
0
0
0
Figure 12-5. Data Result Low Register (ADCRL)
12.3.5 Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.
ADCCVH
0x1874
7
6
5
4
3
2
1
0
R
W
0
0
0
0
ADCV11
ADCV10
0
ADCV9
ADCV8
Reset:
0
0
0
0
0
0
0
Figure 12-6. Compare Value High Register (ADCCVH)
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Freescale Semiconductor
12-7
Analog-to-Digital Converter (ADC)
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the
compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
12.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower eight bits of the 12-bit or 10-bit compare value or all eight bits of the 8-bit
compare value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower eight
bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode.
ADCCVL
0x1875
7
6
5
4
3
2
1
0
R
W
ADCV7
ADCV6
0
ADCV5
ADCV4
ADCV3
ADCV2
0
ADCV1
ADCV0
Reset:
0
0
0
0
0
0
Figure 12-7. Compare Value Low Register (ADCCVL)
12.3.7 Configuration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and
long sample time.
ADCCFG
0x1876
7
6
5
4
3
2
1
0
R
W
ADLPC
ADIV
ADLSMP
MODE
ADICLK
Reset:
0
0
0
0
0
0
0
0
Figure 12-8. Configuration Register (ADCCFG)
Table 12-5. ADCCFG Register Field Descriptions
Description
Field
7
Low-Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
ADLPC
1 Low power configuration: The power is reduced at the expense of maximum clock speed.
6:5
Clock Divide Select — ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
ADIV
Table 12-6 shows the available clock configurations.
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Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Table 12-5. ADCCFG Register Field Descriptions (continued)
Field
Description
4
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
ADLSMP sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
3:2
Conversion Mode Selection — MODE bits select between 12-, 10-, or 8-bit operation. See Table 12-7.
MODE
1:0
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
ADICLK
Table 12-8.
Table 12-6. Clock Divide Select
ADIV
Divide Ratio
Clock Rate
00
01
10
11
1
2
4
8
Input clock
Input clock 2
Input clock 4
Input clock 8
Table 12-7. Conversion Modes
Mode Description
MODE
00
01
10
11
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
Table 12-8. Input Clock Select
ADICLK
Selected Clock Source
00
01
10
11
Bus clock
Bus clock divided by 2
Alternate clock (32 kHz oscillator)
Asynchronous clock (ADACK)
12.3.8 Pin Control 1 Register (APCTL1)
The pin control registers disable the digital interface to the associated MCU pins used as analog inputs to
reduce digital noise and improve conversion accuracy. APCTL1 controls the pins associated with channels
0–7 of the ADC module.
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Freescale Semiconductor
12-9
Analog-to-Digital Converter (ADC)
Some MCUs may not use all bits implemented in this register. Bits in this register that do not have
associated external analog inputs have no control function. Consult the ADC channel assignment in the
module introduction.
APCTL1
0x1877
7
6
5
4
3
2
1
0
R
W
ADPC7
ADPC6
0
ADPC5
ADPC4
ADPC3
ADPC2
0
ADPC1
ADPC0
Reset:
0
0
0
0
0
0
Figure 12-9. Pin Control 1 Register (APCTL1)
Table 12-9. APCTL1 Register Field Descriptions
Description
Field
7
ADC Pin Control 7 — ADPC7 controls the pin associated with channel AD7.
0 AD7 pin I/O control enabled
ADPC7
1 AD7 pin I/O control disabled
6
ADC Pin Control 6 — ADPC6 controls the pin associated with channel AD6.
0 AD6 pin I/O control enabled
ADPC6
1 AD6 pin I/O control disabled
5
ADC Pin Control 5 — ADPC5 controls the pin associated with channel AD5.
0 AD5 pin I/O control enabled
ADPC5
1 AD5 pin I/O control disabled
4
ADC Pin Control 4 — ADPC4 controls the pin associated with channel AD4.
0 AD4 pin I/O control enabled
ADPC4
1 AD4 pin I/O control disabled
3
ADC Pin Control 3 — ADPC3 controls the pin associated with channel AD3.
0 AD3 pin I/O control enabled
ADPC3
1 AD3 pin I/O control disabled
2
ADC Pin Control 2 — ADPC2 controls the pin associated with channel AD2.
0 AD2 pin I/O control enabled
ADPC2
1 AD2 pin I/O control disabled
1
ADC Pin Control 1 — ADPC1 controls the pin associated with channel AD1.
0 AD1 pin I/O control enabled
ADPC1
1 AD1 pin I/O control disabled
0
ADC Pin Control 0 — ADPC0 controls the pin associated with channel AD0.
0 AD0 pin I/O control enabled
ADPC0
1 AD0 pin I/O control disabled
12.4 Functional Description
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
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Freescale Semiconductor
Analog-to-Digital Converter (ADC)
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. In 12-bit
and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into
a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted by a successive
approximation algorithm into a 9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In
10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In
8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO)
is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
with any of the conversion modes and configurations.
12.4.1 Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
•
The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
•
The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of
the bus clock.
•
•
ALTCLK, as defined for this MCU (See module section introduction).
The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC
module. When selected as the clock source, this clock remains active while the MCU is in wait or
Stop3 mode and allows conversions in these modes for lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC do not perform according to specifications. If the available clocks
are too fast, the clock must be divided to the appropriate frequency. This divider is specified by the ADIV
bits and can be divide-by 1, 2, 4, or 8.
12.4.2 Input Select and Pin Control
The pin control registers (APCTL1) disable the digital interface to I/O of the pins used as analog inputs.
When a pin control register bit is set, the following conditions are forced for the associated MCU pin:
•
•
The output buffer is forced to its high impedance state.
The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
•
The pullup is disabled.
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12-11
Analog-to-Digital Converter (ADC)
12.4.3 Asynchronous and Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
or the local asynchronous clock (ADACK) within the module. The alternate clock, a 32 kHz clock, can be
used for ADC conversion. It has to be enabled in SOMC1 before performing ADC conversion.
12.4.4 Software Trigger
The ADC conversion can be initiated by software trigger. To select the software trigger, ADTRG in the
ADCSC2 register must be set to 0. When software trigger is selected, writes to ADCSC1 will start a new
ADC conversion.
12.4.5 Hardware Trigger
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set. ADHWT is connected to PTC[6] or RTC. The selection between PTC[6] and
RTC for ADHWT is in SOPT1[ADCHT].
When the hardware trigger is enabled (ADTRG=1), a conversion is initiated on the rising edge of
ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is ignored. In continuous
convert configuration, only the initial rising edge to launch continuous conversions is observed. The
hardware trigger function operates in conjunction with any of the conversion modes and configurations.
Figure 12-10. ADC Triggering
Table 12-10.
Trigger Source
ADCSC2[ADTRG]
SOPT1[ADCHT]
Software (ADCSC1)
Software (ADCSC1)
RTC
0
0
1
1
0
1
0
1
PTC[6]
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12-12
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
12.4.6 Conversion Control
Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE
bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be
configured for low power operation, long sample time, continuous conversion, and automatic compare of
the conversion result to a software determined compare value.
12.4.6.1 Initiating Conversions
A conversion is initiated:
•
Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is
selected.
•
•
Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled, a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
12.4.6.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 12-bit or 10-bit MODE (the ADCRH register has
been read but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO
is not set, and the new result is lost. In the case of single conversions with the compare function enabled
and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases
of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of
ADCO (single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
12.4.6.3 Aborting Conversions
Any conversion in progress is aborted when:
•
•
•
A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
The MCU is reset.
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Freescale Semiconductor
12-13
Analog-to-Digital Converter (ADC)
•
The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.
However, they continue to be the values transferred after the completion of the last successful conversion.
If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
12.4.6.4 Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum
value for f
.
ADCK
12.4.6.5 Sample Time and Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (fADCK).
After the module becomes active, sampling of the input begins. ADLSMP selects between short and long
sample times.When sampling is complete, the converter is isolated from the input channel and a successive
approximation algorithm is performed to determine the digital value of the analog signal. The result of the
conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm.
If the bus frequency is less than the f
frequency, precise sample time for continuous conversions
ADCK
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f frequency, precise sample time for continuous conversions cannot be guaranteed when long
ADCK
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 12-11.
Table 12-11. Total Conversion Time vs. Control Conditions
Conversion Type
ADICLK
ADLSMP
Max Total Conversion Time
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
0x, 10
0x, 10
0x, 10
0x, 10
11
0
0
1
1
0
0
1
1
0
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 s + 20 ADCK + 5 bus clock cycles
5 s + 23 ADCK + 5 bus clock cycles
5 s + 40 ADCK + 5 bus clock cycles
5 s + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
11
11
Single or first continuous 10-bit or 12-bit
11
Subsequent continuous 8-bit;
xx
fBUS fADCK
Subsequent continuous 10-bit or 12-bit;
xx
xx
0
1
20 ADCK cycles
37 ADCK cycles
fBUS fADCK
Subsequent continuous 8-bit;
fBUS fADCK/11
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Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Table 12-11. Total Conversion Time vs. Control Conditions
Conversion Type
ADICLK
ADLSMP
Max Total Conversion Time
Subsequent continuous 10-bit or 12-bit;
xx
1
40 ADCK cycles
fBUS fADCK/11
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
23 ADCK Cyc
8 MHz/1
5 bus Cyc
8 MHz
+
Conversion time =
= 3.5 s
Number of bus cycles = 3.5 s x 8 MHz = 28 cycles
NOTE
The ADCK frequency must be between f
maximum to meet ADC specifications.
minimum and f
ADCK
ADCK
12.4.7 Automatic Compare Function
The compare function is enabled by the ACFE bit. The compare function can be configured to check for
an upper or lower limit. After the input is sampled and converted, the compare value (ADCCVH and
ADCCVL) is subtracted from the conversion result.When comparing to an upper limit (ACFGT = 1), if
the conversion result is greater-than or equal-to the compare value, COCO is set. When comparing to a
lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. An ADC interrupt is
generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
The subtract operation of two positive values (the conversion result less the compare value) results in a
signed value that is 1-bit wider than the bit-width of the two terms. The final value transferred to the
ADCRH and ADCRL registers is the result of the subtraction operation, excluding the sign bit. The value
of the sign bit can be derived based on ACFGT control setting. When ACFGT=1, the sign bit of any value
stored in ADCRH and ADCRL is always 0, indicating a positive result for the subtract operation. When
ACFGT = 1, the sign bit of any result is always 1, indicating a negative result for the subtract operation.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers.
NOTE
The compare function can monitor the voltage on a channel while the MCU
is in Wait or Stop3 mode. The ADC interrupt wakes the MCU when the
compare condition is met.
An example of compare operation eases understanding of the compare feature. If the ADC is configured
for 10-bit operation, ACFGT=0, and ADCCVH:ADCCVL= 0x200, then a conversion result of 0x080
causes the compare condition to be met and the COCO bit is set. A value of 0x280 is stored in
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12-15
Analog-to-Digital Converter (ADC)
ADCRH:ADCRL. This is signed data without the sign bit and must be combined with a derived sign bit
to have meaning. The value stored in ADCRH:ADCRL is calculated as follows.
The value to interpret from the data is (Result – Compare Value) = (0x080 – 0x200) = –0x180. A standard
method for handling subtraction is to convert the second term to its 2’s complement, and then add the two
terms. First calculate the 2’s complement of 0x200 by complementing each bit and adding 1. Note that
prior to complementing, a sign bit of 0 is added so that the 10-bit compare value becomes a 11-bit signed
value that is always positive.
%101 1111 1111
%1
<= 1’s complement of 0x200 compare value
+
---------------
%110 0000 0000
<= 2’s complement of 0x200 compare value
Then the conversion result of 0x080 is added to 2’s complement of 0x200:
%000 1000 0000
+
%110 0000 0000
---------------
%110 1000 0000
<= Subtraction result is –0x180 in signed 11-bit data
The subtraction result is an 11-bit signed value. The lower 10 bits (0x280) are stored in ADCRH:ADCRL.
The sign bit is known to be 1 (negative) because the ACFGT=0, the COCO bit was set, and conversion
data was updated in ADCRH:ADCRL.
A simpler way to use the data stored in ADCRH:ADCRL is to apply the following rules. When comparing
for upper limit (ACFGT=1), the value in ADCRH:ADCRL is a positive value and does not need to be
manipulated. This value is the difference between the conversion result and the compare value. When
comparing for lower limit (ACFGT=0), ADCRH:ADCRL is a negative value without the sign bit. If the
value from these registers is complemented and then a value of 1 is added, then the calculated value is the
unsigned (i.e., absolute) difference between the conversion result and the compare value. In the previous
example, 0x280 is stored in ADCRH:ADCRL. The following example shows how the absolute value of
the difference is calculated.
%01 0111 1111 <= Complement of 10-bit value stored in ADCRH:ADCRL
+
%1
---------------
%01 1000 0000<= Unsigned value 0x180 is the absolute value of (Result - Compare Value)
12.4.8 Temperature Sensor
The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs. Equation 12-1 provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((V
-V
) m)
TEMP25
Eqn. 12-1
TEMP
where:
— V
— V
is the voltage of the temperature sensor channel at the ambient temperature.
TEMP
is the voltage of the temperature sensor channel at 25C.
TEMP25
MC13234/MC13237 Reference Manual, Rev. 1.8
12-16
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
— m is the hot or cold voltage versus temperature slope in V/C.
For temperature calculations, use the V and m values from the ADC Electricals table.
TEMP25
In application code, the user reads the temperature sensor channel, calculates V
, and compares to
TEMP
V
. If V
is greater than V
the cold slope value is applied in Equation 12-1. If V
is
TEMP25
TEMP
TEMP25
TEMP
less than V
the hot slope value is applied in Equation 12-1.
TEMP25
12.4.9 MCU Wait Mode Operation
Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock
sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until
completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger
or if continuous conversions are enabled.
The bus clock, bus clock divided by two, asynchronous clock, and alternate clock are available as
conversion clock sources while in Wait mode.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait
mode if the ADC interrupt is enabled (AIEN = 1).
12.4.10 MCU Stop3 Mode Operation
Stop3 mode is a low power-consumption standby mode during which most or all clock sources on the
MCU are disabled.
12.4.10.1 Stop3 Mode With ADACK Disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction
aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL
are unaffected by Stop3 mode. After exiting from Stop3 mode, a software or hardware trigger is required
to resume conversions.
12.4.10.2 Stop3 Mode With ADACK Enabled
If ADACK is selected as the conversion clock, the ADC continues operation during Stop3 mode. For
guaranteed ADC operation, the MCU’s voltage regulator must remain active during Stop3 mode. Consult
the module introduction for configuration information for this MCU.
If a conversion is in progress when the MCU enters Stop3 mode, it continues until completion.
Conversions can be initiated while the MCU is in Stop3 mode by means of the hardware trigger or if
continuous conversions are enabled.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from Stop3
mode if the ADC interrupt is enabled (AIEN = 1).
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-17
Analog-to-Digital Converter (ADC)
NOTE
The ADC module can wake the system from low-power stop and cause the
MCU to begin consuming run-level currents without generating a system
level interrupt. To prevent this scenario, software should ensure the data
transfer blocking mechanism (discussed in Section 12.4.6.2, “Completing
Conversions) is cleared when entering Stop3 and continuing ADC
conversions.
12.5 Initialization Information
This section gives an example that provides some basic direction on how to initialize and configure the
ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous
conversion, and a polled or interrupt approach, among many other options. Refer to Table 12-6,
Table 12-7, and Table 12-8 for information used in this example.
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.
12.5.1 ADC Module Initialization Example
12.5.1.1 Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
12.5.1.2 Pseudo-Code Example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7
Bit 6:5 ADIV
Bit 4
ADLPC
1
00
1
Configures for low power (lowers maximum clock speed)
Sets the ADCK to the input clock 1
Configures for long sample time
ADLSMP
Bit 3:2 MODE
Bit 1:0 ADICLK
10
00
Sets mode at 10-bit conversions
Selects bus clock as input clock source
MC13234/MC13237 Reference Manual, Rev. 1.8
12-18
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
ADCSC2 = 0x00 (%00000000)
Bit 7
Bit 6
Bit 5
ADACT
ADTRG
ACFE
0
0
0
Flag indicates if a conversion is in progress
Software trigger selected
Compare function disabled
Bit 4
ACFGT
0
Not used in this example
Bit 3:2
Bit 1:0
00
00
Reserved, always reads zero
Reserved for Freescale’s internal use; always write zero
ADCSC1 = 0x41 (%01000001)
Bit 7
Bit 6
Bit 5
COCO
AIEN
ADCO
0
1
0
Read-only flag which is set when a conversion completes
Conversion complete interrupt enabled
One conversion only (continuous conversions disabled)
Input channel 1 selected as ADC input channel
Bit 4:0 ADCH
00001
ADCRH/L = 0xxx
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that
conversion data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
Holds compare value when compare function enabled
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
APCTL2=0x00
All other AD pins remain general purpose I/O pins
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-19
Analog-to-Digital Converter (ADC)
Reset
Initialize ADC
ADCCFG = 0x98
ADCSC2 = 0x00
ADCSC1 = 0x41
No
Check
COCO=1?
Yes
Read ADCRH
Then ADCRL To
Clear COCO Bit
Continue
Figure 12-11. Initialization Flowchart for Example
12.6 Application Information
This section contains information for using the ADC module in applications. The ADC has been designed
to be integrated into a microcontroller for use in embedded control applications requiring an A/D
converter.
12.6.1 External Pins and Routing
The following sections discuss the external pins associated with the ADC module and how they should be
used for best results.
12.6.1.1 Analog Supply Pins
The ADC module has analog power and ground supplies (V
and V
) available as separate
DDA_ADC
SSA_ADC
pins on some devices. V
is shared on the same pin as the MCU digital V on some devices. On
SSA_ADC
SS
other devices, V
and V
are shared with the MCU digital supply pins. In these cases,
SSA_ADC
DDA_ADC
there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply
so that some degree of isolation between the supplies is maintained.
MC13234/MC13237 Reference Manual, Rev. 1.8
12-20
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
When available on a separate pin, both V
and V
must be connected to the same voltage
SSA_ADC
DDA_ADC
potential as their corresponding MCU digital supply (V and V ) and must be routed carefully for
DD
SS
maximum noise immunity and bypass capacitors placed as near as possible to the package.
If separate power supplies are used for analog and digital power, the ground connection between these
supplies must be at the V
pin. This should be the only ground connection between these supplies
SSA_ADC
if possible. The V
pin makes a good single point ground location.
SSA_ADC
12.6.1.2 Analog Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The
high reference is V
, which may be shared on the same pin as V
on some devices. The low
REFH
DDA_ADC
reference is V
, which may be shared on the same pin as V
on some devices.
REFL
SSA_ADC
When available on a separate pin, V
may be connected to the same potential as V
, or may
REFH
DDA_ADC
be driven by an external source between the minimum V
spec and the V
potential
DDA_ADC
DDA_ADC
(V
must never exceed V
). When available on a separate pin, V
must be connected to
REFH
DDA_ADC
REFL
the same voltage potential as V
. V
and V
must be routed carefully for maximum noise
SSA_ADC
REFH
REFL
immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the V
and V
loop. The best external component to meet this
REFH
REFL
current demand is a 0.1 F capacitor with good high frequency characteristics. This capacitor is connected
between V and V and must be placed as near as possible to the package pins. Resistance in the
REFH
REFL
path is not recommended because the current causes a voltage drop that could result in conversion errors.
Inductance in this path must be minimum (parasitic only).
12.6.1.3 Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer is in its high impedance state and the pullup is disabled. Also, the input buffer
draws DC current when its input is not at V or V . Setting the pin control register bits for all pins used
DD
SS
as analog inputs should be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01 F capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to V
.
SSA_ADC
For proper conversion, the input voltage must fall between V
and V
. If the input is equal to or
REFH
REFL
exceeds V
, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF
REFH
(full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less
than V , the converter circuit converts it to 0x000. Input voltages between V and V are
REFL
REFH
REFL
straight-line linear conversions. There is a brief current associated with V
when the sampling
REFL
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-21
Analog-to-Digital Converter (ADC)
capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or
23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
12.6.2 Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
12.6.2.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R ) is kept
AS
below 2 k.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
12.6.2.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R ) is high.
AS
N
If this error cannot be tolerated by the application, keep R lower than V
/ (2 *I
) for less
AS
DDA_ADC
LEAK
than 1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
12.6.2.3 Noise-Induced Errors
System noise that occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
•
•
•
There is a 0.1 F low-ESR capacitor from V
There is a 0.1 F low-ESR capacitor from V
If inductive isolation is used from the primary supply, an additional 1 F capacitor is placed from
to V
.
REFL
REFH
DDA
to V
.
SSA
V
to V
.
DDA_ADC
SSA_ADC
•
•
V
(and V
, if connected) is connected to V at a quiet point in the ground plane.
REFL SS
SSA_ADC
Operate the MCU in wait or Stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to ADCSC1 with a wait
instruction or stop instruction.
— For Stop3 mode operation, select ADACK as the clock source. Operation in Stop3 reduces V
noise but increases effective conversion time due to stop recovery.
DD
•
There is no I/O switching, input or output, on the MCU during the conversion.
MC13234/MC13237 Reference Manual, Rev. 1.8
12-22
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
DD
Wait or Stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
•
•
•
Place a 0.01 F capacitor (C ) on the selected input channel to V
or V
(this
AS
REFL
SSA_ADC
improves noise issues, but affects the sample rate based on the external analog source resistance).
Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
12.6.2.4 Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1LSB, is:
N
1 lsb = (V
- V
) / 2
REFL
Eqn. 12-2
REFH
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be
1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion is
only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
For 12-bit conversions the code transitions only after the full code width is present, so the quantization
error is 1 lsb to 0 lsb and the code width of each step is 1 lsb.
12.6.2.5 Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
•
•
•
Zero-scale error (E ) (sometimes called offset) — This error is defined as the difference between
ZS
the actual code width of the first conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit
modes and 1 lsb in 12-bit mode). If the first conversion is 0x001, the difference between the actual
0x001 code width and its ideal (1 lsb) is used.
Full-scale error (E ) — This error is defined as the difference between the actual code width of
FS
the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1LSB in 12-bit
mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its
ideal (1LSB) is used.
Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
12-23
Analog-to-Digital Converter (ADC)
•
•
Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function and includes all forms of error.
12.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
converter yields the lower code (and vice-versa). However, even small amounts of system noise can cause
the converter to be indeterminate (between two codes) for a range of input voltages around the transition
voltage. This range is normally around ±1/2 lsb in 8-bit or 10-bit mode, or around 2 lsb in 12-bit mode,
and increases with noise.
This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the
techniques discussed in Section 12.6.2.3 reduces this error.
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a
higher input voltage. Missing codes are those values never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes.
MC13234/MC13237 Reference Manual, Rev. 1.8
12-24
Freescale Semiconductor
Chapter 13
Inter-integrate Circuit (IIC)
13.1 Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of 800 kps (max bus clock/20), with reduced
bus loading. The maximum communication length and the number of devices that can be connected are
limited by a maximum bus capacitance of 400 pF.
NOTE
The SDA and SCL should not be driven above V . These pins are pseudo
DD
open-drain containing a protection diode to V
.
DD
13.1.1 Features
The IIC includes these distinctive features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Compatible with IIC bus standard
Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus busy detection{iic_bus_busy.asm}
General call recognition
10-bit address extension
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
13-1
Inter-integrate Circuit (IIC)
13.1.2 Block Diagram
Figure 13-1 is a block diagram of the IIC
.
ADDRESS
DATA BUS
DATA_MUX
INTERRUPT
ADDR_DECODE
CTRL_REG
FREQ_REG
ADDR_REG
STATUS_REG
DATA_REG
INPUT
SYNC
IN/OUT
DATA
SHIFT
START
STOP
ARBITRATION
CONTROL
REGISTER
CLOCK
ADDRESS
COMPARE
CONTROL
SDA
SCL
Figure 13-1. IIC Functional Block Diagram
13.2 External Signal Description
This section describes the two IIC external signals.
1. SCL — Serial Clock Line; the bidirectional SCL is the serial clock line of the IIC system.
2. SDA — Serial Data Line; the bidirectional SDA is the serial data line of the IIC system..
MC13234/MC13237 Reference Manual, Rev. 1.8
13-2
Freescale Semiconductor
Inter-integrate Circuit (IIC)
13.3 Register Definitions
This section describes the IIC control and status registers. The register addresses are located in the
Direct-Page Register map.
Table 13-1. Module Memory Map
Address
Use
Access
0x006A
0x006B
0x006C
0x006D
0x006E
0x006F
IIC Address Register (IIC1A)
IIC Frequency Divider Register (IIC1F)
IIC Control Register (IIC1C1)
IIC Status Register (IIC1S)
read/write
read/write
read/write
read
IIC Data IO Register (IIC1D)
read/write
read/write
IIC Control Register 2 (IIC1C2)
13.3.1 IIC Address Register (IIC1A)
IIC1A is the slave address register for the module.
IIC1A
0x006A
7
6
5
4
3
2
1
0
R
W
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-2. IIC Address Register (IIC1A)
Table 13-2. IIC1A Field Descriptions
Description
Field
7:1
Slave Address — The AD[7:1] field contains the slave address to be used by the IIC module. This field is used
AD[7:1]
in the 7-bit address scheme and as the lower seven bits of the 10-bit address scheme.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
13-3
Inter-integrate Circuit (IIC)
13.3.2 IIC Frequency Divider Register (IIC1F)
IIC1F register controls generation of the IIC bus baud clock and bus timing. The IIC module clock is
driven from the bus clock (always 1/2 CPU clock) which is typically 16 MHz for the MC13234/MC13237.
As may be required for variable bus loading, it is possible to “tune” the bus hold times. The register
contains two fields used for varying the bus baud rate and hold timing:
1. IIC Multiplier Factor (MULT[1:0]) - this 2-bit field selects a “Mul” multiplication factor as shown
in Table 13-3.
Table 13-3. IIC Multiplication Factor
MULT[1:0]
Mul
00
01
10
11
1 Times
2 Times
4 Times
Reserved
2. IIC Clock Rate (ICR[5:0]) - this 6-bit field programs and selects four hardware factors (see
Table 13-6) that along with the MUL factor determine IIC baud rate and bus hold times. These
factors are:
— SCL_Divider - multiplied by multiplier factor Mul, is used to generate IIC baud rate:
IIC baud rate = bus speed (Hz) / (Mul * SCL_Divider)
Eqn. 13-1
— SDA_Hold_Value - SDA hold time is the delay from the falling edge of SDA (IIC data) to the
changing of SDA (IIC data) and is calculated as follows:
SDA hold time = bus period (s) * (Mul * SDA_Hold_Value)
Eqn. 13-2
— SCL_Start_Hold_Value - SCL Start hold time is the delay from the falling edge of SDA (IIC
data) while SCL is high (Start condition) to the falling edge of SCL (IIC clock) and is calculated
as follows:
SCL Start hold time = bus period (s) * (Mul * SCL_Start_Hold_Value)
Eqn. 13-3
— SCL_Stop_Hold_Value - SCL Stop hold time is the delay from the rising edge of SCL (IIC
clock) to the rising edge of SDA (IIC data) while SCL is high (Stop condition) and is calculated
as follows:
SCL Stop hold time = bus period (s) * (Mul * SCL_Stop_Hold_Value)
Eqn. 13-4
Table 13-4 shows the possible hold time values with different ICR and MULT selections to achieve an IIC
baud rate of 100 kbps using a 16 MHz bus clock.
MC13234/MC13237 Reference Manual, Rev. 1.8
13-4
Freescale Semiconductor
Inter-integrate Circuit (IIC)
Table 13-4. IIC Hold Times for 100 kbps Baud Rate and 16 MHz Bus Clock
Hold times (s)
MULT[1:0]
ICR
SDA
SCL Start
SCL Stop
0x2 (Mul = 4)
0x2 (Mul = 4)
0x1 (Mul = 2)
0x1 (Mul = 2)
0x0 (Mul = 1)
0x0 (Mul = 1)
0x07
0x0B
0x14
0x18
0x1D
0x20
2.50
2.25
2.12
1.12
1.56
1.06
4.00
4.00
4.25
4.75
4.88
4.88
5.25
5.25
5.12
5.12
5.06
5.06
IIC1F
0x006B
7
6
5
4
3
2
1
0
R
W
MULT
ICR
Reset
0
0
0
0
0
0
0
0
Figure 13-3. IIC Frequency Divider Register (IIC1F)
Table 13-5. IIC1F Field Descriptions
Description
Field
7:6
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
MULT[1:0] divider to generate the IIC baud rate. See Table 13-3
5:0
ICR[5:0]
IIC Clock Rate — The ICR bits are used to pre scale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time. Table 13-6 provides the SCL divider and hold values for corresponding values of the ICR.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
13-5
Inter-integrate Circuit (IIC)
Table 13-6. IIC Divider and Hold Values versus ICR Field Setting
SCL_
Start_
Hold_
Value
SDA_
Stop_
Hold_
Value
SCL_
Start_
Hold_
Value
SDA_
Stop_
Hold_
Value
SDA_
Hold_
Value
SDA_
Hold_
Value
ICR
(hex)
SCL_
Divider
ICR
(hex)
SCL_
Divider
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
20
22
7
7
6
7
11
12
13
14
15
16
18
21
15
17
19
21
23
25
29
35
25
29
33
37
41
45
53
65
41
49
57
65
73
81
97
121
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
160
192
17
17
78
94
81
97
24
8
8
224
33
110
126
142
158
190
238
158
190
222
254
286
318
382
478
318
382
446
510
574
638
766
958
638
766
894
1022
1150
1278
1534
1918
113
129
145
161
193
241
161
193
225
257
289
321
385
481
321
385
449
513
577
641
769
961
641
769
897
1025
1153
1281
1537
1921
26
8
9
256
33
28
9
10
11
13
16
10
12
14
16
18
20
24
30
18
22
26
30
34
38
46
58
38
46
54
62
70
78
94
118
288
49
30
9
320
49
34
10
10
7
384
65
40
480
65
28
320
33
32
7
384
33
36
9
448
65
40
9
512
65
44
11
11
13
13
9
576
97
48
640
97
56
768
129
129
65
68
960
48
640
56
9
768
65
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
64
13
13
17
17
21
21
9
896
129
129
193
193
257
257
129
129
257
257
385
385
513
513
72
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
80
88
104
128
80
96
9
112
128
144
160
192
240
17
17
25
25
33
33
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Freescale Semiconductor
Inter-integrate Circuit (IIC)
13.3.3 IIC Control Register (IIC1C1)
IIC1C1 if the primary of two control registers for the IIC module.
IIC1C1
0x006C
7
6
5
4
3
2
1
0
R
W
0
0
0
IICEN
IICIE
MST
TX
TXAK
RSTA
0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-4. IIC Control Register (IIC1C1)
Table 13-7. IIC1C1 Field Descriptions
Description
Field
7
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
IICEN
0 IIC is not enabled.
1 IIC is enabled.
6
IICIE
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
5
Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus
MST
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave mode.
1 Master mode.
4
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
TX
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
3
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
TXAK
0 An acknowledge signal will be sent out to the bus after receiving one data byte.
1 No acknowledge signal response is sent.
2
Repeat START — Writing a 1 to this bit will generate a repeated START condition provided it is the current
master. This bit will always be read as a low{iic_reg.asm}. Attempting a repeat at the wrong time will result in loss
of arbitration.
RSTA
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Freescale Semiconductor
13-7
Inter-integrate Circuit (IIC)
13.3.4 IIC Status Register (IIC1S)
IIC1S is the status register for the IIC module.
IIC1S
0x006D
7
6
5
4
3
2
1
0
R
W
TCF
BUSY
0
SRW
RXAK
IAAS
ARBL
IICIF
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. IIC Status Register (IIC1S)
Table 13-8. IIC1S Field Descriptions
Description
Field
7
TCF
Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid
during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by
reading the IIC1D register in receive mode or writing to the IIC1D in transmit mode.
0 Transfer in progress.
1 Transfer complete.
6
Addressed as a Slave — The IAAS bit is set when the calling address matches the programmed slave
IAAS
address, or when the GCAEN bit is set and a general call is received. Writing the IIC1C register clears this bit.
0 Not addressed.
1 Addressed as a slave.
5
Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master
mode{iic_bus_busy.asm}. The BUSY bit is set when a START signal is detected and cleared when a STOP
signal is detected{iic_bus_busy.asm}.
BUSY
0 Bus is idle{iic_bus_busy.asm}.
1 Bus is busy{iic_bus_busy.asm}.
4
Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
ARBL
cleared by software, by writing a 1 to it.
0 Standard bus operation.
1 Loss of arbitration.
2
Slave Read Only— When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
SRW
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
MC13234/MC13237 Reference Manual, Rev. 1.8
13-8
Freescale Semiconductor
Inter-integrate Circuit (IIC)
Table 13-8. IIC1S Field Descriptions (continued)
Description
Field
1
IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
IICIF
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
•
•
•
One byte transfer completes
Match of slave address to calling address
Arbitration lost
0 No interrupt pending.
1 Interrupt pending.
0
Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received
after the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no
acknowledge signal is detected.
RXAK
0 Acknowledge received.
1 No acknowledge received.
13.3.5 IIC Data I/O Register (IIC1D)
IIC1D is the data transfer register for the IIC module.
IIC1D
0x006E
7
6
5
4
3
2
1
0
R
W
DATA
Reset
0
0
0
0
0
0
0
0
Figure 13-6. IIC Data I/O Register (IIC1D)
Table 13-9. IIC1D Field Descriptions
Description
Field
7:0
Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
DATA[7:0] significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an in-advertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IIC1C must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IIC1D will not initiate the receive.
Reading the IIC1D will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IIC1D does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IIC1D correctly by reading it back.
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Freescale Semiconductor
13-9
Inter-integrate Circuit (IIC)
In master transmit mode, the first byte of data written to IIC1D following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
13.3.6 IIC Control Register 2 (IIC1C2)
IIC1C2 is the second of two IIC module control registers.
IIC1C2
0x06F
7
6
5
4
3
2
1
0
R
W
0
0
0
GCAEN
ADEXT
AD[10:8]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-7. IIC Control Register 2 (IIC1C2)
Table 13-10. IIC1C2 Field Descriptions
Description
Field
7
General Call Address Enable — The GCAEN bit enables or disables general call address.
0 General call address is disabled
GCAEN
1 General call address is enabled.
6
Address Extension — The ADEXT bit controls the number of bits used for the slave address.
ADEXT
0 7-bit address scheme
1 10-bit address scheme
2:0
Slave Address[10:8] — The AD[10:8] field contains the upper three bits of the slave address in the 10-bit
AD[10:8]
address scheme. This field is only valid when the ADEXT bit is set.
13.4 Functional Description
This section provides a complete functional description of the IIC module.
13.4.1 IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
•
•
•
•
START signal
Slave address transmission
Data transfer
STOP signal
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Freescale Semiconductor
Inter-integrate Circuit (IIC)
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and shown in Figure 13-8.
MSB
1
LSB
8
MSB
1
LSB
8
SCL
SDA
2
3
4
5
6
7
9
2
3
4
5
6
7
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
START
SIGNAL
CALLING ADDRESS
READ/ACK
WRITE
NO STOP
ACKSIGNAL
BIT
BIT
MSB
LSB
MSB
LSB
8
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
SIGNAL
CALLING ADDRESS
READ/ACK REPEATED
NEW CALLING ADDRESS
READ/
NO STOP
ACKSIGNAL
BIT
START
WRITE
WRITE
BIT
SIGNAL
Figure 13-8. IIC Bus Transmission Signals
13.4.1.1 START Signal
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logic high),
a master may initiate communication by sending a START signal. As shown in Figure 13-8, a START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
13.4.1.2 Slave Address Transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-8).
No two slaves in the system may have the same address. If the IIC module is the master, it must not
transmit an address that is equal to its own slave address. The IIC cannot be master and slave at the same
time. However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
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Freescale Semiconductor
13-11
Inter-integrate Circuit (IIC)
13.4.1.3 Data Transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 13-8. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the
receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one
complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
•
•
Relinquishes the bus by generating a STOP signal.
Commences a new calling by generating a repeated START signal.
13.4.1.4 STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logic 1 (see Figure 13-8).
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
13.4.1.5 Repeated START Signal
As shown in Figure 13-8, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
13.4.1.6 Arbitration Procedure
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
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Freescale Semiconductor
Inter-integrate Circuit (IIC)
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
13.4.1.7 Clock Synchronization
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 13-9). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
START COUNTING HIGH PERIOD
DELAY
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
Figure 13-9. IIC Clock Synchronization
13.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
13.4.1.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
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Freescale Semiconductor
13-13
Inter-integrate Circuit (IIC)
13.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of
read/write formats are possible within a transfer that includes 10-bit addressing.
13.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed (see Table 13-11). When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own
address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device
will find a match and generate an acknowledge (A1). Each slave that finds a match will compare the eight
bits of the second byte of the slave address with its own address, but only one slave will find a match and
generate an acknowledge (A2). The matching slave will remain addressed by the master until it receives a
STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
Table 13-11. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
Slave Address 1st 7 bits
11110 + AD10 + AD9
R/W
0
Slave Address 2nd byte
AD[8:1]
S
A1
A2
Data
A
...
Data
A/A
P
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
13.4.2.2 Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit (see Table 13-12). Up to and including
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the START condition (S), and tests whether the eighth (R/W) bit is 1. If
there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START
condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices will also compare the first seven bits of the
first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of
them will be addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit
devices) does not match.
Table 13-12. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
Slave Address
1st 7 bits
R/W
Slave
Address
2nd byte
Slave Address
1st 7 bits
R/W
S
A1
A2
Sr
A3
Data
A
...
Data
A
P
11110 + AD10 +
AD9
0
AD[8:1]
11110 + AD10 +
AD9
1
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
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Freescale Semiconductor
Inter-integrate Circuit (IIC)
13.4.3 General Call Address
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches
the general call address as well as its own slave address. When the IIC responds to a general call, it acts as
a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after
the first byte transfer to determine whether the address matches is its own slave address or a general call.
If the value is “00”, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied
from a general call address by not issuing an acknowledgement.
13.4.4 Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
13.4.5 Interrupts
The IIC generates a single interrupt request. The IIC has Interrupt Vector No. 24.
An interrupt from the IIC is generated when any of the events in Table 13-13 occur, provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. The
user can determine the interrupt type by reading the status register.
Table 13-13. Interrupt Summary
Interrupt Source
Status
Flag
Local Enable
Complete 1-byte transfer
Match of received calling address
Arbitration Lost
TCF
IAAS
ARBL
IICIF
IICIF
IICIF
IICIE
IICIE
IICIE
13.4.5.1 Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion
of byte transfer.
13.4.5.2 Address Detect Interrupt
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
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Freescale Semiconductor
13-15
Inter-integrate Circuit (IIC)
13.4.5.3 Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
•
•
SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
•
•
•
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a 1 to it.
13.5 Modes of operation
The IIC is affected by the device mode of operation and the module clock can be disabled:
•
For lower power, the IIC module clock can be disabled via the IIC control bit of the SCGC1
Register
•
LPRun - the reference oscillator is divided by 64 and all clocks are scaled by this factor. It is
recommended to disable the IIC during this mode as all frequencies and timing changes
accordingly.
•
Wait modes - there are two wait modes
— Wait - when entered, the CPU clock is disabled and the bus clock still runs at normal speed .
The IIC, if enabled, will continue to operate normally until an interrupt is required. However,
there will be no new codes or changes of operation while in wait mode, because the CPU is not
operating.
— LP Wait - when entered, the CPU clock is disabled and the bus clock still runs but at a reduced
speed. The IIC, if enabled, will continue to operate, however, all timing would be incorrect.
Operation is not recommended.
•
•
The TPM is disabled in Stop3 mode, regardless of the settings before executing the STOP
instruction.
— During Stop3 mode, clocks to the IIC module are halted. No registers are affected. If Stop3 is
exited with a reset, the IIC will be put into its reset state. If Stop3 is exited with an interrupt,
the IIC will resume operation. It is recommended that the IIC be halted before entering Stop3.
Background Mode Operation -When the microcontroller is in active background mode, the IIC
temporarily suspends until the microcontroller returns to normal user mode.
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Freescale Semiconductor
Chapter 14
Serial Communications Interface (SCI)
14.1 Introduction
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator.
During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and
processes received data.
14.2 Features
Features of SCI module include:
•
•
•
•
•
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable baud rates (13-bit modulo divider)
Fractional baud rates (5-bit divider)
Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
— Active edge on receive pin - can be used for device wake-up
— Break detect supporting LIN
•
•
•
•
•
•
Hardware parity generation and checking
Programmable 8-bit or 9-bit character length
Receiver wake up by idle-line or address-mark
MC13234/MC13237 wake-up capability from Stop3 on an RXD input transition
Optional 13-bit break character generation / 11-bit break character detection
Selectable transmitter output polarity
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Freescale Semiconductor
14-1
Serial Communications Interface (SCI)
14.3 Block Diagrams
Figure 14-2 shows the baud rate generator of the SCI.
SBR[12:0]
Bus
Clock
13-Bit Integer
Counter
Baud
Clock
Divide-by-16
16 x Baud
Clock
5-Bit
Fractional
Counter
BRFA[4:0]
Figure 14-1. SCI Baud Rate Generator
Figure 14-2 shows the transmitter portion of the SCI.
INTERNAL BUS
(WRITE-ONLY)
LOOPS
RSRC
SCID – Tx BUFFER
LOOP
CONTROL
TO RECEIVE
DATA IN
11-BIT TRANSMIT SHIFT REGISTER
M
TO TxD PIN
H
8
7
6
5
4
3
2
1
0
L
1 ¥ BAUD
RATE CLOCK
SHIFT DIRECTION
TXINV
T8
PE
PT
PARITY
GENERATION
SCI CONTROLS TxD
TxD DIRECTION
TE
SBK
TO TxD
PIN LOGIC
TRANSMIT CONTROL
TXDIR
BRK1
TDRE
TIE
Tx INTERRUPT
REQUEST
TC
TCIE
Figure 14-2. SCI Transmitter Block Diagram
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
Serial Communications Interface (SCI)
Figure 14-3 shows the receiver portion of the SCI.
INTERNAL BUS
(READ-ONLY)
SCID – Rx BUFFER
16
BAUD
DIVIDE
BY 16
RATE CLOCK
FROM
TRANSMITTER
11-BIT RECEIVE SHIFT REGISTER
LOOPS
RSRC
SINGLE-WIRE
M
LOOP CONTROL
LBKDE
H
8
7
6
5
4
3
2
1
0
L
FROM RxD PIN
RXINV
DATA RECOVERY
SHIFT DIRECTION
WAKE
ILT
WAKEUP
LOGIC
RWU
RWUID
ACTIVE EDGE
DETECT
RDRF
RIE
IDLE
ILIE
Rx INTERRUPT
REQUEST
LBKDIF
LBKDIE
RXEDGIF
RXEDGIE
OR
ORIE
FE
FEIE
ERROR INTERRUPT
REQUEST
NE
NEIE
PE
PT
PARITY
CHECKING
PE
PEIE
Figure 14-3. SCI Receiver Block Diagram
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Freescale Semiconductor
14-3
Serial Communications Interface (SCI)
14.4 External Signal Description
The UART shares two port pins.
14.4.1 TXD — Transmit Data Output
When the SCI is enabled, this pin is the asynchronous transmit data output.
14.4.2 RXD — Receive Data Input
When the SCI is enabled, this pin is the asynchronous receive data input.
14.5 Functional Description
The SCI has three basic blocks consisting of the baud rate generator, the transmitter, and the receiver.
14.5.1 Baud Rate Generator
As shown in Figure 14-1, the baud rate generator is driven from the Bus Clock and generates a 1 x baud
clock and a 16 x baud clock. The 16 x baud clock is derived from a 13-bit modulus counter and a 5-bit
fractional fine-adjust counter. The 13-bit counter determines the primary integer clock divisor, and it is
programmed via the SBR[12:0] field of the SCI1BDH and SCI1BDL Registers (see Section 14.6.1, “SCI
Baud Rate Registers (SCI1BDH, SCI1BDL)”). Valid divisor values are from 1 to 8191; a value of zero
disables the counter.
The fractional fine-adjust counter adds fractional delays to the baud rate clock to allow a much higher
accuracy baud rate clock than can be derived from a simple prescaler. The 5-bit fractional counter is driven
from the 16 x baud clock and causes the primary counter to increase the divide divisor by one on a periodic
basis as determined by its programming. The BRFA[4:0] field of the SCI1C4 Register (see Section 14.6.8,
“SCI Control Register 4 (SCI1C4)”) allows selection of 32 different fractional divisors that increase the
integer divisor by the amount shown in Table 14-2.
The 16 x baud rate clock is used by the receiver to sample (at a 16x rate) and synchronize the incoming
RX data. The 1 x baud rate clock is used the the transmitter to send TX data at the selected baud rate.
The equation for determining the baud rate is:
SCI baud rate = Bus Clock / (16 * (SBR[12:0]
+ BRFD ))
Eqn. 14-1
dec
dec
As an example, the typical bus clock for the MC13234/MC13237 is 16 MHz and a standard rate is 115,200
baud. For this case, the integer is first determined assuming no fractional divide:
SBR[12:0]dec = 16 MHz / (115,200 * 16) = 8.68 = 8 (integer)
If no fractional value is added, the actual baud rate is:
Baud rate = 16 MHz / (16 * 8) = 125,000
which gives an error of +8.5% which is undesirable. The closest BRFD value is 0.6875 (BRFA[4:0] =
22 ) and if the fractional option is added:
dec
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Freescale Semiconductor
Serial Communications Interface (SCI)
Baud rate = 16 MHz / (16 * 8.6875) = 115,108
The final error is -0.08% which is very good.
Table 14-1 lists common standard baud rates with a bus clock frequency of 16 MHz using fractional fine
adjustment.
Table 14-1. SCI Baud Rates Using 16 MHz Bus Clock
Standard
Baud
Rate
Actual
Baud
Rate
SBR[12:0]
(dec)
BRFA[4:0]
(dec)
BRFD
(dec)
Error
1200
2400
833
416
208
104
52
34
26
17
8
11
25
11
5
0.34375
0.78125
0.34375
0.15625
0.09375
0.71875
0
1199.98
2399.34
-0.09%
-0.03%
-0.01%
+0.01%
+0.02%
+0.01%
+0.16%
-0.08%
-0.08%
-0.08%
+0.64%
4800
4799.76
9600
9600.96
19200
28800
38400
57600
115200
230400
460800
3
19196.16
28802.88
38461.53
57553.96
115107.91
230215.83
463768.12
23
0
12
22
11
5
0.375
0.6875
0.34375
0.15625
4
2
Table 14-2 lists the available Baud Rate Fine Adjust values (BRFA[4:0]) versus the Baud Rate Fractional
Divisor (BRFD)
.
Table 14-2. SCI Baud Rate Fine Adjust (BRFA)
BRFA[4:0]
Baud Rate Fractional Divisor (BRFD)
(dec)
0
1
0/32 = 0
1/32 = 0.03125
2/32 = 0.0625
3/32 = 0.09375
4/32 = 0.125
2
3
4
5
5/32 = 0.15625
6/32 = 0.1875
7/32 = 0.21875
8/32 = 0.25
6
7
8
9
9/32 = 0.28125
10/32 = 0.3125
11/32 = 0.34375
10
11
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
14-5
Serial Communications Interface (SCI)
Table 14-2. SCI Baud Rate Fine Adjust (BRFA) (continued)
BRFA[4:0]
(dec)
Baud Rate Fractional Divisor (BRFD)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
12/32 = 0.375
13/32 = 0.40625
14/32 = 0.4375
15/32 = 0.46875
16/32 = 0.5
17/32 = 0.53125
18/32 = 0.5625
19/32 = 0.59375
20/32 = 0.625
21/32 = 0.65625
22/32 = 0.6875
23/32 = 0.71875
24/32 = 0.75
25/32 = 0.78125
26/32 = 0.8125
27/32 = 0.84375
28/32 = 0.875
29/32 = 0.90625
30/32 = 0.9375
31/32 = 0.96875
14.5.2 Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in Figure 14-2.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCI1C2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCIxD).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, assume M = 0, selecting
the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop
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Freescale Semiconductor
Serial Communications Interface (SCI)
bit. When the transmit shift register is available for a new SCI character, the value waiting in the transmit
data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data
register empty (TDRE) status flag is set to indicate another character may be written to the transmit data
buffer at SCIxD.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
14.5.2.1 Send Break and Queued Idle
The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wake up is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Table 14-3. Break Character Length
BRK13
M
Break Character Length
0
0
1
1
0
1
0
1
10 bit times
11 bit times
13 bit times
14 bit times
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Freescale Semiconductor
14-7
Serial Communications Interface (SCI)
14.5.3 Receiver Functional Description
In this section, the receiver block diagram (Figure 14-3) is used as a guide for the overall receiver
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wake up function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in
SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop
bit of logic 1. For information about 9-bit data mode, see Section 14.5.5.1, “8- and 9-Bit Data Modes”. For
the remainder of this topic, assume that the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already
full, the data character is transferred to the receive data register and the receive data register full (RDRF)
status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the
overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the
program has one full character time after RDRF is set before the data in the receive data buffer must be
read to avoid a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is
normally satisfied in the course of the user’s program that handles receive data. See Section 14.5.4,
“Interrupts and Status Flags” for more details about flag clearing.
14.5.3.1 Data Sampling Technique
The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples
at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16 baud rate clock is used to
divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more
samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at
least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive
data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample
clock is synchronized to bit times. This improves the reliability of the receiver in the presence of noise or
mismatched baud rates. It does not improve worst case analysis because some characters do not have any
extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
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Serial Communications Interface (SCI)
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
14.5.3.2 Receiver Wake up Operation
Receiver wake up is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set,
the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is
set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
message characters. At the end of a message, or at the beginning of the next message, all receivers
automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next
message.
14.5.3.2.1
Idle-Line Wake up
When WAKE = 0, the receiver is configured for idle-line wake up. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE
flag. The receiver wakes up and waits for the first data character of the next message which will set the
RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE
flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
14.5.3.2.2
Address-Mark Wake up
When WAKE = 1, the receiver is configured for address-mark wake up. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wake up allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is
received and sets the RDRF flag. In this case the character with the MSB set is received even though the
receiver was sleeping during most of this character time.
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Freescale Semiconductor
14-9
Serial Communications Interface (SCI)
14.5.4 Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events,
and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can
be separately masked by local interrupt enable masks. The flags can still be polled by software when the
local masks are cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is
often used in systems with modems to determine when it is safe to turn off the modem. If the transmit
complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1.
Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if
the corresponding TIE or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then
reading SCIxD.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains
idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then reading
SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least
one new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags
— noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF.
These flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF
condition is lost.
At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The
RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled
(RE = 1), and as a result can be used as a wake-up function from low power mode or to enable the UART
if it has been disabled.
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Freescale Semiconductor
Serial Communications Interface (SCI)
14.5.5 Additional SCI Functions
The following sections describe additional SCI functions.
14.5.5.1 8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is
held in R8 in SCIxC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wake up so the ninth data bit can serve as the wake up bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
14.5.5.2 Stop3 Mode Operation
In Stop3 mode, clocks to the SCI module are halted.
No SCI module registers are affected in Stop3 mode.
The receive input active edge detect circuit is still active in Stop3 mode. An active edge on the receive
input brings the CPU out of Stop3 mode if the interrupt is not masked (RXEDGIE = 1).
Note, because the clocks are halted, the SCI module will resume operation upon exit from Stop3 mode.
Software should ensure Stop3 mode is not entered while there is a character being transmitted out of or
received into the SCI module.
14.5.5.3 Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.
14.5.5.4 Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used
and reverts to a general-purpose port I/O pin.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
14-11
Serial Communications Interface (SCI)
In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD pin. When
TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin
is an output driven by the transmitter.
14.5.6 Modes of Operation
The SCI is affected by the device mode of operation and the module clock can be disabled:
•
For lower power, the SPI module clock can be disabled via the SCI control bit of the SCGC1
register
•
LPRun - the reference oscillator is divided by 64 and all clocks are scaled by this factor. It is
recommended to disable the SCI during this mode as all frequencies and timing changes
accordingly. If not disabled, the SCI baud rate changes and normal baud rate and accuracy may not
be possible.
•
Wait modes - there are 2 wait modes
— Wait - when entered, the CPU clock is disabled and the peripheral clock still runs at normal
speed. In addition, the SCISWAI control bit in the SCI control SCIC1 register must be enabled
to allow the SCI clock to run during Wait. If the SCI is a slave, it can still respond to a transfer
and enable an interrupt request. No transmit transfers would occur as the CPU is disabled
– Setting SCISWAI does not affect the state of the receiver enable bit RE, or the transmitter
enable bit TE.
– If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the
CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in
progress and resets the SCI.
— LPWait - when entered the the the CPU clock is disabled and the peripheral clock still runs but
at a reduced speed. This mode should be disabled as the baud rate would be altered.
•
The SPI is disabled in Stop3 mode, regardless of the settings before executing the STOP
instruction.
— During Stop3 mode, clocks to the SCI module are halted. No registers are affected. If Stop3 is
exited with a reset, the SCI will be put into its reset state. If Stop3 is exited with an interrupt,
the SCI continues from the state it was in when Stop3 was entered.
— The RXEDGIF flag and related interrupt request is available for wake-up from low power.
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Freescale Semiconductor
Serial Communications Interface (SCI)
14.6 Register Definition
This section provides a detailed description of all SCI registers.
The memory map for the SCI module is given below in Table 14-4. Only the SCIC3 register is located in
the High-Page Register Map.
Table 14-4. Module Memory Map
Address
Name
Access
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
0x1804
SCI Baud Rate Register High (SCI1BDH)
SCI Baud Rate Register Low (SCI1BDL)
SCI Control Register1 (SCI1C1)
SCI Control Register 2 (SCI1C2)
SCI Status Register 1 (SCI1S1)
SCI Status Register 2(SCI1S2)
SCI Control Register 3 (SCI1C3)
SCI Data Register (SCI1D)
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
SCI Control Register 3 (SCI1C3)
14.6.1 SCI Baud Rate Registers (SCI1BDH, SCI1BDL)
This pair of registers (SCI1BDH, SCI1BDL) controls the pre scale integer divisor SBR[12:0] for SCI baud
rate generation. This divisor works in conjunction of the baud rate Fraction Adjust Counter (see
Section 14.6.8, “SCI Control Register 4 (SCI1C4)”) to establish the SCI baud rate.
To update the 13-bit baud rate setting SBR[12:0], first write to SCI1BDH to buffer the high half of the new
value and then write to SCI1BDL. The working value in SCI1BDH does not change until SCI1BDL is
written. To calculate SBR[12:0] for a given baud rate, see Section 14.5.1, “Baud Rate Generator”.
SCI1BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCI1C2 are written to 1).
SCI1BDH
0x0038
7
6
5
4
3
2
1
0
R
W
0
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-4. SCI Baud Rate Register High (SCI1BDH)
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Freescale Semiconductor
14-13
Serial Communications Interface (SCI)
Table 14-5. SCI1BDH Field Descriptions
Description
Field
7
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
LBKDIE
1 Hardware interrupt requested when LBKDIF flag is 1.
6
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
RXEDGIE 0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
4:0
SBR[12:8]
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] set the integer divisor for the baud rate generator.
• When SBR = 0, the SCI baud rate generator is disabled
• Valid SBR values are 1 to 8191
SCI1BDL
0x0x0039
7
6
5
4
3
2
1
0
R
W
SBR7
SBR6
0
SBR5
SBR4
SBR3
SBR2
1
SBR1
SBR0
Reset
0
0
0
0
0
0
Figure 14-5. SCI Baud Rate Register Low (SCI1BDL)
Table 14-6. SCIxBDL Field Descriptions
Description
Field
7:0
SBR[7:0]
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] set the integer divisor for the baud rate generator.
• When SBR = 0, the SCI baud rate generator is disabled
• Valid SBR values are 1 to 8191
14.6.2 SCI Control Register 1 (SCI1C1)
The SCI1C1 read/write register is used to control various optional features of the SCI system.
SCI1C1
0x003A
7
6
5
4
3
2
1
0
R
W
LOOPS
SCISWAI
0
RSRC
M
WAKE
ILT
PE
PT
Reset
0
0
0
0
0
0
0
Figure 14-6. SCI Control Register 1 (SCI1C1)
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Freescale Semiconductor
Serial Communications Interface (SCI)
Table 14-7. SCI1C1 Field Descriptions
Description
Field
7
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1,
the transmitter output is internally connected to the receiver input.
LOOPS
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
<st-blue>RSRC bit.) RxD pin is not used by SCI.
6
SCI Stops in Wait Mode
SCISWAI 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
5
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
RSRC
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
4
9-Bit or 8-Bit Mode Select
M
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
3
Receiver Wake up Method Select — See Section 14.5.3.2, “Receiver Wake up Operation” for more information.
WAKE
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. See
Section 14.5.3.2.1, “Idle-Line Wake up” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
PT
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
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Freescale Semiconductor
14-15
Serial Communications Interface (SCI)
14.6.3 SCI Control Register 2 (SCI1C2)
The SCI1C2 read/write register is also used to control optional features of the SCI system.
SCI1C2
0x003B
7
6
5
4
3
2
1
0
R
W
TIE
TCIE
0
RIE
ILIE
TE
RE
RWU
SBK
Reset
0
0
0
0
0
0
0
Figure 14-7. SCI Control Register 2 (SCI1C2)
Table 14-8. SCI1C2 Field Descriptions
Description
Field
7
Transmit Interrupt Enable (for TDRE)
TIE
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
6
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
TCIE
5
Receiver Interrupt Enable (for RDRF)
RIE
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
Idle Line Interrupt Enable (for IDLE)
ILIE
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI
system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
See Section 14.5.2.1, “Send Break and Queued Idle” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
RE
LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
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Freescale Semiconductor
Serial Communications Interface (SCI)
Table 14-8. SCI1C2 Field Descriptions (continued)
Field
Description
1
Receiver Wake up Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wake up condition. The wake up condition is either an idle
line between messages (WAKE = 0, idle-line wake up), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wake up). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. See Section 14.5.3.2, “Receiver Wake up Operation” for more details.
0 Normal SCI receiver operation.
RWU
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. See Section 14.5.2.1, “Send Break and
Queued Idle” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
14.6.4 SCI Status Register 1 (SCI1S1)
The read-only SCIS1 register has eight status flags. Writes have no effect. Special software sequences
(which do not involve writing to this register) are used to clear these status flags.
SCI1S1
0x003C
7
6
5
4
3
2
1
0
R
W
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-8. SCI Status Register 1 (SCI1S1)
Table 14-9. SCI1S1 Field Descriptions
Description
Field
7
Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from
the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read
SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD).
0 Transmit data register (buffer) full.
TDRE
1 Transmit data register (buffer) empty.
6
TC
Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break
character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCIxD) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIxC2
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Freescale Semiconductor
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Serial Communications Interface (SCI)
Table 14-9. SCI1S1 Field Descriptions (continued)
Field
Description
5
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
RDRF
the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data
register (SCIxD).
0 Receive data register empty.
1 Receive data register full.
4
IDLE
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear
OR, read SCIxS1 with OR = 1 and then read the SCI data register (SCIxD).
0 No overrun.
1 Receive overrun (new SCI data lost).
2
NF
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the
character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD).
0 No noise detected.
1 Noise detected in the received character in SCIxD.
1
FE
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCIxS1 with FE = 1 and then read the SCI data register (SCIxD).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
PF
the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read
the SCI data register (SCIxD).
0 No parity error.
1 Parity error.
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Freescale Semiconductor
Serial Communications Interface (SCI)
14.6.5 SCI Status Register 2 (SCI1S2)
The SCIS2 register has one read-only status flag and several control bits.
SCI1S2
0x003D
7
6
5
4
3
2
1
0
R
W
0
RAF
LBKDIF
RXEDGIF
RXINV
RWUID
BRK13
LBKDE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-9. SCI Status Register 2 (SCI1S2)
Table 14-10. SCI1S2 Field Descriptions
Description
Field
7
LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
character is detected. LBKDIF is cleared by writing a “1” to it.
0 No LIN break character has been detected.
LBKDIF
1 LIN break character has been detected.
6
RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if
RXEDGIF RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
4
Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
0 Receive data not inverted
RXINV1
1 Receive data inverted
3
Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the
IDLE bit.
RWUID
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2
Break Character Generation Length — BRK13 is used to select a longer transmitted break character length.
Detection of a framing error is not affected by the state of this bit.
BRK13
0 Break character is transmitted with length of 10 bit times (11 if M = 1)
1 Break character is transmitted with length of 13 bit times (14 if M = 1)
1
LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While
LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length of 10 bit times (11 if M = 1).
LBKDE
1 Break character is detected at length of 11 bit times (12 if M = 1).
0
RAF
Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
1
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
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Freescale Semiconductor
14-19
Serial Communications Interface (SCI)
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by
one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data
character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This
would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When
the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits
to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.
14.6.6 SCI Control Register 3 (SCI1C3)
The SCI1C3 read/write register is also used to control optional features of the SCI system as well as
provide the 9th receiver bit when 9-bit operation is enabled.
SCI1C3
0x003E
7
6
5
4
3
2
1
0
R
W
R8
T8
0
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-10. SCI Control Register 3 (SCI1C3)
Table 14-11. SCI1C3 Field Descriptions
Description
Field
7
R8
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth
receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data, read
R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could
allow R8 and SCIxD to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to
change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such
as when it is used to generate mark or space parity), it need not be written each time SCIxD is written.
5
TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
TXDIR
1 TxD pin is an output in single-wire mode.
4
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
TXINV1
1 Transmit data inverted
3
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
ORIE
1 Hardware interrupt requested when OR = 1.
2
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
NEIE
1 Hardware interrupt requested when NF = 1.
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Freescale Semiconductor
Serial Communications Interface (SCI)
Table 14-11. SCI1C3 Field Descriptions (continued)
Field
Description
1
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
FEIE
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
PEIE
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
1
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
14.6.7 SCI Data Register (SCI1D)
This register location actually accesses two separate registers:
•
•
Reads return the contents of the read-only receive data buffer
Writes go to the write-only transmit data buffer.
Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI
status flags.
SCI1D
0x003F
7
6
5
4
3
2
1
0
R
W
R7
R6
R5
R4
R3
R2
R1
R0
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
Reset
Figure 14-11. SCI Data Register (SCI1D)
Table 14-12. SCI1D Field Descriptions
Description
Field
7:0
Read Data - This is the read byte from the receiver buffer. When 9-bit operation is enabled, the 9th MSB bit is
R[7:0]
read from SCIC3, Bit 7.
7:0
Write Data - This is the write byte to the transmit buffer. When 9-bit operation is enabled, the 9th MSB bit is
W[7:0]
written to SCIC3, Bit 6.
14.6.8 SCI Control Register 4 (SCI1C4)
SCIC4 is the only SCI control register located in the High-Page Map and controls the fractional adjust
counter of the SCI baud rate generator. This register works in conjunction of the baud rate integer counter
(see Section 14.6.1, “SCI Baud Rate Registers (SCI1BDH, SCI1BDL)”) to establish the SCI baud rate.
To calculate BRFA[4:0] for a given baud rate, see Section 14.5.1, “Baud Rate Generator”.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
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Serial Communications Interface (SCI)
SCI1C4
0x1804
7
6
5
4
3
2
1
0
R
W
0
0
0
BRFA[4:0]
0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-12. SCI Control Register 4 (SCI1C4)
Table 14-13. SCI1C4 Field Description
Description
Field
4:0
Baud Rate Fraction Adjust — The 5 bits in BRFA[4:0] program the fractional adjust of the SCI baud rate
BRFA[4:0] generator. See Table 14-2 for field value versus fractional divisor
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
Chapter 15
Serial Peripheral Interface (SPI) Module
15.1 Introduction
The SPI module is a synchronous serial data input/output port used for interfacing with serial memories,
peripheral devices, or other processors. The SPI allows an 8-bit serial bit stream to be shifted
simultaneously into and out of the device at a programmed bit-transfer rate (called 4-wire mode). There
are four pins associated with the SPI port; SPCLK (SPSCK), MOSI, MISO, and SS.
The SPI module can be programmed for master or slave operation. It also supports a 3-wire mode where
for master mode the MOSI becomes MOMI, a bidirectional data pin, and for slave mode the MISO
becomes SISO, a bidirectional data pin. In 3-wire mode, data is only transferred in one direction at a time.
The SPI bit clock is derived from the bus clock with a maximum 16 MHz operation. A programmable
prescaler (maximum divide-by-8) drives a second baud rate programmable divider (maximum
divide-by-256) to develop the bit clock. The maximum SPI transfer rate is 8 MHz.
15.2 Features
Features of the SPI module include:
•
•
•
•
•
•
•
•
•
Master or slave mode operation
Full-duplex or single-wire bidirectional option
8-Bit only transfer size
Programmable transmit bit rate (8 MHz max)
Double-buffered transmit and receive
Serial clock phase and polarity options (supports all 4 options)
Optional slave select output
Selectable MSB-first or LSB-first shifting
Selectable MSB-first or LSB-first shifting
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Freescale Semiconductor
15-1
Serial Peripheral Interface (SPI) Module
15.3 Block Diagrams
15.3.1 SPI System Block Diagram
This section shows a typical simple SPI system level 4-wire block diagram.
SPI Master
SPI Slave
MOSI
SPI Shifter
SPI Shifter
3
N-1
3
2
1
0
N-1
2
1
0
*
*
*
*
*
*
*
*
MISO
SPICLK
SS
Clock
Generator
MC1323x
Figure 15-1. SPI System Block Diagram
Figure 15-1 shows the MC13234/MC13237 as the SPI master and an external device as a SPI slave. The
MCU (master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to
the slave while simultaneously shifting data in (on the MISO pin) from the slave. The SPI interface
supports simultaneous data exchange between master and slave, although some devices may be read or
write only. The SPSCK signal is a clock output from the master and an input to the slave. The slave device
must be enabled by a low level on the slave select input.
15.3.2 SPI Module Block Diagram
Figure 15-2 shows the block diagram of SPI module.
MC13234/MC13237 Reference Manual, Rev. 1.8
15-2
Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
PIN CONTROL
M
MOSI
SPE
S
(MOMI)
Tx BUFFER (WRITE SPI1D)
ENABLE
SPI SYSTEM
M
S
MISO
(SISO)
SHIFT
OUT
SHIFT
IN
SPI SHIFT REGISTER
SPC0
Rx BUFFER (READ SPI1D)
BIDIROE
SHIFT
DIRECTION
SHIFT Rx BUFFER
Tx BUFFER
EMPTY
LSBFE
FULL
CLOCK
MASTER CLOCK
SLAVE CLOCK
M
S
SPIBR
BUS RATE
CLOCK
CLOCK
LOGIC
SPICLK
CLOCK GENERATOR
MASTER/SLAVE
MASTER/
SLAVE
MSTR
MODE SELECT
MODFEN
SSOE
MODE FAULT
DETECTION
SS
SPTEF
SPTIE
SPRF
SPI
INTERRUPT
REQUEST
MODF
SPIE
Figure 15-2. SPI Module Block Diagram
15.4 External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
15.4.1 SPICLK — SPI Serial Clock (SPSCK)
When the SPI is enabled as a slave, this pin, also known as SPSCK, is the serial clock input. When the SPI
is enabled as a master, this pin is the serial clock output.
15.4.2 MOSI — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
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Freescale Semiconductor
15-3
Serial Peripheral Interface (SPI) Module
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.4.3 MISO — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.4.4 SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).
15.5 Functional Description
The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter
(write to SPI1D) and gets transferred to the SPI shift register at the start of a data transfer. After shifting
in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from
SPI1D). Pin multiplexing logic controls connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK1 pin, the shifter output is
routed to MOSI1, and the shifter input is routed from the MISO1 pin.
When the SPI is configured as a slave, the SPICLK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI1 pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
15.5.1 Bit Rate Generation
As shown in Figure 15-3, the clock source for the SPI bitrate generator is the bus clock. The three prescale
bits (SPPR[2:0]) select a pre scale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR[2:0])
divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI Master
Mode bitrate clock. With a maximum bus clock rate of 16 MHz and prescaler divisor = 1 and clock rate
divider = 2, the SPI maximum bit rate is 8 MHz.
MC13234/MC13237 Reference Manual, Rev. 1.8
15-4
Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
PRESCALER
CLOCK RATE DIVIDER
DIVIDE BY
MASTER
SPI
BIT RATE
DIVIDE BY
BUS CLOCK
1, 2, 3, 4, 5, 6, 7, or 8
2, 4, 8, 16, 32, 64, 128, or 256
SPPR[2:0]
SPR[2:0]
Figure 15-3. MCU SPI Bit Rate Generation
15.5.2 Basic Transfer
A SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing
a byte of data to the SPI data register (SPI1D) in the master SPI device. When the SPI shift register is
available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate
there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing
the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was
in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data
were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data
byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read
by reading SPI1D. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is
moved into the shifter, SPTEF is set, and a new transfer is started.
Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable
(LSBFE) bit is set, SPI data is shifted LSB first.
When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must
stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a
logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See
Section 15.5.3, “SPI Clock Formats” for more details.
Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently
being shifted out, can be queued into the transmit data buffer, and a previously received character can be
in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the
transmit buffer has room for a new character. The SPRF flag indicates when a received character is
available in the receive data buffer. The received character must be read out of the receive buffer (read
SPI1D) before the next transfer is finished or a receive overrun error results.
In the case of a receive overrun, the new data is lost because the receive buffer still held the previous
character and was not ready to accept the new data. There is no indication for such an overrun condition
so the application system designer must ensure that previous data has been read from the receive buffer
before a new transfer is initiated.
15.5.3 SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
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Freescale Semiconductor
15-5
Serial Peripheral Interface (SPI) Module
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 15-4 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown
for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the
sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on
the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms
applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the
MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output
pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master
SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 15-4. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 15-5 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown
for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK
edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE.
Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific
transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a
slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master
and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the
slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active
low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end
of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 15-5. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
MC13234/MC13237 Reference Manual, Rev. 1.8
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15-7
Serial Peripheral Interface (SPI) Module
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.
15.5.4 SPI Interrupts
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit
is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can
poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should
check the flag bits to determine what event caused the interrupt. The service routine should also clear the
flag bit(s) before returning from the ISR (usually near the beginning of the ISR).
The SPI uses Interrupt Vector No. 17.
15.5.5 Mode Fault Detection
A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an
error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is
configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),
and slave select output enable is clear (SSOE = 0).
The mode fault detection feature can be used in a system where more than one SPI device might become
a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other
SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver
conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back
to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPI1C1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.
15.6 Modes of Operation
The SPI is affected by the device mode of operation and the module clock can be disabled:
•
•
•
For lower power, the SPI module clock can be disabled via the SPI control bit of the SCGC2
Register
LPRun - the reference oscillator is divided by 64 and all clocks are scaled by this factor. The SPI
can run but the SPI clock and timing changes during this mode accordingly.
Wait modes - there are two wait modes
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Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
— Wait - when entered, the CPU clock is disabled and the bus clock still runs at normal speed. In
addition, the SPISWAI control bit in the SCI control SPIC2 register must be enabled to allow
the SCI clock to run during Wait. If the SPI is a slave, it can still respond to a transfer and enable
an interrupt request. No master transfers would occur as the CPU is disabled
— LPWait - when entered, the CPU clock is disabled and the bus clock still runs but at a reduced
speed. In addition, the SPISWAI control bit in the SCI control SPIC2 register must be enabled
to allow the SCI clock to run during Wait. If the SPI is a slave, it can still respond to a transfer
and enable an interrupt request. No master transfers would occur as the CPU is disabled.
•
•
The SPI is disabled in Stop3 mode, regardless of the settings before executing the STOP
instruction.
— During Stop3 mode, clocks to the SPI module are halted. No registers are affected. If Stop3 is
exited with a reset, the SPI will be put into its reset state. If Stop3 is exited with an interrupt,
the SPI continues from the state it was in when Stop3 was entered.
Background Mode Operation -When the microcontroller is in active background mode, the SPI
temporarily suspends all counting until the microcontroller returns to normal user mode.
15.7 Register Definition
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data. The SPI registers are all located in the Direct-Page Register Map.
15.7.1 SPI Control Register 1 (SPI1C1)
This read/write control register includes the SPI enable control, interrupt enables, and configuration
options.
SPI1C1
0x0070
7
6
5
4
3
2
1
0
R
W
SPIE
SPE
0
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
Reset
0
0
0
0
1
0
0
Figure 15-6. SPI Control Register 1 (SPI1C1)
Table 15-1. SPI1C1 Field Descriptions
Description
Field
7
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
SPIE
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable — Disabling the SPI halts any transfer that is in progress and initializes internal state
machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
15-9
Serial Peripheral Interface (SPI) Module
Table 15-1. SPI1C1 Field Descriptions (continued)
Field
Description
5
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
SPTIE
1 When SPTEF is 1, hardware interrupt requested
4
Master/Slave Mode Select
MSTR
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. See Section 15.5.3, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
CPOL
1 Active-low SPI clock (idles high)
2
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. See Section 15.5.3, “SPI Clock Formats” for more details.
CPHA
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
1
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SSOE
SPI1C2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 15-2.
0
LSB First (Shifter Direction)
LSBFE
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 15-2. SS Pin Function
MODFEN
SSOE
Master Mode
Slave Mode
0
0
1
1
0
1
0
1
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Slave select input
Slave select input
Slave select input
Slave select input
Automatic SS output
15.7.2 SPI Control Register 2 (SPI1C2)
This read/write control register is used to control optional features of the SPI system.
SPI1C2
0x0071
7
6
5
4
3
2
1
0
R
W
0
0
0
0
MODFEN
BIDIROE
SPISWAI
0
SPC0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-7. SPI Control Register 2 (SPI1C2)
MC13234/MC13237 Reference Manual, Rev. 1.8
15-10
Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
Table 15-3. SPI1C2 Register Field Descriptions
Description
Field
4
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
MODFEN effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (see
Table 15-2 for more details).
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
1
SPI Stop in Wait Mode
SPISWAI 0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
SPC0
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
15.7.3 SPI Baud Rate Register (SPI1BR)
This register is used to set the prescaler and bit rate divisor for an SPI master. See Section 15.5.1, “Bit Rate
Generation”.
SPI1BR
0x0072
7
6
5
4
3
2
1
0
R
W
0
0
SPPR2
0
SPPR1
SPPR0
SPR2
SPR1
SPR0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 15-4. SPI1BR Register Field Descriptions
Description
Field
6:4
SPI Baud Rate Pre scale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
SPPR[2:0] as shown in Table 15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 15-3).
2:0
SPR[2:0]
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table 15-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 15-3). The output of this
divider is the SPI bit rate clock for master mode.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
15-11
Serial Peripheral Interface (SPI) Module
Table 15-5. SPI Baud Rate Prescaler Divisor
SPPR[2:0]
Prescaler Divisor
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
8
Table 15-6. SPI Baud Rate Divisor
SPR[2:0]
Rate Divisor
000
001
010
011
100
101
110
111
2
4
8
16
32
64
128
256
15.7.4 SPI Status Register (SPI1S)
This read-only register has provides the SPI status bits.
SPI1S
0x0073
7
6
5
4
3
2
1
0
R
W
SPRF
0
SPTEF
MODF
0
0
0
0
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-8. SPI Status Register (SPI1S)
MC13234/MC13237 Reference Manual, Rev. 1.8
15-12
Freescale Semiconductor
Serial Peripheral Interface (SPI) Module
Table 15-7. SPI1S Register Field Descriptions
Description
Field
7
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the
SPI data register.
SPRF
0 No data available in the receive data buffer
1 Data available in the receive data buffer
5
SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by
reading SPI1S with SPTEF set, followed by writing a data value to the transmit buffer at SPI1D. SPI1S must be
read with SPTEF = 1 before writing data to SPI1D or the SPI1D write will be ignored. SPTEF generates an
SPTEF CPU interrupt request if the SPTIE bit in the SPI1C1 is also set. SPTEF is automatically set when a data
byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer
or the shift register and no transfer in progress), data written to SPI1D is transferred to the shifter almost
immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the
transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the
transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data
in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data
moves from the buffer to the shifter.
SPTEF
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
4
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes
low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input
only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1, then writing to SPI control register 1 (SPI1C1).
0 No mode fault error
MODF
1 Mode fault error detected
15.7.5 SPI Data Register (SPI1D)
The read/write SPI1D register is used to write data to the transmitter and read data from the receiver.
•
•
Reads of this register return the data read from the receive data buffer.
Writes to this register write data to the transmit data buffer.
When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer.
Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF)
is set, indicating there is room in the transmit buffer to queue a new transmit byte.
Data may be read from SPI1D any time after SPRF is set and before another transfer is finished. Failure
to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
15-13
Serial Peripheral Interface (SPI) Module
SPI1D
0x0075
7
6
5
4
3
2
1
0
R
W
R7
R6
R5
R4
R3
R2
R1
R0
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
Reset
Figure 15-9. SPI Data Register (SPI1D)
Table 15-8. SPI1D Register Field Descriptions
Description
Field
7:0
R[7:0]
Read Data - This is the read byte from the SPI receiver buffer.
Write Data - This is the write byte to the SPI transmit buffer.
7:0
W[7:0]
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Freescale Semiconductor
Chapter 16
Timer/PWM (TPM Module)
16.1 Introduction
The MC13234/MC13237 has four independent timer/PWM modules, each with one channel. Each TPM
module is based on a 16-bit counter and provides input capture, output compare, and pulse width
modulation. Each TPM module has one associated I/O pin for input capture or counter/PWM output. Each
TPM has an independent set of control/status registers.
16.2 Features
Each TPM has the following features:
•
•
•
Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM)
Clock sources independently selectable per TPM
Selectable clock sources
— Bus clock
— Optional 32.768 kHz oscillator
— 32 MHz reference oscillator divided-by 1024 (31,250 Hz)
Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
16-bit free-running or up/down (CPWM) count operation
16-bit modulus register to control counter range
Module enable
•
•
•
•
•
•
One interrupt request per channel and a terminal count interrupt request for each TPM module
Channel features:
— The channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-1
Timer/PWM (TPM Module)
16.2.1 Block Diagram
Figure 16-1 is a block diagram of a single channel TPM module.
BUSCLK
PRESCALE AND SELECT
DIVIDE BY
SYNC
32Hz_OSC
CLOCK SOURCE
SELECT
1, 2, 4, 8, 16, 32, 64, or 128
DIVIDE
BY
32MHz_OSC
1024
PS2
PS1
PS0
CLKSB
CLKSA
CPWMS
MAIN 16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
COUNTER RESET
16-BIT COMPARATOR
TPM1MODH:TPM1MDL
ELS0B ELS0A
CHANNEL 0
PORT
LOGIC
16-BIT COMPARATOR
TPMxCH0
TPM1C0VH:TPM1C0VL
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
CH0IE
MS0B
MS0A
Figure 16-1. TPM Module Block Diagram
16.2.2 External Signals (TPM3:TPM0)
The are 4 timer I/O signals:
•
•
•
•
TPM0 - associated with Channel 0, TPM1
TPM1 - associated with Channel 0, TPM2
TPM2 - associated with Channel 0, TPM3
TPM3 - associated with Channel 0, TPM4
The function of any pin depends on the configuration of its channel:
•
•
•
If no pin function is needed, the pin reverts to being controlled by the general-purpose port I/O
controls
When used as an input, the TPMx I/O can be used for input capture or timer gating. It cannot be
used as a clock source to the TPM counter.
The TPMx I/O may also be used as an output for various PWM and counter modes.
16.3 Functional Description
As shown in Figure 16-1, all TPM functions are associated with a main 16-bit counter that allows flexible
selection of its clock source and pre scale divisor. A 16-bit modulo register also is associated with the main
16-bit counter in the TPM for comparator functions.
MC13234/MC13237 Reference Manual, Rev. 1.8
16-2
Freescale Semiconductor
Timer/PWM (TPM Module)
Each TPM has a single timing channel, with an associated external I/O pin, that supports center-aligned
pulse-width-modulation (PWM), input event capture, output compare, and edge-aligned PWM mode.
Each TPM is completely independent and has its own external I/O pin and control registers
16.3.1 TPM Counter Clock Source
As seen in Figure 16-1, the main 16-bit counter has a programmable clock source. The primary source is
selected by a multiplexer:
•
•
•
The MC13234/MC13237 bus clock (peripheral clock) - the CPU and bus clock (equal to 1/2 CPU
clock) are programmable
An optional onboard 32.768 kHz oscillator - an external 32.768 kHz crystal must be used and the
oscillator enabled
The 32 MHz reference oscillator divided-by-1024 (31,250 Hz)
The multiplexer is controlled by the CLKSB:CLKSA Bits of Register TPMxSC, and this field can also be
used to disable the TPMx module by selecting no clock. Table 16-1 shows the coding for the TPM clock
source selection.
Table 16-1. TPM Clock Source Selection (CLKSB:CLKSA)
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
0:1
1:0
1:1
No clock selected (TPM disabled)
Bus rate clock (BUSCLK)
Optional 32.768 kHz oscillator
Reference oscillator divided-by-1024 (31,250 Hz)
The selected clock source, in turn, drives a prescaler that feeds the counter directly. The prescaler is
programmable for divide ratios from 1 to 128 and is controlled by the PS[2:0] field of Register TPMxSC.
Table 16-2 shows the coding for the prescaler divide ratio selection.
Table 16-2. TPM Clock Prescale Divisor Selection (PS[2:0])
PS[2:0]
TPM Clock Prescaler Divide Ratio
000
001
010
011
100
101
110
111
1
2
4
8
16
32
64
128
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-3
Timer/PWM (TPM Module)
16.3.2 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section
discusses up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset.
After any device reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Typically, CLKSB:CLKSA are set to 0:1 so the bus clock drives the timer counter.
The main 16-bit counter has two counting modes:
•
When center-aligned PWM is selected (CPWMS = 1), the counter operates in up-/down-counting
mode. The counter counts upward from 0x0000 through its terminal count and then counts
downward to 0x0000 where it returns to up-counting. The terminal count is 0xFFFF or a modulus
value in TPM1MODH:TPM1MODL registers, depending on programming.
•
Otherwise (CPWMS = 0), the counter operates as a simple up-counter. As an up-counter, the main
16-bit counter counts from 0x0000 through its terminal count and then rolls over to 0x0000. The
terminal count is 0xFFFF or a modulus value in TPM1MODH:TPM1MODL registers, depending
on programming.
The timer overflow status flag (TOF) is associated with the main 16-bit counter and is an indication that
the timer counter has overflowed. An interrupt request enable bit (TOIE) allows an IRQ to automatically
be generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the
counting mode (up or up/down):
•
Up-counting mode -
— If a modulus limit is not set - the 16-bit counter counts from 0x0000 through 0xFFFF and
overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from
0xFFFF to 0x0000.
— If a modulus limit is set - the 16-bit counter counts from 0x0000 through to the value set in the
modulus register and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from the value set in the modulus register to 0x0000.
•
Up-/down-counting mode - the TOF flag gets set as the counter changes direction at the transition
from the value set in the modulus register and the next lower count value. This corresponds to the
end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
Because the CPU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read
operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are
captured into a buffer so when the other byte is read, the value will represent the other byte of the count at
the time the first byte was read. The counter continues to count normally, but no new value can be read
from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer
count TPM1CNTH or TPM1CNTL. Resetting the counter in this manner also resets the coherency
mechanism in case only one byte of the counter was read before resetting the count.
MC13234/MC13237 Reference Manual, Rev. 1.8
16-4
Freescale Semiconductor
Timer/PWM (TPM Module)
16.3.3 Channel Mode Selection
The MC13234/MC13237 has only one channel per TPM module, i.e., Channel 1. Provided CPWMS = 0
(center-aligned PWM operation is not specified), the MS0B and MS0AMS0A control bits in the channel
status and control registers determine the basic mode of operation for Channel 0. Mode choices include
input capture, output compare, and buffered edge-aligned PWM.
A single channel status flag is used for any of the channel modes.
16.3.3.1 Input Capture Mode
With the input capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter
into the channel value registers (TPMxC0VH:TPMxC0VL). Rising edges, falling edges, or any edge may
be chosen as the active edge that triggers an input capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support
coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to
the channel status/control register (TPMxC0SC).
An input capture event sets a flag bit (CH0F) that can optionally generate an interrupt request.
16.3.3.2 Output Compare Mode
With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an
output compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only
after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset
by writing to the channel status/control register (TPMxC0SC).
An output compare event sets a flag bit (CH0F) that can optionally generate a CPU interrupt request.
16.3.3.3 Edge-Aligned PWM Mode
Edge-aligned PWM output mode uses the normal up-counting mode of the timer counter (CPWMS = 0).
The period of this PWM signal is determined by the setting in the modulus register
(TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the timer channel value
register (TPMxC0VH:TPMxC0VL). The polarity of this PWM signal is determined by the setting in the
ELS0A control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure 16-2 shows, the output compare value in the TPM channel registers determines the pulse width
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELS0A = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELS0A = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-5
Timer/PWM (TPM Module)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TPM1C
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-2. PWM Period and Pulse Width (ELS0A = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPMxC0VH:TPMxC0VL) to a value greater than the modulus setting, a 100% duty cycle
can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the CPU is an 8-bit architecture, the settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxC0VH
or TPMxC0VL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding
timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in
the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next
full period.)
16.3.4 Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The
output compare value in TPMxC0VH:TPMxC0VL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPMxMODH:TPMxMODL.
TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results. ELS0A will determine the polarity of the CPWM output.
pulse width = 2 x (TPMxC0VH:TPMxC0VL)
Eqn. 16-1
period = 2 x (TPMxMODH:TPMxMODL);
for TPMxMODH:TPMxMODL = 0x0001–0x7FFF
Eqn. 16-2
If the channel value register TPMxC0VH:TPMxC0VL is zero or negative (Bit 15 set), the duty cycle will
be 0%. If TPMxC0VH:TPMxC0VL is a positive value (Bit 15 clear) and is greater than the (nonzero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if
generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting
period is much longer than required for normal applications.
TPMxC0VH:TPMxC0VL = 0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,
but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at
0x0000 to change directions from up-counting to down-counting.
MC13234/MC13237 Reference Manual, Rev. 1.8
16-6
Freescale Semiconductor
Timer/PWM (TPM Module)
Figure 16-3 shows the output compare value in the TPM channel registers (multiplied by 2), which
determines the pulse width (duty cycle) of the CPWM signal. If ELS0A = 0, the compare match while
counting up forces the CPWM output signal low and a compare match while counting down forces the
output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then
counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
COUNT = 0
OUTPUT
COMPARE
(COUNT UP)
OUTPUT
COMPARE
(COUNT DOWN)
COUNT =
TPM1MODH:TPM
COUNT =
TPM1MODH:TPM
TPM1C
PULSE WIDTH
2 x
PERIOD
2 x
Figure 16-3. CPWM Period and Pulse Width (ELS0A = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
Because the CPU is an 8-bit architecture, the settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,
TPMxMODH, TPMxMODL, TPMxC0VH, and TPMxC0VL, actually write to buffer registers. Values are
transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have
been written and the timer counter overflows (reverses direction from up-counting to down-counting at the
end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to
PWM channels, not output compares.
Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF
interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they
will all update simultaneously at the start of a new period.
Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the
coherency mechanism for the modulo registers. Writing to TPM1CnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMxC0VH:TPMxC0VL.
16.4 TPM Interrupts
Each TPM has two interrupt request sources:
•
•
The main counter overflow status (TOF)
The Channel 0 status flag (CH0F) - the meaning of channel status depends on the mode of
operation for the channel.
— If the channel is configured for input capture, the interrupt flag is set each time the selected
input capture edge is recognized.
— If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-7
Timer/PWM (TPM Module)
For each interrupt request source in the TPM, a flag bit is set on recognition of the interrupt condition such
as timer overflow, channel input capture, or output compare events. This flag may be read (polled) by
software to verify that the action has occurred, or an associated enable bit (TOIE or CH0IE) can be set to
enable hardware interrupt request generation. While the interrupt enable bit is set, a static interrupt request
will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software
to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine.
16.4.1 Clearing Timer Interrupt Flags
TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)
followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset
and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.
16.4.2 Timer Overflow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction
at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
16.4.3 Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELS0B:ELS0A control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section 16.4.1, “Clearing Timer Interrupt Flags”.
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in Section 16.4.1, “Clearing Timer Interrupt Flags”.
16.4.4 PWM End-of-Duty-Cycle Events
For the channel that is configured for PWM operation, there are two possibilities:
•
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
•
When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
MC13234/MC13237 Reference Manual, Rev. 1.8
16-8
Freescale Semiconductor
Timer/PWM (TPM Module)
The flag is cleared by the 2-step sequence described in Section 16.4.1, “Clearing Timer Interrupt Flags”.
16.5 Modes of operation
The TPM is affected by the device mode of operation and the module clock can be disabled:
•
For lower power, the TPM module clock can be disabled via the KBIx control bit of the SCGC1
Register
•
LPRun - the reference oscillator is divided by 64 and all clocks are scaled by this factor. It is
recommended to disable the TPM during this mode as all frequencies and timing changes
accordingly.
•
Wait modes - there are two wait modes
— Wait - when entered, the CPU clock is disabled and the bus clock still runs at normal speed .
The TPM, if enabled, will continue to operate normally. However, there will be no new codes
or changes of operation while in wait mode, because the CPU is not operating.
— LP Wait - when entered, the CPU clock is disabled and the bus clock still runs but at a reduced
speed. The TPM, if enabled, will continue to operate, however, all timing would be incorrect.
Operation is not recommended.
•
•
The TPM is disabled in Stop3 mode, regardless of the settings before executing the STOP
instruction.
— During Stop3 mode, clocks to the TPM module are halted. No registers are affected. If Stop3
is exited with a reset, the TPM will be put into its reset state. If Stop3 is exited with an interrupt,
the TPM will resume operation. It is recommended that the TPM be halted before entering
Stop3.
Background Mode Operation -When the microcontroller is in active background mode, the TPM
temporarily suspends all counting until the microcontroller returns to normal user mode. When
background mode is active, the timer counter and the coherency mechanism are frozen such that
the buffer latches remain in the state they were in when the background mode became active even
if one or both bytes of the counter are read while background mode is active..
16.6 Register Definition
The TPM includes:
•
•
•
An 8-bit status and control register (TPMxSC)
A 16-bit counter (TPMxCNTH:TPMxCNTL)
A 16-bit modulo register (TPMxMODH:TPMxMODL)
Timer Channel 0 has:
•
•
An 8-bit status and control register (TPMxC0SC)
A 16-bit channel value register (TPMxC0VH:TPMxC0VL)
The MC13234/MC13237 has four TPM modules designated as TPM1, TPM2, TPM3, and TPM4.
Table 16-3 lists the TPM module base addresses; only TPM4 is in the High-Page Register Map.The
following register descriptions are for a single TPM module.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-9
Timer/PWM (TPM Module)
Table 16-3. TPM Register Base Addresses
TPM
Base Address
Module
TPM1
TPM2
TPM3
TPM4
0x0008
0x0010
0x0018
0x1860
The following register descriptions are for a single TPM module.
16.6.1 Timer x Status and Control Register (TPMxSC)
TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
TPMxSC
Base + 0x00
7
6
5
4
3
2
1
0
R
W
TOF
TOIE
0
CPWMS
CLKSB
CLKSA
PS2
0
PS1
PS0
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-4. Timer x Status and Control Register (TPMxSC)
Table 16-4. TPMxSC Register Field Descriptions
Description
Field
7
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another
TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set
after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
TOIE
1 TOF interrupts enabled
MC13234/MC13237 Reference Manual, Rev. 1.8
16-10
Freescale Semiconductor
Timer/PWM (TPM Module)
Table 16-4. TPMxSC Register Field Descriptions (continued)
Description
Field
5
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
CPWMS
0 All TPM1 channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MS0B:MS0A control bits in each channel’s status and control register
1 All TPM1 channels operate in center-aligned PWM mode
4:3
Clock Source Select — This 2-bit field is used to disable the TPM system or select one of three clock sources
CLKS[B:A] to drive the counter prescaler. See Section 16.3.1, “TPM Counter Clock Source” and Table 16-1
2:0
PS[2:0]
Pre scale Divisor Select — This 3-bit field selects one of eight divisors for the TPM counter prescaler. This
prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock
source is selected to drive the TPM system. See Section 16.3.1, “TPM Counter Clock Source” and Table 16-2
16.6.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPM1SC).
Reset clears the TPM counter registers.
TPMxCNTH
Base + 0x01
7
6
5
4
3
2
1
0
R
W
Bit 15
14
13
12
11
10
9
Bit 8
Any write to TPMxCNTH clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure 16-5. Timer x Counter Register TPMxCNTH
TPMxCNTL
Base + 0x02
7
6
5
4
3
2
1
0
R
W
Bit 7
6
5
4
3
2
1
Bit 0
Any write to TPMxCNTL clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure 16-6. Timer x Counter Register TPMxCNTL
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-11
Timer/PWM (TPM Module)
Table 16-5. TPMxCNTH and TPMxCNTL Register Field Descriptions
Description
Field
CNTH[7:0] Timer Count Value [15:8] - Contains high byte of 16-bit counter value
CNT[15:8]
CNTL[7:0] Timer Count Value [7:0] - Contains low byte of 16-bit counter value
CNT[7:0]
16.6.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written.
Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter
(modulo disabled).
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
TPMxMODH
Base + 0x03
7
6
5
4
3
2
1
0
R
W
Bit 15
14
0
13
12
11
10
0
9
Bit 8
Reset
0
0
0
0
0
0
Figure 16-7. Timer x Counter Modulo Register TPMxMODH
TPMxMODL
Base + 0x04
7
6
5
4
3
2
1
0
R
W
Bit 7
6
0
5
4
3
2
1
Bit 0
Reset
0
0
0
0
0
0
0
Figure 16-8. Timer x Counter Modulo Register TPMxMODL
MC13234/MC13237 Reference Manual, Rev. 1.8
16-12
Freescale Semiconductor
Timer/PWM (TPM Module)
Table 16-6. TPMxMODH and TPMxMODL Register Field Descriptions
Description
Field
MODH[7:0] Timer Modulo Value [15:8] - Contains high byte of 16-bit timer modulo value
MOD[15:8]
MODL[7:0] Timer Modulo Value [7:0] - Contains low byte of 16-bit timer modulo value
MOD[7:0]
16.6.4 Timer x Channel 0 Status and Control Register (TPM1C0SC)
TPMxC0SC contains the Channel 0 interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
TPMxC0SC
Base + 0x05
7
6
5
4
3
2
1
0
R
W
0
0
CH0F
CH0IE
0
MS0B
MS0A
ELS0B
ELS0A
0
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Table 16-7. TPMxC0SC Register Field Descriptions
Description
Field
7
Channel 0 Flag — When Channel 0 is configured for input capture, this flag bit is set when an active edge occurs
on the TPMx pin. When Channel 0 is an output compare or edge-aligned PWM channel, CH0F is set when the
value in the TPM counter registers matches the value in the TPM Channel 0 value registers. This flag is seldom
used with center-aligned PWMs because it is set every time the counter matches the channel value register,
which correspond to both edges of the active duty cycle period.
CH0F
A corresponding interrupt is requested when CH0F is set and interrupts are enabled (CH0IE = 1). Clear CH0F
by reading TPM1CnSC while CH0F is set and then writing a 0 to CH0F. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CH0F would remain set after the clear sequence
was completed for the earlier CH0F. This is done so a CH0F interrupt request cannot be lost by clearing a
previous CH0F. Reset clears CH0F. Writing a 1 to CH0F has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
6
Channel 0 Interrupt Enable — This read/write bit enables interrupts from Channel 0. Reset clears CH0IE.
0 Channel 0 interrupt requests disabled (use software polling)
CH0IE
1 Channel 0 interrupt requests enabled
5
Mode Select B for TPM Channel 0 — When CPWMS = 0, MS0B = 1 configures TPM Channel 0 for
MS0B
edge-aligned PWM mode. For a summary of channel mode and setup controls, see Table 16-8.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-13
Timer/PWM (TPM Module)
Table 16-7. TPMxC0SC Register Field Descriptions
Description
Field
4
Mode Select A for TPM Channel 0 — When CPWMS = 0 and MS0B = 0, MS0A configures TPM Channel 0 for
MS0A
input capture mode or output compare mode. See Table 16-8 for a summary of channel mode and setup controls.
3:2
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
ELS0[B:A] CPWMS:MS0B:MS0A and shown in Table 16-8, these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELS0B:ELS0A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin.
Table 16-8. Mode, Edge, and Level Selection
CPWMS
MS0B:MS0A
ELS0B:ELS0A
Mode
Configuration
X
XX
00
Pin not used for TPM channel; use as an external gate for the TPM or
revert to general-purpose I/O
0
00
01
01
10
11
00
01
10
11
10
X1
10
X1
Input capture
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Output
compare
Toggle output on compare
Clear output on compare
Set output on compare
1X
XX
Edge-aligned
PWM
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
1
Center-aligned High-true pulses (clear output on compare-up)
PWM
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
16.6.5 Timer x Channel Value Registers (TPMxC0VH:TPMxC0VL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
In input capture mode, reading either byte (TPMxC0VH or TPMxC0VL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPM1CnSC register is written.
In output compare or PWM modes, writing to either byte (TPMxC0VH or TPMxC0VL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
MC13234/MC13237 Reference Manual, Rev. 1.8
16-14
Freescale Semiconductor
Timer/PWM (TPM Module)
timer channel value registers. The high byte should be written first, followed by the low byte. This latching
mechanism may be manually reset by writing to the TPM1CnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various
compiler implementations.
TPMxC0VH
Base + 0x06
7
6
5
4
3
2
1
0
R
W
Bit 15
14
0
13
12
11
10
0
9
Bit 8
Reset
0
0
0
0
0
0
Figure 16-9. Timer x Channel Value Register TPMxC0VH
TPMxC0VL
Base + 0x07
7
6
5
4
3
2
1
0
R
W
Bit 7
6
0
5
4
3
2
1
Bit 0
Reset
0
0
0
0
0
0
0
Timer x Channel Value Register TPMxC0VL
Table 16-9. TPMxC0VH and TPMxC0VL Register Field Descriptions
Description
Field
CoVH[7:0] Channel 0 Value [15:8] - Contains high byte of 16-bit Channel 0 capture value
C0V[15:8]
C0VL[7:0] Channel 0 Value [7:0] - Contains low byte of 16-bit Channel 0 capture value
C0V[7:0]
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
16-15
Timer/PWM (TPM Module)
MC13234/MC13237 Reference Manual, Rev. 1.8
16-16
Freescale Semiconductor
Chapter 17
Carrier Modulator Timer (CMT) Module
17.1 Introduction
Carrier Modulator Timer (CMT) module is a IR LED driver. The CMT consists of a carrier generator,
modulator, and transmitter that drives the infrared out (IRO) pin. The module can transmit data to IRO
output pin either in baseband or in FSK mode. The IRO pin has 20mA current drive capability.
17.2 Features
The features of the CMT module include:
•
Four modes of operation
— Time with independent control of high and low times
— Baseband
— Frequency shift key (FSK)
— Direct software control of IRO pin
Extended space operation in time, baseband, and FSK modes
Selectable input clock divide: 1, 2, 4, or 8
Interrupt on end of cycle
•
•
•
•
•
Ability to disable IRO pin and use as timer interrupt
CMT use as a timer resource.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-1
Carrier Modulator Timer (CMT) Module
17.3 Block Diagram
PRIMARY/SECONDARY SELECT
CARRIER
MODULATOR
OUT
IRO
PIN
TRANSMITTER
OUTPUT
CARRIER
OUT (fCG
)
CLOCK
MODULATOR
CMTCLK
GENERATOR
CONTROL
CMTDIV
CMT REGISTERS
AND BUS INTERFACE
BUS CLOCK
INTERNAL BUS
IIREQ
Figure 17-1. Carrier Modulator Timer Module Block Diagram
17.4 External Signal (IRO)
The CMT has only one external pin called IRO. The pin is driven by the transmitter output when the
MCGEN bit in the CMTMSC register and the IROPEN bit in the CMTOC register are set. If the MCGEN
bit is clear and the IROPEN bit is set, the pin is driven by the IROL bit in the CMTOC register. This enables
user software to directly control the state of the IRO pin by writing to the IROL bit. If the IROPEN bit is
clear, the pin is disabled and is not driven by the CMT module. This is so the CMT can be configured as
a modulo timer for generating periodic interrupts without causing pin activity.
17.5 Functional Description
The CMT module consists of a carrier generator, a modulator, a transmitter output, and control registers.
The block diagram is shown in Figure 17-1. The module CMTCLK is derived from the bus clock.
17.5.1 Clock Control
The CMT clock (CMTCLK) is generated from a prescaler that is controlled by the CMTDIV[2:0] field
which is located across two registers, i.e., CMTOC register (see Section 17.7.2, “CMT Output Control
Register (CMTOC)”) and CMTMSC register (see Section 17.7.3, “CMT Modulator Status and Control
Register (CMTMSC)”). The prescaler is clocked by the bus clock which is typically 16MHz. Table 17-1
lists the divide ratio vs. the CMTDIV[2:0] field setting.
The CMT clock can also be disabled by the CMT bit of control register SCGC1, see Section 5.8.12,
“System Clock Gating Control 1 Register (SCGC1)”.
MC13234/MC13237 Reference Manual, Rev. 1.8
17-2
Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
Table 17-1. CMT Timing Parameters vs. CMTDIV[2:0] @ 16 MHz Bus Clock
Carrier
Generator
Resolution
(s)
Min. Carrier
Generator
Period
Min.
Modulator
Period
(s)
Clock Resolution
w/16 MHz Bus Clock
(s)
CMTDIV[2:0]
Divide Ratio
(s)
000
001
010
011
100
101
110
111
1
2
4
8
16
1
1
1
0.0625
0.125
0.0625
0.125
0.125
0.250
0.500
1.000
2.000
0.125
0.125
0.125
0.5
1.0
2.0
4.0
8.0
0.5
0.5
0.5
0.250
0.250
0.500
0.500
1.000
1.000
0.0625
0.0625
0.0625
0.0625
0.0625
0.0625
17.5.2 Operating Modes Overview
The module has three main modes of operation: time, baseband, and frequency shift keying (FSK). These
are shown in Figure 17-2.
Time
Baseband
Mark 1
Mark 2
Mark 1
Mark 2
FSK
Frequency 2
Frequency 1
Space 1
Frequency 2
Frequency 1
Space 2
Figure 17-2. CMT Operating Modes
17.5.2.1 Time Mode
When operating in time mode, the output pulse stream is a carrier signal where the carrier high and low
times are independently defined to determine both period and duty cycle. This frequency is developed in
the carrier generator and it is gated on and off by the modulator.
The best carrier generator resolution is 62.5 ns when operating with an 16 MHz bus frequency
(CMTDIV[2:0] =0; divide-by-1). The carrier generator can generate signals with periods between 125 ns
(8 MHz) and 31.875 s (31.37 kHz) in steps of 62.5 ns. See Table 17-1 for the minimum carrier generator
resolution and period. If a lower frequency is desired, the pre scale divide ratio may be increased with the
cost low a longer resolution time.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-3
Carrier Modulator Timer (CMT) Module
The possible duty cycle options will depend upon the number of counts required to complete the carrier
period. For example, a 1.6 MHz signal has a period of 625 ns and will therefore require 10 of the 62.5 nS
counts to generate. These counts may be split between high and low times, so various duty cycles are
available.
For lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty
cycles are possible.
The on/off times are also programmable in the modulator.
17.5.2.2 Baseband Mode
Baseband mode is a special version of time mode. The generator output is held continuously high and
allows the modulator output to directly drive the CMT output signal. The output signal is then determined
by the desired up time (mark) and down time (space) of the modulator.
17.5.2.3 FSK Mode
A third mode allows the carrier generator to alternate between two sets of high and low times (two different
frequencies). When operating in FSK mode, the generator toggles between the two frequency sets when
instructed by the modulator and requires no programming intervention.
The modulator can set different mark and space timing for the two FSK frequencies. The modulator
provides a simple method to control protocol timing. It can count bus clocks (to provide real-time control)
or it can count carrier clocks (for self-clocked protocols). See Section 17.5.4, “Modulator”, for more
details.
17.5.2.4 Mode Control and Options
In addition to the three common modes described above:
•
These modes can be disabled, and the CMT output state can be controlled by a control register bit.
This allows a software managed output state.
•
•
There is an option for extended “space” time between FSK pulses.
The IRO output can be disabled and the timers used as a simple timing resource.
The modes are controlled primarily by the following control bits:
1. Modulator and Carrier Generator Enable (MCGEN) - this bit enables the carrier generator,
modulator, and clocks for normal operation. When disabled, the IRO output state can be set by
writing to the IROL control bit.
2. Baseband Enable (BASE) - when enabled the generator output is forced high and the output timing
is determined by the modulator
3. FSK Mode Select (FSK) - when set selects FSK mode. When clear, time/baseband mode is enabled
and modified by the BASE enable bit.
4. Extended Space Enable (EXSPC) - this is an optional feature that allows for extended time
(“space” time) between FSK pulses (“mark” time).
A summary of the possible modes is shown in Table 17-2.
MC13234/MC13237 Reference Manual, Rev. 1.8
17-4
Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
Table 17-2. CMT Modes of Operation
MCGEN
Bit1
BASE
Bit2
FSK
EXSPC
Bit
Mode
Comment
CG controlled by primary high and low registers.
Bit(2)
f
Time
1
1
0
1
0
x
0
0
fCG transmitted to IRO pin when modulator gate is open.
fCG is always high. IRO pin high when modulator gate is open.
Baseband
f
CG control alternates between primary high/low registers and
FSK
1
0
1
0
secondary high/low registers.
fCG transmitted to IRO pin when modulator gate is open.
Setting the EXSPC bit causes subsequent modulator cycles
to be spaces (modulator out not asserted) for the duration of
the modulator period (mark and space times).
Extended
Space
1
0
x
x
x
x
1
x
IRO Latch
IROL bit controls state of IRO pin.
1
2
To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1).
These bits are not double buffered and should not be changed during a transmission (while MCGEN=1).
17.5.3 Carrier Generator
The carrier generator block diagram is shown in Figure 17-3. The carrier signal is generated by counting
a register-selected number of CMTCLK input clocks (62.5 ns minimum period for an 16 MHz bus clock)
for both the carrier high time and the carrier low time. The period is determined by the total number of
clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The
high and low time values are user programmable and are held in two registers.
An alternate set of high/low count values is held in second set of registers to allow the generation of dual
frequency FSK (frequency shift keying) protocols without CPU intervention.
NOTE
Only non-zero data values are allowed. The carrier generator will not work
if any of the count values are equal to zero.
The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier
generator clocks. When the BASE bit is set, the carrier output to the modulator is held high continuously.
The block diagram is shown in Figure 17-3.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-5
Carrier Modulator Timer (CMT) Module
CMTCGH2
CMTCGH1
=?
CMTCLK
BASE
FSK
CLK
CLR
8-BIT UP COUNTER
PRIMARY/
SECONDAR
SELECT
MCGEN
CARRIER OUT (fCG
)
=?
CMTCGL1
CMTCGL2
Figure 17-3. Carrier Generator Block Diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are
compared with the appropriate high or low count value register. When the compare value is reached, the
counter is reset to a value of 0x01, and the compare is redirected to the other count value register.
Assuming that the high time count compare register is currently active, a valid compare will cause the
carrier output to be driven low. The counter will continue to increment (starting at reset value of 0x01).
When the value stored in the selected low count value register is reached, the counter will again be reset
and the carrier output will be driven high.
The cycle repeats, automatically generating a periodic signal that is directed to the modulator. The lowest
frequency (maximum period) and highest frequency (minimum period) that can be generated are defined
as:
f
= fCMTCLK / (2 x 1) Hz
Eqn. 17-1
Eqn. 17-2
max
8
f
= fCMTCLK / (2 x (2 – 1)) Hz
min
In the general case, the carrier generator output frequency is:
f
= fCMTCLK / (Highcount + Lowcount) Hz
Eqn. 17-3
CG
Where:
0 < Highcount < 256 and
0 < Lowcount < 256
MC13234/MC13237 Reference Manual, Rev. 1.8
17-6
Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low-plus-high time.
As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts
required to generate the desired carrier period.
Highcount
Highcount + Lowcount
Duty Cycle = ---------------------------------------------------------------------
Eqn. 17-4
17.5.4 Modulator
The modulator block diagram is shown in Figure 17-4. The modulator has three main modes of operation:
•
•
•
Gate the carrier onto the modulator output (time mode)
Control the logic level of the modulator output (baseband mode)
Count carrier periods and instruct the carrier generator to alternate between two carrier frequencies
whenever a modulation period (mark + space counts) expires (FSK mode)
The modulator includes a 17-bit down counter with underflow detection. The counter is loaded from the
16-bit modulation mark period buffer registers, CMTCMD1 and CMTCMD2. The most significant bit is
loaded with a logic zero and serves as a sign bit. When the counter holds a positive value, the modulator
gate is open and the carrier signal is driven to the transmitter block.
When the counter underflows, the modulator gate is closed and a 16-bit comparator is enabled that
compares the logical complement of the value of the down-counter with the contents of the modulation
space period register (which has been loaded from the registers CMTCMD3 and CMTCMD4).
When a match is obtained the cycle repeats by opening the modulator gate, reloading the counter with the
contents of CMTCMD1 and CMTCMD2, and reloading the modulation space period register with the
contents of CMTCMD3 and CMTCMD4.
If the contents of the modulation space period register are all zeroes, the match will be immediate and no
space period will be generated (for instance, for FSK protocols that require successive bursts of different
frequencies).
The MCGEN bit in the CMTMSC register must be set to enable the modulator timer.
NOTE
The CMTCLK input is then prescaled by a divide ratio of 8 before clocking
the modulator counters. The minimum clock period for the modulator then
is 62.5 ns times 8 or 500 ns.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-7
Carrier Modulator Timer (CMT) Module
16 BITS
MODE
CMTCMD1:CMTCMD2
0
CMTCLOCK
8
CLOCK CONTROL
.
17-BIT DOWN COUNTER *
16
CARRIER OUT (fCG
)
LOAD
MODULATOR
OUT
MODULATOR GATE
EOC FLAG SET
.
=?
SYSTEM CONTROL
MODULE INTERRUPT REQUEST
PRIMARY/SECONDARY SELECT
16
SPACE PERIOD REGISTER *
CMTCMD3:CMTCMD4
16 BITS
* DENOTES HIDDEN REGISTER
Figure 17-4. Modulator Block Diagram
17.5.4.1 Modulator Time Mode
When the modulator operates in time mode (MCGEN bit is set, BASE bit is clear, and FSK bit is clear),
the modulation mark period consists of an integer number of CMTCLK/8 clock periods. The modulation
space period consists of zero or an integer number of CMTCLK/8 clock periods. With an 16 MHz bus and
CMTDIV[2:0] = 00, the modulator resolution is 0.5 s and has a maximum mark and space period of
about 32.767 ms each. See Figure 17-5 for an example of the time mode and baseband mode outputs.
The mark and space time equations for time and baseband mode are:
t
= (CMTCMD1:CMTCMD2 + 1) / (fCMTCLK / 8)
Eqn. 17-5
Eqn. 17-6
mark
t
= CMTCMD3:CMTCMD4 / (fCMTCLK / 8)
space
where CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated
registers.
NOTE
If the modulator is disabled while the t
time is less than the programmed
mark
carrier high time (t
< CMTCGH1/f
), the modulator can enter
mark
CMTCLK
into an illegal state and end the current cycle before the programmed value.
Make sure to program t
greater than the carrier high time to avoid this
mark
illegal state.
MC13234/MC13237 Reference Manual, Rev. 1.8
17-8
Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
CMTCLK8
(f
CARRIER OUT
)
CG
MODULATOR GATE
MARK
SPACE
MARK
IRO PIN (TIME MODE)
IRO PIN
(BASEBAND MODE)
Figure 17-5. Example CMT Output in Time and Baseband Modes
17.5.4.2 Modulator Baseband Mode
Baseband mode (MCGEN bit is set and BASE bit is set) is a derivative of time mode, where the mark and
space period is based on (CMTCLK / 8) counts. The mark and space calculations are the same as in time
mode. In this mode the modulator output will be at a logic 1 for the duration of the mark period and at a
logic 0 for the duration of a space period. See Figure 17-5 for an example of the output for both baseband
and time modes. In the example, the carrier out frequency (f ) is generated with a high count of 0x01 and
CG
a low count of 0x02, which results in a divide of 3 of CMTCLK with a 33 percent duty cycle. The
modulator down-counter was loaded with the value 0x0003 and the space period register with 0x0002.
NOTE
The waveforms in Figure 17-4 and Figure 17-5 are for the purpose of
conceptual illustration and are not meant to represent precise timing
relationships between the signals shown.
17.5.4.3 Modulator FSK Mode
When the modulator operates in FSK mode (MCGEN bit is set, FSK bit is set, and BASE bit is clear), the
modulation mark and space periods consist of an integer number of carrier clocks (space period can be 0).
When the mark period expires, the space period is transparently started (as in time mode). The carrier
generator toggles between primary and secondary data register values whenever the modulator space
period expires.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-9
Carrier Modulator Timer (CMT) Module
The space period provides an interpulse gap (no carrier). If CMTCMD3:CMTCMD4 = 0x0000, then the
modulator and carrier generator will switch between carrier frequencies without a gap or any carrier
glitches (zero space).
Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode can
automatically generate a phase-coherent, dual-frequency FSK signal with programmable burst and
interburst gaps.
The mark and space time equations for FSK mode are:
t
= (CMTCMD1:CMTCMD2 + 1) / f
Eqn. 17-7
Eqn. 17-8
mark
CG
t
= CMTCMD3:CMTCMD4 / f
space
CG
Where f is the frequency output from the carrier generator. The example in Figure 17-6 shows what the
CG
IRO pin output looks like in FSK mode with the following values: CMTCMD1:CMTCMD2 = 0x0003,
CMTCMD3:CMTCMD4 = 0x0002, primary carrier high count = 0x01, primary carrier low count = 0x02,
secondary carrier high count = 0x03, and secondary carrier low count = 0x01.
(f
CARRIER OUT
)
CG
SPACE1
MARK1
MARK2
SPACE2
MARK1
MARK2
SPACE1
ODULATOR GATE
IRO PIN
Figure 17-6. Example CMT Output in FSK Mode
17.5.5 Extended Space Operation
In time, baseband, or FSK mode, the space period can be made longer than the maximum possible value
of the space period register. Setting the EXSPC bit in the CMTMSC register will force the modulator to
treat the next modulation period (beginning with the next load of the counter and space period register) as
a space period equal in length to the mark and space counts combined. Subsequent modulation periods will
consist entirely of these extended space periods with no mark periods. Clearing EXSPC will return the
modulator to standard operation at the beginning of the next modulation period.
MC13234/MC13237 Reference Manual, Rev. 1.8
17-10
Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
17.5.5.1 EXSPC Operation in Time Mode
To calculate the length of an extended space in time or baseband modes, add the mark and space times and
multiply by the number of modulation periods that EXSPC is set.
t
= t
+ (t
+ t ) x (number of modulation periods)
space
Eqn. 17-9
exspace
space
mark
For an example of extended space operation, see Figure 17-7.
NOTE
The EXSPC feature can be used to emulate a zero mark event.
SET EXSPC
CLEAR EXSPC
Figure 17-7. Extended Space Operation
17.5.5.2 EXSPC Operation in FSK Mode
In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and
secondary registers at the end of each modulation period.
To calculate the length of an extended space in FSK mode, the user must know whether the EXSPC bit
was set on a primary or secondary modulation period, as well as the total number of both primary and
secondary modulation periods completed while the EXSPC bit is high. A status bit for the current
modulation is not accessible to the CPU. If necessary, software should maintain tracking of the current
modulation cycle (primary or secondary). The extended space period ends at the completion of the space
period time of the modulation period during which the EXSPC bit is cleared.
If the EXSPC bit was set during a primary modulation cycle, use the equation:
t
= (t
) + (t
+ t
) + (t
+ t ) +...
space p
Eqn. 17-10
exspace
space p
mark
space s
mark
Where the subscripts p and s see mark and space times for the primary and secondary modulation cycles.
If the EXSPC bit was set during a secondary modulation cycle, use the equation:
t
= (t
) + (t
+ t
) + (t
+ t ) +...
space s
Eqn. 17-11
exspace
space s
mark
space p
mark
17.5.6 Transmitter
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
to the IRO pin when the modulator/carrier generator is enabled. When the modulator/carrier generator is
disabled, the IRO pin is controlled by the state of the IRO latch.
A polarity bit in the CMTOC register enables the IRO pin to be high true or low true.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
17-11
Carrier Modulator Timer (CMT) Module
17.5.7 CMT Interrupts
The CMT has only one source of an interrupt request which is the end of cycle flag (EOCF). This status
flag is set when:
•
The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
transmission
•
At the end of each modulation cycle (when the counter is reloaded from CMTCMD1:CMTCMD2)
while the MCGEN bit is set
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, the EOCF
bit will not be set when the MCGEN is set, but will become set at the end of the current modulation cycle.
When the MCGEN becomes disabled, the CMT module does not set the EOC flag at the end of the last
modulation cycle.
The EOCF bit is cleared by reading the CMT modulator status and control register (CMTMSC) followed
by an access of CMTCMD2 or CMTCMD4.
If the EOC interrupt enable (EOCIE) bit is high when the EOCF bit is set, the CMT module will generate
an interrupt request. The EOCF bit must be cleared within the interrupt service routine to prevent another
interrupt from being generated after exiting the interrupt service routine.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMTCMD1:CMTCMD2 and loading the space period register with the contents of
CMTCMD3:CMTCMD4. The EOC interrupt provides a means for the user to reload new mark/space
values into the modulator data registers. Modulator data register updates will take effect at the end of the
current modulation cycle. Note that the down-counter and space period register are updated at the end of
every modulation cycle, regardless of interrupt handling and the state of the EOCF flag.
NOTE
If the CMT output is disabled, the CMT can be programmed for operation
and still generate a corresponding status. This mode may be used as a
cyclical timer to supplement other device timing resources.
17.6 Modes of Operation
The CMT is affected by the device mode of operation and the module clock can be disabled:
•
For lower power, the CMT module clock can be disabled via the SPI control bit of the SCGC1
Register
•
LPRun - the reference oscillator is divided by 64 and all clocks are scaled by this factor. It is
recommended to disable the CMT during this mode as all frequencies and timing changes
accordingly.
•
Wait modes - there are two wait modes
— Wait - when entered, the CPU clock is disabled and the bus clock still runs at normal speed .
The CMT, if enabled, will continue to operate normally. However, there will be no new codes
or changes of pattern mode while in wait mode, because the CPU is not operating.
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Carrier Modulator Timer (CMT) Module
— LP Wait - when entered, the CPU clock is disabled and the bus clock still runs but at a reduced
speed. The CMT, if enabled, will continue to operate, however, all timing would be incorrect.
Operation is not recommended.
•
•
The CMT is disabled in Stop3 mode, regardless of the settings before executing the STOP
instruction.
— During Stop3 mode, clocks to the CMT module are halted. No registers are affected. If Stop3
is exited with a reset, the CMT will be put into its reset state. If Stop3 is exited with an interrupt,
the CMT will resume operation. Software should ensure Stop3 mode is not entered while the
modulator is in operation to prevent the IRO pin from being asserted while in stop mode. This
may require a time-out period from the time that the MCGEN bit is cleared to allow the last
modulator cycle to complete.
Background Mode Operation -When the microcontroller is in active background mode, the CMT
temporarily suspends all counting until the microcontroller returns to normal user mode.
17.7 Register Definition
The following registers control and monitor CMT operation:
•
•
•
•
CMT carrier generator data registers (CMTCGH1, CMTCGL1, CMTCGH2, CMTCGL2)
CMT output control register (CMTOC)
CMT modulator status and control register (CMTMSC)
CMT modulator period data registers (CMTCMD1, CMTCMD2, CMTCMD3, CMTCMD4)
The CMT registers are all located in the Direct-Page Register Map.
17.7.1 Carrier Generator Data Registers ( CMTCGH1, CMTCGL1,
CMTCGH2, and CMTCGL2)
The carrier generator data registers contain the primary and secondary high and low values for generating
the carrier output.
CMTCGH1
0x0060
7
6
5
4
3
2
1
0
R
W
PH7
PH6
u
PH5
PH4
PH3
PH2
PH1
PH0
Reset
u
u
u
u
u
u
u
u = Unaffected
Figure 17-8. Carrier Generator Data Register CMTCGH1
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Freescale Semiconductor
17-13
Carrier Modulator Timer (CMT) Module
Table 17-3. CMTCGH1 Field Descriptions
Description
Field
7:0
PH[7:0]
Primary Carrier High Time Data Values — When selected, these bits contain the number of input clocks
required to generate the carrier high and low time periods. When operating in time mode (see Section 17.5.4.1,
“Modulator Time Mode”), this register pair is always selected. When operating in FSK mode (see
Section 17.5.4.3, “Modulator FSK Mode”), this register pair and the secondary register pair are alternatively
selected under control of the modulator. The primary carrier high and low time values are unaffected out of reset.
These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results.
CMTCGL1
0x0061
7
6
5
4
3
2
1
0
R
PL7
PL6
u
PL5
PL4
PL3
PL2
PL1
PL0
W
Reset
u
u
u
u
u
u
u
u = Unaffected
Figure 17-9. Carrier Generator Data Register CMTCGL1
Table 17-4. CMTCGL1 Field Descriptions
Description
Field
7:0
PL[7:0]
Primary Carrier Low Time Data Values — When selected, these bits contain the number of input clocks
required to generate the carrier high and low time periods. When operating in time mode (see Section 17.5.4.1,
“Modulator Time Mode”), this register pair is always selected. When operating in FSK mode (see
Section 17.5.4.3, “Modulator FSK Mode”), this register pair and the secondary register pair are alternatively
selected under control of the modulator. The primary carrier high and low time values are unaffected out of reset.
These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results.
CMTCGH2
0x0062
7
6
5
4
3
2
1
0
R
SH7
SH6
u
SH5
SH4
SH3
SH2
SH1
SH0
W
Reset
u
u
u
u
u
u
u
u = Unaffected
Figure 17-10. Carrier Generator Data Register CMTCGH2
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Freescale Semiconductor
Carrier Modulator Timer (CMT) Module
Table 17-5. CMTCGH2 Field Descriptions
Description
Field
7:0
SH[7:0]
Secondary Carrier High Time Data Values — When selected, these bits contain the number of input clocks
required to generate the carrier high and low time periods. When operating in time mode (see Section 17.5.4.1,
“Modulator Time Mode”), this register pair is never selected. When operating in FSK mode (see Section 17.5.4.3,
“Modulator FSK Mode”), this register pair and the primary register pair are alternatively selected under control of
the modulator. The secondary carrier high and low time values are unaffected out of reset. These bits must be
written to nonzero values before the carrier generator is enabled when operating in FSK mode.
CMTCGL2
0x0063
7
6
5
4
3
2
1
0
R
SL7
SL6
u
SL5
SL4
SL3
SL2
SL1
SL0
W
Reset
u
u
u
u
u
u
u
u = Unaffected
Table 17-6. CMTCGL2 Field Descriptions
Description
Field
7:0
SL[7:0]
Secondary Carrier Low Time Data Values — When selected, these bits contain the number of input clocks
required to generate the carrier high and low time periods. When operating in time mode (see Section 17.5.4.1,
“Modulator Time Mode”), this register pair is never selected. When operating in FSK mode (see Section 17.5.4.3,
“Modulator FSK Mode”), this register pair and the primary register pair are alternatively selected under control of
the modulator. The secondary carrier high and low time values are unaffected out of reset. These bits must be
written to nonzero values before the carrier generator is enabled when operating in FSK mode.
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Freescale Semiconductor
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Carrier Modulator Timer (CMT) Module
17.7.2 CMT Output Control Register (CMTOC)
This register is used to control the IRO output of the CMT module.
CMTOC
0x0064
7
6
5
4
3
2
1
0
R
W
0
0
0
0
IROL
CMTPOL
IROPEN
CMTDIV2
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
IROPEN
Figure 17-11. CMT Output Control Register (CMTOC)
Table 17-7. CMTOC Field Descriptions
Description
Field
7
IRO Latch Control — Reading IROL reads the state of the IRO latch. Writing IROL changes the state of the IRO
IROL
pin when the MCGEN bit is clear in the CMTMSC register and the IROPEN bit is set.
6
CMT Output Polarity — The CMTPOL bit controls the polarity of the IRO pin output of the CMT.
CMTPOL 0 IRO pin is active low
1 IRO pin is active high
5
IRO Pin Enable — The IROPEN bit is used to enable and disable the IRO pin. When the pin is enabled, it is an
IROPEN
output that drives out either the CMT transmitter output or the state of the IROL bit depending on whether the
MCGEN bit in the CMTMSC register is set. Also, the state of the output is either inverted or not depending on
the state of the CMTPOL bit. When the pin is disabled, it is in a high impedance state so it doesn’t draw any
current. The pin is disabled during reset.
0 IRO pin disabled
1 IRO pin enabled as output
4
CMT Clock Divide Prescaler 2— This field is the MSB of the 3-bit CMTDIV[2:0] field that sets the clock prescaler
CMTDIV2 ratio for the CMTCLK. CMTDIV[2:0] are Bit6 and Bit 5 of the CMTMSC Register. See Table 17-1for field settings
and pre scale divide ratios.
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Carrier Modulator Timer (CMT) Module
17.7.3 CMT Modulator Status and Control Register (CMTMSC)
The CMT modulator status and control register (CMTMSC) contains the modulator and carrier generator
enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
(BASE), extended space (EXSPC), prescaler (CMTDIV1:CMTDIV0) bits, and the end of cycle (EOCF)
status bit.
CMTMSC
0x0065
7
6
5
4
3
2
1
0
R
W
EOCF
CMTDIV1
0
CMTDIV0
EXSPC
BASE
FSK
EOCIE
0
MCGEN
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-12. CMT Modulator Status and Control Register (CMTMSC)
Table 17-8. CMTMSC Field Descriptions
Field
Description
7
End of Cycle Status Flag — The EOCF bit is set when:
EOCF
•
•
The modulator is not currently active and the MCGEN bit is set to begin the initial CMT transmission.
At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match occurs
between the contents of the space period register and the down-counter. At this time, the counter is
initialized with the (possibly new) contents of the mark period buffer, CMTCMD1 and CMTCMD2. The
space period register is loaded with the (possibly new) contents of the space period buffer, CMTCMD3 and
CMTCMD4.
This flag is cleared by a read of the CMTMSC register followed by an access of CMTCMD2 or CMTCMD4.
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, EOCF will not
be set when MCGEN is set, but will be set at the end of the current modulation cycle.
0
1
No end of modulation cycle occurrence since flag last cleared
End of modulator cycle has occurred
6:5
CMT Clock Divide Prescaler [1:0]— This field is the LS two bits of the 3-bit CMTDIV[2:0] field that sets the clock
CMTDIV[1:0] prescaler ratio for the CMTCLK. CMTDIV3 is Bit 4 of the CMTOC Register. See Table 17-1for field settings and
pre scale divide ratios.
4
Extended Space Enable — The EXSPC bit enables extended space operation.
EXSPC
0
1
Extended space disabled
Extended space enabled
3
Baseband Enable — When set, the BASE bit disables the carrier generator and forces the carrier output high
for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output
toggles at the frequency determined by values stored in the carrier data registers. See Section 17.5.4.2,
“Modulator Baseband Mode”. This bit is cleared by reset. This bit is not double buffered and should not be written
to during a transmission.
BASE
0
1
Baseband mode disabled
Baseband mode enabled
2
FSK Mode Select — The FSK bit enables FSK operation.
FSK
0
1
CMT operates in time or baseband mode
CMT operates in FSK mode
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Freescale Semiconductor
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Carrier Modulator Timer (CMT) Module
Table 17-8. CMTMSC Field Descriptions (continued)
Field
Description
1
End of Cycle Interrupt Enable — A CPU interrupt will be requested when EOCF is set if EOCIE is high.
EOCIE
0
1
CPU interrupt disabled
CPU interrupt enabled
0
Modulator and Carrier Generator Enable — Setting MCGEN will initialize the carrier generator and modulator
and enable all clocks. After it is enabled, the carrier generator and modulator will function continuously. When
MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks
are disabled (to save power) and the modulator output is forced low. To prevent spurious operation, the user
should initialize all data and control registers before enabling the system.
MCGEN
0
1
Modulator and carrier generator disabled
Modulator and carrier generator enabled
17.7.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3,
and CMTCMD4)
The modulator data registers control the mark and space periods of the modulator for all modes. The
contents of these registers are transferred to the modulator down counter and space period register upon
the completion of a modulation period.
Table 17-9. CMTCMDx Registers
Name
7
6
5
4
3
2
1
0
CMTCMD1
R
W
R
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
0x0066
CMTCMD2
MB7
SB15
SB7
MB6
SB14
SB6
MB5
SB13
SB5
MB4
SB12
SB4
MB3
SB11
SB3
MB2
SB10
SB2
MB1
SB9
SB1
MB0
SB8
SB0
W
R
0x0067
CMTCMD3
W
R
0x0068
CMTCMD4
W
0x0068
Table 17-10. CMT Modulator Data Registers Field Descriptions
Description
Field
CMTCMD1[7:0] Mark Data [15:8] - Contains high byte of 16-bit modulator mark period buffer
MB[15:8]
CMTCMD2[7:0] Mark Data [7:0] - Contains low byte of 16-bit modulator mark period buffer
MB[7:0]
CMTCMD3[7:0] Space Data [15:8] - Contains high byte of 16-bit modulator space period buffer
SB[15:8]
CMTCMD4[7:0] Space Data [7:0] - Contains high byte of 16-bit modulator space period buffer
SB[7:0]
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Freescale Semiconductor
Chapter 18
Development Support
18.1 Introduction
The MC13234/MC13237 provides a comprehensive debug/development capability for the HCS08 MCU.
The debug system is implemented using two blocks:
•
•
The Background Debug Controller (BDC) - has a single-wire debug interface (signal BKGD) to
the MCU that provides a convenient interface for programming the on-chip flash and other
nonvolatile memories. The BDC is also the primary debug interface for development and allows
non-intrusive access to memory data and traditional debug features such as CPU register modify,
breakpoints, and single instruction trace commands.
The on-chip Debug Module (DBG) - implements an on-chip ICE (in-circuit emulation) system and
allows non-intrusive debug of application software by providing an on-chip trace buffer with
flexible triggering capability
The single-wire background debug interface supports in-circuit programming of on-chip nonvolatile
memory and sophisticated non-intrusive debug capabilities that does not interfere with normal application
resources. It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
Because the MC13234/MC13237 does not have external address and data buses, the most important
functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists
of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide
when to capture bus information and what information to capture. The system relies on the single-wire
background debug system to access debug control registers and to read results out of the eight stage FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map.
These registers are located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any
of the control and status registers for the debug module.
18.1.1 Features
Features of the background debug controller (BDC) include:
•
•
•
•
•
Single pin for mode selection and background communications
BDC registers are not located in the memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background mode commands for CPU register access
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Freescale Semiconductor
18-1
Development Support
•
•
•
•
•
GO and TRACE1 commands
BACKGROUND command can wake CPU from stop or wait modes
One hardware address breakpoint built into BDC
Oscillator runs in stop mode, if BDC enabled
COP watchdog disabled while in active background mode
Features of the debug module (DBG) include:
•
•
•
Two trigger comparators:
— Two address + read/write (R/W)
— One full address + data + R/W
Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses
— Event-only data
Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
•
Nine trigger modes:
— A-only
— A OR B
— A then B
— A AND B data (full mode)
— A AND NOT B data (full mode)
— Event-only B (store data)
— A then event-only B (store data)
— Inside range (A address B)
— Outside range (address < A or address > B)
18.1.2 Forcing Active Background Mode
Active background mode can be forced as follows:
•
•
After a power-on reset by holding the BKGD pin low as the device exits the reset condition.
By driving BKGD low immediately after a serial background command that writes a one to the
BDFR bit in the SBDFR register.
Other causes of reset including an external pin reset or an internally generated error reset ignore the state
of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the
MCU will always reset into normal operating mode
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Freescale Semiconductor
Development Support
18.1.3 Debug Clock
The Bus Clock (default 16 MHz) is the source clock to the BDG and the debug port. The bus clock to the
DBG can be gated on and off using the DBG bit in SCGC2. This bit is set after any reset, which enables
the bus clock to this module. To conserve power, the DBG bit can be cleared to disable the clock to this
module when not in use. See Section 5.4.4, “Managing Clock Resources”, for details.
18.2 Background Debug Controller (BDC)
The BDC module operation and registers are described in the following description
18.2.1 BDC Overview
The MC13234/MC13237 BDC module provides a single-wire background debug interface that supports
in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities.
It does not interfere with normal application resources and does not use any user memory or locations in
the memory map and does not share any on-chip peripherals.
18.2.2 Block Diagram
Figure 18-1 is a block diagram of the BDC.
BDC Controller
CPU Command Interface
Register Bank
Breakpoint Unit
Serial Interface
Figure 18-1. Block Diagram
BDC commands are divided into two groups:
•
Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.
•
Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
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Freescale Semiconductor
18-3
Development Support
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod.
18.2.3 Standard Debug (BDM) Port
The single pin serial debug communications port is connected to the BDC and uses external signal BKGD.
Typically, a simple debug interface pod is connected to the BDM port (see Figure 18-2) and is used to
translate commands from a host computer to the single-wire, serial interface background debug port.
•
The pod typically connects to the MC13234/MC13237 through a standardized port with ground,
the BKGD pin, RESET, and VDD connections.
•
If used, the RESET is an open-drain drive to the MC13234/MC13237 reset input that allows the
host to force a target system hardware reset, which is useful to regain control of a lost target system
or to control startup of a target system before the on-chip nonvolatile memory has been
programmed.
•
VDD is the target system supply voltage and is not required. However, VDD can be used to supply
pod power from the target system to avoid the need for a separate power supply. If the pod is
powered separately, it can be connected to a running target system without forcing a target system
reset or otherwise disturbing the running application program.
BKGD 1
NC 3
2 GND
4 RESET
6 VDD
NC 5
Figure 18-2. Standard BDM Port Connector
18.2.4 BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
MC13234/MC13237 Reference Manual, Rev. 1.8
18-4
Freescale Semiconductor
Development Support
VBatt
HCS08 Core
Pullup
BDC Hi-Z enable
BDC data out
HOST data in
BKGD
Figure 18-3. BKGD Pin Logic
BDC serial communications use a custom serial protocol that assumes the host knows the communication
clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled
by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are
sent most significant bit first (MSB first).
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and has an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
The source of this speedup pulse is the host for transmit cases and the target for receive cases.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU
into active background mode after reset. It is not necessary to reset the target MCU to communicate with
it through the background debug interface.
18.2.5 Serial Interface Communication Protocol
The communication channel protocol and timing are described in the following sections.
18.2.5.1 General Command protocol
As previously stated, the communication channel uses a single-wire interface that has a command protocol
implemented on it. Figure 18-4 shows a generalized top-level command protocol.
•
•
All commands are initiated by the host
The host to the target command includes -
— Always an 8-bit command opcode
— Any additional command information (if required) - 1) address alone , or 2) address and data
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Freescale Semiconductor
18-5
Development Support
•
After any required wait, the target will send an ACK pulse, followed by any required read data or
status
•
•
•
All address data is a 16-bit length
Write data can be an 8-bit or 16-bit length based on the command
Read data can be an 8-bit or 16-bit length based on the command
Target
Host
BYTE is
Retrieved
BKGD Pin
COMMAND
Host
Byte Address
Target
New BDC Command
Host Target
BDC Issues the
ACK Pulse (out of scale)
CPU Executes the
READ_BYTE
Command
BDC Decodes the Command
Figure 18-4. BDM Command Level Protocol
18.2.5.2 Serial Bit Timing
The serial command protocol is composed of individual “serial bits” with timing as described in this
section. For each serial bit of data:
NOTE
BKGD is a pseudo-open-drain pin that can be driven either by an external
controller or by the MCU
•
The external controller generates a falling edge on the BKGD pin to indicate the start of each bit
time. The external controller provides this falling edge whether data is transmitted or received.
•
•
Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed).
The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any
BDC command that was in progress when this time-out occurs is aborted without affecting the
memory or operating mode of the target MCU system.
The protocol requires the debug pod to know the target BDC communication clock speed. For the
MC13234/MC13237 the serial interface runs from the Bus Clock; the bus clock is 1/2 the reference
oscillator frequency or 16MHz.
NOTE
•
•
The MC13234/MC13237 reference oscillator must be running for the
BDM port to be functional.
When the BDM port is not in used, the bus clock to the DBG can be
gated on and off using the DBG bit in SCGC2. This bit is set after any
reset, which enables the bus clock to this module. To conserve power,
the DBG bit can be cleared to disable the clock to this module when not
in use. See Section 5.4.4, “Managing Clock Resources” for details.
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Freescale Semiconductor
Development Support
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The target BKGD pin can receive a high or low level or transmit a high or low level. The following
diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC,
but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
18.2.5.2.1
Host-to-Target Bit Timing
Figure 18-5 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target. The host is
asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where
the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the
bit level on the BKGD pin. Typically, the host actively drives the BKGD pin during host-to-target
transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the
host-to-target transmission period, there is no need to treat the line as an open-drain signal during this
period.
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
BIT 0 IS VALID
EARLIEST
START OF
NEXT BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
PERCEIVED
START OF BIT TIME
TARGET SENSES BIT
BIT 1 IS VALID
Figure 18-5. BDC Host-to-Target Serial Bit Timing
18.2.5.2.2
Target-to-Host Bit Timing
Figure 18-6 shows the host retrieving a logic 1 from the target. The host must hold the BKGD pin low,
typically for 4 clock cycles, which is enough for the target to recognize the neg-edge in the BKPD pin (it
should be at least two target clock cycles). After perceiving the neg-edge the target waits for seven target
clock cycles and then issues a speed-up pulse for one cycle. Note that, the host must release the BKGD pin
before the target drives the high speedup pulse, seven clock cycles after the perceived start of the bit time,
otherwise a conflict will occur. The host should sample the BKGD pin about 10 clock cycles after it started
the bit time to evaluate if it is a logic 1 or logic 0 bit retrieve.
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BDC CLOCK
(TARGET MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
TARGET MCU
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
PERCEIVED
START OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
SYNCHRONIZATION
UNCERTAINTY
HOST SAMPLES
BKGD PIN
Figure 18-6. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 18-7 shows the host retrieving a logic 0 from the target MCU. The host initiates the bit time, but
the target MCU finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin
low for 12 clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level
about 10 clock cycles after starting the bit time.
BDC CLOCK
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
SYNCHRONIZATION
UNCERTAINTY
HOST SAMPLES
BKGD PIN
Figure 18-7. BDC Target-to-Host Serial Bit Timing (Logic 0)
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18.2.5.3 Handshake Protocol using ACK
Because BDC commands are executed at the target bus rate and can be asynchronous to the serial interface
clock, a handshake or acknowledge signal (ACK) is provided to the host to determine when an issued
command has been executed by the target. Refer to Figure 18-4.
Figure 18-8 show the ACK pulse timing. The ACK is implemented as a 16 serial clock cycles low pulse
followed by a brief speedup pulse on the BKGD pin, generated by the target when a command had been
successfully executed.
•
After the ACK pulse has finished, the host can start the bit retrieve, if the last issued command was
a read command, or start a new command, if the last command was a write command or a control
command (BACKGROUND, GO, GO_UNTIL or TRACE1).
•
•
The ACK pulse is not issued any earlier then 32 serial clock cycles after the BDC command was
issued.
The end of the BDC command is assumed to be the 16th tick of the last bit. This minimum delay
assures enough time for the host to perceive the ACK pulse.
NOTE
There is no upper limit for the delay between the command and the related
ACK pulse.
•
If a BDC command is not acknowledged by an ACK pulse, the host must first abort the pending
command before issuing a new BDC command. - When the CPU enters Wait or Stop mode while
the host issues a command that requires CPU execution (e.g.: WRITE_BYTE), the target discards
the incoming command. Therefore, the command is not acknowledged by the target, which means
that the ACK pulse will not be issued in this case.
BDC CLOCK
(TARGET MCU)
16 CYCLES
TARGET
HIGH-IMPEDANCE
32 CYCLES
HIGH-IMPEDANCE
TRANSMITS
ACK
PULSE
SPEED UP PULSE
MINIMUM DELAY
FROM THE BDC COMMAND
BKGD PIN
EARLIEST
START OF
NEXT BIT
16th TICK OF THE
LAST COMMAD BIT
Figure 18-8. Target Acknowledge Pulse (ACK)
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18.2.5.4 Hardware Handshake Abort Procedure
If a BDC command has not been acknowledged, an abort procedure must be executed before issuing a new
command. The abort procedure is based on the SYNC command, which is really a timed Low pulse. To
execute the SYNC command, the host controller should generate a low pulse in the BKGD pin by driving
it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle for the speedup
pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, and
assumes that the pending command and therefore the related ACK pulse, are being aborted. After the
SYNC protocol completes, the host is free to issue new BDC commands. Figure 18-9 illustrates a SYNC
command aborting a READ_BYTE. Note that after the command is aborted, a new command could be
issued by the host computer.
It is important to notice that any issued BDC command that requires CPU execution will be executed at
the next instruction boundary, provided the CPU does not enter Wait or Stop modes. If the host aborts a
command by sending the SYNC pulse, it should then read the BDCSCR after the SYNC response is issued
by the target, checking for DVF = 0, before attempting to send any new command that requires CPU
execution. This prevents the new command from being discarded at the BDC-CPU interface, due to the
pending command being executed by the CPU. Any new command should be issued only after DVF = 0.
There are two reasons that could cause a command to take too long to be executed, measured in terms of
the serial communication rate. Either the BDC clock frequency is much faster if compared to the CPU
clock frequency, or the CPU is accessing a slow memory, which would cause suspend cycles to occur. The
hardware handshake protocol is appropriate for both situations, but the host could also decide to use the
software handshake protocol instead. In this case, if the DVF bit is at logic 1, there is a BDC command
pending at the BDC-CPU interface. The host controller should monitor the DVF bit and wait until it is at
logic 0 to be able to issue a new command that requires CPU execution. Note that the WSF BDCSCR bit
should be at logic 0 in this case. However, if WSF bit was at logic 1, the host should assume the last
command failed due to a WAIT or STOP instruction being executed by the CPU. In this case, the host
controller should enable background mode and then issue a BACKGROUND command to put the CPU
into background mode. After that, new commands could be issued, including those that require CPU
execution.
Figure 18-9 shows a SYNC command aborting a READ_BYTE. Note that after the command is aborted,
a new command could be issued by the host computer.
READ_BYTE Command is Aborted by the SYNC Request
(Out of Scale)
SYNC Response From the Target
(Out of Scale)
BKGD pin
READ_BYTE
host
Memory Address
target
READ_STATUS
host
new BDC command
host
target
target
New BDC Command
BDC Decodes
and Starts to Execute
the READ_BYTE Command
Figure 18-9. ACK Abort Procedure at the Command Level
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Figure 18-10 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug mode.
Consider that the target CPU is executing a pending BDC command at the exact moment the POD is being
connected to the BKGD pin. In this case an ACK pulse is issued along with the SYNC command. In this
case there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is
not a probable situation, the protocol does not prevent this conflict from happening.
at least 128 cycles
bdc clock
(target mcu)
ack pulse
target mcu
drives to
bkgd pin
high-impedance
electrical conflict
speedup pulse
host and target
drive to bkgd pin
host
drives sync
to bkgd pin
host sync request pulse
bkgd pin
16 cycles
Figure 18-10. ACK Pulse and SYNC Request Conflict
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDC commands, providing backwards compatibility with old POD devices, which may not support the
hardware handshake protocol. It also allows for new POD devices supporting the hardware handshake
protocol to freely communicate with the target device without the need for waiting for the ACK pulse, if
desired. The commands are described as follows:
•
ACK_ENABLE - enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
•
ACK_DISABLE - disables the ACK pulse protocol. In this case the host should verify the state of
the DVF bit in the BDC Status and Control register to evaluate if there are pending commands and
to check if the CPU changed to or from background mode.
The default state of the protocol, after reset, is hardware handshake protocol disabled.
The commands that do not require CPU execution, or that have the status register included in the retrieved
bit stream, do not perform the hardware handshake protocol. Therefore, the target will not respond with an
ACK pulse for those commands even if the hardware protocol was enabled. The commands are:
READ_STATUS, WRITE_CONTROL, WRITE_BWS, READ_BWS, READ_NWS, WRITE_NWS,
WRITE_BKPT, READ_BKPT, READ_LAST and ACK_DISABLE.
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NOTE
The TAGGO command does not have the ACK pulse as a response. Except
by the ACK pulse, this command is equivalent to the GO command. It is
being implemented for compatibility with previous BDC versions. The
HCS08 core does not provide support for external tag using the BKGD pin.
Only commands that require CPU execution perform the hardware handshake protocol. These commands
are: WRITE_BYTE, READ_BYTE, WRITE_NEXT, READ_NEXT, WRITE_A, READ_A,
WRITE_CCR, READ_CCR, WRITE_SP, READ_SP, WRITE_HX, READ_HX, WRITE_PC,
READ_PC. An exception is the ACK_ENABLE, which does not require CPU execution but responds with
the ACK pulse. This feature could be used by the host to evaluate if the target supports the hardware
handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target
supports the hardware handshake protocol. If the target does not support the hardware handshake protocol
the ACK pulse is not issued. In this case the ACK_ENABLE command is ignored by the target, because
it is not recognized as a valid command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to
background mode. The ACK pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse
related to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode
after one instruction of the application program is executed. The ACK pulse related to this command could
be aborted using the SYNC command.
The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this
case, is issued when the CPU enters into background mode. This command is an alternative to the GO
command and should be used if the host wants to trace if a breakpoint match had occurred which caused
the CPU to enter background mode. Note that the ACK is issued whenever the CPU enters BDM, which
could be caused by a BDC Breakpoint match, or an external force/tag, or by a BGND instruction being
executed. The ACK pulse related to this command could be aborted using the SYNC command.
The TAGGO command is equivalent to the GO command, but will not have an ACK pulse as a response.
This command is being kept for backwards compatibility reasons. It is expected that the GO command to
be used instead.
18.2.5.5 Serial Communication Time-out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD to answer the SYNC
request pulse. If the rising edge is not detected, the target will keep waiting forever, without any time-out
limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
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cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieving after the time-out
had occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider
the behavior where the BDC is running in a frequency much greater than the CPU frequency. In this case,
the command could time-out before the data is ready to be retrieved. To allow the data to be retrieved even
with a large clock frequency mismatch, between BDC and CPU, when the hardware handshake protocol
is enabled the time-out between a read command and the data retrieve is disabled. Therefore, the host could
wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read
command. However, after the handshake pulse is issued, the time-out feature is re-activated, meaning that
the target will time-out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512
serial clock cycles time frame after the ACK pulse had been issued. After that period the read command
is discarded and the data is no longer available for retrieve. Any neg-edge in the BKGD pin after the
time-out period is considered to be a new command or a SYNC request.
NOTE
Whenever a partially issued command, or partially retrieved data had
occurred, the time-out in the serial communication is active, meaning that,
if a time frame higher than 512 serial clock cycles is observed between two
consecutive negedges and the command being issued or data being retrieved
is not completed, a soft-reset will occur causing the partially received
command or data retrieve to be disregarded. The next negedge in the BKGD
pin, after the soft-reset had occurred, is considered by the target as the start
of a new BDC command, or the start of a SYNC request pulse.
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18.3 Register Definition
18.3.1 BDC Registers
The BDC provides two registers that can be accessed and modified with dedicated BDC commands: the
BDC Status and Control Register (BDCSCR) and the BDC Breakpoint Register (BDCBKPT). These
registers are not located in the memory space of the MCU (i.e., do not have addresses) and cannot be
accessed by user programs. They can only be accessed by the host computer through the serial single-wire
debug interface (BKGD pin).
18.3.1.1 BDC Status and Control Register
BDCSCR
Bit 7
Bit 6
Bit 5
Bit 4
FTS
Bit 3
Bit 2
WS
Bit 1
Bit 0
DVF
R
W
BDMACT
WSF
ENBDM
BKPTEN
CLKSW
Normal Reset
Reset in BDM
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
= Unimplemented
Figure 18-11. BDC Status and Control Register (BDCSCR)
Table 18-1. BDCSCR Field Descriptions
Description
Field
7
Enable Background Debug Mode. This is a read/write control bit. The CPU may enter background debug mode
only when this bit is set to logic one. If the CPU is placed in background debug mode, this control bit cannot be
written until background debug mode is exited.
ENBDM
1 = CPU is allowed to enter background debug mode.
0 = CPU is not allowed to enter background debug mode.
6
Background Debug Mode Active. This is a read-only status bit. This status bit is controlled by the CPU, and
BDMACT indicates if background debug mode is active. When this bit is set to logic one the BDMEN bit cannot not be
written by WRITE_CONTROL commands. Upon reset, while the CPU is executing the reset sequence, this bit
is a logic zero. If, however, during reset the BKGD pin was held low commanding “BDM out of reset”, soon after
the reset sequence finishes, the CPU will enter background mode (provided no higher priority exception is
present) and the BDMACT bit will be set to logic one.
1 = CPU is in background debug mode.
0 = CPU is not in background debug mode.
5
Breakpoint Enable bit. This is a read/write control bit. If this bit is set to logic one, the BDC breakpoint functionality
is enabled, provided that BDMEN is also set. If this bit is set to logic zero, the BDC breakpoint functionality is
disabled and the FTS control bit and the BDCBKPT match register are ignored.
1 = BDC breakpoint functionality enabled.
BKPTEN
0 = BDC breakpoint functionality disabled.
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Table 18-1. BDCSCR Field Descriptions (continued)
Description
Field
4
FTS
Force/Tag Select bit. This is a read/write control bit. If this bit is set to logic one, a breakpoint is requested
whenever a valid address in the CPU address bus matches the value in the BDCBKPT register. If this bit is set
to logic zero, a match between the address of a fetched opcode and the BDCBKPT register causes the fetched
opcode to be tagged. If this tagged opcode ever reaches the top of the instruction pipe unit, the CPU enters
background debug mode rather than executing the tagged opcode.
1 = Breakpoint match forces background debug mode at the next instruction boundary (provided no higher
priority events are present.)
0 = Tag opcode at breakpoint address and enter background debug mode if the CPU attempts to execute that
instruction (provided no higher priority event is present.)
3
Clock Switch bit. This is a read/write control bit. This bit controls the bypass mode of the BDC Local Oscillator
block. If it is set to logic zero the BDC Local Oscillator is engaged setting the rate for the serial communication
to be the BDC Local Oscillator rate. If it is set to logic one, the BDC Local Oscillator is disengaged, setting the
ext_lclk output clock signal to be connected to the ext_clk24 MCU clock signal. In this case the BDC serial rate
is the CPU frequency.
CLKSW
1 = Communication frequency is ext_clk24.
0 = Communication frequency is ext_lclk (BDC Local Oscillator frequency).
2
WS
Wait/Stop bit. This is a read-only status bit. This status bit is controlled by the CPU and indicates that the CPU is
in Wait/Stop mode, or the CPU exited Wait/Stop mode into background debug mode via a BACKGROUND
command.
1 = CPU is in Wait/Stop mode, or the CPU exited Wait/Stop mode into background debug mode via a
BACKGROUND command.
0 = CPU is not in Wait/Stop mode.
1
WSF
Wait/Stop Failure. This is a read-only status bit. This bit indicates that a foreground memory command failed
because the CPU was in Wait or Stop mode or was about to enter one of these modes. The recovery strategy is
to put the CPU in BDM active mode and re-issue the command in background mode.
1 = Foreground memory command failed because the CPU entered Wait of Stop mode.
0 = Foreground memory command did not conflict with Wait or Stop mode.
0
DVF
Data Valid Failure. This is a read-only status bit. This bit indicates that a CPU command failed or is pending. The
recovery strategy is to issue READ_LAST (for read accesses) or READ_STATUS (for write accesses)
commands until the status information indicates the CPU command had executed successfully.
1 = CPU command failed.
0 = CPU command executed successfully.
NOTE
The DVF bit is asserted also by the CPU registers access commands. This
behavior allows to execute the software handshake protocol when accessing
CPU registers. The READ_LAST instruction should be used to access the
last accessed CPU registers data, available after the DVF bit is cleared. Note
that the READ_LAST instruction returns 16 bit data only. For 8-bit register
read commands only the first byte transmitted should be considered as valid
data, the second byte has no meaning in this case.
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18.3.1.2 BDC Breakpoint Register
BDCBKPT
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-12. BDC Breakpoint Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register.
Breakpoints are normally set while the target MCU is in background debug mode before running the user
application program. However, because READ_BKPT and WRITE_BKPT are foreground commands,
they could be executed even while the user program is running.
18.3.2 DBG Registers
This section consists of the DBG register descriptions in address order.
Note: For all registers below, consider: U = Unchanged, bit maintain its value after reset.
18.3.2.1 Debug Comparator A High Register (DBGCAH)
DBGCAH
Base + 0x0000
7
6
5
4
3
2
1
0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
W
POR
or non-
end-run
1
1
1
1
1
1
1
1
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-13. Debug Comparator A High Register (DBGCAH)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-2. DBGCAH Field Descriptions
Field
Description
Bits 15–8 Comparator A High Compare Bits — The Comparator A High compare bits control whether Comparator A will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.2 Debug Comparator A Low Register (DBGCAL)
DBGCAL
Base + 0x0001
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
POR
or non-
end-run
1
1
1
1
1
1
1
0
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-14. Debug Comparator A Low Register
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-3. DBGCAL Field Descriptions
Field
Description
Bits 7–0
Comparator A Low Compare Bits — The Comparator A Low compare bits control whether Comparator A will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.3 Debug Comparator B High Register (DBGCBH)
DBGCBH
Base + 0x0002
7
6
5
4
3
2
1
0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-15. Debug Comparator B High Register (DBGCBH)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-4. DBGCBH Field Descriptions
Field
Description
Bits 15–8 Comparator B High Compare Bits — The Comparator B High compare bits control whether Comparator B will
compare the address bus bits [15:8] to a logic 1 or logic 0. Not used in Full mode.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.4 Debug Comparator B Low Register (DBGCBL)
DBGCBL
Base + 0x0003
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-16. Debug Comparator B Low Register (DBGCBL)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-5. DBGCBL Field Descriptions
Field
Description
Bits 7–0
Comparator B Low Compare Bits — The Comparator B Low compare bits control whether Comparator B will
compare the address bus or data bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0, compares to data if in Full mode
1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
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18.3.2.5 Debug Comparator C High Register (DBGCCH)
DBGCCCH
Base + 0x0004
7
6
5
4
3
2
1
0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-17. Debug Comparator C High Register (DBGCCH)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-6. DBGCCH Field Descriptions
Field
Description
Bits 15–8 Comparator C High Compare Bits — The Comparator C High compare bits control whether Comparator C will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.6 Debug Comparator C Low Register (DBGCCL)
DBGCCCL
Base + 0x0005
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
Figure 18-18. Debug Comparator C Low Register (DBGCCL)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-7. DBGCCL Field Descriptions
Field
Description
Bits 7–0
Comparator C Low Compare Bits — The Comparator C Low compare bits control whether Comparator C will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.7 Debug FIFO High Register (DBGFH)
DBGFH
Base + 0x0006
7
6
5
4
3
2
1
0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-19. Debug FIFO High Register (DBGFH)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-8. DBGFH Field Descriptions
Field
Description
Bits 15–8 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
18.3.2.8 Debug FIFO Low Register (DBGFL)
DBGFL
Base + 0x0007
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-20. Debug FIFO Low Register (DBGFL)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
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Table 18-9. DBGFL Field Descriptions
Description
Field
Bits 7–0
FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
18.3.2.9 Debug Comparator A Extension Register (DBGCAX)
DBGCAX
Base + 0x0008
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
RWAEN RWA PAGSEL
Bit 16
0
0
0
0
0
0
RWAEN RWA
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-21. Debug Comparator A Extension Register (DBGCAX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-10. DBGCAX Field Descriptions
Field
Description
7
Read/Write Comparator A Enable Bit — The RWAEN bit controls whether read or write comparison is enabled
RWAEN
for Comparator A.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
6
Read/Write Comparator A Value Bit — The RWA bit controls whether read or write is used in compare for
Comparator A. The RWA bit is not used if RWAEN = 0.
0 Write cycle will be matched
RWA
1 Read cycle will be matched
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Table 18-10. DBGCAX Field Descriptions (continued)
Description
Field
5
Comparator A Page Select Bit — This PAGSEL bit controls whether Comparator A will be qualified with the
internal signal (mmu_ppage_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_ppage_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value.
PAGSEL
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
leading zero at bit 16, or a 17-bit linear address pointer address{,}
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
PPAGE[2:0]:addr[13:0]{,}
0
Comparator A Extended Address Bit 16 Compare Bit — The Comparator A bit 16 compare bit controls
whether Comparator A will compare the core address bus bit 16 to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
Bit 16
1 Compare corresponding address bit to a logic 1
18.3.2.10 Debug Comparator B Extension Register (DBGCBX)
DBGCBX
Base + 0x0009
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
RWBEN RWB PAGSEL
Bit 16
0
0
0
0
0
0
RWBEN RWB
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-22. Debug Comparator B Extension Register (DBGCBX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
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Table 18-11. DBGCBX Field Descriptions
Description
Field
7
Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled
RWBEN
for Comparator B. In full modes, RWAEN and RWA are used to control comparison of R/W and RWBEN is
ignored.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
6
Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for
Comparator B. The RWB bit is not used if RWBEN = 0. In full modes, RWAEN and RWA are used to control
comparison of R/W and RWB is ignored.
RWB
0 Write cycle will be matched
1 Read cycle will be matched
5
Comparator B Page Select Bit — This PAGSEL bit controls whether Comparator B will be qualified with the
internal signal (mmu_papge_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_papge_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value. This bit is not used in full modes where
comparator B is used to match the data value.
PAGSEL
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
leading zero at bit 16, or a 17-bit linear address pointer address{,}
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
PPAGE[2:0]:addr[13:0]{,}
0
Comparator B Extended Address Bit 16 Compare Bit — The Comparator B bit 16 compare bit controls
whether Comparator B will compare the core address bus bit 16 to a logic 1 or logic 0. This bit is not used in full
modes where comparator B is used to match the data value.
Bit 16
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
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18.3.2.11 Debug Comparator C Extension Register (DBGCCX)
DBGCCX
Base + 0x000A
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
RWCEN RWC PAGSEL
Bit 16
0
0
0
0
0
0
RWCEN RWC
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-23. Debug Comparator C Extension Register (DBGCCX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-12. DBGCCX Field Descriptions
Field
Description
7
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for Comparator C{dbg_C_brk_rw,dbg_C_freecyc}.
RWCEN
0 Read/Write is not used in comparison{dbg_C_brk_rw,dbg_C_freecyc}
1 Read/Write is used in comparison{dbg_C_brk_rw,dbg_C_freecyc}
6
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
Comparator C{dbg_C_brk_rw,dbg_C_freecyc}. The RWC bit is not used if RWCEN =
0{dbg_C_brk_rw,dbg_C_freecyc}.
RWC
0 Write cycle will be matched{dbg_C_brk_rw,dbg_C_freecyc}
1 Read cycle will be matched{dbg_C_brk_rw,dbg_C_freecyc}
5
Comparator C Page Select Bit — This PAGSEL bit controls whether Comparator C will be qualified with the
internal signal (mmu_papge_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_papge_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value.
PAGSEL
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
leading zero at bit 16, or a 17-bit linear address pointer address{,}
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
PPAGE[2:0]:addr[13:0]{,}
0
Comparator C Extended Address Bit 16 Compare Bit — The Comparator C bit 16 compare bit controls
whether Comparator C will compare the core address bus bit 16 to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
Bit 16
1 Compare corresponding address bit to a logic 1
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18.3.2.12 Debug FIFO Extended Information Register (DBGFX)
DBGFX
Base + 0x000B
7
6
5
4
3
2
1
0
R PPACC
0
0
0
0
0
0
Bit 16
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-24. Debug FIFO Extended Information Register (DBGFX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Table 18-13. DBGFX Field Descriptions
Field
Description
7
PPAGE Access Indicator Bit — This bit indicates whether the captured information in the current FIFO word is
associated with an extended access through the PPAGE mechanism or not{,,}. This is indicated by the internal
signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address with
bit-16 = 0
PPACC
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three most
significant bits and CPU address[13:0] in the 14 least significant bits
0
Extended Address Bit 16 — This bit is the most significant bit of the 17-bit core address
Bit 16
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18.3.2.13 Debug Control Register (DBGC)
DBGC
Base + 0x000C
7
6
5
4
3
2
1
0
R
0
0
0
DBGEN ARM
TAG BRKEN
LOOP1
W
POR
or non-
end-run
1
1
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-25. Debug Control Register (DBGC)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining
control bits in this register do not change after reset.
Table 18-14. DBGC Field Descriptions
Field
Description
7
DBG Module Enable Bit — The DBGEN bit enables the DBG module. The DBGEN bit is forced to zero and
cannot be set if the MCU is secure{dbg_secure}.
DBGEN
0 DBG not enabled{,dbg_reg}
1 DBG enabled{,dbg_reg}
6
ARM
Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in FIFO. See
Section 18.4.2.4.2, “Arming the DBG Module” for more information.
0 Debugger not armed
1 Debugger armed
5
TAG
Tag or Force Bit — The TAG bit controls whether a debugger or comparator C breakpoint will be requested as
a tag or force breakpoint to the CPU. The TAG bit is not used if BRKEN = 0{,dbg_C_brk_tag_force,}.
0 Force request selected
1 Tag request selected
4
Break Enable Bit — The BRKEN bit controls whether the debugger will request a breakpoint to the CPU at the
end of a trace run, and whether comparator C will request a breakpoint to the CPU
0 CPU break request not enabled
BRKEN
1 CPU break request enabled
0
Select LOOP1 Capture Mode — This bit selects either normal capture mode or LOOP1 capture mode. LOOP1
is not used in event-only modes.
LOOP1
0 Normal operation - capture COF events into the capture buffer FIFO
1 LOOP1 capture mode enabled. When the conditions are met to store a COF value into the FIFO, compare the
current COF address with the address in comparator C. If these addresses match, override the FIFO capture
and do not increment the FIFO count. If the address does not match comparator C, capture the COF address,
including the PPACC indicator, into the FIFO and into comparator C.
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18.3.2.14 Debug Trigger Register (DBGT)
DBGT
Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
TRGSEL BEGIN
TRG
W2
POR
or non-
end-run
0
1
0
0
0
0
0
0
0
0
Reset
U
U
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-26. Debug Trigger Register (DBGT)
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the control bits in this register do not change after reset.
1
2 The DBG trigger register (DBGT) can not be changed unless ARM=0{dbg_reg}.
Table 18-15. DBGT Field Descriptions
Field
Description
7
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for the comparators. See
Section 18.4.2.4, “Trigger Break Control (TBC)” for more information.
0 Trigger on any compare address access
TRGSEL
1 Trigger if opcode at compare address is executed
6
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
BEGIN
0 Trigger at end of stored data
1 Trigger before storing data
3–0
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown in Table 18-16.
TRG
Table 18-16. Trigger Mode Encoding
TRG Value
Meaning
0000
0001
0010
0011
0100
0101
0110
0111
1000
A Only
A Or B
A Then B
Event Only B
A Then Event Only B
A And B (Full Mode)
A And Not B (Full mode)
Inside Range
Outside Range
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Table 18-16. Trigger Mode Encoding (continued)
TRG Value Meaning
1001
No Trigger
1111
NOTE
The DBG trigger register (DBGT) can not be changed unless
ARM=0{dbg_reg}.
18.3.2.15 Debug Status Register (DBGS)
DBGS
Base + 0x000E
7
6
5
4
3
2
1
0
R
W
AF
BF
CF
0
0
0
0
ARMF
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
1
0
Reset
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-27. Debug Status Register (DBGS)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF, BF, and CF do
not change after reset.
Table 18-17. DBGS Field Descriptions
Field
Description
7
AF
Trigger A Match Bit — The AF bit indicates if Trigger A match condition was met since arming.
0 Comparator A did not match
1 Comparator A match
6
BF
Trigger B Match Bit — The BF bit indicates if Trigger B match condition was met since arming.
0 Comparator B did not match
1 Comparator B match
5
CF
Trigger C Match Bit — The CF bit indicates if Trigger C match condition was met since arming.
0 Comparator C did not match
1 Comparator C match
0
Arm Flag Bit — The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill.
ARMF
While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See Section 18.4.2.4.2, “Arming
the DBG Module” for more information.
0 Debugger not armed
1 Debugger armed
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18.3.2.16 Debug Count Status Register (DBGCNT)
DBGCNT
Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
CNT
W
POR
or non-
end-run
0
0
0
0
0
0
0
0
0
0
0
0
Reset
U
U
U
U
end-run1
= Unimplemented or
Reserved
Figure 18-28. Debug Count Status Register (DBGCNT)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the CNT[3:0] bits do not change after reset.
Table 18-18. DBGS Field Descriptions
Field
Description
3–0
CNT
FIFO Valid Count Bits — The CNT bits indicate the amount of valid data stored in the FIFO. Table 18-19 shows
the correlation between the CNT bits and the amount of valid data in FIFO. The CNT will stop after a count to
eight even if more data is being stored in the FIFO. The CNT bits are cleared when the DBG module is armed,
and the count increments each time a new word is captured into the FIFO. The host development system is
responsible for checking the value in CNT[3:0] and reading the correct number of words from the FIFO because
the count does not decrement as data is read out of the FIFO at the end of a trace run.
Table 18-19. CNT Bits
CNT Value
Meaning
0000
0001
0010
0011
0100
0101
0110
0111
1000
No data valid
1 word valid
2 words valid
3 words valid
4 words valid
5 words valid
6 words valid
7 words valid
8 words valid
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18.4 Functional Description
18.4.1 BDC Functional Description
18.4.1.1 Background Debug Mode
The Background Debug Controller provides five methods to enter background debug mode provided the
mode is enabled via the ENBDM bit. Each of these methods is described below.
18.4.1.1.1
BACKGROUND command
The usual way to get into Background Debug Mode, after the mode is enabled, is by issuing a
BACKGROUND command from the host. This causes the BDC to issue a request to the CPU to enter
background debug mode. This request is handled by the CPU at instruction boundaries according to the
event priority.
The request to enter background debug mode interrupts the normal program flow and forces the CPU to
execute a BGND instruction. Upon entering background debug mode, the CPU sets the BDMACT bit in
the BDC status and control register. While in background debug mode, the ENBDM bit in the BDC status
and control register cannot be cleared through WRITE_CONTROL commands. Both foreground and
background commands can be executed while the CPU is in background debug mode. However, only
foreground commands can be executed in normal mode (i.e., user code running). Normal program flow
can be resumed with a GO, TRACE1, TAGGO or GO_UNTIL command. Execution starts with the
instruction that would have been executed had the BGND instruction not been forced, provided the
program counter is not altered while in background debug mode and no higher priority events are pending.
If the hardware handshake protocol is enabled, an ACK pulse is issued by the target as soon as the target
CPU enters background mode due to a BACKGROUND BDC instruction. The handshake abort procedure
should be used if the host decides to send a new BDC command before the ACK pulse is issued by the
target.
18.4.1.1.2
Hardware Breakpoint
The second method of entering background mode consists of using the hardware breakpoint functionality
of the BDC. To use the hardware breakpoint, the user must enable it by writing a logic one to the BKPTEN
bit in the BDCSCR register. This can be accomplished by issuing a WRITE_CONTROL command from
the host. Note that the ENBDM bit in the BDCSCR register must be a logic one to use the breakpoint
functionality. If ENBDM is a logic zero, the hardware breakpoint will not issue requests to the CPU
regardless of the value of BKPTEN.
The user can set a breakpoint address in the BDCBKPT register by issuing a WRITE_BKPT command.
The contents of the BDCBKPT register can be read by issuing the complementary READ_BKPT
command. The breakpoint circuitry of the BDC requests the CPU to enter background debug mode
whenever the contents of the BDCBKPT register match a valid address in the address bus. This request
can be generated in two different ways depending on the configuration of the breakpoint functionality.
The user should write a logic one to the FTS bit when he wishes to enter background debug mode as a
result of any valid access (read or write) to the breakpoint address. Under this configuration, if a valid
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address in the address bus matches the contents of the BDCBKPT register, the BDC requests the CPU to
enter background mode. As described before, this forces the CPU to execute a BGND instruction on an
instruction boundary if no higher priority events are pending.
Alternatively, the user should write a logic zero to the FTS bit when he wishes to enter background debug
mode instead of executing a specific instruction in the program sequence. Under this configuration, if the
address of a program read matches the contents of the BDCBKPT register, the BDC indicates to the CPU
that it should enter background debug mode when the current instruction in the read data bus reaches the
top of the instruction pipe. This is referred to as instruction tagging. If the data in the read data bus is tagged
but is not an instruction (due to user error) the request is ignored.
Note that while background debug mode is active, the breakpoint functionality is disabled. This implies
that while background debug mode is active the breakpoint functionality will not issue requests to the
CPU.
As in the first case, normal program flow can be resumed with a GO, TRACE1, TAGGO or GO_UNTIL
command. Execution starts with the instruction that would have been executed had the BGND instruction
not been forced, provided the PC is not altered while in background debug mode and no higher priority
events are pending.
If the hardware handshake protocol is enabled, an ACK pulse is issued by the target as soon as the target
CPU enters background mode, provide the GO_UNTIL command had been used to put the CPU in normal
mode. The SYNC command should be used if the host decides to send a new BDC command before the
ACK pulse is issued by the target, in other words, before the breakpoint address is reached
NOTE
A match detected in the Breakpoint unit does not clear the DVF bit in the
BDC Status and Control register. This bit only indicates a command had
failed or is pending and is not modified by the Breakpoint unit. To evaluate
if a breakpoint match had occurred, without using the hardware handshake
protocol and the GO_UNTIL command, the host should check for the
BDMACT BDCSCR bit to verify if it is at logic one, indicating that the CPU
had entered Background Active mode.
18.4.1.1.3
BGND Instruction
The third method consists of executing a BGND instruction. This can be accomplished by placing a BGND
instruction in the normal program sequence, usually by issuing BDC foreground commands. The BGND
instruction places the CPU in background debug mode. As in the first case, normal program flow can be
resumed with a GO, TRACE1, TAGGO or GO_UNTIL command. However, in this case, execution starts
with the instruction following BGND in the program sequence, provided the PC is not altered while in
background debug mode and no higher priority events are pending.
Note that if the ENBDM bit is not set to logic one, the BGND instruction is treated as an illegal opcode.
Also note that if the BGND instruction comes from secure memory, then the instruction is treated as an
illegal opcode. This is to prevent attempts to break security by using background debug mode as follows:
1. Enter background debug Mode by issuing a BACKGROUND command.
2. Set the PC to an address in secure memory.
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3. Issue a GO command.
If the data pointed by the PC is the opcode of a BGND instruction, then it will be executed as a secure
opcode, defeating the security mechanism. To prevent this from happening, a BGND instruction from
secure memory is treated as an illegal opcode.
If the hardware handshake protocol is enabled, an ACK pulse is issued by the target as soon as the target
CPU enters background mode after executing the BGND instruction, provide the GO_UNTIL command
had been used to put the CPU in normal mode. The hardware handshake abort procedure should be used
if the host decides to send a new BDC command before the ACK pulse is issued by the target.
18.4.1.1.4
External Force and Tag
The fourth and fifth methods of entering background debug mode is through the MCU’s external force/tag
capabilities. This method behaves essentially in the same way as the internal force/tagging capabilities.
The main difference is that a force/tag may be issued when background debug mode is not enabled. In such
a case, the CPU executes the SWI instruction instead of the BGND instruction and sets core_illegal_op_t4
status signal. In addition, the CPU sets core_force_exec_t4 or core_tag_exec_t4 to indicate whether a force
or tag led to this condition. At the chip level these signals can be used to reset the core or used to detect
that an external force or tag was responsible for the SWI flow.
If the hardware handshake protocol is enabled, an ACK pulse is issued by the target as soon as the target
CPU enters background mode, provide the GO_UNTIL command had been used to put the CPU in normal
mode. The hardware handshake abort procedure should be used, if the host decides to send a new BDC
command before the ACK pulse is issued.
18.4.1.2 BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communication protocol. BDC commands
are divided in two classes: foreground commands and background commands. Foreground commands can
be executed while the CPU is running application code. Background commands can be executed only if
the core is in background debug mode. Figure 18-21 and Figure 18-22 describe the foreground and
background commands. Table 18-20 explains the symbols used for the command structure. Subsequent
paragraphs will describe each command in greater detail.
Table 18-20. BDC Commands Legend
Symbol
Description
Separates parts of a BDM command
/
OP
d
8-bit opcode (host-to-target)
Delay 16 clock cycles (based on the reference clock for serial communication)
16-bit address (host-to-target)
AAAA
SS
8 bits of read data from the BDC status and control register (target-to-host)
8 bits of write data to the BDC status and control register (host-to-target)
8 bits of read data (target-to-host)
CC
RB
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Table 18-20. BDC Commands Legend
Description
Symbol
/
Separates parts of a BDM command
WB
8 bits of write data (host-to-target)
RBKP
WBKP
RHWD
WHWD
16 bits of read data from the BDC breakpoint register (target-to-host)
16 bits of write data to the BDC breakpoint register (host-to-target)
16 bits of read data (target-to-host)
16 bits of write data (host-to-target)
Table 18-21. BDC Foreground Commands
Command
Structure
Opcode
(Hex)
Command
Description
Request timed reference pulse
1
None2
SYNC
None
D5
Enable Handshake. Issues an ACK pulse after the command is
executed.
ACK_ENABLE
OP/d
OP/d
Disable Handshake. This command does not issues an ACK
pulse.
ACK_DISABLE
BACKGROUND
D6
90
Enter Background Debug Mode if enabled. Issues an ACK pulse
after the CPU had entered into BDM, if the hardware handshake
protocol was enabled. If ENBDM = 0 the command is ignored and
the ACK pulse is not issued.
OP/d
READ_STATUS
E4
C4
OP/SS
OP/CC
Read the BDC status and control register (BDCSCR)
Write to the BDCSCR register
WRITE_CONTROL
Retrieves the BDCSCR and data from the last READ_BYTE.
Retrieves ACC or CCR if last command was READ_A or
READ_CCR and an extra byte that is not valid data. If the last
command was READ_HX, READ_SP or READ_PC only the
CPU register data is retrieved.
OP/SS/RB or
OP/RHWD
READ_LAST
E8
Read from memory. Issues an ACK pulse when the data is ready
to be retrieved, if the hardware handshake protocol was enabled.
READ_BYTE
WRITE_BYTE
E0
C0
OP/AAAA/d/RB
OP/AAAA/WB/d
Write to memory. Issues an ACK when the data is written to the
addressed memory location, if the hardware handshake protocol
was enabled.
OP/AAAA/d/SS/R
B
READ_BWS
WRITE_BWS
E1
C1
Read from memory with BDC status
Write to memory with BDC status
OP/AAAA/WB/d/S
S
READ_BKPT
WRITE_BKPT
E2
C2
OP/RBKP
OP/WBKP
Read breakpoint address
Write breakpoint address
1Commands begin with an 8-bit hexadecimal code in the host-to-target direction (MSB first).
2The SYNC command is a special operation which does not have a command code.
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Table 18-22. BDC Background Commands
Command
Opcode
(Hex)
Command
Description
Structure
Resume normal program flow. If in background mode issues an ACK
pulse after the CPU exits BDM, if the hardware handshake protocol is
enabled.
GO
08
OP/d
Resume normal program flow. If in background mode, issues an ACK
pulse after the CPU enters back to BDM, if the hardware handshake
protocol is enabled.
GO_UNTIL
TRACE1
0C
OP/d
OP/d
Execute one instruction in the normal program sequence then return to
Background Debug Mode. If in background mode, issues an ACK
pulse when the CPU enters back into BDM, after the user instruction is
executed, if the hardware handshake protocol is enabled.
10
Same as GO, except that this command will not issue an ACK pulse as
a response.
TAGGO
18
69
OP/d
Read condition code register (CCR). If in background mode, issues an
ACK pulse when the CCR data is ready to be retrieved if the hardware
handshake protocol was enabled.
READ_CCR
OP/d/RB
Write condition code register (CCR). If in background mode, issues an
ACK pulse after the CCR register is updated, provided the hardware
handshake protocol is enabled.
WRITE_CCR
READ_A
49
68
48
6C
4C
6F
4F
6B
4B
OP/WB/d
Read Accumulator (A). If in background mode, issues an ACK pulse
when the ACC data is ready to be retrieved, provided the hardware
handshake protocol is enabled.
OP/d/RB
Write Accumulator (A). If in background mode, issues an ACK pulse
when the ACC register is updated, provided the hardware handshake
protocol is enabled.
WRITE_A
READ_HX
WRITE_HX
READ_SP
WRITE_SP
READ_PC
WRITE_PC
OP/WB/d
Read H:X index register. If in background mode, issues an ACK pulse
when the HX data is ready to be retrieved, provided the hardware
handshake protocol is enabled.
OP/d/RHWD
OP/WHWD/d
OP/d/RHWD
Write H:X index register. If in background mode, issues an ACK pulse
when the HX register is updated, provided the hardware handshake
protocol is enabled.
Read stack pointer (SP). If in background mode, issues an ACK pulse
when the SP data is ready to be retrieved, provided the hardware
handshake protocol is enabled.
Write stack pointer (SP). If in background mode, issues an ACK pulse
OP/WHWD/d when the SP register is updated, provided the hardware handshake
protocol is enabled.
Read program counter (PC). If in background mode, issues an ACK
pulse when the PC data is ready to be retrieved, provided the hardware
handshake protocol is enabled.
OP/d/RHWD
OP/WHWD/d
Write program counter (PC). If in background mode, issues an ACK
pulse when the PC register is updated, provided the hardware
handshake protocol is enabled.
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Table 18-22. BDC Background Commands (continued)
Opcode
(Hex)
Command
Structure
Command
Description
Increment H:X by 1 and read from memory at H:X. If in background
mode, issues an ACK pulse when the Memory data is ready to be
retrieved, provided the hardware handshake protocol is enabled.
READ_NEXT
70
OP/d/RB
OP/WB/d
Increment H:X by 1 and write to memory at H:X. If in background
mode, issues an ACK pulse when the Memory location is updated,
provided the hardware handshake protocol is enabled.
WRITE_NEXT
50
READ_NWS
WRITE_NWS
71
51
OP/d/SS/RB
OP/WB/d/SS
Increment H:X by 1 and read from memory at H:X with BDC status
Increment H:X by 1 and write to memory at H:X with BDC status
The serial communication could be set in two different rates: the ext_clk24, which is double the CPU bus
frequency and ext_lclk, which is the independent Local Oscillator frequency source. These modes are
defined by the CLKSW bit in the BDC Status and Control register. If CLKSW = 0 the Local Oscillator is
engaged and the serial communication rate is defined by the Local Oscillator frequency. In this mode the
serial communication rate is asynchronous related to the MCU bus clock. If CLKSW = 1, the Local
Oscillator is disengaged, causing the ext_lclk to be derived from the ext_clk24 MCU clock signal. In this
case the serial communication clock is synchronous related to the MCU bus clock.
18.4.1.2.1
Serial Communication Time-out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD to answer the SYNC
request pulse. If the rising edge is not detected, the target will keep waiting forever, without any time-out
limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieving after the time-out
had occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider
the behavior where the BDC is running in a frequency much greater than the CPU frequency. In this case,
the command could time-out before the data is ready to be retrieved. To allow the data to be retrieved even
with a large clock frequency mismatch, between BDC and CPU, when the hardware handshake protocol
is enabled the time-out between a read command and the data retrieve is disabled. Therefore, the host could
wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read
command. However, after the handshake pulse is issued, the time-out feature is re-activated, meaning that
the target will time-out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512
serial clock cycles time frame after the ACK pulse had been issued. After that period the read command
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is discarded and the data is no longer available for retrieve. Any negedge in the BKGD pin after the
time-out period is considered to be a new command or a SYNC request.
Note that, whenever a partially issued command, or partially retrieved data had occurred, the time-out in
the serial communication is active, meaning that, if a time frame higher than 512 serial clock cycles is
observed between two consecutive negedges and the command being issued or data being retrieved is not
completed, a soft-reset will occur causing the partially received command or data retrieve to be
disregarded. The next negedge in the BKGD pin, after the soft-reset had occurred, is considered by the
target as the start of a new BDC command, or the start of a SYNC request pulse.
18.4.2 DBG Functional Description
This section provides a complete functional description of the on-chip ICE system. The DBG module is
enabled by setting the DBGEN bit in the DBGC register. Enabling the module allows the arming,
triggering and storing of data in the FIFO. The DBG module is made up of three main blocks, the
Comparators, Trigger Break Control logic and the FIFO.
18.4.2.1 Comparator
The DBG module contains three comparators, A, B, and C. Comparator A compares the core address bus
with the address stored in the DBGCAX, DBGCAH, and DBGCAL registers. Comparator B compares the
core address bus with the address stored in the DBGCBX, DBGCBH, and DBGCBL registers except in
full mode, where it compares the data buses to the data stored in the DBGCBL register. Comparator C
compares the core address bus with the address stored in the DBGCCX, DBGCCH, and DBGCCL
registers. Matches on Comparators A, B, and C are signaled to the Trigger Break Control (TBC) block.
18.4.2.1.1
RWA and RWAEN in Full Modes
In full modes ("A And B" and "A And Not B") RWAEN and RWA are used to select read or write
comparisons for both comparators A and B. To select write comparisons and the write data bus in Full
Modes set RWAEN=1 and RWA=0, otherwise read comparisons and the read data bus will be selected.
The RWBEN and RWB bits are not used and will be ignored in Full Modes.
18.4.2.1.2
Comparator C in LOOP1 Capture Mode
Normally comparator C is used as a third hardware breakpoint and is not involved in the trigger logic for
the on-chip ICE system. In this mode, it compares the core address bus with the address stored in the
DBGCCX, DBGCCH, and DBGCCL registers. However, in LOOP1 capture mode, comparator C is
managed by logic in the DBG module to track the address of the most recent change-of-flow event that
was captured into the FIFO buffer. In LOOP1 capture mode, comparator C is not available for use as a
normal hardware breakpoint.
When the ARM and DBGEN bits are set to one in LOOP1 capture mode, comparator C value registers are
cleared to prevent the previous contents of these registers from interfering with the LOOP1 capture mode
operation. When a COF event is detected, the address of the event is compared to the contents of the
DBGCCX, DBGCCH, and DBGCCL registers to determine whether it is the same as the previous COF
entry in the capture FIFO. If the values match, the capture is inhibited to prevent the FIFO from filling up
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with duplicate entries. If the values do not match, the COF event is captured into the FIFO and the
DBGCCX, DBGCCH, and DBGCCL registers are updated to reflect the address of the captured COF
event. When comparator C is updated, the PAGSEL bit (bit-7 of DBGCCX) is updated with the PPACC
value that is captured into the FIFO. This bit indicates whether the COF address was a paged 17-bit
program address using the PPAGE mechanism (PPACC=1) or a 17-bit CPU address that resulted from an
unpaged CPU access.
18.4.2.2 Breakpoints
A breakpoint request to the CPU at the end of a trace run can be created if the BRKEN bit in the DBGC
register is set. The value of the BEGIN bit in DBGT register determines when the breakpoint request to
the CPU will occur. If the BEGIN bit is set, begin-trigger is selected and the breakpoint request will not
occur until the FIFO is filled with 8 words. If the BEGIN bit is cleared, end-trigger is selected and the
breakpoint request will occur immediately at the trigger cycle.
When traditional hardware breakpoints from comparators A or B are desired, set BEGIN=0 to select an
end-trace run and set the trigger mode to either 0x0 (A-only) or 0x1 (A OR B) mode.
There are two types of breakpoint requests supported by the DBG module, tag-type and force-type. Tagged
breakpoints are associated with opcode addresses and allow breaking just before a specific instruction
executes. Force breakpoints are not associated with opcode addresses and allow breaking at the next
instruction boundary. The TAG bit in the DBGC register determines whether CPU breakpoint requests will
be a tag-type or force-type breakpoints. When TAG=0, a force-type breakpoint is requested and it will take
effect at the next instruction boundary after the request. When TAG=1, a tag-type breakpoint is registered
into the instruction queue and the CPU will break if/when this tag reaches the head of the instruction queue
and the tagged instruction is about to be executed.
18.4.2.2.1
Hardware Breakpoints
Comparators A, B, and C can be used as three traditional hardware breakpoints whether the on-chip ICE
real-time capture function is required or not. To use any breakpoint or trace run capture functions set
DBGEN=1. BRKEN and TAG affect all three comparators. When BRKEN=0, no CPU breakpoints are
enabled. When BRKEN=1, CPU breakpoints are enabled and the TAG bit determines whether the
breakpoints will be tag-type or force-type breakpoints. To use comparators A and B as hardware
breakpoints, set DBGT=0x81 for tag-type breakpoints and 0x01 for force-type breakpoints. This sets up
an end-type trace with trigger mode “A OR B”.
Comparator C is not involved in the trigger logic for the on-chip ICE system.
18.4.2.3 Trigger Selection
The TRGSEL bit in the DBGT register is used to determine the triggering condition of the on-chip ICE
system. TRGSEL applies to both trigger A and B except in the event only trigger modes. By setting the
TRGSEL bit, the comparators will qualify a match with the output of opcode tracking logic. The opcode
tracking logic is internal to each comparator and determines whether the CPU executed the opcode at the
compare address. With the TRGSEL bit cleared a comparator match is all that is necessary for a trigger
condition to be met.
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NOTE
If the TRGSEL is set, the address stored in the comparator match address
registers must be an opcode address for the trigger to occur.
18.4.2.4 Trigger Break Control (TBC)
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored
in the FIFO based on the trigger mode and the match signals from the comparator. The TBC also
determines whether a request to break the CPU should occur.
The TAG bit in DBGC controls whether CPU breakpoints are treated as tag-type or force-type breakpoints.
The TRGSEL bit in DBGT controls whether a comparator A or B match is further qualified by opcode
tracking logic. Each comparator has a separate circuit to track opcodes because the comparators could
correspond to separate instructions that could be propagating through the instruction queue at the same
time.
In end-type trace runs (BEGIN=0), when the comparator registers match, including the optional R/W
match, this signal goes to the CPU break logic where BRKEN determines whether a CPU break is
requested and the TAG control bit determines whether the CPU break will be a tag-type or force-type
breakpoint. When TRGSEL is set, the R/W qualified comparator match signal also passes through the
opcode tracking logic. If/when it propagates through this logic, it will cause a trigger to the ICE logic to
begin or end capturing information into the FIFO. In the case of an end-type (BEGIN=0) trace run, the
qualified comparator signal stops the FIFO from capturing any more information.
If a CPU breakpoint is also enabled, TAG and TRGSEL to agree so that the CPU break occurs at the same
place in the application program as the FIFO stopped capturing information. If TRGSEL was 0 and TAG
was 1 in an end-type trace run, the FIFO would stop capturing as soon as the comparator address matched,
but the CPU would continue running until a TAG signal could propagate through the CPUs instruction
queue which could take a long time in the case where changes of flow caused the instruction queue to be
flushed. If TRGSEL was one and TAG was zero in an end-type trace run, the CPU would break before the
comparator match signal could propagate through the opcode tracking logic to end the trace run.
In begin-type trace runs (BEGIN=1), the start of FIFO capturing is triggered by the qualified comparator
signals, and the CPU breakpoint (if enabled by BRKEN=1) is triggered when the FIFO becomes full.
Because this FIFO full condition does not correspond to the execution of a tagged instruction, it would not
make sense to use TAG=1 for a begin-type trace run.
18.4.2.4.1
Begin- and End-Trigger
The definition of begin- and end-trigger as used in the DBG module are as follows:
•
•
Begin-trigger: Storage in FIFO occurs after the trigger and continues until 8 locations are filled.
End-trigger: Storage in FIFO occurs until the trigger with the least recent data falling out of the
FIFO if more than 8 words are collected.
18.4.2.4.2
Arming the DBG Module
Arming occurs by enabling the DBG module by setting the DBGEN bit and by setting the ARM bit in the
DBGC register. The ARM bit in the DBGC register and the ARMF bit in the DBGS register are cleared
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when the trigger condition is met in end-trigger mode or when the FIFO is filled in begin-trigger mode. In
the case of an end-trace where DBGEN=1 and BEGIN=0, ARM and ARMF are cleared by any reset to
end the trace run that was in progress. The ARMF bit is also cleared if ARM is written to zero or when the
DBGEN bit is low. The TBC logic determines whether a trigger condition has been met based on the
trigger mode and the trigger selection.
18.4.2.4.3
Trigger Modes
The on-chip ICE system supports nine trigger modes. The trigger modes are encoded as shown in
Table 18-16. The trigger mode is used as a qualifier for either starting or ending the storing of data in the
FIFO. When the match condition is met, the appropriate flag AF or BF is set in DBGS register. Arming
the DBG module clears the AF, BF, and CF flags in the DBGS register. In all trigger modes except for the
event only modes change of flow addresses are stored in the FIFO. In the event only modes only the value
on the data bus at the trigger event B comparator match address will be stored.
A Only
In the A Only trigger mode, if the match condition for A is met, the AF flag in the DBGS register is set.
A Or B
In the A Or B trigger mode, if the match condition for A or B is met, the corresponding flag(s) in the DBGS
register are set.
A Then B
In the A Then B trigger mode, the match condition for A must be met before the match condition for B is
compared. When the match condition for A or B is met, the corresponding flag in the DBGS register is set.
Event Only B
In the Event Only B trigger mode, if the match condition for B is met, the BF flag in the DBGS register is
set. The Event Only B trigger mode is considered a begin-trigger type and the BEGIN bit in the DBGT
register is ignored.
A Then Event Only B
In the A Then Event Only B trigger mode, the match condition for A must be met before the match
condition for B is compared. When the match condition for A or B is met, the corresponding flag in the
DBGS register is set. The A Then Event Only B trigger mode is considered a begin-trigger type and the
BEGIN bit in the DBGT register is ignored.
A And B (Full Mode)
In the A And B trigger mode, Comparator A compares to the address bus and Comparator B compares to
the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle,
both the AF and BF flags in the DBGS register are set. If a match condition on only A or only B happens,
no flags are set.
For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be
used to determine whether the Breakpoint conditions are met and Comparator B matches will be ignored.
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A And Not B (Full Mode)
In the A And Not B trigger mode, comparator A compares to the address bus and comparator B compares
to the data bus. In the A And Not B trigger mode, if the match condition for A and Not B happen on the
same bus cycle, both the AF and BF flags in the DBGS register are set. If a match condition on only A or
only Not B occur no flags are set.
For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be
used to determine whether the Breakpoint conditions are met and Comparator B matches will be ignored.
Inside Range, A address B
In the Inside Range trigger mode, if the match condition for A and B happen on the same bus cycle, both
the AF and BF flags in the DBGS register are set. If a match condition on only A or only B occur no flags
are set.
Outside Range, address < A or address > B
In the Outside Range trigger mode, if the match condition for A or B is met, the corresponding flag in the
DBGS register is set.
The four control bits BEGIN and TRGSEL in DBGT, and BRKEN and TAG in DBGC, determine the basic
type of debug run as shown in Table 18-23. Some of the 16 possible combinations are not used (refer to
the notes at the end of the table).
.
Table 18-23. Basic Types of Debug Runs
BEGIN TRGSEL BRKEN
TAG
Type of Debug Run
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
x(1)
0
Fill FIFO until trigger address (No CPU breakpoint - keep running)
Fill FIFO until trigger address, then force CPU breakpoint
Do not use(2)
1
x(1)
0
Fill FIFO until trigger opcode about to execute (No CPU breakpoint - keep running)
Do not use(3)
1
Fill FIFO until trigger opcode about to execute (trigger causes CPU breakpoint)
Start FIFO at trigger address (No CPU breakpoint - keep running)
Start FIFO at trigger address, force CPU breakpoint when FIFO full
Do not use(4)
x(1)
0
1
x(1)
0
Start FIFO at trigger opcode (No CPU breakpoint - keep running)
Start FIFO at trigger opcode, force CPU breakpoint when FIFO full
Do not use(4)
1
1 When BRKEN = 0, TAG is do not care (x in the table).
2 In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In
this case, where TRGSEL = 0 to select no opcode tracking qualification and TAG = 1 to specify a tag-type CPU breakpoint,
the CPU breakpoint would not take effect until sometime after the FIFO stopped storing values. Depending on program loops
or interrupts, the delay could be very long.
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3 In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In
this case, where TRGSEL = 1 to select opcode tracking qualification and TAG = 0 to specify a force-type CPU breakpoint, the
CPU breakpoint would erroneously take effect before the FIFO stopped storing values and the debug run would not complete
normally.
4 In begin trace configurations (BEGIN = 1) where a CPU breakpoint is enabled (BRKEN = 1), TAG should not be set to 1. In
begin trace debug runs, the CPU breakpoint corresponds to the FIFO full condition which does not correspond to a taggable
instruction fetch.
18.4.2.5 FIFO
The FIFO is an eight word deep FIFO. In all trigger modes except for event only, the data stored in the
FIFO will be change of flow addresses. In the event only trigger modes only the data bus value
corresponding to the event is stored. In event only trigger modes, the high byte of the valid data from the
FIFO will always read a 0x00 and the extended information byte in DBGFX will always read 0x00.
18.4.2.5.1
Storing Data in FIFO
In all trigger modes except for the event only modes, the address stored in the FIFO will be determined by
the change of flow indicators from the core. The signal core_cof[1] indicates the current core address is
the destination address of an indirect JSR or JMP instruction, or a RTS, RTC, or RTI instruction or interrupt
vector and the destination address should be stored. The signal core_cof[0] indicates that a conditional
branch was taken and that the source address of the conditional branch should be stored.
18.4.2.5.2
Storing with Begin-Trigger
Storing with Begin-Trigger can be used in all trigger modes. After the DBG module is enabled and armed
in the begin-trigger mode, data is not stored in the FIFO until the trigger condition is met. After the trigger
condition is met the DBG module will remain armed until 8 words are stored in the FIFO. If the
core_cof[1] signal becomes asserted, the current address is stored in the FIFO. If the core_cof[0] signal
becomes asserted, the address registered during the previous last cycle is decremented by two and stored
in the FIFO.
18.4.2.5.3
Storing with End-Trigger
Storing with End-Trigger cannot be used in event-only trigger modes. After the DBG module is enabled
and armed in the end-trigger mode, data is stored in the FIFO until the trigger condition is met. If the
core_cof[1] signal becomes asserted, the current address is stored in the FIFO. If the core_cof[0] signal
becomes asserted, the address registered during the previous last cycle is decremented by two and stored
in the FIFO. When the trigger condition is met, the ARM and ARMF will be cleared and no more data will
be stored. In non-event only end-trigger modes, if the trigger is at a change of flow address the trigger event
will be stored in the FIFO.
18.4.2.5.4
Reading Data from FIFO
The data stored in the FIFO can be read using BDM commands provided the DBG module is enabled and
not armed (DBGEN=1 and ARM=0). The FIFO data is read out first-in-first-out. By reading the CNT bits
in the DBGCNT register at the end of a trace run, the number of valid words can be determined. The FIFO
data is read by optionally reading the DBGFX and DBGFH registers followed by the DBGFL register.
Each time the DBGFL register is read the FIFO is shifted to allow reading of the next word however the
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count does not decrement. In event-only trigger modes where the FIFO will contain only the data bus
values stored, to read the FIFO only DBGFL needs to be accessed.
The FIFO is normally only read while ARM and ARMF=0, however reading the FIFO while the DBG
module is armed will return the data value in the oldest location of the FIFO and the TBC will not allow
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Appendix A
IEEE 802.15.4 PHY Messaging Overview
A.1
Introduction
To better understand the full capabilities of the MC13234/MC13237 Sequence Manager, it is necessary to
have a basic understanding of the IEEE 802.15.4 PHY messaging protocol. This appendix is meant as a
simple overview and is not intended to provide an in-depth understanding of the subject. For more
information, the reader is directed to the IEEE 802.15.4 Standard, “Part 15.4: Wireless Medium Access
Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks
(WPANs)”, IEEE Std 802.15.4™-2006
A.2
Basic PHY Functions
At the 802.15.4 PHY level, all activities for any wireless node can be built from three basic functions:
•
Clear Channel Assessment (CCA) / ED scan - this function involves enabling the radio receiver
and scanning the selected 802.15.4 channel frequency for any energy present. The algorithm for
detecting the energy can vary and the detected energy can be compared to a pre-determined level,
but this activity is passive to the network.
•
•
Packet Transmit - this function causes the radio transmitter to power-up and sent a packet formatted
as described in Section 6.4.2, “MAC Frame Structures”.
Packet Receive - this function causes the radio receiver to power-up and receive a packet that has
been transmitted by another wireless node.
All the higher level protocol detailed here are built from these components.
A.3
Non-beacon-Enabled versus Beacon-Enabled Communication
Without getting into the details of network architectures, communication at the over-the-air PHY level can
be divided into non-beacon-enabled vs. beacon-enabled modes.
A.3.1
Non-beacon-Enabled Communication
Non-beacon-enabled devices use a simple model for communication between devices (typically a
coordinator and another network device):
•
Only three of the MAC frame types are used - includes data frame, acknowledgement (ACK)
frame, and MAC command frame. Beacon frames are not used.
•
To send information, a data frame is sent from a source to a destination, and an ACK may be
optionally used. The ACK frame uses a special short format, and if required, must be sent within
a specified time limit. The ACK is typically used but always not required.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
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IEEE 802.15.4 PHY Messaging Overview
•
•
There are no device-to-device timing or synchronization mechanisms.
A standard packet exchange uses a single CCA cycle (assuming no interference) followed by the
packet transmission. An ACK follows if appropriate.
•
•
All access uses unslotted CSMA-CA access - that means that if a device during a CCA cycle finds
the channel busy, its back off period is random and independent of all other devices.
A simple, point-to-point unencumbered communication model
A.3.2
Beacon-Enabled Communication
For lower latency and more deterministic communication especially with a larger number of nodes, a more
sophisticated model is beacon-enabled communication. The protocol is built around the concept of
synchronized timing between devices to determine when communication between the coordinator and its
network devices is allowed.
Beacon-enabled communication is based on the use of a “Superframe” structure. Figure A-1 shows the
most simple superframe structure. The coordinator sends out beacon frames out to the network devices on
a periodic basis. In this simple model, the entire time between beacons is available for communication.
The time available for communication is called the Contention Access Period (CAP) and is always divided
into 16 equal time slots.
Frame
Frame
Beacon
Beacon
Contention Access Period
Time
11 12 13 14 15
10
0
1
2
3
4
5
6
7
8
9
Figure A-1. Simple Superframe Structure
Devices wishing to access the coordinator use a slotted CSMA-CA channel access mechanism:
•
•
All channel access is relative to the start of the beacon transmission.
The back off slots of all devices within the PAN are aligned to the PAN coordinator and all back
off slot lengths are standard at 20 symbols in length.
•
•
Slotted access means that two CCA cycles are used for transmit - two CCA cycles (separated by a
back off slot time) must both find an idle channel before the transmit can commence.
Each time a device wishes to transmit - it locates the boundary of the next back off slot and then
waits for a random number of back off slots. If the channel is busy, following this random back off,
the device waits for another random number of back off slots before trying to access the channel
again. If the channel is idle, the device begins transmitting on the next available back off slot
boundary.
•
All transactions must be completed by the time of the next network beacon.
The superframe structure can be extended to additional capabilities. Figure A-2 illustrations “A” and “B”
show these functions.
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
IEEE 802.15.4 PHY Messaging Overview
Frame
Beacon
Frame
Beacon
Inactive Period
A)
Active Period
Time
Active Period
Contention Free Period
Contention Access Period
B)
11 12 13 14 15
10
0
1
2
3
4
5
6
7
8
9
Figure A-2. Extended Superframe Format
•
•
Optional Inactive Period (Figure A-2A) - the superframe time between beacons can be divided into
an Active Period immediately following the beacon and a sequential Inactive Period. The inactive
period allows the coordinator as well as the network devices to enter a low power mode which has
the advantage allowing for better coordinator battery life if it cannot be mains powered.
Adding a Contention Free Period (CFP) within the active period through use of guaranteed time
slots (GTSs) (Figure A-2B) - For applications requiring low-latency communication or higher data
bandwidth, the coordinator may dedicate a number of active period time slots to GTSs.
— The active period is always divided into 16 time slots
— Up to 7 of the last time slots can be dedicated to GTS(s) and these form the CFP.
— The CFP always follows the CAP.
— One GTS may occupy more than one time slot
— All CAP transactions must be completed before the CFP begins
— One device is assigned per GTS
– No CCA cycle is used by the GTS assigned device
– The device must be sure its transaction completes before the end of its GTS period.
A.4
Summary
The various timing parameters associated with beacon-enabled communication are beyond the scope of
this description. The information here is presented as background for understanding the transceiver
hardware, specifically the Sequence Manager.
MC13234/MC13237 Reference Manual, Rev. 1.8
Freescale Semiconductor
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IEEE 802.15.4 PHY Messaging Overview
MC13234/MC13237 Reference Manual, Rev. 1.8
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Freescale Semiconductor
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