MC13770FCR2 [NXP]
IC,DOWNCONVERTER,BICMOS,LLCC,12PIN,PLASTIC;
| 型号： | MC13770FCR2 |
| 厂家： | 
NXP |
| 描述： | IC,DOWNCONVERTER,BICMOS,LLCC,12PIN,PLASTIC 信息通信管理 |
| 文件： | 总8页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC13770/D
Rev. 2, 11/2003
Freescale Semiconductor
Technical Data
MC13770
(Scale 2:1)
Package Information
Plastic Package
Case 1345
MC13770
Single Band LNA and Mixer FEIC
(QFN-12)
Ordering Information
Device
Device Marking
Package
MC13770FC
770
QFN-12
Contents
1 Introduction
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Electrical Specifications . . . . . . . . . . . . . . . . 2
3 Contact Description . . . . . . . . . . . . . . . . . . . . 4
4 Applications Information. . . . . . . . . . . . . . . . 4
5 Packaging Information. . . . . . . . . . . . . . . . . . 7
The MC13770 is a single band front-end IC designed for
wireless receiver applications. It contains a low noise
LNA and a high linearity mixer. The LNA is integrated
with a bypass switch to preserve input intercept
performance. The device is fabricated using Freescale's
Advanced RF BiCMOS process using the SiGe:C option
and is packaged in a 12 pin Quad Flat Non-leaded
package.
1.1
Features
•
RF Input Frequency: 2100 to 2400 MHz
•
•
LNA Gain = 15 dB (Typ)
LNA Input 3rd Order Intercept Point (IIP3) =
0 dBm (Typ)
•
•
LNA Noise Figure (NF) = 1.5 dB (Typ)
Bypass Mode Included for Improved Intercept
Point Performance
•
•
•
Double Balanced Mixer
Mixer Conversion Gain = 10 dB (Typ)
Mixer Noise Figure (NF) = 8.0 dB (Typ)
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2003, 2005. All rights reserved.
Electrical Specifications
•
•
Mixer Input 3rd Order Intercept Point (IIP3) = -3.0 dBm (Typ)
Total Supply Current = 8.0 mA
LNA = 3.0 mA
Mixer = 5.0 mA
LNA Out
Mix In
LO In+ LO In-
IF+
IF-
LNA In
Bypass
Enable
Mix Bias
Figure 1. Simplified Block Diagram
2 Electrical Specifications
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Supply Voltage
VCC
Tstg
TA
3.6
V
Storage Temperature Range
Operating Temperature Range
Note: Maximum Ratings and ESD
-65 to 150
-40 to 85
°C
°C
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) ≤100 V and Machine Model (MM) ≤30 V.
Additional ESD data available upon request.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Supply Voltage
2.7
2.75
3.0
Vdc
V
Logic Voltage (Enable and Bypass Pins)
Input High Voltage
0.85 VCC
0
-
-
VCC
Input Low Voltage
0.15 VCC
MC13770 Technical Data, Rev. 2
2
Freescale Semiconductor
Electrical Specifications
Table 3. Electrical Characteristics
Symbol Min
Characteristic
Typ
Max
Unit
Turn-on Time
-
100
-
ns
LNA High Gain Mode (Frequency = 2140 MHz, VCC = 2.75 V, Bypass = 2.75 V, Enable = 2.75 V)
LNA Gain
-
-
-
-
15
1.5
0
-
-
-
-
dB
dB
LNA Noise Figure
LNA Input IP3
LNA Supply Current
dBm
mA
IDD
3.0
LNA Low Gain Mode (RF = 2140 MHz, VCC = 2.75 V, Bypass = 0 V, Enable = 2.75 V)
LNA Gain
-
-
-
-
-5.0
5.0
20
-
-
-
-
dB
dB
LNA Noise Figure
LNA Input IP3
LNA Supply Current
dBm
µA
IDD
10
Mixer Mode (RF = 2140 MHz, LO = 2520 MHz, VCC = 2.75 Vdc, Enable = 2.75 V)
Conversion Gain
-
-
-
-
-
10
8.0
-3.0
5.0
-10
-
-
-
-
-
dB
dB
SSB Noise Figure
Input IP3
dBm
mA
Supply Current
LO Drive Level
dBm
Note: Tone spacing for IIP3 measurement is 5.0 MHz.
Table 4. Truth Table
(1 = 2.75 V, 0 = 0 V)
Enable
Bypass
Mode
0
0
1
1
0
Sleep
1
0
1
Undefined - do not use
Low Gain
High Gain
MC13770 Technical Data, Rev. 2
Freescale Semiconductor
3
Contact Description
3 Contact Description
Table 5. Contact Function Description
Pin
Symbol
LNA Out
Description
1
2
LNA Output
Bypass
Mix In
Enable
LO+
LNA Bypass Control
Mixer Input
3
4
Chip Enable
5
Local Oscillator Input +
Local Oscillator Input -
Differential IF Output +
Differential IF Output -
Supply
6
LO-
7
IF+
8
IF-
9
VCC
10
11
12
LNA In
Gnd
LNA Input
Ground
Mix Bias
Mixer Bias Adjustment
4 Applications Information
Figure 2 shows the typical application circuit for 2110 to 2140 MHz band. The Mixer input is internally
broadband matched. Two typical IF output match circuits are provided in Table 6 on page 5.
MC13770 Technical Data, Rev. 2
4
Freescale Semiconductor
Applications Information
VCC1
C1 33 pF
LNA In
C12
0.5 pF
L2
2.7 nH
C9
0.01 µF
R1
4.3 k
C7
33 pF
12
11
10
C2 33 pF
L3 *
C8 0.01 µF
L4 *
L1
2.7 nH
R2
470 Ω
1
2
3
9
8
7
LNA Out
VCC2
C11 1.0 pF
Mini-Circuits
TC8-1 Transformer
8:1
Bypass
Mix In
C3 *
C10 *
IF
C4 *
4
5
6
* See Table 6 for values.
C6
33 pF
C5
33 pF
Enable
LO+
Figure 2. Application Schematic
Table 6. Bill of Material for Application Schematic
Component
190 MHz IF
380 MHz IF
C3
C4
C10
L3
1.2 pF
1.2 pF
1.2 pF
150 nH
150 nH
5.0 kΩ
2.2 pF
2.2 pF
1.2 pF
39 nH
39 nH
20 kΩ
L4
R3
Note: All other components are the same for both configurations.
MC13770 Technical Data, Rev. 2
Freescale Semiconductor
5
Applications Information
L
N
A
Serial
No#
GND
I
N
1
LNAout
IF
VCC2
MIX in
ENABLE
GND
MC13770EVK
V2
LO-
LO+
Figure 3. Application PCB (Not to Scale)
MC13770 Technical Data, Rev. 2
6
Freescale Semiconductor
Packaging Information
5 Packaging Information
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
3
A
M
2X
0.1
C
G
0.1
C
1.0 1.00
0.8 0.75
0.05
C
5
3
(0.24)
0.05
0.00
(0.5)
SEATING PLANE
C
2X
DETAIL G
VIEW ROTATED 90° CLOCKWISE
M
0.1
C
B
0.1 C A B
1.25
0.95
DETAIL M
PIN 1 IDENTIFIER
M
M
0.1
C A B
C
10
12
EXPOSED DIE
ATTACH PAD
0.05
8X (1.177)
4X (45°)
12X
0.3
0.18
9
7
1
3
1.25
0.065
0.015
3X (R0.09)
4X (0.18)
0.1 C A B
12X
0.95
DETAIL N
CORNER CONFIGURATION
N
6
4
12X
0.75
0.5
4
8X
0.5
VIEW M-M
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
DETAIL S
(90°)
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER LEADS,
AND DIE ATTACH PAD.
4X
(0.25)
0.39
0.31
2X
8X
(0.777)
2X 0.1
0.0
DETAIL S
PIN 1 BACKSIDE IDENTIFIER
DETAIL M
PIN 1 BACKSIDE IDENTIFIER
Figure 4. Outline Dimensions for QFN-12
(Case 1345-01, Issue A)
MC13770 Technical Data, Rev. 2
Freescale Semiconductor
7
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MC13770/D
Rev. 2
11/2003
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