MC145503P [NXP]
A/MU-LAW, PCM CODEC, PDIP16, PLASTIC, DIP-16;
| 型号： | MC145503P |
| 厂家： | 
NXP |
| 描述： | A/MU-LAW, PCM CODEC, PDIP16, PLASTIC, DIP-16 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总28页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145500/D
The MC145500, MC145501, MC145502, MC145503, and MC145505 are all
per channel PCM Codec–Filter mono–circuits. These devices perform the voice
digitization and reconstruction as well as the band limiting and smoothing
required for PCM systems. The MC145500 and MC145503 are general
purpose devices that are offered in a 16–pin package. They are designed to
operate in both synchronous and asynchronous applications and contain an
on–chip precision reference voltage. The MC145501 is offered in an 18–pin
package and adds the capability of selecting from three peak overload voltages
(2.5, 3.15, and 3.78 V). The MC145505 is a synchronous device offered in a
16–pin DIP and wide body SOIC package intended for instrument use. The
MC145502 is the full–featured device which presents all of the options of the
chip. This device is packaged in a 22–pin DIP and a 28–pin chip carrier package
and contains all the features of the MC145500 and MC145501 plus several
more. Most of these features can be made available in a lower pin count
package tailored to a specific user’s application. Contact the factory for further
details.
L SUFFIX
CERAMIC PACKAGE
CASE 620
16
MC145500/03/05
1
P SUFFIX
PLASTIC DIP
CASE 648
16
These devices are pin–for–pin replacements for Motorola’s first generation of
MC14400/01/02/03/05 PCM mono–circuits and are upwardly compatible with
the MC14404/06/07 codecs and other industry standard codecs. They also
maintain compatibility with Motorola’s family of MC33120 and MC3419 SLIC
products.
The MC145500 family of PCM Codec–Filter mono–circuits utilizes CMOS
due to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
1
MC145503/05
L SUFFIX
CERAMIC PACKAGE
CASE 726
18
MC145501
1
MC145500 (This Device is Not Recommended for New Designs)
L SUFFIX
CERAMIC PACKAGE
CASE 736
•
•
•
16–Pin Package
22
Transmit Bandpass and Receive Low–Pass Filter On–Chip
Pin Selectable Mu–Law/A–Law Companding with Corresponding Data
Format
1
MC145502
•
•
•
On–Chip Precision Reference Voltage (3.15 V)
Power Dissipation of 50 mW, Power–Down of 0.1 mW at ± 5 V
Automatic Prescaler Accepts 128 kHz, 1.536, 1.544, 2.048, and 2.56 MHz
for Internal Sequencing
P SUFFIX
PLASTIC DIP
CASE 708
22
1
MC145501 — All of the Above Plus:
(This Device is Not Recommended for New Designs)
MC145502
•
•
•
18–Pin Package
DW SUFFIX
SOG PACKAGE
CASE 751G
Selectable Peak Overload Voltages (2.5, 3.15, 3.78 V)
Access to the Inverting Input of the TxI Input Operational Amplifier
16
1
MC145502 — All of the Above Plus:
MC145503/05
•
•
•
22–Pin and 28–Pin Packages
FN SUFFIX
PLCC PACKAGE
CASE 776
Variable Data Clock Rates (64 kHz to 4.1 MHz)
Complete Access to the Three Terminal Transmit Input Operational
Amplifiers
28
MC145502
1
•
An External Precision Reference May Be Used
MC145503 — All of the Above Features of the MC145500 Plus:
•
•
16–Pin Package
Complete Access to the Three Terminal Transmit Input Operational Amplifiers
MC145505 — Same as MC145503 Except:
•
•
16–Pin Package
Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock
REV 1
9/95 (Replaces ADI1287)
Motorola, Inc. 1995
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145500/01/02/03/05 PCM CODEC–FILTER MONO–CIRCUIT BLOCK DIAGRAM
RDD
RCE
RDC
RECEIVE SHIFT
REGISTER
1
RxO
RxG
RxO
D/A
FREQUENCY
Rx
Rx
V
SHARED
DAC
DD
–
+
400 µA
÷
1, 12, 16, 20
CCI PRESCALER
CCI
MSI
V
DD
V
V
SS
2.5 V
REF
+
–
AG
SEQUENCE
AND
V
LS
CONTROL
PDI
V
SS
V
RSI
ref
RSI
TxI
CIRCUITRY
TDD
–
+
– Tx
TRANSMIT SHIFT
REGISTER
A/D
TDE
TDC
+ Tx
FREQUENCY
FREQUENCY
NOTES:
Controlled by V
LS
Rx ≈ 100 kΩ (internal resistors)
MC145500•MC145501•MC145502•MC145503•MC145505
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
2
Freescale Semiconductor, Inc.
PIN ASSIGNMENTS
(DRAWINGS DO NOT REFLECT RELATIVE SIZE)
MC145505L, P
MC145500L
MC145503L, P
MC145501L
V
1
2
3
16
15
14
V
DD
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSI
1
2
3
4
5
6
18
17
16
15
14
13
V
DD
AG
AG
DD
AG
DD
RxO
+ Tx
RxO
RxO
TxI
RxO
+ Tx
TxI
RDD
RCE
DCLK
CCI
V
RDD
RCE
RDC
TDC
TDD
TDE
MSI
RDD
RCE
RDC
TDC
TDD
TDE
MSI
RDD
RCE
RDC
TDC
AG
RxO
TxI
– Tx
Mu/A
PDI
4
5
6
7
8
13
12
11
10
9
RxO
TxI
– Tx
Mu/A
PDI
Mu/A
PDI
– Tx
Mu/A
PDI
TDD
TDE
TDD
TDE
V
7
8
9
12
11
10
SS
V
V
V
V
V
SS
LS
SS
LS
LS
V
V
LS
SS
MC145502L, P
MC145503DW
MC145505DW
MC145502FN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
V
V
V
1
22
21
20
19
18
17
16
15
14
13
12
RSI
AG
DD
AG
DD
ref
RxO
+ Tx
TxI
RDD
RCE
RDC
TDC
TDD
TDE
RxO
+ Tx
TxI
RDD
RCE
DCLK
CCI
V
2
V
DD
AG
4
3
2
1
28 27 26
25
RxG
5
6
7
8
RCE
RDC
RxO
RxG
RxO
+ Tx
TxI
3
RDD
RCE
RDC
TDC
CCI
24
RxO
+ Tx
NC
4
23
22
21
20
TDC
NC
NC
28–PIN PQLCC
(TOP VIEW)
5
– Tx
Mu/A
PDI
– Tx
Mu/A
PDI
NC
9
6
TDD
TDE
CCI
TxI
– Tx
10
11
19
TDD
7
12 13 14 15 16 17 18
– Tx
Mu/A
PDI
8
TDD
TDE
MSI
V
V
V
V
LS
LS
SS
SS
9
10
11
NC = NO CONNECTION
V
V
LS
SS
MOTOROLA
MC145500•MC145501•MC145502•MC145503•MC145505
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to V
)
SS
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For
Rating
DC Supply Voltage
Voltage, Any Pin to V
Symbol
Value
Unit
V
V , V
DD SS
– 0.5 to 13
V
I
– 0.5 to V
DD
+ 0.5
V
SS
DC Drain Per Pin (Excluding V , V
)
10
mA
°C
°C
DD SS
proper operation it is recommended that V
in
in
Operating Temperature Range
Storage Temperature Range
T
A
– 40 to + 85
andV beconstrainedtotherangeV ≤(V
out
out
SS
or V ) ≤ V
.
T
stg
– 85 to + 150
DD
Unused inputs must always be tied to an
appropriatelogicvoltagelevel(e.g.,V ,V
,
SS DD
V , or V ).
LS AG
RECOMMENDED OPERATING CONDITIONS (T = – 40 to + 85°C)
A
Characteristic
Min
Typ
Max
Unit
DC Supply Voltage
V
Dual Supplies: V
Single Supply: V
= – V , (V
SS AG
= V = 0 V)
LS
4.75
8.5
5.0
—
6.3
DD
DD
to V
(V
is an Output, V = V
or V )
SS
SS AG LS DD
MC145500, MC145501, MC145502, MC145503, MC145505 (Using Internal
3.15 V Reference)
12.6
MC145501, MC145502 Using Internal 2.5 V Reference
MC145501, MC145502 Using Internal 3.78 V Reference
MC145502 Using External 1.5 V Reference, Referenced to V
7.0
9.5
4.75
—
—
—
12.6
12.6
12.6
AG
Power Dissipation
mW
CMOS Logic Mode (V
TTL Logic Mode (V
DD
to V
SS
= 10 V, V = V
LS DD
)
—
—
40
50
70
90
DD
= + 5 V, V
SS
= – 5 V, V = V = 0 V)
LS AG
Power Down Dissipation
—
0.1
8.0
1.0
8.5
mW
kHz
kHz
Frame Rate Transmit and Receive
7.5
Data Rate
MC145500, MC145501, MC145503
—
—
—
—
—
128
—
—
—
—
—
1536
1544
2048
2560
Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz
Data Rate for MC145502, MC145505
64
—
4096
kHz
Vp
Full Scale Analog Input and Output Level
MC145500, MC145503, MC145505
—
—
—
—
—
—
—
3.15
3.78
3.15
—
—
—
—
—
—
—
MC145501, MC145502 (V = V
)
RSI = V
DD
ref SS
RSI = V
SS
RSI = V
2.5
1.51 x V
1.26 x V
AG
DD
MC145502 Using an External Reference Voltage Applied at V Pin
ref
RSI = V
RSI = V
ref
ref
SS
RSI = V
V
ref
AG
DIGITAL LEVELS (V
SS
to V
DD
= 4.75 V to 12.6 V, T = – 40 to + 85°C)
A
Characteristic
Symbol
Min
Max
Unit
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI)
V
CMOS Mode (V = V , V
is Digital Ground)
“0”
“1”
V
—
0.7 x V
—
0.3 x V
—
LS
DD SS
IL
DD
V
V
V
IH
IL
DD
V
LS
+ 0.8 V
—
TTL Mode (V ≤ V – 4.0 V, V is Digital Ground)
DD LS
“0”
“1”
LS
V
LS
+ 2.0 V
IH
Output Current for TDD (Transmit Digital Data)
mA
CMOS Mode (V = V , V
= 0 V and is Digital Ground)
(V
LS
DD SS
= 5 V, V
= 10 V, V
= 5 V, V
= 10 V, V
= 0.4 V)
= 0.5 V)
= 4.5 V)
= 9.5 V)
I
1.0
3.0
– 1.0
– 3.0
1.6
—
—
—
—
—
—
DD
out
out
out
out
OL
(V
DD
(V
DD
I
OH
(V
DD
I
TTL Mode (V ≤ V
– 4.75 V, V = 0 V and is Digital Ground)
LS
(V
= 0.4 V)
= 2.4 V)
OL
LS
DD
OL
I
– 0.2
(V
OH
OH
MC145500•MC145501•MC145502•MC145503•MC145505
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
4
Freescale Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(V
DD
= + 5 V ± 5%, V
= – 5 V ± 5%, V = V
= 0 V, V = RSI = V
(Internal 3.15 V Reference), 0 dBm0 = 1.546 Vrms = + 6 dBm @
SS
LS AG
ref SS
600 Ω, T = – 40 to + 85°C, TDC = RDC = CC = 2.048 MHz, TDE = RCE = MSI = 8 kHz, Unless Otherwise Noted)
A
End–to–End
A/D
D/A
Characteristic
Min
—
Max
—
Min
Max
Min
Max
Unit
dB
dB
dB
dB
dB
Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V
= 5 V, V = – 5 V)
SS
– 0.30 + 0.30 – 0.30 + 0.30
A
DD
Absolute Gain Variation with Temperature 0 to + 70°C
Absolute Gain Variation with Temperature – 40 to +85°C
Absolute Gain Variation with Power Supply (V = 5 V, V
—
—
—
—
—
± 0.03
± 0.1
—
—
—
± 0.03
± 0.1
—
—
= – 5 V, 5%)
—
—
± 0.02
± 0.02
DD SS
Gain vs Level Tone (Relative to – 10 dBm0, 1.02 kHz) + 3 to – 40 dBm0 – 0.4
– 40 to – 50 dBm0 – 0.8
+ 0.4
+ 0.8
+ 1.6
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
– 50 to – 55 dBm0 – 1.6
Gain vs Level Pseudo Noise (A–Law Relative to – 10 dBm0)
dB
CCITT G.714
– 10 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
—
—
—
—
—
—
– 0.25 + 0.25 – 0.25 + 0.25
– 0.30 + 0.30 – 0.30 + 0.30
– 0.45 + 0.45 – 0.45 + 0.45
Total Distortion – 1.02 kHz Tone (C–Message)
0 to – 30 dBm0
– 40 dBm0
35
29
24
—
—
—
36
29
24
—
—
—
36
30
25
—
—
—
dBC
dB
– 45 dBm0
Total Distortion With Pseudo Noise (A–Law)
CCITT G.714
– 3 dBm0
– 6 to – 27 dBm0
27.5
35
—
—
—
—
—
28
—
—
—
—
—
28.5
36
34.2
30.0
15.0
—
—
—
—
—
35.5
33.5
28.5
13.5
– 34 dBm0 33.1
– 40 dBm0 28.2
– 55 dBm0 13.2
Idle Channel Noise (For End–End and A/D, See Note 1)
Mu–Law, C–Message Weighted
A–Law, Psophometric Weighted
—
—
15
– 69
—
—
15
– 69
—
—
9
– 78
dBrnC0
dBm0p
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 to 60 Hz
300 to 3000 Hz – 0.3
3400 Hz – 1.6
—
– 23
+ 0.3
0
– 28
– 60
—
– 23
—
0.15
dB
– 0.15 + 0.15 – 0.15 + 0.15
– 0.8
—
0
– 14
– 32
– 0.8
—
—
0
– 14
– 30
4000 Hz
≥ 4600 Hz
—
—
—
Inband Spurious (1.02 kHz @ 0 dBm0, Transmit and RxO)
—
—
—
– 43
—
– 43
dBm0
dB
300 to 3000 Hz
Out–of–Band Spurious at RxO (300 – 3400 Hz @ 0 dBm0 In)
4600 to 7600 Hz
—
—
—
– 30
– 40
– 30
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
7600 to 8400 Hz
8400 to 100,000 Hz
Idle Channel Noise Selective @ 8 kHz, Input = V , 30 Hz Bandwidth
AG
—
—
– 70
—
—
—
—
—
—
– 70
180
dBm0
µs
Absolute Delay @ 1600 Hz (TDC = 2.048 MHz, TDE = 8 kHz)
310
Group Delay Referenced to 1600 Hz (TDC = 2048 kHz,
µs
TDE = 8 kHz)
500 to 600 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
140
70
40
75
– 40
– 40
– 30
– 20
—
—
—
—
—
90
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
110
170
—
—
120
160
Crosstalk of 1020 Hz @ 0 dBm0 From A/D or D/A (Note 2)
—
—
—
—
—
—
– 75
– 41
—
—
– 80
– 41
dB
dB
Intermodulation Distortion of Two Frequencies of Amplitudes – 4 to
– 21 dBm0 from the Range 300 to 3400 Hz
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ – 50 dBm0.
MOTOROLA
MC145500•MC145501•MC145502•MC145503•MC145505
For More Information On This Product,
Go to: www.freescale.com
5
Freescale Semiconductor, Inc.
ANALOG ELECTRICAL CHARACTERISTICS (V
= – V = 5 V to 6 V ± 5%, T = – 40 to + 85°C)
SS A
DD
Characteristic
Symbol
Min
Typ
Max
Unit
µA
Input Current
AC Input Impedance to V
+Tx, –Tx (Txl for MC145500)
I
in
—
± 0.01
± 0.2
(1 kHz)
+Tx, –Tx
Txl for MC145500
Z
in
5
0.1
10
0.2
—
—
MΩ
AG
Input Capacitance
+Tx, –Tx
—
—
—
< ± 30
—
10
—
pF
mV
V
Input Offset Voltage of Txl Op Amp
Input Common Mode Voltage Range
Input Common Mode Rejection Ratio
Txl Unity Gain Bandwidth
+Tx, –Tx
+Tx, –Tx
V
V
+ 1.0
V
– 2.0
ICR
CMRR
BW
SS
DD
—
—
—
—
0
70
—
—
dB
R
R
≥ 10 kΩ
≥ 10 kΩ
1000
75
kHz
dB
L
L
p
Txl Open Loop Gain
A
VOL
—
Equivalent Input Noise (C–Message) Between +Tx and –Tx, at Txl
Output Load Capacitance for Txl Op Amp
– 20
—
—
dBrnC0
pF
100
Output Voltage Range Txl Op Amp, RxO or RxO
V
out
V
R
R
= 10 kΩ to V
= 600 Ω to V
AG
V
SS
V
SS
+ 0.8
+ 1.5
—
—
V
DD
V
DD
– 1.0
– 1.5
L
L
AG
± 5.5
—
—
mA
Output Current Txl, RxO, RxO
Output Impedance RxO, RxO*
V
+ 1.5 V ≤ V
out
≤ V – 1.5 V
DD
SS
0 to 3.4 kHz
Z
out
—
0
3
—
Ω
Output Load Capacitance for RxO and RxO*
Output dc Offset Voltage Referenced to V
—
200
pF
mV
Pin
RxO
RxO*
—
—
—
—
± 100
± 150
AG
Internal Gainsetting Resistors for RxG to RxO and RxO
62
0.5
—
100
—
225
kΩ
V
External Reference Voltage Applied to V (Referenced to V
)
V
– 1.0
ref AG
DD
V
ref
Input Current
—
20
—
µA
V
V
AG
Output Bias Voltage
—
0.53 V
0.47 V
SS
+
DD
V
Output Current
Source
Sink
I
0.4
10.0
—
—
0.8
—
mA
µA
AG
VAG
Output Leakage Current During Power Down for the Txl Op Amp, V
RxO, and RxO
,
—
—
± 30
AG
Positive Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
45
55
50
65
—
—
dBC
dBC
Negative Power Supply Rejection Ratio,
0 – 100 kHz @ 250 mV, C–Message Weighting
Transmit
Receive
50
50
55
60
—
—
* Assumes that RxG is not connected for gain modifications to RxO.
MC145500•MC145501•MC145502•MC145503•MC145505
MOTOROLA
For More Information On This Product,
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6
Freescale Semiconductor, Inc.
MODE CONTROL LOGIC (V
SS
to V = 4.75 V to 12.6 V, T = – 40 to + 85°C)
DD A
Characteristic
Voltage for TTL Mode (TTL Logic Levels Referenced to V
Min
Typ
—
Max
V – 4.0
DD
Unit
V
V
V
)
V
SS
LS
LS
Voltage for CMOS Mode (CMOS Logic Levels of V
to V
)
V
V
– 0.5
—
V
DD
V
LS
SS
DD
DD
Mu/A Select Voltage
Mu–Law Mode
Sign Magnitude Mode
A–Law Mode
V
– 0.5
– 0.5
—
—
—
V
DD
DD
AG
V
V
V
V
SS
+ 0.5
+ 0.5
AG
SS
RSI Voltage for Reference Select Input (MC145501 and MC145502)
3.78 V Mode
2.5 V Mode
3.15 V Mode
V
– 0.5
– 0.5
—
—
—
V
V
V
DD
DD
V
AG
V
+ 0.5
+ 0.5
AG
V
SS
V
SS
V
ref
Voltage for Internal or External Reference (MC145502 Only)
Internal Reference Mode
External Reference Mode
V
—
—
V
V
+ 0.5
– 1.0
SS
+ 0.5
SS
DD
V
AG
Analog Test Mode Frequency, MS = CCI (MC145500, MC145501, MC145502 Only)
See Pin Description; Test Modes
—
128
—
kHz
SWITCHING CHARACTERISTICS (V
SS
to V
DD
= 9.5 V to 12.6 V, T = – 40 to + 85°C, C = 150 pF, CMOS or TTL Mode)
A
L
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
Output Fall Time
TDD
t
t
—
—
30
30
80
80
ns
TLH
THL
Input Rise Time
Input Fall Time
TDE, TDC, RCE, RDC, DC, MSI, CCI
t
t
—
—
—
—
4
4
µs
TLH
THL
Pulse Width
TDE Low, TDC, RCE, RDC, DC, MSI, CCI
t
100
64
—
—
—
ns
w
DCLK Pulse Frequency (MC145502/05 Only)
CCI Clock Pulse Frequency (MSI = 8 kHz)
CCI is internally tied to TDC on the MC145500/01/03, therefore, the
transmit data clock must be one of these frequencies. This pin will accept
one of these discrete clock frequencies and will compensate to produce
internal sequencing.
TDC, RDC, DC
f
4096
kHz
kHz
CL
f
f
f
f
f
—
—
—
—
—
128
—
—
—
—
—
CL1
CL2
CL3
CL4
CL5
1536
1544
2048
2560
Propagation Delay Time
ns
TDE Rising to TDD Low Impedance
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
t
t
t
t
—
—
—
—
—
—
—
—
90
90
—
—
90
90
90
90
180
150
55
P1
P2
P3
P4
TDE Falling to TDD High Impedance
40
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High
180
150
180
150
TDC Falling Edge to TDE Rising Edge Setup Time
TDE Rising Edge to TDC Falling Edge Setup Time
t
20
100
20
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
pF
µA
su1
su2
su8
su3
su4
su5
su6
su7
t
t
t
t
t
t
t
TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data
RDC Falling Edge to RCE Rising Edge Setup Time
RCE Rising Edge to RDC Falling Edge Setup Time
RDD Valid to RDC Falling Edge Setup Time
—
—
20
—
—
100
60
—
—
—
—
CCI Falling Edge to MSI Rising Edge Setup Time
MSI Rising Edge to CCI Falling Edge Setup Time
RDD Hold Time from RDC Falling Edge
20
—
—
100
100
—
—
—
t
h
—
—
TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance
TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
TDD Capacitance During High Impedance (TDE Low)
TDD Input Current During High Impedance (TDE Low)
—
10
—
± 0.01
12
± 10
15
—
—
± 0.1
± 10.0
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MC145500
DEVICE DESCRIPTIONS
The MC145500 PCM Codec–Filter is intended for stan-
dard byte interleaved synchronous and asynchronous appli-
cations. The TDC pin on this device is the input to both the
TDC and CCI functions in the pin description. Consequently,
for MSI = 8 kHz, TDC can be one of five discrete frequencies.
These are 128 kHz (40 to 60% duty cycle) 1.536, 1.544,
2.048, or 2.56 MHz. (For other data clock frequencies, see
MC145502 or MC145505.) The internal reference is set for
3.15 V peak full scale, and the full scale input level at Txl and
output level at RxO is 6.3 V peak–to–peak. This is the
+ 3 dBm0 level of the PCM Codec–Filter. All other functions
are described in the pin description.
A codec–filter is a device which is used for digitizing and
reconstructing the human voice. These devices were devel-
oped primarily for the telephone network to facilitate voice
switching and transmission. Once the voice is digitized, it
may be switched by digital switching methods or transmitted
long distance (T1, microwave, satellites, etc.) without degra-
dation. The name codec is an acronym from “Coder” for the
A/D used to digitize voice, and “Decoder” for the D/A used for
reconstructing voice. A codec is a single device that does
both the A/D and D/A conversions.
To digitize intelligible voice requires a signal to distortion of
about 30 dB for a dynamic range of about 40 dB. This may be
accomplished with a linear 13–bit A/D and D/A, but will far
exceed the required signal to distortion at amplitudes greater
than 40 dB below the peak amplitude. This excess perform-
ance is at the expense of data per sample. Two methods of
data reduction are implemented by compressing the 13–bit
linear scheme to companded 8–bit schemes. These com-
panding schemes follow a segmented or “piecewise–linear”
curve formatted as sign bit, three chord bits, and four step
bits. For a given chord, all 16 of the steps have the same volt-
age weighting. As the voltage of the analog input increases,
the four step bits increment and carry to the three chord bits
which increment. With the chord bits incremented, the step
bits double their voltage weighting. This results in an effec-
tive resolution of 6–bits (sign + chord + four step bits) across
a 42 dB dynamic range (7 chords above zero, by 6 dB per
chord). There are two companding schemes used; Mu–255
Law specifically in North America, and A–Law specifically in
Europe. These companding schemes are accepted world
wide. The tables show the linear quantization levels to PCM
words for the two companding schemes.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the inband signal. The telephone line is also subject to
50/60 Hz power line coupling which must be attenuated from
the signal by a high–pass filter before the A/D converter.
The D/A process reconstructs a staircase version of the
desired inband signal which has spectral images of the in-
band signal modulated about the sample frequency and its
harmonics. These spectral images are called aliasing com-
ponents which need to be attenuated to obtain the desired
signal. The low–pass filter used to attenuate filter aliasing
components is typically called a reconstruction or smoothing
filter.
MC145501
The MC145501 PCM Codec–Filter offers the same fea-
tures and is for the same application as the MC145500, but
offers two additional pins and features. The reference select
input allows the full scale level of the device to be set at
2.5 Vp, 3.15 Vp, or 3.78 Vp. The –Tx pin allows for external
transmit gain adjust and simplifies the interface to the
MC3419 SLIC. Otherwise, it is identical to MC145500.
MC145502
The MC145502 PCM Codec–Filter is the full feature
22–pin device. It is intended for use in applications requiring
maximum flexibility. The MC145502 contains all the features
of the MC145500 and MC145501. The MC145502 is in-
tended for bit interleaved or byte interleaved applications
with data clock frequencies which are nonstandard or time
varying. One of the five standard frequencies (listed above)
is applied to the CCI input, and the data clock inputs can be
any frequency between 64 kHz and 4.096 MHz. The V pin
ref
allows for use of an external shared reference or selection of
the internal reference. The RxG pin accommodates gain ad-
justments for the inverted analog output. All three pins of the
input gain–setting operational amplifier are present, provid-
ing maximum flexibility for the analog interface.
MC145503
The MC145503 PCM Codec–Filter is intended for stan-
dard byte interleaved synchronous or asynchronous applica-
tions. TDC can be one of five discrete frequencies. These
are 128 kHz (40 to 60% duty cycle), 1.536, 1.544, 2.048, or
2.56 MHz. (For other data clock frequencies, see MC145502
or MC145505.) The internal reference is set for 3.15 V peak
full scale, and the full scale input level at Txl and output level
at RxO is 6.3 V peak–to–peak. This is the + 3 dBm0 level of
the PCM Codec–Filter. The +Tx and –Tx inputs provide max-
imum flexibility for analog interface. All other functions are
described in the pin description.
MC145505
The MC145500 series PCM Codec–Filters have the co-
dec, both presampling and reconstruction filters, a precision
voltage reference on chip, and require no external compo-
nents. There are five distinct versions of the Motorola
MC145500 Series.
The MC145505 PCM Codec–Filter is intended for byte in-
terleaved synchronous applications. The MC145505 has all
the features of the MC145503 but internally connects TDC
and RDC (see pin description) to the DC pin. One of the five
standard frequencies (listed above) should be applied to
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CCI. The data clock input (DC) can be any frequency be-
tween 64 kHz and 4.096 MHz.
the transmit shift register (sign bit first) ready to be output at
TDD. The TDE pin is the high impedance control for the
transmit digital data (TDD) output. As long as this pin is high,
the TDD output stays low impedance. This pin also enables
the output shift register for clocking out the 8–bit serial PCM
word. The logical AND of the TDE pin with the TDC pin
clocks out a new data bit at TDD. TDE should be held high
for eight consecutive TDC cycles to clock out a complete
PCM word for byte interleaved applications. The transmit
shift register feeds back on itself to allow multiple reads of
the transmit data. If the PCM word is clocked out once per
frame in a byte interleaved system, the MSI pin function is
transparent and may be connected to TDE.
PIN DESCRIPTIONS
DIGITAL
V
LS
Logic Level Select input and TTL Digital Ground
V
controls the logic levels and digital ground reference
LS
for all digital inputs and the digital output. These devices can
operate with logic levels from full supply (V to V ) or
SS
DD
with TTL logic levels using V
as digital ground. For V
to V
DD
=
LS
, all I/O is full supply (V
LS
swing) with CMOS
V
DD
switch points. For V
outputs are TTL compatible with V being the digital ground.
The pins controlled by V
RCE, RDC, RDD, PDI, and output TDD.
SS
< (V – 4 V), all inputs and
DD
The TDE pin may be cycled during a PCM word for bit in-
terleaved applications. TDE controls both the high imped-
ance state of the TDD output and the internal shift clock. TDE
< V
SS
LS
LS
are inputs MSI, CCI, TDE, TDC,
LS
must fall before TDC rises (t
) to ensure integrity of the
su8
next data bit. There must be at least two TDC falling edges
between the last TDE rising edge of one frame and the first
TDE rising edge of the next frame. MSI must be available
separate from TDE for bit interleaved applications.
MSI
Master Synchronization Input
MSI is used for determining the sample rate of the transmit
side and as a time base for selecting the internal prescale
divider for the convert clock input (CCI) pin. The MSI pin
should be tied to an 8 kHz clock which may be a frame sync
or system sync signal. MSI has no relation to transmit or
receive data timing, except for determining the internal trans-
mit strobe as described under the TDE pin description. MSI
should be derived from the transmit timing in asynchronous
applications. In many applications MSI can be tied to TDE.
(MSI is tied internally to TDE in MC145503/05.)
TDD
Transmit Digital Data Output
The output levels at this pin are controlled by the V
LS
pin. For V
connected to V , the output levels are from
LS
DD
toV .ForavoltageofV betweenV
V
–4VandV
,
SS
DD
LS
DD
SS
the output levels are TTL compatible with V being the digi-
LS
tal ground supply. The TDD pin is a three–state output
controlled by the TDE pin. The timing of this pin is controlled
by TDC and TDE. When in TTL mode, this output may be
made high–speed CMOS compatible using a pull–up resis-
tor. The data format (Mu–Law, A–Law, or sign magnitude) is
controlled by the Mu/A pin.
CCI
Convert Clock Input
CCI is designed to accept five discrete clock frequencies.
These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
2.56 MHz. The frequency at this input is compared with MSI
and prescale divided to produce the internal sequencing
clock at 128 kHz (or 16 times the sampling rate). The duty
cycle of CCI is dictated by the minimum pulse width except
for 128 kHz, which is used directly for internal sequencing
and must have a 40 to 60% duty cycle. In asynchronous
applications, CCI should be derived from transmit timing.
(CCI is tied internally to TDC in MC145500/01/03.)
RDC
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz.
This pin is often tied to the TDC pin for applications that can
use a common clock for both transmit and receive data trans-
fers. The receive shift register is controlled by the receive
clock enable (RCE) pin to clock data into the receive digital
data (RDD) pin on falling RDC edges. These three signals
can be asynchronous with all other digital pins. The RDC in-
put is internally tied to the TDC input on the MC145505 and
called DC.
TDC
Transmit Data Clock Input
RCE
TDC can be any frequency from 64 kHz to 4.096 MHz, and
is often tied to CCI if the data rate is equal to one of the five
discrete frequencies. This clock is the shift clock for the
transmit shift register and its rising edges produce succes-
sive data bits at TDD. TDE should be derived from this clock.
(TDC and RDC are tied together internally in the MC145505
and are called DC.) CCI is internally tied to TDC on the
MC145500/ 01/03. Therefore, TDC must satisfy CCI timing
requirements also.
Receive Clock Enable Input
The rising edge of RCE should identify the sign bit of a re-
ceive PCM word on RDD. The next falling edge of RDC, after
a rising RCE, loads the first bit of the PCM word into the re-
ceive register. The next seven falling edges enter the remain-
der of the PCM word. On the ninth rising edge, the receive
PCM word is transferred to the receive buffer register and the
A/D sequence is interrupted to commence the decode pro-
cess. In asynchronous applications with an 8 kHz transmit
sample rate, the receive sample rate should be between 7.5
and 8.5 kHz. Two receive PCM words may be decoded and
analog summed each transmit frame to allow on–chip con-
ferencing. The two PCM words should be clocked in as two
single PCM words, a minimum of 31.25 µs apart, with a
receive data clock of 512 kHz or faster.
TDE
Transmit Data Enable Input
TDE serves three major functions. The first TDE rising
edge following an MSI rising edge generates the internal
transmit strobe which initiates an A/D conversion. The inter-
nal transmit strobe also transfers a new PCM data word into
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RDD
dec–Filter family can provide its own analog ground supply
internally. The dc voltage of this internal supply is 6% positive
of the midway between V and V . This supply can sink
more than 8 mA but has a current source limited to 400 µA.
The output of this supply is internally connected to the analog
ground input of the part. The node where this supply and the
Receive Digital Data Input
DD
SS
RDD is the receive digital data input. The timing for this pin
is controlled by RDC and RCE. The data format is deter-
mined by the Mu/A pin.
analog ground are connected is brought out to the V
symmetric dual supply systems (± 5, ± 6, etc.), V
AG
externally tied to the system analog ground supply. When
pin. In
may be
Mu/A
Select
AG
This pin selects the companding law and the data format at
TDD and RDD.
Mu/A = V ; Mu–255 Companding D3 Data Format with
Zero Code Suppress
Mu/A = V ; Mu–255 Companding with Sign Magnitude
RxO or RxO drive low impedance loads tied to V , a pull–up
AG
will be required to boost the source current
resistor to V
capability if V
DD
DD
is not tied to the supply ground. All analog
AG
signals for the part are referenced to V , including noise;
AG
AG
therefore, decoupling capacitors (0.1 µF) should be used
Data Format
from V
to V
and V
to V .
DD
AG
SS
AG
Mu/A = V ; A–Law Companding with CCITT Data Format
Bit Inversions
SS
V
ref
Positive Voltage Reference Input (MC145502 Only)
Sign/
Magnitude
A–Law
(CCITT)
The V
ref
pin allows an external reference voltage to be
Code
Mu–Law
used for the A/D and D/A conversions. If V is tied to V
,
ref
SS
the internal reference is selected. If V > V , then the ex-
ternal mode is selected and the voltage applied to V
ref
+ Full Scale
+ Zero
– Zero
1111 1111
1000 0000
0000 0000
0111 1111
1000 0000
1111 1111
0111 1111
0000 0010
1010 1010
1101 0101
0101 0101
0010 1010
ref
AG
is
used for generating the internal converter reference voltage.
In either internal or external reference mode, the actual volt-
age used for conversion is multiplied by the ratio selected by
the RSI pin. The RSI pin circuitry is explained under its pin
description below. Both the internal and external references
are inverted within the PCM Codec–Filter for negative input
voltages such that only one reference is required.
– Full Scale
SIGN
BIT
CHORD BITS
STEP BITS
0
1
2
3
4
5
6
7
External Mode — In the external reference mode (V
>
ref
NOTE: Starting from sign magnitude, to change format:
To Mu–Law —
V
), a 2.5 V reference like the MC1403 may be connected
AG
from V to V . A single external reference may be shared
ref
AG
MSB is unchanged (sign)
by tying together a number of V pins and V
ref AG
pins from dif-
Invert remaining seven bits
If code is 0000 0000, change to 0000 0010 (for zero
code suppression)
To A–Law —
MSB is unchanged (sign)
ferent codec–filters. In special applications, the external ref-
erence voltage may be between 0.5 and 5 V. However, the
reference voltage gain selection circuitry associated with RSI
must be considered to arrive at the desired codec–filter gain.
Internal Mode — In the internal reference mode (V
=
ref
Invert odd numbered bits
Ignore zero code suppression
V
), an internal 2.5 V reference supplies the reference volt-
SS
age for the RSI circuitry. The V
pin is functionally con-
ref
for the MC145500, MC145501, MC145503,
nected to V
SS
PDI
and MC145505 pinouts.
Power Down Input
The power down input disables the bias circuitry and gates
RSI
off all clock inputs. This puts the V , Txl, RxO, RxO, and
AG
Reference Select Input (MC145501/02 Only)
TDD outputs into a high–impedance state. The power dissi-
pation is reduced to 0.1 mW when PDI is a low logic level.
The RSI input allows the selection of three different over-
load or full–scale A/D and D/A converter reference voltages
independent of the internal or external reference mode. The
RSI pin is a digital input that senses three different logic
states: V , V , and V
voltage is used directly for the converters. The internal refer-
The circuit operates normally with PDI = V
or with a logic
DD
high as defined by connection at V . TDD will not come out
LS
of high impedance for two MSI cycles after PDI goes high.
. For RSI = V , the reference
SS AG
DD
AG
DCLK
ence is 2.5 V. For RSI = V , the reference voltage is multi-
plied by the ratio of 1.26, which results in an internal
Data Clock Input
SS
In the MC145505, TDC and RDC are internally connected
to DCLK.
converter reference of 3.15 V. For RSI = V
, the reference
DD
voltage is multiplied by 1.51, which results in an internal con-
verter reference of 3.78 V. The device requires a minimum of
1.0 V of headroom between the internal converter reference
ANALOG
V
AG
Analog Ground input/Output Pin
to V
. V
has this same absolute valued minimum, also
pin. The various modes of operation are
DD SS
measured from V
AG
V
is the analog ground power supply input/output. All
summarized in Table 2. The RSI pin is functionally connected
to V for the MC145500, MC145503, and MC145505
AG
analog signals into and out of the device use this as their
ground reference. Each version of the MC145500 PCM Co-
SS
pinouts.
MC145500•MC145501•MC145502•MC145503•MC145505
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RxO, RxO
+Tx / –Tx
Receive Analog Outputs
Positive Tx Amplifier Input (MC145502/03/05 Only) /
Negative Tx Amplifier Input (MC145501/02/03/05 Only)
These two complimentary outputs are generated from the
output of the receive filter. They are equal in magnitude and
out of phase. The maximum signal output of each is equal to
the maximum peak–to–peak signal described with the refer-
The Txl pin is the input to the transmit band–pass filter. If
+Tx or –Tx is available, then there is an internal amplifier
preceding the filter whose pins are +Tx, –Tx, and TxI. These
pins allow access to the amplifier terminals to tailor the input
gain with external resistors. The resistors should be in the
range of 10 kΩ. If +Tx is not available, it is internally tied to
ence. If a 3.15 V reference is used with RSI tied to V
and a
AG
+ 3 dBm0 sine wave is decoded, the RxO output will be a
6.3 V peak–to–peak signal. RxO will also have an inverted
signal output of 6.3 V peak–to–peak. External loads may be
connected from RxO to RxO for a 6 dB push–pull signal gain
V
. If –Tx and +Tx are not available, the TxI is a unity gain
AG
high–impedance input.
or from either RxO or RxO to V . With a 3.15 V reference
AG
POWER SUPPLIES
each output will drive 600 Ω to + 9 dBm. With RSI tied to V
each output will drive 900 Ω to + 9 dBm.
,
DD
V
DD
Most Positive Power Supply
V
is typically 5 to 12 V.
DD
RxG
V
Receive Output Gain Adjust (MC145502 Only)
SS
Most Negative Power Supply
The purpose of the RxG pin is to allow external gain ad-
justment for the RxO pin. If RxG is left open, then the output
signal at RxO will be inverted and output at RxO. Thus the
push–pull gain to a load from RxO to RxO is two times the
output level at RxO. If external resistors are applied from
RxO to RxG (RI) and from RxG to RxO (RG), the gain of RxO
can be set differently from inverting unity. These resistors
should be in the range of 10 kΩ. The RxO output level is un-
changed by the resistors and the RxO gain is approximately
equal to minus RG/RI. The actual gain is determined by tak-
ing into account the internal resistors which will be in parallel
to these external resistors. The internal resistors have a
large tolerance, but they match each other very closely. This
matching tends to minimize the effects of their tolerance on
external gain configurations. The circuit for RxG and RxO is
shown in the block diagram.
V
is typically 10 to 12 V negative of V .
DD
SS
For a ± 5 V dual–supply system, the typical power supply
configuration is V = + 5 V, V = – 5 V, V = 0 V (digital
DD SS LS
ground accommodating TTL logic levels), and V
= 0 V
AG
being tied to system analog ground.
For single–supply applications, typical power supply con-
figurations include:
V
V
= 10 V to 12 V
= 0 V
generates a mid supply voltage for referencing all
DD
SS
V
AG
analog signals.
controls the logic levels. This pin should be connected
V
LS
to V
for CMOS logic levels from V
to V . This pin
DD
SS DD
should be connected to digital ground for true TTL logic
levels referenced to V
.
LS
TESTING CONSIDERATIONS (MC145500/01/02 ONLY)
An analog test mode is activated by connecting MSI and
CCI to 128 kHz. In this mode, the input of the A/D (the output
of the Tx filter) is available at the PDI pin. This input is direct
coupled to the A/D side of the codec. The A/D is a differential
design. This results in the gain of this input being effectively
attenuated by half. If monitored with a high–impedance buff-
er, the output of the Tx low–pass filter can also be measured
at the PDI pin. This test mode allows independent evaluation
of the transmit low–pass filter and A/D side of the codec. The
transmit and receive channels of these devices are tested
with the codec–filter fully functional.
Txl
Transmit Analog Input
TxI is the input to the transmit filter. It is also the output of
the transmit gain amplifiers of the MC145501/02/03/05. The
input impedance is greater than 100 kΩ to V
MC145500. The TxI input has an internal gain of 1.0, such
that a +3 dBm0 signal at TxI corresponds to the peak con-
verter reference voltage as described in the V and RSI pin
in the
AG
ref
descriptions. For 3.15 V reference, the + 3 dBm0 input
should be 6.3 V peak–to–peak.
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MC145503
V
5 V
AG
51 kΩ*
1
16
0.1 µF
V
V
DD
AG
600
Ω
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Rx
Tx
RxO
+ Tx
RDD
RCE
ENABLE
CLOCK
5 k
Ω
10 kΩ
TxI
RDC
– Tx
Mu/A
PDI
TDC
TDD
TDE
681
V
V
LS
SS
0.1 µF
– 5 V
* To define RDD when TDD is high Z.
Figure 1. Test Circuit
Table 1. Options Available by Pin Selection
RSI*
Pin Level
V
*
Peak–to–Peak Overload Voltage
(Txl, RxO)
ref
Pin Level
V
V
V
7.56 V p–p
DD
SS
V
+ V
(3.02 x V
) V p–p
5 V p–p
DD
AG
EXT
EXT
EXT
EXT
V
AG
V
SS
V
AG
V
+ V
(2 x V ) V p–p
EXT
AG
V
V
V
SS
6.3 V p–p
SS
V
+ V
(2.52 x V ) V p–p
EXT
SS
AG
* On MC145500/03/05, RSI and V
tied internally to V . On MC145501, V
SS
ref
ref
tied internally to V
.
SS
Table 2. Summary of Operation Conditions User Programmed Through Pins V , V , and V
DD AG
SS
Pin
RSI
Programmed
Peak Overload
Voltage
Logic
Level
Mu/A
V
LS
V
Mu–Law Companding Curve and D3/D4 Digital
Formats with Zero Code Suppress
3.78
2.50
3.15
CMOS
DD
Logic Levels
TTL Levels
V
AG
Mu–Law Companding Curve and Sign
Magnitude Data Format
V
Up
AG
TTL Levels
Up
V
A–Law Companding Curve and CCITT Digital
Format
SS
V
SS
MC145500•MC145501•MC145502•MC145503•MC145505
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TDE
TDC
t
t
w
f
P4
CL
t
su2
t
t
t
w
su8
su1
1
2
3
t
4
5
6
7
8
t
9
10
11
t
t
P3
P3
P2
P2
t
P1
MSB
LSB
*
TDD
PCM WORD REPEATED
* Data output during this time will vary depending on TDC rate and TDE timing.
Figure 2. Transmit Timing Diagram
t
w
RCE
t
su4
f
t
w
CL
t
su3
t
w
1
2
3
4
5
6
7
8
9
10
11
RDC
RDD
t
h
t
su5
DON’T
CARE
DON’T
CARE
MSB
LSB
Figure 3. Receive Timing Diagram
t
w
MSI
CCI
t
t
w
su7
t
t
w
su6
1
2
3
4
5
6
7
8
9
10
11
Figure 4. MSI/CCI Timing Diagram
MOTOROLA
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1.00
0.80
1.00
V
V
= + 5 V
= – 5 V
V
V
= + 5 V
= – 5 V
DD
SS
DD
SS
0.80
0.60
0.40
0.20
0
2048 kHz CLOCK
0.60
2048 kHz CLOCK
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
0.40
0.20
0
TYPICAL
PEFORMANCE
TYPICAL
PEFORMANCE
– 0.20
– 0.40
– 0.60
– 0.20
– 0.40
– 0.60
– 0.80
– 1.00
– 0.80
– 1.00
– 60
– 50
– 40
– 30
– 20
– 10
0
– 60
– 50
– 40
– 30
– 20
– 10
0
INPUT LEVEL AT 1.02 kHz
INPUT LEVEL AT 1.02 kHz
Figure 5. MC145502 Gain vs Level Mu–Law Transmit
Figure 6. MC145502 Gain vs Level Mu–Law Receive
45.0
45.0
40.0
40.0
35.0
30.0
25.0
TYPICAL
PEFORMANCE
TYPICAL
PEFORMANCE
35.0
30.0
25.0
C–MESSAGE WEIGHTED
C–MESSAGE WEIGHTED
V
V
= + 5 V
= – 5 V
V
V
= + 5 V
= – 5 V
DD
SS
DD
SS
2048 kHz CLOCK
2048 kHz CLOCK
20.0
15.0
20.0
15.0
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
10.0
10.0
– 60
– 50
– 40
– 30
– 20
– 10
0
– 60
– 50
– 40
– 30
– 20
– 10
0
INPUT LEVEL AT 1.02 kHz
INPUT LEVEL AT 1.02 kHz
Figure 7. MC145502 Quantization
Distortion Mu–Law Transmit
Figure 8. MC145502 Quantization
Distortion Mu–Law Receive
0.8
0.6
0.4
0.8
0.6
0.4
V
V
= + 5 V
= – 5 V
V
V
= + 5 V
= – 5 V
DD
SS
DD
SS
2048 kHz CLOCK
2048 kHz CLOCK
0.2
0
0.2
0
TYPICAL PEFORMANCE
TYPICAL PEFORMANCE
GUARANTEED
– 0.2
– 0.4
– 0.2
– 0.4
PERFORMANCE
GUARANTEED
PERFORMANCE
– 0.6
– 0.8
– 0.6
– 0.8
– 60
– 50
– 40
– 30
– 20
– 10
– 60
– 50
– 40
– 30
– 20
– 10
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 9. MC145502 Gain vs Level A–Law Transmit
Figure 10. MC145502 Gain vs Level A–Law Receive
MC145500•MC145501•MC145502•MC145503•MC145505
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40.0
35.0
30.0
25.0
20.0
15.0
10.0
40.0
TYPICAL
PERFORMANCE
TYPICAL
PERFORMANCE
GUARANTEED
PERFORMANCE
35.0
GUARANTEED
PERFORMANCE
30.0
PSOPHOMETRIC
WEIGHTED
25.0
20.0
15.0
10.0
PSOPHOMETRIC
WEIGHTED
V
V
= + 5 V
= – 5 V
V
V
= + 5 V
= – 5 V
2048 kHz
DD
SS
DD
SS
2048 kHz
– 60
– 50
– 40
– 30
– 20
– 10
0
– 60
– 50
– 40
– 30
– 20
– 10
0
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 11. MC145502 Quantization Distortion
A–Law Transmit
Figure 12. MC145502 Quantization Distortion
A–Law Receive
70
60
70
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
60
50
50
40
30
40
30
20
10
0
20
10
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 13. MC145502 Power Supply Rejection
Ratio Positive Transmit VAC = 250 mVrms,
C–Message Weighted
Figure 14. MC145502 Power Supply Rejection
Ratio Negative Transmit VAC = 250 mVrms,
C–Message Weighted
70
60
50
40
30
20
10
0
70
TYPICAL PERFORMANCE
TYPICAL PERFORMANCE
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 15. MC145502 Power Supply Rejection
Ratio Positive Receive VAC = 250 mVrms,
C–Message Weighted
Figure 16. MC145502 Power Supply Rejection
Ratio Negative Receive VAC = 250 mVrms,
C–Message Weighted
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0.2
0.1
2.0
0
0
– 2.0
TYPICAL
PERFORMANCE
– 4.0
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
– 0.6
– 0.7
– 0.8
– 6.0
– 8.0
GUARANTEED
PERFORMANCE
TYPICAL
PERFORMANCE
– 10.0
– 12.0
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
– 14.0
– 16.0
– 18.0
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 17. MC145502 Pass–Band
Filter Response Transmit
Figure 18. MC145502 Low–Pass Filter
Response Transmit
2.0
– 2.0
0.2
0.1
TYPICAL
PERFORMANCE
0
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
– 6.0
TYPICAL
PERFORMANCE
– 10.0
– 14.0
– 18.0
– 22.0
– 26.0
– 30.0
GUARANTEED
PERFORMANCE
GUARANTEED
PERFORMANCE
– 0.6
– 0.7
– 0.8
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
0
0.04
0.08
0.12
0.16
0.20
0.24
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 19. MC145502 High–Pass Filter
Response Transmit
Figure 20. MC145502 Pass–Band
Filter Response Receive
2.0
0
GUARANTEED
– 2.0
PERFORMANCE
– 4.0
– 6.0
– 8.0
TYPICAL
PERFORMANCE
– 10.0
– 12.0
GUARANTEED
PERFORMANCE
– 14.0
– 16.0
– 18.0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2
FREQUENCY (kHz)
Figure 21. MC145502 Low–Pass Filter Response Receive
MC145500•MC145501•MC145502•MC145503•MC145505
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2.048 MHz
18 pF
18 pF
10 MΩ
300
Ω
2.048 MHz
+ 5 V
(TDC, RDC, CCI)
V
R
OSC
IN
OSC
OUT 1 OUT 2
OSC
CC
8 kHz
(TDE, RCE, MSI)
0.1 µF
MC74HC4060
GND Q8
Q4
+ 5 V
V
CC
J
Q
J
Q
Q
1/2
MC74HC73
1/2
MC74HC73
K
Q
K
GND
R
R
+ 5 V
255
256
1
2
3
4
5
6
7
8
9
10
2.048 MHz
8 kHz
Figure 22. Simple Clock Circuit for Driving MC145500/01/02/03/05 Codec–Filters
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V
V
DD
AG
N = 1
R0
RxO
+ Tx
TxI
RDD
RCE
R0
N = 2
– 48 V
10 kΩ
N = 1
RDC
TDC
10 kΩ
– Tx
TDD
TDE
Mu/A
PDI
V
V
LS
SS
MC145503
23a. Simplified Transformer Hybrid Using MC145503
V
V
DD
AG
N = 1
R3
RxO
+ Tx
TxI
RDD
RCE
R0
R5
R6
N = 2
R4
– 48 V
R1
N = 1
RDC
TDC
R2
– Tx
TDD
TDE
Mu/A
PDI
R0 = R3 R4 (R2 + R1) R3 R4
R0 R4 (R2 + R1)
R0 R4
A
=
V
out
R3 + R0 R4 (R2 + R1)
R3 + R0 R4
V
V
LS
SS
– R1
A
=
V
MC145503
in
R2
NOTE: Hybrid Balance by R5 and R6 to equate the RxO signal gain at Txl through the
inverting and non–inverting signal paths.
23b. Universal Transformer Hybrid Using MC145503
Figure 23. Hybrid Interfaces to the MC145503 PCM Codec–Filter Mono–Circuit
MC145500•MC145501•MC145502•MC145503•MC145505
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Freescale Semiconductor, Inc.
R0 = 600
Ω
R0 = 900 Ω
+ V
ref
RSI
V
SS
V
V
DD
AG
N = 1
RxO
RxG
RDD
R5
R6
R4
R3
R0
N = 2
RCE
RDC
TDC
RxO
+ Tx
– 48
N = 1
R0
TxI
CCI
TDD
TDE
MSI
R2
R1
– Tx
NOTE: Balance by R5 and R6 to equate the Txl gains through the inverting
and non–inverting input signal paths, respectively, is given by:
Mu/A
PDI
R1
R3
R4
R1
R2
R6
R3
R5
1 –
=
1 +
–
2 × R2
R5 + R6
R4 R5 + R6
V
V
LS
SS
Tx Gain = R1/R2
Rx Gain = 1 + R3/R4
R5, R6 ≈ 10 kΩ
MC145502
Adjust Rx Gain with R3
Adjust Tx Gain with R1
24a. Universal Transformer Hybrid Using MC145502
R0 = 600
R0 = 900
T
+ V
V
ref
RSI
N = 1
V
SS
10 kΩ
AG
V
DD
N = 2
R0
R0
RxO
RxG
RDD
20 kΩ
RCE
RDC
TDC
– 48
R
N = 1
RxO
+ Tx
TxI
CCI
20 kΩ
– Tx
10 kΩ
TDD
TDE
Mu/A
PDI
MSI
V
V
LS
SS
MC145502
24b. Single–Ended Hybrid Using MC145502
Figure 24. Hybrid Interfaces to the MC145502 PCM Codec–Filter Mono–Circuit
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Freescale Semiconductor, Inc.
Figure 25. A Complete Single Party Channel Unit Using
MC3419 SLIC and MC145503 PCM Mono–Circuit
MC145500•MC145501•MC145502•MC145503•MC145505
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Freescale Semiconductor, Inc.
MC145406
MC145428
MC145426
MC34119
MC145503
MC145412
Figure 26. Digital Telephone Schematic
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Table 3. Mu–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Decision
Levels
Sign
Chord Chord Chord Step
Step Step
Step
8159
7903
4319
4063
2143
2015
1055
991
511
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031
4191
2079
1023
495
231
99
8
16
256
7
6
5
4
3
2
1
16
16
16
16
16
16
128
64
32
16
8
479
239
223
103
95
4
35
33
31
15
1
2
1
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
MC145500•MC145501•MC145502•MC145503•MC145505
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Table 4. A–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Decision
Levels
Sign
Chord Chord Chord Step
Step Step
Step
4096
3968
2176
2048
1088
1024
544
512
272
256
136
128
68
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
2112
1056
528
264
132
66
7
16
128
6
5
4
3
2
16
16
16
16
16
32
64
32
16
8
4
64
1
2
2
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by CCITT.
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PACKAGE DIMENSIONS
L SUFFIX
CERAMIC PACKAGE
CASE 620–09
(MC145500/03/05)
NOTES:
-A-
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
8
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.770
0.290
0.165
0.021
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.55
7.36
4.19
0.53
0.750
0.240
—
0.015
0.050 BSC
-T-
SEATING
PLANE
K
0.055
0.070
1.40
1.77
F
G
J
0.100 BSC
2.54 BSC
0.009
0.011
0.23
0.27
M
N
E
—
0.200
—
5.08
K
L
M
N
J 16 PL
0.300 BSC
15
0.035
7.62 BSC
15
0.39 0.88
G
D 16 PL
F
0
°
°
0
°
°
M
S
0.015
0.25 (0.010)
T
B
M
S
0.25 (0.010)
T
A
P SUFFIX
PLASTIC DIP
CASE 648–08
(MC145503/05)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
B
S
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
MC145500•MC145501•MC145502•MC145503•MC145505
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Freescale Semiconductor, Inc.
L SUFFIX
CERAMIC PACKAGE
CASE 726–04
(MC145501)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
18
1
10
–B–
9
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.910
0.295
0.200
0.021
0.070
MIN
22.35
6.10
–––
0.38
1.40
MAX
23.11
7.49
5.08
0.53
1.78
0.880
0.240
–––
0.015
0.055
L
C
N
F
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.125
0.012
0.170
0.20
3.18
0.30
4.32
–T–
SEATING
PLANE
K
0.300 BSC
7.62 BSC
M
F
G
0
15
0
15
0.020
0.040
0.51
1.02
J 18 PL
D 18 PL
M
S
0.25 (0.010)
T B
M
S
0.25 (0.010)
T
A
L SUFFIX
CERAMIC PACKAGE
CASE 736–05
(MC145502)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF LEADS
OPTIONAL AT LEAD POSITIONS 1, 11, 12, AND 22.
5. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC BODY.
22
1
12
11
OPTIONAL LEAD
CONFIGURATION
-B-
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.095
0.390
0.215
0.021
0.065
MIN
26.93
9.15
3.81
0.39
1.27
MAX
27.81
9.90
5.46
0.53
1.65
1.060
0.360
0.150
0.015
0.050
-T-
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
N
M
0.008
0.125
0.015
0.170
0.20
3.18
0.39
4.31
F
G
D 22 PL
0.25 (0.010)
J 22 PL
L
M
N
0.400 BSC
15
0.050
10.16 BSC
15
0.51 1.27
0
°
°
0
°
°
M
M
S
S
B
T
A
0.25 (0.010)
T
0.020
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MC145500•MC145501•MC145502•MC145503•MC145505
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P SUFFIX
PLASTIC DIP
CASE 708–04
(MC145502)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
22
1
12
11
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
27.56
8.64
3.94
0.36
1.27
MAX
28.32
9.14
5.08
0.56
1.78
MIN
MAX
1.115
0.360
0.200
0.022
0.070
L
1.085
0.340
0.155
0.014
0.050
A
N
C
K
2.54 BSC
0.100 BSC
1.02
0.20
2.92
1.52
0.38
3.43
0.040
0.008
0.115
0.060
0.015
0.135
10.16 BSC
15
1.02
0.400 BSC
15
0.040
0.020
H
G
F
D
J
SEATING
PLANE
M
°
°
0°
0°
0.51
DW SUFFIX
SOG PACKAGE
CASE 751G–02
(MC145503/05)
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
M
M
0.010 (0.25)
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
MC145500•MC145501•MC145502•MC145503•MC145505
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Freescale Semiconductor, Inc.
FN SUFFIX
PLCC PACKAGE
CASE 776–02
(MC145502)
M
S
S
0.007 (0.180)
T
L–M
N
B
Z
Y BRK
D
–N–
M
S
S
0.007 (0.180)
T
L–M
N
U
–M–
–L–
W
D
S
S
S
0.010 (0.250)
T
L–M
N
X
G1
V
28
1
VIEW D–D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L–M
L–M
N
M
S
S
0.007 (0.180)
T
L–M
N
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
SEATING
PLANE
G
K
–T–
VIEW S
J
M
S
S
0.007 (0.180)
T
L–M
N
F
G1
S
S
S
0.010 (0.250)
T
L–M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
–––
0.032
–––
–––
0.456
0.456
0.048
0.048
0.056
0.020
10
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
–––
0.81
–––
–––
11.58
11.58
1.21
1.21
1.42
0.50
10
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
2
2
0.410
0.040
0.430
–––
10.42
1.02
10.92
–––
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MOTOROLA
MC145500•MC145501•MC145502•MC145503•MC145505
For More Information On This Product,
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