MC14LC5003FU_技术文档

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14LC5002

MC14LC5003

MC14LC5004

QFP

72-Segment / 128-Segment

LCD Drivers

CMOS

FU SUFFIX

CASE 848B

TQFP

FB SUFFIX

CASE 873A

The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv-

ers.The MC14LC5002 is the same as MC14LC5003 except for 72 segments.

The three devices are functionally the same except for their data input pro-

tocols.The MC14LC5002/5003 use a serial interface data input protocol.The

devicesmaybeinterfacedtotheMC68HCXXproductfamiliesusingaminimal

amount of software (see example).The MC14LC5004 has a IIC interface and

has essentially the same protocol, except that the device sends an acknowl-

edge bit back to the transmitter after each eight-bit byte is received.

MC14LC5004 also has a “read mode”, whereby data sent to the device may

be retrieved via the IIC bus.

The MC14LC5002/5003/5004 drive the liquid crystal displays in a multi-

plexed-by-four conﬁguration.The devices accept data from a microprocessor

or other serial data source to drive one segment per bit. The chip does not

have a decoder, allowing for the ﬂexibility of formatting the segment data

externally.

ORDERING INFORMATION

MC14LC5002FB TQFP

MC14LC5003FU QFP

MC14LC5004FU QFP

MCC14LC5003 BARE DIE

MCC14LC5004 BARE DIE

MCC14LC5003Z AU BUMP DIE

MCC14LC5004Z AU BUMP DIE

Devices are independently addressable via a two-wire (or three-wire) com-

munication link which can be common with other peripheral devices.

The MC14LC5003/5004 are low cost version of MC145003 and MC145004

without cascading function.

•

Drives 72 Segments Per MC14LC5002’s Package

•

Drives 128 Segments Per MC14LC5003/5004’s Package

May Be Used with the Following LCDs: Segmented Alphanumeric,

Bar Graph, Dot Matrix, Custom

•

Quiescent Supply Current: 30 µA @ 2.7 V V

Operating Voltage Range: 2.7 to 5.5 V

Operating Temperature Range: -40 to 85°C

DD

Separate Access to LCD Drive Section’s Supply Voltage to Allow for Tem-

perature Compensation

•

See Application Notes AN1066 and AN442

REV 7

02/98

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–3

MC14LC5002 BLOCK DIAGRAM

FP1-FP4, FP9-FP12,

FP17-FP20, FP25-FP28

& FP31-FP32

V_LCD

BP1-BP4

OSC1

OSC2

OSCILLATOR

DRIVERS

FRAME

SYNC

GENERATOR

LCD VOLTAGE

WAVEFORM

AND TIMING

GENERATOR

128 - 32

MULTIPLEX

POR

DCLK

D_in

128-BIT LATCH

A0/A1

A2

ENB

128-BIT SHIFT REGISTER

MC14LC5002 PIN ASSIGNMENT

OSC1

FP32

FP31

FP28

FP27

FP26

FP25

FP20

1

2

3

4

5

6

7

8

ENB

Din

24

23

22

21

20

19

18

17

DCLK

FP1

FP2

FP3

FP4

FP9

MC14LC5002

MC14LC5002 • MC14LC5003 • MC14LC5004

3–4

MOTOROLA

MC14LC5003/MC14LC5004 BLOCK DIAGRAM

V_LCD

BP1-BP4

FP1-FP32

DRIVERS

OSC1

OSC2

OSCILLATOR

DRIVERS

FRAME

SYNC

GENERATOR

LCD VOLTAGE

WAVEFORM

AND TIMING

GENERATOR

128 - 32

MULTIPLEX

POR

DCLK

D_in

128-BIT LATCH

A0

A1

A2

ENB

128-BIT SHIFT REGISTER

MC14LC5003/MC14LC5004 PIN ASSIGNMENT

FP32

FP31

FP30

FP29

FP28

FP27

FP26

FP25

FP24

FP23

FP22

FP21

FP20

1

2

3

4

5

6

7

8

39 Din

38 DCLK

37 NC

36 FP1

35 FP2

34 FP3

33 FP4

32 FP5

31 FP6

30 FP7

29 FP8

28 FP9

27 FP10

MC14LC5003

OR

MC14LC5004

9

10

11

12

13

NC=NO CONNECTION

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–5

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

)

SS

This device contains protection circuitry

to guard against damage due to high static

voltages or electric ﬁelds. However, precau-

tions must be taken to avoid applications of

anyvoltagehigherthanmaximumratedvolt-

ages to this high-impedance circuit. This

device may be light sensitive. Caution

should be taken to avoid exposure of this

device to any light source during normal op-

eration. This device is not radiation protect-

ed.

Symbol

Parameter

DC Supply Voltage

Value

Unit

V

- 0.5 to + 6.5

V

DD

V

Input Voltage, D , and Data Clock

- 0.5 to + 15

V

in

V

Input Voltage, OSC of Master

- 0.5 to V + 0.5

in osc

in

DD

I

DC Input Current, per Pin

± 10

mA

°C

in

T

Operating Temperature Range

Storage Temperature Range

- 40 to + 85

- 65 to + 150

A

T

stg

* Maximum Ratings are those values beyond which damage to the device may occur. Func-

tional operation should be restricted to the limits in the Electrical Characteristics tables or

Pin Descriptions section.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V , T = 25°C)

SS

A

V

LCD

DD

Characteristic

V

Min

Typical

Max

Unit

Symbol

Output Drive Current — Frontplanes

µA

V

= 0.15 V

= 2.65 V

= 1.72 V

= 1.08 V

= 0.15 V

= 5.35 V

= 3.52 V

= 1.98 V

I

5

2.7

260

—

O

FH

I

FL

V

I

5

2.7

-240

—

O

FH

I

FL

V

I

5

2.7

-40

—

-1.5

O

FH

I

FL

V

I

5

2.7

40

—

2

O

FH

I

FL

V

I

5

5.5

600

—

O

FH

I

FL

V

I

5

5.5

-520

—

O

FH

I

FL

V

I

5

5.5

-35

—

-1.5

O

FH

I

FL

V

I

5

5.5

55

—

1

O

FH

I

FL

Supply Standby Currents (No Clock)

µA

I

= Standby @ I = 0 µA

I

DDS

2.7

—

5.5

—

2.7

—

30

800

50

DD

out

I

= Standby @ I = 0 µA

I

LCDS

LCD

out

I

= Standby @ I = 0 µA

I

DDS

DD

out

5.5

1500

= Standby @ I = 0 µA

I

LCDS

LCD

out

Supply Currents (f

) = 110 kHz

µA

OSC

I

2.7

5.5

—

2.7

5.5

—

30

—

170

—

70

—

400

40

70

I

= Quiescent @ I = 0 µA, no loading

DDQ

DD

out

I

= Quiescent @ loading = 270pF

= Quiescent @ I = 0 µA, no loading

out

I

= Quiescent @ loading = 270pF

DD

I

= Quiescent @ I = 0 µA, no loading

LCDQ

LCD

out

—

= Quiescent @ I = 0 µA, no loading

out

Input Current

I

—

-0.1

—

0.1

7.5

µA

in

Input Capacitance

C

pF

in

(continued)

MC14LC5002 • MC14LC5003 • MC14LC5004

3–6

MOTOROLA

ELECTRICAL CHARACTERISTICS (Continued)

V

LCD

DD

V

Characteristic

Min

Typical

Max

Symbol

Unit

Frequencies

OSC2 Frequency @ R1; R1 = 200 kΩ

BP Frequency @ R1

OSC2 Frequency @ R2; R2 = 996 kΩ

f

kHz

Hz

kHz

5

100

23

—

150

33

OSC2

f

BP

f

OSC2

Average DC Offset Voltage (BP Relative to FP)

V

5

2.8

-50

—

+50

mV

V

OO

Input Voltage

“0” Level

“1” Level

= 2.65 V

= 0.15 V

V

2.8

5.5

5

—

0.85

1.65

IL

V

2.8

5.5

5

2

3.85

—

IH

*

Output Drive Current — Backplanes

V

5

2.8

-240

—

µA

O

I

BH

I

BL

V

I

5

2.8

260

—

O

BH

I

BL

V

= 1.08V

= 1.72 V

= 5.35 V

= 0.15 V

= 1.98 V

= 3.52 V

I

5

2.8

40

—

2

O

BH

BL

V

I

5

2.8

-40

—

-1

O

BH

I

BL

V

I

5

5.5

-520

—

O

BH

I

BL

V

I

5

5.5

600

—

O

BH

I

BL

V

I

5

5.5

55

—

1

O

BH

I

BL

V

I

5

5.5

-35

—

-1

O

BH

I

BL

Pulse Width, Data Clock

DCLK Rise/Fall Time

(Figure 1)

(Figure 2)

(Figure 3)

t

5

3

100

—

ns

µs

ns

w

t , t

5

3

—

120

r

f

Setup Time, D to DCLK

t

5

3

20

—

in

su

Hold Time, D to DCLK

t

5

3

40

60

—

in

h

Hold Time for START condition

Hold Time for STOP condition

DCLK Low to ENB High

ENB High to DCLK High

ENB High Pulse Width

t

5

3

100

—

start

t

5

3

100

—

stop

t

5

3

20

—

h

t

5

3

20

—

rec

t

5

3

100

—

w

ENB Low to DCLK High

t

5

3

20

—

su

NOTE: Timing for Figures 1, 2, and 3 are design estimates only.

* For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to

allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change.

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–7

SWITCHING WAVEFORMS

t

r

f

V

DD

90%

50%

10%

CLK

GND

t

w

Figure 1.

VALID

V

DD

50%

D

in

GND

t

stop

t

su

start

h

V

DD

CLK

GND

Figure 2.

t

w

V

DD

50%

ENB

CLK

GND

t

h

su

t

rec

V

DD

50%

FIRST

CLK

GND

LAST

CLK

Figure 3.

MC14LC5002 • MC14LC5003 • MC14LC5004

3–8

MOTOROLA

FUNCTIONAL DESCRIPTION

The MC14LC5002/5003/5004 have essentially two sections

which operate asynchronously from each other;the data input

and storage section and the LCD drive section.The LCD drive

and timing is derived from the oscillator, while the data input

from V

to 0 V, and when it is off, it switches from 1/3 V

LCD LCD

to 2/3 V

. When a frontplane driver is on, its

LCD

output switches from 0 V to V

, and when it is off, it switches

LCD

from 2/3 V

to 1/3 V

.

LCD

and storage is controlled by the Data In (D ), Data Clock

in

The LCD drive and timing section provides the multiplex sig-

nals and backplane driver input signals and formats the front-

plane and backplane waveforms.

The address pins are used to uniquely distinguish LCD driver

from any other chips on the same bus and to deﬁne LCD driver

as the “master” in the system.There must be one master in any

system.

The enable pin may be used as a third control line in the

communication bus. It may be used to deﬁne the moment

when the data is latched. If not used, then the data is latched

after 128 bits of data have been received.

(DCLK), Address (A0, A1, A2), and Enable (ENB) pins.

Data is shifted serially into the 128-bit shift register and ar-

ranged into four consecutive blocks of 32 parallel data bits. A

time-multiplex of the four backplane drivers is made (each

backplane driver becoming active then inactive one after an-

other) and, at the start of each backplane active period, the

corresponding block of 32 bits is made available at the front-

plane drivers. A high input to a plane driver turns the driver

on, and a low input turns the driver off.

Figure 4 shows the sequence of backplanes.Figure 5 shows

the possible conﬁgurations of the frontplanes relative to the

backplanes.When a backplane driver is on, its output switches

TIME FRAME

V

LCD

2/3 (V

1/3 (V

0 V

)

LCD

BP1

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

LCD

BP2

BP3

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

LCD

BP4

LCD

Figure 4. Backplane Sequence

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–9

TIME FRAME

V

LCD

BP1

0 V

V

0 V

V

FP DATA

BITS

4321

FP DATA

BITS

4321

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

0000

0001

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

1000

0100

1001

0101

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

1101

0011

1011

0111

1111

1100

0010

1010

0110

1110

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

V

LCD

2/3 (V

1/3 (V

0 V

)

2/3 (V

1/3 (V

0 V

)

LCD

Figure 5. Frontplane Combinations

MC14LC5002 • MC14LC5003 • MC14LC5004

3–10

MOTOROLA

PIN DESCRIPTIONS

A0, A1,A2 for MC14LC5003/5004

A0/A1,A2 for MC14LC5002

Address Inputs

10 M

1 M

The address pins must be tied to V . This deﬁnes the

DD

normal operation mode.

100 k

10 k

CAUTION

The conﬁguration A0, A1, A2 = 111 must be used.The conﬁg-

uration A0, A1, A2 = 000 is reserved for Motorola’s use only.

Allthreeaddresspinsshouldneverbetiedto0Vsimultaneous-

ly.

1 k

10 k

100 k

1 M

10 M

OSCILLATOR FREQUENCY

Figure 6. Oscillator Frequency vs. Load Resistance

(Approximate)

ENB

Enable Input

If the ENB pin is tied to V , the MC14LC5002/5003/5004

DD

will always latch the data after 128 bits have been received.

The latched data is multiplexed and fed to the frontplane driv-

ers for display. If external control of this latching function is

required, then the ENB pin should be held low, followed by

one high pulse on ENB when data display is required. (This

may be useful in a system where MC14LC5002/5003/5004 is

permanently addressed and only the last 128 bits of data sent

are required to be latched for display).The pulse on the ENB

pin must occur while DCLK is high.

FP1-FP32

Frontplane Drivers

Frontplane driver outputs.

BP1-BP4

Backplane Drivers

Backplane driver outputs.

V

LCD

LCD Driver Supply

DCLK, D

Power supply input for LCD drive outputs. May be used to

supply a temperature-compensated voltage to the LCD drive

section, which can be separate from the logic voltage supply,

in

Data Clock and Data Input

Address input and data input controls.See Data Input Pro-

tocol sections for relevant option.

V

.

DD

V

OSC1, OSC2

DD

Oscillator Pins

Positive Power Supply

To use the on-board oscillator, an external resistor should

be connected between OSC1 and OSC2. Optionally, the

OSC1 pin may be driven by an externally generated clock

signal.

A resistor of 680 kΩ connected between OSC1 and OSC2

pins gives an oscillator frequency of about 30 kHz, giving ap-

proximately30HzasseenattheLCDdriveroutputs.Aresistor

of 200 kΩ gives about 100 kHz, which results in 100Hz at the

driver outputs. LCD manufacturers recommend an LCD drive

frequency of between 30 Hz and 100 Hz. See Figure 6.

This pin supplies power to the main processor interface and

logic portions of the device. The voltage range is 2.7 to 5.5 V

with respect to the V pin.

SS

For optimum performance, V should be bypassed to

DD

V

using a low inductance capacitor mounted very closely

SS

to these pins. Lead length on this capacitor should be mini-

mized.

V

SS

Ground

Common ground.

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–11

line low for at least one clock-pulse time while the clock line is

high.

After the start condition has been established, an eight-bit

DATA INPUT PROTOCOL

Two-wire communication bus DCLK, D ; three-wire com-

in

munication bus DCLK, D , ENB.

in

address (0111111X ) should be sent by the controller followed

0

by an extra clock pulse while the data line is left high. In this

option, only the seven most signiﬁcant bits of the address are

used to uniquely deﬁne devices on the bus, the least signiﬁcant

MC14LC5002/5003 — SERIAL INTERFACE DEVICE (FIG-

URE 7)

Before communication with an MC14LC5002/5003 can be-

gin, a start condition must be set up on the bus by the trans-

mitter.To establish a start condition, the transmitter must pull

the data line low for at least one clock-pulse time while the

clock line is high. The “idle” state for the clock line and data

line is the high state.

After the start condition has been established, an eight-bit

address (01111110) should be sent by the transmitter. If the

address sent corresponds to the address of the

MC14LC5002/5003 then on each successive clock pulse, the

addressed device will accept a data bit.

If the ENB pin is permanently high, then the addressed

MC14LC5002/5003’s internal counter latches the data to be

displayed after 128 data bits have been received. Otherwise,

the control of this latch function may be overridden by holding

the ENB line low until the new data is required to be displayed,

then a high pulse should be sent on the ENB line. The high

pulse must be sent during DCLK high (clock idle).

To end communication with an MC14LC5002/5003, a stop

condition should be set up on the bus (or another start con-

dition may be set up if another communication is desired).To

establish a stop condition, the transmitter must pull the data

line high for at least one clock-pulse time while the clock line

is high.Note that the communication channel to an addressed

device may be left open after the 128 data bits have been sent

by not setting up a stop or a start condition. In such a case,

the 129th rising DCLK edge, which normally would be used

to set up the stop or start condition, is ignored by the

MC14LC5002/5003 and data continues to be received on the

130th rising DCLK. The latch function continues to work as

normal (i.e., data is be latched either after each block of 128

data bits has been received or under external control as re-

quired).

bit X is used as a read/write control: if the least signiﬁcant bit

0

is 0, then the controller writes to the LCD driver; if it is 1, then

the controller reads from the LCD driver’s 128-bit shift register

on a ﬁrst-in ﬁrst-out basis.If the seven most signiﬁcant address

bits sent correspond to the address of the LCD driver then the

addressed LCD driver responds by sending an “acknowledge”

bit back to the controller (i.e., the LCD driver pulls the data line

low during the extra clock pulse supplied by the controller). If

the least signiﬁcant address bit was 0, then the controller

should continue to send data to the LCD driver in blocks of

eight bits followed by an extra ninth clock pulse to allow the

LCD driver to pull the data line D low as an acknowledgment.

in

If the least signiﬁcant address bit was 1, then the LCD driver

sends data back to the controller (the clock is supplied by the

controller). After each successive group of eight bits sent, the

LCD driver leaves the data line high for one pulse.

If the ENB pin is permanently high, then the addressed

MC14LC5004’s internal counter latches the data to be dis-

played after 128 data bits have been received. Otherwise the

control of this latch function may be overridden by holding the

ENB line low until the new data is required to be displayed,

then a high pulse should be sent on the ENB line. The high

pulse must be sent during DCLK high (clock idle).

To end communication with an MC14LC5004, a stop condi-

tion should be set up on the bus (or another start condition

may be set up if another communication is desired).To estab-

lish a stop condition, the transmitter must pull the data line high

for at least one clock-pulse time while the clock line is high.

Note that the communication channel to an addressed device

may be left open after the 128 data bits have been sent by not

setting up a stop or a start condition. In such a case the rising

DCLK edge which comes after all 128 data bits have been sent

and after the last acknowledge-related clock pulse has been

made is ignored;data continues to be received on the following

DCLK high. The latch function continues to work as normal

(i.e., data is latched either after each block of 128 data bits has

been received or under external control as required).

At any time during data transmission, the transfer may be

interrupted with a stop condition. Data transmission may be

resumed with a start condition and resending the address.

MC14LC5004 — IIC DEVICE (FIGURE 8)

Before communication with an MC14LC5004 can begin, a

start condition must be set up on the bus by the controller.To

establish a start condition, the controller must pull the data

At any time during data transmission, the transfer may be

interrupted with a stop condition. Data transmission may be

resumed with a start condition and resending the address.

MC14LC5002 • MC14LC5003 • MC14LC5004

3–12

MOTOROLA

Figure 8 . Data Input MC14LC5004 (IIC Device)

MC14LC5002 • MC14LC5003 • MC14LC5004

3–14

MOTOROLA

APPLICATION INFORMATION

Figure 9 shows an interface example for serial data interface.

Example 1 contains the software to use HC05 with MC14LC5003 in serial data interface.

V

DD

A0 A1 A2

OSC1

OSC2

DOUT

SCK

D

in

R = 470 kΩ

MC14LC5003

MC68HC05

DCLK

ENB

STROBE

FP1-FP32

BP1-BP4

1/4 MUX DISPLAY

Figure 9. Serial Interface Example Between MC68HC05 and MC14LC5003

PORTC

DDRC

SEN

SCL

SDA

EQU

$02

PORTC

PORTDC

ENABLE PIN, PC7

CLOCK PIN, PC6

DATA PIN, PC5

OUTPUT DATA

$06

$07

$06

$05

$FF

DOUT

ORG

$0050

W1

COUNT

RMB

1

ORG

FCB

$1FFE

#$01

#$00

ADDRESS OF RESET VECTOR OF MC68HC805C4

RESET VECTOR

*** Main Program start at 0100 ***

ORG

LDA

STA

$0100

#DOUT

DDRC

START

AGAIN

SET DATA LINE OUTPUT

LDX

#$00

BSET

SDA,PORTC IDLE STATE

SCL,PORTC CLOCK AND DATA ARE HIGH

READY

LBYTE

BSET

LDA

STA

SEN,PORTC EN=1

#$11

W1

SET ADDRESS AND 8 CHARACTERS

BCLR

SDA,PORTC START CONDITION, DATA LOW WHILE CLOCK HIGH

CLC

LDA

STA

LDA

INCX

#$08

COUNT

SEND,X

8 BITS TO SHIFT

GET A BYTE

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–15

LBIT

BCLR

ROLA

BCC

SCL,PORTC CLOCK LOW

DZERO DATA BIT=0 ?

BSET

JMP

SDA,PORTC NO, BIT=1 AND DATA HIGH

CLKHI

DZERO

CLKHI

BCLR

BSET

DEC

SDA,PORTC DATA LOW

SCL,PORTC

COUNT

LBIT

CLOCK HIGH

BNE

DEC

W1

BNE

LBYTE

LAST BYTE ?

STOP

BCLR

BSET

BCLR

RTS

SCL,PORTC

SDA,PORTC STOP CONDITION

SCL,PORTC DATA GOES HIGH WHILE CLOCK HIGH

SDA,PORTC

SEN,PORTC EN=0

*** End of Program ***

*** LCD Address and Data ***

SEND

FCB

RTS

$7E

LCD DRIVER ADDRESS

DATA TO SENT

$FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF

Example 1. Serial Data Interface Method

Figure 10 shows an interface example for IIC interface.

V

DD

1kΩ

A0 A1 A2

OSC1

OSC2

DOUT

D

in

R = 470 kΩ

MC14LC5004

MC68HC05

SCK

DCLK

ENB

STROBE

FP1-FP32

BP1-BP4

1/4 MUX DISPLAY

Figure 10. IIC Interface Example Between MC68HC05 and MC14LC5004

MC14LC5002 • MC14LC5003 • MC14LC5004

3–16

MOTOROLA

PACKAGE DIMENSIONS

QFP

FU SUFFIX

CASE 848B-02

L

39

27

26

40

-D-

B

-A-

L

V

DETAIL A

52

14

B

13

1

-D-

B

S

0.20 (0.008)

0.05 (0.002)

A-B

D

S

M

H

A-B

-A,B,D-

DETAIL A

F

V

0.20 (0.008)

C

M

D

S

DETAIL C

M

C

E

J

N

DATUM

-H-

-C-

SEATING

BASE METAL

0.10 (0.004)

H

D

G

M

D

0.02 (0.008)

C

A-B

S

M

S

SECTION B-B

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MX

NOTES:

U

1.DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

A

B

C

D

E

F

9.90

2.10

0.22

2.00

0.22

10.10 0.390 0.398

2.CONTROLLING DIMENSION: MILLIMETER.

3.DATUM PLANE -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY

AT THE BOTTOM OF THE PARTING LINE.

4.DATUMS -A-, -B- AND -D- TO BE DETERMINED

AT DATUM PLANE -H-.

2.45

0.38

2.10

0.33

0.083 0.096

0.009 0.015

0.079 0.083

0.009 0.013

0.026 BSC

T

^DATUM-H-

G

H

J

0.65 BSC

R

Q

--

0.25

0.23

0.95

--

0.010

5.DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE -C-.

0.13

0.65

0.005 0.009

0.026 0.037

0.307 REF

K

L

6.DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE -H-.

7.DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR CANNOT BE

7.80 REF

K

M

N

Q

R

S

T

5˚

0.13

0˚

10˚

0.17

7˚

5˚

0.005 0.007

0˚ 7˚

0.005 0.012

10˚

W

X

0.13

0.30

12.95 13.45 0.510 0.530

DETAIL C

0.13

0˚

--

0.005

0˚

--

U

V

W

X

12.95 13.45 0.510 0.530

0.35

0.45

0.014 0.018

0.063 REF

1.6 REF

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–17

PACKAGE DIMENSIONS

TQFP

FB SUFFIX

CASE 873A-02

MILLIMETERS

INCHES

MIN MAX

NOTES:

DIM MIN

MAX

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

1.DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

A

AI

B

0.276 BSC

0.138 BSC

0.276 BSC

0.138 BSC

2.CONTROLLING DIMENSION: MILLIMETER.

3.DATUM PLANE -AB- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY

AT THE BOTTOM OF THE PARTING LINE.

4.DATUMS -T-, -U- AND -Z-TO BE DETERMINED AT

DATUM PLANE -AB-.

BI

C

D

E

1.400 1.600 0.055 0.063

0.300 0.450 0.012 0.018

1.350 1.450 0.053 0.057

0.300 0.400 0.012 0.016

0.800 BASIC 0.031 BASIC

0.050 0.150 0.002 0.006

0.090 0.200 0.004 0.008

0.500 0.700 0.020 0.028

5.DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE -AC-.

F

6.DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE -AB-.

7.DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE D

DIMENSION TO EXCEED 0.520 (0.020).

8.MINIMUM SOLDER PLATE THICKNESS SHALL

BE 0.0076 (0.0003).

G

H

J

K

M

N

P

12˚ REF

0.090 0.160 0.004 0.006

0.400 BASIC 0.016 BASIC

Q

R

S

1˚

5˚

1˚

5˚

0.150 0.250 0.006 0.010

9.EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.354 BSC

0.014 BSC

0.354 BSC

0.014 BSC

0.008 REF

0.039 REF

SI

V

VI

W

X

MC14LC5002 • MC14LC5003 • MC14LC5004

3–18

MOTOROLA

BOND PAD LAYOUT

-X

+X

For MCC14LC5003 / MCC14LC5004 BARE DIE &

MCC14LC5003Z / MCC14LC5004Z AU BUMP DIE :

PIN 1

2

DIE SIZE : 1981.2 x 3022.6 µm

2,

(78 x 119 mil 1 mil ~ 25.4µm)

2

AU BUMP SIZE : 70 x 70 µm

+Y

RESERVED AREA :

AREA A

COORDINATES

AREA

X

Y

A

B

-445

-300

-74

193

45

193

-910

-1100

-910

-Y

-74

AREA B

368

HONG KONG I.C.

DESIGN CENTER

©

Dimensions in µm

Note :

1. Reserved area contains dummy bumps for IC bumping process alignment

and IC identiﬁcations.

2. No conductive tracks should be laid underneath reserved area to avoid

short circuit.

3. Reserved area applies to Au bump die only. It does not apply to bare die.

Die Pad Coordinates

Coordinates

Die

Pad No.

Die

Pad No.

Pin Name

X

Y

X

Y

25

26

27

28

29

30

31

32

33

34

35

36

37

FP10

FP9

FP8

FP7

FP6

FP5

FP4

FP3

FP2

FP1

NC

735.998

736.000

-837.201

-690.001

-542.801

-395.601

-248.401

-101.201

45.999

1

2

FP32

FP31

FP30

FP29

FP28

FP27

FP26

FP25

FP24

FP23

FP22

FP21

FP20

FP19

FP18

FP17

FP16

FP15

V_LCD

-736.002

-588.802

-441.602

-294.402

-147.202

0.000

929.199

781.999

3

634.799

4

487.599

5

340.399

6

193.199

7

45.999

193.199

340.399

487.599

634.800

782.000

929.200

8

-101.201

-248.401

-395.601

-542.801

-690.001

-837.201

-1205.601

-1205.600

9

10

11

12

13

14

15

16

17

18

19

DCLK

D_IN

38

39

40

41

42

43

44

45

46

ENB

A2

736.000

588.800

441.600

294.400

147.198

-0.002

1205.600

1205.599

1205.600

A1

A0

BP4

BP3

BP2

BP1

V_DD

-147.202

-294.402

-441.600

20

V_SS

147.200

-1205.600

21

22

23

24

FP14

FP13

FP12

FP11

294.398

441.598

588.798

735.998

-1205.601

47

48

OSC2

OSC1

-588.800

-736.000

1205.600

Dimensions in µm

MOTOROLA

MC14LC5002 • MC14LC5003 • MC14LC5004

3–19


型号：	MC14LC5003FU
厂家：	NXP
描述：	IC,LCD DISPLAY DRIVER,128-SEG,4-BP,CMOS,QFP,52PIN,PLASTIC 驱动 CD 接口集成电路
文件：	总17页 (文件大小：452K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14LC5003FU [NXP]

相关型号：

MC14LC5004

MC14LC5004

MC14LC5004AFU

MC14LC5004FU

MC14LC5004FU

MC14LC5436DW

MC14LC5436DWR2

MC14LC5436P

MC14LC5447

MC14LC5447DW

MC14LC5447DWR2

MC14LC5447P