MC16S2CPU25B1 [NXP]
IC,MICROCONTROLLER,16-BIT,6816 CPU,CMOS,QFP,100PIN,PLASTIC;
| 型号： | MC16S2CPU25B1 |
| 厂家： | 
NXP |
| 描述： | IC,MICROCONTROLLER,16-BIT,6816 CPU,CMOS,QFP,100PIN,PLASTIC 时钟 外围集成电路 |
| 文件： | 总104页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68HC16S2
Technical Summary
16-Bit Modular Microcontroller
1 Introduction
The MC68HC16S2 is a high-speed 16-bit microcontroller. It is a member of the MC68300/M68HC16
family.
M68HC16 microcontrollers are built up from standard modules that interface through a common inter-
module bus (IMB). Standardization facilitates rapid development of devices tailored for specific applica-
tions.
The MCU incorporates a 16-bit central processing unit (CPU16), a system integration module (SIM),
and a 2-Kbyte standby RAM module (SRAM).
The MCU clock can either be synthesized from an external reference or input directly. Operation with a
32.768 kHz reference frequency is standard. The maximum system clock speed is 25.17 MHz. System
hardware and software allow changes in clock rate during operation. Because MCU operation is fully
static, register and memory contents are not affected by clock rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently implements
this capability.
Table 1 MC68HC16S2 Ordering Information
Package Type Frequency
(MHz)
Temperature
Package
Order
Order Number
Quantity
100-pin TQFP
20.97 MHz – 40 to + 85 °C
25.17 MHz – 40 to + 85 °C
2
84
420
2
SPMC16S2CPU20
MC68HC16S2CPU20
MC16S2CPU20B1
SPMC16S2CPU25
MC68HC16S2CPU25
MC16S2CPU25B1
84
420
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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TABLE OF CONTENTS
Section
Page
1
Introduction
1
1.1
1.2
1.3
1.4
1.5
Features ......................................................................................................................................3
Block Diagram .............................................................................................................................4
Pin Assignments ..........................................................................................................................5
Address Map ...............................................................................................................................6
Intermodule Bus ..........................................................................................................................6
2
Signal Descriptions
7
2.1
2.2
2.3
2.4
2.5
Pin Characteristics ......................................................................................................................7
Power Connections .....................................................................................................................8
Output Driver Types ....................................................................................................................8
Signal Characteristics ..................................................................................................................8
Signal Functions ..........................................................................................................................9
3
System Integration Module
10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Overview ...................................................................................................................................10
System Configuration Block ......................................................................................................12
System Clock ............................................................................................................................14
System Protection Block ...........................................................................................................19
External Bus Interface ...............................................................................................................24
Chip-Selects ..............................................................................................................................28
General-Purpose Input/Output ..................................................................................................37
Resets .......................................................................................................................................39
Interrupts ...................................................................................................................................42
3.10 Factory Test Block .....................................................................................................................44
4
Central Processing Unit
45
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Overview ...................................................................................................................................45
M68HC11 Compatibility .............................................................................................................45
Programming Model ..................................................................................................................46
Data Types ................................................................................................................................47
Addressing Modes .....................................................................................................................48
Instruction Set ...........................................................................................................................49
Exceptions .................................................................................................................................68
5
6
Standby RAM Module
71
5.1
5.2
5.3
5.4
Overview ...................................................................................................................................71
SRAM Register Block ................................................................................................................71
SRAM Registers ........................................................................................................................71
SRAM Operation .......................................................................................................................73
Electrical Characteristics
74
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1.1 Features
• CPU16
— 16-bit architecture
— Full set of 16-bit instructions
— Three 16-bit index registers
— Two 16-bit accumulators
— Control-oriented digital signal processing capability
— One Mbyte of program memory and one Mbyte of data memory
— High-level language support
— Fast interrupt response time
— Background debugging mode
— Fully static operation
• System Integration Module (SIM)
— External bus support
— Programmable chip select outputs
— System protection logic
— Watchdog timer, clock monitor and bus monitor
— Two 8-bit dual function input/output ports
— One 7-bit dual function output port
— Phase-locked loop (PLL) clock system
• Standby RAM Module (SRAM)
— 2 Kbytes of static RAM
— External standby voltage supply input
MC68HC16S2
MC68HC16S2TS/D
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1.2 Block Diagram
CSBOOT
ADDR23/CS10
ADDR22/CS9/PC6
ADDR21/CS8/PC5
ADDR20/CS7/PC4
ADDR19/CS6/PC3
FC2/CS5/PC2
FC1/CS4/PC1
FC0/CS3/PC0
BGACK/CS2
CHIP
SELECT
CS[10:0]
V
STBY
BGACK
BG
BR
FC2
FC1
FC0
SIM
BG/CS1
BR/CS0
ADDR[23:19]
2K SRAM
ADDR[18:0]
SIZ1
SIZ0
AS
SIZ1/PE7
SIZ0/PE6
AS/PE5
EBI
DS
DS/PE4
PE3
PE3
V
(10)
(12)
AVEC
DSACK1
DSACK0
AVEC/PE2
DSACK1/PE1
DSACK0/PE0
DD
IMB
V
SS
DATA[15:0]
R/W
RESET
HALT
BERR
IRQ7/PF7
IRQ6/PF6
IRQ5/PF5
IRQ4/PF4
IRQ3/PF3
IRQ2/PF2
IRQ1/PF1
MODCLK/PF0
CLKOUT
XTAL
IRQ[7:1]
CPU16
MODCLK
CLOCK
TEST
EXTAL
XFC
VDDSYN
TSC
TSC
QUOT
FREEZE/QUOT
FREEZE
BKPT
IPIPE1
IPIPE0
DSI
BKPT/DSCLK
IPIPE1/DSI
IPIPE0/DSO
DSO
DSCLK
S2BLOCK
Figure 1 MC68HC16S2 Block Diagram
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1.3 Pin Assignments
ADR21/CS8/PC5
1
DATA10
DATA11
DATA12
DATA13
VSSE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
ADDR22/CS9/PC6
ADDR23/CS10/ECLK
BKPT/DSCLK
VDDE
2
3
4
5
VSSE
6
VDDE
IPIPE0/DSO
IPIPE1/DSI
ADDR1
7
DATA14
DATA15
ADDR0
8
9
ADDR2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
VSSI
ADDR3
ADDR4
VSSI
MC68HC16S2
ADDR5
PE3
ADDR6
DS/PE4
AS/PE5
ADDR7
ADDR8
SIZ0/PE6
SIZ1/PE7
VSSE5
ADDR9
VDDE
VSSE
VDDE5
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
R/W
MODCLK/PF0
IRQ1/PF1
IRQ2/PF2
IRQ3/PF3
16S2 100-PIN QFP
Figure 2 MC68HC16S2 Pin Assignments
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1.4 Address Map
Figure 3 is a map of the MCU internal addresses. Although there are 24 intermodule bus (IMB) address
lines, the CPU16 uses only ADDR[19:0]. ADDR[23:20] follow the logic state of ADDR19. Addresses
$080000 to $F7FFFF are not accessible. The RAM array is positioned by the base address register in
the associated RAM control block. Unimplemented blocks are mapped externally.
$000000
$YFFA00
SIM
128 BYTES
$YFFA7F
BASE
ADDRESS
$YFFB00
SRAM CTL
8 BYTES
SRAM ARRAY
2048 BYTES
$YFFB07
$FFFFFF
16S2 ADDRESS MAP
Figure 3 MC68HC16S2 Address Map
1.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partition-
ing, multiple interrupt levels, and vectored interrupts. The standardized modules in the MC68HC16S2
communicate with one another and with external components through the IMB. Although the full IMB
supports 24 address and 16 data lines, the MC68HC16S2 uses only 16 data lines and 20 address lines.
Because the CPU16 uses only 20 address lines, ADDR[23:20] follow the state of ADDR19.
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2 Signal Descriptions
2.1 Pin Characteristics
Table 2 shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can
be put in a high impedance state, but the method of doing this differs depending upon pin function. Refer
to Table 4 for a description of output drivers. An entry in the discrete I/O column of the MCU pin char-
acteristics table indicates that a pin has an alternate I/O function. The port designation is given when it
applies. Refer to the MCU block diagram for information about port organization.
Table 2 MCU Pin Characteristics
Pin Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:0]
AS
A
A
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
—
—
O
—
PC[6:3]
—
A
—
I/O
I/O
—
—
—
—
—
—
—
—
I/O
I/O
—
O
B
PE5
PE2
—
AVEC
B
1
BERR
B
Yes
BG/CS1
B
—
Yes
Yes
Yes
—
—
BGACK/CS2
BKPT/DSCLK
BR/CS0
B
No
Yes
No
—
—
—
B
—
—
CLKOUT
A
—
CSBOOT
B
—
—
—
2
DATA[15:0]
DS
Aw
B
Yes
No
No
No
Yes
No
—
—
Yes
Yes
—
PE4
PE[1:0]
—
DSACK[1:0]
EXTAL
B
—
A
FC[2:0]/CS[5:3]
FREEZE/QUOT
HALT
Yes
—
PC[2:0]
—
A
—
—
1
Bo
No
—
Yes
IPIPE0/DSO
IPIPE1/DSI
IRQ[7:1]
A
A
B
B
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
No
I/O
I/O
PF[7:1]
PF0
2
MODCLK
R/W
RESET
PE3
A
Bo
B
Yes
Yes
Yes
Yes
Yes
—
No
Yes
Yes
No
—
—
—
—
I/O
I/O
—
PE3
PE[7:6]
—
SIZ[1:0]
TSC
B
—
—
—
Yes
—
XFC
—
—
XTAL
—
—
—
—
NOTES:
1. HALT and BERR synchronized only if late HALT or BERR.
2. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as a port I/O pin.
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2.2 Power Connections
Table 3 MCU Power Connections
Description
Pin
V
Standby RAM power
Clock synthesizer power
STBY
V
DDSYN
V
V
External periphery output driver power (source and drain)
Internal module power (source and drain)
SSE DDE
V
V
SSI, DDI
2.3 Output Driver Types
Table 4 MCU Output Driver Types
Type
A
I/O
O
Description
Output only signals that are always driven; no external pull-up required
Type A output with weak P-channel pull-up during reset
Aw
B
O
O
Three-state output that includes circuitry to pull up output before high impedance is established
to ensure rapid rise time. An external holding resistor is required to maintain logic level while
the pin is in the high-impedance state.
Bo
O
Type B output that can be operated in an open-drain mode.
2.4 Signal Characteristics
Table 5 MCU Signal Characteristics
Signal Name
ADDR[23:0]
AS
MCU Module
SIM
Signal Type
Bus
Active State
—
0
SIM
Output
Input
AVEC
SIM
0
BERR
SIM
Input
0
BG
SIM
Output
Input
0
BGACK
BKPT
SIM
0
CPU16
SIM
Input
0
BR
Input
0
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
SIM
Output
Output
Output
Bus
—
0
SIM
SIM
0
SIM
—
0
SIM
Output
Input
DSACK[1:0]
DSCLK
DSI
SIM
0
CPU16
CPU16
CPU16
SIM
Input
—
—
—
—
—
1
Input
DSO
Output
Input
EXTAL
FC[2:0]
FREEZE
HALT
SIM
Output
Output
Input/Output
Output
Input
SIM
SIM
0
IPIPE[1:0]
IRQ[7:1]
MODCLK
CPU16
SIM
—
0
SIM
Input
—
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Table 5 MCU Signal Characteristics (Continued)
Signal Name
QUOT
R/W
MCU Module
SIM
Signal Type
Output
Active State
—
1/0
0
SIM
Output
RESET
PE3
SIM
Input/Output
Output
SIM
—
—
—
—
—
SIZ[1:0]
TSC
SIM
Output
SIM
Input
XFC
SIM
Input
XTAL
SIM
Output
2.5 Signal Functions
Table 6 MCU Signal Functions
Signal Name
Address Bus
Mnemonic
ADDR[23:0]
AS
Function
20-bit address bus used by CPU16; ADDR[23:20] follow ADDR19
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Signals a bus error to the CPU
Address Strobe
Autovector
AVEC
Bus Error
BERR
Bus Grant
BG
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
System clock output
Bus Grant Acknowledge
Breakpoint
BGACK
BKPT
Bus Request
System Clock Out
Chip Selects
Boot Chip Select
Data Bus
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
Select external devices at programmed addresses
Chip-select for external boot start-up ROM
16-bit data bus
Data Strobe
Indicates that an external device should place valid data on the data
bus during a read cycle and that valid data has been placed on the
bus by the CPU during a write cycle
Data and Size
Acknowledge
DSACK[1:0]
Acknowledges to the SIM that data has been received for a write
cycle, or that data is valid on the data bus for a read cycle
Development Serial In,
Out, Clock
DSI, DSO,DSCLK Serial I/O and clock for background debug mode
Crystal Oscillator
EXTAL, XTAL
Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
Function Codes
Freeze
FC[2:0]
FREEZE
HALT
Identify processor state and current address space
Indicates that the CPU has entered background debug mode
Suspend external bus activity
Halt
Instruction Pipeline
Interrupt Request Level
Clock Mode Select
Quotient Out
Reset
IPIPE[1:0]
IRQ[7:1]
MODCLK
QUOT
Indicate instruction pipeline activity
Request interrupt service from the CPU
Selects system clock source
Provides the quotient bit of the polynomial divider
System reset
RESET
R/W
Read/Write
Indicates the direction of data transfer on the bus
Indicates the number of bytes to be transferred during a bus cycle
Places all output drivers in a high impedance state
Connection for external phase-locked loop filter capacitor
Size
SIZ[1:0]
TSC
Three-State Control
External Filter Capacitor
XFC
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3 System Integration Module
The system integration module (SIM) consists of six functional blocks that control system startup, ini-
tialization, configuration, and external bus. Figure 4 shows the SIM block diagram.
SYSTEM CONFIGURATION
XTAL
CLKOUT
EXTAL
CLOCK SYNTHESIZER
MODCLK
SYSTEM PROTECTION
CHIP-SELECTS
CHIP-SELECTS
EXTERNAL BUS
RESET
EXTERNAL BUS INTERFACE
FACTORY TEST
TSC
FREEZE/QUOT
S(C)IM BLOCK
Figure 4 SIM Block Diagram
3.1 Overview
The system configuration block controls MCU configuration and operating mode.
The clock synthesizer generates clock signals used by the SIM, other IMB modules, and external de-
vices. In addition, a periodic interrupt generator supports execution of time-critical control routines.
The system protection block provides bus and software watchdog monitors.
The chip-select block provides eleven general-purpose chip-select signals and a boot ROM chip-select
signal. Both general-purpose and boot ROM chip-select signals have associated base address regis-
ters and option registers.
The external bus interface handles the transfer of information between IMB modules and external ad-
dress space.
The system test block incorporates hardware necessary for testing the MCU. It is used to perform fac-
tory tests, and its use in normal applications is not supported.
Table 7 shows the SIM address map, which occupies 128 bytes. Unused registers within the 128-byte
address space return zeros when read.
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Table 7 SIM Address Map
Address
15
8 7
0
1
$YFFA00
$YFFA02
$YFFA04
$YFFA06
$YFFA08
$YFFA0A
$YFFA0C
$YFFA0E
$YFFA10
$YFFA12
$YFFA14
$YFFA16
$YFFA18
$YFFA1A
$YFFA1C
$YFFA1E
$YFFA20
$YFFA22
$YFFA24
$YFFA26
$YFFA28
$YFFA2A
$YFFA2C
$YFFA2E
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
$YFFA3C
$YFFA3E
$YFFA40
$YFFA42
$YFFA44
$YFFA46
$YFFA48
$YFFA4A
$YFFA4C
$YFFA4E
$YFFA50
SIM Module Configuration Register (SIMCR)
SIM Test Register (SIMTR)
Clock Synthesizer Control Register (SYNCR)
Not Used
Reset Status Register (RSR)
SIM Test Register E (SIMTRE)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Port E Data (PORTE0)
Port E Data (PORTE1)
Port E Data Direction (DDRE)
Port E Pin Assignment (PEPAR)
Port F Data (PORTF0)
Port F Data (PORTF1)
Port F Data Direction (DDRF)
Port F Pin Assignment (PFPAR)
System Protection Control (SYPCR)
Periodic Interrupt Control Register (PICR)
Periodic Interrupt Timer Register (PITR)
Not Used Software Service (SWSR)
Not Used
Not Used
Not Used
Not Used
Test Module Master Shift A (TSTMSRA)
Test Module Master Shift B (TSTMSRB)
Test Module Shift Count (TSTSC)
Test Module Repetition Counter (TSTRC)
Test Module Control (CREG)
Test Module Distributed Register (DREG)
Not Used
Not Used
Not Used
Port C Data (PORTC)
Not Used
Chip-Select Pin Assignment (CSPAR0)
Chip-Select Pin Assignment (CSPAR1)
Chip-Select Base Boot (CSBARBT)
Chip-Select Option Boot (CSORBT)
Chip-Select Base 0 (CSBAR0)
Chip-Select Option 0 (CSOR0)
Chip-Select Base 1 (CSBAR1)
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Table 7 SIM Address Map (Continued)
Address
$YFFA52
$YFFA54
$YFFA56
$YFFA58
$YFFA5A
$YFFA5C
$YFFA5E
$YFFA60
$YFFA62
$YFFA64
$YFFA66
$YFFA68
$YFFA6A
$YFFA6C
$YFFA6E
$YFFA70
$YFFA72
$YFFA74
$YFFA76
$YFFA78
$YFFA7A
$YFFA7C
$YFFA7E
NOTES:
15
8 7
0
Chip-Select Option 1 (CSOR1)
Chip-Select Base 2 (CSBAR2)
Chip-Select Option 2 (CSOR2)
Chip-Select Base 3 (CSBAR3)
Chip-Select Option 3 (CSOR3)
Chip-Select Base 4 (CSBAR4)
Chip-Select Option 4 (CSOR4)
Chip-Select Base 5 (CSBAR5)
Chip-Select Option 5 (CSOR5)
Chip-Select Base 6 (CSBAR6)
Chip-Select Option 6 (CSOR6)
Chip-Select Base 7 (CSBAR7)
Chip-Select Option 7 (CSOR7)
Chip-Select Base 8 (CSBAR8)
Chip-Select Option 8 (CSOR8)
Chip-Select Base 9 (CSBAR9)
Chip-Select Option 9 (CSOR9)
Chip-Select Base 10 (CSBAR10)
Chip-Select Option 10 (CSOR10)
Not Used
Not Used
Not Used
Not Used
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
3.2 System Configuration Block
The SIM controls MCU configuration during normal operation and during internal testing.
SIMCR — SIM Configuration Register
$YFFA00
15
14
13
12
0
11
10
0
9
8
7
6
5
0
4
0
3
2
1
0
EXOFF FRZSW FRZBM
RESET:
SLVEN
SHEN
SUPV
MM
IARB[3:0]
0
0
0
0
DATA11
0
0
0
1
1
0
0
1
1
1
1
The SIM configuration register controls system configuration. It can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can be written only once.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven by the MCU system clock.
1 = The CLKOUT pin is placed in a high-impedance state.
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FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts while the MCU is in background debug mode.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DATA11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. Table 8 shows whether show cycle data
is driven externally, and whether external bus arbitration can occur. To prevent bus conflict, external
peripherals must not be enabled during show cycles.
Table 8 Show Cycle Enable Bits
SHEN[1:0]
Action
00
01
10
11
Show cycles disabled, external bus arbitration allowed
Show cycles enabled, external bus arbitration not allowed
Show cycles enabled, external bus arbitration allowed
Show cycles enabled, external bus arbitration allowed,
internal activity is halted by a bus grant
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
The logic state of MM determines the value of ADDR23 for IMB module addresses. Because
ADDR[23:20] are driven to the same state as ADDR19, MM must be set to one. If MM is cleared, IMB
modules are inaccessible. This bit can be written only once after reset.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset value of IARB for all other modules
is %0000, which prevents SIM interrupts from being discarded during initialization.
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3.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral
bus. Because the MCU is a fully static design, register and memory contents are not affected when the
clock rate changes. System hardware and software support changes in clock rate during operation.
The system clock signal can be generated in one of two ways. An internal phase-locked loop can syn-
thesize the clock from a reference frequency, or the clock signal can be input directly from an external
source. Keep these clock sources in mind while reading the rest of this section. Figure 5 is a block
diagram of the system clock.
VDDSYN
CLKOUT
EXTAL
XTAL
XFC
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
W
Y
FEEDBACK DIVIDER
X
SYSTEM CLOCK CONTROL
SYSTEM
CLOCK
32 PLL BLOCK
Figure 5 System Clock Block Diagram
3.3.1 Clock Sources
The state of the MODCLK pin during reset determines the system clock source. When MODCLK is held
high during reset, the clock synthesizer generates a clock signal from a reference frequency connected
to the EXTAL pin. The clock synthesizer control register (SYNCR) determines operating frequency and
mode of operation. When MODCLK is held low during reset, the clock synthesizer is disabled and an
external system clock signal must be applied. The SYNCR control bits have no effect.
The input clock is referred to as “f ”, and can be either a crystal or an external clock source. The output
ref
of the clock system is referred to as “f ”. Ensure that f and f are within normal operating limits.
sys
ref
sys
The reference frequency for this MCU is typically 32.768 kHz, but can range from 25 kHz to 50 kHz. To
generate a reference frequency using the crystal oscillator, a reference crystal must be connected be-
tween the EXTAL and XTAL pins. Figure 6 shows a recommended circuit.
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C1
22 pF*
R1
330 kΩ
XTAL
R2
10 MΩ
EXTAL
C2
22 pF*
V
SSI
* RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768 kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
32 OSCILLATOR
Figure 6 System Clock Oscillator Circuit
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty
cycle of the input is critical, especially at operating frequencies close to maximum. The relationship be-
tween clock signal duty cycle and clock signal period is expressed:
Minimum External Clock High/Low Time
Minimum External Clock Period = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------
50 % – Percentage Variation of External Clock Input Duty Cycle
When the system clock signal is applied directly to the EXTAL pin (PLL is disabled, MODCLK = 0 during
reset), or the clock synthesizer reference frequency is supplied by a source other than a crystal (PLL
enabled, MODCLK = 1 during reset), the XTAL pin must be left floating. In either case, the frequency of
the signal applied to EXTAL may not exceed the maximum system clock frequency (PLL disabled) or
the maximum clock synthesizer reference frequency (PLL enabled).
3.3.2 Clock Synthesizer Operation
V
is used to power the clock circuits when the phase-locked loop is used. A separate power
DDSYN
source increases MCU noise immunity and can be used to run the clock when the MCU is powered
down. A quiet power supply must be used as the V source. Adequate external bypass capacitors
DDSYN
should be placed as close as possible to the V
pin to assure stable operating frequency. When
DDSYN
an external system clock signal is applied and the PLL is disabled, V
should be connected to the
DDSYN
V
supply. Refer to the SIM Reference Manual (SIMRM/AD) for more information regarding system
DD
clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty
cycle, the VCO frequency (f ) is either two or four times the system clock frequency, depending on
VCO
the state of the X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider
controls the frequency of one input to a phase comparator. The other phase comparator input is the
reference signal connected to the EXTAL pin. The comparator generates a control signal proportional
to the difference in phase between the two inputs. The signal is low-pass filtered and used to correct
the VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment and required clock sta-
bility. Figure 7 shows a recommended system clock filter network. XFC pin leakage must be kept within
specified limits to maintain optimum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal
is applied and the PLL is disabled. The XFC pin must be left floating in this case.
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VDDSYN
C3
C1
0.1 µF
0.1 µF
*
XFC
VDDSYN
C4
0.01 µF
VSSI
* MAINTAIN LOW LEAKAGE ON THE XFC NODE.
32 XFC CONN
Figure 7 System Clock Filter Network
When the clock synthesizer is used, SYNCR determines the operating frequency of the MCU. The fol-
lowing equation relates the MCU operating frequency to the clock synthesizer reference frequency (f )
ref
and the W, X, and Y fields in SYNCR:
fsys = 4fref(Y + 1)(22W + X
)
The W bit controls a prescaler tap in the feedback divider. Setting W increases VCO speed by a factor
of four. The Y field determines the count modulus for a modulo 64 downcounter, causing it to divide by
a value of Y+1. When W or Y changes, VCO frequency (f
) changes, and the VCO must relock.
VCO
The X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X=0 (reset
state), the divider is enabled, and the system clock is one-fourth the VCO frequency. Setting X=1
disables the divider, doubling the clock speed without changing the VCO frequency. There is no relock
delay when clock speed is changed by the X bit.
Internal VCO frequency is determined by the following equations:
fVCO = 4fsys if X = 0
or
fVCO = 2fsys if X = 1
For the MCU to operate correctly, system clock and VCO frequencies selected by the W, X, and Y bits
must be within the limits specified for the MCU. Do not use a combination of bit values that selects either
an operating frequency or a VCO frequency greater than the maximum specified values.
3.3.3 Clock Synthesizer Control
The clock synthesizer control circuits determine system clock frequency and clock operation under spe-
cial circumstances, such as following loss of synthesizer reference or during low-power operation. Clock
source is determined by the logic state of the MODCLK pin during reset.
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
W
14
X
13
12
11
10
9
8
7
6
0
5
0
4
3
2
1
0
1
1
Y
EDIV
RSVD SLOCK
STSIM STEXT
RSVD
RESET:
0
0
1
1
1
1
1
1
0
0
0
0
U
0
0
0
NOTES:
1. Ensure that initialization software does not change the value of this bit (it should always be zero).
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When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show the status of or control the operation of internal and external
clocks. SYNCR can be read or written only when the CPU is operating in supervisor mode.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting it increases the VCO speed
by a factor of four. VCO relock delay is required.
X — Frequency Control (Prescaler)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
the clock speed without changing the VCO speed. No VCO relock delay is required.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from zero to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by eight.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.6 Chip-Selects for more
information.
SLOCK — Synthesizer Lock Flag
0 = VCO has not locked, but is enabled on the desired frequency.
1 = VCO has locked on the desired frequency, or is disabled.
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock
status until after the user writes to SYNCR.
STSIM — Stop Mode SIM Clock
0 = When LPSTOP is executed, the SIM clock is driven by the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIM clock is driven by the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven by the SIM clock, as determined by
the state of the STSIM bit.
3.3.4 External MC6800 Bus Clock
The state of the ECLK division rate bit (EDIV) in SYNCR determines clock rate for the ECLK signal avail-
able on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can
be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The
clock is enabled by the CS10 field in chip-select pin assignment register 1 (CSPAR1). ECLK operation
during low-power stop is described in the following paragraph. Refer to 3.6 Chip-Selects for more in-
formation about the external bus clock.
3.3.5 Low-Power Operation
Low-power operation is initiated by the CPU16. To reduce power consumption selectively, the CPU16
can enter the following low-power modes:
1. The CPU16 can selectively disable a module by setting the module’s STOP bit.
2. The CPU16 can execute the LPSTOP instruction to stop the operations of the entire MCU.
If the STOP bit in a module is set, then that module enters a low power mode. Some or all of that mod-
ule’s registers remain accessible. The module can be restarted by asserting RESET or by the CPU16
clearing the module’s STOP bit.
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3.3.5.1 LPSTOP Mode
This low power mode offers the greatest power reduction. To enter normal LPSTOP mode, the CPU16
executes the LPSTOP instruction after clearing the STCPU bit in SYNCR. This causes the SIM to turn
off the system clock to most of the MCU.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt
mask into the clock control logic. The SIM brings the MCU out of normal LPSTOP mode when one of
the following exceptions occurs:
• RESET
• Trace
• SIM interrupt of higher priority than the stored interrupt mask
During LPSTOP, unless the system clock signal is supplied by an external source and that source is
removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The peri-
odic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK, and can be
used to bring the processor out of LPSTOP. The software watchdog monitor cannot perform this func-
tion. Optionally, the SIM can also continue to generate the CLKOUT signal while in LPSTOP.
STSIM and STEXT bits in SYNCR determine clock operation during LPSTOP.
The flow chart shown in Figure 8 summarizes the effects of the STSIM and STEXT bits when the MCU
enters normal LPSTOP mode.
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SETUP INTERRUPT
TO WAKE UP MCU
FROM LPSTOP
NO
USING
EXTERNAL CLOCK?
YES
NO
USE SYSTEM CLOCK
AS SIMCLK IN LPSTOP?
YES
SET STSIM = 1
fsimclk1 = fsys
SET STSIM = 0
fsimclk1 = fref
IN LPSTOP
IN LPSTOP
NO
NO
WANT CLKOUT
ON IN LPSTOP?
WANT CLKOUT
ON IN LPSTOP?
YES
YES
SET STEXT = 1
fclkout2 = fsys
SET STEXT = 0
fclkout2 = 0 Hz
SET STEXT = 1
fclkout2 = fref
SET STEXT = 0
fclkout2 = 0 Hz
feclk = ÷ fsys
IN LPSTOP
feclk = 0 Hz
IN LPSTOP
feclk = 0 Hz
IN LPSTOP
feclk = 0 Hz
IN LPSTOP
ENTER LPSTOP
NOTES:
1. THE SIMCLK IS USED BY THE PIT, IRQ, AND INPUT BLOCKS OF THE SIM.
2. CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMCR. IF EXOFF = 1, THE CLKOUT
PIN IS ALWAYS IN A HIGH IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP. IF EXOFF = 0, CLKOUT
IS CONTROLLED BY STEXT IN LPSTOP.
LPSTOPFLOW
Figure 8 LPSTOP Flowchart
3.4 System Protection Block
System protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software
watchdog timer. These functions reduce the number of external components required for complete sys-
tem control. Figure 9 shows the system protection block.
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MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT MONITOR
RESET REQUEST
BERR
BUS MONITOR
SPURIOUS INTERRUPT MONITOR
SOFTWARE WATCHDOG TIMER
CLOCK
RESET REQUEST
IRQ[7:1]
PRESCALER
9
2
PERIODIC INTERRUPT TIMER
SYS PROTECT BLOCK
Figure 9 System Protection Block
3.4.1 System Protection Control Register
The system protection control register controls the software watchdog timer, bus monitor, and halt
monitor. This register can be written only once following power-on or reset, but can be read at any time.
SYPCR — System Protection Control Register
$YFFA21
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
NOT USED
SWE
SWP
SWT[1:0]
HME
BME
BMT
RESET:
1
MODCLK
0
0
0
0
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescaler
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
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SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. Table 9 gives the
ratio for each combination of SWP and SWT bits.
Table 9 Software Watchdog Timing Field
SWP
SWT[1:0]
Ratio
9
0
00
2
11
0
0
0
1
1
1
1
01
10
11
00
01
10
11
2
13
2
15
2
18
2
20
2
22
2
24
2
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This bit field selects the time-out period in system clocks for the bus monitor. Refer to Table 10.
Table 10 Bus Monitor Time-Out Period
BMT[1:0]
Bus Monitor Time-Out Period
64 System clocks
00
01
10
11
32 System clocks
16 System clocks
8 System clocks
3.4.2 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge (IACK) cycles.
The monitor asserts BERR if the response time exceeds a user-specified timeout period.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT[1:0] field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a sys-
tem contains external bus masters, an external bus monitor must be implemented and the internal to
external bus monitor option must be disabled.
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3.4.3 Halt Monitor
The halt monitor responds to assertion of the HALT signal on the internal bus caused by a double bus
fault. A double bus fault occurs when:
• Bus error exception processing begins and a second BERR is detected before the first instruction
of the first exception handler is executed.
• One or more bus errors occur before the first instruction after a reset exception is executed.
• A bus error occurs while the CPU is loading information from a bus error stack frame during a re-
turn from exception (RTE) instruction.
If the halt monitor is enabled by setting HME in SYPCR, the MCU will issue a reset when a double bus
fault occurs, otherwise the MCU will remain halted.
A flag in the reset status register (RSR) indicates that the last reset was caused by the halt monitor.
3.4.4 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt ac-
knowledge cycle. Leaving IARB[3:0] set to %0000 in the module configuration register of any peripheral
that can generate interrupts will cause a spurious interrupt.
3.4.5 Software Watchdog
The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a
service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog
times out and issues a reset. This register can be written at any time, but returns zeros when read.
SWSR — Software Service Register
$YFFA27
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
SWSR
RESET:
0
0
0
0
0
0
0
0
Each time the service sequence is written, the software watchdog timer restarts. The servicing se-
quence consists of the following steps:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT[1:0] in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of RESET, as
shown in Table 11.
Table 11 MODCLK Pin States
MODCLK
SWP
0
1
1
0
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3.4.6 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts at user-programmable intervals. Timing for the
PIT is provided by a programmable prescaler driven by the system clock.
PICR — Periodic Interrupt Control Register
$YFFA22
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
PIRQL[2:0]
PIV[7:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
Table 12 shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT
interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT interrupt is ser-
viced first. The periodic timer continues to run when the interrupt is disabled.
Table 12 Periodic Interrupt Request Levels
PIRQL[2:0]
000
Interrupt Request Level
Periodic interrupt disabled
Interrupt request level 1
Interrupt request level 2
Interrupt request level 3
Interrupt request level 4
Interrupt request level 5
Interrupt request level 6
Interrupt request level 7
001
010
011
100
101
110
111
PIV[7:0] — Periodic Interrupt Vector
This bit field contains the vector generated in response to an interrupt from the periodic timer. When the
SIM responds, the periodic interrupt vector is placed on the bus.
PITR — Periodic Interrupt Timer Register
$YFFA24
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
PTP
PITM[7:0]
RESET:
0
0
0
0
0
0
0
MODCLK
0
0
0
0
0
0
0
0
PITR contains the count value for the periodic timer. Setting the PITM[7:0] field turns off the periodic
timer. This register can be read or written at any time.
PTP — Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by 512
The reset state of PTP is the complement of the state of the MODCLK signal at the rising edge of
RESET.
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PITM[7:0] — Periodic Interrupt Timer Modulus
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
4(PITM[7:0])(Prescaler)
PIT Period = ----------------------------------------------------------------
fref
where
PIT Period = Periodic interrupt timer period
PITM[7:0] = Periodic interrupt timer modulus
f
= Synthesizer reference of external clock input frequency
ref
Prescaler = 1 if PTP = 0 or 512 if PTP = 1
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices. The external bus has 24 address lines and 16 data lines. Because the CPU16 in the
MC68HC16S2 drives only 20 of the 24 IMB address lines, ADDR[23:20] follow the output state of
ADDR19.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the size
(SIZ1 and SIZ0) and data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be
required for dynamically sized transfer.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchro-
nized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.6 Chip-Selects for more information.
3.5.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals
FC[2:0]. The size signals indicate the number of bytes remaining to be transferred during an operand
cycle. They are valid while the address strobe AS is asserted.
Table 13 shows SIZ0 and SIZ1 encoding. The read/write (R/W) signal determines the direction of the
transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle,
and is valid while AS is asserted. The R/W signal only changes state when a write cycle is preceded by
a read cycle or vice versa. The signal can remain low for two consecutive write cycles.
Table 13 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
Byte
0
1
1
0
1
0
1
0
Word
Three byte
Long word
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3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 14 displays CPU16 address space encodings.
Table 14 CPU16 Address Space Encoding
FC2
1
FC1
0
FC0
0
Address Space
Reserved
1
0
1
Data space
1
1
0
Program space
CPU space
1
1
1
3.5.3 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted. Because the CPU16 in the MC68HC16S2 does not drive ADDR[23:20],
these lines follow the logic state of ADDR19.
3.5.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.5 Data Bus
Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer eight or 16 bits of data in one bus cycle. Dur-
ing a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle.
For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.5.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data size acknowledge signals DSACK1 and DSACK0.
During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data. During a write
cycle, the signals indicate that an external device has successfully stored data and that the cycle can
end. These signals also indicate to the MCU the size of the port for the bus cycle just completed. Alter-
nately, chip-selects can be used to generate DSACK1 and DSACK0 internally. Refer to 3.5.8 Dynamic
Bus Sizing for more information.
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The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal-to-external transfers. When BERR and HALT are assert-
ed simultaneously, the CPU takes a bus error exception.
The autovector signal (AVEC) can terminate IRQ pin interrupt acknowledge cycles. AVEC indicates that
the MCU will internally generate a vector number to locate an interrupt handler routine. If it is continu-
ously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored during
all other bus cycles.
3.5.8 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK1
and DSACK0 inputs, as shown in Table 15.
Table 15 Effect of DSACK Signals
DSACK1
DSACK0
Result
1
1
0
0
1
0
1
0
Insert wait states in current bus cycle
Complete cycle — Data bus port size is 8 bits
Complete cycle — Data bus port size is 16 bits
Reserved
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-
ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-
nated as shown in Figure 10. OP0 is the most significant byte of a long-word operand, and OP3 is the
least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The
single byte of a byte-length operand is OP0.
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OPERAND
BYTE ORDER
31
24 23
16 15
8 7
0
LONG WORD
THREE BYTE
WORD
OP0
OP1
OP0
OP2
OP1
OP0
OP3
OP2
OP1
OP0
BYTE
OPERAND BYTE ORDER
Figure 10 Operand Byte Order
3.5.9 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-
sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-
ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1]
indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base. Bear in mind the fact that ADDR[23:20] follow the state of ADDR19 in the
MC68HC16S2.
3.5.10 Misaligned Operands
CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-
dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address.
The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU
transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the
first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible with
the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word trans-
fers.
3.5.11 Operand Transfer Cases
Table 16 summarizes how operands are aligned for various types of transfers. OPn entries are portions
of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and
ADDR0 for that bus cycle.
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Table 16 Operand Alignment
Current
Cycle
Transfer Case
SIZ1 SIZ0 ADDR0 DSACK1 DSACK0 DATA
[15:8]
DATA
[7:0]
Next
Cycle
1
1
2
3
4
5
Byte to 8-bit port (even)
Byte to 8-bit port (odd)
Byte to 16-bit port (even)
Byte to 16-bit port (odd)
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
OP0
OP0
OP0
(OP0)
OP0
(OP0)
(OP0)
(OP0)
OP0
—
—
—
—
2
Word to 8-bit port
(aligned)
(OP1)
6
7
Word to 8-bit port
(misaligned
1
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
OP0
OP0
(OP0)
OP1
1
—
3
Word to 16-bit port
(aligned)
8
Word to 16-bit port
(misaligned)
(OP0)
OP0
OP0
9
Long word to 8-bit port
(aligned)
(OP1)
(OP0)
OP1
13
1
10
11
12
Long word to 8-bit port
OP0
2
(misaligned)
Long word to 16-bit port
(aligned)
OP0
7
Long word to 16-bit port
(OP0)
OP0
3
2
(misaligned)
3
13
Three byte to 8-bit port
1
1
1
1
0
OP0
(OP0)
5
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.
3.6 Chip-Selects
Typical microcontrollers require additional hardware to provide external chip-select and address de-
code signals. The MC68HC16S2 includes 12 programmable chip-selects that can provide 2- to 16-
clock-cycle access to external memory and peripherals. Address block sizes of two Kbytes to one Mbyte
can be selected. However, because ADDR[23:20] = ADDR19 in the CPU16, 512 Kbyte blocks are the
largest usable size. Figure 11 is a functional diagram of a chip-select circuit.
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobe, or interrupt acknowledge signals. Chip-select logic can also generate DSACK and AVEC signals
internally. Each signal can also be synchronized with the ECLK signal available on ADDR23.
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INTERNAL
SIGNALS
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
TIMING
ADDRESS
AND
CONTROL
PIN
OPTION COMPARE
BUS CONTROL
OPTION REGISTER
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
AVEC
GENERATOR
DSACK
GENERATOR
AVEC
DSACK
CHIP-SEL BLOCK
Figure 11 Chip-Select Circuit Block Diagram
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. If a chip-select function is given the same address as a microcontroller module or
an internal memory array, an access to that address goes to the module or array, and the chip-select
signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits except CSBOOT are disabled out of reset. Chip-select option registers must not
be written until base addresses have been written to the proper base address registers. Alternate func-
tions for chip-select pins are enabled if appropriate data bus pins are held low at the release of RESET.
Table 17 lists allocation of chip-selects and discrete outputs on the pins of the MCU.
Table 17 Chip-Select and Discrete Output Allocation
Pin
CSBOOT
BR
Chip-Select
CSBOOT
CS0
Discrete Outputs
—
—
BG
CS1
—
BGACK
FC0
CS2
—
CS3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
—
FC1
CS4
FC2
CS5
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
CS6
CS7
CS8
CS9
CS10
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3.6.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment registers CSPAR[0:1]
determine functions of the pins. Pin assignment registers also determine port size for dynamic bus al-
location. A pin data register (PORTC) latches data for chip-select pins that are used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two Kbytes to one Mbyte
can be selected by writing values to the appropriate base address registers CSBARBT and
CSBAR[0:10]. However, because the logic state of ADDR20 is always the same as the state of ADDR19
in the MC68HC16S2, the largest usable block size is 512 Kbytes. Multiple chip-selects assigned to the
same block of addresses must have the same number of wait states.
Chip-select option registers CSORBT and CSOR[0:10] determine timing of and conditions for assertion
of chip-select signals. Eight parameters, including operating mode, access size, synchronization, and
wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the chip-select cir-
cuits. CSBOOT and registers CSORBT and CSBARBT are provided to support bootstrap operation.
3.6.2 Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields that determine functions of the chip-select pins.
Each pin has two or three possible functions, as shown in Table 18.
Table 18 Chip-Select Pin Functions
Assignment
Register
16-Bit
Chip-Select
Alternate
Function
Discrete
Output
CSPAR0
CSBOOT
CS0
CSBOOT
BR
—
—
CS1
BG
—
CS2
BGACK
FC0
—
CS3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
CS4
FC1
CS5
FC2
CSPAR1
CS6
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
CS7
CS8
CS9
CS10
Table 19 shows pin assignment field encoding. Pins that have no discrete output function do not use
the %00 encoding.
Table 19 Pin Assignment Encodings
Bit Field
Description
Discrete output
00
01
10
11
Alternate function
Chip-select (8-bit port)
Chip-select (16-bit port)
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CSPAR0 — Chip-Select Pin Assignment Register 0
$YFFA44
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CS5PA[1:0]
CS4PA[1:0]
CS3PA[1:0]
CS2PA[1:0]
CS1PA[1:0]
CS0PA[1:0]
CSBTPA[1:0]
RESET:
0
0
DATA2
1
DATA2
1
DATA2
1
DATA1
1
DATA1
1
DATA1
1
1
DATA0
CSPAR0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always
reads one; writes to CSPAR0 bit 1 have no effect. Table 20 shows CSPAR0 pin assignments.
Table 20 CSPAR0 Pin Assignments
CSPAR0 Field
CS5PA[1:0]
CS4PA[1:0]
CS3PA[1:0]
CS2PA[1:0]
CS1PA[1:0]
CS0PA[1:0]
CSBTPA[1:0]
Chip-Select Signal
Alternate Signal
Discrete Output
CS5
CS4
FC2
FC1
FC0
BGACK
BG
PC2
PC1
PC0
—
CS3
CS2
CS1
—
CS0
BR
—
CSBOOT
—
—
CSPAR1 — Chip-Select Pin Assignment Register 1
$YFFA46
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
CS10PA[1:0]
CS9PA[1:0]
CS8PA[1:0]
CS7PA[1:0]
CS6PA[1:0]
RESET:
1
0
0
0
0
0
0
DATA7
1
DATA
[7:6]
1
DATA
[7:5]
1
DATA
[7:4]
1
DATA
[7:3]
1
1
1
1
1
NOTES:
1. Refer to Table 21 for CSPAR1 reset state information.
The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are initially configured as
high-order address lines or chip-selects. Table 21 shows the correspondence between DATA[7:3] and
the reset configuration of CS[10:6]/ADDR[23:19].
Table 21 Reset Pin Function of CS[10:6]
Data Bus Pins at Reset
Chip-Select/Address Bus Pin Function
CS10/ CS9/ CS8/ CS7/ CS8/
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
DATA7 DATA6 DATA5 DATA4 DATA3
1
1
1
1
1
0
1
1
1
1
0
X
1
1
1
0
X
X
1
1
1
0
CS10
CS10
CS10
CS10
CS9
CS9
CS9
CS9
CS8
CS8
CS8
CS7
CS7
CS6
ADDR19
0
X
X
X
X
ADDR20 ADDR19
X
X
X
ADDR21 ADDR20 ADDR19
CS10 ADDR22 ADDR21 ADDR20 ADDR19
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
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CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR1[15:10] are not used. These bits always read zero; writes have no effect. Table 22 shows
CSPAR1 pin assignments.
Table 22 CSPAR1 Pin Assignments
CSPAR1 Field Chip-Select Signal
Alternate Signal
ADDR23
Discrete Output
CS10PA[1:0]
CS9PA[1:0]
CS8PA[1:0]
CS7PA[1:0]
CS6PA[1:0]
CS10
CS9
CS8
CS7
CS6
ECLK
PC6
PC5
PC4
PC3
ADDR22
ADDR21
ADDR20
ADDR19
Port size determines the way in which bus transfers to external addresses are allocated. Port size of
eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. Port size and transfer
size affect how the chip-select signal is asserted. Refer to 3.6.4 Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin.
These pins have weak internal pull-up drivers, but can be held low by external devices. Either 16-bit
chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the
boot ROM chip-select pin (CSBOOT) are disabled out of reset.
The CSBOOT signal is enabled out of reset. The state of the DATA0 line during reset determines what
port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver or by an ex-
ternal pull-up device), 16-bit port size is selected. If DATA0 is held low, 8-bit port size is selected.
A pin programmed as a discrete output drives an external signal to the value specified in the pin data
register. No discrete output function is available on pins CSBOOT, BR, BG, or BGACK. ADDR23 pro-
vides ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still func-
tions and can be used to generate DSACK or AVEC internally on an address and control signal match.
3.6.3 Base Address Registers
Each chip-select has an associated base address register. A base address is the lowest address in the
block of addresses enabled by a chip-select. Block size is the extent of the address block above the
base address. Block size is determined by the value contained in the BLKSZ field. Multiple chip-selects
may be assigned to the same block of addresses so long as each chip-select uses the same number
of wait states.
The BLKSZ field determines which bits in the base address field are compared to corresponding bits on
the address bus during an access. Provided other constraints determined by option register fields are
also satisfied, when a match occurs, the associated chip-select signal is asserted.
After reset, the MCU fetches the address of the first instruction to be executed from the reset vector,
located beginning at address $000000 in program space. To support bootstrap operation from reset,
the base address field in CSBARBT has a reset value of all zeros. A memory device containing the reset
vector and an initialization routine can be automatically enabled by CSBOOT after a reset. The block
size field in CSBARBT has a reset value of 512 Kbytes.
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CSBARBT — Chip-Select Base Address Register Boot ROM
$YFFA48
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
23
BLKSZ[2:0]
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
RESET:
0
1
1
CSBAR[0:10] — Chip-Select Base Address Registers
$YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
BLKSZ[2:0]
23*
22*
21*
20*
19
18
17
16
15
14
13
12
11
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*ADDR[23:20] follow the state of ADDR19 in the MC68HC16S2. ADDR[23:20] must match ADDR19 in
the base address register for the chip select to be active.
ADDR[23:11] — Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be an
integer multiple of the block size.
NOTE
Because ADDR[23:20] = ADDR19 in the CPU16, maximum block size is 512
Kbytes. For this same reason, addresses from $080000 to $F7FFFF are inacces-
sible. Blocks can be based above this dead zone, but the effect of ADDR19 must
be considered.
BLKSZ[2:0] — Block Size Field
This field determines the size of the block that must be enabled by the chip-select. Table 23 shows bit
encoding for the base address registers block size field.
Table 23 Block Size Field Bit Encoding
BLKSZ[2:0]
000
Block Size
2 Kbyte
Address Lines Compared
ADDR[23:11]
001
8 Kbyte
ADDR[23:13]
010
16 Kbyte
64 Kbyte
128 Kbyte
256 Kbyte
512 Kbyte
512 Kbyte
ADDR[23:14]
011
ADDR[23:16]
100
ADDR[23:17]
101
ADDR[23:18]
110
ADDR[23:19]
111
ADDR[23:20]
ADDR[23:20] are at the same logic level as ADDR19 during normal operation.
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3.6.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip-
select signals. To assert a chip-select signal, and to provide DSACK or autovector support, other con-
straints set by fields in the option register and in the base address register must also be satisfied.
CSORBT — Chip-Select Option Register Boot ROM
$YFFA4A
15
14
13
1
12
11
1
10
9
1
8
7
6
1
5
4
3
0
2
1
0
0
MODE
BYTE[1:0]
R/W[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
1
1
0
1
0
1
1
0
0
CSOR[0:10] — Chip-Select Option Registers
$YFFA4E–YFFA76
15
14
13
12
11
10
9
8
7
6
0
5
4
3
0
2
1
0
MODE
BYTE[1:0]
R/W[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tion from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[0:10] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode (chip-select assertion determined by bus control signals)
1 = Synchronous mode (chip-select assertion synchronized with ECLK signal)
In asynchronous mode, the chip-select is asserted synchronized with AS or DS.
DSACK[3:0] is not used in synchronous mode because a bus cycle is only performed as a synchronous
operation. When a match condition occurs on a chip-select programmed for synchronous operation, the
chip-select signals the EBI that an ECLK cycle is pending.
BYTE[1:0] — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
Table 24 lists upper/lower byte options.
Table 24 Upper/Lower Byte Options
BYTE[1:0]
Description
Disable
00
01
10
11
Lower byte
Upper byte
Both bytes
R/W[1:0] — Read/Write
This field causes a chip-select to be asserted only for reads, only for writes, or for both reads and writes.
Refer to Table 25 for options available.
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Table 25 R/W Encodings
R/W[1:0]
Description
Reserved
00
01
10
11
Read only
Write only
Read/Write
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip-select in asynchronous mode. Selecting address
strobe causes chip-select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip-select to be asserted synchronized with data strobe.
DSACK[3:0] — Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. Table 26 shows the DSACK[3:0] encoding. The fast termi-
nation encoding (%1110) is used for two-cycle access to external memory.
Table 26 DSACK Field Encoding
DSACK[3:0]
Clock Cycles Required
Per Access
Wait States
Per Access
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3
4
0 Wait states
1 Wait state
5
2 Wait states
3 Wait states
4 Wait states
5 Wait states
6 Wait states
7 Wait states
8 Wait states
9 Wait states
10 Wait states
11 Wait states
12 Wait states
13 Wait states
Fast termination
External DSACK
6
7
8
9
10
11
12
13
14
15
16
2
—
SPACE[1:0] — Address Space
Use this option field to select an address space for the chip-select logic. The CPU16 normally operates
in supervisor space, but interrupt acknowledge cycles must take place in CPU space. Table 27 shows
address space bit encodings.
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Table 27 Address Space Bit Encodings
SPACE[1:0]
Address Space
CPU space
00
01
10
11
User space
Supervisor space
Supervisor/User space
IPL[2:0] — Interrupt Priority Level
If the space field is set for CPU space, chip-select logic can be used for interrupt acknowledge. During
an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the value
in the IPL field. If the values are the same, a chip-select is asserted, provided that other option register
conditions are met. Table 28 shows IPL field encoding.
Table 28 Interrupt Priority Level Field Encoding
IPL[2:0]
000
Interrupt Priority Level
Any level
001
1
2
3
4
5
6
7
010
011
100
101
110
111
This field only affects the response of chip-selects and does not affect interrupt recognition by the CPU.
Any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle.
AVEC — Autovector Enable
0 = External interrupt vector enabled
1 = Autovector enabled
This field selects one of two methods of acquiring an interrupt vector number during an external interrupt
acknowledge cycle.
If the chip-select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and
the AVEC field is set to one, the chip-select circuit generates an internal AVEC signal in response to an
external interrupt cycle, and the SIM supplies an automatic vector number. Otherwise, the vector num-
ber must be supplied by the requesting device. An internal autovector is generated only in response to
interrupt requests from the SIM IRQ pins. Interrupt requests from other IMB modules are ignored.
The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because
of ECLK synchronization.
3.6.5 Port C Data Register
Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is as-
signed as a discrete output, the value in this register appears at the output. This is a read/write register.
Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.
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PORTC — Port C Data Register
$YFFA41
15
14
13
12
11
10
9
8
7
0
6
5
4
3
2
1
0
NOT USED
PC6
PC5
PC4
PC3
PC2
PC1
1
PC0
RESET:
0
1
1
1
1
1
1
3.7 General-Purpose Input/Output
SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de-
scribe registers that control the ports.
PORTE0, PORTE1 — Port E Data Register
$YFFA11, YFFA13
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
U
U
U
U
U
U
U
U
A write to the port E data register is stored in the internal data latch and, if any port E pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port E data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port E data register is a single register that can be accessed in two locations. When accessed at
$YFFA11, the register is referred to as PORTE0; when accessed at $YFFA13, the register is referred
to as PORTE1. The register can be read or written at any time. It is unaffected by reset.
DDRE — Port E Data Direction Register
$YFFA15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
RESET:
0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time.
PEPAR — Port E Pin Assignment
$YFFA17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
RESET:
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
The bits in this register control the function of each port E pin. Any bit set to one configures the corre-
sponding pin as a bus control signal, with the function shown in Table 29. Any bit cleared to zero defines
the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero
during reset, this register is set to $00, configuring all port E pins as I/O pins.
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Table 29 Port E Pin Assignments
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
Port E Signal
PE7
Bus Control Signal
SIZ1
SIZ0
PE6
PE5
AS
PE4
DS
PE3
—
PE2
AVEC
DSACK1
DSACK0
PE1
PE0
PORTF0, PORTF1 — Port F Data Register
$YFFA19, YFFA1B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
U
U
U
U
U
U
U
A write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven onto the pin. A read of the port F data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port F data register is a single register that can be accessed in two locations. When accessed at
$YFFA19, the register is referred to as PORTF0; when accessed at $YFFA1B, the register is referred
to as PORTF1. The register can be read or written at any time. It is unaffected by reset.
DDRF — Port F Data Direction Register
$YFFA1D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
RESET:
0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time.
PFPAR — Port F Pin Assignment Register
$YFFA1F
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0
RESET:
DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9
The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corre-
sponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request
signal or MODCLK. The MODCLK signal has no function after reset. Table 30 shows port F pin assign-
ments.
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Table 30 Port F Pin Assignments
PFPAR Field
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
Port F Signal
PF7
Alternate Signal
IRQ7
PF6
IRQ6
PF5
IRQ5
PF4
IRQ4
PF3
IRQ3
PF2
IRQ2
PF1
IRQ1
PF0
MODCLK
Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to
zero during reset, this register is set to $00, defining all port F pins as I/O pins.
3.8 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The SIM determines whether a reset is valid,
asserts control signals, performs basic system configuration based on hardware mode-select inputs,
then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
3.8.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines
what happens during subsequent breakpoint assertions. Table 31 is a summary of reset mode selection
options.
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Table 31 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
DATA1
CSBOOT 16-Bit
CSBOOT 8-Bit
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
ADDR19
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK[1:0]
AVEC, DS, AS
SIZ[1:0]
PORTE
DATA9
IRQ[7:1]
PORTF
MODCLK
DATA11
MODCLK
BKPT
Test mode disabled
VCO = System clock
Test mode enabled
EXTAL = System clock
Background mode enabled
Background mode disabled
Data lines have weak internal pull-up drivers. External bus loading can overcome the weak internal pull-
up drivers on data bus lines, and hold pins low during reset. Use an active device to hold data bus lines
low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent
conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is
released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven
lines may be required.
3.8.2 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIM default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sec-
tions in this manual for more information. Table 32 is a summary of module pin function out of reset.
Table 32 Module Pin Functions
Module
Pin Mnemonic
DSI/IPIPE1
Function
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
CPU16
DSO/IPIPE0
BKPT/DSCLK
3.8.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor timeout period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
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When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts the reset signal, the reset control logic asserts RESET for a minimum of
512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to
assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance state for ten cycles.
At the end of this 10-cycle period, the RESET pin is tested. When the input is at logic level one, reset
exception processing begins. If, however, the RESET pin is at logic level zero, the reset control logic
drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance
state for ten cycles, then it is tested again. The process repeats until RESET is released.
3.8.4 Power-On Reset
When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin V
in order for the MCU to
DDSYN
operate. The following discussion assumes that V
is applied before and during reset. This mini-
DDSYN
mizes crystal start-up time. When V
is applied at power-on, start-up time is affected by specific
DDSYN
crystal parameters and by oscillator circuit design. V ramp-up time also affects pin state during reset.
DD
During power-on reset, an internal circuit in the SIM drives the IMB and external reset lines. The circuit
releases the internal reset line as V ramps up to the minimum specified value, and SIM pins are ini-
DD
tialized. As V reaches a specified minimum value, the clock synthesizer VCO begins operation and
DD
clock frequency ramps up to specified limp mode frequency. The external RESET line remains asserted
until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. V ramp time and
DD
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-
ers or isolation resistors to prevent conflict.
3.8.5 Use of Three-State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for ten clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-on reset:
• When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the ten cycles take. Worst case is approximately 20 ms from TSC asser-
tion.
• When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
• When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent
mode selection. Once the output drivers change state, the MCU must be powered down and re-
started before normal operation can resume.
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3.9 Interrupts
Interrupt recognition and servicing involve complex interaction between the CPU16, the SIM, and a de-
vice or module requesting interrupt service.
The CPU16 provides seven levels of interrupt priority (1–7), seven automatic interrupt vectors, and 200
assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the interrupt
priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous
expression.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally on the IMB, and
there are corresponding pins for external interrupt service requests. The CPU treats all interrupt re-
quests as though they come from internal modules — external interrupt requests are treated as interrupt
service requests from the SIM. Each of the interrupt request signals corresponds to an interrupt priority
level. IRQ1 has the lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask value. The inter-
rupt priority mask consists of three bits (IP[2:0]) in the CPU16 condition code register. Binary values
%000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than
or equal to the mask value from being recognized and processed. IRQ7, however, is always recognized,
even if the mask value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted until an interrupt
acknowledge cycle corresponding to that level is detected.
IRQ7 is transition-sensitive as well as level-sensitive: a level 7 interrupt is not detected unless a falling
edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A
non-maskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask
changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re-
quests are processed at instruction boundaries or when exception processing of higher-priority excep-
tions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made,
the CPU16 does not recognize the occurrence of the request. If simultaneous interrupt requests of dif-
ferent priorities are made, and both have a priority greater than the mask value, the CPU16 recognizes
the higher-level request.
3.9.1 Interrupt Acknowledge and Arbitration
When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority
mask value, it places the interrupt request level on the address bus and initiates a CPU space read cy-
cle. The request level serves two purposes: it is decoded by modules or external devices that have re-
quested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to
them, and it is latched into the IP mask field in the CPU16 condition code register, to preclude further
interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the interrupt priority
mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority
of the service request corresponds to the mask value. However, before modules or external devices
respond, interrupt arbitration takes place.
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Arbitration is performed by means of serial contention between values stored in individual module inter-
rupt arbitration (IARB) fields. Each module that can request interrupt service, including the SIM, has an
IARB field in its configuration register. IARB fields can be assigned values from %0000 to %1111. In
order to implement an arbitration scheme, each module that can request interrupt service must be
assigned a unique, non-zero IARB field value during system initialization. Arbitration priorities range
from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an interrupt service request from a
source that has an IARB field value of %0000, a spurious interrupt exception is processed.
WARNING
Do not assign the same arbitration priority to more than one module. When two or
more IARB fields have the same non-zero value, the CPU16 interprets multiple
vector numbers at the same time, with unpredictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same priority, it always takes
place, even when a single source is requesting service. This is important for two reasons: the EBI does
not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention,
and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must terminate the bus
cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate in-
ternal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowl-
edge cycle is transferred to the external bus, the appropriate external device must decode the mask
value and respond with a vector number, then generate data and size acknowledge (DSACK) termina-
tion signals, or it must assert the autovector (AVEC) request signal. If the device does not respond in
time, the EBI bus monitor asserts the bus error signal (BERR), and a spurious interrupt exception is
taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in response to interrupt
requests from external devices. Chip-select address match logic functions only after the EBI transfers
an interrupt acknowledge cycle to the external bus following IARB contention. If a module makes an
interrupt request of a certain priority, and the appropriate chip-select registers are programmed to gen-
erate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-
select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a
vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQL field in the periodic interrupt control register (PICR) determines
PIT priority level. A PIRQL value of %000 means that PIT interrupts are inactive. By hardware conven-
tion, when the CPU16 receives simultaneous interrupt requests of the same level from more than one
SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed
by the IRQ pins. Refer to 3.4.6 Periodic Interrupt Timer for more information.
3.9.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. The processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
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1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3. The request level is latched from the address bus into the IP mask field in the condition
code register.
D. Modules or external peripherals that have requested interrupt service decode the priority value
on ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration by IARB
contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the following ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR,
and the CPU16 generates the spurious interrupt vector number.
2. The dominant interrupt source supplies a vector number and DSACK signals appropriate
to the access. The CPU16 acquires the vector number.
3. The internal AVEC signal is asserted by the dominant interrupt source and the CPU16 gen-
erates an autovector number corresponding to interrupt priority.
4. The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.10 Factory Test Block
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
SIMTR — System Integration Module Test Register
SIMTRE — System Integration Module Test Register (E Clock)
TSTMSRA — Master Shift Register A
$YFFA02
$YFFA08
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
TSTMSRB — Master Shift Register B
TSTSC — Test Module Shift Count
TSTRC — Test Module Repetition Count
CREG — Test Module Control Register
DREG — Test Module Distributed Register
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4 Central Processing Unit
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher
performance while maintaining maximum compatibility with existing systems.
4.1 Overview
The CPU16 instruction set is optimized for high performance. There are two 16-bit general-purpose ac-
cumulators and three 16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit
(long-word) load and store operations, as well as 16- and 32-bit signed fractional operations. Code de-
velopment is simplified by the background debugging mode.
CPU16 memory space includes a one Mbyte data space and a one Mbyte program space. Twenty-bit
addressing and transparent bank switching are used to implement extended memory. In addition, most
instructions automatically handle bank boundaries.
The CPU16 includes instructions and hardware to implement control-oriented digital signal processing
functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to mul-
tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu-
mulator. Modulo addressing supports finite impulse response filters.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. These languages make rapid development of portable software possible. The
CPU16 instruction set supports high-level languages.
4.2 M68HC11 Compatibility
The CPU16 architecture is a superset of the M68HC11 CPU architecture. All M68HC11 CPU resources
are available in the CPU16. M68HC11 CPU instructions are either directly implemented in the CPU16,
or have been replaced by instructions with an equivalent form. The instruction sets are source code
compatible, but some instructions are executed differently in the CPU16. These instructions are mainly
related to interrupt and exception processing — M68HC11 CPU code that processes interrupts, handles
stack frames, or manipulates the condition code register must be rewritten.
CPU16 execution times and number of cycles for all instructions are different from those of the
M68HC11 CPU. As a result, cycle-related delays and timed control routines may be affected.
The CPU16 also has several new or enhanced addressing modes. M68HC11 CPU direct mode ad-
dressing has been replaced by a special form of indexed addressing that uses the new IZ register and
a reset vector to provide greater flexibility.
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4.3 Programming Model
20
16 15
8 7
0 BIT POSITION
A
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
D
E
ACCUMULATOR E
INDEX REGISTER X
INDEX REGISTER Y
INDEX REGISTER Z
STACK POINTER
XK
YK
ZK
SK
PK
IX
IY
IZ
SP
PC
PROGRAM COUNTER
CCR
XK
PK
CONDITION CODE REGISTER
PC EXTENSION REGISTER
EK
YK
ZK
SK
ADDRESS EXTENSION REGISTER
STACK EXTENSION REGISTER
MAC MULTIPLIER REGISTER
MAC MULTIPLICAND REGISTER
HR
IR
35
16
AM (MSB)
AM (LSB)
MAC ACCUMULATORMSB [35:16]
MAC ACCUMULATOR LSB [15:0]
XMSK
YMSK
MAC XY MASK REGISTER
Accumulator A — 8-bit general-purpose register
Accumulator B — 8-bit general-purpose register
Accumulator D — 16-bit general-purpose register formed by concatenating accumulators A and B
Accumulator E — 16-bit general-purpose register
Index Register X — 16-bit indexing register, addressing extended by XK field in K register
Index Register Y — 16-bit indexing register, addressing extended by YK field in K register
Index Register Z — 16-bit indexing register, addressing extended by ZK field in K register
Stack Pointer — 16-bit dedicated register, addressing extended by the SK register
Program Counter — 16-bit dedicated register, addressing extended by PK field in CCR
Condition Code Register — 16-bit register containing condition flags, interrupt priority mask, and
the program counter address extension field
K Register — 16-bit register made up of four 4-bit address extension fields
SK Register — 4-bit register containing the stack pointer address extension field
H Register — 16-bit multiply and accumulate input (multiplier) register
I Register — 16-bit multiply and accumulate input (multiplicand) register
MAC Accumulator — 36-bit multiply and accumulate result register
XMSK, YMSK — Determine which bits change when an offset is added
Figure 12 CPU16 Programming Model
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4.3.1 Condition Code Register
15
S
14
13
H
12
11
N
10
Z
9
8
7
6
5
4
3
2
1
0
MV
EV
V
C
IP[2:0]
SM
PK[3:0]
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed
1 = Perform NOP when LPSTOP instruction is executed
MV — Accumulator M overflow flag
MV is set when an overflow into AM35 has occurred.
H — Half Carry Flag
H is set when a carry from A3 or B3 occurs during BCD addition.
EV — Extension Bit Overflow Flag
EV is set when an overflow into AM31 has occurred.
N — Negative Flag
N is set when the MSB of a result register is set.
Z — Zero Flag
Z is set when all bits of a result register are zero.
V — Overflow Flag
V is set when a two’s complement overflow occurs as the result of an operation.
C — Carry Flag
C is set when a carry or borrow occurs during an arithmetic operation. This flag is also used during shift
and rotate to facilitate multiple word operations.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask interrupts.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is given maximum
positive or negative value, depending on the state of the AM sign bit before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit address.
4.4 Data Types
The CPU16 supports the following data types:
• Bit data
• 8-bit (byte) and 16-bit (word) integers
• 32-bit long integers
• 16-bit and 32-bit signed fractions (MAC operations only)
• 20-bit effective address consisting of 16-bit page address plus 4-bit extension
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consec-
utive bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word bound-
aries. Word operands are normally accessed on word boundaries as well, but can be accessed on odd
byte boundaries, with a substantial performance penalty.
To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are al-
lowed. Transferring a misaligned word requires two successive byte operations.
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4.5 Addressing Modes
The CPU16 provides ten types of addressing. Each type encompasses one or more addressing modes.
Six CPU16 addressing types are identical to M68HC11 addressing types.
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension field
to form a 20-bit effective address. Extension fields are part of a bank switching scheme that provides
the CPU16 with a one Mbyte address space. Bank switching is transparent to most instructions. AD-
DR[19:16] of the effective address change when an access crosses a bank boundary. However, it is
important to note that the value of the associated extension field is dependent on the type of instruction,
and usually does not change as a result of effective address calculation.
In the immediate modes, the instruction argument is contained in bytes or words immediately following
the instruction. The effective address is the address of the byte following the instruction. The AIS, AIX/
Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate value is an 8-bit
signed number that is sign-extended to 16 bits, and then added to the appropriate register. Use of the
extended 8-bit mode decreases execution time.
Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective ad-
dress is formed by concatenating EK and the 16-bit extension.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used
to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions to the
M68HC11 indexed addressing mode.
For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value con-
tained in the index register and its associated extension field.
For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained in
the index register and its associated extension field.
For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This mode
is used for JMP and JSR instructions.
Inherent mode instructions use information available to the processor to determine the effective ad-
dress. Operands (if any) are system resources and are thus not fetched from memory.
Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers and its
associated extension field to form the effective address. This mode allows use of index registers and
an accumulator within loops without corrupting accumulator D.
Relative modes are used for branch and long branch instructions. A byte or word signed two's comple-
ment offset is added to the program counter if the branch condition is satisfied. The new PC value, con-
catenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is add-
ed to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into
page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To
compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset ini-
tialization vectors. By resetting the ZK field to a chosen page, and using 8-bit unsigned index mode with
IZ, a programmer can access useful data structures anywhere in the address map.
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4.6 Instruction Set
The CPU16 instruction set is based on that of the M68HC11, but the opcode map has been rearranged
to maximize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16,
although they may be executed differently. Most M68HC11 code runs on the CPU16 following reassem-
bly. However, take into account changed instruction times, the interrupt mask, and the new interrupt
stack frame.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned
multiplication and division. New instructions have been added to support extended addressing and dig-
ital signal processing.
Table 33 is a quick reference to the entire CPU16 instruction set. Because it is only affected by a few
instructions, the LSB of the condition code register is not shown in the table. Instructions that affect the
interrupt mask and PK field are noted. Table 34 provides a key to the table nomenclature.
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Table 33 Instruction Set Summary
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
INH
INH
INH
INH
Opcode Operand Cycles
S
—
—
—
—
—
—
—
MV
—
—
—
—
∆
H
∆
EV
—
—
—
—
∆
N
∆
Z
∆
V
∆
C
∆
ABA
ABX
ABY
ABZ
ACE
Add B to A
Add B to IX
Add B to IY
(A ) + (B)
A
370B
374F
375F
376F
3722
3723
43
—
—
—
—
—
2
2
2
2
2
4
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
(XK : IX) + (000 : B) XK : IX
(YK : IY) + (000 : B) YK : IY
(ZK : IZ) + (000 : B) ZK : IZ
(AM[31:16]) + (E)
(AM) + (E : D)
(A) + (M) + C
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
—
—
—
∆
Add B to IZ
Add E to AM
Add E : D to AM
Add with Carry to A
AM
AM
A
INH
INH
ACED
ADCA
—
ff
∆
∆
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
—
—
53
ff
63
ff
73
ii
1743
1753
1763
1773
2743
2753
2763
C3
gggg
gggg
gggg
hh ll
—
—
—
ff
E, X
E, Y
E, Z
ADCB
Add with Carry to B
(B) + (M) + C
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
—
—
∆
—
∆
∆
∆
∆
D3
ff
E3
ff
F3
ii
17C3
17D3
17E3
17F3
27C3
27D3
27E3
83
gggg
gggg
gggg
hh ll
—
—
—
ff
E, X
E, Y
E, Z
ADCD
Add with Carry to D
(D) + (M : M + 1) + C
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
∆
∆
∆
∆
93
ff
A3
ff
37B3
37C3
37D3
37E3
37F3
2783
2793
27A3
3733
3743
3753
3763
3773
41
jj kk
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
ADCE
ADDA
Add with Carry to E
(E) + (M : M + 1) + C
E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
jj kk
gggg
gggg
gggg
hh ll
ff
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Add to A
(A) + (M)
A
∆
51
ff
61
ff
71
ii
1741
1751
1761
1771
2741
2751
2761
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ADDB
Add to B
(B) + (M)
B
C1
D1
ff
ff
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
4
6
6
6
6
6
6
6
2
4
6
6
6
6
2
2
—
—
∆
—
∆
∆
∆
∆
E1
ff
F1
ii
17C1
17D1
17E1
17F1
27C1
27D1
27E1
81
gggg
gggg
gggg
hh ll
—
—
—
ff
E, X
E, Y
E, Z
ADDD
Add to D
(D) + (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM8
—
—
—
—
∆
∆
∆
∆
91
ff
A1
ff
FC
ii
37B1
37C1
37D1
37E1
37F1
2781
2791
27A1
7C
jj kk
gggg
gggg
gggg
hh ll
—
—
—
ii
ADDE
Add to E
(E) + (M : M + 1)
E
—
—
—
—
∆
∆
∆
∆
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3731
3741
3751
3761
3771
2778
37CD
jj kk
gggg
gggg
gggg
hh ll
—
ADE
ADX
Add D to E
Add D to IX
(E) + (D)
E
INH
INH
—
—
—
—
—
—
—
—
∆
—
∆
—
∆
—
∆
—
—
(XK : IX) + (20 « D)
XK : IX
ADY
ADZ
AEX
AEY
AEZ
Add D to IY
Add D to IZ
Add E to IX
Add E to IY
Add E to IZ
INH
INH
INH
INH
INH
37DD
37ED
374D
375D
376D
—
—
—
—
—
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(YK : IY) + (20 « D)
YK : IY
(ZK : IZ) + (20 « D)
ZK : IZ
(XK : IX) + (20 « D)
XK : IX
(YK : IY) + (20 « D)
YK : IY
(ZK : IZ) + (20 « D)
ZK : IZ
AIS
AIX
Add Immediate Data
to Stack Pointer
Add Immediate Value
to IX
Add Immediate Value
to IY
(SK : SP) + (20 « IMM)
SK : SP
(XK : IX) + (20 « IMM)
XK : IX
(YK : IY) + (20 « IMM)
YK : IY
(ZK : IZ) + (20 « IMM)
ZK : IZ
IMM8
IMM16
IMM8
IMM16
IMM8
3F
373F
3C
373C
3D
373D
3E
373E
46
56
66
76
1746
1756
1766
1776
2746
2756
2766
ii
jj kk
ii
jj kk
ii
jj kk
ii
jj kk
ff
2
4
2
4
2
4
2
4
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
—
∆
—
—
—
—
0
—
—
—
—
—
AIY
∆
IMM16
IMM8
AIZ
Add Immediate Value
to IZ
∆
IMM16
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
ANDA
AND A
(A) • (M)
A
∆
ff
ff
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MC68HC16S2
MC68HC16S2TS/D
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ANDB
AND B
(B) • (M)
B
C6
D6
E6
F6
17C6
17D6
17E6
17F6
27C6
27D6
27E6
86
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
4
—
—
—
—
∆
∆
0
—
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
E, X
E, Y
E, Z
ANDD
AND D
(D) • (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
∆
∆
0
—
96
A6
ff
37B6
37C6
37D6
37E6
37F6
2786
2796
27A6
3736
3746
3756
3766
3776
373A
jj kk
gggg
gggg
gggg
hh ll
—
—
—
ANDE
AND E
(E) • (M : M + 1)
E
jj kk
gggg
gggg
gggg
hh ll
jj kk
—
—
—
—
∆
∆
0
—
AND CCR
(CCR) • IMM16 CCR
IMM16
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
ANDP1
ASL
Arithmetic Shift Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
04
14
24
1704
1714
1724
1734
3704
ff
ff
ff
8
8
8
8
8
8
8
2
—
—
—
—
gggg
gggg
gggg
hh ll
—
ASLA
ASLB
ASLD
ASLE
ASLM
ASLW
Arithmetic Shift Left A
Arithmetic Shift Left B
Arithmetic Shift Left D
Arithmetic Shift Left E
INH
—
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
INH
INH
INH
INH
3714
27F4
2774
27B6
—
—
—
—
2
2
2
4
∆
∆
∆
∆
Arithmetic Shift Left
AM
—
∆
—
∆
Arithmetic Shift Left
Word
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
2704
2714
2724
2734
0D
gggg
gggg
gggg
hh ll
ff
8
8
8
8
8
8
8
8
8
8
8
2
—
—
ASR
Arithmetic Shift Right
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
1D
2D
ff
ff
170D
171D
172D
173D
370D
gggg
gggg
gggg
hh ll
—
ASRA
Arithmetic Shift Right
A
INH
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
ASRB
Arithmetic Shift Right
B
INH
371D
27FD
277D
27BA
—
—
—
—
2
2
2
4
—
—
—
—
∆
∆
∆
∆
ASRD
ASRE
ASRM
ASRW
Arithmetic Shift Right
D
INH
INH
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Arithmetic Shift Right
E
Arithmetic Shift Right
AM
—
∆
—
∆
Arithmetic Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270D
271D
272D
273D
B4
gggg
gggg
gggg
hh ll
rr
8
8
8
8
6, 2
—
Branch if Carry Clear
Clear Bit(s)
If C = 0, branch
REL8
—
—
—
—
—
—
—
—
—
—
—
0
—
—
BCC2
BCLR
(M) • (Mask)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
1708
1718
1728
08
18
28
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
8
8
8
8
8
8
8
10
∆
∆
38
2708
BCLRW
Clear Bit(s) in a Word
(M : M + 1) • (Mask)
IND16, X
—
—
—
—
∆
∆
0
—
M : M + 1
mmmm
gggg
mmmm
gggg
mmmm
hh ll
IND16, Y
IND16, Z
EXT
2718
2728
2738
10
10
10
mmmm
rr
BCS2
BEQ2
BGE2
Branch if Carry Set
Branch if Equal
If C = 1, branch
If Z = 1, branch
REL8
REL8
REL8
B5
B7
BC
6, 2
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
rr
rr
BranchifGreaterThan
or Equal to Zero
Enter Background
Debug Mode
If N V = 0, branch
BGND
If BDM enabled,
begin debug;
else, illegal instruction trap
INH
37A6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BGT2
BranchifGreaterThan If Z ✛ (N V) = 0, branch
Zero
Branch if Higher
REL8
REL8
BE
B2
rr
rr
6, 2
6, 2
BHI2
BITA
If C ✛ Z = 0, branch
(A) • (M)
—
—
—
—
—
—
—
—
—
—
—
0
—
—
Bit Test A
IND8, X
IND8, Y
IND8, Z
IMM8
49
59
69
ff
ff
ff
6
6
6
∆
∆
79
ii
2
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
1749
1759
1769
1779
2749
2759
2769
C9
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
6
6
6
6
6
6
6
6
E, Z
BITB
Bit Test B
(B) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
—
—
—
—
∆
∆
0
—
D9
E9
F9
6
6
2
ff
ii
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
17C9
17D9
17E9
17F9
27C9
27D9
27E9
BF
gggg
gggg
gggg
hh ll
—
—
—
rr
6
6
6
6
6
6
6
6, 2
E, Z
REL8
BLE2
Branch if Less Than or If Z ✛ (N V) = 1, branch
—
—
—
—
—
—
—
—
Equal to Zero
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
53
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
BLS2
BLT2
Branch if Lower or
Same
Branch if Less Than
Zero
If C ✛ Z = 1, branch
REL8
B3
rr
6, 2
—
—
—
—
—
—
—
—
If N V = 1, branch
REL8
BD
rr
6, 2
—
—
—
—
—
—
—
—
BMI2
BNE2
BPL2
Branch if Minus
If N = 1, branch
If Z = 0, branch
If N = 0, branch
REL8
REL8
REL8
BB
B6
BA
rr
rr
rr
6, 2
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Branch if Not Equal
Branch if Plus
BRA
BRCLR2
Branch Always
Branch if Bit(s) Clear
If 1 = 1, branch
If (M) • (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B0
CB
DB
EB
0A
rr
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
10, 12
10, 12
10, 12
10, 14
IND16, Y
IND16, Z
EXT
1A
2A
3A
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
10, 14
10, 14
10, 14
BRN
BRSET2
Branch Never
Branch if Bit(s) Set
If 1 = 0, branch
If (M) • (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B1
8B
9B
AB
0B
rr
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
10, 12
10, 12
10, 12
10, 14
IND16, Y
IND16, Z
EXT
1B
2B
3B
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
10, 14
10, 14
10, 14
BSET
Set Bit(s)
(M) ✛ (Mask)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
1709
1719
1729
09
19
29
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
8
8
8
8
8
8
8
10
—
—
—
—
—
—
—
—
∆
∆
∆
∆
0
0
∆
∆
39
2709
BSETW
Set Bit(s) in Word
(M : M + 1) ✛ (Mask)
IND16, X
M : M + 1
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
rr
IND16, Y
IND16, Z
EXT
2719
2729
2739
36
10
10
10
10
BSR
Branch to Subroutine
(PK : PC) - 2
PK : PC
SK : SP
REL8
—
—
—
—
—
—
—
—
Push (PC)
(SK : SP) - 2
Push (CCR)
(SK : SP) - 2
SK : SP
(PK : PC) + Offset PK : PC
BVC2
Branch if Overflow
Clear
Branch if Overflow Set
If V = 0, branch
REL8
REL8
B8
B9
rr
rr
6, 2
6, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BVS2
CBA
CLR
If V = 1, branch
Compare A to B
Clear a Byte in
Memory
(A) − (B)
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
371B
05
15
—
ff
ff
2
4
4
4
6
6
6
6
2
2
2
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
$00
M
0
1
0
0
25
ff
1705
1715
1725
1735
3705
3715
27F5
2775
gggg
gggg
gggg
hh ll
—
—
—
—
CLRA
CLRB
CLRD
CLRE
Clear A
Clear B
Clear D
Clear E
$00
$00
A
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
$0000
$0000
D
E
MOTOROLA
54
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
—
—
MV
0
—
H
—
—
EV
0
—
N
—
0
Z
—
1
V
—
0
C
—
0
CLRM
CLRW
Clear AM
Clear a Word in
Memory
$000000000
$0000
AM[35:0]
M : M + 1
27B7
2705
2715
2725
2735
48
—
gggg
gggg
gggg
hh ll
ff
2
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
8
8
8
8
8
8
8
2
2
2
2
8
8
8
8
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
CMPA
CMPB
COM
Compare A to Memory
Compare B to Memory
One’s Complement
(A) − (M)
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
∆
∆
1
58
ff
68
ff
78
ii
1748
1758
1768
1778
2748
2758
2768
C8
gggg
gggg
gggg
hh ll
—
—
—
ff
E, X
E, Y
E, Z
(B) − (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
D8
ff
E8
ff
F8
ii
17C8
17D8
17E8
17F8
27C8
27D8
27E8
00
gggg
gggg
gggg
hh ll
—
—
—
ff
M
$FF − (M)
M, or M
10
ff
20
ff
1700
1710
1720
1730
3700
3710
27F0
2770
2700
2710
2720
2730
88
gggg
gggg
gggg
hh ll
—
—
—
—
gggg
gggg
gggg
hh ll
ff
COMA
COMB
COMD
COME
COMW
One’s Complement A
One’s Complement B
One’s Complement D $FFFF − (D)
One’s Complement E $FFFF − (E)
One’s Complement
Word
$FF − (A)
$FF − (B)
A, or M
B, or B
D, or D
E, or E
A
B
INH
INH
INH
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
0
1
1
1
1
1
D
E
$FFFF − M : M + 1
M : M + 1, or (M : M + 1)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPD
Compare D to Memory
(D) − (M : M + 1)
—
—
—
—
∆
∆
∆
∆
98
ff
A8
ff
37B8
37C8
37D8
37E8
37F8
2788
2798
27A8
3738
3748
3758
3768
3778
4F
jj kk
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
CPE
CPS
Compare E to Memory
(E) − (M : M + 1)
(SP) − (M : M + 1)
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
jjkk
gggg
gggg
gggg
hhll
ff
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Compare Stack
Pointer to Memory
5F
ff
6F
ff
377F
174F
175F
176F
177F
jj kk
gggg
gggg
gggg
hh ll
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
55
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
∆
C
∆
CPX
Compare IX to
Memory
(IX) − (M : M + 1)
4C
5C
6C
377C
174C
175C
176C
177C
4D
ff
ff
ff
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
2
jj kk
gggg
gggg
gggg
hh ll
ff
CPY
Compare IY to
Memory
(IY) − (M : M + 1)
(IZ) − (M : M + 1)
(A)10
—
—
—
—
∆
∆
∆
∆
5D
6D
ff
ff
377D
174D
175D
176D
177D
4E
jj kk
gggg
gggg
gggg
hh ll
ff
CPZ
Compare IZ to
Memory
—
—
—
—
∆
∆
∆
∆
5E
6E
ff
ff
377E
174E
175E
176E
177E
3721
jj kk
gggg
gggg
gggg
hh ll
—
INH
—
—
—
—
—
—
—
—
∆
∆
∆
∆
U
∆
DAA
DEC
Decimal Adjust A
Decrement Memory
(M) − $01
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
01
11
ff
ff
8
8
∆
—
21
ff
8
1701
1711
1721
1731
3701
3711
2701
2711
2721
2731
3728
gggg
gggg
gggg
hh ll
—
8
8
8
8
2
2
8
8
DECA
DECB
DECW
Decrement A
Decrement B
Decrement Memory
Word
(A) − $01
(B) − $01
A
B
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
—
(M : M + 1) − $0001
M : M + 1
gggg
gggg
gggg
hh ll
—
8
8
24
EDIV
Extended Unsigned
Integer Divide
(E : D) / (IX)
INH
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
Quotient
IX
Remainder
D
EDIVS
Extended Signed
Integer Divide
(E : D) / (IX)
INH
3729
—
38
Quotient
Remainder
(E) (D)
IX
D
E : D
EMUL
EMULS
EORA
Extended Unsigned
Multiply
Extended Signed
Multiply
INH
INH
3725
3726
—
—
10
8
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
—
—
0
∆
∆
(E) (D)
E : D
A
Exclusive OR A
(A) (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
44
54
64
74
1744
1754
1764
1774
2744
2754
2764
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
—
ii
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MOTOROLA
56
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
EORB
Exclusive OR B
(B) (M)
B
C4
D4
E4
F4
17C4
17D4
17E4
17F4
27C4
27D4
27E4
84
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
22
—
—
—
—
∆
∆
0
—
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
E, X
E, Y
E, Z
EORD
Exclusive OR D
(D) (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
∆
∆
0
—
94
A4
ff
37B4
37C4
37D4
37E4
37F4
2784
2794
27A4
3734
3744
3754
3764
3774
372B
jj kk
gggg
gggg
gggg
hh ll
—
—
—
EORE
Exclusive OR E
(E) (M : M + 1)
E
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
—
∆
∆
0
—
FDIV
FMULS
IDIV
Fractional
Unsigned Divide
Fractional Signed
Multiply
(D) / (IX)
Remainder
IX
D
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
0
∆
∆
∆
(E) (D)
0
E : D[31:1]
D[0]
INH
INH
3727
372A
—
—
8
Integer Divide
(D) / (IX)
Remainder
(M) + $01
IX
D
M
22
—
∆
∆
INC
Increment Memory
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
03
13
ff
ff
8
8
—
23
ff
8
1703
1713
1723
1733
3703
3713
2703
2713
2723
2733
7A
4B
5B
6B
FA
89
99
A9
gggg
gggg
gggg
hh ll
—
—
gggg
gggg
gggg
hh ll
zb hh ll
zg gggg
zg gggg
zg gggg
zb hh ll
zg gggg
zg gggg
zg gggg
8
8
8
8
2
2
8
8
8
8
6
8
8
8
10
12
12
12
INCA
INCB
INCW
Increment A
Increment B
Increment Memory
Word
(A) + $01
(B) + $01
(M : M + 1) + $0001
M : M + 1
A
B
INH
INH
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
IND16, X
IND16, Y
IND16, Z
EXT
EXT20
IND20, X
IND20, Y
IND20, Z
EXT20
JMP
JSR
Jump
ea
PK : PC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Jump to Subroutine
Push (PC)
(SK : SP) − $0002 SK : SP IND20, X
Push (CCR) IND20, Y
(SK : SP) − $0002 SK : SP IND20, Z
ea PK : PC
LBCC2
LBCS2
LBEQ2
Long Branch if Carry
Clear
Long Branch if Carry
Set
Long Branch if Equal
to Zero
If C = 0, branch
If C = 1, branch
If Z = 1, branch
REL16
REL16
REL16
3784
3785
3787
rrrr
rrrr
rrrr
6, 4
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBEV2
LBGE2
Long Branch if EV Set
If EV = 1, branch
REL16
REL16
3791
378C
rrrr
rrrr
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Long Branch if Greater
Than or Equal to Zero
If N V = 0, branch
LBGT2
LBHI 2
Long Branch if Greater If Z ✛ (N V) = 0, branch
REL16
REL16
378E
3782
rrrr
rrrr
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Than Zero
Long Branch if Higher
If C ✛ Z = 0, branch
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
57
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
LBLE2
LBLS2
LBLT2
Long Branch if Less
Than or Equal to Zero
Long Branch if Lower
or Same
Long Branch if Less
Than Zero
If Z ✛ (N V) = 1, branch
If C ✛ Z = 1, branch
REL16
378F
3783
378D
rrrr
rrrr
rrrr
6, 4
6, 4
6, 4
—
—
—
—
—
—
—
—
REL16
REL16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
If N V = 1, branch
LBMI2
LBMV2
LBNE2
Long Branch if Minus
If N = 1, branch
If MV = 1, branch
If Z = 0, branch
REL16
REL16
REL16
378B
3790
3786
rrrr
rrrr
rrrr
6, 4
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Long Branch if MV Set
Long Branch if Not
Equal to Zero
LBPL2
LBRA
LBRN
LBSR
Long Branch if Plus
If N = 0, branch
REL16
378A
rrrr
6, 4
—
—
—
—
—
—
—
—
Long Branch Always
Long Branch Never
Long Branch to
Subroutine
If 1 = 1, branch
If 1 = 0, branch
Push (PC)
REL16
REL16
REL16
3780
3781
27F9
rrrr
rrrr
rrrr
6
6
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(SK : SP) − 2
SK : SP
Push (CCR)
(SK : SP) − 2
SK : SP
(PK : PC) + Offset
PK : PC
LBVC2
Long Branch if
Overflow Clear
Long Branch if
Overflow Set
Load A
If V = 0, branch
REL16
REL16
3788
3789
rrrr
rrrr
6, 4
6, 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
—
—
∆
—
—
0
—
—
—
LBVS2
LDAA
If V = 1, branch
(M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
45
55
65
75
1745
1755
1765
1775
2745
2755
2765
C5
ff
ff
ff
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
8
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
E, X
E, Y
E, Z
LDAB
LDD
LDE
Load B
Load D
Load E
(M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
0
0
0
∆
D5
E5
F5
ff
ii
17C5
17D5
17E5
17F5
27C5
27D5
27E5
85
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
E, X
E, Y
E, Z
(M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
95
A5
ff
37B5
37C5
37D5
37E5
37F5
2785
2795
27A5
3735
3745
3755
3765
3775
2771
jj kk
gggg
gggg
gggg
hh ll
—
—
—
(M : M + 1)
(M : M + 1)
E
E
jj kk
gggg
gggg
gggg
hh ll
hh ll
—
LDED
LDHI
Load Concatenated
E and D
Initialize H and I
EXT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(M + 2 : M + 3)
D
(M : M + 1)
H R
I R
EXT
27B0
—
8
X
(M : M + 1)
Y
MOTOROLA
58
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
0
C
—
LDS
Load SP
(M : M + 1) SP
CF
DF
ff
ff
6
6
EF
ff
6
17CF
17DF
17EF
17FF
37BF
CC
gggg
gggg
gggg
hh ll
jj kk
ff
6
6
6
6
4
6
IMM16
LDX
LDY
LDZ
Load IX
Load IY
Load IZ
(M : M + 1)
(M : M + 1)
(M : M + 1)
IX
IY
IZ
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
0
0
0
—
—
—
DC
ff
6
EC
ff
6
37BC
17CC
17DC
17EC
17FC
CD
jj kk
gggg
gggg
gggg
hh ll
ff
4
6
6
6
6
6
DD
ff
6
ED
ff
6
37BD
17CD
17DD
17ED
17FD
CE
jj kk
gggg
gggg
gggg
hh ll
ff
4
6
6
6
6
6
DE
ff
6
EE
ff
6
37BE
17CE
17DE
17EE
17FE
27F1
jj kk
gggg
gggg
gggg
hh ll
—
4
6
6
6
6
4, 20
INH
—
—
—
—
—
—
—
—
—
0
—
—
—
LPSTOP
LSR
Low Power Stop
If S
then STOP
else NOP
Logical Shift Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0F
1F
2F
170F
171F
172F
173F
370F
ff
ff
ff
8
8
8
8
8
8
8
2
∆
∆
∆
gggg
gggg
gggg
hh ll
—
LSRA
LSRB
LSRD
LSRE
LSRW
Logical Shift Right A
Logical Shift Right B
Logical Shift Right D
Logical Shift Right E
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
INH
INH
INH
371F
27FF
277F
—
—
—
2
2
2
Logical Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270F
271F
272F
273F
7B
gggg
gggg
gggg
hh ll
8
8
8
8
12
MAC
Multiply and
Accumulate
Signed 16-Bit
Fractions
(HR) (IR)
E : D
AM
IX
IMM8
xoyo
—
∆
—
∆
—
—
∆
—
(AM) + (E : D)
Qualified (IX)
Qualified (IY)
IY
(HR)
IZ
(M : M + 1)X
HR
IR
(M : M + 1)Y
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
59
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IXP to EXT
EXT to IXP
EXT to
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
0
C
—
MOVB
Move Byte
(M1)
M2
30
32
ff hh ll
ff hh ll
8
8
37FE
hh ll hh ll
10
EXT
MOVW
Move Word
(M : M + 11)
M : M + 12 IXP to EXT
31
33
37FF
ff hh ll
ff hh ll
hh ll hh ll
8
8
10
—
—
—
—
∆
∆
0
—
EXT to IXP
EXT to
EXT
MUL
NEG
Multiply
Negate Memory
(A) (B)
$00 − (M)
D
M
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
3724
02
12
—
ff
ff
10
8
8
8
8
8
8
8
2
2
2
2
8
8
8
8
2
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
4
—
—
—
—
—
—
—
—
—
∆
—
∆
—
∆
∆
∆
22
ff
1702
1712
1722
1732
3702
3712
27F2
2772
2702
2712
2722
2732
274C
47
gggg
gggg
gggg
hh ll
—
—
—
—
gggg
gggg
gggg
hh ll
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
NEGA
NEGB
NEGD
NEGE
NEGW
Negate A
Negate B
Negate D
$00 − (A)
$00 − (B)
$0000 − (D)
$0000 − (E)
$0000 − (M : M + 1)
M : M + 1
A
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
D
E
Negate E
Negate Memory Word
IND16, X
IND16, Y
IND16, Z
EXT
NOP
ORAA
Null Operation
OR A
—
INH
—
—
—
—
—
—
—
—
—
—
—
0
—
—
(A) ✛ (M)
A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
∆
∆
57
67
77
1747
1757
1767
1777
2747
2757
2767
C7
E, X
E, Y
E, Z
ORAB
ORD
ORE
OR B
OR D
OR E
(B) ✛ (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
0
0
0
—
—
—
D7
E7
F7
ff
ii
17C7
17D7
17E7
17F7
27C7
27D7
27E7
87
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
E, X
E, Y
E, Z
(D) ✛ (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
97
A7
ff
37B7
37C7
37D7
37E7
37F7
2787
2797
27A7
3737
3747
3757
3767
3777
373B
jj kk
gggg
gggg
gggg
hh ll
—
—
—
(E) ✛ (M : M + 1)
(CCR) ✛ IMM16
E
jj kk
gggg
gggg
gggg
hh ll
jj kk
ORP 1
PSHA
OR Condition Code
Register
CCR
IMM16
∆
∆
∆
∆
∆
∆
∆
∆
Push A
(SK : SP) + $0001 SK : SP
Push (A)
INH
3708
—
4
—
—
—
—
—
—
—
—
(SK : SP) − $0002 SK : SP
MOTOROLA
60
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
PSHB
Push B
(SK : SP) + $0001 SK : SP
Push (B)
INH
3718
—
4
—
—
—
—
—
—
—
—
(SK : SP) − $0002 SK : SP
For mask bits 0 to 7:
PSHM
Push Multiple
Registers
IMM8
34
ii
4 + 2N
—
—
—
—
—
—
—
—
If mask bit set
Push register
Mask bits:
0 = D
1 = E
N =
numberof
iterations
(SK : SP) − 2
SK : SP
2 = IX
3 = IY
4 = IZ
5 = K
6 = CCR
7 = (Reserved)
Push MAC Registers
Pull A
PSHMAC
PULA
MAC Registers
(SK : SP) + $0002 SK : SP
Pull (A)
Stack
INH
INH
27B8
3709
—
—
14
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(SK : SP) – $0001 SK : SP
(SK : SP) + $0002 SK : SP
Pull (B)
(SK : SP) – $0001 SK : SP
For mask bits 0 to 7:
PULB
Pull B
INH
3719
35
—
ii
6
—
—
—
—
—
—
—
—
PULM1
Pull Multiple Registers
IMM8
4+2(N+1)
∆
∆
∆
∆
∆
∆
∆
∆
Mask bits:
0 = CCR[15:4]
1 = K
N =
numberof
iterations
If mask bit set
(SK : SP) + 2
SK : SP
Pull register
2 = IZ
3 = IY
4 = IX
5 = E
6 = D
7 = (Reserved)
Pull MAC State
Repeating
Multiply and
Accumulate
Signed 16-Bit
Fractions
PULMAC
RMAC
Stack
Repeat until (E) < 0
(AM) + (H) (I)
Qualified (IX)
Qualified (IY)
(M : M + 1)X
MAC Registers
INH
IMM8
27B9
FB
—
xoyo
16
6 + 12
per
—
—
—
∆
—
—
—
∆
—
—
—
—
—
—
—
—
AM
IX;
IY;
H;
iteration
(M : M + 1)Y
I
(E) − 1
E
Until (E) < $0000
ROL
Rotate Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0C
1C
2C
170C
171C
172C
173C
370C
ff
ff
ff
8
8
8
8
8
8
8
2
—
—
—
—
∆
∆
∆
∆
gggg
gggg
gggg
hh ll
—
ROLA
ROLB
ROLD
ROLE
ROLW
Rotate Left A
Rotate Left B
Rotate Left D
Rotate Left E
Rotate Left Word
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
INH
INH
INH
371C
27FC
277C
—
—
—
2
2
2
IND16, X
IND16, Y
IND16, Z
EXT
270C
271C
272C
273C
gggg
gggg
gggg
hh ll
8
8
8
8
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
61
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
∆
C
∆
ROR
Rotate Right Byte
0E
1E
2E
170E
171E
172E
173E
370E
ff
ff
ff
8
8
8
8
8
8
8
2
gggg
gggg
gggg
hh ll
—
RORA
RORB
RORD
RORE
RORW
Rotate Right A
Rotate Right B
Rotate Right D
Rotate Right E
Rotate Right Word
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
INH
INH
INH
371E
27FE
277E
—
—
—
2
2
2
IND16, X
IND16, Y
IND16, Z
EXT
270E
271E
272E
273E
2777
gggg
gggg
gggg
hh ll
—
8
8
8
8
12
Return from Interrupt
(SK : SP) + 2
Pull CCR
(SK : SP) + 2
Pull PC
(PK : PC) − 6
(SK : SP) + 2
Pull PK
(SK : SP) + 2
Pull PC
SK : SP
INH
∆
∆
∆
∆
∆
∆
∆
∆
RTI3
SK : SP
PK : PC
SK : SP
Return from Subrou-
tine
INH
27F7
—
12
—
—
—
—
—
—
—
—
RTS4
SK : SP
(PK : PC) − 2
(A) − (B)
PK : PC
A
A
SBA
SBCA
Subtract B from A
Subtract with Carry
from A
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
370A
42
52
62
72
1742
1752
1762
1772
2742
2752
2762
C2
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
2
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
(A) − (M) − C
E, X
E, Y
E, Z
SBCB
Subtract with Carry
from B
(B) − (M) − C
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
∆
∆
∆
∆
D2
E2
F2
17C2
17D2
17E2
17F2
27C2
27D2
27E2
82
E, X
E, Y
E, Z
SBCD
Subtract with Carry
from D
(D) − (M : M + 1) − C
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
—
—
—
—
∆
∆
∆
∆
92
A2
ff
37B2
37C2
37D2
37E2
37F2
2782
2792
27A2
jj kk
gggg
gggg
gggg
hh ll
—
E, X
E, Y
E, Z
—
—
MOTOROLA
62
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
∆
C
∆
SBCE
Subtract with Carry
from E
(E) − (M : M + 1) − C
E
3732
3742
3752
3762
3772
2779
4A
jj kk
gggg
gggg
gggg
hh ll
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
4
6
6
6
6
2
4
4
4
6
6
6
6
4
4
4
4
4
4
6
6
6
6
4
4
4
4
4
4
6
6
6
6
6
6
6
6
6
6
6
8
SDE
STAA
Subtract D from E
Store A
(E) − (D)
E
INH
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
(A)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
0
—
5A
6A
174A
175A
176A
177A
274A
275A
276A
CA
STAB
STD
STE
Store B
Store D
Store E
(B)
M
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
0
0
0
—
—
—
DA
EA
ff
17CA
17DA
17EA
17FA
27CA
27DA
27EA
8A
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
(D)
M : M + 1
9A
AA
ff
37CA
37DA
37EA
37FA
278A
279A
27AA
374A
375A
376A
377A
2773
gggg
gggg
gggg
hh ll
—
—
—
(E)
(E)
M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
gggg
gggg
gggg
hh ll
hh ll
STED
STS
Store Concatenated
D and E
Store Stack Pointer
M : M + 1
M + 2 : M + 3
M : M + 1
EXT
—
—
—
—
—
—
—
—
—
—
—
0
—
—
(D)
(SP)
(IX)
(IY)
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8F
9F
AF
178F
179F
17AF
17BF
8C
ff
ff
ff
4
4
4
6
6
6
6
4
4
4
6
6
6
6
4
4
4
6
6
6
6
∆
∆
gggg
gggg
gggg
hh ll
ff
STX
STY
Store IX
Store IY
M : M + 1
—
—
—
—
—
—
—
—
∆
∆
∆
∆
0
0
—
—
9C
AC
ff
ff
178C
179C
17AC
17BC
8D
9D
AD
178D
179D
17AD
17BD
gggg
gggg
gggg
hh ll
ff
M : M + 1
ff
ff
gggg
gggg
gggg
hh ll
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
63
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
Opcode Operand Cycles
S
—
MV
—
H
—
EV
—
N
∆
Z
∆
V
0
C
—
STZ
Store Z
(IZ) M : M + 1
8E
9E
ff
ff
4
4
4
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
16
AE
ff
178E
179E
17AE
17BE
40
gggg
gggg
gggg
hh ll
ff
SUBA
SUBB
SUBD
Subtract from A
Subtract from B
Subtract from D
(A) − (M)
A
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
50
ff
60
ff
70
ii
1740
1750
1760
1770
2740
2750
2760
C0
gggg
gggg
gggg
hh ll
—
—
—
ff
E, Z
(B) − (M)
B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
D0
ff
E0
ff
F0
ii
17C0
17D0
17E0
17F0
27C0
27D0
27E0
80
gggg
gggg
gggg
hh ll
—
—
—
ff
E, X
E, Y
E, Z
(D) − (M : M + 1)
D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
90
ff
A0
ff
37B0
37C0
37D0
37E0
37F0
2780
2790
27A0
3730
3740
3750
3760
3770
3720
jj kk
gggg
gggg
gggg
hh ll
—
—
—
SUBE
SWI
Subtract from E
(E) − (M : M + 1)
E
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
Software Interrupt
(PK : PC) + $0002 PK : PC
Push (PC)
INH
—
—
—
—
(SK : SP) − $0002 SK : SP
Push (CCR)
(SK : SP) − $0002 SK : SP
$0
PK
SWI Vector
If B7 = 1
PC
SXT
Sign Extend B into A
INH
27F8
—
2
—
—
—
—
∆
∆
—
—
then $FF
else $00
A
A
TAB
TAP
TBA
TBEK
TBSK
TBXK
TBYK
TBZK
TDE
Transfer A to B
Transfer A to CCR
Transfer B to A
Transfer B to EK
Transfer B to SK
Transfer B to XK
Transfer B to YK
Transfer B to ZK
Transfer D to E
Transfer D to
(A)
(A[7:0])
B
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3717
37FD
3707
27FA
379F
379C
379D
379E
277B
372F
—
—
—
—
—
—
—
—
—
—
2
4
2
2
2
2
2
2
2
2
—
∆
—
∆
—
∆
—
∆
∆
∆
∆
—
—
—
—
—
∆
∆
∆
∆
—
—
—
—
—
∆
0
∆
0
—
—
—
—
—
0
—
∆
CCR[15:8]
A
EK
(B)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(B[3:0])
(B[3:0])
(B[3:0])
(B[3:0])
(B[3:0])
(D)
SK
XK
YK
ZK
E
TDMSK
(D[15:8])
(D[7:0])
(D)
X MASK
Y MASK
CCR[15:4]
—
—
—
XMSK : YMSK
Transfer D to CCR
TDP1
TED
INH
INH
372D
27FB
—
—
4
2
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Transfer E to D
(E)
D
—
—
—
—
0
—
MOTOROLA
64
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode Operand Cycles
S
MV
H
EV
N
Z
V
C
TEDM
Transfer E and D to
AM[31:0]
(E)
(D)
AM[31:16]
AM[15:0]
INH
27B1
—
4
—
0
—
0
—
—
—
—
Sign Extend AM
Transfer EK to B
AM[35:32] = AM31
TEKB
TEM
(EK)
$0
B[3:0]
B[7:4]
INH
INH
27BB
27B2
—
—
2
4
—
—
—
0
—
—
—
0
—
—
—
—
—
—
—
—
Transfer E to
AM[31:16]
(E)
$00
AM[31:16]
AM[15:0]
Sign Extend AM
Clear AM LSB
Transfer Rounded AM
to E
AM[35:32] = AM31
TMER
Rounded (AM)
Temp
INH
27B4
—
6
—
∆
—
∆
∆
∆
—
—
If (SM • (EV ✛ MV))
then Saturation Value
else Temp[31:16]
If (SM • (EV ✛ MV))
then Saturation Value
E
E
E
TMET
Transfer Truncated
AM to E
INH
INH
27B5
27B3
—
—
2
6
—
—
—
—
—
—
—
—
∆
∆
—
—
—
—
else AM[31:16]
E
TMXED
Transfer AM to
IX : E : D
AM[35:32]
AM35
IX[3:0]
IX[15:4]
—
—
AM[31:16]
AM[15:0]
(CCR[15:8])
(CCR)
E
D
A
TPA
TPD
TSKB
Transfer CCR to A
Transfer CCR to D
Transfer SK to B
INH
INH
INH
37FC
372C
37AF
—
—
—
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
(SK)
$0
B[3:0]
B[7:4]
TST
Test Byte
Zero or Minus
(M) − $00
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
06
16
26
1706
1716
1726
1736
3706
ff
ff
ff
6
6
6
6
6
6
6
2
—
—
—
—
∆
∆
0
0
gggg
gggg
gggg
hh ll
—
TSTA
TSTB
TSTD
TSTE
TSTW
Test A for
Zero or Minus
Test B for
Zero or Minus
Test D for
Zero or Minus
Test E for
Zero or Minus
Test for
(A) − $00
(B) − $00
INH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
0
0
0
0
0
0
INH
INH
INH
3716
27F6
2776
—
—
—
2
2
2
(D) − $0000
(E) − $0000
(M : M + 1) − $0000
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
2706
2716
2726
2736
274F
275F
276F
37AC
gggg
gggg
gggg
hh ll
—
—
—
—
6
6
6
6
2
2
2
2
Zero or Minus Word
TSX
TSY
TSZ
Transfer SP to IX
Transfer SP to IY
Transfer SP to IZ
Transfer XK to B
(SK : SP) + $0002
(SK : SP) + $0002
(SK : SP) + $0002
XK : IX
YK : IY
ZK : IZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INH
INH
TXKB
(XK)
$0
B[3:0]
B[7:4]
TXS
TXY
TXZ
Transfer IX to SP
Transfer IX to IY
Transfer IX to IZ
Transfer YK to B
(XK : IX) − $0002
SK : SP
INH
INH
INH
INH
374E
275C
276C
37AD
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(XK : IX)
(XK : IX)
(YK)
YK : IY
ZK : IZ
B[3:0]
B[7:4]
TYKB
$0
TYS
TYX
TYZ
Transfer IY to SP
Transfer IY to IX
Transfer IY to IZ
Transfer ZK to B
(YK : IY) − $0002
SK : SP
XK : IX
ZK : IZ
B[3:0]
B[7:4]
INH
INH
INH
INH
375E
274D
276D
37AE
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(YK : IY)
(YK : IY)
(ZK)
TZKB
$0
TZS
TZX
TZY
Transfer IZ to SP
Transfer IZ to IX
Transfer IZ to IY
Wait for Interrupt
Exchange A with B
Exchange D with E
Exchange D with IX
Exchange D with IY
Exchange D with IZ
(ZK : IZ) − $0002
SK : SP
XK : IX
ZK : IY
INH
INH
INH
INH
INH
INH
INH
INH
INH
376E
274E
275E
27F3
371A
277A
37CC
37DC
37EC
—
—
—
—
—
—
—
—
—
2
2
2
8
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(ZK : IZ)
(ZK : IZ)
WAI
WAIT
XGAB
XGDE
XGDX
XGDY
XGDZ
(A)
(D)
(D)
(D)
(D)
(B)
(E)
(IX)
(IY)
(IZ)
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
65
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Table 33 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
INH
INH
Opcode Operand Cycles
S
—
—
—
MV
—
—
H
—
—
—
EV
—
—
—
N
—
—
—
Z
—
—
—
V
—
—
—
C
—
—
—
XGEX
XGEY
XGEZ
Exchange E with IX
Exchange E with IY
Exchange E with IZ
(E)
(E)
(E)
(IX)
(IY)
(IZ)
374C
375C
376C
—
—
—
2
2
2
INH
—
NOTES:
1. CCR[15:4] change according to results of operation. The PK field is not affected.
2. Cycle times for conditional branches are shown in “taken, not taken” order.
3. CCR[15:0] change according to copy of CCR pulled from stack.
4. PK field changes according to state pulled from stack. The rest of the CCR is not affected.
MOTOROLA
66
MC68HC16S2
MC68HC16S2TS/D
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Table 34 Instruction Set Abbreviations and Symbols
A — Accumulator A
X — Register used in operation
M — Address of one memory byte
M +1 — Address of byte at M + $0001
M : M + 1 — Address of one memory word
(…)X — Contents of address pointed to by IX
(...)Y — Contents of address pointed to by IY
(...)Z — Contents of address pointed to by IZ
E, X — IX with E offset
AM — Accumulator M
B — Accumulator B
CCR — Condition code register
D — Accumulator D
E — Accumulator E
EK — Extended addressing extension field
IR — MAC multiplicand register
HR — MAC multiplier register
IX — Index register X
E, Y — IY with E offset
E, Z — IZ with E offset
IY — Index register Y
EXT — Extended
IZ — Index register Z
EXT20 — 20-bit extended
K — Address extension register
PC — Program counter
IMM8 — 8-bit immediate
IMM16 — 16-bit immediate
PK — Program counter extension field
SK — Stack pointer extension field
SL — Multiply and accumulate sign latch
SP — Stack pointer
IND8, X — IX with unsigned 8-bit offset
IND8, Y — IY with unsigned 8-bit offset
IND8, Z — IZ with unsigned 8-bit offset
IND16, X — IX with signed 16-bit offset
IND16, Y — IY with signed 16-bit offset
IND16, Z — IZ with signed 16-bit offset
IND20, X — IX with signed 20-bit offset
IND20, Y — IY with signed 20-bit offset
IND20, Z — IZ with signed 20-bit offset
INH — Inherent
XK — Index register X extension field
YK — Index register Y extension field
ZK — Index register Z extension field
XMSK — Modulo addressing index register X mask
YMSK — Modulo addressing index register Y mask
S — Stop disable control bit
MV — AM overflow indicator
H — Half carry indicator
IXP — Post-modified indexed
REL8 — 8-bit relative
EV — AM extended overflow indicator
N — Negative indicator
REL16 — 16-bit relative
b — 4-bit address extension
Z — Zero indicator
ff — 8-bit unsigned offset
V — Two's complement overflow indicator
C — Carry/borrow indicator
IP — Interrupt priority field
gggg — 16-bit signed offset
hh — High byte of 16-bit extended address
ii — 8-bit immediate data
SM — Saturation mode control bit
PK — Program counter extension field
— — Bit not affected
jj — High byte of 16-bit immediate data
kk — Low byte of 16-bit immediate data
ll — Low byte of 16-bit extended address
mm — 8-bit mask
∆ — Bit changes as specified
0 — Bit cleared
mmmm — 16-bit mask
1 — Bit set
rr — 8-bit unsigned relative offset
rrrr — 16-bit signed relative offset
xo — MAC index register X offset
yo — MAC index register Y offset
z — 4-bit zero extension
M — Memory location used in operation
R — Result of operation
S — Source data
+ — Addition
• — AND
− — Subtraction or negation (two's complement)
— Multiplication
✛ — Inclusive OR (OR)
— Exclusive OR (EOR)
NOT — Complementation
: — Concatenation
/ — Division
> — Greater
< — Less
— Transferred
= — Equal
— Exchanged
≥ — Equal or greater
≤ — Equal or less
≠ — Not equal
± — Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
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4.7 Exceptions
An exception is an event that preempts normal instruction process. Exception processing makes the
transition from normal instruction execution to execution of a routine that deals with an exception.
Each exception has an assigned vector that points to an associated handler routine. Exception process-
ing includes all operations required to transfer control to a handler routine, but does not include execu-
tion of the handler routine itself. Keep the distinction between exception processing and execution of an
exception handler in mind while reading this section.
4.7.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. Exception vectors are con-
tained in a data structure called the exception vector table, which is located in the first 512 bytes of bank
0. Refer to Table 35 for the exception vector table.
All vectors except the reset vector consist of one word and reside in data space. The reset vector
consists of four words that reside in program space. There are 52 predefined or reserved vectors, and
200 user-defined vectors.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by exter-
nal devices; others are supplied by the processor. There is a direct mapping of vector number to vector
table address. The processor left shifts the vector number one place (multiplies by two) to convert it to
an address.
Table 35 Exception Vector Table
Vector
Number
Vector
Address
Address
Space
Type of
Exception
0
0000
0002
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Reset — initial ZK, SK, and PK
Reset — initial PC
0004
Reset — initial SP
0006
Reset — initial IZ (direct page)
Breakpoint
4
5
0008
000A
Bus error
6
000C
Software interrupt
7
000E
Illegal instruction
8
0010
Division by zero
9 – E
F
0012 – 001C
001E
Unassigned, reserved
Uninitialized interrupt
Unassigned, reserved
Level 1 interrupt autovector
Level 2 interrupt autovector
Level 3 interrupt autovector
Level 4 interrupt autovector
Level 5 interrupt autovector
Level 6 interrupt autovector
Level 7 interrupt autovector
Spurious interrupt
10
0020
11
0022
12
0024
13
0026
14
0028
15
002A
16
002C
17
002E
18
0030
19 – 37
38 – FF
0032 – 006E
0070 – 01FE
Unassigned, reserved
User-defined interrupts
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4.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK:SP. Unless it is altered during exception processing, the stacked
PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure
13 shows the exception stack frame.
HIGH ADDRESS
HIGH ADDRESS
SP AFTER EXCEPTION STACKING
CONDITION CODE REGISTER
PROGRAM COUNTER
SP BEFORE EXCEPTION STACKING
EX STACK FRAME
Figure 13 Exception Stack Frame Format
4.7.3 Exception Processing Sequence
Exception processing is performed in four phases.
1. Priority of all pending exceptions is evaluated, and the highest priority exception is processed
first.
2. Processor state is stacked, then the CCR PK extension field is cleared.
3. An exception vector number is acquired and converted to a vector address.
4. The content of the vector address is loaded into the PC, and the processor jumps to the excep-
tion handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but the
reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located
within bank 0 or vectors must point to a jump table.
4.7.4 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which are defined as
asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Inter-
nal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the
background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception.
4.7.4.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing
is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first
instruction boundary following recognition of an exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than re-
set, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI
instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value
to resume execution of the interrupted instruction stream.
4.7.4.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for synchro-
nous exceptions is always completed, and the first instruction of the handler routine is always executed,
before interrupts are detected.
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Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to
the address of the instruction that causes the exception plus $0006. Because RTI always subtracts
$0006 upon return, the stacked PK : PC must be adjusted by the instruction that caused the exception
so that execution resumes with the following instruction. For this reason, $0002 is added to the PK : PC
value before it is stacked.
4.7.5 Multiple Exceptions
Each exception has a hardware priority based upon its relative importance to system operation. Asyn-
chronous exceptions have higher priorities than synchronous exceptions. Exception processing for mul-
tiple exceptions is completed by priority, from highest to lowest. Priority governs the order in which
exception processing occurs, not the order in which exception handlers are executed.
Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of
all exception handler routines is guaranteed to execute before another exception is processed. Because
interrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt
handler are executed before other interrupts are sensed.
Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous excep-
tion are processed before the first instruction of that exception’s handler routine. The converse is not
true. If an interrupt occurs during bus error exception processing, for example, the first instruction of the
exception handler is executed before interrupts are sensed. This permits the exception handler to mask
interrupts during execution.
4.7.6 RTI Instruction
The “return from interrupt instruction” (RTI) must be the last instruction in all exception handlers except
the RESET handler. RTI pulls the exception stack frame that was pushed onto the system stack during
exception processing, and restores processor state. Normal program flow resumes at the address of
the instruction that follows the last instruction executed before exception processing began.
RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create
a stack frame.
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5 Standby RAM Module
The standby RAM module (SRAM) provides two Kbytes of fast RAM that is especially useful for system
stacks and variable storage. The SRAM has a dedicated power supply pin so that memory content can
be preserved when the MCU is powered down.
5.1 Overview
The SRAM module consists of a control register block that is located at a fixed range of addresses in
MCU address space, and a 2-Kbyte array of two bus cycle static RAM that can be mapped to any 2-
Kbyte boundary in MCU address space. SRAM control registers are located at addresses $YFFB00–
YFFB08.
The module responds to program and data space accesses. Data can be read or written in bytes, words,
or long words. The RAM array must not be mapped so that array addresses overlap module control reg-
ister addresses, as overlap makes the registers inaccessible.
The SRAM is powered by V in normal operation. During power-down, SRAM contents are maintained
DD
by power from the V
input. Power switching between sources is automatic.
STBY
Table 36 shows the SRAM address map.
Table 36 SRAM Address Map
Address
15
0
1
$YFFB00
$YFFB02
$YFFB04
$YFFB06
RAM Module Configuration Register (RAMMCR)
RAM Test Register (RAMTST)
RAM Array Base Address Register High (RAMBAH)
RAM Array Base Address Register Low (RAMBAL)
NOTES:
1. Y = M111, where M is the logic state of the module mapping (MM) bit in SIMCR.
5.2 SRAM Register Block
There are four SRAM control registers: the SRAM module configuration register (RAMMCR), the SRAM
test register (RAMTST), and the SRAM array base address registers (RAMBAH/RAMBAL).
5.3 SRAM Registers
SRAM responds to both program and data space accesses based on the value in the RASP field in
RAMMCR. This allows code to be executed from RAM.
RAMMCR — RAM Module Configuration Register
$YFFB00
15
STOP
RESET:
1
14
0
13
0
12
0
11
10
0
9
8
7
6
5
4
3
2
1
0
RLCK
RASP[1:0]
NOT USED
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Use RAMMCR to determine whether the RAM is in STOP mode or normal mode. RAMMCR can deter-
mine in which space the array resides and also controls access to the base array registers. Reads of
unimplemented bits always return zeros. Writes do not affect unimplemented bits.
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STOP — Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is one, leaving
the array configured for LPSTOP operation. In stop mode, the array retains its contents, but cannot be
read or written by the CPU. This bit can be read or written at any time.
RLCK — RAM Base Address Lock
0 = SRAM base address registers can be written from IMB
1 = SRAM base address registers are locked
RLCK defaults to zero on reset. It can be written to one once.
RASP[1:0] — RAM Array Space
This field limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 operates in supervisor mode only, RASP1 has no effect. Refer
to Table 37.
Table 37 RASP Encoding
RASP
X0
Space
Program and data
Program
X1
RAMTST — RAM Test Register
$YFFB02
RAMTST is for factory test only. Reads of this register return zeros and writes have no effect.
RAMBAH — Array Base Address Register High
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
RESET:
RAMBAL — Array Base Address Register Low
$YFFB06
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
0
NOT USED
ADDR
15
ADDR ADDR ADDR ADDR
14
0
13
0
12
0
11
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
RAMBAH and RAMBAL specify an SRAM base address in the system memory map. They can only be
written while the SRAM is in low-power mode (RAMMCR STOP = 1, the default out of reset) and the
base address lock is disabled (RAMMCR RLCK = 0, the default out of reset). This prevents accidental
remapping of the array. Because the CPU16 drives ADDR[23:20] to the same logic level as ADDR19,
the values of the RAMBAH ADDR[23:20] fields must match the value of the ADDR19 field for the array
to be accessible.
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5.4 SRAM Operation
There are five SRAM operating modes. They include the following:
1. The RAM module is in normal mode when powered by V . The array can be accessed by byte,
DD
word, or long word. A byte or aligned word (high-order byte is at an even address) access only
takes one bus cycle or two system clocks. A long word or misaligned word access requires two
bus cycles.
2. Standby mode is intended to preserve RAM contents when V is removed. SRAM contents
DD
are maintained by a power source connected to the V
pin. The standby voltage is referred
STBY
to as V . Circuitry within the SRAM module switches to the higher of V or V with no loss
SB
DD
SB
of data. When SRAM is powered from the V
pin, access to the array is not guaranteed. If
STBY
standby operation is not desired, connect the V
pin to V
.
STBY
SS
3. Reset mode allows the CPU to complete the current bus cycle before resetting. When a syn-
chronous reset occurs while a byte or word SRAM access is in progress, the access is com-
pleted. If reset occurs during the first word access of a long-word operation, only the first word
access is completed. If reset occurs during the second word access of a long word operation,
the entire access is completed. Data being read from or written to the RAM may be corrupted
by asynchronous reset.
4. Test mode is used for factory testing of the RAM array.
5. Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM ar-
ray is disabled which, if necessary, allows external logic to decode SRAM addresses but all
data is retained. If V falls below V , internal circuitry switches to V , as in standby mode.
DD
SB
SB
Exit the stop mode by clearing the STOP bit.
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6 Electrical Characteristics
This section contains 20.97 MHz and 25.17 MHz electrical specification tables and reference timing
diagrams.
Table 38 20.97/25.17 MHz Maximum Ratings
Num
Rating
Symbol
Value
Unit
1, 2, 3
1
VDD
– 0.3 to + 6.5
V
Supply Voltage
1, 2, 3, 4
2
3
Vin
ID
– 0.3 to + 6.5
25
V
Input Voltage
Instantaneous Maximum Current
Single pin limit (applies to all pins)
mA
1, 3, 5, 6
4
Operating Maximum Current
5, 6, 7
Digital Input Disruptive Current
– 0.3 ≤ V ≤ V + 0.3
IID
– 500 to + 500
µA
V
IN
DD
SS
5
6
TL to TH
– 40 to + 85
Operating Temperature Range
Storage Temperature Range
TA
°C
°C
Tstg
– 55 to + 150
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess
of recommended values affects device reliability. Device modules may not operate normally while being ex-
posed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static voltages or elec-
trical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages.
3. This parameter is periodically sampled rather than 100% tested.
4. All pins except TSC.
5. All functional non-supply pins are internally clamped to V for transitions below V . All functional pins except
SS
SS
EXTAL and XFC are internally clamped to V for transitions below V
.
DD
DD
6. Power supply must maintain regulation within operating V range during instantaneous and operating max-
DD
imum current conditions.
7. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding
this limit can cause disruption of normal operation.
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Table 39 20.97 MHz Typical Ratings
Num
Rating
Symbol
Value
5.0
Unit
V
1
2
Supply Voltage
Operating Temperature
Supply Current
V
DD
T
25
°C
A
V
DD
RUN
LPSTOP, VCO Off
LPSTOP, External clock, max f
60
125
3.0
mA
µA
µA
3
4
I
DD
sys
Clock Synthesizer Operating Voltage
Supply Current
V
5.0
V
DDSYN
V
DDSYN
VCO on, maximum f
External Clock, maximum f
LPSTOP, VCO off
1.0
4.5
100
50
mA
mA
µA
sys
5
I
sys
DDSYN
µA
V
powered down
DD
6
7
8
RAM Standby Voltage
V
3.0
V
SB
RAM Standby Current
Normal RAM Operation
Standby Operation
I
7.0
40
µA
µA
SB
Power Dissipation
P
300
mW
D
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Table 40 25.17 MHz Typical Ratings
Num
Rating
Symbol
Value
5.0
Unit
V
1
2
Supply Voltage
Operating Temperature
Supply Current
V
DD
T
25
°C
A
V
DD
RUN
LPSTOP, VCO Off
LPSTOP, External clock, max f
75
125
3.75
mA
µA
mA
3
4
I
DD
sys
Clock Synthesizer Operating Voltage
Supply Current
V
5.0
V
DDSYN
V
DDSYN
VCO on, maximum f
External Clock, maximum f
LPSTOP, VCO off
1.0
5.0
100
50
mA
mA
µA
sys
5
I
sys
DDSYN
µA
V
powered down
DD
6
7
8
RAM Standby Voltage
V
3.0
V
SB
RAM Standby Current
Normal RAM Operation
Standby Operation
I
7.0
40
µA
µA
SB
Power Dissipation
P
375
mW
D
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Table 41 Thermal Characteristics
Num
Characteristic
Thermal Resistance
Plastic 100-Pin Surface Mount
Symbol
Value
Unit
1
Θ
42.5
°C/W
JA
The average chip-junction temperature (T ) in C can be obtained from:
J
(1)
TJ = TA + (PD × ΘJA
)
where:
T = Ambient Temperature, °C
A
Θ
= Package Thermal Resistance, Junction-to-Ambient, °C/W
JA
P = P + P
I/O
D
INT
P
P
= I × V , Watts — Chip Internal Power
DD
INT DD
= Power Dissipation on Input and Output Pins — User Determined
I/O
For most applications P < P and can be neglected. An approximate relationship between
I/O
INT
P and T (if P is neglected) is:
D
J
I/O
(2)
(3)
PD = K ÷ (TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD + (TA + 273°C) + ΘJA × PD2
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring P (at equilibrium) for a known T . Using this value of K, the values of P and T
D
A
D
J
can be obtained by solving equations (1) and (2) iteratively for any value of T .
A
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Table 42 20.97 MHz Clock Control Timing
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
20
Max
Unit
1
1
fref
50
kHz
PLL Reference Frequency Range
2
2
System Frequency
dc
20.97
20.97
20.97
On-Chip PLL System Frequency Range
External Clock Operation
fsys
tlpll
4f
MHz
ref
dc
—
—
1, 3, 4, 5, 6
3
20
ms
PLL Lock Time
7
4
5
VCO Frequency
f
2 (f max)
MHz
VCO
sys
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
—
—
(fsys max)/2
sys max
flimp
MHz
f
1, 4, 5, 6, 8
6
CLKOUT Jitter
– 1.5
– 0.5
1.0
0.5
Short term (5 µs interval)
Long term (500 µs interval)
Jclk
%
NOTES:
1. The base configuration of the MC68HC16S2 requires a 32.768 kHz reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V
is applied, and that the crystal oscillator is stable. Lock time is measured from
DDSYN
the time V and V
are valid until RESET is released. This specification also applies to the period re-
DD
DDSYN
quired for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYN-
CR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
4. This parameter is periodically sampled rather than 100% tested.
5. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 MΩ to guarantee this
specification. Filter network geometry can vary depending upon operating environment.
6. Proper layout procedures must be followed to achieve specifications.
7. Internal VCO frequency (f
) is determined by SYNCR W and Y bit values.
VCO
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f = f
÷ 4.
÷ 2.
sys
VCO
When X = 1, the divider is disabled, and f = f
sys
VCO
X must equal one when operating at maximum specified f
.
sys
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at max-
imum f . Measurements are made with the device powered by filtered supplies and clocked by a stable ex-
sys
ternal clock signal. Noise injected into the PLL circuitry via V
and V and variation in crystal oscillator
DDSYN
SS
frequency increase the J percentage for a given interval. When clock jitter is a critical constraint on control
clk
system operation, this parameter should be measured during functional testing of the final system.
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Table 43 25.17 MHz Clock Control Timing
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit
1
1
PLL Reference Frequency Range
fref
20
50
kHz
2
2
dc
25.17
25.17
25.17
System Frequency
fsys
4f
MHz
On-Chip PLL System Frequency Range
External Clock Operation
ref
dc
—
—
1, 3, 4, 5, 6
3
4
5
tlpll
20
ms
PLL Lock Time
7
f
2 (f max)
MHz
VCO Frequency
VCO
sys
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
—
—
(fsys max)/2
sys max
flimp
MHz
f
1, 4, 5, 6, 8
6
CLKOUT Jitter
– 1.5
– 0.5
1.0
0.5
Short term (5 µs interval)
Long term (500 µs interval)
Jclk
%
NOTES:
1. Refer to notes in Table 42.
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Table 44 20.97 MHz DC Characteristics
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH
)
Num
Characteristic
Symbol
Min
Max
Unit
V
1
Input High Voltage
Input Low Voltage
V
IH
0.7 (V ) V + 0.3
DD
DD
2
3
4
V
V
– 0.3 0.2 (V )
DD
V
IL
SS
1
Input Hysteresis
V
0.5
–2.5
–2.5
—
V
HYS
2
Input Leakage Current
I
2.5
2.5
—
µA
µA
V
IN
V
= V or V
in
DD SS
2
5
6
7
High Impedance (Off-State) Leakage Current
= V or V
I
OZ
V
in
DD
SS
2, 3
CMOS Output High Voltage
= –10.0 µA
V
V
V
– 0.2
DD
OH
I
OH
2
CMOS Output Low Voltage
= 10.0 µA
V
—
0.2
—
V
V
OL
I
OL
2, 3
8
9
Output High Voltage
= –0.8 mA
V
– 0.8
DD
OH
I
OH
2
Output Low Voltage
I
I
I
= 1.6 mA
= 5.3 mA
= 12 mA
—
—
—
0.4
0.4
0.4
OL
OL
OL
V
V
OL
10
11
Three State Control Input High Voltage
V
1.6 (V )
DD
9.1
V
IHTSC
4
Data Bus Mode Select Pull-up Current
V
V
= V
DATA[15:0]
DATA[15:0]
I
—
–15
–120
—
µA
in
in
IL
MSP
= V
IH
5, 6
12
V
Supply Current
DD
110
350
5
mA
µA
mA
6
Run , crystal reference
I
—
—
DD
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
sys
13
14
Clock Synthesizer Operating Voltage
V
I
4.75
5.25
V
DDSYN
5, 6
V
Supply Current
DDSYN
—
—
—
—
1
5
100
50
mA
mA
µA
VCO on, 32.768 kHz crystal reference, maximum f
sys
External Clock, maximum f
DDSYN
sys
LPSTOP, 32.768 kHz crystal reference, VCO off (STSIM = 0)
µA
32.768 kHz, V powered down
DD
7
15
16
RAM Standby Voltage
0.0
3.0
5.25
5.25
Specified V applied
V
V
DD
SB
V
= V
SS
DD
7, 6
RAM Standby Current
8
—
—
—
10
3
50
µA
mA
µA
Normal RAM operation
Transient condition
V
V
> V – 0.5 V
SB
DD
SB
I
SB
– 0.5 V ≥ V ≥ V + 0.5 V
DD
SS
7
Standby operation
V
< V + 0.5 V
DD SS
5, 9
17
18
P
C
—
603
mW
pF
Power Dissipation
D
2, 10
Input Capacitance
—
—
10
20
All input-only pins
All input/output pins
IN
MOTOROLA
80
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 44 20.97 MHz DC Characteristics (Continued)
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH
)
Num
Characteristic
Symbol
Min
Max
Unit
2
19
Load Capacitance
—
—
—
—
90
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
C
100
130
200
pF
L
Group 4 I/O Pins
NOTES:
1. Applies to:
SIZ[1:0], AS, DS, IRQ[7:1], MODCLK, RESET, EXTAL, TSC, BKPT/DSCLK, IPIPE1/DSI
2. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, IPIPE0/DSO
Input/Output Pins:
Group 1: DATA[15:0], IPIPE1/DSI
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] —IRQ[7:1], MODCLK, ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0,
BGACK/CS2
Group 3: HALT, RESET
3. Does not apply to HALT and RESET because they are open drain pins.
4. Use of an active pulldown device is recommended.
5. Total operating current is the sum of the appropriate V , supply and V
supply current. V at 3.3V.
DD
DD
DDSYN
6. Current measured with system clock frequency of 20.97 MHz, all modules active.
7. The SRAM module will not switch into standby mode as long as V does not exceed V by more than 0.5
SB
DD
volts. The SRAM array cannot be accessed while the module is in standby mode.
8. When V is more than 0.3V greater than V , current flows between the V
and V pins, which causes
SB
DD
STBY
DD
standby current to increase toward the maximum transient condition specification. System noise on the V
DD
and V
pin can contribute to this condition.
STBY
9. Power dissipation is measured with a system clock frequency of 20.97 MHz, all modules active. Power dissi-
pation is calculated using the following expression:
P = Maximum V (I + I
+ I
)
D
DD DD
DDSYN
SB
10. Input capacitance is periodically sampled rather than 100% tested.
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
81
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 45 25.17 MHz DC Characteristics
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH
)
Num
Characteristic
Symbol
Min
Max
Unit
V
1
Input High Voltage
Input Low Voltage
V
IH
0.7 (V ) V + 0.3
DD
DD
2
3
4
V
V
– 0.3 0.2 (V )
DD
V
IL
SS
1
Input Hysteresis
V
0.5
—
V
HYS
2
Input Leakage Current
I
–2.5
2.5
2.5
—
µA
µA
V
IN
V
= V or V
in
DD SS
2
5
6
7
8
9
High Impedance (Off-State) Leakage Current
= V or V
I
–2.5
OZ
V
in
DD
SS
2, 3
CMOS Output High Voltage
= –10.0 µA
V
V
V
– 0.2
DD
OH
I
OH
2
CMOS Output Low Voltage
= 10.0 µA
V
—
0.2
—
V
OL
I
OL
2, 3
Output High Voltage
= –0.8 mA
V
– 0.8
DD
V
OH
I
OH
2
Output Low Voltage
I
I
I
= 1.6 mA
= 5.3 mA
= 12 mA
—
—
—
0.4
0.4
0.4
OL
OL
OL
V
V
OL
10
11
Three State Control Input High Voltage
V
1.6 (V )
DD
9.1
V
IHTSC
4
Data Bus Mode Select Pull-up Current
V
V
= V
DATA[15:0]
DATA[15:0]
I
—
–15
–120
—
µA
in
in
IL
MSP
= V
IH
5, 6
12
V
Supply Current
DD
140
350
5
mA
µA
mA
6
Run , crystal reference
I
—
—
DD
LPSTOP, crystal reference, VCO Off (STSIM = 0)
LPSTOP, external clock input = max f
sys
13
14
Clock Synthesizer Operating Voltage
V
I
4.75
5.25
V
DDSYN
5, 6
V
Supply Current
DDSYN
—
—
—
—
2
7
150
100
mA
mA
µA
VCO on, 32.768 kHz crystal reference, maximum f
sys
External Clock, maximum f
DDSYN
sys
LPSTOP, 32.768 kHz crystal reference, VCO off (STSIM = 0)
µA
32.768 kHz, V powered down
DD
7
15
16
RAM Standby Voltage
0.0
3.0
5.25
5.25
Specified V applied
V
V
DD
SB
V
= V
SS
DD
7, 6
RAM Standby Current
8
—
—
—
10
3
50
µA
mA
µA
Normal RAM operation
Transient condition
V
V
> V – 0.5 V
SB
DD
SB
I
SB
– 0.5 V ≥ V ≥ V + 0.5 V
DD
SS
7
Standby operation
V
< V + 0.5 V
DD SS
5, 9
17
18
P
C
—
766
mW
pF
Power Dissipation
D
2, 10
Input Capacitance
—
—
10
20
All input-only pins
All input/output pins
IN
MOTOROLA
82
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 45 25.17 MHz DC Characteristics (Continued)
(VDD and VDDSYN = 5.0 Vdc, VSS = 0 Vdc, TA = TL to TH
)
Num
Characteristic
Symbol
Min
Max
Unit
2
19
Load Capacitance
—
—
—
—
90
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
C
100
130
200
pF
L
Group 4 I/O Pins
NOTES:
1. Refer to notes in Table 44. Parameters are measured with system clock frequency of 25.17 MHz.
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
83
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Freescale Semiconductor, Inc.
Table 46 20.97 MHz AC Timing
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
F1
Characteristic
2
Symbol
Min
4 f
Max
20.97
—
Unit
MHz
ns
Frequency of Operation
Clock Period
f
t
sys
cyc
ref
1
47.7
381
47.7
18.8
183
23.8
—
—
—
0
1A
1B
2, 3
ECLK Period
t
t
—
ns
Ecyc
Xcyc
3
External Clock Input Period
Clock Pulse Width
—
ns
t
—
ns
CW
2A, 3A ECLK Pulse Width
t
—
ns
ECW
3
2B, 3B
4, 5
t
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External Clock Input High/Low Time
CLKOUT Rise and Fall Time
XCHL
t
Crf
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
t
8
rf
4
4B, 5B External Clock Input Rise and Fall Time
t
5
XCrf
5
Clock High to ADDR, FC, SIZE Valid
6
7
t
23
47
—
23
10
—
23
—
—
—
—
—
47
—
23
23
—
—
23
—
—
—
—
—
60
—
48
CHAV
Clock High to ADDR, Data, FC, SIZE High Impedance
Clock High to ADDR, FC, SIZE Invalid
t
0
CHAZx
8
t
0
CHAZn
5
9
t
t
0
Clock Low to AS, DS, CS Asserted
CLSA
6
9A
11
12
13
14
14A
14B
15
16
17
18
20
21
22
23
24
25
26
27
27A
28
29
29A
AS to DS or CS Asserted (Read)
–10
10
2
STSA
AVSA
CLSN
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
t
t
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
t
10
80
36
32
32
—
10
0
SNAI
t
SWA
DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
AS, CS (and DS Read) Width Asserted (Fast Cycle)
7
AS, DS, CS Width Negated
t
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
t
CHSZ
SNRN
CHRH
t
Clock High to R/W High
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W High to AS, CS Asserted
10
54
—
10
10
10
5
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
t
CHDO
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
t
DVASN
t
SNDOI
t
DVSA
5
t
Data In Valid to Clock Low (Data Setup)
DICL
Late BERR, HALT Asserted to Clock Low (Setup Time)
t
15
0
BELCL
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
8
DS, CS Negated to Data In Invalid (Data In Hold)
t
0
SNDI
SHDI
8, 9
t
—
DS, CS Negated to Data In High Impedance
8
30
t
10
—
—
ns
ns
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLDI
8
30A
t
72
CLKOUT Low to Data In High Impedance
CLDH
MOTOROLA
84
MC68HC16S2
MC68HC16S2TS/D
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Freescale Semiconductor, Inc.
Table 46 20.97 MHz AC Timing (Continued)
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
31
Characteristic
Symbol
Min
—
—
1
Max
46
23
—
2
Unit
ns
10
DSACK[1:0] Asserted to Data In Valid
t
DADI
33
Clock Low to BG Asserted/Negated
t
ns
CLBAN
BRAGA
11
35
BR Asserted to BG Asserted
t
t
t
t
t
cyc
cyc
cyc
cyc
37
BGACK Asserted to BG Negated
BG Width Negated
t
1
GAGN
39
t
2
—
—
—
—
GH
39A
46
BG Width Asserted
t
1
GA
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
t
115
70
ns
ns
RWA
46A
t
RWAS
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47A
t
5
—
ns
AIST
AIHT
47B
48
Asynchronous Input Hold Time
t
12
—
0
—
30
—
23
—
23
—
—
—
—
—
—
—
10
40
40
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
DSACK[1:0] Asserted to BERR, HALT Asserted
t
DABA
DOCH
53
Data Out Hold from Clock High
t
54
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
t
—
32
0
CHDH
55
t
RADC
70
t
SCLDD
71
t
10
10
10
10
20
0
SCLDS
t
SCLDH
72
73
t
BKST
BKHT
74
BKPT Input Hold Time
t
75
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
t
t
cyc
MSS
MSH
RSTA
76
t
ns
13
77
RESET Assertion Time
t
4
t
cyc
cyc
14, 15
78
t
—
3
t
RESET Rise Time
RSTR
16
100
101
102
103
104
105
CLKOUT High to Phase 1 Asserted
t
t
ns
ns
ns
ns
ns
ns
CHP1A
CLKOUT High to Phase 2 Asserted
Phase 1 Valid to AS or DS Asserted
Phase 2 Valid to AS or DS Asserted
AS or DS Valid to Phase 1 Negated
AS or DS Valid to Phase 2 Negated
3
CHP2A
t
10
10
10
10
P1VSA
P2VSN
SAP1N
SNP2N
t
t
t
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
85
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NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. The base configuration of the MC68HC16S2 requires a 32.768 kHz crystal reference.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable t
period is reduced when the duty cycle of the external clock varies. The relationship between ex-
Xcyc
ternal clock input duty cycle and minimum t
is expressed:
Xcyc
Minimum t
period = minimum t
/ (50% – external clock input duty cycle tolerance).
Xcyc
XCHL
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external reference applied while the PLL is enabled (MODCLK pin held high during
reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If
transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
5. Address access time = (2.5 + WS) t – t
– t
cyc
CHAV
DICL
Chip-select access time = (2 + WS) t – t
– t
DICL
cyc
CLSA
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
6. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall out-
side the limits shown in specification 9.
7. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
8. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
9. Maximum value is equal to (t / 2) + 25 ns.
cyc
10. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup
time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
11. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
of the current operand transfer are complete.
12. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification
47A).
13. After external RESET negation is detected, a short transition period (approximately 2 t ) elapses, then the SIM
cyc
drives RESET low for 512 tcyc.
14. External assertion of the RESET input can overlap internally-generated resets. To ensure that an external reset
is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
15. External logic must pull RESET high during this period in order for normal MCU operation to begin.
16. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
MOTOROLA
86
MC68HC16S2
MC68HC16S2TS/D
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 47 25.17 MHz AC Timing
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
F1
Characteristic
Symbol
Min
Max
Unit
2
f
4 f
25.166 MHz
Frequency of Operation
Clock Period
sys
ref
1
t
39.7
318
39.7
15
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
1A
1B
2, 3
ECLK Period
t
Ecyc
Xcyc
3
t
External Clock Input Period
Clock Pulse Width
t
CW
2A, 3A ECLK Pulse Width
t
155
19.8
—
ECW
3
2B, 3B
4, 5
t
External Clock Input High/Low Time
CLKOUT Rise and Fall Time
XCHL
t
Crf
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
t
—
8
rf
4
4B, 5B
t
—
4
External Clock Input Rise and Fall Time
XCrf
5
6
7
8
9
t
0
0
0
2
19
39
—
19
ns
ns
ns
ns
Clock High to ADDR, FC, SIZE Valid
CHAV
Clock High to ADDR, Data, FC, SIZE High Impedance
Clock High to ADDR, FC, SIZE Invalid
t
CHAZx
t
CHAZn
5
t
t
Clock Low to AS, DS, CS Asserted
CLSA
6
9A
11
12
13
14
14A
14B
15
16
17
18
20
21
22
23
24
25
26
27
27A
28
29
–10
8
15
—
19
—
—
—
—
—
39
—
19
19
—
—
19
—
—
—
—
—
50
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS to DS or CS Asserted (Read)
STSA
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
t
t
AVSA
2
CLSN
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
t
8
SNAI
t
65
25
22
22
—
10
0
SWA
DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
AS, CS (and DS Read) Width Asserted (Fast Cycle)
7
t
AS, DS, CS Width Negated
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
t
CHSZ
SNRN
CHRH
t
Clock High to R/W High
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W High to AS, CS Asserted
10
40
—
7
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
t
CHDO
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
t
DVASN
t
5
SNDOI
t
8
DVSA
5
t
5
Data In Valid to Clock Low (Data Setup)
DICL
Late BERR, HALT Asserted to Clock Low (Setup Time)
t
10
0
BELCL
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
8
t
0
DS, CS Negated to Data In Invalid (Data In Hold)
SNDI
SHDI
8, 9
29A
30
t
—
8
45
—
ns
ns
DS, CS Negated to Data In High Impedance
8
t
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLDI
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
87
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 47 25.17 MHz AC Timing (Continued)
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
Characteristic
Symbol
Min
Max
Unit
8
30A
t
—
60
ns
CLKOUT Low to Data In High Impedance
CLDH
10
31
33
t
—
—
1
35
19
—
2
ns
ns
DSACK[1:0] Asserted to Data In Valid
DADI
Clock Low to BG Asserted/Negated
t
t
CLBAN
11
35
t
BR Asserted to BG Asserted
BRAGA
cyc
37
BGACK Asserted to BG Negated
BG Width Negated
t
1
t
t
t
GAGN
cyc
cyc
cyc
39
t
2
—
—
—
—
GH
39A
46
BG Width Asserted
t
1
GA
R/W Width Asserted (Write or Read)
t
90
55
ns
ns
RWA
46A
R/W Width Asserted (Fast Write or Read Cycle)
t
RWAS
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47A
t
5
—
ns
AIST
AIHT
47B
48
53
54
55
70
71
72
73
74
75
76
77
Asynchronous Input Hold Time
t
10
—
0
—
27
—
23
—
19
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
t
DSACK[1:0] Asserted to BERR, HALT Asserted
DABA
DOCH
Data Out Hold from Clock High
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
t
—
25
0
CHDH
t
RADC
t
SCLDD
t
8
SCLDS
SCLDH
t
8
t
10
10
20
0
BKST
BKPT Input Hold Time
t
BKHT
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
t
t
cyc
MSS
t
ns
MSH
13
t
4
t
RESET Assertion Time
RSTA
RSTR
cyc
cyc
14, 15
78
t
—
10
t
RESET Rise Time
16
100
101
t
t
3
3
9
9
9
9
34
34
—
—
—
—
ns
ns
ns
ns
ns
ns
CLKOUT High to Phase 1 Asserted
CHP1A
CLKOUT High to Phase 2 Asserted
Phase 1 Valid to AS or DS Asserted
Phase 2 Valid to AS or DS Asserted
AS or DS Valid to Phase 1 Negated
AS or DS Valid to Phase 2 Negated
CHP2A
102
t
P1VSA
P2VSN
SAP1N
SNP2N
103
t
t
104
105
t
NOTES:
1. Refer to notes in Table 46. Parameters are measured with system clock frequency of 25.17 MHz.
MOTOROLA
88
MC68HC16S2
MC68HC16S2TS/D
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1
2
3
4
CLKOUT
5
16 CLKOUT TIM
16 EXT CLK INPUT TIM
16 ECLK OUTPUT TIM
Figure 14 CLKOUT Output Timing Diagram
1B
2B
3B
4B
EXTAL
5B
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
.
DD
PULSE WIDTH SHOWN WITH RESPECT TO 50% V
.
DD
Figure 15 External Clock Input Timing Diagram
1A
2A
3A
4A
ECLK
5A
NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V
DD.
Figure 16 ECLK Output Timing Diagram
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
89
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S0
S1
S2
S3
S4
S5
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
15
11
AS
DS
CS
13
9
9A
12
17
18
21
20
R/W
46
DSACK0
47A
31
28
DSACK1
29
DATA[15:0]
27
29A
BERR
HALT
48
27A
BKPT
47A
47B
ASYNCHRONOUS
INPUTS
105
100
101
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
102
16 RD CYC TIM
Figure 17 Read Cycle Timing Diagram
MOTOROLA
90
MC68HC16S2
MC68HC16S2TS/D
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S0
S1
S2
S3
S4
S5
CLKOUT
6
8
ADDR[23:20]
FC[2:0]
SIZ[1:0]
11
14
15
AS
DS
13
9
21
9
12
CS
22
20
14A
17
R/W
46
DSACK0
47A
28
DSACK1
55
25
DATA[15:0]
23
26
54
53
BERR
HALT
48
27A
73
74
BKPT
101
100
102
105
IPIPE0
IPIPE1
PHASE 1
104
PHASE 2
103
16 WR CYC TIM
Figure 18 Write Cycle Timing Diagram
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
91
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S0
S1
S4
S5
S0
CLKOUT
8
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
AS
14B
12
9
DS
CS
20
18
46A
R/W
30
30A
27
DATA[15:0]
29A
73
29
BKPT
74
100
101
IPIPE0
IPIPE1
PHASE 1
102
PHASE 2
105
104
103
16 FAST RD CYC TIM
Figure 19 Fast Termination Read Cycle Timing Diagram
MOTOROLA
92
MC68HC16S2
MC68HC16S2TS/D
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S0
S1
S4
S5
S0
CLKOUT
6
8
ADDR[23:0]
FC[1:0]
SIZ[1:0]
14B
AS
DS
9
12
CS
20
46A
R/W
24
18
23
DATA[15:0]
73
25
BKPT
100
101
105
IPIPE0
IPIPE1
PHASE 1
PHASE 2
103
102
104
16 FAST WR CYC TIM
Figure 20 Fast Termination Write Cycle Timing Diagram
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
93
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S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
ADDR[23:0]
DATA[15:0]
7
AS
DS
16
R/W
DSACK0
DSACK1
47A
BR
BG
39A
35
33
33
BGACK
37
100
PHASE 1
102
101
IPIPE0
IPIPE1
PHASE 2
104
103
105
16 BUS ARB TIM
Figure 21 Bus Arbitration Timing Diagram — Active Bus Case
MOTOROLA
94
MC68HC16S2
MC68HC16S2TS/D
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A0
A5
A5
A2
A3
A0
CLKOUT
ADDR[23:0]
DATA[15:0]
AS
47A
47A
BR
BG
35
37
47A
33
33
BGACK
16 BUS ARB TIM IDLE
Figure 22 Bus Arbitration Timing Diagram — Idle Bus Case
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
95
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S0
S41
S42
S43
S0
S1
S2
CLKOUT
6
8
ADDR[23:0]
R/W
18
20
AS
9
12
15
DS
71
72
70
74
DATA[15:0]
73
BKPT
100
101
PHASE 1
102
IPIPE0
PHASE 2
105
PHASE 1
PHASE 2
IPIPE1
104
103
SHOW CYCLE
START OF EXTERNAL CYCLE
NOTE:
Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module
wait-state insertion.
16 SHW CYC TIM
Figure 23 Show Cycle Timing Diagram
MOTOROLA
96
MC68HC16S2
MC68HC16S2TS/D
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S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
8
6
6
ADDR[23:0]
FC[2:0]
SIZ[1:0]
14
11
11
14
13
AS
DS
15
9
9
9
12
17
17
21
12
CS
20
18
14A
18
46
R/W
46
25
29
55
DATA[15:0]
29A
53
23
27
54
16 CHIP SEL TIM
Figure 24 Chip-Select Timing Diagram
77
78
RESET
75
DATA[15:0],
MODCLK,
BKPT
76
16 RST/MODE SEL TIM
Figure 25 Reset and Mode Select Timing Diagram
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
97
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Table 48 20.97 MHz Background Debugging Mode Timing
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Characteristic
Symbol
Min
15
10
15
10
—
Max
—
Unit
ns
DSI Input Setup Time
DSI Input Hold Time
DSCLK Setup Time
DSCLK Hold Time
DSO Delay Time
t
DSISU
t
—
ns
DSIH
t
—
ns
DSCSU
t
—
ns
DSCH
t
25
—
ns
DSOD
DSCLK Cycle Time
t
2
t
cyc
DSCCYC
CLKOUT High to FREEZE Asserted/Negated
CLKOUT High to IPIPE1 High Impedance
CLKOUT High to IPIPE1 Valid
t
—
50
50
50
—
ns
ns
ns
FRZAN
t
—
IFZ
t
—
IF
DSCLO
DSCLK Low Time
t
1
t
cyc
cyc
cyc
B10 IPIPE1 High Impedance to FREEZE Asserted
B11 FREEZE Negated to IPIPE[1:0] Active
NOTES:
t
TBD
TBD
—
t
t
IPFA
t
—
FRIP
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
Table 49 25.17 MHz Background Debugging Mode Timing
1
(VDD and VDDSYN = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
)
Num
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Characteristic
Symbol
Min
10
5
Max
—
Unit
ns
DSI Input Setup Time
DSI Input Hold Time
DSCLK Setup Time
DSCLK Hold Time
DSO Delay Time
t
DSISU
t
—
ns
DSIH
t
10
5
—
ns
DSCSU
t
—
ns
DSCH
DSOD
t
—
20
—
ns
DSCLK Cycle Time
t
2
t
cyc
DSCCYC
CLKOUT High to FREEZE Asserted/Negated
CLKOUT High to IPIPE1 High Impedance
CLKOUT High to IPIPE1 Valid
t
—
20
20
20
—
ns
ns
ns
FRZAN
t
—
IFZ
t
—
IF
DSCLO
DSCLK Low Time
t
1
t
cyc
cyc
cyc
B10 IPIPE1 High Impedance to FREEZE Asserted
B11 FREEZE Negated to IPIPE[1:0] Active
NOTES:
t
TBD
TBD
—
t
t
IPFA
FRIP
t
—
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
MOTOROLA
98
MC68HC16S2
MC68HC16S2TS/D
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CLKOUT
FREEZE
B3
B2
BKPT/DSCLK
B9
B5
B1
B0
IPIPE1/DSI
IPIPE0/DSO
B4
16 BDM SER COM TIM
Figure 26 Background Debugging Mode Timing Diagram —
Serial Communication
CLKOUT
FREEZE
B6
B6
B11
B7
B10
IPIPE1/DSI
B8
16 BDM FRZ TIM
Figure 27 Background Debugging Mode Timing Diagram —
Freeze Assertion
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
99
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Table 50 20.97 MHz ECLK Bus Timing
1
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH
)
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
—
10
—
10
25
25
5
Max
48
—
120
—
—
—
—
48
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
ECLK Low to Address Valid
EAD
ECLK Low to Address Hold
ECLK Low to CS Valid (CS Delay)
ECLK Low to CS Hold
t
EAH
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
0
EDHZ
ECDH
t
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
3
t
—
—
10
308
t
t
ECDZ
cyc
cyc
t
t
2
EDDW
EDHW
—
—
ns
ns
ns
E13
E14
t
EACC
Address Access Time (Read)
4
t
236
1/2
—
—
Chip-Select Access Time (Read)
EACS
E15 Address Setup Time
t
t
cyc
EAS
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
MOTOROLA
100
MC68HC16S2
MC68HC16S2TS/D
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Table 51 25.17 MHz ECLK Bus Timing
1
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH
)
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
—
10
—
10
20
25
5
Max
40
—
100
—
—
—
—
40
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
ECLK Low to Address Valid
EAD
ECLK Low to Address Hold
ECLK Low to CS Valid (CS Delay)
ECLK Low to CS Hold
t
EAH
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
0
EDHZ
ECDH
t
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
3
t
—
—
5
t
t
ECDZ
cyc
cyc
t
t
2
EDDW
EDHW
—
—
ns
ns
ns
E13
E14
t
255
Address Access Time (Read)
EACC
4
t
195
—
—
Chip-Select Access Time (Read)
EACS
E15 Address Setup Time
t
1/2
t
cyc
EAS
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
101
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CLKOUT
ECLK
2A
3A
1A
R/W
E1
E2
ADDR[23:0]
E5
E3
E14
E13
E4
E6
CS
E15
E9
DATA[15:0]
READ
E7
WRITE
E8
E11
E10
DATA[15:0]
WRITE
E12
HC16 E CYCLE TIM
Figure 28 ECLK Timing Diagram
MOTOROLA
102
MC68HC16S2
MC68HC16S2TS/D
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MC68HC16S2
MC68HC16S2TS/D
MOTOROLA
103
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability
of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and
all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and
do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
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MC68HC16S2TS/D
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