MC17XSG500EK_技术文档

MC32XSG

Multi-purpose high-side switches

Rev. 5 — 21 July 2021

Product data sheet

1 General description

The 32XSG family is designed to control, protect and diagnose various type of low-

voltage loads with enhanced precision. It combines flexibility, extended digital and analog

feedbacks, safety, and robustness. This family offers the possibility to configure outputs

to improve EMC, manage frequency and duty cycle, adapt the dynamic overcurrent

profiles to the load, program the current sense ratio of each output, and many more.

Devices can be driven either by the embedded SPI module or by direct inputs in Fail-safe

operation mode and remains operational, controllable and protected in this case. This

product is driven by SMARTMOS technology.

2 Features and benefits

• Penta high-side switches with high transient capability

• 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control including PWM duty

cycles, output On and Off openload detections, thermal shutdown and prewarning, and

fault reporting

• Output current monitoring with programmable synchronization signal and supply

voltage feedback

• Fail-safe mode

• External smart power switch control

• Operating voltage is 7.0 V to 30 V with sleep current < 5.0 μA, extended mode from

6.0 V to 32 V

• -16 V reverse polarity and ground disconnect protections

• Compatible PCB foot print and SPI software driver among the family

NXP Semiconductors

MC32XSG

Multi-purpose high-side switches

3 Simplified application diagram

Figure 1.ꢀSimplified application diagram

4 Applications

• Low-voltage exterior lighting

• Low-voltage industrial lighting

• Low-voltage automation systems

• Halogen lamps

• Incandescent bulbs

• Light-emitting diodes (LEDs)

• HID Xenon ballasts

• DC Motors

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MC32XSG

Multi-purpose high-side switches

5 Ordering information

This section describes the part numbers available to be purchased along with their

differences.

Table 1.ꢀOrderable parts

Part number

Notes

Temperature (T_A) Package

OUT1 R_DS(on)OUT2

R_DS(on)

OUT3

R_DS(on)

OUT4

R_DS(on)

OUT5

R_DS(on)

OUT6

Yes

MC07XSG517EK

MC07XSG517DEK

MC17XSG500EK

MC17XSG500BEK

MC17XSG500DEK

SOIC54 pins

exposed pad

17 mΩ

7.0 mΩ

17 mΩ

7.0 mΩ

17 mΩ

7.0 mΩ

17 mΩ

SOIC54 pins

exposed pad

Yes

SOIC32 pins

exposed pad

Yes

[1]

–40 °C to 125 °C

SOIC32 pins

exposed pad

Yes

SOIC32 pins

exposed pad

Yes

[1] To order parts in tape and reel, add the R2 suffix to the part number.

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search.

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6 Internal block diagram

Figure 2.ꢀ32XSG simplified internal block diagram

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7 Pinning information

7.1 Pinning

Figure 3.ꢀPin configuration for 32-pin SOIC-EP package

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Figure 4.ꢀPin configuration for 54-pin SOIC-EP package

7.2 Pin description

Table 2.ꢀPin description

Symbol

Pin function

Formal name

Definition

32 SOIC-EP

54 SOIC-EP ^[1]

CP

1

3

Internal supply Charge pump

This pin is the connection for an

external capacitor for charge pump

use only.

RSTB

CSB

2

4

SPI

Reset

This input pin is used to initialize

the device configuration and fault

registers, as well as place the device

in a low-current Sleep mode. This pin

has a passive internal pull-down.

3

5

Chip select

This input pin is connected to a

chip select output of a master

microcontroller (MCU). When this

digital signal is high, SPI signals are

ignored. Asserting this pin low starts

an SPI transaction. The transaction

is indicated as completed when this

signal returns to high level. This pin

has a passive internal pull-up to VCC

through a diode

SCLK

4

6

SPI

Serial clock

This input pin is connected to the

MCU providing the required bit shift

clock for SPI communication. This pin

has a passive internal pull-down.

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Table 2.ꢀPin description...continued

Symbol

Pin function

Formal name

Definition

32 SOIC-EP

54 SOIC-EP ^[1]

SI

5

7

SPI

Serial input

This pin is the data input of the SPI

communication interface. The data at

the input are sampled on the positive

edge of the SCLK. This pin has a

passive internal pull-down.

VCC

SO

6

7

8

9

Power supply

SPI

MCU power

supply

This pin is a power supply pin for

internal logic, the SPI I/Os and the

OUT6 driver.

Serial Output

This output pin is connected to the

SPI Serial Data Input pin of the MCU

or to the SI pin of the next device of

a daisy chain of devices. The SPI

changes on the negative edge of

SCLK. When CSB is high, this pin is

high- impedance.

OUT6

GND

8

10

Output

External Solid

State

This output pin controls an external

Smart Power Switch by logic level.

This pin has a passive internal pull-

down.

9 and 24

11 and 44

Ground

These pins are the ground for the

logic and analog circuitries of the

device. For ESD and electrical

parameter accuracy purpose, the

ground pins must be shorted on the

board.

OUT2

OUT4

NC

10 to 11

12 to 14

15, 16

12 to 13

14 to 16

Output

N/A

Channel #2

Channel #4

Protected high-side power output pins

to the load.

Protected high-side power output pins

to the load.

1, 2, 18 to 27,

53, 54

Not connected These pins are not connected. It is

recommended to connect these pint to

ground

OUT5

OUT3

OUT1

CSNS

17 to 18

19 to 21

22 to 23

25

28 to 37

39 to 41

42 to 43

45

Output

Channel #5

Channel #3

Channel #1

Current sense

Protected high-side power output pins

to the load

Output

Protected high-side power output pins

to the load

Output

Protected high-side power output pins

to the load

Feedback

This pin reports an analog value

proportional to the designated

OUT[1:5] output current or the

temperature of the exposed pad or the

supply voltage. It is used externally to

generate a ground-referenced voltage

for the microcontroller (MCU). Current

recopy and analog voltage feedbacks

are SPI programmable.

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Table 2.ꢀPin description...continued

Symbol

Pin function

Formal name

Definition

32 SOIC-EP

54 SOIC-EP ^[1]

CSNS

SYNCB

26

27

46

47

Feedback

Current sense

synchronization synchronizing the MCU A/D

conversion. This pin requires an

This open drain output pin allows

external pull-up resistor to VCC.

IN1

IN2

IN3

IN4

Input

Direct input #1 This input wakes up the device. This

input pin is used to directly control

corresponding channel in Fail mode.

During Normal mode the control of the

outputs by the control inputs is SPI

programmable. This pin has a passive

internal pull-down.

28

29

30

48

49

50

Direct input #2 This input wakes up the device. This

input pin is used to directly control

corresponding channel in Fail mode.

During Normal mode the control of the

outputs by the control inputs is SPI

programmable. This pin has a passive

internal pull-down.

Direct input #3 This input wakes up the device. This

input pin is used to directly control

corresponding channel in Fail mode.

During Normal mode the control of the

outputs by the control inputs is SPI

programmable. This pin has a passive

internal pull-down.

Direct input #4 This input wakes up the device. This

input pin is used to directly control

corresponding channel in Fail mode.

During Normal mode the control of the

outputs by the control inputs is SPI

programmable. This pin has a passive

internal pull-down.

LIMP

CLK

31

32

51

52

Input

Limp Home

The Fail mode can be activated

by this digital input. This pin has a

passive internal pull-down.

Input/Output

Device mode

feedback

This pin is an input/output pin. It is

used to report the device sleep-state

information. It is also used to apply

reference PWM clock which is divided

by 2⁸in Normal operating mode. This

pin has a passive internal pull-down.

Reference

PWM clock

VPWR

33

55

Power supply

This exposed pad connects to the

positive power supply and is the

source of operational power for the

device.

[1] Pins 17 and 38 are omitted.

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8 General product characteristics

8.1 Relationship between ratings and operating requirements

The analog portion of device is supplied by the voltage applied to the VPWR exposed

pad. Thereby the supply of internal circuitry (logic in case of a V_CCdisconnect, charge

pump, gate drive,…) is derived from the VPWR pin.

In case of a reverse supply:

• The internal supply rail is protected (max. –16 V)

• The output drivers (OUT1… OUT5) are switched on, to reduce the power consumption

in the drivers when using incandescent bulbs.

Figure 5.ꢀRatings vs. operating requirements (VPWR pin)

The device’s digital circuitry is powered by the voltage applied to the VCC pin. If VCC is

disconnected, the logic part is supplied by the VPWR pin.

The output driver for SPI signals, CLK pin (wake feedback), and OUT6 are supplied by

the VCC pin only. This pin must be protected externally in case of a reverse polarity, and

in case of a high-voltage disturbance.

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Figure 6.ꢀRatings vs. operating requirements (VCC pin)

8.2 Maximum ratings

Table 3.ꢀMaximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Symbol

Description (Rating)

Min

Max

Unit

ELECTRICAL RATINGS

V_PWR

V_CC

V_IN

VPWR voltage range

–16

40

V

VCC logic supply voltage

–0.3

7.0

[1]

Digital input voltage

IN1:IN4 and LIMP

CLK, SI, SCLK, CSB, and RSTB

–0.3

40

20

V

V_OUT

Digital output voltage

SO, CSNS, CSNS SYNCB, OUT6, CLK

–0.3

—

20

V

[2]

[3]

I_CL

Negative digital input clamp current

5.0

mA

I_OUT

Power channel current

7.0 mΩ channel

—

11

A

17 mΩ channel

5.5

[4]

E_CL

Power channel clamp energy capability

7.0 mΩ channel - Initial T_J= 150 °C

17 mΩ channel - Initial T_J= 150 °C

—

100

50

mJ

[1] Exceeding voltage limits on those pins may cause a malfunction or permanent damage to the device.

[2] Maximum current in negative clamping for IN1:IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins.

[3] Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using

package thermal resistance is required.

[4] Active clamp energy using single-pulse method (L = 2.0 mH, R_L= 0 Ω, V_PWR= 14 V). Refer to Section 10.1.4 "Digital diagnostics"

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8.3 Thermal characteristics

Table 4.ꢀThermal ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Symbol

THERMAL RATINGS

Operating temperature

Description (Rating)

Min

Max

Unit

[1]

T_A

T_J

Ambient

Junction

–40

+125

+150

°C

T_STG

Storage temperature

–55

—

+150

260

°C

[2] [3]

T_PPRT

Peak package reflow temperature during reflow

THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

[4]

R_ΘJB

R_ΘJA

Junction-to-Board

—

2.5

°C/W

[5] [6]

Junction-to-Ambient, Natural Convection, Four-Layer

Board (2s2p)

17.4

[7]

R_ΘJC

Junction-to-Case (Case top surface)

—

10.6

°C/W

[1] To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125 °C.

[2] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction

or permanent damage to the device.

[3] NXP's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture

Sensitivity Levels (MSL), go to nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review

parametrics.

[4] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package.

[5] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

[6] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

[7] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

8.4 Operating conditions

This section describes the operating conditions of the device. Conditions apply to the

following data, unless otherwise noted.

Table 5.ꢀOperating conditions

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Symbol

Ratings

Min

Max

Unit

V_PWR

Functional operating supply voltage - Device is fully

functional. All features are operating.

7.0

30

V

Reverse supply

–16

4.5

—

V

V_CC

Functional operating supply voltage - Device is fully

functional. All features are operating.

5.5

8.5 Supply currents

This section describes the current consumption characteristics of the device.

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Table 6.ꢀSupply currents

Characteristics noted under conditions 4.5 V ≤ V_CC≤ 5.5 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

VPWR CURRENT CONSUMPTIONS

I_QVPWRSleep mode measured at V_PWR= 24 V

Ratings

Min

Typ

Max

Unit

[1] [2]

T_A= 25 °C

T_A= 125 °C

—

25

35

45

μA

[2]

I_VPWR

Operating mode measured at V_PWR= 24 V

—

7.0

10

mA

VCC CURRENT CONSUMPTIONS

I_QVCCSleep mode measured at V_CC= 5.5 V and V_PWR

=

—

15

50

µA

24 V

I_VCC

Operating mode measured at V_CC= 5.5 V and V_PWR

= 30 V (SPI frequency 5.0 MHz)

2.8

4.0

mA

[1] With the OUT1… OUT5 power channels grounded.

[2] With the OUT1… OUT5 power channels opened.

9 General IC functional description and application information

9.1 Introduction

The 32XSG family provides advanced features. It consists of two similar devices

compatible in terms of software drivers and package footprints. It diagnoses the low-

current using an enhanced current sense precision with a synchronization pin, as well as

driving high power motors with a perfect control of its current consumption. It combines

flexibility through daisy chainable SPI 5.0 MHz, extended digital and analog feedback,

safety, and robustness. It integrates an enhanced PWM module with 8-bit duty cycle

capability and a PWM frequency prescaler per power channel.

9.2 Features

The main attributes of the 32XSG are:

• Penta high-side switches with overload, overtemperature, and undervoltage protection

• Control output for one external smart power switch

• 16-bit SPI communication interface with daisy chain capability

• Dedicated control inputs for use in fail mode

• Analog feedback pin with SPI programmable multiplexer and sync signal

• Channel diagnosis by SPI communication

• Advanced current sense mode for low current use

• Synchronous PWM module with external clock, prescaler, and multiphase feature

• Excellent EMC behavior

• Power net and reverse polarity protection

• Ultra low-power mode

• Scalable and flexible family concept

• Board layout compatible SOIC54 and SOIC32 package with exposed pad

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9.3 Block diagram

Figure 7.ꢀFunctional block diagram

9.3.1 Self-protected high-side switches

OUT1… OUT5 are the output pins of the power switches. The power channels are

protected against various kinds of short-circuits, and have active clamp circuitry which

may be activated when switching off inductive loads. Many protective and diagnostic

functions are available.

9.3.2 Power supply

The device operates with supply voltages from 5.5 V to 40 V (V_PWR), but is full spec.

compliant only between 7.0 V and 30 V. The VPWR pin supplies power to the internal

regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.) supplies the output

register of the serial peripheral interface (SPI). Consequently, the SPI registers cannot be

read without presence of V_CC. The employed IC architecture guarantees a low quiescent

current in sleep mode.

9.3.3 MCU interface and device control

In normal mode the power output channels are controlled by the embedded PWM

module, which is configured by the SPI register settings. For bidirectional SPI

communication, V_CChas to be in the authorized range. Failure diagnostics and

configuration are also performed through the SPI port. The reported failure types

are: openload, short-circuit to supply, severe short-circuit to ground, overcurrent,

overtemperature, clock-fail, under and overvoltage. The device allows driving loads at

different frequencies to 400 Hz.

9.4 Functional description

The device has four fundamental operating modes: Sleep, Normal, Fail and Power off. It

possesses multiple high-side switches (power channels) each of which can be controlled

independently:

• In Normal mode by SPI interface. A second supply voltage (V_CC) is required for

bidirectional SPI communication.

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• In Fail mode by the corresponding direct inputs IN1… IN4. The OUT5 and OUT6 are off

in this mode.

9.5 Modes of operation

The operating modes are based on the signals:

• wake = (IN1_ON) or (IN2_ON) or (IN3_ON) or (IN4_ON) or (RSTB). For more details,

see Section 10.3.3.2 "Logic I/O plausibility check".

• fail = (SPI_fail) or (LIMP). For more details, see Section 10.3.3.1 "Loss of

communication interface".

Figure 8.ꢀGeneral IC operating modes

9.5.1 Power Off mode

The power off mode is applied when V_PWRand V_CCare below the power on reset

threshold (V_{PWR POR}, V_{CC POR}). No functionality is available, but the device is protected

by the clamping circuits in power off. See Section 10.2.3 "Supply voltage disconnection".

9.5.2 Sleep mode

The sleep mode is used to provide ultra low-current consumption. During sleep mode:

• the component is inactive and all outputs are disabled

• the outputs are protected by the clamping circuits

• the pull-up/pull-down resistors are present

Sleep mode is the default mode of the device after applying the supply voltages (V_PWRor

V_CC) prior to any wake-up condition (wake = [0]). Wake-up from sleep mode is provided

by the wake signal.

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9.5.3 Normal mode

The Normal mode is the regular operating mode of the device. The device is in Normal

mode, when the device is in the wake state (wake = [1]) and no fail condition (fail = [0]) is

detected. During Normal mode:

• the power outputs are under control of the SPI and its programmable PWM mode

• the power outputs are protected by the overload protection circuits

• the digital diagnostic feature transfers status of the smart switch via the SPI

• the analog feedback output (CSNS and CSNS SYNCB) can be controlled by the SPI

9.5.4 Fail mode

The device enters the Fail mode, when:

• the LIMP input pin is high (logic [1])

• or a SPI failure is detected

During Fail mode (wake = [1] & fail = [1]):

• the OUT1… OUT4 outputs are directly controlled by the corresponding control inputs

(IN1… IN4)

• the OUT5… OUT6 are turned off and not controllable

• the PWM module is not available

• while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail

mode condition):

– SO reports the content of SO register defined by SOA0 to 3 bits

• the outputs are fully protected in case of an overload, overtemperature, and

undervoltage

• no analog feedback is available

• the max. output overcurrent profile is activated (OCLO and window times)

• in case of an overload condition or undervoltage, the autorestart feature controls the

OUT1… OUT4 outputs

• in case of an overtemperature condition, OCHI1 detection, or severe short-circuit

detection, the corresponding output is latched OFF until a new wake-up event

9.5.5 Mode transitions

After a wake-up:

• a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])

• the faults are blanked during t_BLANKING

The device enters in Normal mode after start-up if following sequence is provided:

• V_PWRand V_CCpower supplies must be above their undervoltage thresholds (sleep

mode)

• generate wake-up event (wake = 1) setting RSTB from 0 to 1

The device initialization is completed after 50 μsec (typ). During this time, the device is

robust in case of VPWR interrupts higher than 150 nsec. The transition from “Normal

mode” to “Fail mode” is executed immediately when a fail condition is detected. During

the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared.

When the Fail mode condition is a:

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• LIMP input, WD toggle timeout, WD toggle sequence, or a SPI modulo 16 error, the SPI

diagnosis is available during Fail mode

• SI/SO stuck to static level, the SPI diagnosis is not available during Fail mode

The transition from “Fail mode” to “Normal mode” is enabled when:

• the fail condition is removed and

• two SPI commands are sent within a valid watchdog cycle (first WD=[0] and then

WD=[1])

During this transition:

• all SPI SI and SO registers are cleared (logic[0])

• the DSF (device status flag) in the registers #1… #7 and the RCF (Register Clearer

flag) in the device status register #1 are set (logic[1])

To delatch the RCF diagnosis, a read command of the quick status register #1 must be

performed.

9.6 SPI interface and configurations

9.6.1 Introduction

The SPI is used to:

• control the device in case of Normal mode

• provide diagnostics in case of Normal and Fail mode

The SPI is a 16-bit full-duplex synchronous data transfer interface with daisy chain

capability. The interface consists of four I/O lines with 5.0 V CMOS logic levels and

termination resistors:

• The SCLK pin clocks the internal shift registers of the device

• The SI pin accepts data into the input shift register on the rising edge of the SCLK

signal

• The SO pin changes its state on the rising edge of SCLK and reads out on the falling

edge

• The CSB enables the SPI interface:

– with the leading edge of CSB, the registers load

– while CSB is logic [0], SI/SO data shifts

– with the trailing edge of the CSB signal, SPI data latches into the internal registers

– when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is

high-impedance

When the RSTB input is:

• low (logic [0]), the SPI and the fault registers are reset. The wake state then depends

on the status of the input pins (IN_ON1… IN_ON4)

• high (logic[1]), the device is in wake status and the SPI is enabled

The functionality of the SPI is checked by a plausibility check. During a SPI failure, the

device enters Fail mode.

9.6.2 SPI input register and bit descriptions

The first nibble of the 16-bit data word (D15… D12) serves as address bits.

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Table 7.ꢀSPI input register and bit descriptions

Register

SI address

SI data

D6 D5

11 bit address

#

D15 D14 D13 D12 D11 D10 D9

D8

D7

D4

D3

D2

D1

D0

name

x

4 bit address

WD

11 bits (D10… D0) are used as data bits.

The D11 bit is the WD toggle bit. This bit has to be toggled with each write command.

When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected.

All register values are logic [0] after a reset. The predefined value is off/inactive unless

otherwise noted.

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Figure 9.ꢀSPI input register

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9.6.3 SPI output register and bit descriptions

The first nibble of the 16-bit data word (D12… D15) serves as address bits. All register

values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off/

inactive unless otherwise noted.

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Figure 10.ꢀSPI output register

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9.6.4 Timing diagrams

Figure 11.ꢀTiming requirements during SPI communication

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Figure 12.ꢀTiming diagram for serial output (SO) data communication

9.6.5 Electrical characterization

Table 8.ꢀElectrical characteristics

Characteristics noted under conditions 4.5 V ≤ V_CC≤ 5.5 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

SPI SIGNALS CSB, SI, SO, SCLK, SO

f_SPI

V_IH

SPI clock frequency

0.5

3.5

—

5.0

—

MHz

V

Logic input high state level (SI, SCLK, CSB, RSTB)

V_IH(WAKE)Logic input high state level for wake-up (RSTB)

3.75

—

V

V_IL

Logic input low state level (SI, SCLK, CSB, RSTB)

Logic output high state level (SO)

0.85

—

V

V_OH

V_OL

I_IN

VCC – 0.4

—

V

Logic output low state level (SO)

0.4

+0.5

V

Logic input leakage current in inactive state (SI = SCLK

= RSTB = [0] and CSB = [1])

-0.5

μA

I_OUT

Logic output tri-state leakage current (SO from 0 V to

-10

—

+1.0

μA

V_CC

)

R_PULL

Logic input pull-up/pull-down resistor

25

—

10

100

130

20

kΩ

pF

μs

R_PULL-CSBLogic pull-up resistor for CSB

[1]

C_IN

Logic input capacitance

RSTB deglitch time

t_{RST_DGL}

7.5

12.5

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Table 8.ꢀElectrical characteristics...continued

Characteristics noted under conditions 4.5 V ≤ V_CC≤ 5.5 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

t_SO

Characteristic

Min

—

Typ

—

Max

20

Unit

ns

SO rising and falling edges with 80 pF

t_WCLKh

Required high state duration of SCLK (required setup

time)

80

—

ns

t_WCLKI

t_CS

Required low state duration of SCLK (required setup

time)

80

—

ns

μs

Required duration from the rising to the falling edge of

CSB (required setup time)

1.0

t_RST

Required low state duration for reset RST

1.0

—

μs

ns

t_LEAD

Falling edge of CSB to rising edge of SCLK (required

setup time)

320

t_LAG

Falling edge of SCLK to rising edge of CSB (required

setup lag time)

100

—

ns

t_SI(SU)

t_SI(H)

SI to falling edge of SCLK (required setup time)

20

—

ns

Falling edge of SCLK to SI (required hold time of the SI

signal)

t_RSI

SI, CSB, SCLK, max. rise time allowing operation at

maximum f_SPI

—

20

—

50

—

ns

t_FSI

SI, CSB, SCLK, max. fall time allowing operation at

maximum f_SPI

t_SO(EN)

t_SO(DIS)

Time from falling edge of CSB to reach low-impedance

on SO (access time)

Time from rising edge of CSB to reach tri-state on SO

[1] Parameter is derived from simulations.

10 Functional block requirements and behaviors

10.1 Self-protected high-side switches description and application

information

10.1.1 Features

Up to five power outputs are foreseen to drive light as well as DC motor applications.

The outputs are optimized for driving bulbs, HID ballasts, LEDs, and other resistive,

capacitive, or low inductive loads. The smart switches are controlled by use of high

sophisticated gate drivers. The gate drivers provide:

• output pulse shaping

• output protections

• active clamps

• output diagnostics

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10.1.2 Output pulse shaping

The outputs are controlled with a closed loop active pulse shaping to provide the best

compromise between:

• low switching losses

• low EMC emission performance

• minimum propagation delay time

Depending on the programming of the prescaler setting register #12-1, #12-2, the

switching speeds of the outputs are adjusted to the output frequency range of each

channel. The edge shaping must be designed according to the following table.

Divider

factor

PWM freq. (Hz)

PWM period (ms)

D.C. range (hex)

D.C. range (LSB)

Min. on/

off duty

cycle

min.

max.

min.

max.

min.

max.

min.

max.

time (μs)

4

2

1

25

50

100

200

400

10

5

40

20

10

03

07

FB

F7

4

8

252

248

156

78

100

2.5

The edge shaping provides full symmetry for rising and falling transition.

Figure 13.ꢀTypical power output switching (slow and fast slew rate)

10.1.2.1 SPI control and configuration

For optimized control of the outputs, a synchronous clock module is integrated. The

PWM frequency and output timing during normal mode are generated from the clock

input (CLK) by the integrated PWM module. In case of a clock fail (very low frequency,

very high frequency), the output duty cycle is 100 %.

Each output (OUT1:OUT6) can be controlled by an individual channel control register.

Register

SI address

D15 D14 D13 D12 D11

channel address WD

SI data

D5

#

D10

D9

D8

D7

D6

D4

D3

D2

D1

D0

CHx

2-7

PH1x PH0x Onx PWM7x PWM6x PWM5x PWM4x PWM3x PWM2x PWM1x PWM0x

control

Where:

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• PH0x… PH1x: phase assignment of the output channel x

• ONx: on/off control including overcurrent window control of the output channel x

• PWM0x… PWM7x: 8-bit PWM value individually for each output channel x

The ONx bits are duplicated in the output control register #8 to control the outputs

with either the CHx control register or the output control register. The PRS1x… PRS0x

prescaler settings can be set in the prescaler settings register #12-1 and #12-2.

The synchronization of the switching phases between different devices is provided by the

PWM SYNC bit in the initialization 2 register #1.

On a SPI write into initialization 2 register (#1):

• initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module

are reset with the positive edge of the CSB, the phase synchronization is performed

immediately within one SPI frame. It could help to synchronize different 32XSG devices

in the board

• when the bit D1 is logic[0], no action is executed

The switching frequency can be adjusted for the corresponding channel as described in

the following table:

CLK freq. (kHz)

prescaler setting

divider

factor

PWN freq. (Hz)

slew rate

PWM resolution

min.

max.

PRS1x

PRS0x

min.

25

max.

100

200

400

(Bit)

(steps)

25.6

102.4

0

1

0

1

X

4

2

1

slow

fast

8

256

50

100

No PWM feature is provided in case of:

• fail mode

• clock input signal failure

10.1.2.2 Global PWM control

In addition to the individual PWM register, each channel can be assigned independently

to a global PWM register. The setting is controlled by the GPWM EN bits inside the global

PWM control register #9-1. When no control by direct input pin is enabled and the GPWM

EN bit is:

• low (logic[0]), the output is assigned to individual PWM (default status)

• high (logic[1]), the output is assigned to global PWM

The PWM value of the global PWM channel is controlled by the global PWM control

register #9-2.

When a channel is assigned to global PWM, the switching phase the prescaler and the

pulse skipping are according the corresponding output channel setting.

Table 9.ꢀGlobal PWM Register

Register SI address

SI data

D5

#

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D4

D3

D2

D1

D0

Global

PWM

9-1

1

0

1

WD

0

X

GPWM

EN6

GPWM

EN5

GPWM

EN4

GPWM

EN3

GPWM

EN2

GPWM

EN1

control

9-2

1

0

1

WD

1

X

GPWM 7 GPWM6 GPWM5 GPWM4 GPWM3 GPWM2 GPWM1 GPWM0

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10.1.2.3 Incremental PWM control

To reduce the control overhead during soft start/stop of bulbs or DC motors (theatre

dimming), an incremental PWM control feature is implemented. With the incremental

PWM control feature the PWM values of all internal channels OUT1:OUT5 can be

incremented or decremented with one SPI frame.

The incremental PWM feature is not available for:

• the global PWM channel

• the external channel OUT6

The control is according the increment/decrement register #14:

• INCR SGN: sign of incremental dimming (valid for all channels)

• INCR 1x, INCR 0x increment/decrement

INCR SGN

Increment/decrement

decrement

0

1

increment

INCR 1x

INCR 0x

Increment/decrement

0

1

0

1

0

1

no increment/decrement

4

8

16

This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.

10.1.2.4 Input control

Up to four dedicated control inputs (IN1:IN4) are foreseen to:

• wake-up the device

• fully control the corresponding output in case of Fail mode

• control the corresponding output in case of Normal mode

The control during Normal mode is according the INEN0x and INEN1x bits in the input

enable register #11 and according to the logic in Table 9. An input deglitcher is provided

at each control input to avoid high frequency control of the outputs. The internal signal is

called iINx.

As the input thresholds are logic level compatible, the input structure of the pin is able

to withstand supply voltage levels (max. 40 V) without damage. External current limit

resistors (1.0 kΩ, 10 kΩ) can be used to handle reverse current conditions. The inputs

have an integrated pull-down resistor.

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10.1.2.5 Electrical characterization

Table 10.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

POWER OUTPUTS OUT1:OUT5

R_DS(on)ON-Resistance, Drain-to-Source for 7.0 mΩ power

Characteristic

Min

Typ

Max

Unit

channel

T_J= 25 °C, V_PWR≥ 24 V

—

7.0

—

12.9

13

mΩ

T_J= 150 °C, V_PWR≥ 24 V

T_J= 25 °C, V_PWR= –12 V

T_J= 150 °C, V_PWR= –12 V

18.2

R_DS(on)

ON-Resistance, Drain-to-Source for 17 mΩ power

channel

T_J= 25 °C, V_PWR≥ 24 V

T_J= 150 °C, V_PWR≥ 24 V

T_J= 25 °C, V_PWR= –12 V

T_J= 150 °C, V_PWR= –12 V

—

17

—

30.9

31

mΩ

43.5

I_LEAK

Sleep mode output leakage current (Output shorted

to GND) per channel

SLEEP

T_J= 25 °C, V_PWR= 24 V

T_J= 125 °C, V_PWR= 24 V

T_J= 25 °C, V_PWR= 35 V

T_J= 125 °C, V_PWR= 35 V

—

0.5

5.0

25

μA

I_{OUT OFF}

OFF operational output leakage current in OFF-state

per channel

T_J= 25 °C, V_PWR= 30 V

T_J= 125 °C, V_PWR= 30 V

—

10

20

μA

δ_PWM

Output PWM duty cycle range (measured at V_OUT

V_PWR/2

=

)

Low Frequency Range (25 to 100 Hz)

Medium Frequency Range (50 to 200 Hz)

High Frequency Range (100 to 400 Hz)

4.0

8.0

—

252

248

LSB

[1]

SR

Rising and falling edges slew rate at VPWR = 24 V

(measured from VOUT = 2.5 V to VPWR – 2.5 V)

Low Frequency Range

Medium Frequency Range

High Frequency Range

0.15

0.35

0.7

0.5

V/μs

1.05

[1]

ΔSR

t_DLY

Rising and falling edges slew rate matching at V_PWR

= 24 V (SRr/ SRf)

0.9

1.0

1.1

Turn-on and turn-off delay time at V_PWR= 24 V

μs

Low frequency range

Medium frequency range

High frequency range

20

10

70

30

120

50

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Table 10.ꢀElectrical characteristics...continued

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

[1]

Δt_DLY

Turn-on and turn-off delay time matching at V_PWR

24 V

=

Low frequency range

Medium frequency range

High frequency range

–20

–10

0.0

20

10

μs

t_{OUTPUT SD}Shutdown delay time in case of fault

0.5

2.5

4.5

μs

REFERENCE PWM CLOCK

f_CLK

Clock input frequency range

25.6

—

102.4

kHz

[1] With nominal resistive load: 2.5 Ω and 5.0 Ω respectively for 7.0 mΩ and 17 mΩ channel.

10.1.3 Output protections

The power outputs are protected against fault conditions in Normal and Fail mode in case

of:

• overload conditions

• harness short-circuit

• overcurrent and severe short-circuit

• overtemperature including overtemperature warning

• under and overvoltage

• charge pump failure

• reverse polarity

In case a fault condition is detected, the corresponding output is commanded off

immediately after the deglitch time t_{FAULT SD}. The turn off in case of a fault shutdown

(OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature

(fast turn off). The FTO:

• does not use edge shaping

• is provided with high slew rate to minimize the output turn-off time t_{OUTPUT SD}, in

regards to the detected fault

• uses a latch which keeps the FTO active during an undervoltage condition (0 ≤ V_PWR

V_{PWR UVF}

≤

)

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Figure 14.ꢀPower output switching in nominal operation and in case of fault

In case of a fault condition during Normal mode:

• the status is reported in the quick status register #1 and the corresponding channel

status register #2:#6.

To restart the output:

• the channel must be restarted by writing the corresponding ON bit in the channel

control register #2:#6 or output control register #8

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Figure 15.ꢀOutput control diagram in Normal mode

Fail mode

If an overcurrent (OCHI2, OCHI3, OCLO) or undervoltage is detected, the restart is

controlled by the autorestart feature.

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Figure 16.ꢀAutorestart in Fail mode

During overtemperature (OTSx), severe short-circuit (SSCx), or OCHI1 overcurrent,

the corresponding output enters the latch off state until the next wake-up cycle or mode

change.

Figure 17.ꢀOutput control diagram in Fail mode

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10.1.3.1 Overcurrent protections

Each output channel is protected against overload conditions by use of a multilevel

overcurrent shutdown.

Figure 18.ꢀTransient overcurrent profile

The current thresholds and the threshold window times are fixed for each type of

power channel. When the output is in PWM mode, these timings (tOCHI1:tOCHI3) are

accumulated at each On state period of the output.

In addition, a severe short-circuit protection (SSC) is implemented to limit the power

dissipation in Normal and Fail modes, in case of severe short-circuit event. This feature

is active only for a very short period of time, during OFF-to-ON transition. The load

impedance is monitored during the output turn-on. Each of the previously listed faults are

reported in the corresponding channel status register #2…#6, as shown in Table 11.

Table 11.ꢀChannel status register #2…#6

OC2x

OC1x

OC0x

Overcurrent status

no overcurrent

OCHI1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OCHI2

OCHI3

OCLO

OCHIOD

SSC

not used

Normal mode

The enabling of the high current window (OCHI1:OCHI3) is dependent on CHx signal.

When no control input pin is enabled, the control of the overcurrent window depends on

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the ON bits inside channel control registers #2:#7 or the output control register #8. When

the corresponding CHx signal is:

• toggled (turn OFF and then ON), the OCHI window counter resets and the full OCHI

windows is applied

• rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI

counter

Fail mode

The enabling of the high current window (OCHI1:OCHI3) is dependent on INx_ON toggle

signal. The enabling of output (OUT1:5) is dependent on CHx signal.

10.1.3.2 Overcurrent control programming

OCHI On Demand (OCHI OD)

In some instances, a lamp might be de-powered when its supply is interrupted by the

opening of a switch (as in a door), or by disconnecting the load (as for a supply dock). In

these cases, the driver should be tolerant of the inrush current occurring when the load is

reconnected and the channel is already ON. The OCHI On Demand feature allows such

control individually for each channel through the OCHI ODx bits inside the Initialization #2

register. When the OCHI ODx bit is:

• low (logic[0]), the channel operates in its Normal, Default mode. After end of OCHI

window timeout the output is protected with an OCLO threshold

• high (logic[1]), the channel operates in the OCHI On Demand mode and uses the

OCHI2 and OCHI3 windows and times after an OCLO event (when horizontal current

threshold OCLO is crossed, a new window with OCHI2&3 is started)

To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first

change the bit in the Initialization #2 register and then turn the channel off. The OCHI

ODx bit is also reset after an overcurrent event at the corresponding output. The fault

detection status is reported in the quick status register #1 and the corresponding channel

status registers #2:#6.

OCLO Threshold Setting

The static overcurrent threshold can be programmed individually for each output in

two levels to adapt low duty cycle dimming and a variety of loads. The CSNS recopy

factor and OCLO threshold depend on OCLO and ACM settings. The OCLO setting is

controlled by the OCLOx bits inside the overcurrent control register #10-1. When the

OCLOx bit is:

• low (logic[0]), the output is protected with the higher OCLO threshold (default status

and during Fail mode)

• high (logic[1]), the lower OCLO threshold is applied

Short OCHI

The length of the OCHI windows can be shortened by a factor of 2, to accelerate the

availability of the CSNS diagnosis and to reduce the potential stress inside the switch

during an overload condition. The setting is controlled individually for each output by the

SHORT OCHIx bits inside the overload control register #10-2. When the SHORT OCHIx

bit is:

• low (logic[0]), the default OCHI window times are applied (default status and during Fail

mode)

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• high (logic[1]), the short OCHI window times are applied (50 % of the regular OCHI

window time)

NO OCHI

Depending on the type of load in the output, the OCHI windows can be suppressed with

the NO OCHI feature. In that case, the output is protected with OCLO protection right

after the turn On and CSNS reporting is directly available. The switch on process of an

output can be done without an OCHI window, to accelerate the availability of the CSNS

diagnosis. The setting is controlled individually for each channel by the NO OCHIx bits

inside the overcurrent control register #10-2. When the NO OCHIx bit is:

• low (logic[0]), the regular OCHI window is applied (default status and during Fail mode)

• high (logic[1]), the turn on of the output is provided without OCHI windows

Thermal OCHI

To minimize the electro-thermal stress inside the device in case of a short-circuit, the

OCHI1 level can be automatically adjusted in regards to the control die temperature.

The functionality is controlled for all channels by the OCHI THERMAL bit inside the

initialization 2.

When the OCHI THERMAL bit is:

• low (logic[0]), the output is protected with default OCHI1 level

• high (logic[1]), the output is protected with the OCHI1 level reduced by R_{THERMAL OCHI}

=

20 % (typ) when the control die temperature is above T_{THERMAL OCHI}= 63 °C (typ.)

10.1.3.3 Electrical characterization

Table 12.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

POWER OUTPUTS OUT1:OUT5

I_OCHI1

I_OCHI2

I_OCHI3

I_OCLO

High overcurrent level 1 for 7.0 mΩ power channel

76

38

26

84

46

31

93

62

A

High overcurrent level 2 for 7.0 mΩ power channel

High overcurrent Level 3 for 7.0 mΩ power channel

35.5

Low overcurrent for 7.0 mΩ power channel

High level

Low level

17.6

8.8

21.9

10.8

26.4

13.2

A

I_{OCLO ACM}Low overcurrent for 7.0 mΩ power channel in ACM mode

High level

Low level

8.8

4.4

10.8

5.5

13.2

6.6

I_OCHI1

I_OCHI2

I_OCHI3

I_OCLO

High overcurrent level 1 for 17 mΩ power channel

High overcurrent Level 2 for 17 mΩ power channel

High overcurrent Level 3 for 17 mΩ power channel

32

38

44

A

18.5

11.0

22.5

13.5

26.5

15.7

Low overcurrent for 17 mΩ power channel

High level

Low level

8.8

4.4

10.8

5.5

13.2

6.6

A

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Table 12.ꢀElectrical characteristics...continued

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

I_{OCLO ACM}Low overcurrent for 17 mΩ power channel in ACM mode

High level

Low level

4.4

2.2

5.5

2.6

6.6

3.3

A

R_THERMALHigh overcurrent ratio 2

0.785

0.8

0.815

OCHI

T_THERMALTemperature threshold for IOCHI1 level adjustment

50

63

70

°C

OCHI

t_OCHI1

t_OCHI2

t_OCHI3

High overcurrent time 1

Default value

1.5

2.0

1.0

2.5

ms

Short OCHI option

0.75

1.25

High overcurrent time 2

Default value

6.0

3.0

8.0

4.0

10

ms

µs

Short OCHI option

5.0

High overcurrent time 3

Default value

48

24

64

32

80

40

Short OCHI option

[1]

t_{FAULT SD}Fault deglitch time

OCLO and OCHI OD

1.0

2.0

3.0

OCHI1:3 and SSC

t_AUTO

Fault autorestart time in Fail mode

48

64

80

ms

µs

RESTART

t_BLANKINGFault blanking time after wake-up

—

50

100

[1] Guaranteed by test mode.

10.1.3.4 Overtemperature protection

A dedicated temperature sensor is located on each power transistor, to protect the

transistors and provide SPI status monitoring. The protection is based on a two stage

strategy. When the temperature at the sensor exceeds the:

• selectable overtemperature warning threshold (T_OTW1, T_OTW2), the output stays on and

the event is reported in the SPI

• overtemperature threshold (T_OTS), the output is switched off immediately after the

deglitch time t_{FAULT SD}and the event is reported in the SPI after the deglitch time

t_{FAULT SD}

10.1.3.4.1 Overtemperature warning (OTW)

In case of an overtemperature warning:

• the output remains in current state

• the status is reported in the quick status register #1 and the corresponding channel

status register #2:#6

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The OTW threshold can be selected by the OTW SEL bit inside the initialization 2

register #1. When the bit is:

• low (logic[0]), the high overtemperature threshold is enabled (default status)

• high (logic[1]), the low overtemperature threshold is enabled

To delatch the OTW bit (OTWx):

• the temperature has to drop below the corresponding overtemperature warning

threshold

• a read command of the corresponding channel status register #2:#6 must be performed

10.1.3.4.2 Overtemperature shutdown (OTS)

During an overtemperature shutdown:

• the corresponding output is disabled immediately after the deglitch time t_{FAULT SD}

• the status is reported after t_{FAULT SD}in the quick status register #1 and the

corresponding channel status register #2:#6

To restart the output after an overtemperature shutdown event in Normal mode:

• the overtemperature condition must be removed, and the channel must be restarted by

a write command of the ON bit in the corresponding channel control register #2:#6, or

in the output control register #8

To delatch the diagnosis:

• the overtemperature condition must be removed

• a read command of the corresponding channel status register #2:#6 must be performed

To restart the output after an overtemperature shutdown event in Fail mode:

• a mode transition is needed. Refer to Section 9.5.5 "Mode transitions"

10.1.3.4.3 Electrical characterization

Table 13.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

POWER OUTPUTS OUT1:OUT5

[1]

T_OW

Overtemperature warning

T_OW1level

100

120

115

135

130

150

°C

μs

T_OW2level

T_OTS

Overtemperature shutdown

155

170

185

t_{FAULT SD}Fault deglitch time

OTS

2.0

5.0

10

[1] Guaranteed by test mode.

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10.1.3.5 Undervoltage and overvoltage protections

10.1.3.5.1 Undervoltage

During an undervoltage condition (V_PWRPOR≤ V_PWR≤ V_{PWR UVF}), all outputs

(OUT1:OUT5) are switched off immediately after deglitch time t_{FAULT SD}. The

undervoltage condition is reported after the deglitch time t_{FAULT SD}

:

• in the device status flag (DSF) in the registers #1:#7

• in the undervoltage flag (UVF) inside the device status register #7

Normal mode

The reactivation of the outputs is controlled by the microcontroller. To restart, the output

the undervoltage condition must be removed and:

• a write command of the ON Bit must be performed in the corresponding channel control

register #2:#6 or in the output control register #8

To delatch the diagnosis:

• the undervoltage condition must be removed

• a read command of the device status register #7 must be performed

Fail mode

When the device is in Fail mode, the restart of the outputs is controlled by the autorestart

feature.

10.1.3.5.2 Overvoltage

The overvoltage condition (V_PWR≥ V_{PWR OVF}) is reported in the:

• device status flag (DSF) in the registers #1:#7

• overvoltage flag (OVF) inside the device status register #7

To delatch the diagnosis:

• the overvoltage condition must be removed

• a read command of the device status register #7 must be performed

During an overvoltage (V_PWR≥ V_{PWR OVF}), the output stays in the ON state.

10.1.3.5.3 Electrical characterization

Table 14.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

SUPPLY VPWR

V_{PWR UVF}

Supply undervoltage

5.0

200

32

5.25

350

33.5

1.0

5.5

550

35

V

V_{PWR UVF HYS}Supply undervoltage hysteresis

mV

V

V_{PWR OVF}

Supply overvoltage

V_{PWR OVF HYS}Supply overvoltage hysteresis

0.5

32

1.5

—

V

V_{PWR HIGH}

Maximum supply voltage for short-circuit protection

—

V

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Table 14.ꢀElectrical characteristics...continued

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

t_{FAULT SD}

Fault deglitch time

UV and OV

2.0

3.5

6.0

µs

10.1.3.6 Charge pump protection

The charge pump voltage is monitored in order to protect the smart switches in case of:

• power up

• failure of external capacitor

• failure of charge pump circuitry

When a charge pump failure occurs, output control is no longer possible, and the status

reports after t_{FAULT SD}in the register Quick status #1 bit D7 (CPF flag) and on all output

registers #1…#7 (DSF flag).

To delatch the diagnosis:

• the charge pump failure condition must be removed

• a read command of the quick status register #1 is necessary

10.1.3.6.1 Electrical characterization

Table 15.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND =0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

CHARGE PUMP CP

C_CP

Charge pump capacitor range (Ceramic type X7R)

Maximum charge pump voltage

47

—

220

16

nF

V

V_{CP MAX}

t_{FAULT SD}Fault deglitch time

CPF

—

4.0

6.0

µs

10.1.3.6.2 Reverse supply protection

The device is protected against reverse polarity of the V_PWRline. In reverse polarity

condition:

• the output transistors OUT1:5 are turned ON in order to prevent the device from

thermal overload

• the OUT6 pin is pulled down to GND. An external current limit resistor must be added

in series with OUT6 pin

• no output protection is available in this condition

10.1.4 Digital diagnostics

The device offers several modes for load status detection in on state and off state

through the SPI.

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10.1.4.1 Openload detections

The device provides smart diagnostics for openload conditions: These diagnostics are

provided for each power output (OUT1…5), based on the current monitoring circuit.

Openload detection is reported:

• for the corresponding OUTx on the QSFx bit in the quick status register #1.

• In the global openload flag OLF (register #1…#7)

• In the OLON or OLOFF bit in the corresponding channel status register (#2…#6)

• For LED loads type with the OLLED feature (OLLED control register #13-2)

Openload detection is provided for the following output configuration:

10.1.4.1.1 Output is in the ON state

OLON flag is reported on the bit D1 of the corresponding channel status register if the

output current is below the following threshold:

• IOL threshold if the corresponding OLLED EN bit is low (register #13-2)

• IOLLED threshold if the corresponding OLLED EN bit is high

When openload detection in LED mode is enabled (OLLED ENx=1), the output current is

checked differently, depending on the output operation:

• When the output is fully On (100 % PWM), the comparison with IOLLED threshold is

done by user's demand by setting OLLED TRIG=1 on bit D5 of register OLLED control

(#13-2)

When the output is in PWM operation, the comparison with IOLLED threshold is done at

each Turn Off phase of each PWM cycle.

• In PWM operation, the OLON diagnosis available within δ_{PWM OLON}duty cycle range.

10.1.4.1.2 Output is in the OFF state

OLOFF flag is reported on the bit D0 of the corresponding channel status register if the

output current is below IOLOFF threshold. Openload OFF diagnostic is reported on at

the user's demand by setting the bit OLOFF ENx of the corresponding output to high

(logic[1]). Once the OLOFF ENx is set high, the corresponding output turns ON during

t_OLOFFand the output current is compared to I_OLOFF

:

• If the output current goes above IOLOFF within the t_OLOFFperiod, the output is turned

back to the Off state and a logic [0] is reported on the OLOFFx bit of CHx status

register #2…#6

• If the output current is below IOLOFF within the t_OLOFFperiod, a logic [1] is reported on

the OLOFFx bit of CHx status register #2…#6. The output is turned OFF at the end of

the t_OLOFFperiod.

To delatch the diagnosis, the openload condition must be removed and a read command

of the corresponding channel status register #2…#6 must be read.

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10.1.4.1.3 Electrical characterization

Table 16.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND =0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

POWER OUTPUTS OUT1…OUT5

I_OL

Openload current threshold in ON state

7.0 mΩ power channel

17 mΩ power channel

50

30

200

100

350

160

mA

δ_{PWM OLON}

Output PWM duty cycle range for openload detection

in ON state

Low frequency range (25 to 100 Hz)

Medium frequency range (100 to 200 Hz)

High frequency range (200 to 400 Hz)

18

17

—

LSB

I_OLLED

Openload current threshold in ON state/OLLED

mode

2.0

4.0

5.0

mA

ms

t_OLOFF

I_OLOFF

Openload detection time in OFF state

0.9

1.2

1.5

Openload current threshold in OFF state

7.0 mΩ power channel

0.77

1.1

1.43

A

17 mΩ power channel

0.385

0.55

0.715

10.1.4.2 Output shorted to V_PWRin OFF state

A short to VPWR detection during OFF state is provided individually for each power

output OUT1…OUT5, based on an output voltage comparator referenced to V_PWR/2

(VOUT DETECT) and an external pull-down circuitry. The detection result is reported in

the OUTx bits of the I/O status register #8 in real time. In case of UVF, the OUTx bits are

undefined.

10.1.4.2.1 Electrical characterization

Table 17.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND =0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

POWER OUTPUTS OUT1…OUT5

V_OUTDETECT

Output voltage comparator threshold

0.42

0.5

0.58

V_PWR

10.1.4.3 SPI fault reporting

Protection and monitoring of the outputs during normal mode is provided by digital switch

diagnosis via the SPI. The selection of the SO data word is controlled by the SOA0…

SOA3 bits inside the initialization 1 register #0. By default the quick status register #1 is

returned during write access on the SPI. SOA0…SOA3 selects the output register the

user wants to read. The 'quick status register' #1 provides one glance failure overview.

As long as no failure flag is set (logic[1]), no action by the microcontroller is needed.

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Register

SO address

SO data

D6 D5

RCF CLKF QSF5 QSF4 QSF3 QSF2 QSF1

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D4

D3

D2

D1

D0

quick

1

0

1

FM

DSF OVLF

OLF

CPF

address

• FM: Fail mode indication. This bit is also present in all other SO data words, and

indicates the fail mode by a logic[1]. When the device is in Normal mode, the bit is

logic[0]

• global device status flags (D10:D8): These flags are also present in the channel status

registers #2:#6, the device status register #7, and are cleared when all fault bits are

cleared by reading the registers #2:#7

• DSF: device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and

TMF are also reported in the device status register #7

• OVLF: over load flag (wired OR of all OC and OTS signals)

• OLF: openload flag

• CPF: charge pump flag

• RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset

• CLKF: clock fail flag. Refer to Section 10.3.3.2 "Logic I/O plausibility check"

• QSF1:QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx,

or OTSx, or OLONx, or OLOFFx)

The SOA address #0 is also mapped to register #1 (D15…D12 bits report logic [0001]).

When a fault condition is indicated by one of the quick status bits (QSF1…QSF5, OVLF,

OLF), the detailed status can be evaluated by reading of the corresponding channel

status registers #2…#6.

Register

SO address

SO data

D5

#

D15

D14

0

D13

1

D12

0

D11

FM

D10

D9

D8

D7

res

D6

D4

D3

D2

D1

D0

CH1 status

CH2 status

CH3 status

CH4 status

CH5 status

2

3

4

5

6

0

DSF OVLF

OLF

OTS1 OTW1 OC21 OC11 OC01 OLON1 OLOFF1

OTS2 OTW2 OC22 OC12 OC02 OLON2 OLOFF2

OTS3 OTW3 OC23 OC13 OC03 OLON3 OLOFF3

OTS4 OTW4 OC24 OC14 OC04 OLON4 OLOFF4

OTS5 OTW5 OC25 OC15 OC05 OLON5 OLOFF5

0

1

0

1

0

1

0

• OTSx: overtemperature shutdown flag

• OTWx: overtemperature warning flag

• OC0x…OC2x: overcurrent status flags

• OLONx: openload in ON state flag

• OLOFFx: openload in OFF state flag

The most recent OC fault is reported by the OC0x…OC2x bits, if a new OC occurs before

an old OC on the same output read. When a fault condition is indicated by one of the

global status bits (FM, DSF), the detailed status can be evaluated by reading of the

device status registers #7:

Register

SO address

SO data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

res

D5

D4

D3

D2

D1

D0

device

status

7

0

1

FM

DSF OVLF

OLF

res

TMF

OVF

UVF

SPIF

iLMP

• TMF: test mode activation flag. Test mode is used for manufacturing testing only. If this

bit is set to logic [1], the MCU must reset the device

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• OVF: overvoltage flag

• UVF: undervoltage flag

• SPIF: SPI fail flag

• iLIMP: real time reporting after the t_{IN_DGL}, not latched

The I/O status register #8 can be used for system test, fail mode test and the power

down procedure:

Register

SO address

SO data

D6

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D5

iIN1

D4

D3

D2

D1

D0

I/O status

8

1

0

FM

res

TOGGLE

iIN4

iIN3

iIN2

OUT5 OUT4 OUT3 OUT2 OUT1

The register provides the status of the control inputs, the toggle signal, and the power

outputs state in real time (not latched).

• TOGGLE: status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or

IN4_ON), reported in real time

• iINx: status of iINx signal (real time reporting after the tIN_DGL, not latched)

• OUTx: status of output pins OUTx (the detection threshold is V_PWR/2) when

undervoltage condition does not occur

10.1.5 Analog diagnostics

The analog feedback circuit (CSNS) is implemented to provide load and device

diagnostics during Normal mode. During Fail and Sleep modes, the analog feedback is

not available. The routing of the integrated multiplexer is controlled by MUX0:MUX2 bits

inside the initialization 1 register #0.

10.1.5.1 Output current monitoring

The current sense monitor provides a current proportional to the current of the selected

output (OUT1…OUT5). CSNS output delivers 1.0 mA full scale range current source

reporting channel 1…5 current feedback (IFSR).

Figure 19.ꢀOutput current sensing

The feedback is suppressed during OCHI window (t ≤ t_OCHI1+ t_OCHI2+ t_OCHI3) and only

enabled during low overcurrent shutdown threshold (OCLO). During PWM operation,

the current feedback circuit (CSNS) delivers current only during the on time of the output

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switch. Current sense settling time, t_CSNS(SET), varies with current amplitude. Current

sense valid time, t_CSNS(VAL), depends on the PWM frequency (see Section 10.1.5.5

"Electrical characterization").

An advanced current sense mode (ACM) is implemented to diagnose LED loads in

Normal mode and to improve current sense accuracy for low current loads. In the ACM

mode, the offset sign of current sense amplifier is toggled on every CSNS SYNCB

rising edge. The error amplifier offset contribution to the CSNS error can be fully

eliminated from the measurement result by averaging each two sequential current sense

measurements. The ACM mode is enabled with the ACM ENx bits inside the ACM

control register #10-1. When the ACM ENx bit is:

• low (logic[0]), ACM disabled (default status and during Fail mode)

• high (logic[1]), ACM enabled

In ACM mode:

• the precision of the current recopy feature (CSNS) is improved, especially at low output

currents by averaging CSNS reporting on sequential PWM periods

• the current sense full scale range (FSR) is reduced by a factor of two

• the overcurrent protection threshold OCLO is reduced by a factor of two

Figure 20 describes the timings between the selected channel current and the analog

feedback current. Current sense valid time pertains to stabilization time needed after

turn on. Current sense settling time pertains to the stabilization time needed after the

load current changes while the output is continuously on or when another output signal is

selected.

Figure 20.ꢀCurrent sensing response time

Internal circuitry limits the voltage of the CSNS pin when its sense resistor is absent.

This feature prevents damage to other circuitry sharing this electrical node, such as

a microcontroller pin, for example. Several 32XSG devices may be connected to one

shared CSNS resistor.

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10.1.5.2 Supply voltage monitoring

The V_PWRmonitor provides a voltage proportional to the supply tab. The CSNS voltage is

proportional to the V_PWRvoltage as shown in Figure 21.

Figure 21.ꢀSupply voltage reporting

10.1.5.3 Temperature monitoring

The average temperature of the control die is monitored by an analog temperature

sensor. The CSNS pin can report the voltage of this sensor. The chip temperature

monitor output voltage is independent of the resistor connected to the CSNS pin,

provided the resistor is within the min/max range of 5.0 kΩ to 50 kΩ. Temperature

feedback range, T_FB, –40 °C to 150 °C.

Figure 22.ꢀTemperature reporting

10.1.5.4 Analog diagnostic synchronization

A current sense synchronization pin is provided to simplify the synchronous sampling of

the CSNS signal. The CSNS SYNCB pin is an open drain requiring an external 5.0 kΩ

(min.) pull-up resistor to V_CC. The CSNS SYNCB signal is:

• available during Normal mode only

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• behavior depends on the type of signal selected by the MUX2…MUX0 bits in the

initialization 1 register #0. This signal is either a current proportional to an output

current or a voltage proportional to temperature or the supply voltage

Current sense signal

When a current sense signal is selected:

• the pin delivers a recopy of the output control signal during on phase of the PWM

defined by the SYNC EN0, SYNC EN1 bits inside the initialization 1 register #0

Table 18.ꢀCurrent sense signal details

SYNC EN1 SYNC EN0

Setting

OFF

Behavior

0

1

CSNS SYNCB is inactive (high)

VALID

CSNS SYNCB is active (low) when CSNS is valid. During switching the output

of MUX, the CSNS SYNCB is inactive (high)

1

0

1

TRIG0

As in setting VALID, but after a change of the MUX, the CSNS SYNCB is

inactive (high) until the next PWM cycle is started

TRIG1/2

Pulses (active low) from the middle of the CSNS pulse to its end are generated.

Switching phases (output and MUX) and the time from the MUX switching to the

next middle of the CSNS pulse are blanked (high)

• the CSNS SYNCB pulse is suppressed during OCHI and during OFF phase of the

PWM

• the CSNS SYNCB is blanked during settling time of the CSNS multiplexer and ACM

switching by a fixed time of t_DLY(ON)+ t_CSNS(SET)

• when a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty

cycle at a fixed period of 6.5 ms

• when the output is programmed with 100 % PWM, the CSNS SYNCB delivers a logic[0]

a high pulse with the length of 100 µs (typ.) during the PWM counter overflow for

TRIG0 and TRIG1/2 settings

• In case of an output fault, the CSNS SYNCB signal for current sensing does not deliver

a trigger signal until the output is enabled again

Temperature signal or V_PWRmonitor signal

When a voltage signal (average control die temperature or supply voltage) is selected:

• the CSNS SYNCB delivers a signal with 50 % duty cycle and the period of the lowest

prescaler setting (f_CLK/1024)

• and a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty

cycle at a fixed period of 6.5 ms (t_{SYNC DEFAULT}

)

10.1.5.5 Electrical characterization

Table 19.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the

approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

CURRENT SENSE CSNS

R_CSNS

I_{CSNS LEAK}

V_CS

Current sense resistor range

5.0

–1.0

6.0

—

50

+ 1.0

8.0

kΩ

μA

V

Current sense leakage current when CSNS is disabled

Current sense clamp voltage

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Table 19.ꢀElectrical characteristics...continued

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the

approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

I_FSR

Current sense full scale range for 7.0 mΩ power channel

High OCLO and ACM = 0

—

22

11

—

A

Low OCLO and ACM = 0

11

High OCLO and ACM = 1

5.5

Low OCLO and ACM = 1

ACC I_CSNS

Current sense accuracy for 7.0 V ≤ V_PWR≤ 30 V for 7.0 mΩ power channel

I_OUT= 80 % FSR

I_OUT= 25 % FSR

I_OUT= 10 % FSR

I_OUT= 5.0 % FSR

–11

–14

–20

–29

—

11

14

20

29

%

[1] [2]

I_CSNSMIN

Minimum current sense reporting for 7.0 mΩ

7.0 V < V_PWR< 30 V

—

1.0

%

A

I_FSR

Current sense full scale range for 7 mΩ power channel

High OCLO and ACM = 0

—

11

5.5

—

Low OCLO and ACM = 0

5.5

High OCLO and ACM = 1

2.75

Low OCLO and ACM = 1

[1]

ACCI_CSNS

Current sense accuracy for 7.0 V ≤ V_PWR≤ 30V for 17 mΩ power

channel

–11

–14

–20

–29

—

+11

+14

+20

+29

%

I_OUT= 80 % FSR

I_OUT= 25 % FSR

I_OUT= 10 % FSR

I_OUT= 5.0 % FSR

[1] [2]

I_CSNSMIN

Minimum current sense reporting for 17 mΩ

9.0 V ≤ V_PWR≤ 30 V

—

V_PWRMAX

–7.0

–40

—

1.0

40

%

V_PWR

Supply voltage feedback range

Supply feedback precision

V

ACC V_PWR

T_FB

—

+7.0

150

—

%

[3]

Temperature feedback range

—

°C

V_FB

Temperature feedback voltage at 25 °C

Temperature feedback thermal coefficient

—

2.31

7.72

V

COEF V_FB

ACC T_FB

—

mV/°C

Temperature feedback voltage precision

Default

–15

—

+15

°C

µs

–5.0

+5.0

1 calibration point at 25 °C and V_PWR= 7.0 V

[3]

[4]

t_CSNS(SET)

Current sense settling time

Current sensing feedback for I_OUTfrom 75 % FSR to 50 % FSR

Current sensing feedback for I_OUTfrom 10 % FSR to 1.0 %

FSR temperature and supply voltage feedbacks

—

40

260

20

t_CSNS(VAL)

Current sense valid time current sensing feedback

Low / medium frequency ranges for I_OUT> 20 % FSR

Low / medium frequency ranges for I_OUT≤ 20 % FSR

High frequency range for I_OUT> 20 % FSR

High frequency range for I_OUT≤ 20 % FSR

Temperature and supply voltage feedback

Supply voltage feedback

10

70

5.0

70

—

150

300

75

µs

300

12

—

15

t_{SYNC DEFAULT}Current sense synchronization period for PWM clock failure

4.8

6.5

8.2

ms

CURRENT SENSE SYNCHRONIZATION CSNS SYNCB

R_{CSNS SYNC}

V_OL

Pull-up current sense synchronization resistor range

5.0

—

0.4

kΩ

V

Current sense synchronization logic output low state level at 1.0 mA

I_{OUT MAX}

Current sense synchronization leakage current in tri-state (CSNS

SYNC from 0 to 5.5 V)

–1.0

+1.0

μA

[1] Precision either OCLO and ACM setting.

[2] Error of ±100 % without calibration for all modes and ±50 % with 1 calibration point done at 25 °C.

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[3] Parameter is derived mainly from simulations.

[4] Tested at 5.0 % of final value at VPWR = 14 V, current step from 0 A to 2.8 A (or 5.6 A). Parameter guaranteed by design at 1 % of final value.

10.2 Power supply functional block description and application

information

10.2.1 Introduction

The device is functional when wake = [1] with supply voltages from 5.5 V to 40 V (V_PWR),

but is fully specification compliant only between 7.0 V and 30 V. The VPWR pin supplies

power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.)

supplies the output register of the Serial Peripheral Interface (SPI) and the OUT6 driver.

Consequently, the SPI registers cannot be read without presence of V_CC. The employed

IC architecture guarantees a low quiescent current in Sleep mode (wake = [0]).

10.2.2 Wake state reporting

The CLK input/output pin is also used to report the wake state of the device to the

microcontroller as long as RSTB is logic [0].

When the device is in:

• "wake state" and RSTB is inactive, the CLK pin reports a high signal (logic[1])

• "sleep mode" or the device is wake by the RSTB pin, the CLK is an input pin

10.2.2.1 Electrical characterization

Table 20.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

CLOCK INPUT/OUTPUT CLK

V_OH

Logic output high state level (CLK) at 1.0 mA

V_CC– 0.6

—

V

10.2.3 Supply voltage disconnection

10.2.3.1 Loss of V_PWR

In case of V_PWRdisconnection (V_PWR≤ V_{PWR POR}) the device behavior depends on V_CC

voltage value:

• V_CC≤ V_{CC POR}: the device enters the power off mode. All outputs are shut off

immediately. All registers and faults are cleared

• V_CC> V_{CC POR}: all registers and faults are maintained. OUT1:5 are shut off

immediately. The ON/OFF state of OUT6 depends on the current SPI configuration.

SPI reporting is available when V_CCremains within its operating voltage range (4.5 V to

5.5 V)

The wake-up event is not reported to the CLK pin. The clamping structures (supply

clamp, negative output clamp) are available to protect the device. No current is

conducted from V_CCto V_PWR. An external current path must be available to drain the

energy from an inductive load, if a supply disconnection occurs when an output is ON.

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10.2.3.2 Loss of V_CC

In case of a V_CCdisconnection, the device behavior depends on V_PWRvoltage:

• V_PWR≤ V_{PWR POR}: the device enters the power off mode. All outputs are shut off

immediately. All registers and faults are cleared

• V_PWR> V_{PWR POR}: the SPI is not available. Therefore, the device enters WD timeout

The clamping structures (supply clamp, negative output clamp) are available to protect

the device. No current is conducted from V_PWRto V_CC

.

10.2.3.3 Loss of device GND

During loss of ground, the device cannot drive the loads, therefore the OUT1…OUT5

outputs are switched off and the OUT6 voltage is pulled up. The device might be

damaged in this failure condition where the load is inductive and V_PWRis above 28 V. For

protection of the digital inputs series resistors (1.0 kΩ typ.) can be provided externally in

order to limit the current to I_CL.

10.2.3.4 Electrical characterization

Table 21.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

3.0

—

Max

Unit

SUPPLY VPWR

V_{PWR POR}

VCC

Supply power on reset

2.0

4.0

V

V_{CC POR}

V_CCpower on reset

2.0

4.0

V

GROUND GND

V_{GND SHIFT}

Maximum ground shift between GND pin and load

ground

–1.5

+1.5

V

10.3 Communication interface and device control functional block

description and application information

10.3.1 Introduction

In Normal mode, the power output channels are controlled by the embedded PWM

module, which is configured by the SPI register settings. For bidirectional SPI

communication, V_CChas to be in the authorized range. Failure diagnostics and

configuration are also performed through the SPI port. The reported failure types

are: openload, short-circuit to supply, severe short-circuit to ground, overcurrent,

overtemperature, clock fail, and under and overvoltage. For direct input control, the

device must be in Fail-safe mode. V_CCis not required and this mode can be forced by the

LIMP input pin.

10.3.2 Fail mode input (LIMP)

The Fail mode of the component can be activated by LIMP direct input. The Fail mode

is activated when the input is logic [1]. In Fail mode, the channel power outputs are

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controlled by the corresponding inputs (INx). Even though the input thresholds are logic

level compatible, the input structure of the pins are able to withstand supply voltage level

(max. 40 V) without damage. External current limit resistors (1.0 kΩ, 10 kΩ) can be used

to handle reverse current conditions. The direct inputs have an integrated pull-down

resistor. The LIMP input has an integrated pull-down resistor. The status of the LIMP

input can be monitored by the LIMP IN bit inside the device status register #7.

10.3.2.1 Electrical characterization

Table 22.ꢀElectrical characteristics

Characteristics noted under conditions 4.5 V ≤ V_PWR≤ 5.5 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

FAIL MODE INPUT LIMP

V_IH

Logic input high state level

3.5

—

V

V_IL

Logic input low state level

1.5

+0.5

100

20

V

I_IN

Logic input leakage current in inactive state (LIMP = [0])

Logic input pull-down resistor

– 0.5

25

μA

kΩ

pF

R_PULL

C_IN

[1]

Logic input capacitance

—

DIRECT INPUTS IN1…IN4

V_IH

Logic input high state level

3.5

3.75

—

V

V_IH(WAKE)Logic input high state level for wake-up

V

V_IL

Logic input low state level

1.5

+0.5

100

20

V

I_IN

Logic input leakage current in inactive state (forced to [0])

Logic input pull-down resistor

–0.5

25

μA

kΩ

pF

R_PULL

C_IN

[1]

Logic input capacitance

—

[1] Parameter is derived mainly from simulations.

10.3.3 MCU communication interface protections

10.3.3.1 Loss of communication interface

If a SPI communication error occurs, the device is switched into Fail mode. A SPI

communication fault is detected if:

• the WD bit is not toggled with each SPI message or

• WD timeout is reached or

• protocol length error (modulo 16 check)

The SI stuck to static levels during CSB period and V_CCfail (SPI not functional) are

indirectly detected by a WD toggle error. The SPI communication error is reported in:

• SPI failure flag (SPIF) inside the device status register #7 in the next SPI

communication

As long as the device is in Fail mode, the SPIF bit retains its state. The SPIF bit is

delatched during the transition from fail-to-normal modes.

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10.3.3.2 Logic I/O plausibility check

The logic and signal I/O are protected against fatal mistreatment by a signal plausibility

check, according following table:

I/O

IN1 ~ IN4

LIMP

Signal check strategy

frequency above limit (low pass filter)

RSTB

CLK

The LIMP and IN1…IN4 have an input deglitch time t_{IN_DGL}= 200 µs (typical). If the LIMP

input is set to logic [1] for a delay longer than 200 µs (typ.), the device is switched into

Fail mode (internal signal called iLIMP).

Figure 23.ꢀLIMP and iLIMP signal

If the INx input is set to logic [1] for a delay longer than 200µs (typ.), the corresponding

channel is controlled by the direct signal (internal signal called iINx).

The RSTB has an input deglitch time t_{RST_DGL}= 10 µs (typ.) for the falling edge only. The

CLK has a symmetrical input deglitch time t_{CLK_DGL}= 2.0 µs (typical). Due to the input

deglitcher (at the CLK input) a very high input frequency leads to a clock fail detection.

The CLK fail detection (clock input frequency detection f_CLKLOW) is started immediately

with the positive edge of RSTB signal. If the CLK frequency is below f_{CLK LOW}limit, the

output state depends on the corresponding CHx signal. As soon as the CLK signal is

valid, the output duty cycle depends on the corresponding SPI configuration. To delatch

the CLK fail diagnosis:

• the clock failure condition must be removed

• a read command of the quick status register #1 must be performed

10.3.3.3 Electrical characterization

Table 23.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

LOGIC I/O LIMP IN1:IN4 CLK

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Table 23.ꢀElectrical characteristics...continued

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

t_WD

SPI watchdog timeout

WD SEL = 0

24

96

32

40

ms

WD SEL = 1

128

160

t_DGL

Input deglitching time

LIMP and IN1:IN4

CLK

150

1.5

7.5

200

2.0

10

250

2.5

μs

RSTB

12.5

f_{CLOCK LOW}

Clock low frequency detection

50

100

200

Hz

10.3.4 External smart power control (OUT6)

The device provides a control output to drive an external smart power device in Normal

mode only. The control is according to the channel 6 settings in the SPI input data

register.

• The protection and current feedback of the external SMARTMOS device are under the

responsibility of the microcontroller

• The output delivers a 5.0 V CMOS logic signal from V_CC

The output is protected against overvoltage. An external current limit resistor (1.0 kΩ,

10 kΩ) must be used to handle negative output voltage conditions. The output has

an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and

Fail mode. In case of a ground disconnection, the OUT6 voltage is pulled up. External

components are mandatory to define the state of external smart power device and to limit

possible reverse OUT6 current (resistor in series).

10.3.4.1 Electrical characterization

Table 24.ꢀElectrical characteristics

Characteristics noted under conditions 7.0 V ≤ V_PWR≤ 30 V, –40 °C ≤ T_A≤ 125 °C, GND = 0 V, unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise

noted.

Symbol

Characteristic

Min

Typ

Max

Unit

EXTERNAL SMART POWER OUTPUT OUT6

t_{OUT6 RISE}

OUT6 rising edge for 100 pF capacitive load

—

5.0

—

10

—

5.0

30

μs

kΩ

V

R_{OUT6 DOWN}OUT6 pull-down resistor

V_OH

V_OL

Logic output high state level (OUT6)

Logic output low state level (OUT6)

V_CC– 0.6

—

0.6

V

11 Typical applications

11.1 Introduction

The 32XSG is the latest achievement in DC motors and lighting drivers.

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11.1.1 Application diagram

Figure 24.ꢀAutomation system application

11.1.2 Bill of materials

Table 25.ꢀ32XSG Bill of materials

Signal

Location

Mission

Value^[1]

V_PWR

close to 32XSG improve emission and immunity performances

eXtreme switch

100 nF (X7R 50 V)

CP

close to 32XSG charge pump tank capacitor

eXtreme switch

100 nF (X7R 50 V)

V_CC

close to 32XSG improve emission and immunity performances

eXtreme switch

10 nF to 100 nF (X7R 16 V)

OUT1 to OUT5 close to output sustain ESG gun and fast transient pulses improve

10 nF to 22 nF (X7R 50 V)

connector

emission and immunity performances

CSNS

close to MCU

output current sensing

5.0 k (±1.0 %)

low pass filter removing noise

10 kΩ (±1.0%) and

10 nF (X7R 16 V)

CSNS SYNCB N/A

pull-up resistor for the synchronization of A/D

conversion

5.0 k (±1.0 %)

IN1 to IN4

OUT6

N/A

sustain high-voltage

1.0 kΩ (±1.0 %)

sustain reverse polarity

To sustain 5.0 V voltage regulator Failure mode

prevent high-voltage application on the MCU

V_CC

close to 5.0

V voltage

regulator

5.0 V Zener diode and

a bipolar transistor

[1] NXP does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While NXP

offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

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12 Packaging

12.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current

package outline drawing, go to nxp.com and perform a keyword search for the drawing’s

document number.

Table 26.ꢀPackage outline

Package

Suffix

Package outline drawing number

98ASA00368D

32-pin SOICEP

54-pin SOICEP

32-pin SOICEP

EK and DEK

BEK

98ASA00367D

98ASA00894D

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13 Revision history

Revision

1.0

Date

8/2016

7/2018

11/2018

Description of changes

• Initial release

2.0

• Added MC17XSG500BEK part and associated 98ASA00894D package information

3.0

• Updated as per CIN 201811005I

• Added footnote [1] to Table 8

• Added footnote [1] to Table 24

4.0

5.0

9/2020

7/2021

• Changed document status from Advance Information to Technical Data

• Added values for R_PULL-CSBto Table 8

• Updated the max value for R_{OUT6 DOWN}in Table 24 (replaced 20 by 30)

• Updated as per 202106018I

– Table 1: added MC07XSG517DEK and MC17XSG500DEK parts

– Section 10.1.3.2: replaced "R_{THERMAL OCHI}= 15 % (typ)" by "R_{THERMAL OCHI}= 20 % (typ)"

– Table 12: updated values for High overcurrent ratio 2 (R_THERMALOCHI

)

– Section 12.1: updated package drawings due to migration of devices from OHT Fab to ICN8,

and the change from etch to stamp lead frame

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14 Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

14.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP product has

been qualified for use in automotive applications. If this product is used

by customer in the development of, or for incorporation into, products or

services (a) used in safety critical applications or (b) in which failure could

lead to death, personal injury, or severe physical or environmental damage

(such products and services hereinafter referred to as “Critical Applications”),

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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then customer makes the ultimate design decisions regarding its products

and is solely responsible for compliance with all legal, regulatory, safety,

and security related requirements concerning its products, regardless of

any information or support that may be provided by NXP. As such, customer

assumes all risk related to use of any products in Critical Applications and

NXP and its suppliers shall not be liable for any such use by customer.

Accordingly, customer will indemnify and hold NXP harmless from any

claims, liabilities, damages and associated costs and expenses (including

attorneys’ fees) that NXP may incur related to customer’s incorporation of

any product in a Critical Application.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Export control — This document as well as the item(s) described herein

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NXP — wordmark and logo are trademarks of NXP B.V.

MC32XSG

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 21 July 2021

64 / 66

NXP Semiconductors

MC32XSG

Multi-purpose high-side switches

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Tab. 7.

Tab. 8.

Tab. 9.

Orderable parts ................................................. 3

Tab. 14. Electrical characteristics ..................................37

Tab. 15. Electrical characteristics ..................................38

Tab. 16. Electrical characteristics ..................................40

Tab. 17. Electrical characteristics ..................................40

Tab. 18. Current sense signal details ............................45

Tab. 19. Electrical characteristics ..................................45

Tab. 20. Electrical characteristics ..................................47

Tab. 21. Electrical characteristics ..................................48

Tab. 22. Electrical characteristics ..................................49

Tab. 23. Electrical characteristics ..................................50

Tab. 24. Electrical characteristics ..................................51

Tab. 25. 32XSG Bill of materials ...................................52

Tab. 26. Package outline ...............................................53

Pin description ...................................................6

Maximum ratings .............................................10

Thermal ratings ............................................... 11

Operating conditions ....................................... 11

Supply currents ............................................... 12

SPI input register and bit descriptions .............17

Electrical characteristics ..................................22

Global PWM Register ......................................25

Tab. 10. Electrical characteristics ..................................27

Tab. 11. Channel status register #2…#6 .......................32

Tab. 12. Electrical characteristics ..................................34

Tab. 13. Electrical characteristics ..................................36

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Simplified application diagram ...........................2

32XSG simplified internal block diagram ...........4

Pin configuration for 32-pin SOIC-EP

package .............................................................5

Pin configuration for 54-pin SOIC-EP

package .............................................................6

Ratings vs. operating requirements (VPWR

pin) .................................................................... 9

Ratings vs. operating requirements (VCC

pin) .................................................................. 10

Functional block diagram ................................ 13

General IC operating modes ...........................14

SPI input register ............................................ 18

Fig. 12. Timing diagram for serial output (SO) data

communication ................................................ 22

Fig. 13. Typical power output switching (slow and

fast slew rate) ................................................. 24

Fig. 4.

Fig. 5.

Fig. 6.

Fig. 14. Power output switching in nominal

operation and in case of fault ..........................29

Fig. 15. Output control diagram in Normal mode ..........30

Fig. 16. Autorestart in Fail mode ..................................31

Fig. 17. Output control diagram in Fail mode ............... 31

Fig. 18. Transient overcurrent profile ........................... 32

Fig. 19. Output current sensing ....................................42

Fig. 20. Current sensing response time ....................... 43

Fig. 21. Supply voltage reporting ................................. 44

Fig. 22. Temperature reporting .....................................44

Fig. 23. LIMP and iLIMP signal ....................................50

Fig. 24. Automation system application ........................52

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 10. SPI output register .......................................... 20

Fig. 11.

Timing requirements during SPI

communication ................................................ 21

MC32XSG

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 21 July 2021

65 / 66

NXP Semiconductors

MC32XSG

Multi-purpose high-side switches

Contents

1

2

3

4

5

6

7

7.1

7.2

8

General description ............................................ 1

10.1.3.5 Undervoltage and overvoltage protections .......37

10.1.3.6 Charge pump protection ..................................38

Features and benefits .........................................1

Simplified application diagram ..........................2

Applications .........................................................2

Ordering information .......................................... 3

Internal block diagram ........................................4

Pinning information ............................................ 5

Pinning ...............................................................5

Pin description ...................................................6

General product characteristics ........................ 9

Relationship between ratings and operating

requirements ......................................................9

Maximum ratings ............................................. 10

Thermal characteristics ....................................11

Operating conditions ........................................11

Supply currents ................................................11

General IC functional description and

10.1.4

Digital diagnostics ............................................38

10.1.4.1 Openload detections ........................................39

10.1.4.2 Output shorted to VPWR in OFF state ............ 40

10.1.4.3 SPI fault reporting ............................................40

10.1.5

Analog diagnostics ...........................................42

10.1.5.1 Output current monitoring ................................42

10.1.5.2 Supply voltage monitoring ............................... 44

10.1.5.3 Temperature monitoring ...................................44

10.1.5.4 Analog diagnostic synchronization ...................44

10.1.5.5 Electrical characterization ................................45

8.1

8.2

8.3

8.4

8.5

9

10.2

Power supply functional block description

and application information ..............................47

Introduction ...................................................... 47

Wake state reporting ....................................... 47

10.2.1

10.2.2

10.2.2.1 Electrical characterization ................................47

10.2.3 Supply voltage disconnection .......................... 47

application information .................................... 12

Introduction ...................................................... 12

Features ...........................................................12

Block diagram ..................................................13

Self-protected high-side switches .................... 13

Power supply ...................................................13

MCU interface and device control ................... 13

Functional description ......................................13

Modes of operation ..........................................14

Power Off mode .............................................. 14

Sleep mode ..................................................... 14

Normal mode ...................................................15

Fail mode .........................................................15

Mode transitions .............................................. 15

SPI interface and configurations ......................16

Introduction ...................................................... 16

SPI input register and bit descriptions ............. 16

SPI output register and bit descriptions ........... 19

Timing diagrams .............................................. 21

Electrical characterization ................................22

Functional block requirements and

9.1

9.2

9.3

9.3.1

9.3.2

9.3.3

9.4

10.2.3.1 Loss of VPWR .................................................47

10.2.3.2 Loss of VCC ....................................................48

10.2.3.3 Loss of device GND ........................................ 48

10.2.3.4 Electrical characterization ................................48

10.3

Communication interface and device

control functional block description and

application information .....................................48

Introduction ...................................................... 48

Fail mode input (LIMP) ....................................48

9.5

10.3.1

10.3.2

9.5.1

9.5.2

9.5.3

9.5.4

9.5.5

9.6

9.6.1

9.6.2

9.6.3

9.6.4

9.6.5

10

10.3.2.1 Electrical characterization ................................49

10.3.3 MCU communication interface protections ...... 49

10.3.3.1 Loss of communication interface ..................... 49

10.3.3.2 Logic I/O plausibility check .............................. 50

10.3.3.3 Electrical characterization ................................50

10.3.4

External smart power control (OUT6) .............. 51

10.3.4.1 Electrical characterization ................................51

11

Typical applications .......................................... 51

Introduction ...................................................... 51

Application diagram ......................................... 52

Bill of materials ................................................52

Packaging .......................................................... 53

Package mechanical dimensions .................... 53

Revision history ................................................ 62

Legal information ..............................................63

11.1

11.1.1

11.1.2

12

12.1

13

behaviors ........................................................... 23

Self-protected high-side switches

description and application information ............23

Features ...........................................................23

Output pulse shaping .......................................24

10.1

10.1.1

10.1.2

14

10.1.2.1 SPI control and configuration .......................... 24

10.1.2.2 Global PWM control ........................................ 25

10.1.2.3 Incremental PWM control ................................ 26

10.1.2.4 Input control .....................................................26

10.1.2.5 Electrical characterization ................................27

10.1.3

Output protections ........................................... 28

10.1.3.1 Overcurrent protections ................................... 32

10.1.3.2 Overcurrent control programming ....................33

10.1.3.3 Electrical characterization ................................34

10.1.3.4 Overtemperature protection .............................35

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described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 July 2021

Document identifier: MC32XSG


型号：	MC17XSG500EK
厂家：	NXP
描述：	Multi-purpose high-side switches
文件：	总66页 (文件大小：3311K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC17XSG500EK [NXP]

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