MC20XS4200BAFK [NXP]
High-Side Switch, 24V, Dual 20mOhms, PQFN 24, Tray;
| 型号： | MC20XS4200BAFK |
| 厂家： | 
NXP |
| 描述： | High-Side Switch, 24V, Dual 20mOhms, PQFN 24, Tray |
| 文件： | 总63页 (文件大小：1411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC20XS4200
Rev. 5.0, 11/2013
escale Semiconductor
Advance Information
Dual 24 V, 20 mOhm
Switch
High Side
20XS4200
The 20XS4200 device is part of a 24 V dual high side switch product
family with integrated control, and a high number of protective and
diagnostic functions. It has been designed for truck, bus, and industrial
applications. The low RDS(ON) channels (<20 m) can control different
load types; bulbs, solenoids, or DC motors. Control, device
HIGH SIDE SWITCH
configuration, and diagnostics are performed through a 16-bit serial
peripheral interface (SPI), allowing easy integration into existing
applications. This device is powered by SMARTMOS technology
Both channels can be controlled individually by external/internal
clock signals, or by direct inputs. Using the internal clock allows fully
autonomous device operation. Programmable output voltage slew-
rates (individually programmable) helps improve electromagnetic
compatibility (EMC) performance. To avoid shutting off the device upon
inrush current, while still being able to closely track the load current, a
dynamic overcurrent threshold profile is featured. Switching current of
each channel can be sensed with a programmable sensing ratio.
Whenever communication with the external microcontroller is lost, the
device enters a Fail-safe operation mode, but remains operational,
controllable, and protected.
FK SUFFIX (PB-FREE)
98ASA00428D
23 PIN PQFN
(12 X12 mm)
Features
• Two fully-protected 20 m (@ 25 °C) high side switches
• Up to 3.0 A steady-state current per channel
• Separate bulb and DC motor latched overcurrent handling
• Individually programmable internal/external PWM clock signals
• Overcurrent, short-circuit, and overtemperature protection with
programmable autoretry functions
• Accurate temperature and current sensing
• OpenLoad detection (channel in OFF and ON state), also for LED
applications (7.0 mA typ.)
• Normal operating range: 8.0 - 36 V, extended range: 6.0 - 58 V
• 3.3 V and 5.0 V compatible 16-bit SPI port for device control,
configuration and diagnostics at rates up to 8.0 MHz
VDD
VPWR
20XS4200
VDD
VDD
CLOCK
FSB
VPWR
I/O
I/O
SCLK
CSB
SI
SCLK
CSB
SO
RSTB
SI
IN0
HS0
HS1
LOAD
LOAD
MCU
I/O
SO
I/O
M
I/O
IN1
CONF0
CONF1
FSOB
SYNC
CSNS
I/O
A/D
A/D
GND
GND
Figure 1. Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2012-2013. All rights reserved.
ORDERABLE PARTS
ORDERABLE PARTS
Table 1. Simplified Orderable Part VariationsTable
Reverse Battery Negative Clamp
Orderable Part Number
Version
Slew Rate
Product ID Bit
Loss of Ground
Voltage (V)
Voltage (V)
MC20XS4200FK
MC20XS4200BFK (1)
MC20XS4200BAFK (1)
Notes
–
-28 V
-24 V
Hardware
Standard
01
00
B (2)
Hardward +
Software
-32 V
-32 V
BA (2), (3)
Accelerated
1. Recommended for all new designs
2. Version B and BA devices can support negative voltage battery and ground loss down to -32V, the overcurrent profile can be selected
by the SPI. It is no longer recommended to disable the off-state OpenLoad for the HS1 output in parallel mode, errata sheet MC24XS4ER
is no longer valid.
3. Version BA devices have faster slew rates to reduce switching losses.
20XS4200
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
Drain/Gate
Clamp
Internal
Regulator
Over/Undervoltage
Protections
VDD Failure
Detection
Charge
Pump
POR
I
UP
VREG
CSB
SCLK
Selectable Slew Rate
Gate Driver
I
DWN
Selectable Overcurrent
Detection
HS0
SO
SI
RSTB
Severe Short-circuit
Detection
Short-circuit to
VPWR detec.
FSB
IN0
Control
Logic
Overtemperature
Detect.
IN1
FSOB
OpenLoad
Detect
CONF0
CONF1
HS0
HS1
HS1
VREG
Calibratable
Oscillator *
PWM
Module
*
Temperature
Feedback
Output
Current Sense
CLOCK
I
DWN
Analog MUX
Overtemperature
Prewarning
*blocks marked in grey have been implemented
independently for each of both channels
GND
CSNS
SYNC
Figure 2. Internal Block Diagram
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TABLE OF CONTENTS
TABLE OF CONTENTS
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Assignment and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functional Internal Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operation and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Logic Commands and SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
20XS4200
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
PIN ASSIGNMENT
PIN ASSIGNMENT
Transparent Top View
SYNC
GND
VPWR
SO
GND
VPWR
23
22
21
16
17
18
GND
14
VPWR
15
19
20
HS1
HS0
PQFN Package
Figure 3. 20XS4200 Device Pin Assignments
The function of each pin is described in the section Functional Description
Table 2. 20XS4200 Pin Description
Pin
Pin Name
Function
Formal Name
Definition
Number
This pin either outputs a current proportional to the channel’s output current or
a voltage proportional to the temperature of the GND pin (pin 14). Selection
between current and temperature sensing, as well as setting the current
sensing sensitivity are performed through the SPI interface. An external pull-
down resistor must be connected between CSNS and GND.
1
CSNS
Output
Output Current/
Temperature
Monitoring
The IN[0:1] input pins are used to directly control the switching state of both
switches and consequently the voltage on the HS0:HS1 output pins. The pins
are connected to GND by internal pull-down resistors
2
3
IN0
IN1
Input
Output
Input
Direct Inputs
FSOB is asserted (active-low) upon entering Fail-safe mode (see Functional
Description) This open-drain output requires an external pull-up resistor to
VPWR
4
FSOB
Fail-safe Output
(Active Low)
The CONF[0:1] input pins are used to select the appropriate overcurrent
detection profile (bulb/DC motor) for each of both channels. CONF requires a
pull-down resistor to GND.
5
6
CONF0
CONF1
Configuration Input
This open-drain output pin (external pull-up resistor to VDD required) is set
when the device enters Fault mode (see Fault Mode)
7
8
FSB
Output
Input
Fault Status
(Active Low)
The clock input gives the time-base when the device is operated in external
clock/internal PWM mode.
CLOCK
PWM Clock
This pin has an internal pull-down current source.
This input pin is used to initialize the device’s configuration - and fault registers.
Reset puts the device in Sleep mode (low current consumption) provided it is
not stimulated by direct input signals.This pin is connected to GND by an
internal pull-down resistor.
9
RSTB
CSB
Input
Input
Reset
This input pin is connected to the SPI chip-select output of an external micro-
10
Chip Select
(Active Low)
controller. CSB is internally pulled up to VDD by a current source IUP
.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
PIN ASSIGNMENT
Table 2. 20XS4200 Pin Description (continued)
Pin
Pin Name
Function
Formal Name
Definition
Number
This input pin is to be connected to an external SPI Clock signal. The SCLK pin
is internally connected to a pull-down current source IDWN
11
SCLK
Input
Serial Clock
This input pin receives the SPI input data from an external device (micro-
controller or another extreme switch device in case of daisy-chaining). The SI
pin is internally connected to a pull-down current source IDWN
12
SI
Input
Serial Input
This is the positive supply pin of the SPI interface.
13
16
VDD
SO
Power
Output
Digital Drain Voltage
Serial Output
This output pin transmits SPI data to an external device (external micro-
controller or the SI pin of the next SPI device in case of daisy-chaining). The
pin doesn’t require external pull-up or pull-down resistors, but a series resistor
is recommended to limit current consumption in case of GND disconnection
These pins, internally connected, are the ground pins for the logic - and analog
circuitry. It is recommended to also connect these pins on the PCB.
14, 17, 22
15,18,21
GND
Ground
Power
Ground
These pins, internally connected, supply both the device’s power and control
circuitry (except the SPI port). The drain of both internal MOSFET switches is
connected to them. Pin 15 is the device’s primary thermal pad.
VPWR
Positive Power Supply
Output pins of the switches, to be connected to the load.
19
20
HS1
HS0
Output
Output
Power Switch Outputs
This output pin is asserted (active low) when the Current Sense (CS) output
signal is within the specified accuracy range. Reading the SYNC pin allows the
external micro-processor to synchronize to the device when operating in
autonomous operating mode. SYNC is open-drain and requires a pull-up
resistor to VDD.
23
SYNC
Output Current
Monitoring
Synchronization
20XS4200
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.
Parameter
Symbol
Maximum ratings
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage Range
Load Dump at 25 °C (500 ms)
Reverse Battery at 25 °C
20XS4200FK
VPWR
V
58
-28
-32
-60
20XS4200BFK, and 20XS4200BAFK
Fast Negative Transient Pulses (ISO 7637-2 pulse #1, VPWR=14 V & Ri=10 )
VDD Supply Voltage Range
VDD
VMAX,LOGIC
VFSO
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 58
-0.3 to VDD+0.3
58
V
V
V
V
V
V
Voltage on Input pins (4) (except IN[0:1]) and Output pins (5)) (except HS[0:1])
Voltage on Fail-safe Output (FSOB)
(4)
Voltage on SO pin
VSO
Voltage (continuous, max. allowable) on IN[0:1] Inputs
VIN,MAX
VHS[0:1]
Voltage (continuous, max. allowable) on output pins (HS [0:1])
20XS4200FK
-28 to 58
-32 to 58
20XS4200BFK, and 20XS4200BAFK
Rated Continuous Output Current per channel (6)
IHS[0:1]
3.0
A
Maximum allowable energy dissipation per channel and two parallel channels,
single-pulse method (7)
ECL[0:1]_SING
mJ
70
Notes:
4. Concerned Input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, and CSB.
5. Concerned Output pins are: CSNS, SYNC, and FSB.
6. Output current rating valid as long as maximum junction temperature is not exceeded. For computation of the maximum allowable output
current, the thermal resistance of the package & the underlying heatsink must be taken into account
7. Single pulse Energy dissipation, Single-pulse short-circuit method (LL = 0.5 mH, R = 48 mV
= 28 V, T = 150 C initial).
J
PWR
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.
Parameter
Symbol
Maximum ratings
Unit
ELECTRICAL RATINGS (CONTINUED)
ESD Voltage(8)
V
Human Body Model (HBM) for HS[0:1], VPWR and GND
Human Body Model (HBM) for other pins
Charge Device Model (CDM)
V
V
±8000
±2000
ESD1
ESD2
V
V
±750
±500
Package Corner pins
All Other pins
ESD3
ESD4
THERMAL RATINGS
Operating Temperature
Ambient
C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 150
0.32
C
C/W
C
Thermal Resistance Junction to Case Bottom / VPWR Flag Surface
Peak package reflow temperature during reflow(9),(10)
Notes:
R
JC
TPPRT
Note 10
8. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
9. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
10. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
20XS4200
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
SUPPLY ELECTRICAL CHARACTERISTICS
Supply Voltage Range:
VPWR
Full Specification compliant
Extended Mode(11)
8.0
6.0
24
–
36
58
V
V
Supply Current, device in wake-up mode, channel On, OpenLoad
IPWR(ON)
mA
mA
PWR
Outputs in ON-state, HS[0:1] open, IN[0:1] > V
–
6.5
8.0
IH
VPWR Supply Current, device in wake-up mode (Standby), channel Off
IPWR(SBY)
OpenLoad in OFF-state detection disabled, HS[0:1] shorted to ground
with VDD = 5.5 V and RSTB > VWAKE
MC20XS4200FK
MC20XS4200BAFK
–
–
6.5
6.5
8.0
8.5
Sleep State Supply Current
IPWR(SLEEP)
A
VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0:1] connected to ground
TA = 25 °C
–
–
3.0
–
10.0
60.0
TA = 125 °C
V
V
Supply Voltage
VDD(ON)
IDD(ON)
3.0
–
5.5
V
DD
DD
Supply Current at V
5.5 V
mA
DD =
No SPI Communication
8.0 MHz SPI Communication(12)
–
–
–
5.0
2.2
–
V
Sleep State Current at V
5.5 V with or without VPWR
DD =
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
–
–
5.0
45.5
1.5
6.0
4.0
2.5
2.8
A
V
DD
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
39
42
0.8
–
0.2
5.0
2.2
1.5
2.2
V
Undervoltage Shutdown Threshold(13)
V
V
V
V
Power-On-Reset (POR) Voltage Threshold(13)
VPWR(POR)
VDD(POR)
2.6
2.0
2.5
V
PWR
Power-On-Reset (POR) Voltage Threshold(13)
V
DD
DD
Supply Failure Voltage Threshold (assumed VPWR > VPWR(UV)
)
VDD(FAIL)
V
Notes
11. In extended mode, availability of several device functions (channel control, value of R
, overtemperature protection) is guaranteed,
DS(ON)
but compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal
shutdown). Above V , the channels can only be turned ON when the overvoltage detection function has been disabled.
PWR(OV)
12. Typical value guaranteed per design.
13. When the device recovers from undervoltage and returns to normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period
(see Auto-retry), the device performs normally. When VPWR drops below V
(Latchable Fault) and EMC Performances).
, undervoltage is detected (see Undervoltage Fault
PWR(UV)
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1)
ON-Resistance, Drain-to-Source (I = 3.0 A, T = 25 °C)
RDS(ON)25
RDS(ON)150
RDS(ON)150
m
HS
J
CSNS_ratio = 0
V
V
V
= 8.0 V
= 28 V
= 36 V
PWR
PWR
PWR
–
–
–
–
–
–
20
20
20
ON-Resistance, Drain-to-Source (I = 3.0 A,T = 150 °C)
m
m
HS
J
CSNS_ratio = 0
V
V
V
8.0 V
PWR =
–
–
–
–
–
–
36
36
36
= 28 V
= 36 V
PWR
PWR
ON-Resistance, Drain-to-Source difference from one channel to the other
in parallel mode (I = 1.0 A,T = 150 °C) CSNS_ratio = X
HS
J
-0.9
–
–
–
+0.9
36
ON-Resistance, Source-Drain (I = -3.0 A, T = 150 °C,
PWR
RSD(ON)150
LSHORT
m
HS
J
V
= -24 V)
Max. detectable wiring length (2.5 mm²) for severe short-circuit detection
(see Severe Short-circuit Fault (latchable fault)):
cm
20XS4200FK and 20XS4200BFK
High slew rate selected
50
100
200
130
260
500
300
600
1200
Medium slew rate selected
Low slew rate selected
20XS4200BAFK
30
55
110
100
175
365
180
300
620
High slew rate selected
Medium slew rate selected
Low slew rate selected
Overcurrent Detection thresholds with CSNS_ratio bit = 0 (CSR0)
I_OCH1_0
I_OCH2_0
I_OCM1_0
I_OCM2_0
I_OCL1_0
I_OCL2_0
I_OCL3_0
27.5
17.5
10.8
6.7
4.5
3.0
33.0
21.0
13.0
8.0
5.4
3.6
38.5
24.5
15.2
9.3
6.3
4.2
A
A
1.5
1.8
2.1
Overcurrent Detection thresholds with CSNS_ratio bit = 1(CSR1)
I_OCH1_1
I_OCH2_1
I_OCM1_1
I_OCM2_1
I_OCL1_1
I_OCL2_1
I_OCL3_1
9.2
5.8
3.6
2.2
1.5
1.0
0.48
11.0
7.0
4.3
2.7
1.8
1.2
0.6
12.8
8.2
5.1
3.1
2.1
1.4
0.72
20XS4200
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED)
Output (HS[x]) leakage Current in sleep state (positive value = outgoing)
20XS4200FK
IOUT_LEAK
µA
VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
–
–
–
+16
+5.0
-40.0
VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
20XS4200BFK and 20XS4200BAFK
–
–
–
–
+16
+5.0
+5.0
VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
VHS,OFF = VPWR, device in sleep state (VPWR = 36 V)
-120
-1400
Output biasing current in off-state (positive value = outgoing)
20XS4200BFK
IOUT_OFF
µA
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
-500
-370
-300
0
-400
-300
-250
-
-300
-230
-200
1000
Fast slew rate selected
Medium slew rate selected
Slow slew rate selected
With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V)
20XS4200BAFK
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
-620
-440
-330
-495
-360
-280
-380
-280
-230
Fast slew rate selected
Medium slew rate selected
Slow slew rate selected
Switch Turn-on threshold for Supply overvoltage (VPWR -GND)
VD_GND(CLAMP)
VDS(CLAMP)
58
58
–
–
66
66
V
V
Switch turn-on threshold for Drain-Source overvoltage (measured at
I
OUT = 500 mA
Switch turn-on threshold for Drain-Source overvoltage difference from
one channel to the other in parallel mode (@ IHS = 500 mA)
VDS(CLAMP)
-2.0
–
+2.0
V
–
Current Sensing Ratio(14)
CSNS_ratio bit = 0 (high current mode)
CSNS_ratio bit = 1 (low current mode)
CSR0
CSR1
–
–
1/1500
1/500
–
–
Minimum measurable load current with compensated error(15)
I_LOAD_MIN
ICSR_LEAK
–
–
–
50
mA
µA
CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0)
-4.0
+4.0
Systematic offset error (see Current Sense Errors)
20XS4200FK
I_LOAD_ERR_SYS
mA
–
–
5.5
-5
–
–
20XS4200BFK and 20XS4200BAFK
Random offset error
I_LOAD_ERR_RAND
-125
–
125
mA
Notes:
14. Current Sense Ratio CSRx = ICSNS / (IHS[x] +I_LOAD_ERR_SYS
)
15. See note (14), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation).
Further accuracy improvements can be obtained by performing a 1 or 2 point calibration.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED)
E
Output Current Sensing Error (%, uncompensated(16) at output
ESR0_ERR
%
SR0
Current level (Sense ratio CSR0 selected):
TJ=-40 C
-13
-12
-17
-31
–
–
–
–
13
12
17
31
3.0 A
1.5 A
0.75 A
0.375 A
TJ=125C
-10
-9.0
-12
-19
–
–
–
–
10
9.0
12
19
3.0 A
1.5 A
0.75 A
0.375 A
TJ=25 to 125C
-10
-9.0
-12
-19
–
–
–
–
-10
-9.0
-12
-19
3.0 A
1.5 A
0.75 A
0.375 A
E
Output Current Sensing Error (% after offset compensation(16) at
ESR0_ERR(Comp)
%
SR0
output Current level (Sense ratio CSR0 selected):
TJ=-40 C
-10
-10
-10
-10
–
–
–
–
10
10
10
10
3.0 A
1.5 A
0.75 A
0.375 A
TJ=125C
-9.0
-8.0
-8.0
-9.0
–
–
–
–
9.0
8.0
8.0
9.0
3.0 A
1.5 A
0.75 A
0.375 A
TJ=25 to 125C
-9.0
-8.0
-8.0
-9.0
–
–
–
–
9.0
8.0
8.0
9.0
3.0 A
1.5 A
0.75 A
0.375 A
Notes:
16. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see
section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
20XS4200
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED)
E
Output Current Sensing Error (%, uncompensated (17) at output
ESR1_ERR
%
SR1
Current level (Sense ratio CSR1 selected):
TJ=-40 C
0.75 A
-15
-12
-12
–
–
–
15
12
12
TJ=125C
0.75 A
TJ=25 to 125C
0.75 A
E
Output Current Sensing Error (% after offset compensation(18) at
%
SR1
output Current level (Sense ratio CSR1 selected):
ESR1_ERR(Comp)
TJ=-40 C
-10
-11
-18
-29
–
–
–
–
10
11
18
29
0.75 A
0.25 A
0.125 A
0.075 A
TJ=125C
-8.0
-10
-12
-16
–
–
–
–
8.0
10
12
16
0.75 A
0.25 A
0.125 A
0.075 A
TJ=25 to 125C
-8.0
-10
-13
-21
–
–
–
–
8.0
10
13
21
0.75 A
0.25 A
0.125 A
0.075 A
E
Output Current Sensing Error in parallel mode (%,
ESR0_ERR_PAR
%
SR0
uncompensated(19)) at outputs Current level (Sense ratio CSR0 selected):
TJ=-40 C
-10
-11
–
–
10
11
6.0 A
3.0 A
TJ=125C
-8.0
-8.0
–
–
8.0
8.0
6.0 A
3.0 A
TJ=25 to 125C
-8.0
-8.0
–
–
8.0
8.0
6.0 A
3.0 A
Notes:
17. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see
section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
18. See note (20), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation).
Further accuracy improvements can be obtained by performing a 1 or 2 point calibration
19. Minimum required value of OpenLoad impedance for detection of OpenLoad in OFF-state: 200 k.(VOLD(THRES) = VHS @ IOLD(OFF)
)
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED)
Current Sense Clamping Voltage (condition: R(CSNS) > 10 kOhm)
OpenLoad detection Current threshold in OFF state (20)
OpenLoad Fault Detection Voltage Threshold (20)
VCL(CSNS)
IOLD(OFF)
VOLD(THRES)
IOLD(ON)
5.5
30
–
–
–
7.5
100
5.5
V
A
V
4.0
OpenLoad detection Current threshold in ON state (see OpenLoad
Detection In On State (OL_ON)):
mA
CSNS_ratio bit = 0
20XS4200FK
60
40
5.0
150
150
7.0
300
300
10
20XS4200BFK and 20XS4200BAFK
CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this
function)
Time period of the periodically activated OpenLoad in ON state detection
for CSNS_ratio bit = 1
tOLLED
VOSD(THRES)
VCL
105
150
195
ms
V
Output Shorted-to-V
state)
Detection Voltage Threshold (channel in OFF
VPWR-1.2
VPWR-0.8 VPWR-0.4
PWR
Switch turn-on threshold for Negative Output Voltages (protects against
negative transients) - (measured at IOUT = 100mA, Channel in OFF state)
V
20XS4200FK
20XS4200BFK and 20XS4200BAFK
-35
-38
–
–
-24
-32
Switch turn-on threshold for Negative Output Voltages difference from
one channel to the other in parallel mode - (measured at IOUT = 100 mA,
Channel in OFF state)
VCL
V
-2.0
–
+2.0
Switching State (On/Off) discrimination thresholds
Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V)
Notes:
VHS_TH
TSD
0.45*VPWR 0.5*VPWR 0.55*VPWR
160 175 190
V
C
20. Minimum required value of OpenLoad impedance for detection of OpenLoad in OFF-state: 200 k.(VOLD(THRES) = VHS @ IOLD(OFF)
)
20XS4200
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS
Logic Input Voltage, High(21)
VIH
VIL
2.0
-0.3
1.0
5.0
5.0
25
–
–
5.5
0.8
2.2
20
V
V
Logic Input Voltage, Low(21)
Wake-up Threshold Voltage (IN[0:1] and RSTB)(22)
Internal Pull-down Current Source (on Inputs: CLOCK, SCLK and SI)(23)
Internal Pull-up Current Source (input CSB)(24)
Internal Pull-up Current Source (input CONF[0:1])(25)
Capacitance of SO, FSB and FSOB pins in Tri-state
Internal Pull-down Resistance (RSTB and IN[0:1])
Input Capacitance(26)
VWAKE
IDWN
–
V
–
A
A
A
pF
k
pF
V
IUP_CSB
IUP_CONF
CSO
–
20
–
100
20
–
–
RDWN
CIN
125
–
250
4.0
500
12
SO High-state Output Voltage
(IOH = 1.0 mA)
VSOH
VDD-0.4
–
–
–
–
SYNC, SO, FSOB and FSB Low-state Output Voltage
(IOL = -1.0 mA)
VSOL
V
0.4
2.0
SYNC, SO, CSNS, FSOB and FSB Tri-state Leakage Current:
(0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V
or V(CSNS) = 0.0 V
ISO(LEAK)
A
-2.0
0.0
CONF[0:1]: Required values of the External Pull-down Resistor
- Lighting applications
RCONF
k
1.0
50
–
–
10
Infinite
- DC motor applications
Notes
21. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from
PWR and can tolerate voltages up to 58 V.
V
22. Voltage above which the device wakes up
23. Valid for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V.
24. Valid for VCSB < 2.0 V. CSB has an internal pull-up current source derived from VDD
25. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V).
26. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing
process but is not tested in production.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
OUTPUT VOLTAGE SWITCHING CHARACTERISTICS
Rising and Falling edges medium slew rate (SR[1:0] = 00)(27)
20XS4200FK and 20XS4200BFK
VPWR = 16 V
SRR_00
SRF_00
V/s
0.164
0.28
0.34
–
–
–
0.65
0.79
0.90
VPWR = 28 V
V
PWR = 36 V
20XS4200BAFK
VPWR = 16 V
0.25
0.45
0.5
–
–
–
1.1
1.4
1.5
VPWR = 28 V
V
PWR = 36 V
Rising and Falling edges low slew rate (SR[1:0] = 01)(27)
20XS4200FK and 20XS4200BFK
VPWR = 16 V
SRR_01
SRF_01
V/s
0.081
0.14
0.17
–
–
–
0.32
0.395
0.45
VPWR = 28 V
V
PWR = 36 V
20XS4200BAFK
VPWR = 16 V
0.125
0.225
0.25
–
–
–
0.55
0.7
0.75
V
PWR = 28 V
VPWR = 36 V
Rising and Falling edges high slew rate / SR[1:0] = 10)(27)
20XS4200FK and 20XS4200BFK
VPWR = 16 V
SRR_10
SRF_10
V/s
0.29
0.55
0.68
–
–
–
1.30
1.58
1.80
V
PWR = 28 V
VPWR = 36 V
20XS4200BAFK
VPWR = 16 V
0.5
0.9
1.0
–
–
–
2.2
2.8
3.0
VPWR = 28 V
V
PWR = 36 V
Notes
27. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 resistive load (see Output Voltage Slew Rate
and Delay).
20XS4200
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
OUTPUT VOLTAGE SWITCHING CHARACTERISTICS (CONTINUED)
Rising/Falling edge slew rate matching (SRR /SRF)
16 V < VPWR < 36 V
SR
0.75
0.75
1.0
1.0
1.2
1.25
20XS4200FK
20XS4200BFK and 20XS4200BAFK
Edge slew rate difference from one channel to the other in parallel mode(28)
SR
20XS4200FK and 20XS4200BFK
16 V < VPWR < 36 V
SR[1:0] = 00
SR[1:0] = 01
SR[1:0] = 10
V/s
-0.1
-0.06
-0.14
0.0
0.0
0.0
+0.1
+0.06
+0.14
20XS4200BAFK
16 V < VPWR < 36 V
SR[1:0] = 10
-0.2
0.0
+0.2
Output Turn-ON and Turn-OFF Delays (medium slew rate: SR[1:0] = 00)(29)
16 V < VPWR < 36 V
tDLY_00
tDLY_01
tDLY_10
s
s
s
32
20
–
–
128
120
20XS4200FK and 20XS4200BFK
20XS4200BAFK
Output Turn-ON and Turn-OFF Delays (low slew rate / SR[1:0] = 01)(29)
16 V < VPWR < 36 V
59
40
–
–
245
240
20XS4200FK and 20XS4200BFK
20XS4200BAFK
Output Turn-ON and Turn-OFF Delays (high slew rate / SR[1:0] = 10)(29)
16 V < VPWR < 36 V
18
10
–
–
68
60
20XS4200FK and 20XS4200BFK
20XS4200BAFK
Turn-ON and Turn-OFF Delay time matching (tDLY(ON) - tDLY(OFF)
)
tRF_00
s
s
fPWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 00
-25
0.0
25
Turn-ON and Turn-OFF Delay time matching (tDLY(ON) - tDLY(OFF)
)
tRF_01
fPWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %,
SR[1:0] = 01
20XS4200FK and 20XS4200BAFK
20XS4200BFK
-50
-90
0.0
–
50
90
Notes
28. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 resistive load (see Output Voltage Slew Rate
and Delay).
29. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0:1] = 1) and the associated rising edge
of the output voltage up to: VHS[0:1] = VPWR / 2 (where RL = 10.0). Turn-OFF delay time is measured as time between a falling edge
of the channel control signal (IN[0:1] = 0) and the associated falling edge of the output voltage up to the instant at which:
VHS[0:1] = VPWR / 2 (RL = 10.0 )
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
OUTPUT VOLTAGE SWITCHING CHARACTERISTICS (CONTINUED)
Turn-ON and Turn-OFF Delay time matching (tDLY(ON) - tDLY(OFF)
)
tRF_10
s
fPWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %,
SR[1:0] = 10
-13
0.0
13
Delay time difference from one channel to the other in parallel mode(30)
t(DLY)
s
16 V < VPWR < 36 V
SR[1:0] = 00
20XS4200FK
20XS4200BFK and 20XS4200BAFK
SR[1:0] = 01
-21
-25
0.0
0.0
21
25
20XS4200FK
20XS4200BFK and 20XS4200BAFK
SR[1:0] = 10
-40
-50
0.0
0.0
40
50
20XS4200FK
20XS4200BFK and 20XS4200BAFK
-11
-12
0.0
0.0
11
12
Fault Detection Delay Time(31)
Output Shutdown Delay Time(32)
tFAULT
tDETECT
–
–
5.0
8.0
s
s
s
10.0
15.0
Current sense output settling Time for SR[1:0] = 00 (medium slew rate) (33)
16 V < VPWR < 36 V
tCSNSVAL_00
20XS4200FK and 20XS4200BFK
20XS4200BAFK
0.0
0.0
118
–
235
200
Current sense output settling Time for SR[1:0] = 01(low slew rate) (33)
16 V < VPWR < 36 V
tCSNSVAL_01
tCSNSVAL_10
tSYNCVAL_00
s
s
s
20XS4200FK and 20XS4200BFK
20XS4200BAFK
0.0
0.0
185
–
355
315
Current sense output settling Time for SR[1:0] = 10 (high slew rate) (33)
16 V < VPWR < 36 V
20XS4200FK and 20XS4200BFK
20XS4200BAFK
0.0
0.0
108
–
205
165
SYNC output signal delay for SR[1:0] = 00 (medium SR) (33)
20XS4200FK
20XS4200BFK
20XS4200BAFK
50
50
25
–
–
–
150
160
130
Notes
30. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 resistive load (see Output Voltage Slew Rate
and Delay).
31. Time required to detect and report the fault to the FSB pin.
32. Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured
between start of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR
33. Settling time ( = tCSNSVAL_XX), SYNC output signal delay ( = tSYNCVAL_XX) and Read-out delay ( = tSYNREAD_XX) are defined for a
stepped load current (100 mA< I(LOAD)<IOCLX A FOR CSNS_RATIO_S = 1, AND 300 mA< I(LOAD)<IOCLX A_0 FOR CSNS_RATIO_S = 0).
(see Figure 9 and Output Current Monitoring (CSNS))
20XS4200
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
OUTPUT VOLTAGE SWITCHING CHARACTERISTICS (CONTINUED)
SYNC output signal delay for SR[1:0] = 01 (low SR) (34)
tSYNCVAL_01
s
20XS4200FK
20XS4200BFK
20XS4200BAFK
80
80
50
–
–
–
290
320
250
SYNC output signal delay for SR[1:0] = 10 (high SR) (34)
tSYNCVAL_10
s
20XS4200FK
20XS4200BFK
20XS4200BAFK
24
22
10
–
–
–
80
80
65
Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate) (34)
20XS4200FK and 20XS4200BFK
tSYNREAD_00
tSYNREAD_01
tSYNREAD_10
µs
µs
µs
0.0
0.0
–
–
200
150
20XS4200BAFK
Recommended sync_to_read delay SR[1:0] = 01 (low slew rate) (34)
20XS4200FK and 20XS4200BFK
0.0
0.0
–
–
200
150
20XS4200BAFK
Recommended sync_to_read delay SR[1:0] = 10 (high slew rate) (34)
20XS4200FK and 20XS4200BFK
0.0
0.0
–
–
200
150
20XS4200BAFK
Upper overcurrent threshold duration
tOCH1
tOCH2
6.0
12.0
8.6
17.2
11.2
22.4
ms
ms
ms
Medium overcurrent threshold duration (CONF = 0; Lighting Profile)
Medium overcurrent threshold duration (CONF = 1; DC motor Profile)
tOCM1_L
tOCM2_L
48
96
67
137
87
178
tOCM1_M
tOCM2_M
48
96
67
137
87
178
FREQUENCY & PWM DUTY CYCLE RANGES (35)(protections fully operational, see Protective Functions)
Switching Frequency range - Direct Inputs
fCONTROL
fPWM_EXT
fPWM_INT
RCONTROL
0.0
20
–
–
–
–
1000
1000
1000
100
Hz
Hz
Hz
%
Switching Frequency range - External clock with internal PWM (recommended)
Switching Frequency range - Internal clock with internal PWM (recommended)
60
Duty Cycle range
0.0
Notes
34. Settling time ( = tCSNSVAL_XX), SYNC output signal delay ( = tSYNCVAL_XX) and Read-out delay ( = tSYNREAD_XX) are defined for a
stepped load current (100 mA< I(LOAD)<IOCLX A FOR CSNS_RATIO_S = 1, AND 300 mA< I(LOAD)<IOCLX A_0 FOR CSNS_RATIO_S = 0).
(see Figure 9 and Output Current Monitoring (CSNS))
35. In Direct Input mode, the lower frequency limit is 0 Hz with RSTB=5.0 V and 4.0 Hz with RSTB=0.0 V. Duty-cycle applies to instants at
which VHS = 50 % VPWR. For low duty-cycle values, the effective value also depends on the value of the selected slew rate.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
AVAILABILITY DIAGNOSTIC FUNCTIONS OVER DUTY CYCLE AND SWITCHING FREQUENCY
(protections & diagnostics both fully operational, see Diagnostic Features for the exact boundary values)
Available Duty Cycle Range, fPWM = 1.0 kHz high slew rate, PWM mode(36)
RPWM_1K_H
%
OL_OFF
OL_ON
OS
0.0
35
0.0
–
–
–
62
100
90
Available Duty Cycle Range, fPWM = 400 Hz, medium slew rate, PWM mode(36)
RPWM_400_M
%
%
%
OL_OFF
OL_ON
OS
0.0
21
0.0
–
–
–
81
100
88
Available Duty Cycle Range, fPWM = 400 Hz, high slew rate, PWM mode(36)
RPWM_400_H
OL_OFF
OL_ON
OS
0.0
14
0.0
–
–
–
84
100
95
Available Duty Cycle Range, fPWM = 200 Hz, low slew rate mode, PWM mode(36)
RPWM_200_L
OL_OFF
OL_ON
OS
0.0
15
0.0
–
–
–
86
100
93
AVAILABILITY DIAGNOSTIC FUNCTIONS OVER DUTY CYCLE AND SWITCHING FREQUENCY (CONTINUED)
(protections & diagnostics both fully operational, see Diagnostic Features for the exact boundary values)
Available Duty Cycle Range, fPWM = 200 Hz, medium slew rate, PWM mode(36)
RPWM_200_M
%
%
OL_OFF
0.0
11
0.0
–
–
–
90
100
94
OL_ON
OS
Available Duty Cycle Range, fPWM = 100 Hz in low slew rate, PWM mode(36)
OL_OFF
RPWM_100_L
0.0
8.0
0.0
–
–
–
93
100
96
OL_ON
OS
Deviation of the internal clock PWM frequency after Calibration(37)
Default output frequency when using an uncalibrated oscillator
Minimal required Low Time during Calibration of the Internal Clock through CSB
Maximal allowed Low Time during Calibration of the Internal Clock through CSB
Recommended external Clock Frequency Range (external clock/PWM Module)
Upper detection threshold for external Clock frequency monitoring
Lower detection threshold for external Clock frequency monitoring
Notes
AFPWM(CAL)
fPWM(0)
-10
280
1.0
70
–
+10
520
2.0
%
Hz
400
1.5
100
–
tCSB(MIN)
tCSB(MAX)
fCLOCK
s
130
512
930
10
s
15
kHz
kHz
kHz
fCLOCK(MAX)
fCLOCK(MIN)
512
5.0
730
7.0
36. The device can be operated outside the specified duty cycle and frequency ranges (basic protective functions OC, SC, UV, OV, OT
remain active) but the availability of the diagnostic functions OL_ON, OL_OFF, OS is affected.
37. Values guaranteed from 60 Hz to 1.0 kHz (recommended switching frequency range for internal clock operation).
20XS4200
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
TIMING: SPI PORT, IN[0]/ IN[1] SIGNALS & AUTORETRY
Required Low time allowing delatching or triggering sleep mode (direct input
mode)
tIN
175
217
250
310
325
400
ms
Watchdog Timeout for entering Fail-safe Mode due to loss of SPI contact(38)
tWDTO
ms
ms
Auto-Retry Repetition Period (when activated):
Auto_period bits = 00
Auto_period bits = 01
Auto_period bits = 10
Auto_period bits = 11
tAUTO_00
tAUTO_01
tAUTO_10
tAUTO_11
105
52.5
26.2
13.1
150
75
37.5
17.7
195
97.5
47.8
24.4
GND PIN TEMPERATURE SENSING FUNCTION
Thermal Prewarning Detection Threshold(39)
TOTWAR
TFEED
110
918
10.7
-15
125
1078
11.1
–
140
1238
11.5
+15
°C
mV
Temperature Sensing output voltage @ TA = 25 °C (470 < RCSNS < 10 k
Gain Temperature Sensing output @ TA = 25 °C (470 < RCSNS < 10 k(39)
Temperature Sensing Error, range [-40 °C, 150 °C], default(39)
DTFEED
mV/°C
°C
TFEED_ERRO
R
Temperature Sensing Error, [-40 °C, 150 °C] after 1 point calibration @ 25 °C(39)
TFEED_ERRO
-5.0
–
+5.0
°C
R_CAL
Notes
38. Only when the WD_dis bit set to logic [0] (default). Watchdog timeout defined from the rising edge on RST to rising edge HS[0,1]
39. Values were obtained by lab. characterization
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, -40 C TA 125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
SPI INTERFACE ELECTRICAL CHARACTERISTICS(40)
Maximum Operating Frequency of the Serial Peripheral Interface (SPI)(41)
Required Low-state Duration for reset RSTB (42)
fSPI
tWRSTB
tCSB
–
–
–
–
8.0
–
MHz
s
10
1.0
Required duration from the Rising to the Falling Edge of CSB (Required Setup
Time)(43)
–
s
Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)(43)
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(43)
Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)(43)
Required High State Duration of SCLK (Required Setup Time)(43)
Required Low State Duration of SCLK (Required Setup Time)(43)
SI to Falling Edge of SCLK (Required Setup Time)(44)
tENBL
tLEAD
5.0
500
60
50
50
15
30
–
–
–
–
–
–
–
–
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
tLAG
–
tWSCLKh
tWSCLKl
tSI(SU)
tSI(H)
–
–
–
Falling Edge of SCLK to SI (Required hold Time of the SI signal)(44)
–
SO Rise Time
CL = 80 pF
tRSO
20
SO Fall Time
CL = 80 pF
tFSO
–
–
20
ns
SI, CSB, SCLK, Max. Rise Time allowing operation at fSPI = 8.0 MHz(44)
SI, CSB, SCLK, Max. Fall Time allowing operation at fSPI = 8.0 MHz(44)
Time from Rising Edge of SCLK to reach a valid level at the SO pin(45)
Time from Falling Edge of CSB to reach low-impedance on SO (access time)(46)
Notes:
tRSI
tFSI
tVALID
tSOEN
–
–
–
–
–
–
–
–
11
11
44
30
ns
ns
ns
ns
40. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k
41. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V)
ceramic speed-up capacitors in parallel with the >8.0 k input resistors are required on pins SCLK, SI, SO, CS
42. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs
inactive).
43. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state.
44. Rise and Fall time of incoming SI, CSB, and SCLK signals.
45. Time required for output data to be available for use at SO, measured with a 1.0 kseries resistorconnected CSB.
46. Time required for output data to be terminated at SO measured with a 1.0 kseries resistorconnected CSB.
20XS4200
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
IN[0:1]
High Logic Level
Low Logic Level
Time
Time
or
CSB
High Logic Level
Low Logic Level
VHS[0:1]
RPWM range defined for 50% of VPWR
V
PWR
50%V
PWR
Time
tDLY_XX
(tDLY(OFF)
tDLY_XX
(tDLY(ON)
VHS[0:1]
)
)
80% V
PWR
SRF
SRR
20% V
PWR
Time
Figure 4. Output Voltage Slew Rate and Delay
Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V).
Static overcurrent protection profile activated once per turn-on.
Default levels shown as solid lines
I
OCH1
I
OCH2
I
OCM1
OCM2
Load
Current
I
I
I
OCL1
OCL2
I
OCL3
Time
t
t
OCM2_L
OCM1_L
t
OCH2
t
OCH1
Figure 5. Overcurrent Protection Profile for Bulb Applications
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
I
I
OCH1
Inductive Load profile:
CONFs = 1 (V (pin 5/6) > 2.0 V)
OCH2
Default levels shown as solid lines
Dynamic overcurrent window, activated
when the IOCLx threshold is crossed
Load
Current
I
OCL1
I
OCL2
Load current
Time
I
OCL3
t
OCM2_M
t
OCM1_M
t
OCH2
t
OCH1
Figure 6. Overcurrent Protection Profile for Applications with Inductive Loads (DC motors, solenoids)
RSTB
CSB
V
V
IH
IL
10% VDD
t
t
CSB
ENBL
t
WRSTB
90% VDD
V
V
IH
IL
10% VDD
t
RSI
t
WSCLKh
t
LAG
t
LEAD
V
V
IH
IL
90% VDD
10% VDD
SCLK
t
SI(SU)
t
WSCLKl
t
FSI
t
SI(H)
V
V
IH
IL
90% VDD
10% VDD
SI
Must be Valid
Don’t Care
Must be Valid
Don’t Care
Don’t Care
t
t
SOEN
SODIS
V
V
IH
IL
Tri-stated
Tri-stated
SO
Figure 7. Timing Requirements During SPI Communication
20XS4200
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
t
t
FSI
RSI
V
V
OH
OL
90% VDD
50%
SCLK
10% VDD
V
V
OH
OL
10% VDD
SO
t
RSO
Low to High
t
VALID
t
FSO
SO
V
V
OH
OL
High To Low
90% VDD
10% VDD
Figure 8. Timing Diagram for Serial Output (SO) Data Communication
turn-on
control
turn-off
control
(from IN_s or CSB)
(from IN_s or CSB)
VHS[0:1]
See Figure 4
V
PWR
50%V
PWR
Time
tDLY_XX
(tDLY(ON)
tDLY_XX
(tDLY(OFF
VCSNS
)
)
95% of scaled
output current
Track & Hold Mode
synchronous Mode
Time
Time
tSYNCVAL
VSYNC
5.0 V
tCSNSVAL_XX
tSYNREAD_XX
0.0 V
Figure 9. Synchronous & Track-and-Hold Current Sensing Modes: Associated Delay & Settling Times
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 20XS4200 is a two-channel, 24 V high side switch
with integrated control and diagnostics designed for truck,
bus, and industrial applications. The device provides a high
number of protective functions. Both low RDS(ON) channels
(<20 m) can independently drive various load types like
light bulbs, solenoid actuators, or DC motors. Device control
and diagnostics are configured through a 16-bit SPI port with
daisy chain capability.
Current sensing with an adjustable ratio is available on
both channels, allowing both high current (bulbs) and low
current (LED) monitoring. By activating the Track & Hold
Mode, current monitoring can be performed during the
switch-Off phase. This allows random access to the current
sense functionality. A patented offset compensation
technique further enhances current sense accuracy.
To avoid turning off upon inrush current, while being able
to monitor it, the device features a dynamic overcurrent
threshold profile. For bulbs, this profile is a stair function with
stages of which the height and width are programmable
through the SPI port. DC motors can be protected from
overheating by activating a specific window-shaped
Independently programmable output voltage slew rates
allow satisfying electromagnetic compatibility (EMC)
requirements.
Both channels can independently be operated in three
different switching modes: internal clock and internal PWM
mode (fully autonomous operation), external clock and
internal PWM mode, and direct control switching mode.
overcurrent profile that allow stall currents of limited duration.
Whenever communication with the external micro-
controller is lost, the device enters Fail-safe operation mode,
but remains operational, controllable, and protected.
PIN ASSIGNMENT AND FUNCTIONS
Functions and register bits that are implemented
independently for both channels have extension “_s”. Max.
ratings of the pins are given in Table 3.
CURRENT SENSE SYNCHRONIZATION (SYNC)
To synchronize current sensing with an external process,
the SYNC signal can be connected to a digital input of an
external MCU. SYNC is asserted logic low when the current
sense signal is accurate and ready to be read. The current
sense signal on the CSNS pin has the specified accuracy
tSYNREAD_XX seconds after the falling edge on the SYNC pin
(Figure 9) and remains valid until a rising edge is generated.
The rising edge that is generated by the SYNC pin at the turn-
OFF instant (internal or external) may also be used to
implement synchronization with the external MCU.
Parameter tSYNCVAL_XX is defined as the time between the
instant at the middle of the output-voltage rising edge
(HS[0:1] = 50% of VPWR), and the instant at which the
voltage on the SYNC-pin drops below 0.4 V (VSOL). The
SYNC pins of different devices can be connected together to
save µ-controller input channels. However, in this
OUTPUT CURRENT MONITORING (CSNS)
The CS pin allows independent current monitoring of
channel 0 or channel 1 up to the steady-state overcurrent
threshold. It can also be used to sense the device
temperature. The different functions are selected by setting
bits CSNS1_en and CSNS0_en to the appropriate value
(Table 23). When the CSNS pin is sensed during switch-off in
the (optional) track & hold mode (see Figure 9), it outputs the
scaled value of the load current as it was just before turn-Off.
When several devices share the same pull-down resistor, the
CSNS pins of devices the current of which is not monitored
must be tri-stated. This is accomplished by setting
CSNS0_en = 0 and CSNS1_en = 0 in the GCR register
(Table 10). Settling time (tCSNSVAL_XX) is defined as the time
between the instant at the middle of the output voltage’s
rising edge (HS[0:1] = 50% of VPWR), and the instant at which
the voltage on the CSNS-pin has settled to ±5.0% of its final
value. Anytime an overcurrent window is active, the CSNS
pin is disabled (see Overcurrent Detection on Resistive and
Inductive Loads). The current and temperature sensing
functions are unavailable in Fail-safe mode and in Normal
mode when operating without the VDD supply voltage. In
order to generate a voltage output, a pull-down resistor is
required (R(CSNS)=1.0 k typ. and 470 < R(CSNS) < 10 k).
When the current sense resistor connected to the CSNS pin
configuration, the CSNS function of only one device should
be active at a time. Otherwise, the MCU does not determine
the origin of the SYNC signal. The SYNC pin is open drain
and requires an external pull-up resistor to VDD.
DIRECT CONTROL INPUTS (IN0 AND IN1)
The IN[0:1] pins allow direct control of both channels. A
logic [0] level turns off the channel and a logic[1] level turns it
on (Channel Control in Normal Mode). When the device is in
Sleep mode, a transition from logic 0 to logic 1 on any of
these pins wake it up (Sleep Mode). If it is desired to
automatically turn on the channels after a transition to Fail-
safe mode, inputs IN[0] and IN[1] must be externally
is disconnected, the CSNS voltage is clamped to VCL(CSNS)
The CSNS pin can source currents up to about 5.6 mA.
.
connected to the VPWR pin by a pull-up resistor (e.g. 10 k
typ. However, this prevents the device from going into Sleep
20XS4200
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
PIN ASSIGNMENT AND FUNCTIONS
mode. Both IN pins are internally connected to a pull-down
resistor.
CHIP SELECT (CSB)
Data communication over the SPI port is enabled when the
CSB pin is in the logic [0] state. Data from the Input Shift
registers are locked in the addressed SI registers on the
rising edge of CSB. The device transfers the contents of one
of the eight internal registers to the SO register on the falling
edge of CSB. The SO output driver is enabled when CSB is
logic [0]. CSB should transition from a logic [1] to a logic [0]
state only when SCLK is at logic [0] (Figure 7 and Figure 8).
CONFIGURATION INPUTS (CONF0 AND CONF1)
The CONF[0:1] input pins allow configuring both channels
for the appropriate load type. CONF = 0 activates the bulb
overcurrent protection profile, and CONF = 1 the DC motor
profile. These inputs are connected to an internal voltage
regulator of 3.3 V by an internal pull-up current source IUP
.
CSB is internally pulled up to VDD through IUP
.
Therefore, CONF = 1 is the default value when these pins are
disconnected. Details on how to configure the channels are
given in Table 9.
SPI SERIAL CLOCK (SCLK)
The SCLK pin clocks the SPI data communication of the
device. The serial input pin (SI) transfers data to the SI shift
registers on the falling edge of the SCLK signal while data in
the SO registers are transferred to the SO pin on the rising
edge of the SCLK signal. The SCLK pin must be in low state
when CSB makes any transition. For this reason, it is
recommended to have the SCLK pin in the logic [0] state
when the device is not accessed (CSB is at logic [1]). When
CSB is set to logic [1], the signals at the SCLK and SI pins are
ignored and the SO output is tri-stated (high-impedance).
The SCLK pin is connected to an internal pull-down current
FAULT STATUS (FSB)
This open-drain output is asserted low when any of the
following faults occurs (see Fault Mode): overcurrent (OC),
overtemperature (OT), Output connected to VPWR, Severe
short-circuit (SC), OpenLoad in ON state (OL_ON),
OpenLoad in OFF state (OL_OFF), External Clock-fail
(CLOCK_fail), overvoltage (OV), undervoltage (UV). Each
fault type has its own assigned bit inside the STATR,
FAULTR_s, or DIAGR_s register. Fault type identification
and fault bit reset are accomplished by reading out these
registers. They are part of the SO register (Fault Mode) and
are accessed through the SPI port.
source IDWN
.
SERIAL INPUT (SI)
PWM CLOCK (CLOCK)
Serial input (SI) data bits are shifted in at this pin. SI data
is read on the falling edge of SCLK. 16-bit data packages are
required on the SI pin (see Figure 7), starting with bit D15
(MSB) and ending with D0 (LSB). All the internal device
registers are addressed and controlled by a 4-bit address
(D9-D12) described in Table 14. Register addresses and
function attribution are described in Table 15. The SI pin is
This pin is the input for an external clock signal that
controls the internal PWM module.The clock signal is
monitored by the device. The PWM module controls ON-time
and turn-ON delay of the selected channels. The CLOCK pin
should not be confused with the SCLK pin, which is the clock
pin of the SPI interface. CLOCK has an internal pull-down
current source (IDWN) to GND.
internally connected to a pull-down current source, IDWN
.
SUPPLY OF THE DIGITAL CIRCUITRY (VDD)
RESET (RSTB)
This pin supplies the SPI circuit (3.3 V or 5.0 V). When
lost, all circuitry becomes supplied by a VPWR derived
voltage, except the SPI’s SO shift-register that can no longer
be read.
All SPI register contents are reset when RSTB = 0. When
RSTB = 0, the device returns to Sleep mode tIN sec. after the
last falling edge of the last active IN[0:1] signal. As long as the
Reset input (RSTB pin) is at logic 0 and both direct input
states are low, the device remains in Sleep mode (Channel
configuration through the SPI). A 0-to-1 transition on RSTB
wakes up the device and starts a watchdog timer to check the
continuous presence of the SPI signals. To do this, the device
monitors the contents of the first bit (WDIN bit) of all SPI
words following that transition (regardless the register it is
contained in). When this contents is not alternated within a
duration tWDTO, SPI communication is considered lost, and
Fail-safe mode is entered (Entering Fail-safe Mode). RSTB is
GROUND (GND)
This is the GND pin common for both the SPI and the other
circuitry.
POSITIVE SUPPLY PIN (VPWR)
This pin is the positive supply and the common input pin of
both switches. A 100 nF ceramic capacitor must be
connected between VPWR and GND, close to the device. In
addition, it is recommended to put a ceramic capacitor of at
least 1.0 µF in parallel with this 100 nF capacitor.
internally pulled-down to GND by resistor RDWN
.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SERIAL OUTPUT (SO)
POWER SWITCH OUTPUT PINS (HS0 AND HS1)
The SO pin is a tri-stateable output pin that conveys data
from one of the 13 internal SO registers or from the previous
SI register to the outside world. The SO pin remains in a high-
impedance state (tri-state) until the CSB pin becomes
logic [0]. It then transfers the SPI data (device state,
configuration, fault information). The SO pin changes state at
the rising edge of the SCLK signal. For daisy-chaining, it can
be read out on the falling edge of SCLK. VDD must be present
before the SO registers can be read. The SO register
assignment is described in Table 13.
HS0 and HS1 are the output pins of the power switches, to
be connected to the loads. A ceramic capacitor (<= 22 nF (+/
- 20%) is recommended between these pins and GND for
optimal EMC performances.
FAIL-SAFE OUTPUT (FSOB)
This pin (active low) is used to indicate loss of SPI
communication or loss of SPI supply voltage, VDD. This open-
drain output requires an external pull-up resistor to VPWR.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER SUPPLY
internal regulator
SELF-
PROTECTED
HIGH SIDE
SWITCHES
MCU
MCU INTERFACE and
OUTPUT CONTROL
INTERFACE
HS0-HS1
SPI INTERFACE
PARALLEL CONTROL
INPUTS
PWM CONTROLLER
POWER SUPPLY
COMMUNICATION INTERFACE AND DEVICE
CONTROL
The device operates with supply voltages from 6.0 to 58 V
(VPWR), but is full spec. compliant between 8.0 and 36 V. The
VPWR pin supplies power to the internal regulator, analog,
and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the
output register of the Serial Peripheral Interface (SPI).
Consequently, the SPI registers cannot be read without
presence of VDD. The employed IC architecture guarantees
a low quiescent current in Sleep mode.
In Normal mode the output channels can either be
controlled by the direct inputs or by the internal PWM module,
which is configured by the SPI register settings. For
bidirectional SPI communication, VDD has to be in the
authorized range. Failure diagnostics and configuration are
also performed through the SPI port. The reported failure
types are: OpenLoad, short-circuit to battery, severe short-
circuit to ground, overcurrent, overtemperature, clock-fail,
undervoltage, and overvoltage. The SPI port can be supplied
either by a 5.0 V or by a 3.3 V voltage supply. For direct input
control, VDD is not required.
SWITCH OUTPUT PINS HS0 & HS1
HS0 and HS1 are the output pins of the power switches.
Both channels are protected against various kinds of short-
circuits and have active clamp circuitry that may be activated
when switching off inductive loads. Many protective and
diagnostic functions are available. For large inductive loads,
it is recommended to use a freewheeling diode. The device
can be configured to control the output switches in parallel,
which guarantees good switching synchronization.
A Pulse Width Modulation (PWM) circuit allows driving
loads at frequencies up to 1.0 kHz from an external or an
internal clock. SPI communication is required to set these
options.
20XS4200
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
The device possesses two high side switches (channels)
each of which can be controlled independently. The device
has four fundamental operating modes: Sleep, Normal, Fail-
safe, and Fault mode, as shown in Table 6.
reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG
registers (see section Serial Output Register Assignment and
beyond).
NORMAL MODE
Each channel can be controlled in three different ways in
Normal mode: by a signal on the Direct Input pin, by an
internal clock signal (autonomous operation) or by an
external clock signal. For bidirectional SPI communication, a
second supply voltage is required (VDD = 5.0 V or 3.3 V).
When only the direct inputs IN[x] are used, VDD isn’t required.
Normal mode (bit NM = 1) can be entered in two ways:
either by driving the device through the direct inputs (IN[x]) or
by establishing SPI communication (requires RSTB =high).
Bidirectional SPI communication additionally requires the
presence of VDD. To maintain the device in Normal mode,
communication must take place regularly (see Entering and
Maintaining Normal Mode). The device is in Normal mode
(NM) when:
DEVICE START-UP SEQUENCE
To put the device in a known configuration and guarantee
predictable behavior, the device must undergo a wake-up
sequence. However, it should not be woken up earlier than
the moment at which VPWR has exceeded its undervoltage
threshold, VPWR(UV), and VDD has exceeded its supply
failure threshold, VDD(FAIL). In applications using the SPI
port, the device is typically put in wake mode by setting
RSTB=1. Wake-up of applications with direct input control
can be achieved by having signals IN_ON[0] = 1 or
IN_ON[1 ]= 1 (see Figure 10). After wake-up, all SPI register
contents are reset (as defined in Table 12 and Table 13) and
Normal mode is entered. All the device functions are
available 50 µs later (typically).
• VPWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• fault = 0.
Channel Control in Normal Mode
In direct input mode, the channel’s switching state (On/Off)
is controlled by the logic state of the direct input signal with
the default values (00) of turn-on delay and slew rate,
specified in Table 5.
In internal clock mode, the switching state is controlled by
an internal clock signal (Internal Clock & Internal PWM
(Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and
turn-on delay are programmable independently for both
channels.
If the start-up sequence is not performed at device start-
up, its configuration may be undetermined and correct
operation is not guaranteed. In situations where the above
described start-up sequence can not be performed, it is
recommended to generate a wake-up event after the moment
VPWR has reached the undervoltage threshold.
In external clock mode, the frequency of the external clock
controls the output's PWM frequency, but slew rate, duty-
cycle, and turn-on delay are still programmable.
CHANNEL CONFIGURATION THROUGH THE SPI
Setting the Channel Configuration
Factors Determining the Channel’s Switching State
The switching state of a channel is defined by the
instantaneous value of the output voltage. It is defined as
“On” when the output voltage V(HS[x]) > VPWR /2 and “Off”
when V(HS[x]) < VPWR /2. The channel’s switching state
should not be confused with the device’s internal channel
control state hson[x] (= High Side On). Signal hson[x] defines
the targeted switching state of the channel (On/Off). It is
either controlled by the value of the direct input signal or by
that of the internal/external clock signals combined with the
SPI register settings. The value of hson[x] is given by the
following boolean expression:
The channel configuration is determined by the contents of
the pulse-width (PWMR_s), the configuration (CONFR_s)
and the overcurrent (OCR_s) registers. They allow setting,
among others, the following parameters: duty-cycle, delay,
Slew Rate, PWM enable (PWM_en), clock selection
(CLOCK_sel), prescaler (PR), and direct_input disable
(DIR_dis). Extension “_s” means that these registers exist for
each of both channels. Function assignment is described in
detail in the section SI Register Addressing.
hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and
Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and
PWM_en[x] = 0)].
Reading Back the Channel’s Status and Settings
The channel’s global switching and operating states (On/
Off, normal/fault) are all contained in the SO-STATR register
(see Table 16). The precise fault type can be found by
reading out the FAULTR_s and STATR registers. The current
channel settings (channel configuration) can be known by
In this expression Duty_cycle[x] represents the value of the
duty cycle, set by bits D7…D0 of the PWMR register
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
(Table 7). The channel’s actual switching state may differ
from the control signal’s state in the following cases:
Direct Control Mode
When RSTB = 0 (and also in Fail-safe mode), the channels
are merely controlled by the direct input pins IN[x]. All
protective functions (OC, OT, SC, OV, and UV) are
operational including auto-retry. To avoid entering Sleep
mode at frequencies < 4.0 Hz, reset should be set to
RSTB = 1.
• short-circuits to GND, before automatic turn-Off (t <
tFAULT
)
• short-circuits to VPWR when the channel is set to Off
• VPWR < 13 V when OpenLoad in Off-state detection is
selected and the load is actually lost
• during the turn-on transition as long as V(HS[x])< VPWR/2
• during the turn-off transition as long as V(HS[x]) > VPWR/2
Going from Normal to Fail-safe, Fault or Sleep Mode
The device changes from Normal to Fail-safe (Fail-safe
Mode), Sleep mode (Sleep Mode), or Fault mode (Fault
Mode), according to the value of the following signals (see
Table 6).
Entering and Maintaining Normal Mode
A 0-to-1 transition on RSTB, (when both VPWR and VDD
are present) or on any of both direct inputs IN[x] (when only
supplied by VPWR) puts the device in Normal mode. If
desired, the device can be operated in Normal mode without
VDD, but this requires that at least one of both direct inputs be
regularly turned on (Operation and Operating Modes). To
maintain the device in Normal mode (NM), communication
must take place on a regular basis.
• wake-up = RSTB or IN_ON[0] or IN_ON[1]
• fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI
watchdog timeout (tWDTO) and WD_dis = 0)
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and
OV_dis)
For SPI communication, the state of the WDIN bit must be
alternated at least every 310 ms (typ.) (tWDTO), unless the
WD_disable bit is set to 1.
Table 6. Device Operating Modes
Fail-
Wake-up
Fault Comments
Mode
safe
For direct input control, the timing requirements are shown
in Figure 10. A signal called IN_ON[x] is not directly
accessible to the user but is used by the internal logic circuitry
to determine the device state. When no activity is detected on
a direct input pin (IN[x]) for a time longer than tIN = 250 ms
(typ.), timeout is detected and IN_ON[x] goes low. When this
occurs on both channels, Sleep mode is entered (Sleep
Mode), provided reset = RSTB = 0.
All channels are OFF.
Sleep
0
1
x
x
The SPI Watchdog is active
when: VDD = 5.0 V,
WD_dis = 0, RSTB = 1
Normal
0
0
The channels are controlled by
the IN inputs. (see Fail-safe
Mode)
Fail-safe
Fault
1
1
1
0
1
The channels are OFF, see
Fault Mode.
X
.
x = Don’t care.
tIN
It enters Fail-safe mode in case of a timeout on SPI
communication or when VDD is lost after having been initially
present (if this function was previously enabled by setting:
IN[x]
IN_ON[x]
VDD FAIL EN bit = [1]). Setting watchdog disabled
_
_
(WD_dis = 1, D4 of the GCR register) avoids entering Fail-
safe mode after watchdog timeout. Device behavior upon
fault occurrence is explained in the paragraph on Faults
(Fault Mode).
Figure 10. Relation Between Signals IN(x) and IN_ON[x]
20XS4200
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
(fail-safe = 0) and (wake-up = 1) and (fault = 0)
Sleep
(wake-up = 0)
(wake-up = 1) and
(fail-safe = 1)
and (fault = 0)
(wake-up = 0)
(wake-up = 1)
and (fault = 1)
(wake-up = 0)
(fail-safe = 0) and
(wake-up = 1)and
(fault = 1)
(fail-safe = 1) and
(wake-up = 1)
and (fault = 1)
Fault
Normal
Fail-safe
(fail-safe = 0) and (wake-
up = 1) and (fault = 0)
(fail safe = 1) and
(wake-up = 1) and
(fault = 0)
(fail-safe = 0) and (wake-up = 1) and (fault = 0)
(fail-safe = 1) and (wake-up = 1) and (fault = 0)
Figure 11. Device Operating Modes
protective functions remain fully operational. Previously
latched faults are delatched and SPI register contents is reset
(except bits POR & PARALLEL). The SPI registers can not
be accessed. These conditions are also described by the
following expressions:
SLEEP MODE
In Sleep mode, the channels and the SPI interface are
turned off to minimize current consumption.
The device enters Sleep mode (wake-up = 0) when both
Direct Input pins IN(x) remain Off longer than tIN sec. (when
reset is active; RSTB = 0). This is expressed as follows:
• VPWR is within the normal voltage range, and
• wake-up = 1, fault = 0, and
• fail-safe = 1 ((VDD Failure and VDD_FAIL_en=1 before)
or (t(SPI)> tWDTO and WD_dis = 0).
• VPWR (and VDD) are within the normal range, and
• wake-up = 0 (wake-up = RSTB or IN_ON[0] or
IN_ON[1])
• and
• fail-safe = X and
• fault = X
The last condition describes the loss of SPI
communication which is detailed in the next section.
Watchdog on SPI Communication and Fail-safe Mode
When employed, VDD must be kept in the normal range.
Sleep mode is the default mode after the first application of
the supply voltage (VPWR), prior to any I/O communication
(RSTB and the internal states IN_ON[0:1] are still at logic [0]).
All SPI register contents remain in their default state during
sleep mode.
When VDD is present, the SPI watchdog timer is started
upon a rising edge on the RSTB pin. Thereafter the device
monitors the state of the first bit (WDIN) of all received SPI
words. When the state of this bit is not alternated at least
once within a data stream of duration tWDTO = 310 ms typ.,
the device considers that SPI communication has been lost
and enters Fail-safe mode. This behavior can be disabled by
setting the bit WD_DIS = 1. The value of watchdog timeout is
derived from an internal oscillator.
FAIL-SAFE MODE
Entering Fail-safe Mode
Fail-safe mode is entered either upon loss of SPI
Returning from Fail-safe to Normal mode
communication or after loss of optional SPI supply voltage
VDD (VDD Out of Range). The FSOB pin goes low and the
channels are only controlled by the direct inputs (IN[0:1]). All
To exit Fail-safe mode and return to normal mode again,
first a SPI data word with its WDIN bit = 1 (D15) must be
received by the device (regardless the register it is contained
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
in and regardless the values of the other bits in this register).
Next, a second data word must be received within the timeout
period (tWDTO = 310 ms typ.) to be able to change any SPI
register contents. Upon entering Normal mode, the FSOB pin
returns to logic high and previously set faults and SPI
registers are reset, except bits POR, PARALLEL and fault
bits of latchable faults that had actually been latched.
Returning from Fault Mode to Fail-safe Mode
When disappearance of the fault previously produced in Fail-
safe mode has been detected, the device returns to Fail-safe
mode and behaves accordingly. FSB goes high, but the auto-
retry counter is not reset. Latched faults are not delatched.
SPI registers remain reset.
FAULT MODE
LATCHABLE FAULTS
The device enters Fault mode when any of the following
faults occurs in Normal or Fail-safe mode:
An auto-retry function (see Auto-retry) controls how the
device responds to the so-called latchable faults. Latchable
faults are: overcurrent (OC), severe short-circuit (SC),
overtemperature (OT), and undervoltage (UV). If a latchable
fault occurs, the channel is turned off, the FSB terminal goes
low, and the assigned fault bit is set. These bits can not be
reset before the next turn-on event is generated by auto-retry.
Next, the channel automatically turns on at a programmable
interval (provided auto-retry was enabled and the channel
wasn’t latched).
• Overtemperature fault, (latchable fault)
• Overcurrent fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to VPWR in OFF state (default: disabled)
• OpenLoad fault in OFF state (default: disabled)
• OpenLoad fault in ON state (default: disabled)
• External Clock Failure (default: enabled)
• Overvoltage fault (enabled by default)
• Undervoltage fault, (latchable fault)
If the failure disappears prior to the expiration of the
available amount of auto-retries, the FSB pin automatically
returns to logic [1], but the fault bit remains set. It can then still
be reset by reading the SPI register it is contained in.
The Fault Status pin (FSB) asserts a fault occurrence on
any channel in real time (active low). Additionally, the
assigned fault bit in the STATR_s or FAULTR_s register is
set to one. Conversely to the FSB pin, a fault bit remains set
until the corresponding register is read, even if the fault has
disappeared. These bits can be read via the SO pin. Fault
occurrence results in a turn-off of the incurred channel,
except for the following faults: OpenLoad (On and Off state),
External Clock Failure and Output(s) shorted to VPWR. Under
and overvoltage occurrences cause simultaneous turn-off of
both channels. Details on the device’s behavior after the
occurrence of one of the above faults can be found in
Protection and Diagnostic Features.
However, the fault actually gets latched if the failure cause
hasn’t disappeared at the first turn-on event following
expiration of the available amount of auto-retries (see Auto-
retry). In that case, the channel gets latched and the FSB
terminal remains low. The fault bit can not be reset by reading
out the associated SPI register prior to performing a delatch
sequence (Fault Delatching).
Fault Delatching
To delatch a latched channel and be able to turn it on
again, a delatch sequence must be executed after
disappearance of the failure cause. Delatching resets the
fault bit of latched faults (see Resetting FAULT bits). To reset
the FSB pin, both channels must be delatched.
Fault mode (Operation and Operating Modes) is entered
when:
• VPWR (+VDD) were within the normal voltage range, and
• wake-up = 1, and
• fail-safe = X, and
• fault = 1 (see Going from Normal to Fail-safe, Fault or
Sleep Mode)
Delatching is achieved either by alternating the state of the
channels’ fault control signal fc[x] (generating a 1_0_1
sequence), or by resetting the auto-retry counter (provided
retry is enabled). See Reset of the Auto-retry Counter.
Delatching then actually occurs at the rising edge of the turn-
on event.
Resetting FAULT bits
Registers STATR_s and FAULTR_s contain global and
channel-specific fault information. Reading the register the
fault bit is contained in clears it, provided failure cause
disappearance was detected and the fault wasn’t latched.
Signal fc[x] is an internal signal used by the device’s
internal logic circuitry to control the diagnostic functions. The
value of fc[x] depends on the state of the variables IN_ON[x],
DIR_dis[x] and ON[x] and is expressed as follows:
fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1)
Entering Fault Mode from Fail-safe Mode
Alternating the fc[x] signal is achieved differently according
to the way the user controls the device.
When a Fault occurs in Fail-safe mode, the device is in
Fault/Fail-safe mode and behaves according to the
description of fault mode. However, SPI registers remain
reset and can not be accessed. Only the Direct Inputs control
the channels.
• In direct-input controlled mode (DIR_dis_s = 0), the IN[x]
pin must be set low, remain low for at least tIN seconds,
and set high again (be switched On). This might happen
automatically when operating at frequencies f<4.0 Hz.
20XS4200
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
• In SPI-controlled mode, the ON_bit state (D8 of the
PWMR_s reg.) must be alternated (‘toggled’). No minimum
OFF state duration is required in this case.
By delaying the activation of one channel relative to the
other (Table 8), switch-on surges can be delayed, which may
improve EMC performance. Switch-On delay can be selected
among seven different values (default=0) by setting bits
D2…D0 of the CONFR_s register (expressed as a number of
ext./int. PWM clock periods). To start the PWM function at a
known point in time, the PWM_en_s bit (D8 /D7 of the GCR
reg.) must be set to 1 after having set the PWMR_s (duty
cycle) and CONFR_s (delay) registers. The best way to
improve EMC is to use an external clock with a staggered
switch on delay.
Performing a delatch sequence anytime during an ongoing
auto-retry sequence (before latching) allows turning the
channel on unconditionally.
When a Power-ON event occurs (see Loss of VPWR, Loss
of VDD, and Power-on-Reset (POR)), latched channels are
also delatched and faults are reset.
When Fail-safe mode is entered (fault=1, fail-safe
becomes 1) during operating in Fault mode (fault=1, fail-
safe=0), previously latched faults are delatched and SPI
register content is reset (except bits POR & PARALLEL). The
device is then in a combined Fail-safe/Fault mode.
Table 8. Switch-on Delay in PWM Mode
Delay Bits
Switch-On Delay
When the device was already in Fail-safe mode (fault=1,
failsafe=1) and (new) faults occurs, the internal auto-retry
counter does not reset and latched channels are not
delatched until a delatching sequence has been performed
(see Protection and Diagnostic Features).
000
001
010
011
100
101
110
111
no delay
32 PWM clock periods
64 PWM clock periods
96 PWM clock periods
128 PWM clock periods
160 PWM clock periods
192 PWM clock periods
224 PWM clock periods
PROGRAMMABLE PWM MODULE
Each channel has a fully independent PWM module
activated by setting PWM_en_s. It modulates an internal or
external clock signal. Setting Clock_int_s = 1 (bit D6 of the
OCR_s register) activates the internal clock, and setting
Clock_int_s = 0 activates the external clock. The duty cycle
can be set in a range from 0% to 100% with 8 bit-resolution
(Table 7) by setting bits D8…D0 of the PWMR_s register
(Table 12). The channel’s switching frequency equals the
clock frequency divided by 256 in internal clock mode, and by
256 or 512 in external clock mode.
External Clock & Internal PWM (CLOCK_int_s = 0)
The channels can be controlled by an external clock signal
by setting bit D6 =0 of the OCR_s register (Clock_int_s). Duty
cycle values specified in Table 7 apply. When an external
clock is used, the value of frequency division (256 when
PR[x] = 0) may be doubled by setting the prescaler bit
PR[x]) = 1(bit D7 of the OCR_s reg.). This allows driving the
channels at different switching frequencies from a single
clock signal. Simultaneously setting PWM_en_1=1 and
PWM_en_0=1 synchronizes the channels.
External Clock
Frequency Monitoring
CLOCK_fail
PWMR_s register
PWM_en_x
CLOCK_sel_x
VPWR
PR_x
CLOCK
(1 + PR_x
PWM
Mode
25
The clock frequency on the CLOCK pin is monitored when
external clock (CLOCK_int_s = 0) and pulse width
modulation (PWM_en_s = 1) are both selected. If a clock
failure occurs under these conditions (f< fCLOCK(LOW) or f>
fCLOCK(HIGH)), the external clock signal is ignored and a fault
is detected (FSB =0), CLOCK_fail bit is set (OD2 in the
DIAGR register). The state of the ON_s bit in the SPI register
then determines the channel’s switching state. To return to
external clock mode (and reset FSB), the clock-fail bit must
be read and the external clock has to be within the authorized
range again.
Internal
Oscillator
HS_x
Driver
Block
CS
Internal Clock
Calibration
HSx
IN_x
Figure 12. Internal and External Clock Operation
.
Table 7. PWM Duty Cycle Value Assignment
ON-bit
Duty Cycle
X
Channel Configuration
OFF
0
1
Internal Clock & Internal PWM (Clock_int_s bit = 1)
00000000
PWM (duty-cycle=1/256)
By using a reference time slot (usually available from an
external microcontroller), the period of each of the internal
PWM clocks can be changed or calibrated (see
Programmable PWM module). Calibration of the default
period = 1/fPWM(0) reduces it maximum variation from about
+/-30% to +/-10%. The programming procedure is initialized
by sending a dedicated word to the SI-CALR register (see
1
1
1
1
00000001
00000010
n
PWM (duty-cycle=2/256)
PWM (duty-cycle=3/256)
PWM (duty-cycle=(n+1)/256)
fully ON
11111111
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
Table 7). Next, the device sets the new value of the switching
period in 2 steps. First it measures the time elapsed between
the first falling edge on the CSB pin and the next rising edge
on the CSB pin (tCSB). Then it changes the value of the
internal clock period accordingly. The actual value of the
channel’s switching period is obtained by multiplying the
internal clock period by 256.
D6-D8 of the CONFR_1 register (configuration of the
OpenLoad/Output short-circuited diagnostics). It is
recommended to disable the off-state OpenLoad for the HS1
output (not necessary for 20XS4200B). After setting
PARALLEL=1, contents of SO registers in bank 0 are copied
to registers of bank 1 only when new information is written in
them. Bits OD3, OD4 and OD5 of both FAULTR_s registers
(OLON, OLOFF, OS) are always reported independently.
•
Direct Input controlled Parallel mode:
tCSB
The IN0 and IN1 pins must be connected externally.
CSB
2- Diagnostics in Parallel Mode:
The Diagnostics in Parallel mode operate as follows:
• OpenLoad in OFF state and - OpenLoad in ON state:
SI
SI command
ignored
CALR_s
The OL_ON and OL_OFF bits of both FAULTR registers
independently report failures of the channels according to the
settings of bits D7 and D6 of the CONFR_s register.
tCSB
• Current sensing:
Internal clock
Refer to the Table 23 for a description of the various
current sensing modes.
period of channel s
When the duration of the negative CSB pulse is outside a
predefined time slot (from tCSB(MIN) to tCSB(MAX)), the
calibration event is ignored and the internal clock frequency
remains unchanged. If the value (fPWM(0)) has not been
previously calibrated, it remains at its default level.
Only the Current sense ratio of bank 0 (D5 of the OCR_0
register) is considered. The corresponding bit in the OCR_1
register is copied from that of the OCR_0 register.
• output shorted to battery:
The OS-bit (OD3) of each of both FAULT registers
independently report this fault, according to the settings of bit
D8 of the CONFR_s reg.
Synchronization of both Channels
When internal clock signals are used to drive the PWM
modules, perfect synchronization over a long time can not be
achieved since both clock signals are independent. However,
when the channels are driven by an external clock, perfect
synchronization can be achieved by simultaneously setting
PWM_en_1=1 and PWM_en_0=1. The best way to optimize
EMC is to use an external clock with a staggered switch on
delay (see Table 8).
3- Protections in Parallel Mode:
• Overcurrent:
-Only the Configuration of overcurrent thresholds &
blanking windows of channel 0 are considered.
-In case overcurrent (OC) occurs on any channel, both
channels are turned-off. Regardless the order of occurrence
of OC, both OC-bits (OD0) in the FAULT registers are
simultaneously set to logic 1.
PARALLEL OPERATION
The channels can be paralleled to drive higher currents.
Setting the PARALLEL bit in the GCR register to logic [1] is
mandatory in this case. The improved synchronization of
both transistors allows an equal current distribution between
both channels. In parallel mode, both output pins (HS[x])
must be connected (as well as both IN[x] pins in case of
external control). CONF0 and CONF1 must be set to equal
values.
• severe short-circuit:
In case of SC detection on any channel, both channels are
turned-off and the SC bits (OD1) in both FAULT registers are
simultaneously set to logic 1.
• overtemperature:
In case of OT detection on any channel, both channels are
turned-off and both OT bits in the FAULT registers (OD2) are
simultaneously set to logic 1.
1- Device Configuration in Parallel mode:
• auto-retry:
Only one 4-bit auto-retry counter specifies the number of
successive turn-on events on paralleled channels
(RETRYR_0). The counter value in register RETRYR_1
(OD4…OD7) is copied from that in RETRYR_0.
There are two ways to configure the On/Off control: SPI-
configured PWM control and Direct Input Control.
•
SPI configured Parallel mode:
The switching configuration is solely defined by the (SI)
To delatch the channels, only channel 0 needs to be
delatched.
PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As
soon as PARALLEL=1, the contents of the corresponding
registers in bank 1 are replaced by that of bank 0, except bits
20XS4200
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
PROTECTION AND DIAGNOSTIC FEATURES
Table 9. Overcurrent Profile Selection
PROTECTIVE FUNCTIONS
CONF[0:1] Resistor/Voltage
Type of Load
Overtemperature Fault (latchable fault)
1.0 kOhm < R(CONF[x]) <
10 kOhm
or 0 < V(CONF[X) < VIL (0.8 V)
resistive: CONF = 0,
Lighting-Mode
The channels have individual overtemperature detection.
As soon as a channel’s junction temperature rises above TSD
(175 °C typ.), it is turned OFF, the overtemperature bit
(OT = OD2) is set, and FSB = 0. FSB can only be reset by
turning ON the channel when the junction temperature of
R(CONF[x]) > 50 kOhm
or VIH (2.0 V)< V(CONF) < 5.0 V
inductive: CONF = 1,
DC motor mode
both channels has dropped below the threshold: TJ<TSD
Overtemperature is detected in ON and in OFF state:
.
When overcurrent windows are active, current sensing is
disabled and the SYNCB pin remains high. This is illustrated
by Figure 13. After turn on, the output voltage (second
waveform (20 V/div.) and the output current (first waveform,
12 A/div.) rise immediately, but the current sense voltage
(third waveform, 2.0 V/div, 1.0 V = 3.0 A) and its
synchronization signal SYNC (fourth waveform, 5.0 V/div.)
only become active at the end of the selected overcurrent
window (duration tOCM2_L).
• If the channel is ON, the associated output is switched
OFF, the OT bit is set, and FSB = 0.
• If the channel is OFF: FSB goes to logic [0] and remain low
until the temperature of both channels is below TSD and
any of the channels is turned on again.
The auto-retry function (if activated) automatically turns
the channel on when the junction temperature has dropped
below TSD. The OT fault bit can only be reset by reading out
the FAULTR register, provided that TJ<TSD and FSB = 1
again.
Overcurrent Fault (latchable fault)
When overcurrent (OC) is detected, the channel is
immediately turned Off (after tFAULT seconds). The OC-bit is
set to 1 and FSB becomes low [0]. Overcurrent is detected
anytime the load current crosses an overcurrent threshold or
exceeds the window width of the selected overcurrent
protection profile. This profile is a stair function with windows
the height and width of which are preselected through the SPI
port. The maximum allowable value of the load current at a
particular moment in time is defined by levels I_OCH and
I_OCM and windows tOCM_x and tOCH (programmable by SPI
bits). The steady-state overcurrent protection level I_OCL is
defined by the settings of the OCL and HOCR bits. Anytime
an overcurrent window is active, current sensing is blanked
and SYNC becomes 1.
Figure 13. Current Sense Blanking During Overcurrent
Window Activity
Overcurrent Duration Counter
Activation of the lighting profile is time driven and
activation of the DC motor profile is event driven, as
explained below.
The load current can spend only a defined amount of time
in a particular window of the overcurrent profile. If the time in
the window exceeds the selected window width (tOCx) or the
overcurrent threshold is crossed, the channel is turned off
(OC fault), followed by auto-retry (if enabled). An internal
overcurrent duration counter is employed for this function.
In lighting mode, the height of the overcurrent profile is
defined by three different thresholds (I_OCH, I_OCM and I_OCL
which stand for the higher, the middle, and the lower
,
overcurrent threshold), as illustrated by Figure 5. This profile
has two adjacent windows the width of which is compatible
with typical bulb inrush current profiles. The width of the first
of these windows is either tOCH1 or tOCH2. The width of the
second window is either tOCM1_L or tOCM2_L (see Table 18).
The lighting profile is activated at each turn-on event
including auto-retry, except in switch mode. In switch mode,
the profile is activated only at the first turn-on event, but is not
renewed. During the on-period, the load current is
Overcurrent Detection on Resistive and Inductive Loads
According to the load type (resistive or inductive), one of
two different overcurrent profiles should be selected. This is
done by connecting a resistor with the appropriate value
between the CONF[0:1] pins and GND (Table 9).
.
continuously compared to the programmed overcurrent
profile. The channel is switched Off when a threshold is
crossed or a window width is exceeded.
20XS4200
Analog Integrated Circuit Device Data
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35
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
In DC motor mode, only one overcurrent window exists,
defined by only two different thresholds (I_OCH and I_OCL) as
illustrated by Figure 6. This window is opened anytime the
output current exceeds the selected lower overcurrent
threshold (IOCLx). In this case, the allowed overcurrent
duration is defined by parameters tOCM1_M, tOCM2_M, tOCH1
Reset of the Duration Counter
Reset of the duration counter is achieved by performing a
delatch sequence (Fault Delatching). In lighting mode
(CONFs = 0), this counter is also reset automatically at each
auto-retry (but not in DC motor mode).
In DC motor mode, the duration counter is reset by a
performing a delatch sequence and automatically after a full
on-period without overcurrent ([hson[x]=1 for any duration).
Reset then actually occurs at the first turn-off instant following
that on-period.
and tOCH2
.
The selection of the different profiles and values is
explained in the section Address A0100— Overcurrent
protection configuration Register (OCR_s).
In switch mode, the duration counter is not reset by normal
PWM activity unless delatching is performed.
Auto-retry after Overcurrent Shut Off
When auto-retry is activated, OC-latching (Overcurrent
Fault (latchable fault)) only occurs after expiration of the
available amount of auto-retries (described in section Auto-
retry).
Severe Short-circuit Fault (latchable fault)
When a severe short-circuit (SC) is detected at turn-ON
(wiring length LLOAD< LSHORT, see Table 4), the channel is
shut off immediately. For wiring lengths above LSHORT, the
device is protected from short-circuits by the normal
overcurrent protection functions (Overtemperature Fault
(latchable fault)). When an SC occurs, FSB goes low (logic
[0]), and the SC bit is set, eventually followed by an auto-
retry. SC is of the latchable fault type (see Protection and
Diagnostic Features and Fault Delatching).
Switch Mode Operation and Overcurrent Duration
Switch mode is defined as any device operation with a
duty cycle lower than 100% at a frequency above fPWM_EXT
(min.) or fPWM_INT (min.). The device may operate in Switch
mode in internal/external PWM or in direct input mode. In
switch mode, the accumulated time spent by the load current
in a particular window segment during On times of
successive switching periods is identified by the
Overvoltage Detection (enabled by default)
aforementioned duration counter, and compared to the active
segment width. The associated off-times are excluded by the
duration counter. The channel is turned-off when the value of
the counter exceeds the window width. In Figure 14,
overcurrent detection shutdown is shown in case of switch
mode operation with a duty cycle of 50% (solid line) and
100% (fully-on, dashed line). The device is turned off much
later in switch mode than in fully-on mode, since the duration
counter only counts overcurrent during on-times.
By default, the supply overvoltage protection (VPWR) is
enabled. When overvoltage occurs (VPWR > VPWR(OV)), the
device turns OFF both channels simultaneously, the FSB pin
is asserted low, and the OV fault bit is set to logic [1]. The
channels remain OFF until the supply voltage drops below a
threshold voltage VPWR < VPWR(OV) - VPWR(OVHYS). The OV
bit can then be reset by reading out the STATR register.
The overvoltage protection can be disabled by setting the
OV_dis = 1 in the general configuration (GCR) register. In
this case, the FSB pin neither asserts a fault occurrence, nor
turns off the channels. However, the fault register (OV bit) still
reports an overvoltage occurrence (when VPWR > VPWR(OV)
)
as a warning. When VPWR > VPWR(OV), the value of the on-
resistance on both channels (RDS(ON)) still lays within the
ranges specified in Table 4.
Undervoltage Fault (Latchable Fault)
The channels are always turned off when the supply
voltage (VPWR) drops below VPWR(UV). FSB drops to logic [0],
and the fault register’s (common) UV bit is set to [1].
When the undervoltage condition then disappears, two
different cases exist:
• If the channel’s internal control signal hson[x] is off, FSB
returns to logic [1], but the UV bit remains set until at least
one output is turned on (warning).
• If the channel’s control signal is on, the channel is turned
on if a delatch or POR sequence is performed prior to the
turn on request. The UV bit can then only be reset by
reading out the STATR register.
Figure 14. Overcurrent Shutdown in PWM mode (solid
line) and Fully-on Mode (dashed line)
Auto-retry (if enabled) starts as soon as the UV condition
disappears.
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
Extended Mode Protection
the supply-voltage measurement-diode (zener) and the
current injected into the MOSFET’s gate to turn it on.
In extended mode (6.0 V < VPWR < 8.0 V or 36 V < VPWR
< 58 V), the channels are still fault protected, but compliance
with the specified protection levels is not guaranteed. The
register settings however (including previously detected
faults) remain unaltered, provided VDD is within the
authorized range. Below 6.0 V, the channels are only
protected from overtemperature, and this fault is only
reported in the SPI register the moment VPWR has again
risen above VPWR(UV). To allow the outputs to remain ON
between 36 V and 58 V, overvoltage detection should be
disabled (by setting OV_dis = 1 in the GCR register).
.
V
PWR
V V
DS(CLAMP)- th
K.I
z
HS[x]
V
th
DC
I2
Faults (overtemperature, overcurrent, severe short-circuit,
over and undervoltage) are reset if:
V
D_GND(Clamp)
IMEG
Load
V
V
CL- th
• VDD < VDD(FAIL) with VPWR in the normal voltage range
• VDD and VPWR are below the VSUPPLY(POR) voltage
threshold
GND
• The corresponding SPI register is read after the
disappearance of the failure cause (and delatching)
Figure 15. Supply and Output Voltage Protections
Reverse Voltage Protection on VPWR
Drain/source Overvoltage Protection
The device tries to limit the Drain-to-Source voltage by
turning on the channel whenever VDS exceeds VDS(CLAMP)
The device can withstand reverse supply voltages on
VPWR down to -28 V. Under these conditions, the outputs
are automatically turned On and the channel’s On-resistance
(RDS(ON)) is similar to that during positive supply voltages. No
additional components are required to protect the VPWR
circuit except series resistors (>8.0 k) between the direct
inputs IN[0:1] and VPWR, in case they are connected to
VPWR. The VDD pin needs reverse voltage protection from
an externally connected diode (Figure 21).
.
When a fault occurs (SC, OC, OT, UV), the device is rapidly
switched Off (in t < tFAULT seconds), regardless the value of
the selected slew rate. This may induce voltage surges on
VPWR and/or the output pin (HS[x]) when connected to an
inductive line/load. Turning on the device also dissipates the
energy stored in the inductive supply line. This function
monitors overvoltage for VPWR > 30 V. For supply voltages
VPWR < 30 V, the device is protected from negative output
voltages by automatically turning on the channel. The feature
remains functional after device ground loss.
Load and System Ground Loss
In case of load ground loss, the channel’s state does not
change, but the device detects an OpenLoad fault. In case of
a system GND loss, the channels are turned off.
Supply Overvoltage Protection
In order to protect the device from excessive voltages on
the supply lines, the voltage between the device’s supply pins
(VPWR and the GND) is monitored. When the VPWR-to-GND
voltage exceeds the threshold VD_GND(CLAMP), the channel is
automatically turned on. The feature is not operational in
cases of ground loss.
Device Ground Loss
In the (improbable) case the device loses all of its three
ground connections (pins 14, 17, and 22), the channels’ state
(On/ Off), depends on several factors: the values of the series
resistors connected to the device pins, the voltage of the
direct input signals, the device’s momentary current
consumption (influenced by the SPI settings) and the state of
other high side switches on the board when there are pins in
common like FSB, FSOB, and SYNC. In the following
description, all voltages are referenced to the system
(module) GND.
Negative Output Voltage Protection
The device tries to limit the undervoltage on the output
pins HS[x] when turning off inductive loads. When the output
voltage drops below VCL, the channel is switched on
automatically. This feature is not guaranteed after a device
ground loss.
When series resistors are used, the channel state can be
controlled by entering Fail-safe mode. The channels are
turned off automatically when the voltage applied to the IN[x]
input(s) through the series resistor(s) is not higher than VDD
and be turned on when the IN[x] input(s) are tied to VPWR
Fail-safe is entered under the following conditions:
The energy dissipation capabilities of the circuit are
defined by the ECL[0:1] parameters. For inductive loads larger
than 20 µH, it is recommended to employ a freewheeling
diode. The three different overvoltage protection circuits are
symbolically represented in Figure 15. The values of the
clamping diodes are those specified in Table 4. Coupling
factor k represents the current ratio between the current in
.
• all unused pins are tied to the overall system’s GND
connection by resistors > 8.0 k
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FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
• any device pin connected to external system
components has a series resistors > 8.0 k (except pins
Vpwr, VDD, HS[0], HS[1], and R(CSNS)>2.0 k)
• the FSB, FSOB, and SYNC pins are in the logic high
state when they are shared with other devices. This
means that none of the other devices is in Fault or Fail-
safe mode, nor should current sensing be performed on
any one of them when GND is lost
is unavailable. Current sensing also becomes unavailable. If
VDD_FAIL_EN wasn’t set before VDD was lost, the device
remains SPI-controlled, even though the SPI registers can’t
be read. No current flows from the VPWR to the VDD pin.
VPWR Supply Voltage Out of Range
In case VPWR is below the undervoltage threshold
VPWR(UV), it is still possible to address the device by the SPI
port, provided VDD is within the normal range. It does not
prevent other devices from operating when a device is part of
a daisy-chain. To accomplish this, RSTB must be kept at
logic [1]. When the device operates at supply voltages above
the maximum supply voltage (VPWR=36 V), SPI
communication is not affected (see Overvoltage Detection
(enabled by default)). The internal pull-up and pull-down
current sources on the SPI pins are not operational.
Executing a Power-on-Reset (POR) sequence is
When no series resistors are employed, the channel state
after GND loss is determined by the voltage on pins IN[0:1]
and the voltage shift of the device GND. Device GND shift is
determined by the lowest value of the external voltage
applied to either pin of the following list: CLOCK, FSB,
IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC,
and CSNS. When the device GND voltage becomes logic low
(V(GND)< VIL), the SPI port continues to operate and the
device operates normally. When the GND voltage becomes
logic high (V(GND)> VIH), SPI communication is lost and Fail-
safe mode is entered. When the voltage applied to the IN[0:1]
input is VPWR, the channel is turned on when it is VDD, the
channel is turned off if (VDD - V(GND)) < VIH.
recommended when VPWR re-enters its authorized range. No
current flows from the VDD to the VPWR pin.
Loss of VPWR, Loss of VDD, and Power-on-Reset (POR)
In typical applications (Figure 21 and Figure 22), an
external voltage regulator may be used to derive VDD from
VPWR. In wake mode, a Power-on-Reset (POR) sequence is
executed and the POR bit (OD6 of the STATR register) is set
when:
SUPPLY VOLTAGES OUT OF RANGE
VDD Out of Range
If the external VDD supply voltage is lost (or falls outside
the authorized range: VDD<VDD(FAIL)), the device enters Fail-
safe mode, provided the VDD_FAIL_en bit had been set.
Consequently, the contents of all SPI registers are reset. The
channels are controlled by the direct inputs IN[0:1] (if VPWR
is within the normal range). Since the VPWR pin supplies the
circuitry of the SPI, current sense and most of the protective
functions (overtemperature, overcurrent, severe short-circuit,
short to VPWR, and OpenLoad detection circuitry), these
faults are still detected and reported at the FSB pin. However,
without VDD, the SO pin is no longer functional. The SPI
registers can no longer be read and detailed fault information
• VPWR > VPWR (POR), after a period VPWR < VPWR (POR)
(and VDD < VDD (POR) before and after)
• VDD > VDD (POR) after a period with VDD < VDD (POR) (VPWR
< VPWR (POR) before and after)
POR is also set at the transition to wake-up (by setting
RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and
after) or VDD >VDD(POR) (before and after). POR is not
performed when VPWR > VPWR (POR) after a period VPWR
VPWR (POR) (and VDD > VDD (POR) permanently).
<
20XS4200
Analog Integrated Circuit Device Data
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
(fc[x] = 0)
(OpenLoadOFF = 1
or OS = 1
or OV = 1)
(OpenLoadOFF = 1
or OS = 1
or OV = 1)
(fc[x] = 1 and (OV = 0))
(OpenLoadON = 1)
OFF
ON
(fc[x]= 0 or OV = 1)
Latched
OFF
(count = 16)
(Retry = 1)
(fc[x] = 0)
Auto-retry Loop
(OpenLoadON = 1)
(after Retry Period and OV = 0 and OT = 0 and UV = 0)
(OV = 1)
OFF
ON
(Retry = 1)
= > count = count+1
(OpenloadOFF = 1
or OS = 1
or OV = 1
or UV = 1
or OT = 1)
(fc[x] = 0)
Figure 16. State Machine: Fault Occurrence and Auto-retry
AUTO-RETRY
Table 10. Auto-Retry Activation for Lamps (CONF=0)
and DC Motors (CONF=1)
The auto-retry circuitry automatically tries to turn on the
channel on a cyclic basis. Only faults of the latchable type
(overcurrent, severe short-circuit, overtemperature (OT), and
undervoltage (UV)) may activate auto-retry. For UV and OT
faults, auto-retry only starts after disappearance of the failure
cause (when auto-retry is enabled). The retry condition is
expressed by:
CONF[x]
Retry_s bit
auto-retry
0
0
1
1
0
1
0
1
enabled
disabled
disabled
enabled
Retry[x] = OC[x] or SC[x] or OT[x] or UV.
If Auto-retry has been enabled, its mode of operation
depends on the settings of the auto-retry related bits (bits
D0...D3 of the SI-RETRY_s register, see Table 12) and the
available amount of auto-retries (bits OD7...OD4 of the SO-
RETRY_s reg.). More details can be found in Amount of
Auto-retries.
If auto-retry is enabled, an auto-retry sequence starts
when the channel’s fault control signal is set to 1 (fc[x] = 1,
see Fault Delatching) and the retry condition applies
(Retry[x]=1, see Auto-retry).
If Auto-retry is disabled, latchable faults are immediately
latched upon their occurrence (see Protection and Diagnostic
Features).
When a failure occurs (fault = 1), the channel
automatically switches on again after the auto-retry period.
The value of this period (tAUTO) is set through the SPI port
(bits D2 and D3 of the RETRY_s register, see Table 22).
When the failure cause disappears before expiration of the
available amount of auto-retries, the device behaves
normally (FSB = 1), but the retry counter keeps its current
value and the fault bit remains set until it is cleared. This
guarantees a maximum device availability without preventing
fault detection.
Auto-retry Configuration
To enable the auto-retry function, bit retry_s (D0 of the SI
RETRY_s register) has to be set to the appropriate value.
Auto-retry is enabled for retry_s = 0 when the channel is
configured for lighting applications (CONF=0). It is enabled
for retry_s=1 for DC motor applications (CONF[x] =1).
20XS4200
Analog Integrated Circuit Device Data
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39
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
Amount of Auto-retries
values also depend on the way the device is controlled
(direct/internal PWM), on the current sense ratio and on the
optional activation of the OpenLoad-in-On-state detection. As
an example, in direct input (DIR_dis_s = 0), Low-Current
mode (CSR1), OLON, OLOFF and OS detection are
performed for duty cycle values up to: RPWM_400_h = 85%
(instead of 90%) when OpenLoad in On state detection is
enabled (OLON_dis=0).
In case the device is configured for an unlimited amount of
auto-retries (Retry_unlimited_s = 1), auto-retry continues as
long as the device remains powered. The channel never
latches off.
In case a limited amount of retries was selected (Retry-
unlimited_s = 0), auto-retry continues as long as the value of
the 4-bit auto-retry counter does not exceed 15 (bits
OD4...OD7 of the RETRY_s register). After 15 retries, the
Rfull bit of the STATR (OD4 for channel 0, OD5 for channel
1) register is set to a logic high. The amount of available auto-
retries is then reduced to one. If the fault still hasn’t
disappeared at the next retry, the corresponding channel is
switched off definitively and the fault is latched (FSB = 0, see
Protection and Diagnostic Features and Fault Delatching).
Occurrence of an OLON, OLOFF or OS fault sets the
associated bit in the FAULTR_s register but does not trigger
automatic turn-off. Any of these diagnostic functions can be
disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or
OS_dis_s=1 (bits D8...D6 of the CONFR reg.).
The functions are guaranteed over the specified ranges for
output capacitor values up to 22 nF (+/-20%).
Any channel can be turned on at any moment during the
auto-retry cycle by performing a delatch sequence. However,
this does not reset the retry counter.
Output Shorted-to-VPWR Fault
The device detects short-circuits between the output and
VPWR. The detection is performed during the Off-state. The
output-shorted-to-VPWR fault-bit (OS_s) is set whenever the
output voltage rises above VOSD(THRES). The fault is reported
in real time on the FSB pin and saved by the OS_s bit.
Occurrence of this fault does not trigger automatic turn-off.
The value of the auto-retry counter can be read back in
Normal mode only (SO-RETRYR register bits OD7-OD4).
Reset of the Auto-retry Counter
Any one of the below events reset the retry counter:
Even if the short-circuit disappears, the OS_s bit is not
cleared until the FAULTR register is read. The function may
be disabled by setting OS_dis_s=1. The function operates
over the duty cycle ranges specified in Diagnostic Features.
• Fail-safe is entered (Fail-safe Mode)
• Sleep mode is left (Sleep Mode)
• POR occurs (Supply Voltages Out of Range)
• the retry function is set to unlimited (bit Retry-
unlimited_s = 1 (D1 = 1))
• the retry function is disabled (retry_s bit= D0 of the
RETRY_s register under goes a 1-0 transition for
CONF = 1 and a 0-1 transition for CONF = 0).
This type of event shall be limited to 1000 min. during the
vehicle lifetime. In case of permanent output shorted to the
battery condition, it is needed to turn-on the corresponding
channel.
If the channel is latched at the moment the auto-retry
counter was reset (case 4), the channel is delatched, and
turned on after one retry period (if retry was enabled).
OpenLoad Detection In Off State
OpenLoad-in-OFF-state detection (OL_OFF) is performed
continuously during each OFF-state (both for CSR0 and
CSR1). This function is implemented by injecting a small
current into the load (IOLD(OFF)). When the load is
Auto-retry and Overcurrent Duration
During the on-period following an auto-retry, the load
current profile is compared to the length and height of the
selected overcurrent threshold profile, as described in the
section on overcurrent protection (See Overcurrent Fault
(latchable fault)).
disconnected, the output voltage rises above V
.
OLD(THRES)
OL_OFF is then detected and the OL_OFF bit in the FAULTR
register is set. If disappearance of the OpenLoad fault is
detected, the FSB output pin returns to a high immediately,
but the OL_OFF bit in the fault register remains set until it is
cleared by a read out of the FAULTR register. The function
may be disabled by setting OLOFF_dis_s=1. The function
operates over the duty cycle ranges specified in Diagnostic
Features.
When the lighting profile is activated, the overcurrent
duration counter is reset at each auto-retry (to allow
sustaining new inrush currents).
For DC motor mode however, it is only reset at the turn-off
event of the first PWM period without any overcurrent (see
Reset of the Duration Counter). Figure 16 gives a description
of the retry state machine with the various transitions
between operating modes.
OpenLoad Detection In On State (OL_ON)
OpenLoad in ON state detection (OLON) is performed
continuously during the On state for CSR0 over the ranges
specified in section Diagnostic Features. An OpenLoad in On
state fault is detected when the load current is lower than the
OpenLoad current threshold IOLD(ON). This happens at
IOLD(ON) = 150 mA (typ.) for high current sense mode
(CSR0), and at 7.0 mA (typ.) for low current mode. FSB is
asserted low and the OLON bit in the fault register is set to 1
but the channel remains On. FSB goes high as soon as
DIAGNOSTIC FEATURES
Diagnostic functions OpenLoad-in-On state (OLON),
OpenLoad-in-Off-state (OLOFF) and output short-circuited to
VPWR (OS) are operational over the frequency and duty cycle
ranges specified in Table 5 for PWM mode, but the precise
20XS4200
Analog Integrated Circuit Device Data
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
disappearance of the failure cause is detected, but the
OL_ON bit remains set.
CURRENT & TEMPERATURE SENSING
The scaled values of either of the output currents or the
temperature of the device’s GND pin (#14) can be made
available at the CSNS pin. To monitor the current of a
particular channel or the general device temperature, the
CSNS0_en and CSNS1_en bits (see Table 23) in the
General Configuration Register (GCR) must be set to the
appropriate values. When overcurrent windows are active,
current sensing is disabled and the SYNCB pin remains high.
In high current mode (CSR0), OpenLoad in On state
detection is done continuously during the On state and the
OLON-bit remains set even if the fault disappears.
In high current mode, the OLON-bit is cleared when the
FAULTR register is read during the Off state, even if the fault
hasn't disappeared. The OLON-bit is also cleared when the
FAULTR register is read during the ON state, provided the
failure cause (load disconnected) has disappeared.
Instantaneous and Sampled Current Sensing
In low current mode (CSR1), OL_ON is done periodically
instead of continuously and only operates when fast slew rate
is selected. When the internal PWM module is used with an
internal or external clock (case 1), the period is 150 ms (typ.).
When the direct inputs are used (case 2), the period is that of
the input signal. The detection instants in both cases are
given by the following:
The device offers two possibilities for load current sensing:
instantaneous (synchronous) sensing mode and track & hold
mode (see Figure 9). In synchronous mode, the load current
is mirrored through the current sense pin (Output Current
Monitoring (CSNS)) and is therefore synchronous with it.
After turn-off, the current sense pin does not output the
channel current. In track & hold mode however, the current
sense pin continues to mirror the load current as it was just
before turn-off. Synchronous mode is activated by setting the
T_H_en bit to 0, and Track & Hold mode by setting the
T_H_en bit to 1.
1. In internal PWM (int./ext. clock), low current mode
(CSR1), OpenLoad in ON state detection is not
performed each switching period, but at a fixed
frequency of about 7.0 Hz (each tOLLED =150 ms typ.).
The function is available for a duty cycle of 100%.
OLON detection is also performed at 7.0 Hz, at the first
turn-off event occurring 150 ms after the previous
OL_ON detection event (before OS and OL_OFF).
Current Sense Ratio Selection
The load current is mirrored through the CSNS pin with a
sense ratio (Figure 17) selected by the CSNS_ratio bit in the
OCR register. To achieve optimal accuracy at low current
levels, the lower current sensing ratio, called CSR1, must be
selected. In that case, the overcurrent threshold levels are
decreased. The best accuracy that can be obtained for either
ratio is shown in Figure 18. The amount of current the CSNS
pin can sink is limited to ICSNS,MAX..The CSNS pin must be
connected to a pull-down resistor (470 < R(CSNS) <10 k,
1.0 k typical), in order to generate a voltage output. A small
low-pass filter can be used for filtering out switching
2. In direct input, low current mode (CSR1), OL_ON is
performed each switching period (at the turn-off
instant) but the duty cycle is restricted to the values.
Consequently, when the signal on the IN[x] pin has a
duty cycle of 100%, OL_ON is not performed. To solve
this problem, either the internal PWM function must be
activated with a duty cycle of 100%, or the channel’s
direct input must be disabled by setting Dir_dis_s=1
(bit D5 of the CONFR-s register). The OLON-bit is only
reset when the FAULTR register is read after
occurrence of an OL_ON detection event without fault
presence.
transients (Figure 21). Current sensing operates for load
currents up to the lower overcurrent threshold (OCLx A).
Synchronous Current Sensing Mode
OpenLoad Detection in Discontinuous Conduction Mode
For activation of synchronous mode, T_H_en must be set
to 0 (default). After turn-on, the CSNS output current
accurately reflects the value of the channel’s load current
after the required settling time. From this moment on (CSNS
valid), the SYNC pin goes low and remains low until a switch
off signal (internal/external) is received. This allows
synchronization of the device’s current sensing feature with
an external process running on a separate device (see
Current Sense Synchronization (SYNC)). After turn-off, the
load current does not flow through the switch, and the load
current cannot be monitored.
If small inductive loads (solenoids / DC motors) are driven
at low frequencies, discontinuous conduction mode may
occur. Undesired OpenLoad in On state errors may then be
detected, as the inductor current needs some time to rise
above the OpenLoad detection threshold after turn-on. This
problem can be solved by increasing the switching frequency
or by disabling the function and activating OpenLoad in Off
state detection instead.
When small DC motors are driven in discontinuous
conduction mode, undesired OpenLoad in Off state detection
may also occur when the load current reaches 0.0 A during
the Off state. This problem can be solved by increasing the
switching frequency or by enabling OpenLoad in Off state
detection only during a limited time, preferably directly after
turn-off (see Diagnostic Features). The signal on the SYNC
pin can be used to identify the turn-off instant.
Track & Hold Current Sensing Mode
In Track & Hold mode (T&H) (T_H_en = 1), conversely
from synchronous mode, the CSNS output current is
available even after having switched off the load. This feature
is useful when the device operates autonomously (internal
clock/PWM), since it allows current monitoring without any
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
synchronization of the device. An external sample and hold
(S/H) capacitor is not required. After turn on, the CSNS
output current reflects the channel’s load current with the
specified accuracy after occurrence of the negative edge on
the SYNC pin, as in synchronous mode (see Current Sense
Synchronization (SYNC)). However, at the switch-off instant,
the last observed CSNS current is sampled and its value
saved, thanks to an internal S/H capacitor. The SYNC pin
goes high (SYNC = 1). If the channel on which Track & Hold
current sensing is performed is changed to another, the
internal S/H hold capacitor is first emptied and then charged
again to allow current monitoring of the other channel.
Consequently, T&H current monitoring of a channel is lost
when this channel is in the Off state at the moment the
current is monitored on the other channel. Track & Hold mode
should not be used for frequencies below 60 Hz.
Activation and Use of Offset Compensation
According to the settings of the OFP_s bit (in the
RETRYR_s register), opposite values of the random offset
error are generated. To compensate the random offset error,
two separate measurements with opposite values of the
random offset error are required. The measured values must
be saved by an external µ-processor. Compensation of the
random offset error is achieved by computing the average of
both. When a dedicated bit called Offset Positive (OFP = bit
D8 of the RETRYR_s register) is set to 1, the current sunk
through the CSNS pin (ICSNS) can be described by:
ICSNS1=CSRx *(ILOAD+ I_LOAD_ERR_SYS+ I_LOAD_ERR_RAND
)
(2)
When bit OFP is set to 0, ICSNS can be described by:
ICSNS2 = CSRx *(ILOAD+ I_LOAD_ERR_SYS - I_LOAD_ERR_RAND) (3)
The random offset term I_LOAD_ERR_RAND can be
computed from equations (2) and (3) as follows:
.
I_LOAD_ERR_RAND = (ICSNS1 - ICSNS2) / (2*CSRx)
(4)
The compensated current sense value ICSNS,COMP can be
obtained by computing the average value of measurements
ICSNS1 and ICSNS2 as follows:
ICSNS,COMP = (ICSNS1 + ICSNS2) / 2
(5)
When equations 2 and 3 are substituted in equation 5, the
random offset error cancels out, as shows eq. 6:
ICSNS,COMP = (I_LOAD_ERR_SYS + ILOAD
)
* CSRx
(6)
The systematic offset error I_LOAD_ERR_SYS is referenced
at the operating point 28 V and 25 °C. It can eventually be
fine tuned by performing a calibration. Gain errors at 25 °C
(=current sense ratio errors, represented by GAIN0 and
Figure 17. Current Sensing Ratio Versus Output Current
Current Sense Errors
Current sense accuracy is adversely affected by errors of
the internal circuitry’s current sense ratio and offset. The
value of the current sensing output current can be expressed
with sufficient accuracy by the following equation:
Gain1) can also be reduced by performing a calibration at a
point in the range of interest. If calibration can not be done, it
is recommended to use the typical value of I_LOAD_ERR_SYS
(see ESR0_ERR).
ICSNS = (I(HS[x])+ I_LOAD_ERR_SYS + I_LOAD_Err_RAND)*CSRx
(1)
Current Sense Error Model
with CSR0 = (1/1500+GAIN0) and CSR1 = (1/500+GAIN1).
The figures of uncompensated and compensated current
sense accuracy mentioned in Table 4 have been obtained
applying the error model of eq. 7 to the data:
The device’s offset error has a “systematic” and a
“random” component (I_LOAD_ERR_SYS, I_LOAD_ERR_RAND).
At low current levels, the random offset error may become
dominant. The systematic offset error is caused by
predictable variations with supply voltage and temperature,
and has a small but positive value with small spread. The
random offset error is a randomly distributed parameter with
an average value of zero, but with high spread. The random
offset error is subject to part-to-part variations and also
depends on the values of supply voltage and device
temperature. The device has a special feature called offset
compensation, allowing an almost complete compensation of
the random offset error (see ESR0_ERR). This offset
compensation technique greatly minimizes this error.
Computing the compensated current sensing value is
illustrated in the next sections.
ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx
ESRx_ERR = (ICSNS1 - ICSNS_MODEL)/ICSNS_MODEL
(7)
(8)
E
SRx_ERR(COMP)= (ICSNS,COMP - ICSNS_MODEL)/ICSNS_MODEL (9)
The computation has been applied to each of the specified
measurement points. Model parameters I_LOAD_ERR_SYS and
CSRx have the nominal values, specified in ESR0_ERR
.
The load current can be computed from this model as:
I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
I(HS[x]) = ICSNS,COMP / CSRx - I_LOAD_ERR_SYS
(10)
(11)
20XS4200
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
Using expression (11) generally gives more accurate
values than expression (10), since in expression (11),
random offset errors have been compensated.
Figure 19 (error percentage as a function of the switch-off
time is displayed, for CSR0 and CSR1). Track & Hold mode
shouldn’t be used below f= 60 Hz.
Offset Compensation in Track & Hold Mode
In Track & Hold mode, the last observed sense current
(ICSNS) is sampled at the switch off instant. This takes into
account the currently active settings of the OFP_s offset
compensation bit. Changing the value of the OFP bit during
the switch’s off time produces an identical value of the current
sense output. Consequently, to implement the before
mentioned offset compensation technique, the channel must
have been turned on at least once prior to sensing the output
current with an opposite value of the OFP bit.
System Requirements for Current Monitoring
Current monitoring is usually implemented by reading the
(RC-filtered) voltage across the pull-down resistor connected
between the CSNS pin and GND (Figure 21). Therefore,
measurements (1) and (2) must be spaced sufficiently wide
apart (e.g. 5 time constants) to get stabilized values, but
close enough to be sure that the offset value wasn’t changed.
The A/D converter of the external micro controller that is used
to read the current sense voltage V(csns) must have
Figure 19. Track and Hold Current Sense Accuracy
Temperature Prewarning Detection
In Normal mode, the temperature prewarning (OTW) bit is
set (bit OD8 of the FAULTR register) when the observed
temperature of the GND pin is higher than TOTWAR (pin #14,
see Figure 3). The feature is useful when the temperature of
the direct surroundings of the device must be monitored.
However, the channel isn’t switched off. To be able to reset
the OTW-bit, the FAULTR register must be read after the
sufficient resolution to avoid introducing additional errors.
Accuracy with and without Offset Compensation
The sensing accuracy for CSR0 and CSR1, obtained
before and after offset compensation, is shown in Figure 18
(solid lines = full scale accuracy with offset compensation
and dotted lines without offset compensation).
moment that temperature T °C < TOTWAR
.
Switching State Monitoring
The switching state (On/Off) of the channels is reported in
real time by bits OUT[x] in the STATR register (bit OD0/OD1).
The Out[x] bit is asserted logic high when the channel is on
(output voltage V(HS[x]) higher than VPWR /2). When supply
voltage VPWR drops below 13 V, the reported channel state
may not correspond to the state of the channel’s control
signal hson[x] in case of an OpenLoad fault (see Factors
Determining the Channel’s Switching State).
.
EMC PERFORMANCES
Specified EMC performance is board and module
dependent and applies to a typical application (Figure 21).
The device withstands transients per ISO 7637-2 /24 V. An
external freewheeling diode connected to at least one output
is required for sustaining ISO 7637 Pulse 1 (-600 V). To
withstand Pulse 2, at least one of the two channels must be
connected to a typical load (bulb). It withstands electric fields
up to 200 V/m and Bulk Current Injection (BCI) up to 200 mA
per ISO11452.
Figure 18. Current Sense Accuracy Versus Output
Current
In Track & Hold mode, the accuracy of the current sense
function is lowered according to the values shown in
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
LOGIC COMMANDS AND SPI REGISTERS
or 3.3 V CMOS logic levels. Parity check is performed after
SPI PROTOCOL DESCRIPTION
transfer of each 16-bit SPI data word.The SPI interface can
be driven without series resistors provided that voltage
ratings on VDD and SPI pins (Table 3) aren’t exceeded.
Unused SPI pins must be tied to GND, eventually by resistors
(see Device Ground Loss).
The SPI interface offers full duplex, synchronous data
transfer over four I/O lines: Serial Input (SI), Serial Output
(SO), Serial Clock (SCLK), and Chip Select (CSB).The SI/SO
pins of the device follow a first-in first-out (D15 to D0)
protocol. Transfer of input and output words starts with the
most significant bit (MSB). All inputs are compatible with 5.0
CSB
SCLK
SI
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RSTB must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).
Figure 20. 16-Bit SPI Interface Timing Diagram
SERIAL INPUT COMMUNICATION PROTOCOL
SERIAL PORT OPERATION
SPI communication requires that RSTB = high. SPI
communication is accomplished with 16-bit messages. A
valid message must start with the MSB (D15) and end with
the LSB (D0) (Table 11). Incoming messages are interpreted
according to Table 12. The MSB, D15, is the watchdog bit
(WDIN). Bit D14, Parity check (P), must be set such that the
total number of 1-bits in the SPI word is even (P=0 for an
even number of 1-bits and P=1 for an odd number). Bank
selection is done by setting bit D13. Bits D12:D10 are used
for register addressing. The remaining ten bits, D9:D0, are
used to configure the device and activate diagnostic and
protective functions. Multiple messages can be transmitted
for applications with daisy chaining (or to validate already
transmitted data) by keeping the CSB pin at logic 0.
Messages with a length different from a multiple of 16 or with
a parity error is ignored. The device has thirteen input
registers for device configuration and thirteen output
registers containing the fault/device status and settings.
Table 12 gives the SI register function assignment. Bit names
with extension “_s” refer to functions that have been
implemented independently for each of both channels.
When Chip Select occurs (1-to-0 transition on the CSB
pin), the output register data is clocked out of the SO pin
(MSB-first) at the serial clock frequency (SLCK). Bits at the SI
pin are clocked in at the same time. The first sixteen SO
register bits are those addressed by the previous SI word (bit
D13, D2…D0 of the STATR_s input register). At the end of
the chip select event (0-to-1 transition), the SI register
contents are latched. The second SPI word clocked out of the
Serial Output (SO) after the first CSB event represents the
initial SO register contents. This allows daisy chaining and
data integrity verification.
The message length is validated at the end of the CSB
event (0-to-1 transition). If it is valid (multiples of 16, no parity
error), the data is latched into the selected register. After
latch-in, the SO pin is tri-stated and the status register is
updated with the latest fault status information.
Daisy Chain Operation
Daisy-chaining propagates commands through devices
connected in series. The commands enter the device at the
SI pin and leave it by the SO pin, delayed by one command
cycle of 16 bits. To address a particular device in a daisy
chain, the CSB pin of all the devices in that chain has to be
kept low until the SPI message has arrived at its destination.
Once the command has been clocked in by the addressed
device, it can be executed by setting CSB=1.
20XS4200
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
Table 11. SI Message Bit Assignment
Bit n°
SI Reg. Bit
Bit Functional Description
Watchdog in (WDIN): Its state must be alternated at least once within the timeout period
Parity (P) check. P-bit must be set to 0 for an even number of 1-bits and to 1 for an odd number.
Selection between SI registers from bank 0 (0= channel 0) and bank 1 (Table 14).
Register address bits.
MSB
.
.
.
.
D15
D14
D13
D12:D10
D9:D0
LSB
Used to configure the device and the protective functions and to address the SO registers.
Table 12. Serial Input register Addresses and Function Assignment
SI Data
SI
Register
D
D
D
D
D
D 15
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
14 13 12 11 10
STATR_s WDIN
P
P
A
A
0
0
0
0
0
1
0
0
0
0
0
0
0
0
SOA2
SOA1
SOA0
0
0
PWMR_s
WDIN
ON_s
PWM7_s
PWM6_s
PWM5_s PWM4_
s
PWM3_s
PWM2_s
PWM1_s PWM0_s
CONFR_s
WDIN
P
P
P
P
A
A
A
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
OS_dis_s OLON_dis OLOFF_dis DIR_dis_s SR1_s
SR0_s
DELAY2_s DELAY1_s DELAY0_
s
0
0
0
_s
_s
OCR_s
WDIN
HOCR_s
OFP_s
PR_s
Clock_int_s CSNS_rati
o_s
t
tOCM_s
OCH_s
OCM_s
OCL_s
OCH_s
(47)
RETRY_s
WDIN
0
0
0
Auto_period Auto_period Retry_unli
retry_s
1_s
0_s
mited_s
GCR
0
PWM_en PWM_en_ PARALLEL
T_H_en
WD_dis
V
DD_FAIL_en
CSNS1_en CSNS0_en OV_dis
WDIN
_1
0
WDIN
0
CALR_s
P
X
A
1
1
1
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
1
0
0
contents
after
0
X
X
X
0
0
0**
reset*
* = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V or POR
** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before
X = register address, P = parity bit
Notes
47. Bit D4 of RETRY_s Serial Input register
MC20XS4200FK = 0
MC20XS4200BFK and MC20XS4200BAFK= CONF_SPI_s
Setting bit D4 to 0 (CONF_SPI_s=0) will configure the overcurrent profile as the CONF pin.
Setting bit D4 to 1 (CONF_SPI_s=1) will configure the overcurrent profile as the opposite of CONF pin.
After device reset, the overcurrent profile is defined by the CONF input pin. The SPI-SO CONF bit reporting shall combine external
hardware configuration and SPI setting.
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
Table 13. Serial Output Register Bit Assignment
bits D13,
D2, D1, D0
of the
SO Returned Data
Previous
STATR
S
O
A
3
S
O
A
2
S
O
A
1
S
O
A
0
OD OD OD OD OD OD
15 14 13 12 11 10 D9
O
OD8 OD7 OD6 OD5 OD4
OD3
OD2
OD1
OD0
WDI
N
SOA SOA SO SO
N
M
R_FUL R_FUL
STATR
0
0
0
0
0
0
1
0
1
0
PF
PF
PF
OV
UV
0
POR
0
FAULT1
FAULT0
OUT1
SC_s
OUT0
OC_s
3
2
A1 A0
L1
L0
FAULT
R_s
WDI
N
SOA SOA SO SO
A1 A0
N
M
OLON OLOFF
_s _s
A
A
OTW
OS_s
OT_s
0
0
3
2
PWMR_
s
WDI
N
SOA SOA SO SO
A1 A0
N
M
ON_
s
PWM PWM6 PWM5 PWM4
PWM3_s
PWM2_s
PWM1_s PWM0_s
3
2
7_s
_s
_s
_s
OLO
N_di
s_s
DIR_di SR1_s
s_s
SR0_s
DELAY2_s DELAY1_ DELAY0_
CONFR
_s
WDI
N
SOA SOA SO SO
N
M
OS_
dis_s
OLOFF
_dis_s
A
0
1
1
PF
s
s
0
3
2
A1 A0
WDI
N
SOA SOA SO SO
N
M
HOC
R_s
Clock_i CSNS_ tOCH_
tOCM_s
OCH_s
OCM_s
OCL_s
retry_s
OCR_s
A
A
1
1
0
0
0
1
PF
PF
PR_s
0
0
3
2
A1 A0
nt_s
ratio_s
s
RETRY
R_s
WDI
N
SOA SOA SO SO
A1 A0
N
M
OFP R3
R2
R1
R0
Auto_period Auto_period0 Retry_unli
1_s _s mited_s
3
2
PWM PWM PARAL T_H_e WD_di VDD_Fail_e CSNS1_en CSNS0_e OV_dis
WDI
N
SOA SOA SO SO
N
M
GCR
0
1
1
1
1
0
1
PF
PF
_en_ _en_ LLEL
n
s
n
n
3
2
A1 A0
1
0
DIAGR
(48)
WDI
N
SOA SOA SO SO
N
M
CON CON
IN0
CLOCK_fail CAL_fail1
0
ID1
0**
ID0
IN1
CAL_fail0
0
3
0
2
0
A1 A0
F1
F0
content
s after
reset or
failure*
0
0
N/ N/ N/ N/
A
0
0
0
0
0
0
0
0***
0
0
A
A
A
* = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V, or POR
** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs provided VDD = 5.0 V and VDD_Fail_en = 1 before
*** = except bit D7 (POR) of the STATR register that is saved when VDD(FAIL) occurs after VDD = 5.0 V and VDD_Fail_en = 1 (fail-safe
mode)
x = register address, PF = parity Fault
Notes
48. DIAGR Serial Output register bits D5 and D6 for product identification will report: MC20XS4200FK and MC20XS4200BFK:01,
MC20XS4200BAFK:00
SI REGISTER ADDRESSING
Table 14. Value of bit A0 Required for Addressing
Register Banks 0 or 1
The address in the title of the following sections (A0xxx)
refer to bits D[13:10] of the SPI word required to address the
associated SI register. Bit A0 = D13 selects between
registers of bank 0 and bank 1 (Table 14). The function
assignment of register bits D[8:0] is described in the
associated section. The “_s” behind a register name
indicates that the variable applies to the register contents of
both banks.
Value A0 (D13)
Bank
0
1
0 = channel 0 (default)
1 = channel 1
ADDRESS A 000—STATUS REGISTER (STATR_S)
0
To read back the contents of any of the 13 SO registers,
bits D[13:10] of the channel’s SI STATR register must be set
to A0000 and bits D[2:0] in the same SPI word to the address
of the desired SO register. The SO registers thus addressed
20XS4200
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
are: STATR, FAULTR_s, PWMR_s, CONFR_s, OCR_s,
RETRY_s, GCR, and DIAGR (Table 13).
Table 16. Slew Rate Selection
SR1_s (D4)
SR0_s (D3)
Slew Rate
ADDRESS A 001— PWM CONTROL REGISTER
0
(PWMR_S)
0
0
1
1
0
1
0
1
medium (default)
The PWMR_s register contents determines the value of
the PWM duty cycle at the output (Table 12), both for internal
and external clock signals.
low
high
medium SR <SR< high SR
Bit D8 must be set to 1 to activate this function. The
desired value of duty cycle is obtained by setting Bits D7:D0
to one of the 256 levels as shown in Table 7.To start the
PWM function at a known point in time, the PWM_en_s bit
(both in the GCR register) must be set to 1.
Delaying a channel’s turn-On instant with respect to the
other is accomplished by setting bits D2:D0 of the PWMR_s
register to the appropriate values. Switch On is delayed by
the number of (internal/external) clock periods shown in
Table 8. Refer to the section Programmable PWM module.
ADDRESS A 010—CHANNEL CONFIGURATION
0
REGISTER (CONFR_S)
ADDRESS A 100— OVERCURRENT PROTECTION
0
The CONFR_s is used to select the appropriate value of
slew rate and turn-ON delay. The settings of Bits D[8:6]
determine the activation of OpenLoad and short-circuit (to
VPWR) detection. Bit D13 ( = A0) of the incoming SPI word
determines which of both CONFR registers is addressed
(Table 14).
CONFIGURATION REGISTER (OCR_S)
The contents of the OCR_s registers determines operation
of overcurrent, current sensing, and PWM related functions.
For each load type (bulb or DC motor), a different kind of
overcurrent profile exists (see Overcurrent Protection Profile
for Bulb Applications). For lighting mode, the overcurrent
profile is defined by three different thresholds each of which
is active over a dedicated time slot. These thresholds are
called the higher (=I_OCH), the middle (=I_OCM) and the lower
(=I_OCL) threshold. The DC motor profile only has two
thresholds (I_OCH and I_OCL).
Setting bit D8 (OS_dis_s) to logic [1] disables detection of
short-circuits between the channel’s output pin and the
VPWR pin. The default value [0] enables the feature.
Setting bit D7 (OLON_dis_s) to logic [1] disables detection
of OpenLoad in the On state for the selected channel. The
default value [0] enables this feature (Table 15).
Each threshold can be set to two different values, except
I_OCL that can be set to three different values (I_OCL1, I_OCL2
I_OCL3). Setting the low-current sense ratio (CSR1) reduces
the values of all the overcurrent thresholds by a factor of
,
Setting bit D6 (OLOFF_dis_s) to logic [1] disables
detection of OpenLoad in the OFF state. The default value [0]
enables the feature, see Table 15.
three. The terminology is defined as follows: I_OCxy_z stands
for overcurrent threshold x (x=I_OCH, I_OCM or I_OCL) that can
be set to two or three different values, selected by y (y=1, 2,
(or 3)). The previously selected current sense ratio (z=0 for
CSR0 and z=1 for CSR1) further determines the shape of the
applicable overcurrent protection profile (see I_OCH1_0).
Table 15. Selection of OpenLoad Detection Features
OLON_dis_s
(D7: On state)
OLOFF_dis_s
(D6: Off state)
Selected OpenLoad
Detection function
0
0
0
1
both enabled (default)
Setting bit D8 (HOCR_s) to 0 activates overcurrent level
I_OCL1, the highest of the 3 levels, regardless the value of the
D0 bit. Setting HOCR to 1 activates the medium level I_OCL2
when D0 = 0, and the lowest level I_OCL3 when D0 = 1
(Table 21). When overcurrent windows are active, current
sensing is not available.
Off state detection
disabled
1
0
On state detection
disabled
1
1
Both disabled
Bit D7 (PR_s) controls which of two divider values are
used to create the PWM frequency from the external clock.
Setting bit D7 to 1 causes the external clock to be divided by
512. When PR_s = 0, the divider is 256.
Setting bit D5 (DIR_DIS_s) to logic [0] enables direct
control of the selected channel. Setting bit D5 to logic [1]
disables direct control. In that case, the channel state is
determined by the settings of the internal PWM functions.
Setting bit D6 (Clock_int_s) activates the internal clock of
the selected channel. The default value [0] configures the
PWM module to use an external clock signal.
D4:D3 bits (SR1_s and SR0_s) control the slew rate at
turn on and turn off (Table 16). The default value ([00])
corresponds to the medium slew rate. Rising and falling edge
slew rates are identical.
Setting bit D5 (CSNS_ratio_s) to 1 activates the “low-
current” current sense ratio CSR1, optimal for measuring
currents in the lowest range. The default value [0] activates
the “high-current” sensing ratio CSR0 (Table 17).
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
Table 17. Current Sense Ratio Selection
Table 20. OCM Current Threshold Selection
CSNS_ratio_s (D5)
Current Sense Ratio
OCM_s (D1)
OCM Current Threshold
0
1
CRS0 (default)
CRS1
0
1
I_OCM1_s (default)
I_OCM2_s
The width of the overcurrent protection window(s) is
controlled by bits D4 and D3 (tOCH_s and tOCM_s), and also
depends on the load type configuration as shown in Table 18.
(CONF[x]=0: bulb, CONF[x]=1: DC motor).
Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest
overcurrent threshold, as shown in Table 21.
Table 21. OCL Current Threshold Selection
Selected OCL
The lighting profile has two adjacent windows the width of
which is compatible with typical bulb inrush current profiles.
The width of the first of these windows is either tOCH1 or
tOCH2. The width of the second window is either tOCM1_L or
tOCM2_L (see Table 18).
HOCR (D8)
OCL_s (bit D0)
Current Level
0
0
1
1
0
1
0
1
I_OCL1_x(default)
I_OCL1_x
The DC motor profile has one overcurrent window defined
by two different thresholds (I_OCH and I_OCL), as illustrated by
Figure 6. In this case, the maximum overcurrent duration is
selected among four values: tOCM1_M, tOCM2_M, tOCH1 and
I_OCL2_x
I_OCL3_x
tOCH2
.
ADDRESS A 101— AUTO-RETRY REGISTER
0
(RETRYR_S)
Table 18. Dynamic Overcurrent Threshold Activation
Times for Bulb -and DC Motor Profiles
The RETRYR_s register contents are used to set the
different auto-retry options (Auto-retry) and the offset
compensation feature of the current sense function.
Selected threshold
CONF[x] tOCH_s (D4) tOCM_s (D3)
activation times
Setting bit D8 to 1(OFP = 1) causes the random offset
current (and the overcurrent profile on the 20XS4200B) to be
added to the sensed current (pin CSNS). Setting bit D8 to 0
results in the offset current being subtracted from the sensed
current.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tOCH1 and tOCM1_L
tOCH1 and tOCM2_L
tOCH2 and tOCM1_L
tOCH2 and tOCM2_L
tOCM1_M
Setting D3 and D2 (Table 22) to the appropriate values
allows selection of the value of the auto-retry period among
four predefined values.
tOCM2_M
Table 22. Auto-Retry Period
tOCH1
Auto_period1_s Auto_period0_s
Retry Period
tOCH2
(D3)
(D2)
Bit D2 (OCH_s) selects the value of the higher (upper)
overcurrent threshold among two values. The default
value [0] corresponds to the highest value, and [1] to the
lowest value (Table 19).
0
0
1
1
0
1
0
1
tAUTO_00 (default)
tAUTO_01
tAUTO_10
Table 19. OCH Upper Current Threshold Selection
tAUTO_11
OCH_s (D2)
I_OCH Current Threshold
Setting bit D1 to 1 (RETRY_unlimited_s = 1) results in an
unlimited number of auto retries, provided the auto-retry
function wasn’t disabled.
0
1
I_OCH1_s (default)
I_OCH2_s
Setting bit D1 to 0 (RETRY_unlimited_s = 0) limits the
amount of auto retries to 16 (see Amount of Auto-retries). The
value of the counter neither resets after delatching, nor when
the fault disappears.
Bit D1 (OCM_s) sets the value of the middle overcurrent
threshold. The default value [0] corresponds to the highest
value, and [1] to the lowest value (Table 20). In DC motor
mode, there is no middle overcurrent threshold and the value
of this bit has no influence.
Setting bit D0 (retry_s) enables or disable auto-retry,
accordingly to setting of the CONF pin.
20XS4200
Analog Integrated Circuit Device Data
48
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
For CONF[x] = 0 (Lighting profile configured), setting
Setting bit D0 (OV_dis = 1 of the GCR reg.) disables
retry_s = 1 disables auto-retry. The default value [0] enables
it.
overvoltage protection. Setting this bit to [0] (default), enables
it.
For CONF[x] = 1 (DC motor), setting retry_s = 1 enables
auto-retry. The default value [0] disables it.
ADDRESS A 111—CALIBRATION REGISTER
0
(CALR_S)
For details, see Table 12.
The internal clock frequency of both channels can be
calibrated independently. Setting the appropriate calibration
word in the CALR_s register (Table 12) puts the device in
calibration mode. The default switching frequency is 400 Hz,
but can be changed by applying a specific calibration
procedure. See Internal Clock & Internal PWM (Clock_int_s
bit = 1).
ADDRESS 0110—GLOBAL CONFIGURATION
REGISTER (GCR)
The GCR register is used to activate various functions and
diagnostic functions.
Setting bits D8 = 1 and D7 = 1 of the GCR register
(PWM_en_1 and PWM_en_0) activates the internal PWM
function of both channels simultaneously according to the
values of duty cycle and turn-on delays in the PWMR_s and
CONFR_s registers (Table 7). However, this option should
never be used to drive channels in parallel. To increase the
load current capability, the instructions in the section Parallel
Operation should be followed.
SO REGISTER ADDRESSING
The device has two register banks, each of which has five
channel-specific SO registers containing the channel’s
configuration and diagnostics status (Table 13). These
registers are FAULTR_s, PWMR_s, CONFR_s, OCR_s, and
RETRYR_s.
Setting bit D6 sets parallel mode (improved switching
synchronization between both channels). Only configuration
and diagnostic information of bank 0 (A0 = 0) is available in
this setting (see Parallel Operation).
Global fault and diagnostic information are contained in
the following common SO-registers: STATR, GCR, and
DIAGR. All the SO registers can be addressed by setting the
appropriate bits in the SI-STATR_s register (bits D13, D2,
D1, D0). The value of the bit D13 determines which register
bank is addressed (bank 0 or 1). Data is made available the
next cycle after register addressing.
Setting Bit D5 (T_H_en = 1) activates Track & Hold current
sensing mode. When T&H is activated, the value of the
channel’s load current is kept available after turn-off.
Setting bit D4 (WD_dis = 1) disables the SPI watchdog
function. A logic [0] enables the SPI watchdog.
The output status register correctly reflects the contents of
the addressed SO register as long as CSB is low, except
when the data from the previous SPI cycle was invalid. In this
case, the device outputs the contents of the last successfully
addressed SO register.
Setting bit D3 (VDD_FAIL_EN = 1) enables or disable the
VDD failure detection. When enabled, the device enters Fail-
safe mode after VDD < VDD(FAIL).
Bits D6 (parallel bit), D2 and D1 set the different (current)
sensing options. The CSNS pin outputs a scaled value of the
selected channel’s load current, the sum of both currents or
the die temperature, according to the values in Table 23.
When the highest overcurrent range is selected (bit D8 of the
OCR register, HOCR = 0), the device’s CSNS pin only
outputs scaled values of a single channel’s load current.
SERIAL OUTPUT REGISTER ASSIGNMENT
The output register shifted out through the SO pin is
previously addressed by bits D13, D2, D1, and D0 of the
STATR_s SI register. Table 13 gives the functional
assignment (OD15:OD0) of each of the thirteen SO register
bits, preceded by the address of the SI STATR_s required to
address it.
Table 23. Current Sense Pin Functionality Selection
• Bit OD15 (MSB) reports the state of the watchdog bit
from the previously clocked-in SPI message.
• Bit OD14 (PF, active 1) reports an eventual parity error
on the previously transferred SI register contents.
• Bits OD13:OD10 echo the state of bits D13, D2, D1, and
D0 (SOA3:SOA0) of the previously received SI word.
• Bit OD9: Normal mode (NM) reports the device state. In
Normal Mode, NM = 1.
D8
D6
D2
D1
Activated Function at CSNS Pin
disabled
x
0
0
0
1
1
1
1
x
x
x
x
0
x
x
1
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
current sensing on channel 0
current sensing on channel 1
temperature sensing
• Bits OD8:OD0 are the contents of the selected SO
register (addressed by bit D13 and bits D2:D0 of the
previous SI STATR register).
current sensing on channel 0
current sensing on channel 1
temperature
current sensing summed currents of
channels 0 and 1
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND SPI REGISTERS
PREVIOUS ADDRESS SOA :SOA = 0000 (STATR)
PREVIOUS ADDRESS SOA :SOA = A 010
3 0 0
3
0
(PWMR_S)
When bits SOA3…SOA0 of the previously received SI
STATR_s register = 0000, the SO STATR register is
addressed. Bits OD8:OD0 contain the relevant channel
information: Faults, channel state, and supply voltage errors.
The device outputs the contents of the addressed
PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
• Bits OD8:OD6 report failures common to both channels
• Bit OD8 = OV = 1: overvoltage fault
PREVIOUS ADDRESS SOA :SOA = A 011
(CONFR_S)
3
0
0
• Bit OD7 = UV = 1: undervoltage fault
The device outputs the contents of the addressed
• Bit OD6 = POR = 1: power-on reset (POR) has occurred
CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
Power-ON-Reset occurs when VPWR<VSUPPLY(POR). The
OV, UV, and POR bits can be reset by a reading the STATR
register.
PREVIOUS ADDRESS SOA :SOA = A 100
(OCR_S)
3
0
0
Bits OD5:OD4 (RFULL) of the STATR register are set to
logic [1] when the auto-retry counter of the corresponding
channel is full. These bits are automatically cleared by
resetting the corresponding auto-retry counter (see Reset of
the Auto-retry Counter)
The device outputs the contents of the addressed OCR_s
register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
PREVIOUS ADDRESS SOA :SOA = A 101
3
0
0
(RETRYR_S)
Bits OD3 (FAULT1) and OD2 (FAULT0) are set to logic [1]
when channel-specific (non-generic) faults are detected:
The device outputs the contents of the addressed
RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
FAULTs = OC_s + SC_s + OT_s + OS_s + OLOFF_s +
OLON_s.
Bit OD8 contains the value of the OFP bit (offset positive),
used for current sense offset compensation. Bits OD7:OD4
contain the real time value of the auto-retry counter. When
these bits contain [0000], either auto-retry has not been
enabled or Auto-retry did not occur.
The FAULTs bit can be reset by reading out the common
STATR register or the individual FAULTR_s register
(provided the fault has disappeared).
Bits OD1:OD0 (OUT1 and OUT0) report the channel’s
switching state (On/Off) in real time.
PREVIOUS ADDRESS SOA :SOA = 0110 (GCR)
3
0
The device outputs the contents of the general
configuration register (GCR) common to both channels.
PREVIOUS ADDRESS SOA :SOA = A 001
3
0
0
(FAULTR_S)
Bit OD8 of both Fault registers (FAULTR_s) is set
simultaneously when the overtemperature prewarning
(OTW) condition occurs, but the channels are not switched
off (temperature of the common GND pin (#14)> TOTWAR).
PREVIOUS ADDRESS SOA :SOA = 0111
(DIAGR_S)
3
0
Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0)
of the DIAGR_s register contain the values of the channels’
configuration bits (0 = bulb, 1 = DC motor).
Reading either FAULT register clears both OTW bits.
Bits OD5:OD0 of the Fault register (FAULTR_s) report the
faults that occurred on the channel previously selected by bit
SOA3 = A0 (Table 14).
For 20XS4200FK and 20XS4200BFK
• Bits OD6:OD5 contain the product identification (ID)
number, equal to 01 for the present dual 20 m
product.
• bit OD0 = OC_s: overcurrent fault on channel s,
• bit OD1 = SC_s: severe short-circuit on channel s,
• bit OD3 = OS_s: output shorted to VPWR on channel s,
• bit OD4 = OLOFF_s: OpenLoad in OFF state on
channel s,
For 20XS4200BAFK
• Bits OD6:OD5 contain the product identification (ID)
number, equal to 00 for the present dual 20 m
product.
• bit OD5 = OLON_s: OpenLoad in ON state on channel s.
(The threshold value above which this fault is triggered
depends on the selected current sense ratio; for CSR0 @
150 mA typ. and for CSR1 @ 7.0 mA typ.).
Bits OD4:OD3 report the logic state of the direct inputs
IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1,
OD3 = Ch. 0.
Bit OD2 reports a logic [1] in case an external clock error
occurred (if an external clock was selected by Clock_int = 0).
The Fault Status pin (FSB) is set to 0 (active Low) upon
occurrence of any of the above mentioned faults. Latched
faults can only be delatched by the procedure described in
Fault Delatching.
Bit OD1:OD0 report logic [1] in case a calibration failure
occurred during calibration of a channel’s internal clock
period.
The FAULTR_s register is reset when it is read out,
provided that the failure cause has disappeared and latched
faults have been delatched.
20XS4200
Analog Integrated Circuit Device Data
50
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 21 shows the electrical circuit of a typical truck
application. As an example, an external circuit is added that
takes over load control in case Fail-safe mode is activated
(FSOB goes low). This circuit allows keeping full control of
both channels in case of SPI failure.
VPWR
VDD
Voltage regulator
10 µF
100 nF
10 µF
100 nF
VPWR
VDD
VPWR
VDD
VDD
VPWR
VDD
100 k
10 k
100 nF
100 nF
1.0 µF
VDD
I/O
I/O
CLOCK
FSB
IN0
HS0
HS1
IN1
20XS4200
22 nF
22 nF
FSOB
MCU
SCLK
CSB
I/O
SO
SI
SCLK
CSB
RSTB
SI
SO
CONF0
CONF1
LOAD 0
M
8.0 k2
75 k
LOAD 1
I/O
SYNC
CSNS
A/D
GND
GND
1.0 k2
2.0 k
22 nF
10 k
10 k
VPWR
External Control Circuitry
direct controls (pedals, handles, etc.)
Figure 21. Typical Application with Two Different Load Types
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
TYPICAL APPLICATIONS
.
VPWR
VDD
Voltage regulator
10 µF
100 nF
10 µF
100 nF
VPWR
VDD
VPWR
VDD
VDD
VPWR
VDD
100 k
10 k
100 nF
1.0 µF
100 nF
VDD
I/O
I/O
CLOCK
FSB
IN0
IN1
HS0
M
22 nF
MCU
20XS4200
FSOB
SCLK
CSB
I/O
SCLK
CSB
RSTB
SI
LOAD
HS1
SO
SI
SO
CONF0
CONF1
75 k
75 k
I/O
SYNC
CSNS
A/D
GND
GND
1.0 k2
22 nF
2.0 k
10 k
VPWR
External Control Circuitry
direct controls (pedals, handles,...)
Figure 22. Two Channels in Parallel / Recommended External Current Sense Circuit
20XS4200
Analog Integrated Circuit Device Data
52
Freescale Semiconductor
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The FK package is a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board.
The AN2467 provides guidelines for Printed Circuit Board design and assembly.
PACKAGE MECHANICAL DIMENSIONS
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Table 24. Packaging Information
Package
Suffix
Package Outline Drawing Number
98ASA00428D
23-Pin PQFN
FK
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
.
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
54
Freescale Semiconductor
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
56
Freescale Semiconductor
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
58
Freescale Semiconductor
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
59
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
60
Freescale Semiconductor
PACKAGING
PACKAGE MECHANICAL DIMENSIONS
FK SUFFIX
23-PIN PQFN
98ASA00428D
ISSUE A
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
61
REVISION HISTORY
PACKAGE MECHANICAL DIMENSIONS
REVISION HISTORY
REVISION
DATE
5/2012
6/2012
5/2013
DESCRIPTION OF CHANGES
•
•
Initial release
1.0
2.0
3.0
Updated values in Table 4, Static Electrical Characteristics
•
•
Grammatical accuracy and form consistency changes made. No changes to content.
Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.
•
•
•
•
•
Added a table
8/2013
4.0
5.0
Introduction of parameters related to 20XS4200B device (Table 1).
Removed RDSON values at 1.0 A.
Rectification of the inversion between ∆tDLY values at slow and medium slew rate.
Added the 20XS4200B to the Systematic offset error (see Current Sense Errors) parameter.
•
•
•
•
•
•
Removed EK package information
11/2013
Removed all references to the SOIC package
Added 20XS4200BAFK to the ordering information
Introduction of parameters related to 20XS4200BAFK device
Removed Ecl_rep energy values
Update Ecl_sing value
20XS4200
Analog Integrated Circuit Device Data
Freescale Semiconductor
62
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC20XS4200
Rev. 5.0
11/2013
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