MC22XS4200BEK [NXP]
High-Side Switch, 24V, Dual 22mOhms, SOICW-EP 32, Rail;
| 型号： | MC22XS4200BEK |
| 厂家： | 
NXP |
| 描述： | High-Side Switch, 24V, Dual 22mOhms, SOICW-EP 32, Rail |
| 文件： | 总64页 (文件大小：1052K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC22XS4200
Rev. 5.0, 6/2018
NXP Semiconductors
Data Sheet: Advance Information
Dual 24 V, 22 mOhm high-side switch
22XS4200
The 22XS4200 device is part of a 24 V dual high-side switch product family with
integrated control, and a high number of protective and diagnostic functions. It
is designed for truck and bus applications. The low RDS(on) channels (<22 mΩ)
can control different load types; bulbs, solenoids, or DC motors. Control, device
configuration, and diagnostics are performed through a 16-bit serial peripheral
interface (SPI), allowing easy integration into existing applications. This device
is powered by SMARTMOS technology.
HIGH-SIDE SWITCH
Both channels can be controlled individually by external/internal clock signals,
or by direct inputs. Using the internal clock allows fully autonomous device
operation. Programmable output voltage slew rates (individually programmable)
helps improve electromagnetic compatibility (EMC) performance. To avoid
shutting off the device upon inrush current, while still being able to closely track
the load current, a dynamic overcurrent threshold profile is featured. Switching
current of each channel can be sensed with a programmable sensing ratio.
Whenever communication with the external microcontroller is lost, the device
enters a Fail-safe operation mode, but remains operational, controllable, and
protected.
CEK SUFFIX (PB-FREE)
98ASA00894D
32 PIN SOIC (10 mm X 11 mm)
BEK SUFFIX (PB-FREE)
98ASA00368D
32 PIN SOIC (10 mm X 11 mm)
Features
• Two fully-protected 22 mΩ (at 25 °C) high-side switches
• Up to 4.2 A steady state current per channel
• Separate bulb and DC motor latched overcurrent handling
• Individually programmable internal/external PWM clock signals
• Overcurrent, short-circuit, and overtemperature protection with
programmable autoretry functions
Applications
• Truck, bus and 24 V transportation systems
• Resistive, capacitive, and inductive loads
• Accurate temperature and current sensing
• Open load detection (channel in OFF and ON state), also for LED
applications (7.0 mA typ.)
• Normal operating range: 8.0 V to 36 V, extended range: 6.0 V to 58 V
• 3.3 V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz
VDD
VPWR
22XS4200
VDD
VDD
CLOCK
FSB
VPWR
I/O
I/O
SCLK
CSB
SI
SCLK
CSB
SO
RSTB
SI
IN0
HS0
HS1
LOAD
LOAD
MCU
I/O
SO
I/O
M
I/O
IN1
CONF0
CONF1
FSOB
SYNC
CSNS
I/O
A/D
A/D
GND
GND
Figure 1. Simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2018.
Table of Contents
1
2
3
4
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Pin assignment and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Functional internal block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Operation and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Logic commands and SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5
6
7
8
9
22XS4200
NXP Semiconductors
2
1
Orderable parts
Table 1. Orderable part variations
Part number (1)
Temperature (T )
Package
A
MC22XS4200BEK
MC22XS4200CEK
Notes
-40 °C to 125 °C
32 SOIC-EP
1. To order parts in tape and reel, add the R2 suffix to the part number.
22XS4200
3
NXP Semiconductors
2
Internal block diagram
VDD
VPWR
Drain/Gate
Clamp
Internal
Regulator
Over/Undervoltage
Protections
VDD Failure
Detection
Charge
Pump
POR
I
UP
VREG
CSB
SCLK
Selectable Slew Rate
Gate Driver
I
DWN
Selectable Overcurrent
Detection
HS0
SO
SI
RSTB
Severe Short-circuit
Detection
Short-circuit to
VPWR detec.
FSB
IN0
Control
Logic
Overtemperature
Detect.
IN1
FSOB
Open Load
Detect
CONF0
CONF1
HS0
HS1
HS1
VREG
Calibratable
Oscillator *
PWM
Module
*
Temperature
Feedback
Output
Current Sense
CLOCK
I
DWN
Analog MUX
Overtemperature
Prewarning
*blocks marked in grey have been implemented
independently for each of both channels
GND
SYNC
CSNS
Figure 2. Internal block diagram
22XS4200
NXP Semiconductors
4
3
Pin assignment
Transparent Top View
1
2
3
4
5
6
7
8
CONF1
CONF0
FSOB
IN1
CLOCK
RSTB
CSB
SCLK
SI
VDD
SO
GND
FSB
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IN0
CSNS
SYNC
GND
NC
NC
NC
HS0
HS0
HS0
NC
VPWR
33
9
10
11
12
13
14
15
16
NC
HS1
HS1
HS1
NC
NC
NC
Figure 3. Device pin assignments
The function of each pin is described in the section Functional description
Table 2. 22XS4200 pin description
Pin
Pin name
Function
Formal name
Definition
number
The clock input gives the time-base when the device is operated in external clock/internal
PWM mode. This pin has an internal pull-down current source.
1
CLOCK
Input
PWM Clock
This input pin is used to initialize the device’s configuration - and fault registers. Reset
puts the device in Sleep mode (low current consumption) provided it is not stimulated by
direct input signals. This pin is connected to GND by an internal pull-down resistor.
2
RSTB
Input
Reset
Chip Select (Active This input pin is connected to the SPI chip-select output of an external microcontroller.
3
4
CSB
Input
Input
Low)
CSB is internally pulled up to VDD by a current source IUP
.
This input pin is to be connected to an external SPI Clock signal. The SCLK pin is
SCLK
Serial Clock
internally connected to a pull-down current source IDWN
.
This input pin receives the SPI input data from an external device (microcontroller or
another extreme switch device in case of daisy-chaining). The SI pin is internally
5
6
SI
Input
Serial Input
connected to a pull-down current source IDWN
Digital Drain Voltage This is the positive supply pin of the SPI interface.
This output pin transmits SPI data to an external device (external microcontroller or the
.
VDD
Power
SI pin of the next SPI device in case of daisy-chaining). The pin doesn’t require external
pull-up or pull-down resistors, but a series resistor is recommended to limit current
consumption in case of GND disconnection.
7
SO
Output
Serial Output
These pins are the ground for the logic and analog circuitries of the device. For ESD and
electrical parameter accuracy purpose, the ground pins must be shorted in the board.
8, 25
9
GND
FSB
Ground
Output
Ground
Fault Status
(Active Low)
This open drain output pin (external pull-up resistor to VDD required) is set when the
device enters Fault mode (see Fault mode).
10, 11, 15,
16, 17, 18,
22, 23, 24
NC
N/A
Not connected
These pins may not be connected.
HS1
HS0
12, 13, 14,
19, 20, 21
Output
Power Switch Outputs Output pins of the switches, to be connected to the load.
22XS4200
5
NXP Semiconductors
Table 2. 22XS4200 pin description (continued)
Pin
Pin name
Function
Formal name
Definition
number
This output pin is asserted (active low) when the Current Sense (CS) output signal is
within the specified accuracy range. Reading the SYNC pin allows the external
microprocessor to synchronize to the device when operating in autonomous operating
Output Current
Monitoring
Synchronization
26
SYNC
Output
mode. SYNC is open drain and requires a pull-up resistor to VDD
.
This pin either outputs a current proportional to the channel’s output current or a voltage
proportional to the temperature of the GND pin (pin 14). Selection between current and
temperature sensing, as well as setting the current sensing sensitivity are performed
through the SPI interface. An external pull-down resistor must be connected between
CSNS and GND.
Output Current/
Temperature
Monitoring
27
CSNS
Output
Input
The IN[0: 1] input pins are used to directly control the switching state of both switches
and consequently the voltage on the HS0: HS1 output pins. The pins are connected to
GND by internal pull-down resistors.
IN0
IN1
28, 29
Direct Inputs
Fail-safe Output
(Active Low)
FSOB is asserted (active-low) upon entering Fail-safe mode (see Functional description)
30
31, 32
33
FSOB
Output
Input
This open drain output requires an external pull-up resistor to VPWR
.
CONF0
CONF1
The CONF[0: 1] input pins are used to select the appropriate overcurrent detection profile
(bulb/DC motor) for each of both channels. CONF requires a pull-down resistor to GND.
Configuration Input
This exposed pad connects to the positive power supply and is the drain of both internal
MOSFET switches.
VPWR
Power
Positive Power Supply
22XS4200
NXP Semiconductors
6
4
Electrical characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.
Symbol
Parameter
Maximum ratings
Unit
Notes
Electrical ratings
VPWR supply voltage range
• Load dump at 25 °C (350 ms)
• Reverse battery at 25 °C
58
-32
-60
VPWR
V
• Fast negative transient pulses (ISO 7637-2 pulse #1, VPWR=28 V & Ri=10 Ω)
VDD
VMAX,LOGIC
VFSO
VDD supply voltage range
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 58
-0.3 to VDD+0.3
58
V
V
V
V
V
V
A
(2) (3)
Voltage on input pins (except IN[0:1]) and Output pins) (except HS[0:1])
Voltage on fail-safe output (FSOB)
VSO
Voltage on SO pin
VIN,MAX
VHS[0:1]
IHS[0:1]
Voltage (continuous, max. allowable) on IN[0:1] inputs
Voltage (continuous, max. allowable) on output pins (HS [0:1]),
Rated continuous output current per channel
-32 to 58
4.2
(4)
(5)
Maximum allowable energy dissipation per channel and two parallel channels, single-
pulse method
ECL[0:1]_SING
36
mJ
ESD voltage
• Human body model (HBM) for HS[0:1], VPWR and GND
• Human body model (HBM) for other pins
• Charge device model (CDM)
V
V
±8000
±2000
ESD1
ESD2
(6)
V
Package corner pins (1, 13, 19, 20)
All other pins
V
V
±750
±500
ESD3
ESD4
Notes:
2. Concerned input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, and CSB.
3. Concerned output pins are: CSNS, SYNC, and FSB.
4. Output current rating valid as long as maximum junction temperature is not exceeded. For computation of the maximum allowable output current,
the thermal resistance of the package and the underlying heatsink must be taken into account.
5. Single pulse energy dissipation, single-pulse short-circuit method (LL = 0.5 mH, R = 48 mΩ V
= 28 V, T = 150 °C initial).
J
PWR
6. ESD testing is performed in accordance with the Human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model
(CDM), robotic (CZAP = 4.0 pF).
22XS4200
7
NXP Semiconductors
Table 3. Maximum ratings (continued)
All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.
Symbol
Parameter
Maximum ratings
Unit
Notes
Thermal ratings
Operating temperature
• Ambient
TA
TJ
-40 to 125
-40 to 150
°C
• Junction
TSTG
Storage temperature
-55 to 150
1.4
°C
°C/W
°C/W
°C
R
Thermal resistance junction to case (exposed pad)
Thermal resistance junction to ambient
θJC
θJA
(7)
R
22
(8),(9)
TPPRT
Peak package reflow temperature during reflow
Note 9
Notes:
7. Four layer board (2s2p), per JEDEC JESD51-6 with the board (JESD51-7) horizontal
8. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
9. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes), enter the core ID to view all orderable
parts, and review parametrics.
22XS4200
NXP Semiconductors
8
4.2
Static electrical characteristics
Table 4. Static electrical characteristics
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Supply electrical characteristics
Supply voltage range:
(10)
VPWR
• Full specification compliant
• Extended mode
8.0
6.0
24
–
36
58
V
V
supply current, device in Wake-up mode, channel On, open load
PWR
IPWR(ON)
–
–
6.5
6.5
8.5
8.5
mA
mA
outputs in ON-state, HS[0:1] open, IN[0:1] > V
IH
VPWR supply current, device in Wake-up mode (Standby), channel Off
open load in OFF-state detection disabled, HS[0:1] shorted to ground with
IPWR(SBY)
V
DD = 5.5 V and RSTB > VWAKE
Sleep state supply current
VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0:1] connected to ground
• TA = 25 °C
IPWR(SLEEP)
μA
–
–
3.0
–
10.0
60.0
• TA = 125 °C
VDD(ON)
V
V
supply voltage
3.0
–
5.5
V
DD
supply current at V
5.5 V
DD
DD =
(11)
IDD(ON)
• No SPI communication
• 8.0 MHz SPI communication
–
–
–
5.0
2.2
–
mA
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
V
sleep state current at V
5.5 V with or without VPWR
DD =
–
–
5.0
45.5
1.5
6.0
4.0
2.5
2.8
μA
V
DD
Overvoltage shutdown threshold
Overvoltage shutdown hysteresis
Undervoltage shutdown threshold
39
42
0.8
–
0.2
5.0
2.2
1.5
2.2
V
(12)
(12)
(12)
V
VPWR(POR)
VDD(POR)
V
V
V
Power-on reset (POR) voltage threshold
2.6
2.0
2.5
V
PWR
Power-on reset (POR) voltage threshold
V
DD
DD
VDD(FAIL)
supply failure voltage threshold (assumed VPWR > VPWR(UV)
)
V
ON-Resistance, Drain-to-Source (I = 1.0 A, T = 25 °C) CSNS_ratio = 0
HS
J
• V
• V
• V
= 8.0 V
= 28 V
= 36 V
PWR
PWR
PWR
–
–
–
18.7
18.7
18.7
–
–
–
RDS(on)25
mΩ
Notes
10. In Extended mode, availability of several device functions (channel control, value of R
, overtemperature protection) is guaranteed, but
DS(on)
compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown).
Above V , the channels can only be turned ON when the overvoltage detection function has been disabled.
PWR(OV)
11. Typical value guaranteed per design.
12. When the device recovers from undervoltage and returns to Normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see
Auto-retry), the device performs normally. When VPWR drops below V
and EMC performances).
, undervoltage is detected (see Undervoltage fault (Latchable fault)
PWR(UV)
22XS4200
9
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Electrical characteristics of the output stage (HS0 and HS1)
ON-Resistance, Drain-to-Source (I = 1.0 A,T = 150 °C) CSNS_ratio = 0
Parameter
Min.
Typ.
Max.
Unit
Notes
HS
J
• V
• V
• V
8.0 V
PWR =
–
–
–
–
–
–
43
43
43
RDS(on)150
mΩ
= 28 V
= 36 V
PWR
PWR
ON-Resistance, Drain-to-Source difference from one channel to the other in
Parallel mode (I = 1.0 A,T = 150 °C) CSNS_ratio = X
ΔRDS(on)150
mΩ
mΩ
-0.9
–
–
–
0.9
43
HS
J
ON-Resistance, Source-Drain (I = -1.0 A, T = 150 °C,
HS
J
RSD(on)150
V
= -24 V)
PWR
Max. detectable wiring length (2.5 mm²) for severe short-circuit detection
(see Severe short-circuit fault (Latchable fault)):
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected
LSHORT
30
55
110
100
175
365
180
300
620
cm
26.4
16.3
10.4
6.4
32
20.1
12.6
7.7
38.5
24.5
15.2
9.3
I_OCH1_0
I_OCH2_0
I_OCM1_0
I_OCM2_0
I_OCL1_0
I_OCL2_0
I_OCL3_0
Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0)
A
4.3
5.3
6.3
2.9
3.6
4.3
1.4
1.8
2.2
8.9
5.6
10.7
6.8
12.8
8.2
I_OCH1_1
I_OCH2_1
I_OCM1_1
I_OCM2_1
I_OCL1_1
I_OCL2_1
I_OCL3_1
3.5
4.25
2.7
5.1
Overcurrent detection thresholds with CSNS_ratio bit = 1(CSR1)
2.2
3.2
A
1.45
0.98
0.48
1.75
1.2
2.1
1.45
0.72
0.6
Output (HS[x]) leakage current in sleep state (positive value = outgoing)
• VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
IOUT_LEAK
–
+5.0
+5.0
+5.0
µA
µA
–
–
–
-120
-1400
VHS,OFF = VPWR, device in sleep state (VPWR = 36 V)
Output biasing current in off-state (positive value = outgoing)
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
• Fast slew rate selected
• Medium slew rate selected
• Slow slew rate selected
-620
-440
-330
-495
-360
-280
-380
-280
-230
IOUT_OFF
• With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V)
0
-
1000
VD_GND(CLAMP) Switch turn-on threshold for supply overvoltage (VPWR -GND)
58
–
67
V
V
Switch turn-on threshold for Drain-Source overvoltage (measured at
VDS(CLAMP)
58
–
–
66
I
OUT = 500 mA
Switch turn-on threshold for Drain-Source overvoltage difference from one
channel to the other in Parallel mode (at IHS = 500 mA)
ΔVDS(CLAMP)
-2.0
+2.0
V
22XS4200
NXP Semiconductors
10
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Electrical characteristics of the output stage (HS0 and HS1) (continued)
Current Sensing Ratio
(13)
(14)
CSR0
CSR1
• CSNS_ratio bit = 0 (high current mode)
• CSNS_ratio bit = 1 (low current mode)
–
–
1/1500
1/500
–
–
–
I_LOAD_MIN
ICSR_LEAK
Minimum measurable load current with compensated error
–
–
–
50
+4.0
–
mA
µA
CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0)
-4.0
–
I_LOAD_ERR_SYS Systematic offset error (see Current sense errors)
I_LOAD_ERR_RAND Random offset error
-4.0
–
mA
mA
mA
-125
5.15
125
–
ICSNS,MAX
CSNS pin current sourcing capability, absolute upper limit
output current sensing error (%), uncompensatedat output current level
–
E
SR0
(sense ratio CSR0 selected):
TJ = -40 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 125 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 25 °C to 125 °C
• 3.0 A
-13
-12
-17
-26
–
–
–
–
13
12
17
26
(15)
-10
-9.0
-12
-15
–
–
–
–
10
9.0
12
15
ESR0_ERR
%
-10
-10
-12
-16
–
–
–
–
10
10
12
16
• 1.5 A
• 0.75 A
• 0.375 A
Notes:
13. Current sense ratio CSRx = ICSNS / (IHS[x] +I_LOAD_ERR_SYS
)
14. See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration (see Application Note).
15. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
22XS4200
11
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Electrical characteristics of the output stage (HS0 and HS1) (continued)
E
output current sensing error (%) after offset compensation at output
SR0
current level (sense ratio CSR0 selected):
TJ = -40 °C
• 3.0 A
-11
-11
-11
-11
–
–
–
–
11
11
11
11
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 125 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 25 °C to 125 °C
• 3.0 A
(16)
-9.0
-9.0
-9.0
-10
–
–
–
–
9.0
9.0
9.0
10
ESR0_ERR(Comp)
%
-10
-9.0
-9.0
-10
–
–
–
–
10
9.0
9.0
10
• 1.5 A
• 0.75 A
• 0.375 A
E
output current sensing error (%), uncompensated at output current level
SR1
(sense ratio CSR1 selected):
TJ = -40 °C
-16
-10
-12
–
–
–
16
10
12
• 0.75 A
(16)
ESR1_ERR
%
TJ = 125 °C
• 0.75 A
TJ = 25 °C to 125 °C
• 0.75 A
E
output current sensing error (%) after offset compensation at output
SR1
current level (sense ratio CSR1 selected):
TJ = -40 °C
• 0.75 A
-11
-14
-19
-29
–
–
–
–
11
14
19
29
• 0.25 A
• 0.125 A
• 0.075 A
TJ = 125 °C
• 0.75 A
(17)
-9.0
-10
-12
-16
–
–
–
–
9.0
10
12
16
ESR1_ERR(Comp)
%
• 0.25 A
• 0.125 A
• 0.075 A
TJ = 25 °C to 125 °C
• 0.75 A
-9.0
-11
-13
-21
–
–
–
–
9.0
11
13
21
• 0.25 A
• 0.125 A
• 0.075 A
Notes:
16. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
17. See note (18), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration.
22XS4200
NXP Semiconductors
12
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Electrical characteristics of the output stage (HS0 and HS1) (continued)
E
output current sensing error in parallel mode (%), uncompensated) at
SR0
outputs current level (sense ratio CSR0 selected):
TJ = -40 °C
• 6.0 A
-10
-11
–
–
10
11
• 3.0 A
(18)
TJ = 125 °C
• 6.0 A
ESR0_ERR_PAR
%
-8.0
-8.0
–
–
8.0
8.0
• 3.0 A
TJ = 25 °C to 125 °C
• 6.0 A
-9.0
-9.0
–
–
9.0
9.0
• 3.0 A
VCL(CSNS)
IOLD(OFF)
Current sense clamping voltage (condition: R(CSNS) > 10 kΩ)
Open load detection current threshold in OFF state
Open load fault detection voltage threshold
5.5
30
–
–
–
7.5
100
5.5
V
μA
V
VOLD(THRES)
4.0
Open load detection current threshold in ON state (see Open load detection
in On state (OL_ON)):
IOLD(ON)
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this
function)
40
4.0
150
7.0
300
10
mA
Time period of the periodically activated open load in ON state detection for
CSNS_ratio bit = 1
tOLLED
VOSD(THRES)
VCL
105
150
195
ms
V
Output shorted-to-V
detection voltage threshold (channel in OFF state) VPWR-1.2 VPWR-0.8 VPWR-0.4
PWR
Switch turn-on threshold for negative output voltages (protects against
negative transients) - (measured at IOUT = 100mA, channel in OFF state)
-38
–
–
-32
V
Switch turn-on threshold for negative output voltages difference from one
channel to the other in parallel mode - (measured at IOUT = 100 mA, channel
in OFF state)
ΔVCL
-2.0
+2.0
V
VHS_TH
TSD
Switching State (On/Off) discrimination thresholds
0.45*VPWR 0.5*VPWR 0.55*VPWR
160 175 190
V
Shutdown temperature (power MOSFET junction; 6.0 V < VPWR < 58 V)
°C
Notes:
18. Minimum required value of open load impedance for detection of open load in OFF-state: 200 kΩ.(VOLD(THRES) = VHS at IOLD(OFF)
)
22XS4200
13
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Electrical characteristics of the control interface pins
(19)
(19)
(20)
(21)
(22)
(23)
VIH
VIL
Logic input voltage, high
2.0
-0.3
1.0
5.0
5.0
25
–
–
5.5
0.8
2.2
20
V
Logic input voltage, low
V
VWAKE
IDWN
Wake-up threshold voltage (IN[0:1] and RSTB)
Internal pull-down current source (on inputs: CLOCK, SCLK and SI)
Internal pull-up current source (input CSB)
Internal pull-up current source (input CONF[0:1])
Capacitance of SO, FSB and FSOB pins in tri-state
Internal pull-down resistance (RSTB and IN[0:1])
Input capacitance
–
V
–
μA
μA
μA
pF
kΩ
pF
IUP_CSB
IUP_CONF
CSO
–
20
–
100
20
–
–
RDWN
CIN
125
–
250
4.0
500
12
(24)
SO high-state output voltage
• (IOH = 1.0 mA)
VSOH
VDD-0.4
–
–
–
–
V
V
SYNC, SO, FSOB and FSB low-state output voltage
• (IOL = -1.0 mA)
VSOL
0.4
SYNC, SO, CSNS, FSOB and FSB tri-state leakage current:
• 0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V
or V(CSNS) = 0.0 V
ISO(LEAK)
-2.0
0.0
2.0
μA
kΩ
CONF[0:1]: Required values of the external pull-down resistor
• Lighting applications
RCONF
1.0
50
–
–
10
Infinite
• DC motor applications
Notes
19. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR
and can tolerate voltages up to 58 V.
20. Voltage above which the device wakes up
21. Valid for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V
22. Valid for VCSB < 2.0 V. CSB has an internal pull-up current source derived from VDD
23. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V).
24. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process
but is not tested in production.
22XS4200
NXP Semiconductors
14
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Output voltage switching characteristics
Rising and falling edges medium slew rate (SR[1:0] = 00)
• VPWR = 16 V
SRR_00
SRF_00
0.4
0.6
0.7
–
–
–
1.2
1.8
2.1
(25)
V/μs
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges low slew rate (SR[1:0] = 01)
• VPWR = 16 V
SRR_01
SRF_01
0.2
0.3
0.35
–
–
–
0.6
0.9
1.05
(25)
(25)
V/μs
V/μs
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges high slew rate / SR[1:0] = 10)
• VPWR = 16 V
SRR_10
SRF_10
0.8
1.2
1.4
–
–
–
2.5
3.6
4.2
• VPWR = 28 V
• VPWR = 36 V
Rising/falling edge slew rate matching (SRR /SRF)
• 16 V < VPWR < 36 V
ΔSR
ΔSR
0.75
–
1.25
Edge slew rate difference from one channel to the other in Parallel
mode
16 V < VPWR < 36 V
SR[1:0] = 00
SR[1:0] = 01
(25)
(26)
V/μs
μs
-0.16
-0.08
-0.32
0.0
0.0
0.0
0.16
0.08
0.32
SR[1:0] = 10
Output Turn-ON and Turn-OFF Delays (medium slew rate:
SR[1:0] = 00)
tDLY_00
6.0
–
60
• 16 V < VPWR < 36 V
Output Turn-ON and Turn-OFF delays (low slew rate / SR[1:0] = 01)
• 16 V < VPWR < 36 V
(26)
(26)
tDLY_01
10
–
–
120
35
μs
μs
Output Turn-ON and Turn-OFF delays (high slew rate / SR[1:0] = 10)
• 16 V < VPWR < 36 V
tDLY_10
4.0
Turn-ON and Turn-OFF delay time matching (tDLY(ON) - tDLY(OFF)
• fPWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 00
)
ΔtRF_00
ΔtRF_01
ΔtRF_10
-25
-50
-13
–
–
–
25
50
13
μs
μs
μs
Turn-ON and Turn-OFF delay time matching (tDLY(ON) - tDLY(OFF)
• fPWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 01
)
Turn-ON and Turn-OFF Delay time matching (tDLY(ON) - tDLY(OFF)
• fPWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 10
)
Notes
25. Rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay).
26. Turn-ON delay time measured as delay between a rising edge of the channel control signal (IN[0:1] = 1) and the associated rising edge of the
output voltage up to: VHS[0:1] = VPWR / 2 (where RL = 25 Ω). Turn-OFF delay time is measured as time between a falling edge of the channel
control signal (IN[0:1] = 0) and the associated falling edge of the output voltage up to the instant at which:
VHS[0:1] = VPWR / 2 (RL = 25 Ω)
22XS4200
15
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Output voltage switching characteristics (continued)
Delay time difference from one channel to the other in Parallel mode
Parameter
Min.
Typ.
Max.
Unit
Notes
16 V < VPWR < 36 V
SR[1:0] = 00
SR[1:0] = 01
(27)
Δt(DLY)
-25
-50
-12
0.0
0.0
0.0
25
50
12
μs
SR[1:0] = 10
(28)
(29)
tFAULT
Fault detection delay time
Output shutdown delay time
–
–
5.0
10
8.0
15
μs
μs
tDETECT
Current sense output settling time for SR[1:0] = 00 (medium slew rate)
• 16 V < VPWR < 36 V
(30)
(30)
(30)
tCSNSVAL_00
tCSNSVAL_01
tCSNSVAL_10
0.0
0.0
0.0
–
–
–
200
315
165
μs
μs
μs
Current sense output settling time for SR[1:0] = 01(low slew rate)
• 16 V < VPWR < 36 V
Current sense output settling time for SR[1:0] = 10 (high slew rate)
• 16 V < VPWR < 36 V
(30)
(30)
(30)
(30)
(30)
(30)
tSYNCVAL_00
tSYNCVAL_01
tSYNCVAL_10
tSYNREAD_00
tSYNREAD_01
tSYNREAD_10
SYNC output signal delay for SR[1:0] = 00 (medium SR)
SYNC output signal delay for SR[1:0] = 01 (low SR)
20
40
–
–
–
–
–
–
120
240
60
μs
μs
μs
µs
µs
µs
SYNC output signal delay for SR[1:0] = 10 (high SR)
10
Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate)
Recommended sync_to_read delay SR[1:0] = 01 (low slew rate)
Recommended sync_to_read delay SR[1:0] = 10 (high slew rate)
0.0
0.0
0.0
150
150
150
tOCH1
tOCH2
6.0
12.0
8.6
17.2
11.2
22.4
Upper overcurrent threshold duration
ms
ms
ms
tOCM1_L
tOCM2_L
48
96
67
137
87
178
Medium overcurrent threshold duration (CONF = 0; Lighting profile)
Medium overcurrent threshold duration (CONF = 1; DC motor profile)
tOCM1_M
tOCM2_M
96
245
137
350
178
455
Notes
27. Rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay).
28. Time required to detect and report the fault to the FSB pin.
29. Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured between start
of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR
30. Settling time ( = tCSNSVAL_XX), SYNC output signal delay ( = tSYNCVAL_XX) and Read-out delay ( = tSYNREAD_XX) are defined for a stepped load
current (100 mA< I(LOAD)<IOCLX A FOR CSNS_RATIO_S = 1, AND 300 mA< I(LOAD)<IOCLX A_0 FOR CSNS_RATIO_S = 0). See Figure 9 and
Output current monitoring (CSNS).
22XS4200
NXP Semiconductors
16
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Frequency and PWM duty cycle ranges (protections fully operational, see Protective functions) (31)
fCONTROL
fPWM_EXT
Switching frequency range - direct inputs
0.0
20
–
–
1000
1000
Hz
Hz
Switching frequency range - external clock with internal PWM
(recommended)
Switching frequency range - internal clock with internal PWM
(recommended)
fPWM_INT
60
–
–
1000
100
Hz
%
RCONTROL
Duty cycle range
0.0
Availability diagnostic functions for CSR0 over duty cycle and switching frequency
(protections and diagnostics both fully operational, see Diagnostic features for the exact boundary values)
Available duty cycle range, fPWM = 1.0 kHz high slew rate, PWM mode
• OL_OFF
(32)
(32)
(32)
(32)
(32)
0.0
35
0.0
–
–
–
62
100
90
RPWM_1K_H
RPWM_400_M
RPWM_400_H
RPWM_200_L
RPWM_200_M
RPWM_100_L
%
%
%
%
%
%
• OL_ON
• OS
Available duty cycle range, fPWM = 400 Hz, medium slew rate, PWM
mode
• OL_OFF
• OL_ON
• OS
0.0
21
0.0
–
–
–
81
100
88
Available duty cycle range, fPWM = 400 Hz, high slew rate, PWM mode
• OL_OFF
• OL_ON
• OS
0.0
14
0.0
–
–
–
84
100
95
Available duty cycle range, fPWM = 200 Hz, low slew rate mode, PWM
mode
• OL_OFF
• OL_ON
• OS
0.0
15
0.0
–
–
–
86
100
93
Available duty cycle range, fPWM = 200 Hz, medium slew rate, PWM
mode
• OL_OFF
• OL_ON
• OS
0.0
11
0.0
–
–
–
90
100
94
Available duty cycle range, fPWM = 100 Hz in low slew rate, PWM mode
• OL_OFF
• OL_ON
• OS
(32)
(33)
0.0
8.0
0.0
–
–
–
93
100
96
AFPWM(CAL)
fPWM(0)
Notes
Deviation of the internal clock PWM frequency after calibration
Default output frequency when using an uncalibrated oscillator
-10
–
+10
520
%
280
400
Hz
31. In Direct input mode, the lower frequency limit is 0 Hz with RSTB=5.0 V and 4.0 Hz with RSTB = 0.0 V. Duty Cycle applies to instants at which
VHS = 50 % VPWR. For low duty cycle values, the effective value also depends on the value of the selected slew rate.
32. The device can be operated outside the specified duty cycle and frequency ranges (basic protective functions OC, SC, UV, OV, OT remain active)
but the availability of the diagnostic functions OL_ON, OL_OFF, OS is affected.
33. Values guaranteed from 60 Hz to 1.0 kHz (recommended switching frequency range for internal clock operation).
22XS4200
17
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Availability diagnostic functions over duty cycle and switching frequency (Continued)
(protections & diagnostics both fully operational, see Diagnostic features for the exact boundary values)
Minimal required low time during calibration of the internal clock
through CSB
tCSB(MIN)
tCSB(MAX)
fCLOCK
1.0
70
15
1.5
100
–
2.0
130
512
μs
μs
Maximal allowed low time during calibration of the internal clock
through CSB
Recommended external clock frequency range (external clock/PWM
Module)
kHz
fCLOCK(MAX)
fCLOCK(MIN)
Upper detection threshold for external clock frequency monitoring
Lower detection threshold for external clock frequency monitoring
512
5.0
730
7.0
930
10
kHz
kHz
Timing: SPI port, IN[0]/ IN[1] signals and autoretry
Required low time allowing delatching or triggering Sleep mode (Direct
input mode)
tIN
175
217
250
310
325
400
ms
ms
Watchdog timeout for entering Fail-safe mode due to loss of SPI
contact
(34)
tWDTO
Auto-Retry repetition period (when activated):
• Auto_period bits = 00
105
52.5
26.2
13.1
150
75
7.5
195
97.5
47.8
24.4
tAUTO_00
tAUTO_01
tAUTO_10
tAUTO_11
• Auto_period bits = 01
• Auto_period bits = 10
• Auto_period bits = 11
ms
17.7
GND pin temperature sensing function
TOTWAR Thermal prewarning detection threshold
(35)
110
918
125
140
°C
Temperature sensing output voltage at TA = 25 °C (470 Ω < RCSNS
10 kΩ)
<
TFEED
1078
1238
mV
Gain temperature sensing output at TA = 25 °C (470 Ω < RCSNS
10 kΩ)
<
(35)
(35)
(35)
DTFEED
TFEED_ERROR
TFEED_ERROR_CAL
Notes
10.7
-15
11.1
–
11.5
+15
mV/°C
°C
Temperature sensing error, range [-40 °C, 150 °C], default
Temperature sensing error, [-40 °C, 150 °C] after 1 point calibration at
25 °C
-5.0
–
+5.0
°C
34. Only when the WD_dis bit set to logic [0] (default). Watchdog timeout defined from the rising edge on RST to rising edge HS[0,1]
35. Values were obtained by lab. characterization
36. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k.
22XS4200
NXP Semiconductors
18
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SPI interface electrical characteristics (36)
(42)
(37)
fSPI
Maximum operating frequency of the Serial Peripheral Interface (SPI)
Required low-state duration for reset RSTB
–
–
–
8.0
–
MHz
tWRSTB
10
μs
Required duration from the rising to the falling edge of CSB (required
setup time)
(38)
tCSB
1.0
–
–
μs
(38)
(38)
(38)
(38)
(38)
(39)
(39)
tENBL
tLEAD
Rising edge of RSTB to falling edge of CSB (required setup time)
Falling edge of CSB to rising edge of SCLK (required setup time)
Falling edge of SCLK to rising edge of CSB (required setup lag time)
Required high state duration of SCLK (required setup time)
Required low state duration of SCLK (required setup time)
SI to falling edge of SCLK (required setup time)
5.0
500
60
–
–
–
–
–
–
–
–
–
–
–
–
–
–
μs
ns
ns
ns
ns
ns
ns
tLAG
tWSCLKh
tWSCLKl
tSI(SU)
tSI(H)
50
50
15
Falling edge of SCLK to SI (required hold time of the SI signal)
30
SO rise time
• CL = 80 pF
tRSO
–
–
–
–
20
20
ns
ns
SO fall time
tFSO
• CL = 80 pF
(39)
(39)
(40)
tRSI
tFSI
SI, CSB, SCLK, Max. Rise Time allowing operation at fSPI = 8.0 MHz
SI, CSB, SCLK, Max. Fall Time allowing operation at fSPI = 8.0 MHz
Time from rising edge of SCLK to reach a valid level at the SO pin
–
–
–
–
–
–
11
11
44
ns
ns
ns
tVALID
Time from falling edge of CSB to reach low-impedance on SO (access
time)
(41)
tSOEN
–
–
30
ns
Notes:
37. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs inactive).
38. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state.
39. Rise and Fall time of incoming SI, CSB, and SCLK signals.
40. Time required for output data to be available for use at SO, measured with a 1.0 kΩ series resistor connected CSB.
41. Time required for output data to be terminated at SO measured with a 1.0 kΩ series resistor connected CSB.
42. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V) ceramic speed-
up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, CS
22XS4200
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NXP Semiconductors
4.4
Timing diagrams
IN[0:1]
High Logic Level
Low Logic Level
Time
Time
or
CSB
High Logic Level
Low Logic Level
VHS[0:1]
RPWM range defined for 50% of VPWR
V
PWR
50%V
PWR
Time
tDLY_XX
(tDLY(OFF)
tDLY_XX
(tDLY(ON)
VHS[0:1]
)
)
80% V
20% V
PWR
SRF
SRR
PWR
Time
Figure 4. Output voltage slew rate and delay
Bulb profile: CONFs = 0 (V (pin 31/32) <0.8 V).
Static overcurrent protection profile activated once per turn-on.
Default levels shown as solid lines
I
OCH1
I
OCH2
I
OCM1
OCM2
Load
Current
I
I
I
OCL1
OCL2
I
OCL3
Time
t
OCM2_L
OCM1_L
t
t
OCH2
t
OCH1
Figure 5. Overcurrent protection profile for bulb applications
22XS4200
NXP Semiconductors
20
I
I
OCH1
Inductive Load profile:
CONFs = 1 (V (pin 31/32) > 2.0 V)
OCH2
Default levels shown as solid lines
Dynamic overcurrent window, activated
when the IOCLx threshold is crossed
Load
Current
I
OCL1
I
OCL2
Load current
Time
I
OCL3
t
OCM2_M
t
OCM1_M
t
OCH2
t
OCH1
Figure 6. Overcurrent protection profile for applications with inductive loads (DC motors, solenoids)
RSTB
CSB
V
V
IH
IL
10% VDD
t
t
CSB
ENBL
t
WRSTB
90% VDD
V
V
IH
IL
10% VDD
t
RSI
t
WSCLKh
t
LAG
t
LEAD
V
V
IH
IL
90% VDD
10% VDD
SCLK
t
SI(SU)
t
WSCLKl
t
FSI
t
SI(H)
V
V
IH
IL
90% VDD
10% VDD
SI
Must be Valid
Don’t Care
Must be Valid
Don’t Care
Don’t Care
t
t
SOEN
SODIS
V
V
IH
IL
Tri-stated
Tri-stated
SO
Figure 7. Timing requirements during SPI communication
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NXP Semiconductors
t
t
FSI
RSI
V
V
OH
OL
90% VDD
50%
SCLK
10% VDD
V
V
OH
OL
10% VDD
SO
t
RSO
Low to High
t
VALID
t
FSO
SO
V
V
OH
OL
High To Low
90% VDD
10% VDD
Figure 8. Timing diagram for serial output (SO) data communication
turn-on
control
turn-off
control
(from IN_s or CSB)
(from IN_s or CSB)
VHS[0:1]
See Figure 4
V
PWR
50%V
PWR
Time
tDLY_XX
(tDLY(ON)
tDLY_XX
(tDLY(OFF
VCSNS
)
)
95% of scaled
output current
Track & Hold Mode
synchronous Mode
Time
Time
tSYNCVAL
VSYNC
5.0 V
tCSNSVAL_XX
tSYNREAD_XX
0.0 V
Figure 9. Synchronous and track-and-hold current sensing modes: associated delay and settling time
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NXP Semiconductors
22
5
Functional description
5.1
Introduction
The 22XS4200 is a two-channel, 24 V high-side switch with integrated control and diagnostics designed for truck and bus applications.
The device provides a high number of protective functions. Both low RDS(on) channels (<22 mΩ) can independently drive various load
types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy
chain capability.
Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels
can independently be operated in three different switching modes: internal clock and internal PWM mode (fully autonomous operation),
external clock and internal PWM mode, and direct control switching mode.
Current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (LED) monitoring.
By activating the Track & Hold mode, current monitoring can be performed during the switch-Off phase. This allows random access to the
current sense functionality. A patented offset compensation technique further enhances current sense accuracy.
To avoid turning off upon inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For
bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be
protected from overheating by activating a specific window-shaped overcurrent profile that allow stall currents of limited duration.
Whenever communication with the external micro-controller is lost, the device enters Fail-safe operation mode, but remains operational,
controllable, and protected.
5.2
Pin assignment and functions
Functions and register bits that are implemented independently for both channels have extension “_s”. Maximum ratings of the pins are
given in Table 3.
5.2.1
Output current monitoring (CSNS)
The CS pin allows independent current monitoring of channel 0 or channel 1 up to the steady-state overcurrent threshold. It can also be
used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate
value (Table 23). When the CSNS pin is sensed during switch-off in the (optional) Track & Hold mode (see Figure 9), it outputs the scaled
value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of devices
the current of which is not monitored must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in the GCR
register (Table 10). Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage’s rising edge
(HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS-pin has settled to ±5.0% of its final value. Anytime an
overcurrent window is active, the CSNS pin is disabled (see Overcurrent detection on resistive and inductive loads). The current and
temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In
order to generate a voltage output, a pull-down resistor is required (R(CSNS)=1.0 kΩ typ. and 470 < R(CSNS) < 10 k). When the current
sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents
up to about 5.6 mA.
5.2.2
Current sense synchronization (SYNC)
To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. SYNC
is asserted logic low when the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the
specified accuracy tSYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is
generated. The rising edge that is generated by the SYNC pin at the turn-OFF instant (internal or external) may also be used to implement
synchronization with the external MCU. Parameter tSYNCVAL_XX is defined as the time between the instant at the middle of the output-
voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC
pins of different devices can be connected together to save µ-controller input channels. However, in this configuration, the CSNS function
of only one device should be active at a time. Otherwise, the MCU does not determine the origin of the SYNC signal. The SYNC pin is
open drain and requires an external pull-up resistor to VDD.
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NXP Semiconductors
5.2.3
Direct control inputs (IN0 and IN1)
The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on (Channel control
in Normal mode). When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wake it up (Sleep mode). If
it is desired to automatically turn on the channels after a transition to Fail-safe mode, inputs IN[0] and IN[1] must be externally connected
to the VPWR pin by a pull-up resistor (e.g. 10 kΩ typ.). However, this prevents the device from going into Sleep mode. Both IN pins are
internally connected to a pull-down resistor.
5.2.4
Configuration inputs (CONF0 and CONF1)
The CONF[0:1] input pins allow configuring both channels for the appropriate load type. CONF = 0 activates the bulb overcurrent
protection profile, and CONF = 1 the DC motor profile. These inputs are connected to an internal voltage regulator of 3.3 V by an internal
pull-up current source IUP. Therefore, CONF = 1 is the default value when these pins are disconnected. Details on how to configure the
channels are given in Table 9.
5.2.5
Fault status (FSB)
This open drain output is asserted low when any of the following faults occurs (see Fault mode): overcurrent (OC), overtemperature (OT),
Output connected to VPWR, Severe short-circuit (SC), open load in ON state (OL_ON), open load in OFF state (OL_OFF), External Clock-
fail (CLOCK_fail), overvoltage (OV), undervoltage (UV). Each fault type has its own assigned bit inside the STATR, FAULTR_s, or
DIAGR_s register. Fault type identification and fault bit reset are accomplished by reading out these registers. They are part of the SO
register (Fault mode) and are accessed through the SPI port.
5.2.6
PWM clock (CLOCK)
This pin is the input for an external clock signal that controls the internal PWM module.The clock signal is monitored by the device. The
PWM module controls ON-time and turn-ON delay of the selected channels. The CLOCK pin should not be confused with the SCLK pin,
which is the clock pin of the SPI interface. CLOCK has an internal pull-down current source (IDWN) to GND.
5.2.7
Reset (RSTB)
All SPI register contents are reset when RSTB = 0. When RSTB = 0, the device returns to Sleep mode tIN sec. after the last falling edge
of the last active IN[0:1] signal. As long as the Reset input (RSTB pin) is at logic 0 and both direct input states are low, the device remains
in Sleep mode (Channel configuration through the SPI). A 0-to-1 transition on RSTB wakes up the device and starts a watchdog timer to
check the continuous presence of the SPI signals. To do this, the device monitors the contents of the first bit (WDIN bit) of all SPI words
following that transition (regardless the register it is contained in). When this contents is not alternated within a duration tWDTO, SPI
communication is considered lost, and Fail-safe mode is entered (Entering fail-safe mode). RSTB is internally pulled-down to GND by
resistor RDWN
.
5.2.8
Chip select (CSB)
Data communication over the SPI port is enabled when the CSB pin is in the logic [0] state. Data from the Input Shift registers are locked
in the addressed SI registers on the rising edge of CSB. The device transfers the contents of one of the eight internal registers to the SO
register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a
logic [0] state only when SCLK is at logic [0] (Figure 7 and Figure 8). CSB is internally pulled up to VDD through IUP
.
5.2.9
SPI serial clock (SCLK)
The SCLK pin clocks the SPI data communication of the device. The serial input pin (SI) transfers data to the SI shift registers on the
falling edge of the SCLK signal while data in the SO registers are transferred to the SO pin on the rising edge of the SCLK signal. The
SCLK pin must be in low state when CSB makes any transition. For this reason, it is recommended to have the SCLK pin in the logic [0]
state when the device is not accessed (CSB is at logic [1]). When CSB is set to logic [1], the signals at the SCLK and SI pins are ignored
and the SO output is tri-stated (high-impedance). The SCLK pin is connected to an internal pull-down current source IDWN
.
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NXP Semiconductors
24
5.2.10 Serial input (SI)
Serial input (SI) data bits are shifted in at this pin. SI data is read on the falling edge of SCLK. 16-bit data packages are required on the
SI pin (see Figure 7), starting with bit D15 (MSB) and ending with D0 (LSB). All the internal device registers are addressed and controlled
by a 4-bit address (D9-D12) described in Table 14. Register addresses and function attribution are described in Table 15. The SI pin is
internally connected to a pull-down current source, IDWN
.
5.2.11 Supply of the digital circuitry (VDD)
This pin supplies the SPI circuit (3.3 V or 5.0 V). When lost, all circuitry becomes supplied by a VPWR derived voltage, except the SPI’s
SO shift-register that can no longer be read.
5.2.12 Ground (GND)
This is the GND pin common for both the SPI and the other circuitry.
5.2.13 Positive supply pin (VPWR)
This pin is the positive supply and the common input pin of both switches. A 100 nF ceramic capacitor must be connected between VPWR
and GND, close to the device. In addition, it is recommended to put a ceramic capacitor of at least 1.0 µF in parallel with this 100 nF
capacitor.
5.2.14 Serial output (SO)
The SO pin is a tri-stateable output pin that conveys data from one of the 13 internal SO registers or from the previous SI register to the
outside world. The SO pin remains in a high-impedance state (tri-state) until the CSB pin becomes logic [0]. It then transfers the SPI data
(device state, configuration, fault information). The SO pin changes state at the rising edge of the SCLK signal. For daisy-chaining, it can
be read out on the falling edge of SCLK. VDD must be present before the SO registers can be read. The SO register assignment is
described in Table 13.
5.2.15 Power switch output pins (HS0 and HS1)
HS0 and HS1 are the output pins of the power switches, to be connected to the loads. A ceramic capacitor (<= 22 nF (+/- 20%) is
recommended between these pins and GND for optimal EMC performances.
5.2.16 Fail-safe output (FSOB)
This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This open drain output requires an
external pull-up resistor to VPWR.
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25
NXP Semiconductors
5.3
Functional internal block description
POWER SUPPLY
internal regulator
SELF-
PROTECTED
HIGH-SIDE
SWITCHES
MCU
MCU INTERFACE and
OUTPUT CONTROL
INTERFACE
HS0-HS1
SPI INTERFACE
PARALLEL CONTROL
INPUTS
PWM CONTROLLER
Figure 10. Internal block description
5.3.1
Power supply
The device operates with supply voltages from 6.0 V to 58 V (VPWR), but is full spec. compliant between 8.0 V and 36 V. The VPWR pin
supplies power to the internal regulator, analog, and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the output register of the Serial
Peripheral Interface (SPI). Consequently, the SPI registers cannot be read without presence of VDD. The employed IC architecture
guarantees a low quiescent current in Sleep mode.
5.3.2
Switch output pins HS0 and HS1
HS0 and HS1 are the output pins of the power switches. Both channels are protected against various kinds of short-circuits and have
active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available.
For large inductive loads, it is recommended to use a freewheeling diode. The device can be configured to control the output switches in
parallel, which guarantees good switching synchronization.
5.3.3
Communication interface and device control
In Normal mode the output channels can either be controlled by the direct inputs or by the internal PWM module, which is configured by
the SPI register settings. For bidirectional SPI communication, VDD has to be in the authorized range. Failure diagnostics and
configuration are also performed through the SPI port. The reported failure types are: open load, short-circuit to battery, severe short-
circuit to ground, overcurrent, overtemperature, clock-fail, undervoltage, and overvoltage. The SPI port can be supplied either by a 5.0 V
or by a 3.3 V voltage supply. For direct input control, VDD is not required.
A pulse width modulation (PWM) circuit allows driving loads at frequencies up to 1.0 kHz from an external or an internal clock. SPI
communication is required to set these options.
22XS4200
NXP Semiconductors
26
6
Functional device operation
6.1
Operation and operating modes
The device possesses two high-side switches (channels) each of which can be controlled independently. The device has four fundamental
operating modes: Sleep, Normal, Fail-safe, and Fault mode, as shown in Table 6.
Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal
(autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required
(VDD = 5.0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD is not required.
6.1.1
Device start-up sequence
To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However,
it should not be woken up earlier than the moment at which VPWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has
exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting
RSTB=1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ]= 1 (see
Figure 11). After wake-up, all SPI register contents are reset (as defined in Table 12 and Table 13) and Normal mode is entered. All the
device functions are available 50 µs later (typically).
If the start-up sequence is not performed at device start-up, its configuration may be undetermined and correct operation is not
guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up
event after the moment VPWR has reached the undervoltage threshold.
6.1.2
Channel configuration through the SPI
Setting the channel configuration
6.1.2.1
The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent
(OCR_s) registers. They allow setting, among others, the following parameters: duty cycle, delay, Slew Rate, PWM enable (PWM_en),
clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension “_s” means that these registers exist for each
of both channels. Function assignment is described in detail in the section SI register addressing.
6.1.2.2
Reading back the channel’s status and settings
The channel’s global switching and operating states (On/Off, normal/fault) are all contained in the SO-STATR register (see Table 16). The
precise fault type can be found by reading out the FAULTR_s and STATR registers. The current channel settings (channel configuration)
can be known by reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG registers (see section Serial output register assignment
and beyond).
6.1.3
Normal mode
Normal mode (bit NM = 1) can be entered in two ways: either by driving the device through the direct inputs (IN[x]) or by establishing SPI
communication (requires RSTB = high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the
device in Normal mode, communication must take place regularly (see Entering and maintaining Normal mode). The device is in Normal
mode (NM) when:
• VPWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• fault = 0.
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27
NXP Semiconductors
6.1.3.1
Channel control in Normal mode
In Direct input mode, the channel’s switching state (On/Off) is controlled by the logic state of the direct input signal with the default values
(00) of turn-on delay and slew rate, specified in Table 5. In internal clock mode, the switching state is controlled by an internal clock signal
(Internal clock and internal PWM (Clock_int_s bit = 1)). Frequency, slew rate, duty cycle, and turn-on delay are programmable
independently for both channels. In external clock mode, the frequency of the external clock controls the output's PWM frequency, but
slew rate, duty cycle, and turn-on delay are still programmable.
6.1.3.2
Factors determining the channel’s switching state
The switching state of a channel is defined by the instantaneous value of the output voltage. It is defined as “On” when the output voltage
V(HS[x]) > VPWR /2 and “Off” when V(HS[x]) < VPWR /2. The channel’s switching state should not be confused with the device’s internal
channel control state hson[x] (= High-side On). Signal hson[x] defines the targeted switching state of the channel (On/Off). It is either
controlled by the value of the direct input signal or by the internal/external clock signals combined with the SPI register settings. The value
of hson[x] is given by the following boolean expression:
hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)].
In this expression Duty_cycle[x] represents the value of the duty cycle, set by bits D7…D0 of the PWMR register (Table 7). The
channel’s actual switching state may differ from the control signal’s state in the following cases:
• short-circuits to GND, before automatic turn-Off (t < tFAULT
)
• short-circuits to VPWR when the channel is set to Off
• VPWR < 13 V when open load in Off-state detection is selected and the load is actually lost
• during the turn-on transition as long as V(HS[x])< VPWR/2
• during the turn-off transition as long as V(HS[x]) > VPWR/2
6.1.3.3
Entering and maintaining Normal mode
A 0-to-1 transition on RSTB, (when both VPWR and VDD are present) or on any of both direct inputs IN[x] (when only supplied by VPWR
)
puts the device in Normal mode. If desired, the device can be operated in Normal mode without VDD, but this requires that at least one of
both direct inputs be regularly turned on (Operation and operating modes). To maintain the device in Normal mode (NM), communication
must take place on a regular basis.
For SPI communication, the state of the WDIN bit must be alternated at least every 310 ms (typ.) (tWDTO), unless the WD_disable bit is
set to 1.
For direct input control, the timing requirements are shown in Figure 11. A signal called IN_ON[x] is not directly accessible to the user but
is used by the internal logic circuitry to determine the device state. When no activity is detected on a direct input pin (IN[x]) for a time longer
than tIN = 250 ms (typ.), timeout is detected and IN_ON[x] goes low. When this occurs on both channels, Sleep mode is entered (Sleep
mode), provided reset = RSTB = 0.
tIN
IN[x]
IN_ON[x]
Figure 11. Relation between signals IN(x) and IN_ON[x]
6.1.3.4
Direct control mode
When RSTB = 0 (and also in Fail-safe mode), the channels are merely controlled by the direct input pins IN[x]. All protective functions (OC,
OT, SC, OV, and UV) are operational including auto-retry. To avoid entering Sleep mode at frequencies < 4.0 Hz, reset should be set to
RSTB = 1.
22XS4200
NXP Semiconductors
28
6.1.3.5
Going from Normal to Fail-safe, Fault or Sleep mode
The device changes from Normal to Fail-safe (Fail-safe mode), Sleep mode (Sleep mode), or Fault mode (Fault mode), according to the
value of the following signals (see Table 6).
• wake-up = RSTB or IN_ON[0] or IN_ON[1]
• fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0)
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis)
Table 6. Device operating modes
Mode
Sleep
Wake-up
Fail-safe Fault
Comments
0
1
1
1
x
0
1
X
x
0
0
1
All channels are OFF
Normal
The SPI Watchdog is active when: VDD = 5.0 V, WD_dis = 0, RSTB = 1
The channels are controlled by the IN inputs (see Fail-safe mode)
The channels are OFF, see Fault mode
Fail-safe
Fault
x = Don’t care.
It enters Fail-safe mode in case of a timeout on SPI communication or when VDD is lost after having been initially present (if this function
was previously enabled by setting: VDD FAIL EN bit = [1]). Setting watchdog disabled (WD_dis = 1, D4 of the GCR register) avoids
_
_
entering Fail-safe mode after watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults (Fault
mode).
(fail-safe = 0) and (wake-up = 1) and (fault = 0)
Sleep
(wake-up = 0)
(wake-up = 1) and
(fail-safe = 1)
and (fault = 0)
(wake-up = 0)
(wake-up = 1)
and (fault = 1)
(wake-up = 0)
(fail-safe = 0) and
(fail-safe = 1) and
(wake-up = 1) and
(wake-up = 1)
(fault = 1)
and (fault = 1)
Fault
Normal
Fail-safe
(fail-safe = 0) and (wake-
up = 1) and (fault = 0)
(fail safe = 1) and
(wake-up = 1) and
(fault = 0)
(fail-safe = 0) and (wake-up = 1) and (fault = 0)
(fail-safe = 1) and (wake-up = 1) and (fault = 0)
Figure 12. Device operating modes
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6.1.4
Sleep mode
In Sleep mode, the channels and the SPI interface are turned off to minimize current consumption. The device enters Sleep mode (wake-
up = 0) when both Direct Input pins IN(x) remain Off longer than tIN sec. (when reset is active; RSTB = 0). This is expressed as follows:
• VPWR (and VDD) are within the normal range, and
• wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1]) and
• fail-safe = X and
• fault = X
When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage
(VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in
their default state during Sleep mode.
6.1.5
Fail-safe mode
6.1.5.1
Entering fail-safe mode
Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD out of range). The
FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational.
Previously latched faults are delatched and SPI register contents is reset (except bits POR & PARALLEL). The SPI registers can not be
accessed. These conditions are also described by the following expressions:
• VPWR is within the normal voltage range, and
• wake-up = 1, fault = 0, and
• fail-safe = 1 ((VDD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0).
The last condition describes the loss of SPI communication which is detailed in the next section.
6.1.5.2
Watchdog on SPI communication and Fail-safe mode
When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of
the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration
tWDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be
disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator.
6.1.5.3
Returning from Fail-safe to Normal mode
To exit Fail-safe mode and return to Normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device
(regardless the register it is contained in and regardless the values of the other bits in this register). Next, a second data word must be
received within the timeout period (tWDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the
FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable
faults that had actually been latched.
6.1.6
Fault mode
The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode:
• Overtemperature fault, (latchable fault)
• Overcurrent fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to VPWR in OFF state (default: disabled)
• Open load fault in OFF state (default: disabled)
• Open load fault in ON state (default: disabled)
• External Clock Failure (default: enabled)
• Overvoltage fault (enabled by default)
• Undervoltage fault, (latchable fault)
The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the
STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read,
even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence results in a turn-off of the incurred channel,
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except for the following faults: open load (On and Off state), External Clock Failure and Output(s) shorted to VPWR. Under and overvoltage
occurrences cause simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults
can be found in Protection and diagnostic features.
Fault mode (Operation and operating modes) is entered when:
• VPWR (+VDD) were within the normal voltage range, and
• wake-up = 1, and
• fail-safe = X, and
• fault = 1 (see Going from Normal to Fail-safe, Fault or Sleep mode)
6.1.6.1
Resetting fault bits
Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register the fault bit is contained
in clears it, provided failure cause disappearance was detected and the fault wasn’t latched.
6.1.6.2
Entering Fault mode from Fail-safe mode
When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode.
However, SPI registers remain reset and can not be accessed. Only the Direct Inputs control the channels.
6.1.6.3
Returning from Fault mode to Fail-safe mode
When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail-safe mode and
behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset.
6.1.7
Latchable faults
An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent
(OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the
FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto-
retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t
latched).
If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the
fault bit remains set. It can then still be reset by reading the SPI register it is contained in.
However, the fault actually gets latched if the failure cause hasn’t disappeared at the first turn-on event following expiration of the available
amount of auto-retries (see Auto-retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be
reset by reading out the associated SPI register prior to performing a delatch sequence (Fault delatching).
6.1.7.1
Fault delatching
To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure
cause. Delatching resets the fault bit of latched faults (see Resetting fault bits). To reset the FSB pin, both channels must be delatched.
Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by
resetting the auto-retry counter (provided retry is enabled). See Reset of the auto-retry counter. Delatching then actually occurs at the
rising edge of the turn-on event.
Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends
on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows:
fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1)
Alternating the fc[x] signal is achieved differently according to the way the user controls the device.
• In direct-input controlled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again
(be switched On). This might happen automatically when operating at frequencies f<4.0 Hz.
• In SPI-controlled mode, the ON_bit state (D8 of the PWMR_s reg.) must be alternated (‘toggled’). No minimum OFF state duration is
required in this case.
Performing a delatch sequence anytime during an ongoing auto-retry sequence (before latching) allows turning the channel on
unconditionally. When a Power-ON event occurs (see Loss of VPWR, loss of VDD, and power-on reset (POR)), latched channels are also
delatched and faults are reset.
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When Fail-safe mode is entered (fault =1, fail-safe becomes 1) during operating in Fault mode (fault=1, fail-safe=0), previously latched
faults are delatched and SPI register content is reset (except bits POR & PARALLEL). The device is then in a combined Fail-safe/Fault
mode. When the device was already in Fail-safe mode (fault = 1, fail-safe =1) and (new) faults occurs, the internal auto-retry counter does
not reset and latched channels are not delatched until a delatching sequence has been performed (see Protection and diagnostic
features).
6.1.8
Programmable PWM module
Each channel has a fully independent PWM module activated by setting PWM_en_s. It modulates an internal or external clock signal.
Setting Clock_int_s = 1 (bit D6 of the OCR_s register) activates the internal clock, and setting Clock_int_s = 0 activates the external clock.
The duty cycle can be set in a range from 0% to 100% with 8 bit-resolution (Table 7) by setting bits D8…D0 of the PWMR_s register
(Table 12). The channel’s switching frequency equals the clock frequency divided by 256 in internal clock mode, and by 256 or 512 in
external clock mode.
External Clock
Frequency Monitoring
CLOCK_fail
PWMR_s register
PWM_en_x
CLOCK_sel_x
VPWR
PR_x
CLOCK
ℜ÷ (1 + PR_x
PWM
Mode
ℜ÷ 25
Internal
Oscillator
HS_x
Driver
Block
CS
Internal Clock
Calibration
HSx
IN_x
Figure 13. Internal and external clock operation
Table 7. PWM duty cycle value assignment
ON-bit
Duty cycle
Channel configuration
0
1
X
OFF
00000000
PWM (duty cycle =1/256)
1
1
1
1
00000001
00000010
n
PWM (duty cycle =2/256)
PWM (duty cycle =3/256)
PWM (duty cycle = (n+1)/256)
fully ON
11111111
By delaying the activation of one channel relative to the other (Table 8), switch-on surges can be delayed, which may improve EMC
performance. Switch-On delay can be selected among seven different values (default=0) by setting bits D2…D0 of the CONFR_s register
(expressed as a number of ext./int. PWM clock periods). To start the PWM function at a known point in time, the PWM_en_s bit (D8 /D7
of the GCR reg.) must be set to 1 after having set the PWMR_s (duty cycle) and CONFR_s (delay) registers. The best way to improve
EMC is to use an external clock with a staggered switch on delay.
Table 8. Switch-on delay in PWM mode
Delay bits
000
Switch-on delay
no delay
001
32 PWM clock periods
64 PWM clock periods
96 PWM clock periods
128 PWM clock periods
160 PWM clock periods
192 PWM clock periods
224 PWM clock periods
010
011
100
101
110
111
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6.1.8.1
External clock and internal PWM (Clock_int_s = 0)
The channels can be controlled by an external clock signal by setting bit D6 =0 of the OCR_s register (Clock_int_s). Duty cycle values
specified in Table 7 apply. When an external clock is used, the value of frequency division (256 when PR[x] = 0) may be doubled by
setting the prescaler bit PR[x]) = 1(bit D7 of the OCR_s reg.). This allows driving the channels at different switching frequencies from a
single clock signal. Simultaneously setting PWM_en_1=1 and PWM_en_0=1 synchronizes the channels.
The clock frequency on the CLOCK pin is monitored when external clock (CLOCK_int_s = 0) and pulse width modulation (PWM_en_s = 1)
are both selected. If a clock failure occurs under these conditions (f< fCLOCK(LOW) or f> fCLOCK(HIGH)), the external clock signal is ignored
and a fault is detected (FSB =0), CLOCK_fail bit is set (OD2 in the DIAGR register). The state of the ON_s bit in the SPI register then
determines the channel’s switching state. To return to external clock mode (and reset FSB), the clock-fail bit must be read and the external
clock has to be within the authorized range again.
6.1.8.2
Internal clock and internal PWM (Clock_int_s bit = 1)
By using a reference time slot (usually available from an external microcontroller), the period of each of the internal PWM clocks can be
changed or calibrated (see Programmable PWM module). Calibration of the default period = 1/fPWM(0) reduces it maximum variation from
about +/-30% to +/-10%. The programming procedure is initialized by sending a dedicated word to the SI-CALR register (see Table 7).
Next, the device sets the new value of the switching period in 2 steps. First it measures the time elapsed between the first falling edge on
the CSB pin and the next rising edge on the CSB pin (tCSB). Then it changes the value of the internal clock period accordingly. The actual
value of the channel’s switching period is obtained by multiplying the internal clock period by 256.
tCSB
CSB
SI
SI command
ignored
CALR_s
tCSB
Internal clock
period of channel s
Figure 14. Internal clock calibration
When the duration of the negative CSB pulse is outside a predefined time slot (from tCSB(MIN) to tCSB(MAX)), the calibration event is ignored
and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level.
6.1.8.3
Synchronization of both channels
When internal clock signals are used to drive the PWM modules, perfect synchronization over a long time can not be achieved since both
clock signals are independent. However, when the channels are driven by an external clock, perfect synchronization can be achieved by
simultaneously setting PWM_en_1=1 and PWM_en_0=1. The best way to optimize EMC is to use an external clock with a staggered
switch on delay (see Table 8).
6.1.9
Parallel operation
The channels can be paralleled to drive higher currents. Setting the PARALLEL bit in the GCR register to logic [1] is mandatory in this
case. The improved synchronization of both transistors allows an equal current distribution between both channels. In Parallel mode, both
output pins (HS[x]) must be connected (as well as both IN[x] pins in case of external control). CONF0 and CONF1 must be set to equal
values.
1- Device configuration in Parallel mode:
There are two ways to configure the On/Off control: SPI-configured PWM control and Direct Input Control.
• SPI configured Parallel mode:
The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as
PARALLEL=1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1
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register (configuration of the open load/Output short-circuited diagnostics). After setting PARALLEL=1, contents of SO registers in bank
0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4 and OD5 of both FAULTR_s registers
(OLON, OLOFF, OS) are always reported independently.
• Direct Input controlled Parallel mode:
The IN0 and IN1 pins must be connected externally.
2- Diagnostics in Parallel mode:
The Diagnostics in Parallel mode operate as follows:
• Open load in OFF state and - open load in ON state:
The OL_ON and OL_OFF bits of both FAULTR registers independently report failures of the channels according to the settings of bits D7
and D6 of the CONFR_s register.
• Current sensing: See Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of
the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register.
• output shorted to battery:
The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg.
3- Protections in Parallel mode:
• Overcurrent:
-Only the configuration of overcurrent thresholds and blanking windows of channel 0 are considered.
-If overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of OC, both OC-bits (OD0)
in the FAULT registers are simultaneously set to logic 1.
• severe short-circuit:
In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously
set to logic 1.
• overtemperature:
In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously
set to logic 1.
• auto-retry:
Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter
value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be
delatched.
6.2
Protection and diagnostic features
Protective functions
6.2.1
6.2.1.1
Overtemperature fault (Latchable fault)
The channels have individual overtemperature detection. As soon as a channel’s junction temperature rises above TSD (175 °C typ.), it is
turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction
temperature of both channels has dropped below the threshold: TJ<TSD. Overtemperature is detected in ON and in OFF state:
• If the channel is ON, the associated output is switched OFF, the OT bit is set, and FSB = 0.
• If the channel is OFF: FSB goes to logic [0] and remain low until the temperature of both channels is below TSD and any of the channels
is turned on again.
The auto-retry function (if activated) automatically turns the channel on when the junction temperature has dropped below TSD. The OT
fault bit can only be reset by reading out the FAULTR register, provided that TJ<TSD and FSB = 1 again.
6.2.1.2
Overcurrent fault (Latchable fault)
When overcurrent (OC) is detected, the channel is immediately turned Off (after tFAULT seconds). The OC-bit is set to 1 and FSB becomes
low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected
overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI
port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and windows
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tOCM_x and tOCH (programmable by SPI bits). The steady-state overcurrent protection level I_OCL is defined by the settings of the OCL
and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked and SYNC becomes 1.
6.2.1.3
Overcurrent duration counter
The load current can spend only a defined amount of time in a particular window of the overcurrent profile. If the time in the window
exceeds the selected window width (tOCx) or the overcurrent threshold is crossed, the channel is turned off (OC fault), followed by auto-
retry (if enabled). An internal overcurrent duration counter is employed for this function.
6.2.1.4
Overcurrent detection on resistive and inductive loads
According to the load type (resistive or inductive), one of two different overcurrent profiles should be selected. This is done by connecting
a resistor with the appropriate value between the CONF[0:1] pins and GND (Table 9).
The overcurrent profile can also be configured through the SPI in the RETRY_s register. If CONF_SPI_s bit is set to 0, the overcurrent
profile is selected on the CONF input pin, otherwise it is the opposite. After device reset, the overcurrent profile is defined by the CONF
input pin. The SPI-SO CONF bit reporting shall combine external hardware configuration and SPI settings.
.
Table 9. Overcurrent profile selection
CONF[0:1] resistor/voltage
Type of load
1.0 kΩ < R(CONF[x]) < 10 kΩ or 0 < V(CONF[X) < VIL (0.8 V)
R(CONF[x]) > 50 kΩ or VIH (2.0 V)< V(CONF) < 5.0 V
resistive: CONF = 0, Lighting-mode
inductive: CONF = 1, DC motor mode
When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. This is illustrated by Figure 15. After
turn on, the output voltage (second waveform) and the output current (first waveform) rise immediately, but the current sense voltage (third
waveform) and its synchronization signal SYNC (fourth waveform) only become active at the end of the selected overcurrent window
(duration tOCM2_L).
Figure 15. Current sense blanking during overcurrent window activity
Activation of the lighting profile is time driven and activation of the DC motor profile is event driven, as explained below.
In lighting mode, the height of the overcurrent profile is defined by three different thresholds (I_OCH, I_OCM and I_OCL, which stand for the
higher, the middle, and the lower overcurrent threshold), as illustrated by Figure 5. This profile has two adjacent windows the width of
which is compatible with typical bulb inrush current profiles. The width of the first of these windows is either tOCH1 or tOCH2. The width of
the second window is either tOCM1_L or tOCM2_L (see Table 18). The lighting profile is activated at each turn-on event including auto-retry,
except in switch mode. In switch mode, the profile is activated only at the first turn-on event, but is not renewed. During the on-period, the
load current is continuously compared to the programmed overcurrent profile. The channel is switched Off when a threshold is crossed
or a window width is exceeded.
In DC motor mode, only one overcurrent window exists, defined by only two different thresholds (I_OCH and I_OCL) as illustrated by
Figure 6. This window is opened anytime the output current exceeds the selected lower overcurrent threshold (IOCLx). In this case, the
allowed overcurrent duration is defined by parameters tOCM1_M, tOCM2_M, tOCH1 and tOCH2. The selection of the different profiles and
values is explained in the section Address A0100— overcurrent protection configuration register (OCR_s).
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6.2.1.5
Auto-retry after overcurrent shut off
When auto-retry is activated, OC-latching (Overcurrent fault (Latchable fault)) only occurs after expiration of the available amount of auto-
retries (described in section Auto-retry).
6.2.1.6
Switch mode operation and overcurrent duration
Switch mode is defined as any device operation with a duty cycle lower than 100% at a frequency above fPWM_EXT (min.) or fPWM_INT
(min.). The device may operate in Switch mode in internal/external PWM or in Direct input mode. In Switch mode, the accumulated time
spent by the load current in a particular window segment during On times of successive switching periods is identified by the
aforementioned duration counter, and compared to the active segment width. The associated off-times are excluded by the duration
counter. The channel is turned-off when the value of the counter exceeds the window width. In Figure 16, overcurrent detection shutdown
is shown in case of switch mode operation with a duty cycle of 50% (solid line) and 100% (fully-on, dashed line). The device is turned off
much later in switch mode than in fully-on mode, since the duration counter only counts overcurrent during on-times.
Figure 16. Overcurrent shutdown in PWM mode (solid line) and fully-on mode (dashed line)
6.2.1.7
Reset of the duration counter
Reset of the duration counter is achieved by performing a delatch sequence (Fault delatching). In lighting mode (CONFs = 0), this counter
is also reset automatically at each auto-retry (but not in DC motor mode).
In DC motor mode, the duration counter is reset by a performing a delatch sequence and automatically after a full on-period without
overcurrent ([hson[x]=1 for any duration). Reset then actually occurs at the first turn-off instant following that on-period. In switch mode,
the duration counter is not reset by normal PWM activity unless delatching is performed.
6.2.1.8
Severe short-circuit fault (Latchable fault)
When a severe short-circuit (SC) is detected at turn-ON (wiring length LLOAD< LSHORT, see Table 4), the channel is shut off immediately.
For wiring lengths above LSHORT, the device is protected from short-circuits by the normal overcurrent protection functions
(Overtemperature fault (Latchable fault)). When an SC occurs, FSB goes low (logic [0]), and the SC bit is set, eventually followed by an
auto-retry. SC is of the latchable fault type (see Protection and diagnostic features and Fault delatching).
6.2.1.9
Overvoltage detection (enabled by default)
By default, the supply overvoltage protection (VPWR) is enabled. When overvoltage occurs (VPWR > VPWR(OV)), the device turns OFF both
channels simultaneously, the FSB pin is asserted low, and the OV fault bit is set to logic [1]. The channels remain OFF until the supply
voltage drops below a threshold voltage VPWR < VPWR(OV) - VPWR(OVHYS). The OV bit can then be reset by reading out the STATR
register.
The overvoltage protection can be disabled by setting the OV_dis = 1 in the general configuration (GCR) register. In this case, the FSB
pin neither asserts a fault occurrence, nor turns off the channels. However, the fault register (OV bit) still reports an overvoltage occurrence
(when VPWR > VPWR(OV)) as a warning. When VPWR > VPWR(OV), the value of the on-resistance on both channels (RDS(on)) still lays within
the ranges specified in Table 4.
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6.2.1.10 Undervoltage fault (Latchable fault)
The channels are always turned off when the supply voltage (VPWR) drops below VPWR(UV). FSB drops to logic [0], and the fault register’s
(common) UV bit is set to [1]. When the undervoltage condition then disappears, two different cases exist:
• If the channel’s internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned
on (warning).
• If the channel’s control signal is on, the channel is turned on if a delatch or POR sequence is performed prior to the turn on request.
The UV bit can then only be reset by reading out the STATR register.
Auto-retry (if enabled) starts as soon as the UV condition disappears.
6.2.1.11 Extended mode protection
In extended mode (6.0 V < VPWR < 8.0 V or 36 V < VPWR < 58 V), the channels are still fault protected, but compliance with the specified
protection levels is not guaranteed. The register settings however (including previously detected faults) remain unaltered, provided VDD
is within the authorized range. Below 6.0 V, the channels are only protected from overtemperature, and this fault is only reported in the
SPI register the moment VPWR has again risen above VPWR(UV). To allow the outputs to remain ON between 36 V and 58 V, overvoltage
detection should be disabled (by setting OV_dis = 1 in the GCR register).
Faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
• VDD < VDD(FAIL) with VPWR in the normal voltage range
• VDD and VPWR are below the VSUPPLY(POR) voltage threshold
• The corresponding SPI register is read after the disappearance of the failure cause (and delatching)
6.2.1.12 Drain/source overvoltage protection
The device tries to limit the Drain-to-Source voltage by turning on the channel whenever VDS exceeds VDS(CLAMP). When a fault occurs
(SC, OC, OT, UV), the device is rapidly switched Off (in t < tFAULT seconds), regardless the value of the selected slew rate. This may
induce voltage surges on VPWR and/or the output pin (HS[x]) when connected to an inductive line/load. Turning on the device also
dissipates the energy stored in the inductive supply line. This function monitors overvoltage for VPWR > 30 V. For supply voltages VPWR
< 30 V, the device is protected from negative output voltages by automatically turning on the channel. The feature remains functional after
device ground loss.
6.2.1.13 Supply overvoltage protection
In order to protect the device from excessive voltages on the supply lines, the voltage between the device’s supply pins (VPWR and the
GND) is monitored. When the VPWR-to-GND voltage exceeds the threshold VD_GND(CLAMP), the channel is automatically turned on. The
feature is not operational in cases of ground loss.
6.2.1.14 Negative output voltage protection
The device tries to limit the undervoltage on the output pins HS[x] when turning off inductive loads. When the output voltage drops below
VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss.
The energy dissipation capabilities of the circuit are defined by the ECL[0:1] parameters. For inductive loads larger than 20 µH, it is
recommended to employ a freewheeling diode. The three different overvoltage protection circuits are symbolically represented in
Figure 17. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the
current in the supply-voltage measurement-diode (zener) and the current injected into the MOSFET’s gate to turn it on.
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.
Figure 17. Supply and output voltage protections
6.2.1.15 Reverse voltage protection on V
PWR
The device can withstand reverse supply voltages on VPWR down to -32 V. Under these conditions, the outputs are automatically turned
On and the channel’s On-resistance (RDS(on)) is similar to that during positive supply voltages. No additional components are required to
protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR, in case they are connected to VPWR.
The VDD pin needs reverse voltage protection from an externally connected diode (Figure 24).
6.2.1.16 Load and system ground loss
In case of load ground loss, the channel’s state does not change, but the device detects an open load fault. In case of a system GND loss,
the channels are turned off.
6.2.1.17 Device ground loss
In the (improbable) case the device loses all of its three ground connections (pins 8, and 28), the channels’ state (On/ Off), depends on
several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device’s
momentary current consumption (influenced by the SPI settings) and the state of other high-side switches on the board when there are
pins in common like FSB, FSOB, and SYNC. In the following description, all voltages are referenced to the system (module) GND.
When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically
when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s)
are tied to VPWR. Fail-safe is entered under the following conditions:
• all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k
• any device pin connected to external system components has a series resistors > 8.0 k (except pins Vpwr, VDD, HS[0], HS[1], and
R(CSNS)>2.0 k)
• the FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means that none of the
other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost
When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage
shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following
list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes logic
low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high
(V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the
channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH.
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6.2.2
Supply voltages out of range
6.2.2.1
V
out of range
DD
If the external VDD supply voltage is lost (or falls outside the authorized range: VDD<VDD(FAIL)), the device enters Fail-safe mode, provided
the VDD_FAIL_en bit had been set. Consequently, the contents of all SPI registers are reset. The channels are controlled by the direct
inputs IN[0:1] (if VPWR is within the normal range). Since the VPWR pin supplies the circuitry of the SPI, current sense and most of the
protective functions (overtemperature, overcurrent, severe short-circuit, short to VPWR, and open load detection circuitry), these faults are
still detected and reported at the FSB pin. However, without VDD, the SO pin is no longer functional. The SPI registers can no longer be
read and detailed fault information is unavailable. Current sensing also becomes unavailable. If VDD_FAIL_EN wasn’t set before VDD was
lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current flows from the VPWR to the VDD pin.
6.2.2.2
V
supply voltage out of range
PWR
If VPWR is below the undervoltage threshold VPWR(UV), it is still possible to address the device by the SPI port, provided VDD is within the
normal range. It does not prevent other devices from operating when a device is part of a daisy-chain. To accomplish this, RSTB must be
kept at logic [1]. When the device operates at supply voltages above the maximum supply voltage (VPWR=36 V), SPI communication is
not affected (see Overvoltage detection (enabled by default)). The internal pull-up and pull-down current sources on the SPI pins are not
operational. Executing a Power-on-Reset (POR) sequence is recommended when VPWR re-enters its authorized range. No current flows
from the VDD to the VPWR pin.
6.2.2.3
Loss of V
, loss of V , and power-on reset (POR)
PWR DD
In typical applications (Figure 24 and Figure 25), an external voltage regulator may be used to derive VDD from VPWR. In wake mode, a
Power-on-Reset (POR) sequence is executed and the POR bit (OD6 of the STATR register) is set when:
• VPWR > VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after)
• VDD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after)
POR is also set at the transition to wake-up (by setting RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR)
(before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently).
(fc[x] = 0)
(Open Load OFF = 1
or OS = 1
or OV = 1)
(Open Load OFF = 1
or OS = 1
or OV = 1)
(fc[x] = 1 and (OV = 0))
(Open Load ON = 1)
OFF
ON
(fc[x]= 0 or OV = 1)
Latched
OFF
(count = 16)
(Retry = 1)
(fc[x] = 0)
Auto-retry Loop
(Open Load ON = 1)
(after Retry Period and OV = 0 and OT = 0 and UV = 0)
(OV = 1)
OFF
ON
(Retry = 1)
= > count = count+1
(Open Load OFF = 1
or OS = 1
or OV = 1
or UV = 1
or OT = 1)
(fc[x] = 0)
Figure 18. State machine: fault occurrence and auto-retry
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6.2.3
Auto-retry
The auto-retry circuitry automatically tries to turn on the channel on a cyclic basis. Only faults of the latchable type (overcurrent, severe
short-circuit, overtemperature (OT), and undervoltage (UV)) may activate auto-retry. For UV and OT faults, auto-retry only starts after
disappearance of the failure cause (when auto-retry is enabled). The retry condition is expressed by:
Retry[x] = OC[x] or SC[x] or OT[x] or UV.
If Auto-retry has been enabled, its mode of operation depends on the settings of the auto-retry related bits (bits D0...D3 of the SI-RETRY_s
register, see Table 12) and the available amount of auto-retries (bits OD7...OD4 of the SO-RETRY_s reg.). More details can be found in
Amount of auto-retries. If Auto-retry is disabled, latchable faults are immediately latched upon their occurrence (see Protection and
diagnostic features).
6.2.3.1
Auto-retry configuration
To enable the auto-retry function, bit retry_s (D0 of the SI RETRY_s register) has to be set to the appropriate value. Auto-retry is enabled
for retry_s = 0 when the channel is configured for lighting applications (CONF=0). It is enabled for retry_s=1 for DC motor applications
(CONF[x] =1).
Table 10. Auto-retry activation for lamps (CONF=0) and DC motors (CONF=1)
CONF[x]
Retry_s bit
auto-retry
enabled
disabled
disabled
enabled
0
0
1
1
0
1
0
1
If auto-retry is enabled, an auto-retry sequence starts when the channel’s fault control signal is set to 1 (fc[x] = 1, see Fault delatching)
and the retry condition applies (Retry[x]=1, see Auto-retry).
When a failure occurs (fault = 1), the channel automatically switches on again after the auto-retry period. The value of this period (tAUTO
)
is set through the SPI port (bits D2 and D3 of the RETRY_s register, see Table 22). When the failure cause disappears before expiration
of the available amount of auto-retries, the device behaves normally (FSB = 1), but the retry counter keeps its current value and the fault
bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection.
6.2.3.2
Amount of auto-retries
In case the device is configured for an unlimited amount of auto-retries (Retry_unlimited_s = 1), auto-retry continues as long as the device
remains powered. The channel never latches off.
In case a limited amount of retries was selected (Retry-unlimited_s = 0), auto-retry continues as long as the value of the 4-bit auto-retry
counter does not exceed 15 (bits OD4...OD7 of the RETRY_s register). After 15 retries, the Rfull bit of the STATR (OD4 for channel 0,
OD5 for channel 1) register is set to a logic high. The amount of available auto-retries is then reduced to one. If the fault still hasn’t
disappeared at the next retry, the corresponding channel is switched off definitively and the fault is latched (FSB = 0, see Protection and
diagnostic features and Fault delatching).
Any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. However, this does not reset
the retry counter. The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4).
6.2.3.3
Reset of the auto-retry counter
Any one of the below events reset the retry counter:
• Fail-safe is entered (Fail-safe mode)
• Sleep mode is left (Sleep mode)
• POR occurs (Supply voltages out of range)
• the retry function is set to unlimited (bit Retry-unlimited_s = 1 (D1 = 1))
• the retry function is disabled (retry_s bit= D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for
CONF = 0).
If the channel is latched the moment the auto-retry counter resets (case 4), the channel is delatched, and turns on after one retry period
(if retry was enabled).
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6.2.3.4
Auto-retry and overcurrent duration
During the on-period following an auto-retry, the load current profile is compared to the length and height of the selected overcurrent
threshold profile, as described in the section on overcurrent protection (See Overcurrent fault (Latchable fault)).
When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents).
For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the duration
counter). Figure 18 gives a description of the retry state machine with the various transitions between operating modes.
6.2.4
Diagnostic features
Diagnostic functions open load-in-On state (OLON), open load-in-Off-state (OLOFF) and output short-circuited to VPWR (OS) are
operational over the frequency and duty cycle ranges specified in Table 5 for PWM mode, but the precise values also depend on the way
the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the open load-in-On-state
detection. As an example, in direct input (DIR_dis_s = 0), Low-current mode (CSR1), OLON, OLOFF and OS detection are performed for
duty cycle values up to: RPWM_400_h = 85% (instead of 90%) when open load in On state detection is enabled (OLON_dis=0).
Occurrence of an OLON, OLOFF or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any
of these diagnostic functions can be disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or OS_dis_s=1 (bits D8...D6 of the CONFR
reg.). The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%).
6.2.4.1
Output shorted-to-V
fault
PWR
The device detects short-circuits between the output and VPWR. The detection is performed during the Off-state. The output-shorted-to-
VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and
saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off.
Even if the short-circuit disappears, the OS_s bit is not cleared until the FAULTR register is read. The function may be disabled by setting
OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features. This type of event shall be limited to
1000 min. during the vehicle lifetime. In case of permanent output shorted to the battery condition, it is needed to turn-on the
corresponding channel.
6.2.4.2
Open load detection in Off state
Open load-in-OFF-state detection (OL_OFF) is performed continuously during each OFF-state (both for CSR0 and CSR1). This function
is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above
V
OLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the open load fault is
detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read
out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges
specified in Diagnostic features.
6.2.4.3
Open load detection in On state (OL_ON)
Open load in ON state detection (OLON) is performed continuously during the On state for CSR0 over the ranges specified in section
Diagnostic features. An open load in On state fault is detected when the load current is lower than the open load current threshold IOLD(ON)
.
This happens at IOLD(ON) = 150 mA (typ.) for high-current sense mode (CSR0), and at 7.0 mA (typ.) for low-current mode. FSB is asserted
low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure
cause is detected, but the OL_ON bit remains set.
In High-current mode (CSR0), open load in On state detection is done continuously during the On state and the OLON-bit remains set
even if the fault disappears.
In high-current mode, the OLON-bit is cleared when the FAULTR register is read during the Off state, even if the fault hasn't disappeared.
The OLON-bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has
disappeared.
In low-current mode (CSR1), OL_ON is done periodically instead of continuously and only operates when fast slew rate is selected. When
the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used
(case 2), the period is that of the input signal. The detection instants in both cases are given by the following:
1. In internal PWM (int./ext. clock), low-current mode (CSR1), open load in ON state detection is not performed each switching
period, but at a fixed frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%.
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OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event
(before OS and OL_OFF).
2. In direct input, low-current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is
restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To
solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel’s direct input must
be disabled by setting Dir_dis_s=1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read
after occurrence of an OL_ON detection event without fault presence.
6.2.4.4
Open load detection in discontinuous conduction mode
If small inductive loads (solenoids / DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired open
load in On state errors may then be detected, as the inductor current needs some time to rise above the open load detection threshold
after turn-on. This problem can be solved by increasing the switching frequency or by disabling the function and activating open load in
Off state detection instead.
When small DC motors are driven in discontinuous conduction mode, undesired open load in Off state detection may also occur when the
load current reaches 0.0 A during the Off state. This problem can be solved by increasing the switching frequency or by enabling open
load in Off state detection only during a limited time, preferably directly after turn-off (see Diagnostic features). The signal on the SYNC
pin can be used to identify the turn-off instant.
6.2.5
Current and temperature sensing
The scaled values of either of the output currents or the temperature of the device’s GND pins (8 and 25) can be made available at the
CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits (see
Table 23) in the General Configuration Register (GCR) must be set to the appropriate values. When overcurrent windows are active,
current sensing is disabled and the SYNCB pin remains high.
6.2.5.1
Instantaneous and sampled current sensing
The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and Track & Hold mode (see
Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output current monitoring (CSNS)) and is
therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In Track & Hold mode however,
the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the
T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1.
6.2.5.2
Current sense ratio selection
The load current is mirrored through the CSNS pin with a sense ratio (Figure 19) selected by the CSNS_ratio bit in the OCR register. To
achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, must be selected. In that case, the
overcurrent threshold levels are decreased. The best accuracy that can be obtained for either ratio is shown in Figure 21. The amount of
current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 Ω < R(CSNS)
<10 kΩ, 1.0 kΩ typical), in order to generate a voltage output. A small low-pass filter can be used for filtering out switching transients
(Figure 24). Current sensing operates for load currents up to the lower overcurrent threshold (OCLx A).
6.2.5.3
Synchronous current sensing mode
For activation of synchronous mode, T_H_en must be set to 0 (default). After turn-on, the CSNS output current accurately reflects the
value of the channel’s load current after the required settling time. From this moment on (CSNS valid), the SYNC pin goes low and remains
low until a switch off signal (internal/external) is received. This allows synchronization of the device’s current sensing feature with an
external process running on a separate device (see Current sense synchronization (SYNC)). After turn-off, the load current does not flow
through the switch, and the load current cannot be monitored.
6.2.5.4
Track & Hold current sensing mode
In Track & Hold mode (T&H) (T_H_en = 1), conversely from synchronous mode, the CSNS output current is available even after having
switched off the load. This feature is useful when the device operates autonomously (internal clock/PWM), since it allows current
monitoring without any synchronization of the device. An external sample and hold (S/H) capacitor is not required. After turn on, the CSNS
output current reflects the channel’s load current with the specified accuracy after occurrence of the negative edge on the SYNC pin, as
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in synchronous mode (see Current sense synchronization (SYNC)). However, at the switch-off instant, the last observed CSNS current is
sampled and its value saved, thanks to an internal S/H capacitor. The SYNC pin goes high (SYNC = 1). If the channel on which Track &
Hold current sensing is performed is changed to another, the internal S/H hold capacitor is first emptied and then charged again to allow
current monitoring of the other channel. Consequently, T&H current monitoring of a channel is lost when this channel is in the Off state at
the moment the current is monitored on the other channel. Track & Hold mode should not be used for frequencies below 60 Hz. When
Track & Hold is used to sense the temperature and then to sense a current, the Track & Hold mode has to be reset by a turn off, then turn
on before sensing a new current.
.
Figure 19. Current sensing ratio versus output current
Figure 20 shows how the limits are constructed in Figure 19. The limits are Six-Sigma with regards to the population. CSR1 limits are
constructed like CSRO.
Figure 20. Current sensing ratio versus output current
6.2.5.5
Current sense errors
Current sense accuracy is adversely affected by errors of the internal circuitry’s current sense ratio and offset. The value of the current
sensing output current can be expressed with sufficient accuracy by the following equation:
ICSNS = (I(HS[x])+ I_LOAD_ERR_SYS + I_LOAD_Err_RAND)*CSRx(1) with CSR0 = (1/1500+εGAIN0) and CSR1 = (1/500+εGAIN1).
The device’s offset error has a “systematic” and a “random” component (I_LOAD_ERR_SYS, I_LOAD_ERR_RAND). At low current levels, the
random offset error may become dominant. The systematic offset error is caused by predictable variations with supply voltage and
temperature, and has a small but positive value with small spread. The random offset error is a randomly distributed parameter with an
average value of zero, but with high spread. The random offset error is subject to part-to-part variations and also depends on the values
of supply voltage and device temperature. The device has a special feature called offset compensation, allowing an almost complete
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compensation of the random offset error (see ESR0_ERR). This offset compensation technique greatly minimizes this error. Computing the
compensated current sensing value is illustrated in the next sections.
6.2.5.6
Activation and use of offset compensation
According to the settings of the OFP_s bit (in the RETRYR_s register), opposite values of the random offset error are generated. To
compensate the random offset error, two separate measurements with opposite values of the random offset error are required. The
measured values must be saved by an external µ-processor. Compensation of the random offset error is achieved by computing the
average of both. When a dedicated bit called Offset Positive (OFP = bit D8 of the RETRYR_s register) is set to 1, the current sunk through
the CSNS pin (ICSNS) can be described by:
ICSNS1=CSRx *(ILOAD+ I_LOAD_ERR_SYS+ I_LOAD_ERR_RAND
)
(2)
When bit OFP is set to 0, ICSNS can be described by:
ICSNS2 = CSRx *(ILOAD+ I_LOAD_ERR_SYS - I_LOAD_ERR_RAND) (3)
The random offset term I_LOAD_ERR_RAND can be computed from equations (2) and (3) as follows:
I_LOAD_ERR_RAND = (ICSNS1 - ICSNS2) / (2*CSRx)
(4)
The compensated current sense value ICSNS,COMP can be obtained by computing the average value of measurements ICSNS1 and ICSNS2
as follows:
ICSNS,COMP = (ICSNS1 + ICSNS2) / 2
(5)
When equations 2 and 3 are substituted in equation 5, the random offset error cancels out, as shows eq. 6:
ICSNS,COMP = (I_LOAD_ERR_SYS + ILOAD
)
* CSRx
(6)
The systematic offset error I_LOAD_ERR_SYS is referenced at the operating point 28 V and 25 °C. It can eventually be fine tuned by
performing a calibration. Gain errors at 25 °C (=current sense ratio errors, represented by εGAIN0 and εGain1) can also be reduced by
performing a calibration at a point in the range of interest. If calibration can not be done, it is recommended to use the typical value of
I_LOAD_ERR_SYS (see ESR0_ERR).
6.2.5.7
Current sense error model
The figures of uncompensated and compensated current sense accuracy mentioned in Table 4 have been obtained applying the error
model of eq. 7 to the data:
ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx
(7)
(8)
ESRx_ERR = (ICSNS1 - ICSNS_MODEL)/ICSNS_MODEL
ESRx_ERR(COMP)= (ICSNS,COMP - ICSNS_MODEL)/ICSNS_MODEL (9)
The computation has been applied to each of the specified measurement points. Model parameters I_LOAD_ERR_SYS and CSRx have the
nominal values, specified in ESR0_ERR
.
The load current can be computed from this model as:
I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
I(HS[x]) = ICSNS,COMP / CSRx - I_LOAD_ERR_SYS
(10)
(11)
Using expression (11) generally gives more accurate values than expression (10), since in expression (11), random offset errors have
been compensated.
6.2.5.8
Offset compensation in Track & Hold mode
In Track & Hold mode, the last observed sense current (ICSNS) is sampled at the switch off instant. This takes into account the currently
active settings of the OFP_s offset compensation bit. Changing the value of the OFP bit during the switch’s off time produces an identical
value of the current sense output. Consequently, to implement the before mentioned offset compensation technique, the channel must
have been turned on at least once prior to sensing the output current with an opposite value of the OFP bit.
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6.2.5.9
System requirements for current monitoring
Current monitoring is usually implemented by reading the (RC-filtered) voltage across the pull-down resistor connected between the
CSNS pin and GND (Figure 24). Therefore, measurements (1) and (2) must be spaced sufficiently wide apart (e.g. 5 time constants) to
get stabilized values, but close enough to be sure that the offset value wasn’t changed. The A/D converter of the external micro controller
that is used to read the current sense voltage V(csns) must have sufficient resolution to avoid introducing additional errors.
6.2.5.10 Accuracy with and without offset compensation
The sensing accuracy for CSR0 and CSR1, obtained before and after offset compensation, is shown in Figure 21 (solid lines = full scale
accuracy with offset compensation and dotted lines without offset compensation).
.
Notes
43. Accuracy ranges are six-sigma constructed.
Figure 21. Current sense accuracy versus output current
In Track & Hold mode, the accuracy of the current sense function is lowered according to the values shown in Figure 22 (error percentage
as a function of the switch-off time is displayed, for CSR0 and CSR1). Track & Hold mode should not be used below f = 60 Hz.
Figure 22. Track & Hold current sense accuracy
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6.2.5.11 Temperature prewarning detection
In Normal mode, the temperature prewarning (OTW) bit is set (bit OD8 of the FAULTR register) when the observed temperature of the
GND pin is higher than TOTWAR (pin #14, see Figure 3). The feature is useful when the temperature of the direct surroundings of the device
must be monitored. However, the channel isn’t switched off. To be able to reset the OTW-bit, the FAULTR register must be read after the
moment that temperature T °C < TOTWAR
.
6.2.5.12 Switching state monitoring
The switching state (On/Off) of the channels is reported in real time by bits OUT[x] in the STATR register (bit OD0/OD1). The Out[x] bit is
asserted logic high when the channel is on (output voltage V(HS[x]) higher than VPWR /2). When supply voltage VPWR drops below 13 V,
the reported channel state may not correspond to the state of the channel’s control signal hson[x] in case of an open load fault (see Factors
determining the channel’s switching state).
6.2.6
EMC performances
Specified EMC performance is board and module dependent and applies to a typical application (Figure 24). The device withstands
transients per ISO 7637-2 /24 V. The device meets CISPR-25 Class5 from 1.0 MHz to 1.0 GHz peak. See application AN5000 for EMC
result details.
6.3
Logic commands and SPI registers
SPI protocol description
6.3.1
The SPI interface offers full duplex, synchronous data transfer over four I/O lines: Serial Input (SI), Serial Output (SO), Serial Clock
(SCLK), and Chip Select (CSB).The SI/SO pins of the device follow a first-in first-out (D15 to D0) protocol. Transfer of input and output
words starts with the most significant bit (MSB). All inputs are compatible with 5.0 or 3.3 V CMOS logic levels. Parity check is performed
after transfer of each 16-bit SPI data word.The SPI interface can be driven without series resistors provided that voltage ratings on the
VDD and SPI pins (Table 3) aren’t exceeded. Unused SPI pins must be tied to GND, eventually by resistors (see Device ground loss).
CSB
SCLK
SI
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RSTB must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).
Figure 23. 16-bit SPI interface timing diagram
6.3.2
Serial input communication protocol
SPI communication requires that RSTB = high. SPI communication is accomplished with 16-bit messages. A valid message must start
with the MSB (D15) and end with the LSB (D0) (Table 11). Incoming messages are interpreted according to Table 12. The MSB, D15, is
the watchdog bit (WDIN). Bit D14, Parity check (P), must be set such that the total number of 1-bits in the SPI word is even (P=0 for an
even number of 1-bits and P=1 for an odd number). Bank selection is done by setting bit D13. Bits D12:D10 are used for register
addressing. The remaining ten bits, D9:D0, are used to configure the device and activate diagnostic and protective functions. Multiple
messages can be transmitted for applications with daisy chaining (or to validate already transmitted data) by keeping the CSB pin at logic
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46
0. Messages with a length different from a multiple of 16 or with a parity error is ignored. The device has thirteen input registers for device
configuration and thirteen output registers containing the fault/device status and settings. Table 12 gives the SI register function
assignment. Bit names with extension “_s” refer to functions that have been implemented independently for each of both channels.
6.3.3
Serial port operation
When Chip Select occurs (1-to-0 transition on the CSB pin), the output register data is clocked out of the SO pin (MSB-first) at the serial
clock frequency (SLCK). Bits at the SI pin are clocked in at the same time. The first sixteen SO register bits are those addressed by the
previous SI word (bit D13, D2…D0 of the STATR_s input register). At the end of the chip select event (0-to-1 transition), the SI register
contents are latched. The second SPI word clocked out of the Serial Output (SO) after the first CSB event represents the initial SO register
contents. This allows daisy chaining and data integrity verification.
The message length is validated at the end of the CSB event (0-to-1 transition). If it is valid (multiples of 16, no parity error), the data is
latched into the selected register. After latch-in, the SO pin is tri-stated and the status register is updated with the latest fault status
information.
6.3.3.1
Daisy chain operation
Daisy-chaining propagates commands through devices connected in series. The commands enter the device at the SI pin and leave it by
the SO pin, delayed by one command cycle of 16 bits. To address a particular device in a daisy chain, the CSB pin of all the devices in
that chain has to be kept low until the SPI message has arrived at its destination. Once the command has been clocked in by the
addressed device, it can be executed by setting CSB=1.
Table 11. SI message bit assignment
Bit n°
SI reg. bit
D15
Bit functional description
Watchdog in (WDIN): Its state must be alternated at least once within the timeout period
Parity (P) check. P-bit must be set to 0 for an even number of 1-bits and to 1 for an odd number.
Selection between SI registers from bank 0 (0= channel 0) and bank 1 (Table 14)
Register address bits
MSB
.
.
.
.
D14
D13
D12:D10
D9:D0
LSB
Used to configure the device and the protective functions and to address the SO registers
Table 12. Serial input register addresses and function assignment
SI data
SI
D
D
D
D
D
register
D 15
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
14 13 12 11 10
STATR_s WDIN
PWMR_s WDIN
P
P
A
0
0
0
0
0
1
0
0
0
0
0
0
0
0
SOA2
SOA1
SOA0
0
0
A
ON_s
PWM7_s
PWM6_s
PWM5_s
PWM4_s
PWM3_s
PWM2_s
PWM1_s
PWM0_s
OLON_dis_ OLOFF_dis_
CONFR_s WDIN
P
P
P
A
A
A
0
1
1
1
0
0
0
0
1
0
0
0
OS_dis_s
HOCR_s
OFP_s
DIR_dis_s
SR1_s
SR0_s
DELAY2_s
OCH_s
DELAY1_s DELAY0_s
0
0
0
s
s
CSNS_ratio
_s
OCR_s
WDIN
PR_s
Clock_int_s
t
tOCM_s
OCM_s
OCL_s
retry_s
OCH_s
CONF_S Auto_period1 Auto_period0 Retry_unlim
PI_s
RETRY_s WDIN
0
0
0
_s
_s
ited_s
PWM_en_
1
GCR
WDIN
P
P
X
0
1
1
X
1
1
X
0
1
0
0
0
PWM_en_0 PARALLEL
T_H_en
WD_dis
V
CSNS1_en CSNS0_en
OV_dis
DD_FAIL_en
1
CALR_s WDIN
A
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
contents
0
0
X
0**
0
after reset*
* = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V or POR
** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before
X = register address, P = parity bit
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NXP Semiconductors
Table 13. Serial output register bit assignment
bits D13, D2,
D1, D0 of the
previous
SO returned data
STATR
S
O
A
3
S
O
A
2
S
O
A
1
S
O
A
0
OD OD OD OD OD OD
15 14 13 12 11 10 D9
O
OD8 OD7 OD6
OD5
OD4
OD3
OD2
OD1
OD0
WDI
N
SOA SOA SOA SOA
R_FUL R_FULL
STATR
0
0
0
0
0
0
1
0
1
0
PF
PF
PF
NM OV
NM OTW
NM ON_s
UV
0
POR
0
FAULT1
OS_s
FAULT0
OT_s
OUT1
SC_s
OUT0
OC_s
3
2
1
0
L1
0
FAULTR
_s
WDI
N
SOA SOA SOA SOA
OLON_ OLOFF
_s
A
A
0
0
3
2
1
0
s
PWMR_
s
WDI
N
SOA SOA SOA SOA
PWM PWM6_ PWM5_ PWM4_
PWM3_s
PWM2_s
PWM1_s
PWM0_s
3
2
1
0
7_s
s
s
s
OLO
N_dis
_s
CONFR
_s
WDI
N
SOA SOA SOA SOA
OS_d
NM
OLOFF DIR_dis
_dis_s _s
A
0
1
1
PF
SR1_s
SR0_s
DELAY2_s
OCH_s
DELAY1_s DELAY0_s
0
3
2
1
0
is_s
WDI
N
SOA SOA SOA SOA
HOC
NM
Clock_i CSNS_r
OCR_s
A
A
1
1
0
0
0
1
PF
PF
PR_s
R3
tOCH_s
R0
tOCM_s
OCM_s
OCL_s
retry_s
0
0
3
2
1
0
R_s
nt_s
atio_s
RETRY
R_s
WDI
N
SOA SOA SOA SOA
Auto_period1 Auto_period0_ Retry_unli
NM OFP
R2
R1
3
2
1
0
_s
s
mited_s
PWM PWM
NM _en_ _en_
WDI
N
SOA SOA SOA SOA
PARAL
LLEL
GCR
0
1
1
1
1
0
1
PF
PF
T_H_en WD_dis VDD_Fail_en
CSNS1_en
CSNS0_en
OV_dis
3
2
1
0
1
0
WDI
N
SOA SOA SOA SOA
CON CON
DIAGR
0
NM
0
ID1
0**
ID0
IN1
0
IN0
0
CLOCK_fail
0
CAL_fail1 CAL_fail0
3
2
1
0
F1
F0
contents
after
reset or
failure*
N/ N/ N/ N/
A
0
0
0
0
0
0
0
0
0***
0
0
A
A
A
* = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V, or POR
** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs provided VDD = 5.0 V and VDD_Fail_en = 1 before
*** = except bit D7 (POR) of the STATR register that is saved when VDD(FAIL) occurs after VDD = 5.0 V and VDD_Fail_en = 1 (fail-safe mode)
x = register address, PF = parity Fault
6.3.4
SI register addressing
The address in the title of the following sections (A0xxx) refer to bits D[13:10] of the SPI word required to address the associated SI
register. Bit A0 = D13 selects between registers of bank 0 and bank 1 (Table 14). The function assignment of register bits D[8:0] is
described in the associated section. The “_s” behind a register name indicates that the variable applies to the register contents of both
banks.
Table 14. Value of bit A0 required for addressing register banks 0 or 1
Value A0 (D13)
Bank
0
1
0 = channel 0 (default)
1 = channel 1
6.3.5
Address A0000—status register (STATR_s)
To read back the contents of any of the 13 SO registers, bits D[13:10] of the channel’s SI STATR register must be set to A0000 and bits
D[2:0] in the same SPI word to the address of the desired SO register. The SO registers thus addressed are: STATR, FAULTR_s,
PWMR_s, CONFR_s, OCR_s, RETRY_s, GCR, and DIAGR (Table 13).
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6.3.6
Address A0001— PWM control register (PWMR_s)
The PWMR_s register contents determines the value of the PWM duty cycle at the output (Table 12), both for internal and external clock
signals.
Bit D8 must be set to 1 to activate this function. The desired value of duty cycle is obtained by setting Bits D7:D0 to one of the 256 levels
as shown in Table 7. To start the PWM function at a known point in time, the PWM_en_s bit (both in the GCR register) must be set to 1.
6.3.7
Address A0010—channel configuration register (CONFR_s)
The CONFR_s is used to select the appropriate value of slew rate and turn-ON delay. The settings of Bits D[8:6] determine the activation
of open load and short-circuit (to VPWR) detection. Bit D13 ( = A0) of the incoming SPI word determines which of both CONFR registers
is addressed (Table 14).
Setting bit D8 (OS_dis_s) to logic [1] disables detection of short-circuits between the channel’s output pin and the VPWR pin. The default
value [0] enables the feature.
Setting bit D7 (OLON_dis_s) to logic [1] disables detection of open load in the On state for the selected channel. The default value [0]
enables this feature (Table 15).
Setting bit D6 (OLOFF_dis_s) to logic [1] disables detection of open load in the OFF state. The default value [0] enables the feature, see
Table 15.
Table 15. Selection of open load detection features
OLON_dis_s
(D7: On state)
OLOFF_dis_s
(D6: Off state)
Selected open load detection function
0
0
1
1
0
1
0
1
both enabled (default)
Off state detection disabled
On state detection disabled
Both disabled
Setting bit D5 (DIR_DIS_s) to logic [0] enables direct control of the selected channel. Setting bit D5 to logic [1] disables direct control. In
that case, the channel state is determined by the settings of the internal PWM functions.
D4:D3 bits (SR1_s and SR0_s) control the slew rate at turn on and turn off (Table 16). The default value ([00]) corresponds to the medium
slew rate. Rising and falling edge slew rates are identical.
Table 16. Slew rate selection
SR1_s (D4)
SR0_s (D3)
Slew rate
medium (default)
low
0
0
1
1
0
1
0
1
high
medium SR <SR< high SR
Delaying a channel’s turn-On instant with respect to the other is accomplished by setting bits D2:D0 of the PWMR_s register to the
appropriate values. Switch On is delayed by the number of (internal/external) clock periods shown in Table 8. See section Programmable
PWM module.
6.3.8
Address A0100— overcurrent protection configuration register (OCR_s)
The contents of the OCR_s registers determines operation of overcurrent, current sensing, and PWM related functions. For each load
type (bulb or DC motor), a different kind of overcurrent profile exists (see Overcurrent protection profile for bulb applications). For lighting
mode, the overcurrent profile is defined by three different thresholds each of which is active over a dedicated time slot. These thresholds
are called the higher (=I_OCH), the middle (=I_OCM) and the lower (=I_OCL) threshold. The DC motor profile only has two thresholds (I_OCH
and I_OCL).
Each threshold can be set to two different values, except I_OCL that can be set to three different values (I_OCL1, I_OCL2, I_OCL3). Setting
the low-current sense ratio (CSR1) reduces the values of all the overcurrent thresholds by a factor of three. The terminology is defined as
follows: I_OCxy_z stands for overcurrent threshold x (x=I_OCH, I_OCM or I_OCL) that can be set to two or three different values, selected by
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NXP Semiconductors
y (y=1, 2, (or 3)). The previously selected current sense ratio (z=0 for CSR0 and z=1 for CSR1) further determines the shape of the
applicable overcurrent protection profile (see I_OCH1_0).
Setting bit D8 (HOCR_s) to 0 activates overcurrent level I_OCL1, the highest of the 3 levels, regardless the value of the D0 bit. Setting
HOCR to 1 activates the medium level I_OCL2 when D0 = 0, and the lowest level I_OCL3 when D0 = 1 (Table 21). When overcurrent
windows are active, current sensing is not available.
Bit D7 (PR_s) controls which of two divider values are used to create the PWM frequency from the external clock. Setting bit D7 to 1
causes the external clock to be divided by 512. When PR_s = 0, the divider is 256.
Setting bit D6 (Clock_int_s) activates the internal clock of the selected channel. The default value [0] configures the PWM module to use
an external clock signal.
Setting bit D5 (CSNS_ratio_s) to 1 activates the “low- current” current sense ratio CSR1, optimal for measuring currents in the lowest
range. The default value [0] activates the “high-current” sensing ratio CSR0 (Table 17).
Table 17. Current sense ratio selection
CSNS_ratio_s (D5)
Current sense ratio
CRS0 (default)
CRS1
0
1
The width of the overcurrent protection window(s) is controlled by bits D4 and D3 (tOCH_s and tOCM_s), and also depends on the load type
configuration as shown in Table 18. (CONF[x]=0: bulb, CONF[x]=1: DC motor).
The lighting profile has two adjacent windows the width of which is compatible with typical bulb inrush current profiles. The width of the
first of these windows is either tOCH1 or tOCH2. The width of the second window is either tOCM1_L or tOCM2_L (see Table 18).
The DC motor profile has one overcurrent window defined by two different thresholds (I_OCH and I_OCL), as illustrated by Figure 6. In this
case, the maximum overcurrent duration is selected among four values: tOCM1_M, tOCM2_M, tOCH1 and tOCH2
.
Table 18. Dynamic overcurrent threshold activation times for bulb and DC motor profiles
CONF[x]
tOCH_s (D4)
tOCM_s (D3)
Selected threshold activation times
tOCH1 and tOCM1_L
tOCH1 and tOCM2_L
tOCH2 and tOCM1_L
tOCH2 and tOCM2_L
tOCM1_M
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tOCM2_M
tOCH1
tOCH2
Bit D2 (OCH_s) selects the value of the higher (upper) overcurrent threshold among two values. The default value [0] corresponds to the
highest value, and [1] to the lowest value (Table 19).
Table 19. OCH upper current threshold selection
OCH_s (D2)
I_OCH Current Threshold
I_OCH1_s (default)
I_OCH2_s
0
1
Bit D1 (OCM_s) sets the value of the middle overcurrent threshold. The default value [0] corresponds to the highest value, and [1] to the
lowest value (Table 20). In DC motor mode, there is no middle overcurrent threshold and the value of this bit has no influence.
Table 20. OCM current threshold selection
OCM_s (D1)
OCM current threshold
I_OCM1_s (default)
I_OCM2_s
0
1
Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest overcurrent threshold, as shown in Table 21.
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50
Table 21. OCL current threshold selection
HOCR (D8)
OCL_s (bit D0)
Selected OCL current level
I_OCL1_x(default)
I_OCL1_x
0
0
1
1
0
1
0
1
I_OCL2_x
I_OCL3_x
6.3.9
Address A0101— Auto-retry register (RETRYR_s)
The RETRYR_s register contents are used to set the different auto-retry options (Auto-retry), the offset compensation feature of the
current sense function, and the overcurrent profile.
Setting bit D8 to 1(OFP = 1) causes the random offset current to be added to the sensed current (pin CSNS). Setting bit D8 to 0 results
in the offset current being subtracted from the sensed current. Setting D3 and D2 (Table 22) to the appropriate values allows selection of
the value of the auto-retry period among four predefined values.
Table 22. Auto-retry period
Auto_period1_s (D3)
Auto_period0_s (D2)
Retry period
tAUTO_00 (default)
tAUTO_01
0
0
1
1
0
1
0
1
tAUTO_10
tAUTO_11
Setting bit D1 to 1 (RETRY_unlimited_s = 1) results in an unlimited number of auto retries, provided the auto-retry function wasn’t
disabled.
Setting bit D1 to 0 (RETRY_unlimited_s = 0) limits the amount of auto retries to 16 (see Amount of auto-retries). The value of the counter
neither resets after delatching, nor when the fault disappears.
Setting bit D0 (retry_s) enables or disable auto-retry, accordingly to setting of the CONF pin.
For CONF[x] = 0 (Lighting profile configured), setting retry_s = 1 disables auto-retry. The default value [0] enables it.
For CONF[x] = 1 (DC motor), setting retry_s = 1 enables auto-retry. The default value [0] disables it.
Setting bit D4 to 0 (CONF_SPI_s = 0) will configure the overcurrent profile as the CONF pin.
Setting bit D4 to 1 (CONF_SPI_s = 1) will configure the overcurrent profile as the opposite of the CONF pin.
6.3.10 Address 0110—global configuration register (GCR)
The GCR register is used to activate various functions and diagnostic functions.
Setting bits D8 = 1 and D7 = 1 of the GCR register (PWM_en_1 and PWM_en_0) activates the internal PWM function of both channels
simultaneously according to the values of duty cycle and turn-on delays in the PWMR_s and CONFR_s registers (Table 7). However, this
option should never be used to drive channels in parallel. To increase the load current capability, the instructions in the section Parallel
operation should be followed.
Setting bit D6 sets Parallel mode (improved switching synchronization between both channels). Only configuration and diagnostic
information of bank 0 (A0 = 0) is available in this setting (see Parallel operation).
Setting Bit D5 (T_H_en = 1) activates Track & Hold current sensing mode. When T&H is activated, the value of the channel’s load current
is kept available after turn-off.
Setting bit D4 (WD_dis = 1) disables the SPI watchdog function. A logic [0] enables the SPI watchdog.
Setting bit D3 (VDD_FAIL_EN = 1) enables or disable the VDD failure detection. When enabled, the device enters Fail-safe mode after VDD
< VDD(FAIL).
Bits D6 (parallel bit), D2 and D1 set the different (current) sensing options. The CSNS pin outputs a scaled value of the selected channel’s
load current, the sum of both currents or the die temperature, according to the values in Table 23. When the highest overcurrent range is
selected (bit D8 of the OCR register, HOCR = 0), the device’s CSNS pin only outputs scaled values of a single channel’s load current.
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NXP Semiconductors
Table 23. Current sense pin functionality selection
D8
x
D6
x
D2
0
D1
0
Activated function at CSNS pin
disabled
0
x
0
1
current sensing on channel 0
current sensing on channel 1
temperature sensing
0
x
1
0
0
x
1
1
1
0
x
0
1
current sensing on channel 0
current sensing on channel 1
temperature
1
1
0
1
x
1
1
1
1
0
1
current sensing summed currents of channels 0 and 1
Setting bit D0 (OV_dis = 1 of the GCR reg.) disables overvoltage protection. Setting this bit to [0] (default), enables it.
6.3.11 Address A0111—Calibration register (CALR_s)
The internal clock frequency of both channels can be calibrated independently. Setting the appropriate calibration word in the CALR_s
register (Table 12) puts the device in calibration mode. The default switching frequency is 400 Hz, but can be changed by applying a
specific calibration procedure. See Internal clock and internal PWM (Clock_int_s bit = 1).
6.3.12 SO register addressing
The device has two register banks, each of which has five channel-specific SO registers containing the channel’s configuration and
diagnostics status (Table 13). These registers are FAULTR_s, PWMR_s, CONFR_s, OCR_s, and RETRYR_s.
Global fault and diagnostic information are contained in the following common SO-registers: STATR, GCR, and DIAGR. All the SO
registers can be addressed by setting the appropriate bits in the SI-STATR_s register (bits D13, D2, D1, D0). The value of the bit D13
determines which register bank is addressed (bank 0 or 1). Data is made available the next cycle after register addressing. The output
status register correctly reflects the contents of the addressed SO register as long as CSB is low, except when the data from the previous
SPI cycle was invalid. In this case, the device outputs the contents of the last successfully addressed SO register.
6.3.13 Serial output register assignment
The output register shifted out through the SO pin is previously addressed by bits D13, D2, D1, and D0 of the STATR_s SI register.
Table 13 gives the functional assignment (OD15:OD0) of each of the thirteen SO register bits, preceded by the address of the SI
STATR_s required to address it.
• Bit OD15 (MSB) reports the state of the watchdog bit from the previously clocked-in SPI message.
• Bit OD14 (PF, active 1) reports an eventual parity error on the previously transferred SI register contents.
• Bits OD13:OD10 echo the state of bits D13, D2, D1, and D0 (SOA3:SOA0) of the previously received SI word.
• Bit OD9: Normal mode (NM) reports the device state. In Normal Mode, NM = 1.
• Bits OD8:OD0 are the contents of the selected SO register (addressed by bit D13 and bits D2:D0 of the previous SI STATR register).
6.3.14 Previous address SOA3:SOA0 = 0000 (STATR)
When bits SOA3…SOA0 of the previously received SI STATR_s register = 0000, the SO STATR register is addressed. Bits OD8:OD0
contain the relevant channel information: Faults, channel state, and supply voltage errors.
• Bits OD8:OD6 report failures common to both channels
• Bit OD8 = OV = 1: overvoltage fault
• Bit OD7 = UV = 1: undervoltage fault
• Bit OD6 = POR = 1: power-on reset (POR) has occurred
Power-ON-Reset occurs when VPWR<VSUPPLY(POR). The OV, UV, and POR bits can be reset by a reading the STATR register. Bits
OD5:OD4 (RFULL) of the STATR register are set to logic [1] when the auto-retry counter of the corresponding channel is full. These bits
are automatically cleared by resetting the corresponding auto-retry counter (see Reset of the auto-retry counter). Bits OD3 (FAULT1) and
OD2 (FAULT0) are set to logic [1] when channel-specific (non-generic) faults are detected:
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52
FAULTs = OC_s + SC_s + OT_s + OS_s + OLOFF_s + OLON_s.
The FAULTs bit can be reset by reading out the common STATR register or the individual FAULTR_s register (provided the fault has
disappeared).
Bits OD1:OD0 (OUT1 and OUT0) report the channel’s switching state (On/Off) in real time.
6.3.15 Previous address SOA3:SOA0 = A0001 (FAULTR_s)
Bit OD8 of both Fault registers (FAULTR_s) is set simultaneously when the overtemperature prewarning (OTW) condition occurs, but the
channels are not switched off (temperature of the common GND pins (8 and 25)> TOTWAR). Reading either FAULT register clears both
OTW bits.
Bits OD5:OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0
(Table 14).
• bit OD0 = OC_s: overcurrent fault on channel s,
• bit OD1 = SC_s: severe short-circuit on channel s,
• bit OD3 = OS_s: output shorted to VPWR on channel s,
• bit OD4 = OLOFF_s: open load in OFF state on channel s,
• bit OD5 = OLON_s: open load in ON state on channel s. (The threshold value above which this fault is triggered depends on the
selected current sense ratio; for CSR0 at 150 mA typ. and for CSR1 at 7.0 mA typ.).
The Fault Status pin (FSB) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be
delatched by the procedure described in Fault delatching. The FAULTR_s register is reset when it is read out, provided that the failure
cause has disappeared and latched faults have been delatched.
6.3.16 Previous address SOA3:SOA0 = A0010 (PWMR_s)
The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
6.3.17 Previous address SOA3:SOA0 = A0011 (CONFR_s)
The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
6.3.18 Previous address SOA3:SOA0 = A0100 (OCR_s)
The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).
6.3.19 Previous address SOA3:SOA0 = A0101 (RETRYR_s)
The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the
value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7:OD4 contain the real time value of the auto-
retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur.
6.3.20 Previous address SOA3:SOA0 = 0110 (GCR)
The device outputs the contents of the general configuration register (GCR) common to both channels.
6.3.21 Previous address SOA3:SOA0 = 0111 (DIAGR_s)
Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels’ configuration bits
(0 = bulb, 1 = DC motor)
Bits OD6:OD5 contain the product identification (ID) number, equal to 00 for the present dual 22 mΩ product.
Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0.
Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0)
Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel’s internal clock period.
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Typical applications
Figure 24 shows the electrical circuit of a typical truck application. As an example, an external circuit is added that takes over load control
in case Fail-safe mode is activated (FSOB goes low). This circuit allows keeping full control of both channels in case of SPI failure.
VPWR
VDD
Voltage regulator
10 µF
100 nF
10 µF
100 nF
VPWR
VDD
VPWR
VDD
22XS4200
VDD
VPWR
VDD
100 k
10 k
100 nF
100 nF
1.0 µF
VDD
I/O
I/O
CLOCK
FSB
IN0
HS0
IN1
22 nF
FSOB
MCU
SCLK
CSB
I/O
SCLK
CSB
RSTB
SI
LOAD 0
HS1
SO
SI
SO
CONF0
CONF1
M
8.0 k2
22 nF
75 k
LOAD 1
SYNC
CSNS
I/O
A/D
GND
GND
1.0 k2
2.0 k
22 nF
10 k
10 k
VPWR
External Control Circuitry
direct controls (pedals, handles, etc.)
Figure 24. Typical application with two different load types
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.
VPWR
VDD
Voltage regulator
10 µF
100 nF
10 µF
100 nF
VPWR
VDD
VPWR
VDD
22XS4200
VDD
VPWR
VDD
100 k
10 k
100 nF
1.0 µF
100 nF
VDD
I/O
I/O
CLOCK
FSB
IN0
IN1
HS0
HS1
M
22 nF
MCU
FSOB
SCLK
CSB
I/O
SCLK
CSB
RSTB
SI
LOAD
SO
SI
SO
CONF0
CONF1
75 k
75 k
I/O
SYNC
CSNS
A/D
GND
GND
1.0 k2
22 nF
2.0 k
10 k
VPWR
External Control Circuitry
direct controls (pedals, handles,...)
Figure 25. Two channels in parallel / recommended external current sense circuit
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Packaging
8.1
Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
Package outline drawing number
BEK
98ASA00368D
32 Pin SOIC-EP
CEK
98ASA00894D
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59
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9
Revision history
Revision
Date
Description of changes
1.0
3/2014
•
•
•
•
•
Initial release
Updated turn-on and turn-off delay time
Updated overcurrent detection thresholds
Updated output current sensing error
Thermal parameter update per PB#16607
2.0
9/2014
1/2015
8/2016
3.0
•
Updated to NXP document form and style
Updated as per CIN 201805020I
Changed steady-state current value from 3.0 to 4.2 A listed under features on page 1
Updated IHS[0:1] value in Table 3 (changed 3.0 to 4.2)
•
•
•
•
•
•
•
•
Added clarification for diagnostic range to Table 5
Corrected typo in Reverse voltage protection on VPWR (changed -28 V to -32 V)
Updated load dump duration (changed 500 ms to 350 ms) and changed VPWR from 14 V to 28 V in Table 3
Updated Track & Hold current sensing mode
Changed “Bits OD6:OD5 contain the product identification (ID) number, equal to 01 for the present dual 22 mΩ
product” to “Bits OD6:OD5 contain the product identification (ID) number, equal to 00 for the present dual 22 mΩ
product” in Previous address SOA3:SOA0 = 0111 (DIAGR_s)
4.0
5.0
5/2018
6/2018
•
Added MC22XS4200CEK part to Table 1 and associated 98ASA00894D package information
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Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to
anyproducts herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for
any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation, consequential or incidental damages.
"Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different
applications, and actual performance may vary over time. All operating parameters, including "typicals," must be
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its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which
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All other product or service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2018.
Document Number: MC22XS4200
Rev. 5.0
6/2018
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