MC33742PEG/R2_技术文档

Document Number: MC33742

Rev. 14.0, 6/2013

Freescale Semiconductor

Technical Data

System Basis Chip with

Enhanced High Speed CAN

Transceiver

33742

33742S

SYSTEM BASIS CHIP

The 33742 and the 33742S are SPI-controlled System Basis Chips

(SBCs), combining many frequently used functions, along with a CAN

2.0-compliant transceiver, used in many automotive electronic control

units (ECUs). The 33742 SBC has a fully protected fixed 5.0 V low

dropout internal regulator, with current limiting, over-temperature pre-

warning, and reset. A second 5.0 V regulator can be implemented using

external pass PNP bipolar junction pass transistor, driven by the SBC’s

external V2 sense input and V2 output drive pins.

EG SUFFIX (PB-FREE)

EP SUFFIX

(PB-FREE)

98ASA10825D

48-PIN QFN

98ASB42345B

28-PIN SOICW

The SBC has four main operating modes: Normal, Standby, Stop, and

Sleep mode. Additionally, there is an internally switched high side power

supply output, four wake-up inputs pins, a programmable window

watchdog, interrupt, reset, and a SPI module for communication and

control. The high speed CAN A and B transceiver is available for inter-

module communication.

ORDERING INFORMATION

Temperature

Range (T_A)

Device

Package

Features

MC33742PEG/R2

MC33742SPEG/R2

MC33742PEP/R2

• 1.0 Mbps CAN transceiver bus interface with bus diagnostic capability

• SPI control at frequencies up to 4.0 Mhz

• 5.0 V low dropout voltage regulator with current limiting, over-

temperature prewarning, and output monitoring and reset

• A second 5.0 V regulator capability using an external series pass

transistor

28 SOICW

48 QFN

-40 to 125 °C

• Normal, Standby, Stop, and Sleep modes of operation with low Sleep

and Stop mode current

• A high side switch output driver for controlling external circuitry

V_PWR

33742

V2

5.0V

VDD VSUP

V2CTRL

RST

V2

MCU

V_PWR

CS

L0

L1

L2

L3

SCLK

SPI

MOSI

MISO

MOSI

MISO

Safe

WDOG

HS

Circuitry

INT

ECU Local

Circuitry

Twisted

TXD

RXD

CANH

CANL

GND

CAN Bus

Pair

GND

Figure 1. 33742 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

DEVICE VARIATIONS

Table 1. Device Differences During a Reset Condition

Part No.

Reset Duration

Device Differences

See Page

33742

15 ms (typical)

page 18

The duration the RST pin is asserted low when the Reset mode is entered after

the SBC is powered up, a V_DDunder-voltage condition is detected, and the

watchdog register is not properly triggered.

33742S

3.5 ms (typical)

page 18

The duration the RST pin is asserted low when the Reset mode is entered after

the SBC is powered up, a V_DDunder-voltage condition is detected, and the

watchdog register is not properly triggered.

33742

Analog Integrated Circuit Device Data

2

Freescale Semiconductor

INTERNAL BLOCK DIAGRAM

V2

V2CTRL

VSUP Monitor

Dual Voltage Regulator

VSUP

5.0V/200mA

V1 Monitor

HS Control

V1

Mode Control

Oscillator

HS

INT

Interrupt

Watchdog

Reset

WDOG

RST

MOSI

SCLK

MISO

CS

L1

L2

L3

L4

Programmable

Wake-up Input

SPI

High-speed

1.0 Mbps

CAN Physical

Interface

CANH

CANL

TXD

RXD

GND

Figure 2. 33742 Simplified Internal Block Diagram

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

WDOG

CS

RXD

TXD

VDD

RST

2

3

MOSI

MISO

SCLK

GND

CANL

CANH

L3

4

5

INT

6

GND

V2

7

8

9

10

11

12

13

14

V2CTRL

VSUP

HS

L2

L0

L1

Figure 3. 33742 28-Pin Connections

Table 2. 33742 28-Pin Definitions

A functional description of each pin can be found in the Functional Pin description section beginning on page 22.

Pin Name

Formal Name

Definition

CAN bus receive data output pin.

CAN bus transmit data input pin.

1

2

3

4

RXD

TXD

VDD

RST

Receive Data

Transmit Data

5.0 V regulator output pin. Supply pin for the MCU.

Voltage Digital Drain

This is the device reset output pin whose main function is to reset the MCU. This pin has

an internal

Reset Output

(Active LOW)

-up current source to VDD.

This output is asserted LOW when an enabled interrupt condition occurs. The output is

a push-pull structure.

5

INT

GND

V2

Interrupt Output

(Active LOW)

These device ground pins are internally connected to the package lead frame to provide

a 33742-to-PCB thermal path.

6–9

20–23

Ground

Sense input for the V2 regulator using an external series pass transistor. V2 is also the

internal supply for the CAN transceiver.

10

Voltage Source 2

Output drive source for the V2 regulator connected to the external series pass transistor.

Supply input pin for the 33742.

11

12

V2CTRL

VSUP

HS

Voltage Source 2 Control

Voltage Supply

Output of the internal high side switch. The output current is internally limited to 150 mA.

Inputs from external switches or from logic circuitry.

CAN high output pin.

13

High Side Output

Level 0-3 Inputs

14–17

18

L0-L3

CANH

CANL

SCLK

MISO

CAN High Output

CAN Low Output

Serial Data Clock

Master In Slave Out

CAN low output pin.

19

Clock input pin for the Serial Peripheral Interface (SPI).

24

SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-

impedance state.

25

SPI data received by the 33742.

26

27

MOSI

CS

Master Out Slave In

Chip Select

(Active LOW)

The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted

LOW, the 33742 is the selected device of the SPI bus.

The WDOG output pin is asserted LOW if the software watchdog is not correctly

triggered.

28

Watchdog Output

(Active LOW)

WDOG

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

PIN CONNECTIONS

36 NC

1

NC

SCLK 2

MISO

CANL

35

34

33

32

31

30

29

28

CANH

L3

3

MOSI 4

CS 5

L2

Transparent

Top View

L1

WDOG

RXD

6

7

8

9

L0

HS

TXD

VDD

VSUP

27 V2 CTRL

26 V2

RST 10

INT 11

25

NC

12

Figure 4. 33742 48-Pin Connections

Table 3. 33742 48-Pin Definitions

A functional description of each pin can be found in the Functional Pin description section beginning on page 22.

Pin Name

NC

Formal Name

No Connect

Definition

No connection.

1, 12-16,

21-25,

36-40,

45-48

Clock input pin for the Serial Peripheral Interface (SPI).

2

3

SCLK

MISO

Serial Data Clock

SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-

impedance state.

Master In Slave Out

SPI data received by the 33742.

4

5

MOSI

CS

Master Out Slave In

Chip Select

(Active LOW)

The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted

LOW, the 33742 is the selected device of the SPI bus.

The WDOG output pin is asserted LOW if the software watchdog is not correctly

triggered.

6

Watchdog Output

(Active LOW)

WDOG

CAN bus receive data output pin.

7

8

RXD

TXD

VDD

RST

Receive Data

Transmit Data

CAN bus transmit data input pin.

5.0 V regulator output pin. Supply pin for the MCU.

9

Voltage Digital Drain

This is the device reset output pin whose main function is to reset the MCU. This pin has

an internal pull-up current source to VDD.

10

Reset Output

(Active LOW)

This output is asserted LOW when an enabled interrupt condition occurs. The output is

a push-pull structure.

11

INT

Interrupt Output

(Active LOW)

These device ground pins are internally connected to the package lead frame to provide

a 33742-to-PCB thermal path.

17-20

41-44

GND

Ground

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

PIN CONNECTIONS

Table 3. 33742 48-Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin description section beginning on page 22.

26

Pin Name

V2

Formal Name

Definition

Sense input for the V2 regulator using an external series pass transistor. V2 is also the

internal supply for the CAN transceiver.

Voltage Source 2

Output drive source for the V2 regulator connected to the external series pass

transistor.

27

V2CTRL

Voltage Source 2 Control

Supply input pin for the 33742.

28

29

VSUP

HS

Voltage Supply

High Side Output

Level 0-3 Inputs

CAN High Output

CAN Low Output

Output of the internal high side switch. The output current is internally limited to 150 mA.

Inputs from external switches or from logic circuitry.

CAN high output pin.

30-33

34

L0-L3

CANH

CANL

CAN low output pin.

35

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 4. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage at VSUP

Continuous (Steady-state)

V_SUP

V

-0.3 to 27

-0.3 to 40

Transient Voltage (Load Dump)

Logic Signals 

V_LOG

-0.3 to V_DD+ 0.3

V

(RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT)

Output Voltage at VDD

Output Current at VDD

V_DD

I_DD

0.0 to 5.3

V

A

Internally Limited

HS

Voltage

V_HS

I_HS

-0.3 to V_SUP+ 0.3

Internally Limited

V

A

Output Current

ESD Capability, Human Body Model⁽¹⁾

MC33742 in 28-pin SOIC

HS, L0, L1, L2, L3, CANH, CANL pins

All Other pins

V_ESD1

V

±4000

±2000

MC33742 in 48-pin QFN

All pins

±2000

±200

ESD Capability, Machine Model⁽¹⁾

V_ESD2

V

Input Voltage/Current at L0, L1, L2, L3

DC Input Voltage

V_DCIN

I_DCIN

-0.3 to 40

±2.0

V

mA

V

DC Input Current

Transient Input Voltage attached to external circuitry⁽²⁾

V_TRINEC

±100

CANL and CANH

Continuous Voltage

Continuous Current

V_CANH/L

I_CANH/L

-27 to 40

200

V

mA

CANH and CANL Transient Voltage (Load Dump)⁽³⁾

CANH and CANL Transient Voltage⁽³⁾

Notes

V_LDH/L

V_TRH/L

40

V

±40

1. Testing done in accordance with the Human Body Model (C_ZAP=100 pF, R_ZAP=1500 ), Machine Model (C_ZAP=200 pF, R_ZAP=0 ).

2. Testing done in accordance with ISO 7637-1. See Figure 5.

3. Load dump testing done in accordance with ISO 7637-1, Transient test done in accordance with ISO 7637-1. See Figure 6.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 4. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating

Symbol

Value

Unit

THERMAL RATINGS

Operating Temperature

Ambient

C

T_A

T_J

-40 to 125

-40 to 150

Junction

Storage Temperature

Thermal Resistance

T_STG

R_JG

-55 to 165

20

C

C/W

Thermal Resistance Junction Case (QFN)

Power Dissipation⁽⁴⁾

R_TJC-R_JC

P_D

TBD

1.0

W

Peak Package Reflow Temperature During Reflow^{(6) (7)}

,

T_PPRT

Note 7

°C

Notes

4. Maximum power dissipation is at 85 °C ambient temperature in free aIr and with no heatsink, according to JEDEC JESD51-2 and

JESD51-3 specifications.

5. The package is not designed for immersion soldering. The maximum soldering time is 10 seconds at 240 C on any pin. Exceeding the

maximum temperature and time limits may cause permanent damage to the device.

6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

33742

Transient Pulse

Generator

(Note)

1.0 nF

Lx

10 k

GND

Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

Figure 5. Transient Test Setup for L0:L3 Inputs

33742

1.0 nF

CANH

Transient Pulse

Generator

(Note)

CANL

GND

1.0 nF

Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

Figure 6. Transient Test Setup for CANH/CANL

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

INPUT PIN (VSUP)

Supply Voltage

V_SUP

V

Nominal DC Voltage

5.5

18

4.5

—

18

27

5.5

40

27

Extended DC Voltage: Full Functionality⁽⁸⁾

Extended DC Voltage: Reduced Functionality⁽⁹⁾

Load Dump

Jump Start

—

Supply Current in Standby Mode⁽¹⁰⁾

(I_OUTat VDD = 40 mA, CAN Recessive or Sleep Mode)

I_SUP(STDBY)

I_SUP(NORM)

I_SUP(SLP-WD)

mA

A

T_A 25 C

—

42

45

Supply Current in Normal Mode⁽¹⁰⁾

(I_OUTat VDD = 40 mA, CAN Recessive or Sleep mode)

T_A 25 C

Supply Current in Sleep Mode⁽¹⁰⁾

(VDD and V2 OFF, CAN in Sleep Mode with CAN Wake-up Disabled⁽¹¹⁾

)

V_SUP< 13.5 V, Oscillator Running⁽¹²⁾

V_SUP< 13.5 V, Oscillator Not Running⁽¹³⁾

V_SUP= 18 V, Oscillator Running⁽¹²⁾

—

85

53

105

80

110

140

Supply Current in Sleep Mode⁽¹⁰⁾

I_SUP(SLP-WE)

A

(V1 and V2 OFF, V_SUP< 13.5 V, Oscillator Not Running⁽¹³⁾, CAN in Sleep

Mode with Wake-up Enabled)

T_A= -40 C

T_A= 25 C

T_A= 125 C

—

80

65

55

—

Supply Current in Stop Mode⁽¹⁰⁾

I_SUP(STOP-WD)

(I_OUTat VDD < 2.0 mA, VDD ON, CAN in Sleep Mode with Wake-up

Disabled⁽¹¹⁾

)

VSUP < 13.5 V, Oscillator Running⁽¹²⁾

VSUP < 13.5 V, Oscillator Not Running⁽¹³⁾

VSUP = 18 V, Oscillator Running⁽¹²⁾

—

80

160

210

100

Notes

8. All functions and modes available and operating: Watchdog, HS turn ON/turn OFF, CAN transceiver operating, L0:L3 inputs operating,

normal SPI operation. The 33742 may experience an over-temperature fault.

9. At VDD > 4.0 V, RST HIGH if reset 2 selected via SPI. The logic HIGH level will be degraded but the 33742 is functional.

10. Current measured at the VSUP pin.

11. If CAN Module is Sleep-enabled for wake-up, an additional current (I_CAN-SLEEP) must be added to specified value.

12. Oscillator running means one of the following function is active: Forced Wake-up or Cyclic Sense or Software Watchdog in Stop mode.

13. Oscillator not running means none of the following functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in

Stop mode.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

INPUT PIN (VSUP) (CONTINUED)

Supply Current in Stop Mode⁽¹⁴⁾

I_SUP(STOP-WE)

A

(I_OUTat VDD < 2.0 mA, VDD ON, VSUP < 13.5 V, Oscillator Not Running,

CAN in Sleep Mode with Wake-up Enabled)⁽¹⁵⁾

T_A= -40 C

T_A= 25 C

T_A= 125 C

—

100

92

—

80

BATFAIL Flag Internal Threshold

BATFAIL Flag Hysteresis⁽¹⁶⁾

V_BF

1.5

—

3.0

1.0

4.0

—

V

V_BF(HYS)

V_BF(EW)

Battery Fall Early Warning Threshold

In Normal and Standby Modes

5.3

0.1

5.8

0.2

6.3

0.3

Battery Fall Early Warning Hysteresis

In Normal and Standby Modes⁽¹⁶⁾

V_BF(EW-HYST)

V

OUTPUT PIN (VDD)⁽¹⁷⁾

VDD Output Voltage (2.0 mA < I_V1< 200 mA)

5.5 V < VSUP < 27 V

V_DDOUT

4.9

4.0

5.0

—

5.1

—

4.5 V < VSUP < 5.5 V

Dropout Voltage

I_DD= 200 mA

V_DDDRP1

V

—

0.2

0.1

0.5

Dropout Voltage, Limited Output Current and Low V_SUP

I_DD= 50 mA, 4.5 V < VSUP

V_DDDRP2

0.25

Output Current

I_DD

T_SD

T_PW

mA

°C

Internally Limited

200

160

125

285

—

350

200

160

Thermal Shutdown (Junction)

Normal or Standby Mode

Over-temperature Pre-warning (Junction)

VDDTEMP Bit Set

°C

—

Notes

14. Current measured at the VSUP pin.

15. Oscillator not running means none of the following functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in

Stop mode.

16. Guaranteed by design; it is not production tested.

17. I_DDis the total regulator output current. V1 specification with external capacitor. Stability requirement: Capacitance > 47 F, ESR < 1.3 

(tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47 F tantalum.

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

OUTPUT PIN (VDD) (CONTINUED)⁽¹⁸⁾

Symbol

Min

Typ

Max

Unit

Temperature Threshold Difference

T_SD-T_PW

V_RSTTH

20

—

40

°C

V

Reset Threshold

Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0]

Threshold 2, RSTTH Bit Set to Logic [1]

4.5

4.0

4.6

4.2

4.7

4.3

VDD for Reset Active

V_DDR

1.0

—

V_RSTTH

V

Line Regulation (I_DD= 10 mA, Capacitance = 47 F Tantalum at VDD)

9.0 V < V_SUP< 18 V

mV

—

5.0

10

25

5.5 V < V_SUP< 27 V

Load Regulation (Capacitance = 47 F Tantalum at V1)

V_LD

mV

1.0 mA < I_DD< 200 mA

—

25

30

75

50

Thermal Stability

V_THERM-S

V_SUP= 13.5 V, I_DD= 100 mA⁽¹⁹⁾

OUTPUT PIN IN STOP MODE (VDD)⁽¹⁸⁾

VDD Output Voltage

I_DD 2.0 mA

V

V_DDSTOP

4.75

5.0

5.25

I_DD 10 mA

I_DDOutput Current to Wake-up

10

17

25

mA

V

I_DDS-WU

Reset Threshold⁽¹⁸⁾

V_RST-STOP

Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0]

Threshold 2, RSTTH Bit Set to Logic [1]

4.5

4.1

4.6

4.2

4.7

4.3

Line Regulation (Capacitance = 47 F Tantalum at VDD)

V_LR-STOP

mV

5.5 V < V_SUP< 27 V, I_DD= 2.0 mA

—

5.0

15

25

75

Load Regulation (Capacitance = 47 F Tantalum at V1)

V_LD-STOP

1.0 mA < I_DD< 10 mA

Notes

18. I_DDis the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47 F,

ESR < 1.3  (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47 F

tantalum.Selectable by RSTTH bit in SPI Register Reset Control Register (RCR).

19. Guaranteed by characterization and design; it is not production tested.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TRACKING VOLTAGE REGULATOR (V2)⁽²⁰⁾

V2 Output Voltage (Capacitance = 10 F Tantalum at V2)

2.0 mA  I_V2 200 mA, 5.5 V < V_SUP< 27 V

V_DD

V₂

0.99

200

1.0

—

1.01

—

I_V2Output Current (for Information Only)

Depending on External Ballast Transistor

mA

I_V2

V2 Control Drive Current Capability⁽²¹⁾

Worst Case at T_J= 125 °C

I_V2CTRL

0.0

—

10

V2LOW Flag Threshold

3.75

4.0

4.25

V

V_2LTH

LOGIC OUTPUT PIN (MISO)⁽²²⁾

Low-level Output Voltage

I_OUT= 1.5 mA

V_OL

V_OH

I_HZ

V

0.0

V_DD-0.9

-2.0

—

1.0

V_DD

2.0

High-level Output Voltage

I_OUT= -250 A

Tri-stated MISO Leakage Current

0 V < V_MISO< V_DD

A

LOGIC INPUT PINS (MOSI, SCLK, CS)

High-level Input Voltage

V_IH

V_IL

I_IH

0.7 V_DD

-0.3

—

V_DD+ 0.3

0.3 V_DD

V

Low-level Input Voltage

High-level Input Current on CS

V_IN= 4.0 V

A

-100

-10

—

-20

10

Low-level Input Current on CS

V_IN= 1.0 V

A

I_IL

MOSI and SCLK Input Current

0 V < V_IN< V_DD

I_IN

OUTPUT PIN (RST)⁽²³⁾

High-level Output Current

0 V < V_OUT< 0.7 V_DD

I_OH

A

-300

-250

-150

Low-level Output Voltage

V_OL

V

I_O= 1.5 mA, 5.5 V < V_SUP< 27 V

I_O= 0 mA, 1.0 V <V_SUP< 5.5 V

0.0

—

0.9

RST Pull-down Current

V > 0.9 V

I_PDW

mA

2.3

—

5.0

Notes

20. V2 specification with external capacitor. Stability requirement: capacitance > 42 F and ESR < 1.3  (tantalum capacitor), external

resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10 F tantalum, 2.2 k

resistor between base and emitter of ballast transistor.

21. The guaranteed V2CTRL current capability is 10 mA. No active current limiting is used so the actual available current may be higher.

22. Push-pull structure with tri-state condition (CS HIGH).

23. Output pin only. Supply from VDD. Structure switch to ground with pull-up current source.

33742

Analog Integrated Circuit Device Data

12

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OUTPUT PIN (WDOG)⁽²⁴⁾

Low-level Output Voltage

V_OL

V

I_O= 1.5 mA, 1.0 V < V_SUP< 27 V

0.0

—

0.9

High-level Output Voltage

V_OH

I_O= -250 A

V_DD-0.9

V_DD

OUTPUT PIN (INT)⁽²⁴⁾

Low-level Output Voltage

I_O= 1.5 mA

V_OL

V

0.0

—

0.9

High-level Output Voltage

V_OH

I_O= -250 A

V_DD-0.9

V_DD

OUTPUT PIN (HS)

Driver Output ON Resistance

R_DS(ON)



T_A= 25 °C, I_OUT- 150 mA, V_SUP> 9.0 V

T_A= 125 °C, I_OUT- 150 mA, V_SUP> 9.0 V

T_A= 125 °C, I_OUT- 120 mA, 5.5 V < V_SUP< 9.0 V

—

2.0

—

2.5

4.5

5.5

3.5

Output Current Limitation

V_SUP-V_HS> 1.0 V

I_LIM

mA

160

—

500

HS Thermal Shutdown

HS Leakage Current

T_SD

I_LEAK

V_CL

155

—

190

10

°C

A

V

Output Clamp Voltage

I_OUT= -10 mA, No Inductive Load Drive Capability

-1.5

—

-0.3

INPUT PINS (L0, L1, L2, AND L3)

Low-voltage Detection Threshold

5.5 V < V_SUP< 6.0 V

V_THL

V

2.0

2.5

2.7

2.5

3.0

3.2

3.0

3.6

3.7

6.0 V < V_SUP< 18 V

18 V < V_SUP< 27 V

High-voltage Detection Threshold

5.5 V < V_SUP< 6.0 V

V_THH

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.6

4.7

6.0 V < V_SUP< 18 V

18 V < V_SUP< 27 V

Hysteresis

V_HYS

V

5.5 V < V_SUP< 27 V

0.6

-10

—

1.3

10

Input Current

I_IN

A

-0.2 V < V_IN< 40 V

Notes

24. Push-pull structure.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

CAN TRANSCEIVER CURRENT

Symbol

Min

Typ

Max

Unit

Supply Current of CAN Module

I_RES

I_DOM

I_CAN-SLEEP

I_DIS

CAN in Normal mode, Bus Recessive State

—

1.3

1.5

12

—

3.0

3.5

24

mA

A

CAN in Normal mode, Bus Dominant State without Bus Load

CAN in Sleep State, Wake-up Enabled, V2 Regulator OFF

CAN in Sleep State, Wake-up Disabled, V2 Regulator OFF⁽²⁵⁾

1.0

A

PINS (CANH AND CANL)

Bus Pin Common Mode Voltage

V_CM

-27

—

40

V

Differential Input Voltage (Common Mode Between -3.0 V and 7.0 V)

Recessive State at RXD

V_CANH-V_CANL

mV

—

500

—

Dominant State at RXD

900

Differential Input Hysteresis (RXD)

V_HYS

R_IN

100

—

mV

Input Resistance

28-pin SOIC

48-pin QFN

k

5.0

—

100

50

Differential Input Resistance

R_IND

10

—

100

k

CANH Output Voltage

TXD Dominant State

TXD Recessive State

V_CANH

V

2.75

—

4.5

3.0

CANL Output Voltage

TXD Dominant State

TXD Recessive State

V_CANL

V

0.5

2.0

—

2.25

—

Differential Output Voltage

TXD Dominant State

Vo_H-Vo_L

1.5

—

3.0

V

TXD Recessive State

100

mV

Output Current Capability (Dominant State)

mA

I_CANH

I_CANL

CANH

CANL

—

-35

—

35

Over-temperature Shutdown

T_SD

160

180

—

°C

CANL Over-current Detection⁽²⁶⁾

mA

I_CANL/OC

I_CANH/OC

CANL

CANH

60

—

200

-60

-200

CANH and CANL Input Current, Device Supplied 

(CAN Sleep mode with CAN Wake-up Enabled or Disabled)

I_CAN1

A

V_CANH, V_CANLfrom 0 V to 5.0 V

V_CANH, V_CANL= -2.0 V

—

-60

—

3.0

-50

60

10

—

75

V_CANH, V_CANL= 7.0 V

Notes

25. Guaranteed by design; it is not production tested.

26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 49

33742

Analog Integrated Circuit Device Data

14

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

PINS (CANH AND CANL) (CONTINUED)

Symbol

Min

Typ

Max

Unit

CANH and CANL Input Current, Device Unsupplied

V_CANH, V_CANL= 2.5 V

I_CAN2

A

—

-60

—

40

100

—

V_CANH, V_CANL= -2.0 V

-50

190

240

V_CANH, V_CANL= 7.0 V

DIAGNOSTIC INFORMATION (CANH AND CANL)

CANL to GND Threshold

V_LG

V_HG

—

1.75

—

V

CANH to GND Threshold

1.75

CANL to VSUP Threshold

V_LVB

V_HVB

V_L5

V_SUP-2.0

V_DD-0.43

V

CANH to VSUP Threshold

V

CANL to VDD Threshold

V

CANH to VDD Threshold

V_H5

V

RXD Weak Pull-down Current Source⁽²⁷⁾

RXD Permanent Dominant Failure Condition

I_RXDW

A

—

100

—

PINS (TXD AND RXD)

TXD Input High-voltage

TXD Input Low-voltage

V_IH

V_IL

I_IH

0.7 V_DD

-0.4

—

V_DD+ 0.4

0.3 V_DD

V

TXD High-level Input Current

V_TXD= V₂

A

-10

-150

—

-100

—

10

-50

—

TXD Low-level Input Current

V_TXD= 0 V

I_IL

A

V

RXD Output High Voltage⁽²⁸⁾

V_OH

I_RXD= 250 A

V_DD-1.0

RXD Output Low-voltage

I_RXD= 1.0 mA

V_OL

V

—

0.5

Notes

27. Guaranteed by design; it is not production tested.

28. RXD is a push-pull structure between the V2 pin and GND.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)⁽²⁹⁾

SPI Operation Frequency

f_REQ

t_PCLK

t_WSCLKH

t_WSCLKL

t_LEAD

t_LAG

0.25

250

125

100

40

—

4.0

N/A

MHz

ns

SCLK Clock Period

SCLK Clock High Time

ns

SCLK Clock Low Time

ns

Falling Edge of CS to Rising Edge of SCLK

Falling Edge of SCLK to Rising Edge of CS

MOSI to Falling Edge of SCLK

Falling Edge of SCLK to MOSI

ns

t_SISU

ns

t_SIH

40

ns

MISO Rise Time⁽³⁰⁾

C_L= 220 pF

t_RSO

ns

—

25

50

MISO Fall Time⁽³⁰⁾

C_L= 220 pF

t_FSO

ns

Time from Falling or Rising Edges of CS

MISO Low-impedance

t_SOEN

t_SODIS

—

50

MISO High-impedance

Time from Rising Edge of SCLK to MISO Data Valid

t_VALID

ns

0.2 V_DD MISO  0.8 V_DD, C_L= 200 pF

—

50

34

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT)

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop mode Activation⁽³¹⁾

t_CS-STOP

s

18

Interrupt Low-level Duration

Stop Mode

t_INT

7.0

—

10

13

—

Internal Oscillator Frequency⁽³²⁾

f_OSC

100

kHz

Notes

29. See Figure 7, SPI Timing Diagram, page 20.

30. Not production tested. Guaranteed by design.

31. Not production tested. Guaranteed by design. Detected by V2 OFF.

32. f_OSCis indirectly measured (1.0 ms reset) and trimmed.

33742

Analog Integrated Circuit Device Data

16

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED)

Watchdog Period Normal and Standby Modes

t_WDOG

ms

28-pin SOIC

Period 1

Period 2

Period 3

Period 4

48-pin QFN

Period 1

Period 2

Period 3

Period 4

8.58

39.6

88

9.75

45

10.92

50.4

112

100

350

308

392

8.3

38.5

86

9.75

45

10.92

50.4

112

100

350

300

392

Normal Request Mode Timeout

28-pin SOIC

t_NRTOUT

ms

308

300

350

392

48-pin QFN

Watchdog Period Stop Mode

t_WD-STOP

Period 1

Period 2

Period 3

Period 4

6.82

31.5

70

9.75

45

12.7

58.5

130

455

100

350

245

Watchdog Period Accuracy

Normal and Standby Modes

Stop Mode

t_ACC

%

-12

-30

—

12

30

Cyclic Sense/FWU Timing Sleep and Stop Modes

t_CSFWU

ms

Timing 1

Timing 2

Timing 3

Timing 4

Timing 5

Timing 6

Timing 7

Timing 8

3.22

6.47

12.9

25.9

51.8

66.8

134

4.6

9.25

18.5

37

5.98

12

24

48.1

96.2

124

248

504

74

95.5

191

388

271

Cyclic Sense ON Time

Sleep and Stop modes.

t_ON

s

200

-30

350

—

500

30

Cyclic Sense/FWU Timing Accuracy

Sleep and Stop modes

t_ACC

%

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED)

Delay Between SPI Command and HS Turn ON⁽³³⁾

Normal or Standby mode, V_SUP> 9.0 V

t_S-HSON

—

s

22

Delay Between SPI Command and HS Turn OFF⁽³³⁾

Normal or Standby mode, V_SUP> 9.0 V

t_S-HSOFF

Delay Between SPI and V2 Turn ON⁽³³⁾

Standby mode

t_S-V2ON

t_S-V2OFF

t_S-NR2N

s

9.0

—

22

Delay Between SPI and V2 Turn OFF⁽³³⁾

Normal mode

Delay Between Normal Request and Normal mode After Watchdog Trigger

Command⁽³³⁾

15

35

70

Normal Request mode

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED)

Delay Between SPI and CAN Normal mode⁽³⁴⁾

Normal mode⁽³⁵⁾

t_{S-CAN_N}

s

—

10

Delay Between SPI and CAN Sleep Mode⁽³⁴⁾

Normal mode ⁽³⁵⁾

t_{S-CAN_S}

Delay Between CS Wake-up (CS LOW to HIGH) and Device in Normal

Request mode (VDD ON and RST HIGH)

t_W-CS

Stop mode

15

90

40

—

90

Delay Between CS Wake-up (CS LOW to HIGH) and First Accepted SPI

Command

t_W-SPI

s

Device in Stop mode After Wake-up

N/A

Delay Between INT Pulse and First SPI Command Accepted

Device in Stop mode After Wake-up

t_S-1STSPI

s

20

25

—

N/A

—

Delay Between Two SPI Messages Addressing the Same Register

t_2SPI

OUTPUT PIN (VDD)

Reset Delay Time

s

t_D

Measured at 50% of Reset Signal

4.0

40

—

30

75

I_DDOver-current to Wake-up Deglitcher Time⁽³⁵⁾

55

t_IDD-DGLT

Notes

33. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2.

34. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2.

35. Guaranteed by design; it is not production tested.

33742

Analog Integrated Circuit Device Data

18

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V  V2  5.25 V, 5.5 V  V_SUP 18 V, and -40 C  T_A 125 C. Typical values

noted reflect the approximate parameter mean at T_A= 25 C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OUTPUT PIN (RST)

Reset Duration After VDD HIGH

ms

33742

t_RST

12

15

18

DUR

33742S

t_RSTDURS

3.0

3.5

4.0

INPUT PINS (L0, L1, L2, AND L3)

Wake-up Filter Time

t_WUF

8.0

20

38

s

CAN MODULE–SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL)

Dominant State Timeout

t_DOUT

t_LRD

200

360

520

s

Propagation Loop Delay TXD to RXD (Recessive to Dominant)⁽³⁶⁾

ns

60

70

100

110

130

200

210

225

255

310

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

80

110

Propagation Delay TXD to CAN (Recessive to Dominant)⁽³⁷⁾

t_TRD

ns

20

25

35

50

65

80

110

150

200

300

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

100

160

Propagation Delay CAN to RXD (Recessive to Dominant)⁽³⁸⁾

t_RRD

t_LDR

10

50

140

ns

Propagation Loop Delay TXD to RXD (Dominant to Recessive)⁽³⁶⁾

100

120

140

250

150

165

200

340

200

220

250

410

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

Propagation Delay TXD to CAN (Dominant to Recessive)⁽³⁷⁾

t_TDR

ns

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

60

65

125

150

180

310

150

190

250

460

75

200

Propagation Delay CAN to RXD (Dominant to Recessive)⁽³⁸⁾

t_RDR

20

30

60

ns

Non-Differential Slew Rate (CANL or CANH)

V/s

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

t_SL3

t_SL2

t_SL1

t_SL0

4.0

3.0

2.0

1.0

19

13.5

8.0

40

20

15

10

5.0

Bus Communication Rate

t_BUS

60k

—

1.0M

bps



36. See Figure 8, page 20.

37. See Figure 9, page 20.

38. See Figure 10, page 21.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

t_PCLK

CS

t_WSCLKH

t_LEAD

t_LAG

SCLK

t_WSCLKL

t_SISU

t_SIH

MOSI

MISO

Undefined

t_VALID

DI 0

Don’t Care

DI 8

Don’t Care

t_SODIS

t_SOEN

DO 0

DO 8

Note Incoming data at MOSI pin is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO pin

is set by the 33742 at SCLK rising edge (after t_VALIDdelay time).

Figure 7. SPI Timing Diagram

t

LRD

2.0 V

TXD

RXD

0.8 V

t

LDR

2.0 V

0.8 V

Figure 8. Propagation Loop Delay TXD to RXD

t

TRD

2.0 V

TXD

0.8 V

t

TDR

0.9 V

V

DIFF

0.5 V

V_DIFF= V_CANH- V_CANL

Figure 9. Propagation Delay TXD to CAN

33742

Analog Integrated Circuit Device Data

20

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

t

RDR

0.9 V

V

DIFF

0.5 V

t

RRD

2.0 V

RXD

0.8 V

Figure 10. Propagation Delay CAN to RXD

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33742 and the 33742S are system basis chips (SBCs) dedicated to automotive applications. Their functions include the

following:

• One fully protected 5.0 V voltage regulator with 200 mA total output current capability available at the VDD pin.

• VDD regulator under-voltage reset function, programmable window or time-out software watchdog function.

• Internal driver (V2) for an external series pass transistor to implement a second 5.0 V voltage regulator.

• Two running modes: Normal and Standby modes set by the system microcontroller.

• Sleep and Stop modes low power operating modes to reduce an application’s current consumption while providing a wake-

up capability from the CAN interface, L3:L0 wake-up inputs, or from a timer wake-up.

• Programmable wake-up input and cyclic sense wake-ups.

• CAN high-speed physical bus interface with TXD and RXD fault diagnostic capability and enhanced protection features.

• An SPI interface for use in communicating with a MCU and Interrupt outputs to report SBC status, perform diagnostics, and

report wake-up events.

FUNCTIONAL PIN DESCRIPTION

RECEIVE AND TRANSMIT DATA (RXD AND TXD)

The RXD and TXD pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol

handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is

HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive).

The RXD terminal is a push-pull structure between the V2 pin and GND.

Voltage Digital Drain (VDD)

The VDD pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against over-

current and over-temperature. It includes an over-temperature pre-warning flag, which is set when the internal regulator

temperature exceeds 130 °C typical. When the temperature exceeds the over-temperature shutdown (170 °C typical), the

regulator is turned off.

VDD includes an under-voltage reset circuitry, which sets the RST pin LOW when VDD is below the under-voltage reset

threshold.

RESET OUTPUT (RST)

The RESET pin RST, is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device

is not in reset mode. RST includes an internal pull-up current source. When RST is LOW, the sink current capability is limited,

allowing RST to be shorted to 5.0 V for software debug or software download purposes.

INTERRUPT OUTPUT (INT)

The Interrupt pin INT, is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR).

When an interrupt occurs, INT stays LOW until the interrupt source is cleared.

INT output also reports a wake-up event by a 10 s typical pulse when the device is in Stop mode.

VOLTAGE SOURCE 2 (V2)

The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V

supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no

external series pass transistor is used. In this case, the V2CTRL pin must be left open. Refer to Figure 31, SBC Typical

Application Schematic, page 57.

VOLTAGE SOURCE 2 CONTROL (V2CTRL)

The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor.

33742

Analog Integrated Circuit Device Data

22

Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

VOLTAGE SUPPLY (VSUP)

The VSUP pin is the battery supply input of the device.

HIGH SIDE OUTPUT (HS)

The HS pin is the internal high side driver output. It is internally protected against over-current and over-temperature.

LEVEL 0-3 INPUTS (L0: L3)

The L0:L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be

read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode.

CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL)

The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the

state of CANH and CANL is reported through RXD output. A 60 termination resistor is connected between CANH and CANL

pins.

SERIAL DATA CLOCK (SCLK)

SCLK is the Serial Data Clock input pin of the serial peripheral interface.

MASTER IN SLAVE OUT (MISO)

MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through

the MISO pin.

MASTER OUT SLAVE IN (MOSI)

MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through

this pin.

CHIP SELECT (CS)

CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected.

WATCHDOG OUTPUT (WDOG)

The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.

33742

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23

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

MC33742 - Functional Block Diagram

Outputs

Integrated Supply

5.0V Linear

VSUP Control & Monitor

Regulator (LDO)

Analog Circuitry

5.0V Regulator

Base PNP Drive

Oscillator

Mode Control

Programmable Wake-up

High-side

Switch

MCU Interface

SPI Interface

Reset & INT

CAN Physical Layer

Interface

CAN Interface / Control

Watchdog Timer

Integrated Supply

Analog Circuitry

MCU Interface

Outputs

OUTPUTS

5.0 V LINEAR REGULATOR (LDO)

This low dropout linear regulator (V1) outputs a regulated 5.0 V at 200 mA. The associated monitoring circuit provides

detection of under-voltage, over-current, and short-circuit conditions, as well as over-temperature and a reset function.

5.0 V REGULATOR BASE PNP DRIVE

The V2 linear regulator control circuitry provides drive for an external series pass transistor (PNP type). The 5.0 V output tracks

the V1 regulator

HIGH SIDE SWITCH

The high switch provides a 2.0 ohm (typ.) RDS_ONMOSFET driver connected to the VSUP pin. The output is protected against

short-circuit conditions and provides over-temperature shutdown.

CAN PHYSICAL LAYER INTERFACE

This circuitry provides communication between the TXD & RXD pins, from/to the MCU, and the CANL & CANH pins of the

CAN physical interface. The various modes of the CAN interface are controlled through the SPI control registers.

INTEGRATED SUPPLY

VSUP CONTROL & MONITOR

This circuitry protects the IC from transient conditions such as vehicle jump-start (27 V) and load dump (40 V). If the V_SUP

voltage falls below 3.0 V (or a 6.0 V warning interrupt), an under-voltage detection is reported.

33742

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Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

ANALOG CIRCUITRY

OSCILLATOR

This circuit is used to generate the internal timings for reset, watchdog, cyclic wake-up, filtering time, etc.

MODE CONTROL

The 4 operating modes of the IC are controlled through the SPI control registers. There are also several special modes

possible.

PROGRAMMABLE WAKE-UP

The 4 inputs are used in conjunction with various SPI control register bits to determine the wake-up conditions and the reaction

of the IC. They can be connected to contact switches or other ICs.

MCU INTERFACE

SPI INTERFACE

The IC and the MCU communicate using the SPI control and status reporting registers. The clock speed (SCLK) can be as

high as 4.0 MHz.

RESET & INT

These 2 outputs notify the MCU when the IC is in reset mode, or when an enabled interrupt condition has occurred.

WATCHDOG TIMER

The timer can be used as a watchdog window or watchdog timeout function. The SPI control register provide the choice as

well as the timeout value. When the watchdog timer is not properly serviced by the MCU, an error signal (WDOGN low) and a

reset signal (RSTN low) are output.

CAN INTERFACE/CONTROL

The operation of the CAN interface is controlled by the MCU through the use of SPI control register bits.

33742

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25

FUNCTIONAL DEVICE OPERATION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

FUNCTIONAL DEVICE OPERATION

SUPPLY VOLTAGE AT VSUP

The 33742 receives its operating voltage via the VSUP pin. An external diode is needed in series with the VSUP pin and the

supply voltage to protect the SBC against negative transients or from a reverse battery situation that can occur in a vehicle

application. The 33742 will operate from a supply voltage input as low as 4.5 VDC to as high as 27 VDC. The later voltage is

often encountered during a vehicle jump-start.

The VSUP pin can tolerate automotive transient conditions such as load dump to 40 V. The SBC is able to detect when V_SUP

falls below 3.0 V typical. This under-voltage state is detected and retained in the parts Mode Control Register (MCR) as the

BATFAIL bit. This detection capability is available across all operating modes.

Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI Interface And

Register Description beginning on page 46.

The SBC incorporates a V_SUPlevel early warning function, which provides a maskable interrupt if the VSUP voltage level falls

below 6.0 V typical. Hysteresis is used to reduce false detections. The early warning function works only in Normal and Standby

operation modes. An under-voltage at the VSUP pin is reported in the Input/Output Register (IOR).

VDD REGULATOR

The VDD regulator provides a 5.0 V low dropout voltage capable of supplying up to 200 mA with monitoring circuitry for under-

voltage detection and a reset function. The VDD regulator is protected against over-current and short-circuit conditions. It has

over-temperature detection and will set warning flags (bit VDDTEMP in the MCR and INTR registers) and has over-temperature

shutdown with hysteresis.

V2 REGULATOR

The V2 regulator feature provides for a second 5.0 VDC voltage source The internal V2 circuitry will drive an external series

pass transistor, substantially increasing the available supply current. Two pins, the V2 and the V2CTRL, are used to sense and

drive the series pass transistor. The output voltage is 5.0 V and tracks the VDD regulator. The MJD32C transistor is

recommended for use as the external pass device. Other PNP transistors can be used but depending on the device’s gain, an

external resistor-capacitor network might be needed. V2 is also the supply voltage for the on-board CAN module. An under-

voltage condition for the V2 voltage is reported in the IOR Register (bit V2LOW set to logic [1] if V2 falls below 4.0 V typical).

HS VSUP SWITCH OUTPUT

The HS output is a 2.0  typical switch tied to the VSUP pin. It can power or bias external switches and their associated pull-

up or put-downs or other circuitry. An example is biasing a set of switches connected to the L0:L3 wake-up input pins. The HS

VSUP output current is limited to 200 mA and is protected against short-circuits conditions and will report an over-temperature

shutdown condition (bit HSOT in the IOR register and bit HSOT-V2LOW in the INTR register).

The HS output “on” state is set by the HSON bit in the IOR register. A cyclic mode of operation can be implemented using an

internal timer in the Sleep and Stop operating modes. It can also be turned on in Normal or Standby modes to drive loads or

supply peripheral components. No internal protection circuitry is provided, however. Dedicated chip protection circuitry is required

for inductive load applications. The HS output pin should not go below -0.3 V.

BATTERY FAIL EARLY WARNING

Refer to the previous discussion under the heading, Supply Voltage at VSUP.

INTERNAL CLOCK

The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). There are

two on-board oscillators: a higher accuracy (±12 percent) oscillator used in Normal Request, Normal, and Standby modes, and

a lower accuracy (±30 percent) oscillator used during Sleep and Stop modes.

33742

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Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

INTRODUCTION

The 33742 has four modes of operation, all controllable via the SPI. The modes are Standby, Normal, Stop, and Sleep. An

additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake-up from

Stop mode. A Reset mode is also implemented. Special modes and configurations are possible for debug and program

microcontroller flash memory.

Table , page 28, offers a summary of the functional modes.

STANDBY MODE

In Standby mode only the VDD regulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL pin. Other functions

available are the L0:L3 inputs read through via the SPI and HS output activation.

The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. The watchdog timer

is running.

NORMAL MODE

In Normal mode, both the VDD and V2 regulators are in the ON state. All functions are available in this operating mode

(watchdog, wake-up input reading through SPI, HS activation, and CAN communication). The watchdog timer is running and

must be periodically cleared through SPI.

STOP MODE

The V2 regulator is turned OFF by disabling the V2CTRL pin. The VDD regulator is activated in a special low power mode

supplying only a few mA of current. This maintains “keep alive” power for the application’s MCU while the MCU is in a power-

saving state (i.e., a MCU’s version of Stop or Wait). In the Stop mode, the supply current available from VSUP pin is very low.

Both parts (the SBC or the MCU) can be awakened from either the 33742 side (for example, cyclic sense, forced wake-up,

CAN message, wake-up inputs, and over-current on VDD) or from the MCU side (key wake-up, etc.).

Stop mode is always selected via SPI. In Stop mode, the watchdog software may be either running or not running depending

upon selection by SPI (Reset Control Register [RCR], bit WDSTOP). To clear a running watchdog timer, the SBC must be

awakened using the CS pin (SPI wake-up). In Stop mode, wake-up is identical to that in Sleep mode, with the addition of CS and

VDD over-current wake-up. Refer to Table , page 28.

SLEEP MODE

In Sleep mode, the VDD and V2 regulators are OFF. Current consumption from the VSUP pin is cut. In Sleep mode, the SBC

can be awakened by sensing individual level individual level changes in the L0:L3 inputs, by cyclic checking of the L0:L3 inputs,

by the forced wake-up timer, or from the CAN physical interface upon receiving a CAN message. When a wake-up occurs, the

SBC goes first into the Reset mode before entering Normal Request mode.

RESET MODE

In the Reset mode, the RST pin is LOW and a timer runs for t_RSTDURtime. After t_RSTDURhas elapsed, the 33742 enters the

Normal Request operating mode. The Reset mode is entered if a reset condition occurs (VDD LOW, watchdog time-out, or

watchdog trigger in a closed window).

NORMAL REQUEST MODE

The Normal Request mode is a temporary operating mode automatically entered by the SBC after the Reset mode or after the

33742 wakes up from the Stop mode.

After a wake-up from the Sleep mode or after a device power-up, the SBC enters the Reset mode prior to entering the Normal

Request mode. After a wake-up from the Stop mode, the 33742 enters the Normal Request mode directly.

In Normal Request mode, the VDD regulator is ON, the V2 regulator is OFF, and the RST pin is HIGH. As soon as the SBC

enters the Normal Request mode, an internal 350ms timer is started (parameter t_NRTOUT). During this time, the application’s MCU

must address the 33742 via SPI and configure the TIM1 sub register to select the watchdog period. This is required of the SBC

to stop the 350 ms watchdog timer and enter the Normal or Standby mode and to set the watchdog timer configuration.

33742

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27

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

NORMAL REQUEST ENTERED AND NO WATCHDOG CONFIGURATION OCCURS

If the Normal Request mode is entered after the SBC powers up or after a wake-up from Stop mode and no watchdog

configuration occurs before the 350 ms time period has expired, the device enters the Reset mode. If no watchdog configuration

is performed, the 33742 will cycle from the Normal Request mode to Reset mode to Normal Request mode.

If the Normal Request mode is entered after a wake-up from Sleep mode, and no watchdog configuration occurs while the

33742S is in Normal Request mode, the SBC returns to the Sleep mode.

Table 7. Table of Operations

Wake-up

Voltage Regulator

HS Switch

Watchdog

Software

Mode

Capabilities

(if Enabled)

RST Pin

INT Pin

CAN Cell

Normal

Request

VDD: ON,

V2: OFF,

HS: OFF

–

Low for t_RSTDURtime,

then HIGH

–

Normal

VDD: ON,

V2: ON,

HS: Controllable

–

Normally HIGH.

Active LOW if WDOG

or V_DDunder-voltage

occurs

If enabled, signal

failure (VDD

Pre-warning

Running

TXD/RXD

Low power

Temp, CAN, HS)

Standby

Stop

VDD: ON,

V2: OFF,

HS: Controllable

–

Same as Normal

mode

Same as Normal

mode

Running

VDD: ON

(Limited Current

Capability),

CAN, SPI, L0:L3,

Cyclic Sense,

Forced Wake-up,

Normally HIGH.

Active LOW if

WDOG⁽⁴¹⁾

Signal 33742S

wake-up and

Running if

enabled.

Not running if

disabled

Low power.

Wake-up capability

if enabled

I

_DD> I_DDS-WU

V2: OFF,

HS:OFF or Cyclic Sense

I

_DDOver-current⁽⁴⁰⁾orVDDunder-voltage (not maskable)

occurs

Sleep

VDD: OFF,

V2: OFF,

HS: OFF or Cyclic

CAN, SPI,

L0:L3, Cyclic Sense

Forced Wake-up

LOW

Not Active

Not running

Low power.

Wake-up capability

if enabled

Normal

Same as Normal

Same as Standby

Same as Stop

–

Normally HIGH.

Active LOW if VDD

under-voltage occurs

Same as Normal Not running

Same as Normal

Debug⁽³⁹⁾

Standby

–

Normally HIGH.

Active LOW if VDD

under-voltage occurs

Same as Standby Not running Same as Standby

Debug⁽³⁹⁾

Stop

Same as Stop

Normally HIGH.

Active LOW if VDD

under-voltage occurs

Same as Stop

Not operating

Not running

Same as Stop

Not operating

Debug⁽³⁹⁾

Flash

Forced externally

–

Not operating

Programming

Notes

39. Mode entered via special sequence described under the heading Debug Mode: Hardware and Software Debug with the 33742,

beginning on page 34.

40. I_DDover-current always enabled.

41. WDOG if enabled.

APPLICATION WAKE-UP FROM THE 33742

When the application is in Stop mode, it can be awakened from the SBC side. When a wake-up condition is detected by the

SBC (for example, CAN, wake-up input), the 33742 enters the Normal Request mode and generates an interrupt pulse at the

INT pin.

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

APPLICATION WAKE-UP FROM THE MCU

When the device is in the Stop mode, a wake-up event may come from the system MCU. In this case the MCU selects the

device the using a LOW-to-HIGH transition on the 33742 CS pin. Then the 33742S goes into Normal Request mode and

generates an interrupt pulse at the INT pin.

STOP MODE CURRENT MONITOR

If the VDD output current exceeds an internal set threshold (I_DDS-WU), the SBC automatically enters the Normal Request mode

and generates an interrupt at the INT pin. The interrupt is a non-maskable and the INTR register will have no flag set.

INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE

When the SBC wakes from Stop mode, it first enters the Normal Request mode before generating a 10 s typical pulse on the

INT pin. These are non-maskable interrupts with the wake-up event read through the SPI registers, the CANWU bit in the CAN

Register (CANR), or the LCTRx bit in the Wake-up Register (WUR). In case of wake-up from Stop mode over-current situation

or from forced wake-up, no bits are set. After the INT pulse, the 33742 accepts SPI command after a time delay (t_S-1STSPI).

WATCHDOG SOFTWARE IN STOP MODE

If the SBC watchdog is enabled, the application must provide a “system ok” response before the end of the 33742 watchdog

time. Typically an MCU initiates the wake-up of the 33742 through the SPI wake-up (CS activation). The SBC will awaken and

jump into the Normal Request mode. The MCU has to configure the 33742 to go to either Normal or Standby mode. The MCU

can then decide to return to the Stop mode.

If no MCU wake-up occurs within the watchdog time period, the SBC activates the RST pin and jumps into the Normal Request

mode. The MCU can then be re-initialized.

STOP MODE ENTER COMMAND

Stop mode is entered at the end of the SPI message at the rising edge of the CS. (Refer to the t _CS-STOPdata in the Dynamic

Electrical Characteristics table on page 16.) Once Stop mode is entered, the SBC can wake up from a VDD regulator over-current

detection state. In order to allow time for the MCU to complete the last CPU instruction and enter its low power mode, a deglitcher

time of 40 s typical is implemented.

Figure 11, page 29, depicts the operation of entering the Stop mode.

SPI Stop/Sleep

Command

SPI CS

t

CS-STOP

IDD-DGLT

33742 in Stop mode.

No I_DDover I_DD-DGLT

33742 in Normal

or Standby mode

33742 in Stop mode.

I_DDover I_DD-DGLT

Figure 11. Entering the Stop Mode

WATCHDOG SOFTWARE (RST AND WDOG)(SELECTABLE WATCHDOG WINDOW 

OR WATCHDOG TIME-OUT)

A watchdog is used in the SBC Normal and Standby modes for monitoring the MCU operation. The watchdog timer may be

implemented as either a watchdog window or watchdog timeout, selectable by SPI (TIM1 sub register, bit WDW). Default

operation is a watchdog window.

The watchdog period can be set from 10 to 350 ms (TIM1 sub register, bits WDT0 and WDT1). When a watchdog window is

selected, the closed window is the first part of the selected period, and the open window is the second part of the period. (Refer

to Timing Register (TIM1/2) beginning on page 52.)

The watchdog can only be cleared within the open window time period. Any attempt to clear watchdog in the closed window

will generate a reset. The watchdog is cleared addressing the TIM1 sub register using the SPI

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

RST PIN DESCRIPTION

A 33742 output is available to perform a reset of the MCU. Reset can happen from:

• V_DDFalling Out of Range—If V_DDfalls below the reset threshold (V_RSTTH), the RST pin is pulled LOW until V_DDreturns to

the normal voltage.

• Power-ON Reset—At 33742 power-on or wake-up from Sleep mode, the RST pin is maintained LOW until V_DDis within its

operation range.

• Watchdog Timeout—If watchdog is not cleared, the 33742 will pull the RST pin LOW for the duration of the reset time

(t_RSTDUR).

RST AND WDOG OPERATION

Table 8 describes watchdog and reset output modes of operation. RST is activated in the event V_DDfall or watchdog is not

triggered. WDOG output is active LOW as soon as RST goes LOW and stays LOW as long as the watchdog is not properly reset

via SPI. The WDOG output pin is designed as a push-pull structure that can drive off chip components signaling, for instance,

errant MCU operation.

Figure 12 illustrates the device behavior in the event the TIM1 register in not properly accessed. In this case, a software reset

occurs and the WDOG pin is set LOW until the TIM1 register is properly accessed.

Table 8. Watchdog and Reset Output Operation

WDOG

Events

RST Output

Output

Device Power up

V_DDNormal, WDOG Properly Triggered

V_DD< V_RSTTH

LOW to HIGH

HIGH

LOW to HIGH

HIGH

LOW

WDOG Timeout Reached

LOW ⁽⁴²⁾

LOW

Notes

42. WDOG stays LOW until the TIM1 register is properly addressed through SPI.

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Device power up

Device is in Normal mode, W/D refresh failure

V

SUP

V

DD

V

DD

RST

Watchdog

Period

WDOG

SPI

Mode

N-Request

RESET

Normal

SPI CS

Power up

Watchdog refresh failure

Device is in stop mode

Device is in sleep mode

V

SUP

V

SUP

V

DD

INT

RST

WDOG

SPI

WDOG

SPI

Mode Stop

Mode Sleep

N-Request

N-Request Normal

RESET

Normal

Wake-up event

Legend: TIM1 register write

Figure 12. RST and WDOG Output Operation

WAKE-UP CAPABILITIES

Several wake-up capabilities are available to the SBC when it is in Sleep or Stop mode. When a wake-up has occurred, the

wake-up event is stored in the Wake-up Register (WUR) or the CAN register and read by the MCU to determine the wake-up

source. The wake-up options are selectable through SPI while the 33742 is in Normal or Standby mode and prior to entering low

power modes (Sleep or Stop mode). When a wake-up occurs in Sleep mode, the SBC reactivates the VDD supply. It generates

an interrupt if a wake-up occurs from Stop mode.

WAKE-UP FROM WAKE-UP INPUTS (L0:L3) WITHOUT CYCLIC SENSE

The wake-up lines are used to determine the state of external switches and if changes occurred to wake up the MCU (in Sleep

or Stop modes). The wake-up pins L0:L3 are able to handle up to 40 VDC. The internalize” threshold is 3.0 V typical, and these

inputs can be used as an input port expander. The wake-up input states are read through SPI (WUR register).

In order to select and activate direct wake-up from the L0:L3 inputs, the WUR register must be configured with the appropriate

level sensitivity. Additionally, the Low Power Control (LPC) Register must be configured with 0xx0 data (bits LX2HS and

HSAUTO are set to 0).

The sensitivity of the L0:L3 inputs is selected by the WUR register. Level sensitivity is configured by L0:L3 input pairs: L0 and

L1 level sensitivity are configured together, while L2 and L3 are configured together.

CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0:L3)

The 33742 can wake up upon state change of one of the four wake-up input lines (L0:L3). The external pull-up or pull-down

resistor of the switches associated with the wake-up input lines can be biased from the HS VSUP switch. The HS switch is

activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-up are exclusive states. If Cyclic Sense

is enabled, Forced Wake-up cannot be enabled.

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

In order to select and activate the cyclic sense wake-up from the L0:L3 inputs, the WUR register must be configured with the

appropriate level sensitivity and the LPC register must be configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO set 

at 1. The wake-up mode selection (direct or cyclic sense) is valid for all four wake-up inputs.

FORCED WAKE-UP

The SBC can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic Sense and Forced Wake-

up are exclusive. If Forced Wake-up is enabled (FWU bit set to 1 in the LPC register), Cyclic Sense cannot be enabled.

CAN INTERFACE WAKE-UP

The SBC incorporates a high-speed 1.0 Mbps CAN physical interface. It is compatible with ISO 11898-2 standard. The

operation of the CAN physical interface is controlled through the SPI. The CAN operating modes are independent of the 33742

operational modes.

The SBC can wake up from a CAN message if the CAN wake-up feature is enabled. Refer to the section titled LOGIC

COMMANDS AND REGISTERS beginning on page 46 for details of the wake-up detection.

SPI WAKE-UP

The 33742 can be awakened by changes on the CS pin in Sleep or Stop modes. Wake-up is detected as a LOW-to-HIGH level

transition on the CS pin. In the Stop mode, this corresponds to a condition where an MCU and the SBC are both in the Stop mode

and when the application wake-up event comes through the MCU.

33742 POWER-UP AND WAKE-UP FROM SLEEP MODE

After device or system power-up, or after the SBC awakens from Sleep mode, the 33742S enters into the Reset mode prior

to moving into Normal Request mode.

Figure 13, shows the device state diagram. Figure 14, shows device operation after power-up.

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Watchdog: Timeout OR V

DD

Low

Watchdog: Timeout & Nostop &!BATFAIL

SPI: Standby and

Watchdog Trigger

2

Reset Counter (3.4 ms)

Expired

1

3

Standby

Reset

Normal Request

1

V

Low OR Watchdog:

DD

Timeout 350 ms & Nostop

4

2

Power

Down

1

Normal

Stop

SPI: Stop & CS

LOW to HIGH

Transition

1

Watchdog: Timeout OR V

Low

DD

Wake-Up

(V

DD

High Temperature OR [V

Low > 100 ms & V

> BFew]) & Nostop &!BATFAIL

DD

SUP

Sleep

Denotes priority

1

2

3

4

State Machine Description

Nostop = Nostop bit = 1

!Nostop = Nostop bit = 0

BATFAIL = Batfail bit = 1

!BATFAIL = Batfail bit = 0

Watchdog: Timeout = TIM1 register not written before watchdog timeout period

expired, or watchdog written in incorrect time window if watchdog window

selected (except Stop mode). In Normal Request mode, timeout is 355 ms

p2.2 (350 ms p3) ms.

V

Over-temperature = V

thermal shutdown occurs

SPI: Sleep = SPI write command to MCR register, data sleep

SPI: Stop = SPI write command to MCR register, data stop

SPI: Normal = SPI write command to MCR register, data normal

SPI: Standby = SPI write command to MCR register, data standby

DD

below reset threshold

LOW = V

DD

LOW > 100 ms = V

below reset threshold for more than 100 ms

DD

Watchdog: Trigger = TIM1 subregister write operation

> BFew = V > Battery Fail Early Warning (6.1 V typical)

V

SUP

Notes

43. These two SPI commands must be sent consecutively in this sequence.

44. If watchdog activated.

Figure 13. SBC State Diagram (Not Valid in Debug Modes)

Power-up

Reset

Operation after power-up if no trigger appears

Operation after reset of BATFAIL if no trigger appears

Normal

Request

Yes

Batfail

No

Yes

Trigger

Yes

No Stop

Sleep

Normal

Figure 14. Operation After SBC Power-up

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

DEBUG MODE: HARDWARE AND SOFTWARE DEBUG WITH THE 33742

When a SBC, and the MCU it serves, is used on the same printed circuit board, both the MCU software and the 33742

operation must be debugged concurrently. The following features permit system debugging by allowing the disabling of the SBC

internal software watchdog timer.

DEVICE POWER-UP, RESET PIN CONNECTED TO VDD

The VDD voltage is available when the 33742 power-up but the 33742 will not have received any SPI communication to

configure itself. Until set up by the system MCU, the 33742 will generate a reset every 350 ms until the part is configured. To

avoid continuous MCU hardware resets, the 33742’s RST pin can be connected directly to the VDD pin by a hardware jumper.

DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY

DEBUG, AND STOP DEBUG)

The software configurable watchdog can be disabled through the SPI. To set the watchdog disable while limiting the risk of

inadvertently disabling the watchdog timer during normal 33742 operation, it is recommended that the disable be done using the

following sequence:

• Step 1–Power down the SBC.

• Step 2–Power up the SBC. This sets the BATFAIL bit, allowing the 33742 to enter Normal Request mode.

• Step 3–Write to the TIM1 sub register to allow the SBC to enter Normal mode.

• Step 4–Write to the MCR register with data 0000. This enables the debug mode. Complete SPI byte is 0001 0000.

• Step 5–Write to the MCR register normal debug. SPI byte is 0001 x101.

Important While in debug mode, the SBC can be used without having to clear the watchdog on a regular basis to facilitate

software and hardware debug.

• Step 6–To leave the debug mode, write 0000 to the MCR register.

At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time

period of the Normal Request mode. If not, the 33742 will go into Reset mode and enter Normal Request again.

Figure 15, page 34, illustrates debug mode selection.

V_SUP

V_DD

BATFAIL

TIM1(Step 3)

MCR (Step 5)

SPI: Read BATFAIL

MCR (Step 6)

SPI

MCR (Step 4)

33742 not in Debug mode.

Watchdog ON

Debug Mode

33742 in Debug mode.

No Watchdog

Figure 15. Entering Debug Mode

When the SBC is operating in the debug mode and has been set into Stop Debug or Sleep mode, a wake-up causes the 33742

to enter the Normal Request mode for 350 ms. To avoid having the SBC generate an unwanted reset (enter Reset mode), the

next debug mode (Normal Debug or Standby Debug) should be configured within the 350 ms time window of the Normal Request

mode.

To avoid entering debug mode after a power-up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR register.

Figures 16 and 17, page 35, show the detailed operation of the SBC once the debug mode has been selected.

33742

Analog Integrated Circuit Device Data

34

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Watchdog: Timeout 350 ms

Power

Down

Reset Counter

(3.4 ms) Expired

Reset

Normal Request

SPI: MCR (0000) and Normal Debug

SPI: MCR (0000) and Standby Debug

Normal Debug

Normal

Standby Debug

Figure 16. Transitions to Enter Debug Modes

Watchdog: Timeout 350 ms

Wake-up

Reset Counter

(3.4 ms) Expired

Reset

Sleep

Stop (1)

Normal Request

R

Normal

Stop Debug

Standby

E

SPI: Standby Debug

SPI: Normal Debug

Normal Debug

Standby Debug

R

(1) If Stop mode is entered, it is entered without watchdog, no matter the WDSTOP bit.

(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).

(R) Represents transitions to Reset mode due to V1 low.

Figure 17. Simplified 33742S State Diagram in Debug Modes

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

MCU FLASH PROGRAMMING CONFIGURATION

To allow for new software to be loaded into a SBC’s MCU NVM or to standalone EEPROM or Flash, the 33742 is capable of

having (1) VSUP applied to it to from an external power 5.0 V supply and (2) having the RST and the WDOG outputs pins

eternally forced to 0.0 or 5.0 V without damaging the device.

This allows the SBC to be externally powered and off-board signals to be applied to the reset pins. No functions of the 33742

are operating. Figure 18 illustrates a typical configuration for the connection of programming and debugging tools.

The VSUP should be left open or forced to a value equal to or above V.

The VDD regulator uses an internal pass transistor between VSUP and the VDD output pin. Biasing the VDD output pin with

a voltage greater than VDD potential will force current through the body diode of the internal pass transistor to the VSUP pin.

The RST pin is periodically pulled LOW for the t_RSTDURtime (device in Reset mode), before being pulled to VDD for 350 ms

typical (device in Normal Request mode). During the time reset is LOW, the RST pin sinks 5.0 mA maximum (I_PDW).

VDD

VSUP (Open or > 5.0 V

RST

MCU with

Flash Memory

33742

WDOG

Programming Bus

5.0 V

Programming Tool

Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board.

Figure 18. Simplified Schematic for Microcontroller Flash Programming

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

CAN PHYSICAL INTERFACE

The SBC features a high-speed CAN physical interface for bus communication from 60kbps up to 1.0Mbps. Figure 19 is a

simplified block diagram of the CAN interface of the 33742.

V2

33742

V2

SPI Control

TXD

RXD

Driver

QH

CANH

CANL

V2

CANH Line

Bus Termination (60

CANL Line

Differential

Receiver

2.5 V



)

V2

Driver

QL

SPI Control

VSUP

Internal

Wake-up

Signal

Wake-up

Pattern

Recognition

Wake-up

Receiver

SPI Control

Figure 19. Simplified Block Diagram of CAN Interface

CAN INTERFACE SUPPLY

The supply voltage for the CAN transceiver is the V2 pin. The CAN interface also has a supply path from the external supply

line through the VSUP pin. This path is used in CAN Sleep mode to allow wake-up detection.

During CAN communication (transmission and reception), the CAN interface current is sourced from the V2 pin. During CAN

low power mode, the current is sourced from the VSUP pin.

MAIN OPERATION MODES DESCRIPTION

The CAN interface of the SBC has two main operating modes: TXRX and Sleep mode. The modes are controlled by the CAN

SPI Register. In the TXRX mode, which is used for communication, four different slew rates are available for the user. In the

Sleep mode, the user has the option of enabling or disabling the remote CAN wake-up capability.

CAN DRIVER OPERATION IN TXRX MODE

When the CAN interface is in TXRX mode, the driver has two states: recessive or dominant. The driver state is controlled by

the TXD pin. The bus state is reported through the RXD pin.

When TXD is HIGH, the driver is set in recessive state, and CANH and CANL lines are biased to the voltage set at V2 divided

by 2, or approximately 2.5 V.

When TXD is LOW, the bus is set into dominant state: CANL and CANH drivers are active. CANL is pulled to ground, and

CANH is pulled HIGH toward 5.0 V (voltage at V2).

The RXD pin reports the bus state: CANH minus CANL voltage is compared versus an internal threshold (a few hundred

millivolts). If CANH minus CANL is below the threshold, the bus is recessive and RXD is set HIGH. If CANH minus CANL is above

the threshold, the bus is dominant and RXD is set LOW. This is illustrated in Figure 19.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

TXD

Typ 2.5 V

CANH

CANL

V

-V

< 500 mV

CANH CANL

V

-V

> 900 mV

CANH CANL

RXD

CAN Recessive State

CAN Dominant State

Figure 20. CAN Interface Levels

TXD AND RXD PINS

The TXD pin has an internal pull-up to V2. The state of TXD depends on the V2 status. RXD is a push-pull structure, supplied

by V2. When V2 is set at 5.0 V and CAN is TXRX mode, RXD reports bus status. For details, refer to Table , page 28, Table 9,

below, and Table 10, page 39.

The TXD pin is a push-pull structure between the V2 pin and GND. The circuitry has a parasitic diode between RXD and V2.

It is illustrated in Figure 25. This parasitic diode is reversed biased in normal operation (TXD voltage is lower or equal to V2). In

case the TXD voltage is greater than V2, a current will flow into the diode.

If the V2 pin is low (e.g. in sleep mode, or in stop with a ballast transistor), the current leakage at V2 is low enough (10 A

max) to ensure than the RXD pin can be pulled up by an external resistor (i.e. the MCU RXD pin internal pull-up).

The states of the RXD pin in the following Table 9 and 10 is dependant upon external circuitry connected to the V2 and RXD

pins.

CAN TXRX MODE AND SLEW RATE SELECTION

The slew rate selection is done via CAN register (refer to Tables 22 through 24 on page 50). Four slew rates are available and

control the recessive-to-dominant and dominant-to-recessive transitions. The delay time from TXD pin to CAN bus, from CAN

bus to RXD, and from the TXD to RXD loop time is affected by the slew rate selection.

Table 9. CAN Interface/33742S Modes and Pin Status—Operation with Ballast on V2⁽⁴⁵⁾

CANH/CANL

(Disconnected from

Other Node)

CAN Mode

(Controlled by SPI)

CAN

Communication

Mode

V2 Voltage

TXD Pin

RXD Pin⁽⁴⁶⁾

Unpowered

–

0.0 V

LOW

Floating to GND

NO

Reset (with Ballast)

Normal Request

(with Ballast)

Normal

Sleep

5.0 V

0.0 V

5.0 V

Floating to GND

NO

Normal

Internal Pull-up Report Bus State

Bus Recessive

YES

Slew Rate 0, 1, 2, 3

to V2

HIGH if Bus

Recessive,

CANH = CANL = 2.5 V

LOW if dominant

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 9. CAN Interface/33742S Modes and Pin Status—Operation with Ballast on V2⁽⁴⁵⁾

Standby with

External Ballast

Normal or Sleep

0.0 V

LOW

Floating to GND

NO

Sleep

Stop

Sleep

Floating to GND

NO.

Wake-up if enabled

Sleep

NO.

Wake-up if enabled

Notes

45. See also Figure 31, page 57.

46. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and

3) any external pull-up between RXD and the 5.0 V supply.

Table 10. CAN Interface/33742 Modes and Pin Status—Operation without Ballast on V2 ⁽⁴⁷⁾

CANH/CANL

CAN Mode

CAN

Communication

RXD Pin⁽⁴⁸⁾

Mode

V2 Voltage

TXD Pin

(Disconnected from

Other Node)

(Controlled by SPI)

Unpowered

–

0.0 V

5.0 V

LOW

5.0 V

Floating to GND

NO

Reset (without Ballast)

Normal Request without

Ballast.

V2 Connected to VDD

StandbywithoutExternal

Ballast,.

V2 connected to VDD

Normal or Sleep

5.0 V

0.0 V

5.0 V

0.0 V

5.0 V

Floating to GND

NO

YES

NO

Normal without External

Ballast.

V2 Connected to VDD

Normal

Slew Rate 0, 1, 2,3

Bus Recessive

CANH = CANL = 2.5 V

Normal without External

Ballast,.

Sleep

Floating to GND

V2 Connected to VDD

Sleep

0.0 V

5.0 V

LOW

Floating to GND

NO.

Wake-up if enabled

Stop

NO.

Wake-up if enabled

Notes

47. See also Figure 36, page 60.

48. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and

3) any external pull-up between RXD and the 5.0 V supply.

CAN SLEEP MODE

The 33742 offers two CAN Sleep modes:

• Sleep mode with CAN wake-up enable: detection of incoming CAN message and SBC wake-up.

• Sleep mode with CAN wake-up disable: no detection of incoming CAN message.

The CAN Sleep modes are set via the CAN SPI register.

In CAN Sleep mode (with wake-up enable or disable), the CAN interface is internally supplied from the VSUP pin. The voltage

at V2 pin can be either 5.0 V or turned off. When the CAN is in Sleep mode, the current sourced from V2 is extremely low. In

most cases the V2 voltage is off; however, the CAN can be placed into Sleep mode even with 5.0 V applied on V2.

In CAN Sleep mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL are high-

impedance mode to ground.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

CAN SIGNALS IN TXRX AND SLEEP MODES

When the CAN interface is set back into TXRX mode by an SPI command, CAN H and CANL are set in recessive level. This

is illustrated in Figure 21.

TXD

CANH Dominant

CANH

CANL/CANH Recessive

2.5 V

CANL

CANL Dominant

Ground

RXD

CAN in TXRX Mode

CAN in Sleep Mode

(Controlled by SPI Command)

(Wake-up Enable or Disable)

CAN in TXRX Mode

Figure 21. CAN Signals in TXRX and Sleep Modes

CAN IN SLEEP MODE WITH WAKE-UP ENABLE

When the CAN interface is in Sleep mode with wake-up enable, the CAN bus traffic is detected. The CAN bus wake-up is a

pattern wake-up.

PATTERN WAKE-UP

In order to wake up the CAN interface, the following criteria must be fulfilled:

• The CAN interface wake-up receiver must receive a series of three consecutive valid dominant pulses, each of which must be

longer than 500 ns and shorter than 500 s.

• The distance between 2 pulses must be lower than 500 s.

• The three pulses must occur within a time frame of 1.0 ms.

The pattern wake-up of the 33742 CAN interface allow wake-up by any CAN message content.

Figure 22 below illustrates the CAN signals during a CAN bus Sleep state and wake-up sequence.

33742

Analog Integrated Circuit Device Data

40

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

TXD

CANH Dominant

CANL Dominant

CANH Dominant

Pulse # 1

CANH Dominant

Pulse # 3

CANH

CANL

CANL/CANH Recessive

Ground

Pulse # 2

2.5 V

CANL Dominant

CAN Bus Sleep State

Incoming CAN Message

RXD

CAN in TXRX Mode

CAN in Sleep Mode (Wake-up Enable)

WU Receiver

Min 500 ns

Max 500



s

Internal Wake-up Signal

Figure 22. CAN Bus Signal During Can Sleep State and Wake-up Sequence

Figure 23 illustrates how the wake-up signal is generated. First the CAN signal is detected by a low consumption receiver (WU

receiver). Then the signal passes through a pulse width filter, which discards the undesired pulses. The pulse must have a width

bigger than 0.5 s and smaller than 500 s to be accepted. When a pulse is discarded, the pulse counter is reset and no wake-

up signal is generated. When a pulse is accepted, the pulse counter is incremented and, after three pulses, the internal wake-up

signal is asserted.

Each one of the pulses must be spaced by no more than 500 s. If not, the counter will be reset and no wake-up signal will be

generated. This is accomplished by the wake-up timeout generator. The wake-up cycle is completed (and the wake-up flag reset)

when the CAN interface is brought to CAN Normal mode.

Pulse OK

Counter

RST

Latch

RST

Internal Wake-up

Signal

CANH

CANL

Pulse Width

Filter

Timeout

Narrow

Pulse

+

WU Receiver

Standby

Timeout

Generator

Figure 23. Wake-up Functional Block Diagram

CAN WAKE-UP REPORT

The CAN wake-up reporting depend upon the low power mode the SBC is in.

If the SBC is placed into Sleep mode (VDD and V2 off), the CAN wake-up or any wake-up results in the VDD regulator turning

on, leading to turning on the MCU supply and releasing reset. If the 33742 is in Stop mode (V2 off and VDD active), the CAN

wake-up or any wake-up is signalled by a pulse on the INT output. In addition the CANWU bit is set in the CAN register.

If the SBC is in Normal or Standby mode and the CAN interface is in Sleep mode with wake-up enabled, the CAN wake-up is

reported by the CANWU bit in the CAN register.

In the event the SBC is in Normal mode and CAN Sleep mode with wake-up enabled, it is recommended that the user check

for the CANWU bit prior to placing the 33742 in Sleep or Stop mode in case bus traffic has occurred while the CAN interface was

in Sleep mode.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

After a CAN wake-up, a flag is set in the CAN register. Bit CANWU reports the CAN wake-up event while the 33742 was in

Sleep or Stop mode. This bit is set until the CAN is in placed by SPI command into TXRX mode and the CAN register can be read.

CAN BUS DIAGNOSTIC

The SBC can diagnose CANH or CANL lines short to GND, shorts to VSUP or VDD.

As illustrated in Figure 24, several single-ended comparators are implemented on the CANH and CANL bus lines. These

comparators monitor the bus voltage level in the recessive and dominant states. This information is then managed by a logic

circuit to determine if a failure has occurred and to report it. Table 11 indicates the state of the comparators in the event of bus

failure and the state of the drivers; that is, whether they are recessive or dominant.

V

R5

H5

V_SUP(12V–14 V)

RVB

VDD

Hb

V

(V_SUP-2.0 V)

RVB

RG

CANH

TXD

Hg

Lg

V_DD(5.0 V)

V

(V_DD-0.43 V)

Logic

R5

Diagnostic

CANH Dominant Level (3.6 V)

CANL

V

RG

Recessive Level (2.5 V)

Lb

V

RVB

V

(1.75 V)

RG

CANL Dominant Level (1.4 V)

GND (0.0 V)

L5

V

R5

Figure 24. CAN Bus Simplified Structure

Table 11. Short to GND, Short to VSUP, and Short to 5.0 V (VDD) Detection Truth Table

Driver Recessive State

Driver Dominant State

Failure Description

Lg (Threshold 1.75 V)

Hg (Threshold 1.75 V)

Lg (Threshold 1.75 V)

Hg (Threshold 1.75 V)

No failure

1

0

1

0

1

0

CANL to GND

CANH to GND

Lb (Threshold V_SUP-2.0 V) Hb (Threshold V_SUP-2.0 V) Lb (Threshold V_SUP-2.0 V) Hb (Threshold V_SUP-2.0 V)

No failure

0

1

0

1

0

1

0

1

CANL to VSUP

CANH to VSUP

H5

L5 (Threshold VDD-0.43 V) H5 (Threshold VDD-0.43 V) L5 (Threshold VDD-0.43 V)

(Threshold VDD-0.43 V)

No failure

0

1

0

1

0

1

0

1

CANL to V_DD

CANH to V_DD

DETECTION PRINCIPLE

In the recessive state, if one of the two bus lines is shorted to GND, VDD, or VSUP, then voltage at the other line follows the

shorted line due to bus termination resistance and the high-impedance of the driver. For example, if CANL is shorted to GND,

CANL voltage is zero, and CANH voltage, as measured by the Hg comparator, is also close to zero.

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

In the recessive state the failure detection to GND or VSUP is possible. However, it is impossible to distinguish which bus line,

CANL or CANH, is shorted to GND or VSUP. In the dominant state, the complete diagnostic is possible once the driver is turned

on.

CAN BUS FAILURE REPORTING

CANL bus line failures (for example, CANL short to GND) is reported in the SPI register TIM1/2. CANH bus line (for example,

CANH short to VSUP) is reported in the LPC register.

In addition CAN-F and CAN-UF bits in the CAN register indicate that a CAN bus failure has been detected.

NON-IDENTIFIED AND FULLY IDENTIFIED BUS FAILURES

As indicated in Table 11, page 42, when the bus is in a recessive state it is possible to detect an error condition; however, is

it not possible to fully identify the specific error. This is called “non-identified” or “under-acquisition” bus failure. If there is no

communication (i.e., bus idle), it is still possible to warn the MCU that the SBC has started to detect a bus failure.

In the CAN register, bits D2 and D1 (CAN-F and CAN-UF, respectively) are used to signal bus failure. Bit D2 reports a bus

failure and bit D1 indicates if the failure is identified or not (bit D1 is set to logic [1} if the error is not identified).

When the detection mechanism is fully operating any bus error will be detected and reported in the TIM1/2 and LPC registers

and bit D1 will be reset to logic [0].

NUMBER OF SAMPLES FOR PROPER FAILURE DETECTION

The failure detector requires at least one cycle of recessive and dominant state to properly recognize the bus failure. The error

will be fully detected after five cycles of recessive-dominant states. As long as the failure detection circuitry has not detected the

same error for five recessive-dominant cycles, the bit “non-identified failure” (CAN-UF) will be set.

RXD PERMANENT RECESSIVE FAILURE

The purpose of this detection mechanism is to diagnose an external hardware failure at the RXD output pin and to ensure that

a permanent failure at the RXD pin does not disturb network communication.In the event RXD is shorted to a permanent high

level signal (i.e., 5.0 V), the CAN protocol module within the MCU cannot receive any incoming message. Additionally, the CAN

protocol module cannot distinguish the bus idle state and could start communication at any time. To prevent this, an RXD failure

detection, as illustrated in Figure 25 and explained below, is necessary.

TXD

CANL

CANH

Diag

TXD

Driver

Logic

Diff Output

Sampling

2.0 V

V

2

V

2

RXD Sense

RXD Output

RXD Short to V1

CANH

CANL

RXD

RXD Flag Latched

RXD

Driver

Diff

60 

RXD Flag

GND

Prop Delay

Note The RXD Flag is neither the RXPR bit in the LPC register, nor the CANF bit in the INTR register.

Figure 25. RXD Path and RXD Permanent Recessive Detection Principle

RXD FAILURE DETECTION

The SBC senses the RXD output voltage at each LOW-to-HIGH transition of the differential receiver. Excluding internal

propagation delay, RXD output should be LOW when the differential receiver is LOW. In the event RXD is shorted to 5.0 V (e.g.,

to VDD), RXD will be tied to a high level and the RXD short to 5.0 V can be detected at the next LOW-to-HIGH transition of the

differential receiver. Compete detection requires three samples.

When the error is detected, an error flag is latched and the CAN driver is disabled. The error is reported through the SPI

register LPC, bit RXPR.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

RECOVERY CONDITION

The SBC will try to recover from a bus fault condition by sampling for a correct low level at TXD, as illustrated in Figure 26.

As soon as an RXD permanent recessive is detected, the RXD driver is deactivated and a weak pull-down current source is

activated in order to allow recovery conditions. The driver stays disabled until the failure is cleared (RXD no longer permanent

recessive) and the bus driver is activated by an SPI register command (write 1 to the CANCLR bit in the CAN register).

CANL

CANH

Diff Output

Sampling

RXD Short to V

DD

RXD Output

RXD no longer shorted to V

DD

RXD Flag Latched

RXD Flag

Note RXD Flag is neither the RXPR bit in the LPC register

nor the CANF bit in INTR register.

Figure 26. RXD Recovery Conditions

TXD PERMANENT DOMINANT FAILURE

PRINCIPLE

In the event TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible.

The SBC has a TXD permanent timeout detector. After timeout, the bus driver is disabled and the bus is released in a recessive

state. The TXD permanent dominant failure is reported in the TIM1 register.

RECOVERY

The TXD permanent dominant is used and activated also in case of TXD short to RXD. The recovery condition for TXD

permanent dominant (recovery means the reactivation of the CAN drivers) is done by an SPI command and is controlled by the

MCU.

The driver stays disabled until the failure is cleared (TXD no longer permanent dominant) and the bus driver is activated by

an SPI register command (write logic [1] to CANCLR bit in the CAN register).

TXD TO RXD SHORT CIRCUIT FAILURE

PRINCIPLE

In the event the TXD is shorted to RXD when an incoming CAN message is received, the RXD will be at a LOW. Consequently,

the TXD pin is LOW and drives CANH and CANL into the dominant state. The bus is stuck in dominant mode and no further

communication is possible.

DETECTION AND RECOVERY

The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next

incoming dominant bit, the bus will be stuck again in dominant. In order to avoid this situation, the recovery from a failure

(recovery means the reactivation of the CAN drivers) is done by an SPI command and controlled by the MCU.

INTERNAL ERROR OUTPUT FLAGS

There are internal error flags to signal whenever thermal protection is activated or over-current detection occurs on the CANL

or CANH pins (THERM-CUR bit). The errors are reported in the CAN register.

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

DEVICE FAULT OPERATION

Table 12 describes the relationship between device fault or warning and the operation of the VDD, V2, CAN, and HS interface.

Table 12. Fault/Warning

Fault/Warning

VDD

V2

CAN

HS

Battery Fail

Turn OFF

Turn OFF due to V2.

No communication

OFF

VDD Temperature

Pre-warning

Warning flag only.

Leave as is

No change

Turn OFF

No change

OFF

VDD Over-temperature

Turn OFF

Turn OFF due to V2.

No communication

VDD Over-current

VDD regulator enters linear Turn OFF if VDD under-

If V2 is OFF, turn OFF

and no communication

Turn OFF if VDD under-

voltage reset occurs

mode. VDD under-voltage

reset may occurs. VDD

over-temperature Pre-

warning or shutdown may

occur

voltage reset occurs

VDD Short-circuit

Watchdog Reset

VDD under-voltage reset

occurs. VDD over-

temperaturePre-warningor

shutdown may occur

Turn OFF

Turn OFF due to V2.

No communication

OFF

ON

Turn OFF due to V2.

No communication

V2LOW (e.g., V2 < 4.0 V)

HS Over-temperature

HS Over-current

No change

V2 out of range

No change

Turn OFF due to V2 low

No change

OFF

No change

HS over-temperature

may occur

VSUP LOW

No change

CAN Over-temperature

Disable. As soon as

temperature falls, CAN is

re-enabled automatically

(49)

CAN Over-current

CANH Short to GND

CANH Short to VDD

CANH Short to VSUP

CANL Short to GND

CANL Short to VDD

CANL Short to VSUP

Notes

No change

No change⁽⁵⁰⁾

No change

No communication⁽⁵¹⁾

Communication OK

No communication⁽⁵¹⁾

49. Refer to descriptions of CANH and CANL short to GND, VDD, and VSUP elsewhere in table.

50. Peak current 150 mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current

out of V2 is below 10 mA.

51. Over-current might be detected. THERM-CUR bit set in CAN register.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

45

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI INTERFACE AND REGISTER DESCRIPTION

DATA FORMAT DESCRIPTION

Figure 27 illustrates an 8-bit byte corresponding to the 8 bits in a SPI register. The first three bits are used to identify the

internal SBC register address. Bit 4 is a read/write bit. The last four bits are data sent from the MCU to the SBC or read back

from the 33742 to the MCU.

The state of the MISO has no significance during the write operation. However, during a read operation the final four bits of

MISO have meaning; namely, they contain the content of the accessed register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MISO

MOSI

A2

A1

A0 R/W D3

D2

D1

D0

Address

Data

Note Read operation: R/W bit = logic [0]

Write operation: R/W = logic [1]

:

Figure 27. Data Format Description.

Table 13. Possible Reset Conditions

Condition

Name

Definition

Power-ON Reset

33742 Reset

POR

NR2R

33742 Mode

Transition

Normal Request to Reset mode

Normal Request to Normal mode

Normal Request to Standby mode

Normal to Reset mode

NR2N

NR2STB

N2R

Standby to Reset mode

STB2R

STO2R

STO2NR

RESET

Stop to Reset mode

Stop to Normal Request

33742S in Reset mode

33742 Mode

REGISTER DESCRIPTIONS

The following tables in this section describe the SPI register list and register bit meaning. Register reset values are also

described, along with the reset condition. A reset condition is the condition causing the bit to be set at the reset value.

Table 14. List of Registers

Comment and Use

Formal Name

Register

MCR

Address

$000

and Link

Write

Read

Selection for Normal, Standby, Sleep,

Stop, and Debug modes

BATFAIL, general failure, VDD pre-

warning, and Watchdog flag

Mode Control Register (MCR)

on page 48

Configuration for reset voltage level, CAN Sleep and Stop modes

RCR

$001

Reset Control Register (RCR)

on page 49

CAN slew rate, Sleep and Wake-up

enable/disable modes, drive enable after

failure

CAN wake-up and CAN failure status bits

CAN

$010

CAN Register (CAN) on page

49

33742

Analog Integrated Circuit Device Data

46

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 14. List of Registers

HS (high side switch) control in Normal

and Standby mode

HS over-temperature bit, VSUP, and V2

LOW status

IOR

WUR

TIM

$011

$100

$101

Input/Output Register (IOR)

on page 50

Control of wake-up input polarity

Wake-up input and real time Lx input

state

on page 51

•

TIM1: Watchdog timing control, Watch-

dog Window (WDW) or Watchdog Tim-

eout (WTO) mode

CANL and TXD failure reporting

Timing Register (TIM1/2) on

page 52

TIM2: Cyclic Sense and Forced Wake-

up timing selection

Control HS periodic activation in Sleep

and Stop modes, Forced Wake-up mode

activation, CAN-INT mode selection

CANH and RXD failure reporting

Interrupt source

LPC

$110

$111

Low Power Control Register

(LPC) on page 54

Enable or Disable of Interrupts

INTR

Interrupt Register (INTR) on

page 56

NOTE: For SPI Operation

In case a low pulse is asserted by the device on the RST output pin during a SPI message,

the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:

Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command

before the expiration of the timeout (in Normal mode or Normal Request mode and if the

“Timeout watchdog” option is selected), or the SPI watchdog refresh command is performed

in the closed window (in Normal mode and if “Window watchdog” option is selected).

Case 2: V_DDundervoltage condition: V_DDfalls below the V_DDundervoltage threshold.

Message corruption means that the targeted register address can be changed, and another

register is written. Table 15 shows the various cases and impacts on SPI register address:

Table 15. Possible Corrupted Registers In Case of RST Pulse During SPI Communication

Resulting Written register

Register

Address

MCR

$000

RCR

$001

CAN

$010

IOR

$011

Target

written

register

Register

CAN

Address

$010

$011

$100

$101

$110

$111

X

IOR

X

WUR

TIM1/2

LPC

X

INTR

X

Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:

•

write to CAN register can end up as write to MCR register, or

write to TIM1 register can end up as write to RCR register

To avoid the previously described behavior, it is recommended to write into the MCR, RCR,

CAN, and IOR registers with the expected configuration, after each RST assertion.

In the application, a RST low pulse leads to an MCU reset and a software restart. By

applying this recommendation, all registers will be written with the expected configuration.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

MODE CONTROL REGISTER (MCR)

Tables 16 through 18 describes the various Mode Control Registers.

Table 16. Mode Control Register

MCR

R/W

D3

D2

D1

D0

$000b

W

R

–

MCTR2

VDDTEMP

0

MCTR1

GFAIL

MCTR0

WDRST

0

BATFAIL⁽⁵²⁾

Reset Value

Reset Condition (Write)⁽⁵³⁾

Notes

–

0

–

POR, RESET

52. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.

53. See Table 13 page 46, for definitions of reset conditions

Table 17. Mode Control Register Control Bits

MCTR MCTR MCTR

33742S Mode

Description

2

1

0

To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and

Software Debug with the 33742, page 34.

0

Enter/Exit Debug Mode

0

1

0

1

0

1

0

1

0

1

Normal

Standby

–

0

–

0

Stop, Watchdog OFF⁽⁵⁴⁾

Stop, Watchdog ON⁽⁵⁴⁾

Sleep⁽⁵⁵⁾

–

0

–

1

–

No Watchdog running. Debug mode.

1

Normal

Standby

1

Stop

Notes

54. Watchdog ON or OFF depends on RCR bit D3.

55. Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be

previously set to logic [1].

Table 18. Mode Control Register Status Bits

Name

Logic

Description

VSUP was not below V_BF

VSUP has been below V_BF

No over-temperature pre-warning.

.

0

1

0

1

0

1

0

1

BATFAIL

.

VDDTEMP

GFAIL

Temperature pre-warning on VDD regulator (bit latched).

No failure.

CAN Failure or HS over-temperature or V2 low.

No watchdog reset occurred.

WDRST

Watchdog reset occurred.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

48

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

RESET CONTROL REGISTER (RCR)

Tables 19 and 20 contain various Reset Control Register information.

Table 19. Reset Control Register

RCR

R/W

D3

D2

D1

D0

W

R

–

$001b

WDSTOP

1

NOSTOP

0

CAN SLEEP

RSTTH

Reset Value

Reset Condition (Write)⁽⁵⁶⁾

Notes

0

–

POR, RESET, STO2NR POR, NR2N, NR2STB

POR, NR2N, NR2STB

POR

56. See Table 13 page 46, for definitions of reset conditions.

Table 20. Reset Control Register Control Bits

Name

Logic

Description

No Watchdog in Stop mode.

Watchdog runs in Stop mode.

Device cannot enter Sleep mode.

0

1

0

1

0

1

0

1

WDSTOP

NOSTOP

CAN SLEEP

RSTTH

Sleep mode allowed. Device can enter Sleep mode.

CAN Sleep mode disable (despite D0 bit in CAN register).

CAN Sleep mode enabled (in addition to D0 in CAN register).

Reset Threshold 1 selected (typ 4.6 V).

Reset Threshold 2 selected (typ 4.2 V).

CAN REGISTER (CAN)

Tables 21 through 24 contain the information on the CAN register. Table 21 describes control of the high-speed CAN module,

mode, slew rate, and wake-up.

Table 21. CAN Register

CAN

R/W

D3

D2

D1

D0

W

R

–

CANCLR

CANWU

0

SC1

CAN-F

0

SC0

CAN-UF

0

MODE

THERM-CUR

1

$010b

Reset Value

Reset Condition (Write)⁽⁵⁷⁾

Notes

–

POR

NR2N, STB2N

57. See Table 13, page 46, for definitions of reset conditions.

Table 22. CANCLR Control Bits

Logic

Description

No effect.

0

1

Re-enables CAN driver after TXD permanent dominant or RXD permanent recessive failure occurred. Failure

recovery conditions must occur to re-enable.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

49

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HIGH-SPEED CAN TRANSCEIVER MODES

The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 23). SC0 bit (D1) defines the slew

rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is

in Sleep mode.

Table 23. CAN High Speed Transceiver Modes

CAN Mode

SC1

SC0

MODE

(Pass 1.1)

0

1

0

1

0

1

CAN TXRX, Slew Rate 0

CAN TXRX, Slew Rate 1

0

1

CAN TXRX, Slew Rate 2

1

CAN TXRX, Slew Rate 3

x

CAN Sleep and CAN Wake-up Disable

CAN Sleep and CAN Wake-up Enable

x

x = Don’t care.

Table 24. CAN Register Status Bits

Name

Logic

Description

No CAN wake-up occurred.

0

1

0

1

0

CANWU

CAN wake-up occurred.

No CAN failure.

CAN-F

CAN failure⁽⁵⁸⁾

Identified CAN failure⁽⁵⁸⁾

.

CAN-UF

Non-identified CAN failure.

1

0

1

No over-temperature or over-current on CANH or CANL drivers.

Over-temperature or over-current on CANH or CANL drivers.

THERM-CUR

Notes

58. Error bits are latched in the CAN register.

INPUT/OUTPUT REGISTER (IOR)

Tables 25 through 27 contain the Input/Output Register information. Table 26 provides information about information HS

control in Normal and Standby modes, while Table 27 provides status bit information.

Table 25. Input/Output Register

IOR

R/W

D3

D2

D1

D0

W

R

–

HSON

HSOT

0

–

$011b

V2LOW

VSUPLOW

DEBUG

Reset Value

Reset Condition (Write)⁽⁵⁹⁾

Notes

–

POR

59. See Table 13, page 46, for definitions of reset conditions.

33742

Analog Integrated Circuit Device Data

50

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 26. HSON Control Bits

Logic

HS State

HS OFF, in Normal and Standby modes.

HS ON, in Normal and Standby modes.⁽⁶⁰⁾

0

1

Notes

60. When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error

bits are latched in the IOR register.

Table 27. Input/Output Register Status Bits

Name

Logic

Description

V_2LTH> 4.0V.

0

1

0

1

0

1

0

1

V2LOW

V_2LTH< 4.0V.

No HS over-temperature.

HS over-temperature.

V_BF(EW)> 5.8V.

HSOT

VSUPLOW

DEBUG

V_BF(EW)< 5.8V.

SBC not in Debug mode.

SBC accepts command to go to Debug modes (no Watchdog).

WAKE-UP REGISTER (WUR)

Tables 28 through 30 contain the Wake-up Register information. Local wake-up inputs L0:L3 can be used in both Normal and

Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 28).

Table 28. Wake-up Register

WUR

R/W

D3

D2

D1

D0

W

R

–

LCTR3

L3WU

0

LCTR2

L2WU

0

LCTR1

L1WU

0

LCTR0

L0WU

0

$100b

Reset Value

Reset Condition (Write)⁽⁶¹⁾

Notes

–

POR, NR2R, N2R, STB2R, STO2R

61. See Table 13, page 46, for definitions of reset conditions.

Wake-up inputs can be configured by pair. L0 and L1 can be configured together, and L1 and L2, and L2 and L3 can be

configured together (Table 29).

Table 29. Wake-up Register Control Bits

LCTR3

LCTR2

LCTR1

LCTR0

L0 L1:L1 L2 Config

L2 L3:L3 L4 Config

x

0

1

0

1

0

1

Inputs Disabled

High Level Sensitive

Low Level Sensitive

Both Level Sensitive

–

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

51

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 29. Wake-up Register Control Bits (continued)

0

1

0

1

x

–

Inputs Disabled

High Level Sensitive

Low Level Sensitive

Both Level Sensitive

0

1

x = Don’t care.

Table 30. Wake-up Register Status Bits ⁽⁶²⁾

Name

Logic

Description

If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has

occurred.

L3WU

L2WU

L1WU

L0WU

0 or 1

When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW

or HIGH) (0 = Lx LOW, 1 = Lx HIGH)

Notes

62. WUR status bits have two functions. After SBC wake-up, they indicate the wake-up source; for example, L2WU set at logic [1] if wake-

up source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx

inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog timeout occurs before the

first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.

TIMING REGISTER (TIM1/2)

Tables 31 through 35 contain the Timing Register information. The TIM register is composed of two sub registers:

• TIM1—Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option

(Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 31). Watchdog timing characteristics are

described in Table 32.

• TIM2—Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on

or off. TIM2 is selected when bit D3 is 1 (Table 33). Figure 30, page 54, describes HS operation when cyclic sense is selected

Cyclic sense timing characteristics are described in Table 35, page 54.

Both subregisters also report the CANL and TXD diagnostics.

Table 31. TIM1 Timing and CANL Failure Diagnostic Register

TIM1

R/W

D3

D2

D1

D0

$101b

W

R

–

0

WDW

WDT1

WDT0

TXPD

CANL2VDD

CANL2BAT

CANL2GND

Reset Value

Reset Condition (Write)⁽⁶³⁾

Notes

–

0

–

POR, RESET

63. See Table 13, page 46, for definitions of reset conditions.

33742

Analog Integrated Circuit Device Data

52

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 32. TIM1 Control Bits

WDW

WDT1

WDT0

Timing (ms typ)

Parameter

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

9.75

45

Watchdog Period 1

Watchdog Period 2

Watchdog Period 3

Watchdog Period 4

Watchdog Period 1

Watchdog Period 2

Watchdog Period 3

Watchdog Period 4

No Window Watchdog

100

350

9.75

45

Watchdog Window enabled

(Window length is half the

Watchdog Timing).

100

350

Window Closed

No Watchdog Clear Allowed

Window Open for Watchdog Clear

Watchdog Timing x 50%

Watchdog Period

(Watchdog Timing Selected by TIM1 Bit WDW=1)

Figure 28. Window Watchdog

Window Open for Watchdog Clear

Watchdog Period

(Watchdog Timing Selected by TIM1 Bit WDW = 0)

Figure 29. Timeout Watchdog

Table 33. Timing Register Status Bits

Name

Logic

Failure Description

No CANL short to VDD.

0

1

0

1

0

1

0

1

CANL2VDD

CANL2BAT

CANL2GND

TXPD

CANL short to VDD.

No CANL short to VSUP.

CANL short to VSUP.

No CANL short to GND.

CANL short to GND.

No TXD dominant.

TXD dominant.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

53

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 34. TIM2 Timing and CANL Failure Diagnostic Register

TIM2

R/W

D3

D2

D1

D0

W

R

–

1

CSP2

CANL2BAT

0

CSP1

CANL2GND

0

CSP0

TXPD

$101b

CANL2VDD

Reset Value

Reset Condition (Write)⁽⁶⁴⁾

Notes

–

0

–

POR, RESET

64. See Table 13, page 46, for definitions of reset conditions.

Cyclic Sense Timing,

ON Time

HS ON

Cyclic Sense Timing, OFF Time

HS OFF

HS

10 s

Lx Sampling Point

Sample

time

Figure 30. HS Operation When Cyclic Sense Is Selected

Table 35. TIM2 Control Bits

Parameter

CSP2

CSP1

CSP0

Cyclic Sense Timing (ms)

Cyclic Sense/FWU Timing 1

Cyclic Sense/FWU Timing 2

Cyclic Sense/FWU Timing 3

Cyclic Sense/FWU Timing 4

Cyclic Sense/FWU Timing 5

Cyclic Sense/FWU Timing 6

Cyclic Sense/FWU Timing 7

Cyclic Sense/FWU Timing 8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4.6

9.25

18.5

37

74

95.5

191

388

LOW POWER CONTROL REGISTER (LPC)

Tables 36 through 40 contain the Low Power Control Register information. The LPC register controls:

• The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).

• Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is

defined by the TIM2 sub register).

• Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to

Reset Control Register (RCR) on page 49 for details of the LPC register setup required for proper cyclic sense or direct wake-

up operation.

The LPC register also reports the CANH and RXD diagnostic.

33742

Analog Integrated Circuit Device Data

54

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 36. Low Power Control Register

LPC

R/W

D3

D2

D1

D0

W

R

LX2HS

FWU

CAN-INT

HSAUTO

RXPR

$110b

CANH2VDD

CANH2BAT

CANH2GND

–

0

Reset Value

Reset Condition (Write)⁽⁶⁵⁾

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

Notes

65. See Table 13, page 46, for definitions of reset conditions.

Table 37. LX2HS Control Bits

Logic

Wake-up Inputs Supplied by HS

No.

Yes. Lx inputs sensed at sampling point.

0

1

Table 38. HSAUTO Control Bits

Logic

Auto-timing HS in Sleep and Stop modes

OFF.

ON, HS Cyclic, period defined in TIM2 subregister.

0

1

Table 39. CAN-INT Control Bits

Logic⁽⁶⁶⁾

Description

Interrupt as soon as CAN bus failure detected.

0

1

Interrupt when CAN bus failure detected and fully identified.

Notes

66. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by

SPI (refer to CAN Register (CAN) on page 49). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared

automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not

allow clearing the CAN-UF bit.

Table 40. LPC Status Bits

Name

Logic

Failure Description

No CANH short to V_DD

CANH short to V_DD

.

0

1

0

1

0

1

0

1

CANH2VDD

.

No CANH short to VSUP.

CANH short to VSUP.

No CANH short to GND.

CANH short to GND.

CANH2BAT

CANH2GND

RXPR

No RXD permanent recessive.

RXD permanent recessive.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

55

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

INTERRUPT REGISTER (INTR)

Tables 41 through 43 contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt

source. A read operation identifies the interrupt source. Table 43 provides status bit information. The status bits of the INTR

register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,

CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched

in the CAN register and the IOR register.

Table 41. Interrupt Register

INTR

R/W

D3

D2

HSOT-V2LOW

HSOT

D1

D0

(67)

VSUPLOW

V1TEMP

W

R

–

CANF

0

$111b

Reset Value

Reset Condition (Write)⁽⁶⁸⁾

Notes

0

–

POR, RST

67. If only HSOT-V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:

1. Bit D2 = 1: Interrupt source is HSOT.

2. Bit D2 = 0: Interrupt source is V2LOW.

HSOT and V2LOW bits status are available in the IOR register.

68. See Table 13, page 46, for definitions of reset conditions.

Table 42. Interrupt Register Control Bits

Name

Description

Mask bit for CAN failures.

CANF

Mask bit for VDD medium temperature (pre-warning).

Mask bit for HS over-temperature AND V_2LTH< 4.0 V.

Mask bit for V_BF(EW)< 5.8 V.

VDDTEMP

HSOT- V2LOW

VSUPLOW

When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode

due to over-current detection (I_DDS-WU1or I_DDS-WU2), an INT pulse is generated; however, INTR register content remains at 0000

(not bit set into the INTR register).

Table 43. Interrupt Register Status Bits

Name

Logic

Description

No V_BF(EW)< 5.8 V.

V_BF(EW)< 5.8 V.

0

1

0

1

0

1

0

1

VSUPLOW

No HS over-temperature.

HS over-temperature.

HSOT

VDDTEMP

CANF

No VDD medium temperature (pre-warning).

VDD medium temperature (pre-warning).

No CAN failure.

CAN failure.

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

56

TYPICAL APPLICATIONS

SBC POWER SUPPLY

The 33742 is supplied from the battery line. A serial diode is necessary to protect the device against negative transient pulses

and from reverse battery. This is illustrated in Figure 31.

V

Q1

PWR

V2

33742

VSUP Monitor

Dual Voltage Regulator

VDD Monitor

R5

D1

C1

V2CTRL

V2

V

SUP

C2

Rp

C10 C5

R1

VDD

to L1

C6

5.0V/200mA

Mode Control

SW1

C3

HS

Control

C4

Oscillator

HS

INT

Interrupt

Watchdog

Reset

WDOG

RST

L0

L1

L2

L3

Programmable

Wake-up Input

R2

to L1

MOSI

SCLK

MISO

CS

MCU

SPI Interface

SW2

SW3

C7

CANH

CANL

TXD

RXD

1.0 Mbps CAN

Physical Interface

GND

R3

Internal

Module

Supply

to L2

Rd

C8

C9

Safe Circuitry

SW4

Clamp (1)

to L3

R4

Connector

Legend

D1: Example: 1N4002 type

Q1: MJD32C

C2: 100 nF

C3: 47 F

C4: 100 nF

R1, R2, R3, R4: 10k

C5: 47 F tantalum or 100 F chemical

Rp, Rd: Example: 1.0k depending on switch type.

C6, C7, C8, C9, C10: 100 nF

R5: 2.2 k

C1: 10 F

(1) Clamp circuit to ensure max ratings for HS (HS from

-0.3V to V_SUP+0.3) are respected.

Figure 31. SBC Typical Application Schematic

VOLTAGE REGULATOR

The SBC contains two 5.0 V regulators: a V1 regulator, fully integrated and protected, and a V2 regulator, which operates with

an external ballast transistor.

VDD REGULATOR

The VDD regulator provides 5.0 V output, 2.0% accuracy with current capability of 200 mA max. It requires external decoupling

and stabilizing capacitors. The minimum recommended values are as follows:

• C4: 100 nF

• C3: 10 F < C3 <22 F, ESR < 1.0 or

• C3: 22 F < C3 <47 F, ESR < 5.0 or

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

57

TYPICAL APPLICATIONS

• C3: 47 F, ESR < 10 

V2 REGULATOR: OPERATING WITH EXTERNAL BALLAST TRANSISTOR

The V2 regulator is a tracking regulator of the VDD output. Its accuracy relative to VDD is ±1.0%. It requires external

decoupling and stabilizing capacitors.

The recommended value are as follows:

• 22 F, ESR < 5.0 

• 47 F, ESR < 10 

The V2 pin has two functions: it is a sense input for the V2 regulator and is a 5.0 V power supply input to the CAN interface.

With respect to ballast transistor selection, either PNP or PMOS transistors may be used. A resistor between base and emitter

(or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is

MJD32C.

V2 REGULATOR: OPERATION WITHOUT BALLAST TRANSISTOR

The external ballast transistor is optional. If the application does not requires more than the maximum output current capability

of the VDD regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well.

The electrical connection is illustrated in Figure 32.

No Connect

33742

V

PWR

V2CTRL

VSUP

V2

Components List

C1: 22 F

VDD

C2

C1

C3

C4

C2: 100 nF

V

DD

C3: >10 F

C4: 100 nF

RESET

RST

MCU

Figure 32. V2 Regulator Electrical Connection

FAILURE ON VDD, WDOG, RESET, AND INT PINS

The paragraphs below describe the behavior of the device and of the INT, RST, and WDOG pins at power-up and under failure

of the VDD regulator.

POWER-UP AND SBC ENTERING NORMAL OPERATION

After power-up the 33742 enters Normal Request mode (CAN interface is in TXRX mode): VDD is on and V2 is off.

After 350 ms if no watchdog is written (no TIM1 register write), a reset occurs and the 33742 returns to Normal Request mode.

During this sequence WDOG is active (low level).

Once watchdog is written, the 33742 goes to Normal mode: VDD is still on and V2 turns on, WDOG is no longer active, and

the RST pin is HIGH. If watchdog is not refreshed, the 33742 generates a reset and returns to Normal Request mode. Figure 33,

illustrates the operation.

33742

Analog Integrated Circuit Device Data

58

Freescale Semiconductor

TYPICAL APPLICATIONS

Missing Watchdog Refresh

Watchdog Refresh

VDD

SPI ^(CS)

Watchdog

Refresh

WD

RST

350ms

INT

SBC in Normal Request

& Reset modes

SBC in Normal

mode

SBC in Normal

Request & Reset

mode

SBC in

Reset

mode

Reset each 350 ms

Figure 33. Power up sequence, No W/D write at first

POWER UP AND VDD GOING LOW WITH STOP MODE AS DEFAULT LOW POWER MODE IS SELECTED

The first part of Figure 34 is identical to Figure 33. If VDD is pulled below VDD under-voltage reset (typ 4.6 V), say by an over-

current or short-circuit (for instance, short to 4.0 V), and if a low power mode previously selected was Stop mode, the 33742

enters Reset mode (RST pin is active). The WDOG pin stays HIGH, but the high level (Voh) follows V1 level. The INT pin goes

LOW.

When the VDD overload condition is removed, the 33742 restarts in Normal Request mode.

Under-voltage at VDD (VDD < V_RSTTH

)

Watchdog Refresh

VDD

350 ms

SPI ^(CS)

WD

RST

INT

SBC in

Reset

mode

SBC in Normal Request

& Reset modes

SBC in Normal

Reset mode

SBC in Normal

mode

Reset each 350 ms

Figure 34. Under-voltage on VDD

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

59

TYPICAL APPLICATIONS

POWER-UP AND VDD GOING LOW WITH SLEEP MODE AS DEFAULT LOW POWER MODE IS SELECTED

The first part of Figure 35 is identical to Figure 34. If VDD is pulled below the VDD under-voltage reset (typ 4.6 V), say by an

over-current or short-circuit (for instance, short to 4.0 V), and if the low power mode previously selected was Sleep mode and if

the BATFAIL flag has been cleared, the 33742 enters in Reset mode for a time period of 100 ms. The WDOG pin stays HIGH,

but the high level (VOH) follows VDD level. The RST and INT pins are low. After 100 ms the 33742 goes into Sleep mode, and

the VDD and V2 are off.

Figure 35 shows an example wherein VDD is shorted to 4.0 V, and after 100 ms the 33742 enters Sleep mode.

.

Under-voltage at VDD

Watchdog Refresh

VDD

SPI ^(CS)

100 ms

WD

RST

Reset mode

INT

SBC in Sleep mode

SBC in

Reset

mode

SBC in Normal Request

& Reset modes

SBC in Normal

mode

SBC in Reset mode for

100ms, then enter

Sleep mode

Reset each 350 ms

Figure 35. Under-voltage at VDD. Sleep mode selected.

CANH (33742)

CANL (33742)

CANH

CH

CL

R5

CANL

CAN Connector

Legend

R5: 60 

CL, CH: 220 pF

Figure 36. CAN Bus Standard Termination

CANH

CANH (33742)

CANL (33742)

Legend

R6, R7: 30 

CL, CH: 220 pF

CS: > 470 pF

R6

R7

CH

CL

CANL

CAN Connector

CS

Figure 37. CAN Bus Split Termination

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

PACKAGING

PACKAGE AND THERMAL CONSIDERATIONS

PACKAGING

PACKAGE AND THERMAL CONSIDERATIONS

The 33742 SBC is a standard surface mount 28-pin SOIC wide body. In order to improve the thermal performances of the

SOIC package, eight of the 28 pins are internally connected to the package lead frame for heat transfer to the printed circuit

board.

PACKAGING DIMENSIONS

Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the

98ASB42345B drawing number below. Dimensions shown are provided for reference ONLY.

EG SUFFIX (PB-FREE)

28-LEAD SOICW

98ASB42345B

ISSUE G

33742

Analog Integrated Circuit Device Data

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61

PACKAGING

PACKAGING DIMENSIONS

EG SUFFIX (PB-FREE)

28-LEAD SOICW

98ASB42345B

ISSUE G

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

PACKAGING

PACKAGING DIMENSIONS

EP SUFFIX (PB-FREE)

48-LEAD QFN

98ASA10825D

ISSUE 0

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

63

PACKAGING

PACKAGING DIMENSIONS

EP SUFFIX (PB-FREE)

48-LEAD QFN

98ASA10825D

ISSUE 0

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

PACKAGING

PACKAGING DIMENSIONS

EP SUFFIX (PB-FREE)

48-LEAD QFN

98ASA10825D

ISSUE 0

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

65

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

33742SOICW

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum is provided as a supplement to the MC33742

technical datasheet. The addendum provides thermal performance

information that may be critical in the design and development of system

applications. All electrical, application, and packaging information is

provided in the data sheet.

28-PIN SOICW

Packaging and Thermal Considerations

The MC33742 is offered in a 28 pin SOICW exposed pad, single die

package. There is a single heat source (P), a single junction temperature

(T_J), and thermal resistance (R_JA).

T_J

.

=

R_JA

P

EG SUFFIX (PB-FREE)

98ASB42345B

The stated values are solely for a thermal performance comparison of

one package to another in a standardized environment. This methodology

is not meant to and will not predict the performance of a package in an

application-specific environment. Stated values were obtained by

measurement and simulation according to the standards listed below.

28-PIN SOICW

Note For package dimensions, refer to

98ASB42345B.

Standards

Table 44. Thermal Performance Comparison

Thermal Resistance

[C/W]

41

(1), (2)

R

JA

JB

JA

JC

(2), (3)

(1), (4)

(5)

10

68

220

Notes:

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-7.

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

4. Single layer thermal test board per JEDEC JESD51-3.

5. Thermal resistance between the die junction and the

package top surface; cold plate attached to the package top

surface and remaining surfaces insulated.

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Freescale Semiconductor

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

1.0

0.2

1.0

0.2

* All measurements

are in millimeters

28 Pin SOICW

1.27 mm Pitch

16.0 mm x 7.5 mm Body

Figure 38. Surface Mount for SOIC Wide Body non-Exposed Pad

1

28

RXD

TXD

VDD

RST

INT

GND

V2

WDOG

CS

2

27

26

25

24

23

22

21

20

19

18

17

16

15

3

MOSI

MISO

SCLK

GND

CANL

CANH

L3

4

A

5

6

7

8

9

10

11

12

13

14

V2CTRL

VSUP

HS

L2

L1

L0

33742 Pin Connections

28-Pin SOICW

1.27 mm Pitch

18.0 mm x 7.5 mm Body

Figure 39. Thermal Test Board

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

67

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

Device on Thermal Test Board

Material:

Single layer printed circuit board

FR4, 1.6 mm thickness

Cu traces, 0.07 mm thickness

Outline:

80 mm x 100 mm board area,

including edge connector for thermal

testing

Area A:

Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

Table 45. Thermal Resistance Performance

R_θJA[°C/W]

[mm²]

0

300

600

A

68

52

47

R_JAis the thermal resistance between die junction and ambient air.

80

70

60

50

40

30

x

R_

JA

20

10

0

300

Heat spreading area [mm²]

600

A

Figure 40. Device on Thermal Test Board R_JA

33742

Analog Integrated Circuit Device Data

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Freescale Semiconductor

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

100

10

1

x

R_JA

0.1

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

Time[s]

Figure 41. Transient Thermal Resistance R_{ A,}

J

1 W Step response, Device on Thermal Test Board Area A = 600 (mm²)

33742

Analog Integrated Circuit Device Data

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69

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Converted to Freescale format

Implemented Revision History page

2/2006

3

•

Added Thermal Addendum (Rev. 1.0)

Changed Data Sheet from “Advanced” to “Final”

6/2006

4

8/2006

•

Added MCZ33742EG/R2 and MCZ33742SEG/R2 to the Ordering Information block

5

6

Replaced label for Logic Inputs to Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and

INT) on page 7

•

Removed all references to the 54 pin package.

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum

Ratings on page 7. Added note with instructions from www.freescale.com.

10/2006

2/2007

7

8

•

Revised () and (),

Restated notes in Maximum Ratings on page 7

3/2007

5/2007

•

Text corrections to the included thermal addendum

9

•

Added EP 48 pin QFN package

Added 98ARH99048A Package drawing

Added PCZ33742EP/R2 to the ordering information

10

•

Made changes defining RXD as a push-pull structure on page 15, 22, 38, and 39

Updated figures Figure 12 and Figure 25

Added provisions of differentiation for 28-pin SOIC and 48-pin QFN for ESD Capability, Human Body

Model⁽¹⁾on page 7, Watchdog Period Normal and Standby Modes on page 17, and Normal Request

Mode Timeout on page 17

6/2008

11

•

Update the Freescale format and style to the current standards

Added the Functional Internal Block Description section

Changed PCZ33742EP/R2 to MC33742EP/R2 in the ordering information

2/2011

7/2011

•

Added MC33742PEG/R2, MC33742SPEG/R2, and MC33742PEP/R2 to the ordering information

12.0

13.0

•

Updated Freescale form and style

Removed MCZ33742EG/R2, MC33742SDW/R2, MCZ33742SEG/R2, and MCZ33742EP/R2 from the

ordering information

•

Added a For SPI Operation on page 47

Updated document properties.

6/2013

14.0

33742

Analog Integrated Circuit Device Data

70

Freescale Semiconductor

Information in this document is provided solely to enable system and software implementers to use Freescale products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no

warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any

and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by

customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.

Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:

freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their

respective owners.

Document Number: MC33742

Rev. 14.0

6/2013


型号：	MC33742PEG/R2
厂家：	NXP
描述：	SPECIALTY TELECOM CIRCUIT, PDSO28, ROHS COMPLIANT, MS-013AE, WSOIC-28 电信光电二极管电信集成电路
文件：	总71页 (文件大小：2011K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33742PEG/R2 [NXP]

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MC33742SDWR2

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MC3374FTB