MC33771BSB1AE [NXP]
Battery cell controller IC;型号: | MC33771BSB1AE |
厂家: | NXP |
描述: | Battery cell controller IC 电池 |
文件: | 总29页 (文件大小:563K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC33771B_SDS
Battery cell controller IC
Rev. 6.0 — 22 June 2020
Product short data sheet
1 General description
The 33771 is a SMARTMOS lithium-ion battery cell controller IC designed for automotive
applications, such as hybrid electric (HEV) and electric vehicles (EV) along with industrial
applications, such as energy storage systems (ESS) and uninterruptible power supply
(UPS) systems.
The device performs ADC conversions of the differential cell voltages and current, as well
as battery coulomb counting and battery temperature measurements. The information is
digitally transmitted through the Serial Peripheral Interface (SPI) or Transformer Isolation
(TPL) to a microcontroller for processing.
2 Features
• 9.6 V ≤ VPWR ≤ 61.6 V operation, 75 V transient
• 7 to 14 cells management
• Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI
• Addressable on initialization
• 0.8 mV maximum total voltage measurement error
• Synchronized cell voltage/current measurement with coulomb count
• Total stack voltage measurement
• Seven GPIO/temperature sensor inputs
• 5.0 V at 5.0 mA reference supply output
• Automatic over/undervoltage and temperature detection routable to fault pin
• Integrated sleep mode over/undervoltage and temperature monitoring
• Onboard 300 mA passive cell balancing with diagnostics
• Hot plug capable
• Detection of internal and external faults, as open lines, shorts, and leakages
• Designed to support ISO 26262, up to ASIL D safety system
• Fully compatible with the MC33772 for a maximum of six cells
• Qualified in compliance with AEC–Q100
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
3 Simplified application diagram
RDTX_OUT+
VCOM
RDTX_OUT-
VCOM
VPWR1
VPWR2
CT14
CGND
battery
reference
CB14
VANA
AGND
DGND
+
battery
reference
CB14:13_C
CT13
FAULT
CTn
CBn
SDA
14 cell
voltage
measure
EEPROM
(OPTIONAL)
SCL
MCU
SPI_COM_EN
FAULT
VCOM
CT1
CB2:1_C
CB1
GPIOy
MC33771
GPIOx
CSB
RESET
+
CSB
MISO
MOSI
SCLK
SO
CTREF
SI/RDTX_IN+
SCLK/RDTX_IN-
battery reference GNDREF
GNDFLG
VCOM
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
ISENSE+
ISENSE-
current
measure
battery
reference
aaa-027844
Figure 1.ꢀSimplified application diagram, SPI use case
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
2 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
RDTX_OUT+
RDTX_OUT-
VCOM
VPWR1
VPWR2
CT14
VCOM cluster # 2
CGND
VANA
cluster # 2
reference
CB14
CB14:13_C
CT13
+
AGND
DGND
FAULT
SDA
cluster # 2
reference
CTn
CBn
14 cell
voltage
EEPROM
(OPTIONAL)
SCL
measure
SO
CT1
CB2:1_C
CB1
CSB
MC33771
SPI_COM_EN
RESET
SI/RDTX_IN+
cluster # 2
reference
+
T1
CTREF
SCLK/RDTX_IN-
GPIO0
GNDREF
GNDFLG
cluster # 2
reference
VCOM cluster # 2
GPIO1
ISENSE+
GPIO2
GPIO3
GPIO4
ISENSE-
GPIO5
GPIO6
cluster # 2
reference
RDTX_OUT+
RDTX_OUT-
VCOM
V
V
PWR1
PWR2
VCOM cluster # 1
CT14
CB14
CB14:13_C
CT13
CGND
VANA
cluster # 1
reference
+
AGND
DGND
FAULT
SDA
cluster # 1
reference
CTn
CBn
14 cell
voltage
measure
BATTERY PACK
CONTROLLER
EEPROM
(OPTIONAL)
SCL
CT1
CB2:1_C
CB1
SO
CSB
MC33771
+
SPI_COM_EN
RESET
SI/RDTX_IN+
cluster # 1
reference
MCU
T1
CTREF
T1
SPI1
MC33664
SCLK/RDTX_IN-
GPIO0
SPI2
GNDREF
GNDFLG
VCOM cluster # 1
cluster # 1
reference
GPIO1
GPIO2
ISENSE+
ISENSE-
GPIO3
GPIO4
current
measure
GPIO5
GPIO6
cluster # 1
reference
aaa-027845
Figure 2.ꢀSimplified application diagram, TPL use case
4 Applications
• Automotive: 48 V and high-voltage battery packs
• E-bikes, e-scooters
• Energy storage systems
• Uninterruptible power supply (UPS)
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
3 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
5 Ordering information
5.1 Part numbers definition
MC33771B xꢁyꢁzꢁAE/R2
Table 1.ꢀPart number breakdown
Code
Option
Description
S
T
x = S (SPI communication type)
x = T (TPL communication type)
y = A (Advanced)
x
A
y
z
B
y = B (Basic)
P
y = P (Premium)
1
z = 1 (7 to 14 channels)
z = 2 (7 to 8 channels)
Package suffix
2
AE
R2
Tape and reel indicator
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
4 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
5.2 Part numbers list
This section describes the part numbers available to be purchased along with their
differences. Valid orderable part numbers are provided on the web. To determine the
orderable part numbers for this device, go to http://www.nxp.com.
Table 2.ꢀAdvanced orderable part table
Temperature range is −40 to 105 °C
Package type is 64-pin LQFP-EP
Orderable part
Number of
channels
OV/UV
Precision GPIO as temperature
channels and OT/UT
Current channel or
coulomb count
SPI communication protocol
MC33771BSA1AE
MC33771BSA2AE
7 to 14
7 to 8
Yes
Yes
Yes
Yes
No
No
TPL differential communication protocol
MC33771BTA1AE
MC33771BTA2AE
7 to 14
7 to 8
Yes
Yes
Yes
Yes
No
No
Table 3.ꢀBasic orderable part table
Temperature range is −40 to 105 °C
Package type is 64-pin LQFP-EP
Orderable part
Number of
channels
OV/UV
Precision GPIO as temperature
channels and OT/UT
Current channel or
coulomb count
SPI communication protocol
MC33771BSB1AE
MC33771BSB2AE
7 to 14
7 to 8
Yes
Yes
No
No
No
No
TPL differential communication protocol
MC33771BTB1AE
MC33771BTB2AE
7 to 14
7 to 8
Yes
Yes
No
No
No
No
Table 4.ꢀPremium orderable part table
Temperature range is −40 to 105 °C
Package type is 64-pin LQFP-EP
Orderable part
Number of
channels
OV/UV
Precision GPIO as temperature
channels and OT/UT
Current channel or
coulomb count
SPI communication protocol
MC33771BSP1AE
MC33771BSP2AE
7 to 14
7 to 8
Yes
Yes
Yes
Yes
Yes
Yes
TPL differential communication protocol
MC33771BTP1AE
MC33771BTP2AE
7 to 14
7 to 8
Yes
Yes
Yes
Yes
Yes
Yes
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
5 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
6 Pinning information
6.1 Pinout diagram
terminal 1
index area
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VPWR2
VPWR1
CT_14
RDTX_OUT+
SI/RDTX_IN+
SCLK/RDXT_IN-
RDTX_OUT-
CGND
3
4
CB_14
5
CB_14:13C
CB_13
6
VCOM
7
CT_13
SO
8
CT_12
CSB
65
9
CB_12
FAULT
GNDFLAG
10
11
12
13
14
15
16
CB_12:11_C
CB_11
SPI_COM_EN
CT_REF
CT_1
CT_11
CT_10
CB_1
CB_10
CB_2:1_C
CB_2
CB_10:9_C
CB_9
CT_2
aaa-027847
Transparent top view
Figure 3.ꢀPinout diagram
6.2 Pin definitions
Table 5.ꢀPin definitions
Number
Name
Function
Definition
1
2
3
4
VPWR2
VPWR1
CT_14
CB_14
Input
Input
Input
Output
Power input to the 33771
Power input to the 33771
Cell pin 14 input. Terminate to LPF resistor.
Cell balance driver. Terminate to cell 14 cell
balance load resistor.
5
6
CB_14:13_C
CB_13
Output
Output
Cell balance 14:13 common. Terminate to
cell 14 and 13 common pin.
Cell balance driver. Terminate to cell 13 cell
balance load resistor.
7
8
CT_13
CT_12
Input
Input
Cell pin 13 input. Terminate to LPF resistor.
Cell pin 12 input. Terminate to LPF resistor.
MC33771BSDS
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Product short data sheet
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6 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Number
Name
Function
Definition
9
CB_12
Output
Cell balance driver. Terminate to cell 12 cell
balance load resistor.
10
11
CB_12:11_C
CB_11
Output
Output
Cell balance 12:11 common. Terminate to
cell 12 and 11 common pin.
Cell balance driver. Terminate to cell 11 cell
balance load resistor.
12
13
14
CT_11
CT_10
CB_10
Input
Cell pin 11 input. Terminate to LPF resistor.
Cell pin 10 input. Terminate to LPF resistor.
Input
Output
Cell balance driver. Terminate to cell 10 cell
balance load resistor.
15
16
CB_10:9_C
CB_9
Output
Output
Cell balance 10:9 common. Terminate to cell
10 and 9 common pin.
Cell balance driver. Terminate to cell 9 cell
balance load resistor.
17
18
19
CT_9
CT_8
CB_8
Input
Cell pin 9 input. Terminate to LPF resistor.
Cell pin 8 input. Terminate to LPF resistor.
Input
Output
Cell balance driver. Terminate to cell 8 cell
balance load resistor.
20
21
CB_8:7_C
CB_7
Output
Output
Cell balance 8:7 common. Terminate to cell 8
and 7 common pin.
Cell balance driver. Terminate to cell 7 cell
balance load resistor.
22
23
24
CT_7
CT_6
CB_6
Input
Cell pin 7 input. Terminate to LPF resistor.
Cell pin 6 input. Terminate to LPF resistor.
Input
Output
Cell balance driver. Terminate to cell 6 cell
balance load resistor.
25
26
CB_6:5_C
CB_5
Output
Output
Cell balance 6:5 common. Terminate to cell 6
and 5 common pin.
Cell balance driver. Terminate to cell 5 cell
balance load resistor.
27
28
29
CT_5
CT_4
CB_4
Input
Cell pin 5 input. Terminate to LPF resistor.
Cell pin 4 input. Terminate to LPF resistor.
Input
Output
Cell balance driver. Terminate to cell 4 cell
balance load resistor.
30
31
CB_4:3_C
CB_3
Output
Output
Cell balance 4:3 common. Terminate to cell 4
and 3 common pin.
Cell balance driver. Terminate to cell 3 cell
balance load resistor.
32
33
34
CT_3
CT_2
CB_2
Input
Cell pin 3 input. Terminate to LPF resistor.
Cell pin 2 input. Terminate to LPF resistor.
Input
Output
Cell balance driver. Terminate to cell 2 cell
balance load resistor.
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
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7 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Number
Name
Function
Definition
35
CB_2:1_C
Output
Cell Balance 2:1 common. Terminate to cell 2
and 1 common pin.
36
CB_1
Output
Cell balance driver. Terminate to cell 1 cell
balance load resistor.
37
38
39
CT_1
Input
Input
Input
Cell pin 1 input. Terminate to LPF resistor.
Cell pin REF input. Terminate to LPF resistor.
CT_REF
SPI_COM_EN
SPI communication enable, pin must be high
for the SPI to be active
40
FAULT
Output
Fault output dependent on user defined
internal or external faults. If not used, it must
be left open.
41
42
43
CSB
SO
Input
SPI chip select
Output
Output
SPI serial output
VCOM
Communication regulator output. Decouple
with 2.2 µF ceramic.
44
CGND
Ground
I/O
Communication decoupling ground.
Terminate to GNDREF
45
46
47
RDTX_OUT-
Receive/transmit output negative
SCLK/RDTX_IN- I/O
SPI clock or receive/transmit input negative
SI/RDTX_IN+
I/O
SPI serial input or receiver/transmit input
positive
48
49
RDTX_OUT+
GPIO0
I/O
I/O
Receive/transmit output positive
General purpose analog input or GPIO or
wake-up or fault daisy chain
50
51
GPIO1
GPIO2
I/O
I/O
General purpose analog input or GPIO
General purpose analog input or GPIO or
conversion trigger
52
53
54
55
56
57
58
59
60
GPIO3
GPIO4
GPIO5
GPIO6
ISENSE+
ISENSE-
AGND
I/O
General purpose analog input or GPIO
General purpose analog input or GPIO
General purpose analog input or GPIO
General purpose analog input or GPIO
Current measurement input+
I/O
I/O
I/O
Input
Input
Ground
Ground
Output
Current measurement input−
Analog ground, terminate to GNDREF
Digital ground, terminate to GNDREF
DGND
VANA
Precision ADC analog supply. Decouple with
ceramic 47 nF ceramic capacitor to AGND.
61
62
SCL
SDA
I/O
I/O
I2C clock
I2C data
MC33771BSDS
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Product short data sheet
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8 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Number
Name
Function
Definition
63
RESET
Input
RESET is an active high input. RESET has
an internal pull down. If not used, it can be
tied to GND.
64
65
GNDREF
Ground
Ground
Ground reference for device. Terminate to
reference of battery cluster.
GNDFLAG
Device flag. Terminate to lowest potential of
battery cluster.
7 General product characteristics
7.1 Ratings and operating requirements relationship
The operating voltage range pertains to the VPWR pins referenced to the AGND pins.
Table 6.ꢀRatings vs. operating requirements
Fatal range
Handling range – no permanent failure
Fatal range
• Permanent
failure might
occur
• Permanent
failure might
occur
Lower limited operating range Normal operating range Upper limited operating range
• No permanent failure,
but IC functionality is not
guaranteed
• 100 % functional
• IC parameters might be out
of specification
• Detection of VPWR
overvoltage is functional
VPWR < −0.3 V 7.6 V ≤ VPWR < 9.6 V
Reset range:
9.6 V ≤ VPWR ≤ 61.6 V
61.6 V < VPWR ≤ 75 V
75 V < VPWR
–0.3 V ≤ VPWR < 7.6 V
In both upper and lower limited operating range, no information can be provided about IC
performance. Only the detection of VPWR overvoltage is guaranteed in the upper limited
operating range.
Performance in normal operating range is guaranteed only if there is a minimum of seven
battery cells in the stack.
7.2 Maximum ratings
Table 7.ꢀMaximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Symbol
Description (rating)
Min
Max
Unit
Electrical ratings
VPWR1, VPWR2
CT14
Supply input voltage
−0.3
−0.3
−10
−0.3
—
75
V
Cell terminal voltage
75
V
VPWR to CT14
CTN to CTN-1
CTN(CURRENT)
Voltage across VPWR1,2 pins pair and CT14 pin
Cell terminal differential voltage
Cell terminal input current
10.5
6.0
±500
10
V
[1]
V
µA
V
CBN to CBN:N-1_C
CBN:N-1_C to CBN-1
Cell balance differential voltage
—
CBN-1_C to CTn-1
Cell balance input to cell terminal input
−10
+10
V
MC33771BSDS
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Product short data sheet
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NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
VISENSE
VCOM
Description (rating)
Min
−0.3
—
Max
2.5
Unit
V
ISENSE+ and ISENSE– pin voltage
Maximum voltage may be applied to VCOM pin from external
source
5.8
V
VANA
VGPIO0
VGPIOx
Maximum voltage may be applied to VANA pin
GPIO0 pin voltage
—
3.1
6.5
V
V
V
–0.3
–0.3
GPIOx pins (x = 1 to 6) voltage
VCOM +
0.5
VDIG
Voltage I2C pins (SDA, SCL)
–0.3
VCOM +
0.5
V
VRESET
VCSB
VSPI_COMM_EN
VSO
RESET pin
CSB pin
–0.3
–0.3
–0.3
–0.3
6.5
6.5
6.5
V
V
V
V
SPI_COMM_EN
SO pin
VCOM +
0.5
VGPIO5,6
Maximum voltage for GPIO5 and GPIO6 pins used as current
input
−0.3
2.5
V
FAULT
VCOMM
Maximum applied voltage to pin
−0.3
7.0
V
V
Maximum voltage to pins RDTX_OUT+, RDTX_OUT–, SI/RDTX_
IN+, CLK/RDTX_IN–
−10.0
10.0
fSPI
SPI frequency (SPI mode)
—
4.2
2.1
4.2
MHz
Mbps
MHz
V
BRTPL
fTPL
Transformer communication bit rate (TPL mode)
Transformer signal frequency (TPL mode)
1.9
3.8
VESD
ESD voltage
Human body model (HBM)
Charge device model (CDM)
Charge device model corner pins (CDM)
—
—
—
±2000
±500
±750
[2]
VESD
ESD voltage (VPWR1, VPWR2, CTx, CBx, GPIOx, ISENSE+,
ISENSE−, RDTX_OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/
RDTX_IN−)
V
V
—
±4000
Human body model (HBM)
VESD
ESD voltage (CTREF, CTx, CBx, GPIOx, ISENSE+, ISENSE−,
RDTX_OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−)
IEC 61000-4-2, Unpowered (Gun configuration: 330Ω / 150pF)
HMM, Unpowered (Gun configuration: 330Ω / 150pF)
—
—
—
—
±8000
±8000
±8000
±8000
ISO 10605:2009, Unpowered (Gun configuration: 2 kΩ / 150pF)
ISO 10605:2009, Powered (Gun configuration: 2 kΩ / 150pF)
[1] Adjacent CT pins may experience an overvoltage that exceeds their maximum rating during OV/UV functional verification test or during open line
diagnostic test. Nevertheless, the IC is completely tolerant to this special situation.
[2] ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM) (CZAP
4.0 pF).
=
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
10 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
7.3 Thermal characteristics
Table 8.ꢀThermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Symbol
Description (rating)
Min
Max
Unit
Thermal ratings
Operating temperature
Ambient
°C
TA
TJ
−40
−40
+105
+150
Junction
TSTG
Storage temperature
−55
—
+150
260
°C
°C
[1]
[2]
TPPRT
Peak package reflow temperature
Thermal resistance and package dissipation ratings
[3]
RΘJB
RΘJA
RΘJA
Junction-to-board (bottom exposed pad soldered to board) 64
LQFP EP
—
—
—
10
59
27
°C/W
°C/W
°C/W
[4]
[5]
Junction-to-ambient, natural convection, single-layer board (1s) 64
LQFP EP
[4]
[5]
Junction-to-ambient, natural convection, four-layer board (2s2p) 64
LQFP EP
[6]
[7]
[8]
RΘJCTOP
RΘJCBOTTOM
ΨJT
Junction-to-case top (exposed pad) 64 LQFP EP
Junction-to-case bottom (exposed pad) 64 LQFP EP
Junction to package top, natural convection
—
—
—
14
0.97
3
°C/W
°C/W
°C/W
[1] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
[2] NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture
Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts
(MC33xxxD enter 33xxx), and review parametrics.
[3] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board
near the package.
[4] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
[5] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
[6] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1), with the cold plate
temperature used for the case temperature.
[7] Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
[8] Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2.
When Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT.
7.4 Electrical characteristics
Table 9.ꢀStatic and dynamic electrical characteristics
Characteristics noted under conditions 9.6 V ≤ VPWR ≤ 61.6 V, −40 °C ≤ TA ≤ 105 °C, GND = 0 V, unless otherwise stated.
Typical values refer to VPWR = 56 V, TA = 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Power management
VPWR(FO)
Supply voltage
V
Full parameter specification
9.6
—
61.6
MC33771BSDS
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Product short data sheet
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NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
IVPWR
Supply current (base value)
mA
Normal mode, cell balance OFF, ADC inactive, SPI
communication inactive, IVCOM = 0 mA
—
—
5.4
8.0
—
—
Normal mode, cell balance OFF, ADC inactive, TPL
communication inactive, IVCOM = 0 mA
IVPWR(TPL_TX)
IVPWR(CBON)
IVPWR(ADC)
Supply current adder when TPL communication active
Supply current adder to set all 14 cell balance switches ON
—
—
50
—
—
mA
mA
mA
0.97
Delta supply current to perform ADC conversions (addend)
ADC1-A,B continuously converting
—
—
3.0
1.4
—
—
ADC2 continuously converting
IVPWR(SS)
Supply current in sleep mode and in idle mode, communication
µA
inactive, cell balance off, cyclic measurement off, oscillator monitor
on
SPI mode (25 °C)
—
40
—
TPL mode (25 °C)
—
—
—
—
—
—
—
68
5
—
—
—
—
—
—
—
IVPWR(CKMON)
VPWR(OV_FLAG)
VPWR(LV_FLAG)
VPWR(UV_POR)
VPWR(HYS)
Clock monitor current consumption
VPWR overvoltage fault threshold (flag)
VPWR low-voltage warning threshold (flag)
VPWR undervoltage shutdown threshold (POR)
VPWR UV hysteresis voltage
µA
V
65
12
8.5
200
50
V
V
mV
µs
tVPWR(FILTER)
VCOM power supply
VCOM
VPWR OV, LV filter
VCOM output voltage
—
—
—
—
—
—
5.4
65
—
5.0
—
—
V
IVCOM
VCOM output current allocated for external use
VCOM undervoltage fault threshold
VCOM undervoltage hysteresis
VCOM undervoltage fault timer
VCOM fault retry timer
5.0
—
mA
V
VCOM(UV)
4.4
100
10
VCOM_HYS
—
mV
µs
ms
V
tVCOM(FLT_TIMER)
tVCOM(RETRY)
VCOM(OV)
—
10
—
VCOM overvoltage fault threshold
VCOM current limit
—
5.9
140
—
ILIM(OC)
—
mA
kΩ
RVCOM(SS)
VCOM sleep mode pull-down resistor
2.0
VANA power supply
VANA
VANA output voltage (not used by external circuits)
Decouple with 47 nF X7R 0603 or 0402
V
—
—
—
—
—
—
5.0
—
—
2.65
2.4
50
—
—
—
—
—
—
10
—
100
VANA(UV)
VANA undervoltage fault threshold
VANA undervoltage hysteresis
VANA undervoltage fault timer
VANA overvoltage fault threshold
VANA fault retry timer
V
VANA_HYS
mV
µs
V
VANA(FLT_TIMER)
VANA(OV)
tVANA(RETRY)
ILIM(OC)
RVANA_RPD
tVANA
11
2.8
10
ms
mA
kΩ
µs
VANA current limit
—
VANA sleep mode pull-down resistor
VANA rise time (CL = 47 nF ceramic X7R only)
1.0
—
ADC1-A, ADC1-B
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
12 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
CTn(LEAKAGE)
Cell terminal input leakage current (except in SLEEP mode when cell
balancing is ON)
—
10
—
nA
CTn(FV)
Cell terminal input current - functional verification
Cell terminal input current during conversion
Cell terminal open load detection pull-down resistor
VPWR terminal measurement resolution
—
0.365
50
—
mA
CTN
—
—
nA
RPD
—
950
—
Ω
VVPWR_RES
VVPWR_RNG
VPWRTERM_ERR
VCT_RNG
VCT_ANx_RES
VERR33RT
VERR
—
2.44141
—
—
mV/LSB
VPWR terminal measurement range
9.6
−0.5
0.0
—
75
0.5
4.85
—
V
VPWR terminal measurement accuracy
—
%
ADC differential input voltage range for CTn to CTn-1
Cell voltage and ANx resolution in 15-bit MEAS_xxxx registers
Cell voltage measurement error VCELL = 3.3 V, TA = 25 °C
Cell voltage measurement error
—
V
152.58789
±0.4
µV/LSB
mV
mV
−0.8
0.8
0.1 V ≤ VCELL ≤ 4.8 V, −40 °C ≤ TA ≤ 105 °C (or −40 °C ≤ TJ ≤
125 °C)
—
—
—
—
—
—
±0.7
±0.4
±0.4
±0.5
±0.7
±0.7
—
—
—
—
—
—
VERR_1
VERR_2
VERR_3
VERR_4
VERR_5
VANx_ERR
Cell voltage measurement error
mV
mV
mV
mV
mV
mV
0 V ≤ VCELL ≤ 1.5 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤
85 °C)
Cell voltage measurement error
1.5 V ≤ VCELL ≤ 2.7 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤
85 °C)
Cell voltage measurement error
2.7 V ≤ VCELL ≤ 3.7 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤
85 °C)
Cell voltage measurement error
3.7 V ≤ VCELL ≤ 4.3 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤
85 °C)
Cell voltage measurement error
1.5 V ≤ VCELL ≤ 4.5 V, −40 °C ≤ TA ≤ 105 °C (or −40 °C ≤ TJ ≤
125 °C)
Magnitude of ANx error in the entire measurement range:
Ratiometric measurement
—
—
—
—
16
10
Absolute measurement after soldering and aging, input in the
range [1.0, 4.5] V
Absolute measurement after soldering and aging, input in the
range [0, 4.85] V, for −40 °C < TA < 60 °C)
−8.0
−11
—
—
8.0
11
Absolute measurement after soldering and aging, input in the
range [0, 4.85] V, for −40 °C < TA < 105 °C)
tVCONV
Single channel net conversion time
13-bit resolution
µs
—
—
—
—
6.77
—
—
—
—
14-bit resolution
9.43
15-bit resolution
14.75
25.36
16-bit resolution
VV_NOISE
Conversion noise
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
µVrms
—
—
—
—
1800
1000
600
—
—
—
—
400
ADC2/current sense module
VINC
ISENSE+/ISENSE− input voltage (reference to AGND)
−300
—
300
mV
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
13 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
−150
—
Typ
—
Max
150
0.5
0.5
—
Unit
mV
VIND
ISENSE+/ISENSE− differential input voltage range
ISENSE+/ISENSE− input voltage offset error
ISENSE error including nonlinearities
ISENSE open load injected current
ISENSE open load detection threshold
Current sense user register resolution
VISENSEX(OFFSET)
IGAINERR
—
µV
−0.5
—
—
%
IISENSE_OL
VISENSE_OL
V2RES
130
460
0.6
µA
—
—
mV
—
—
µV/LSB
mV
VPGA_SAT
PGA saturation half-range
Gain = 256
—
—
—
—
4.9
—
—
—
—
Gain = 64
19.5
78.1
150.0
Gain = 16
Gain = 4
VPGA_ITH
Voltage threshold for PGA gain increase
mV
mV
Gain = 256
Gain = 64
Gain = 16
Gain = 4
—
—
—
—
—
—
—
—
—
2.344
9.375
37.50
VPGA_DTH
Voltage threshold for PGA gain decrease
Gain = 256
Gain = 64
Gain = 16
Gain = 4
—
—
—
—
4.298
17.188
68.750
—
—
—
—
—
tAZC_SETTLE
tICONV
Time to perform auto-zero procedure after enabling the current
channel
—
200
—
µs
µs
ADC conversion time including PGA settling time
13 bit resolution
—
—
—
—
19.00
21.67
27.00
37.67
—
—
—
—
14 bit resolution
15 bit resolution
16 bit resolution
VI_NOISE
Noise error at 16-bit conversion
Noise error at 13-bit conversion
ADC2 and ADC1-A,B clocking frequency
—
—
—
3.01
8.33
6.0
—
—
—
µVrms
µVrms
MHz
VI_NOISE
ADCCLK
Cell balance drivers
VDS(CLAMP)
VOUT(FLT_TH)
Cell balance driver VDS active clamp voltage
—
—
11
—
—
V
V
Output fault detection voltage threshold
Balance off (open load)
0.55
Balance on (shorted load)
RPD_CB
IOUT(LKG)
RDS(on)
Output OFF open load detection pull-down resistor
Balance off, open load detect disabled
kΩ
µA
Ω
—
—
2.0
—
—
Output leakage current
Balance off, open load detect disabled at VDS = 4.0 V
1.0
Drain-to-source on resistance
IOUT = 300 mA, TJ = 105 °C
IOUT = 300 mA, TJ = 25 °C
IOUT = 300 mA, TJ = −40 °C
—
—
—
—
0.80
—
0.5
0.4
—
ILIM_CB
tCB_AUTOP
tON
Driver current limitation (shorted resistor)
CB_AUTO_PAUSE timing
310
—
—
950
—
mA
µs
4.0
Cell balance driver turn on
RL = 15 Ω
µs
—
350
—
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
14 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
tOFF
Cell balance driver turn off
RL = 15 Ω
µs
—
—
200
20
—
—
tBAL_DEGLICTH
Short/open detect filter time
µs
Internal temperature measurement
IC_TEMP1_ERR
IC_TEMP1_RES
TSD_TH
IC temperature measurement error
−3.0
—
—
3.0
—
—
—
K
IC temperature resolution
Thermal shutdown
0.032
170
10
K/LSB
°C
—
TSD_HYS
Thermal shutdown hysteresis
—
°C
Default operational parameters
VCTOV(TH)
Cell overvoltage threshold (8 bits), typical value is default value after
0.0
4.2
5.0
V
reset
VCTOV(RES)
VCTUV(TH)
Cell overvoltage threshold resolution
—
19.53125
2.5
—
mV/LSB
V
Cell undervoltage threshold (8 bits), typical value is default value
after reset
0.0
5.0
VCTUV(RES)
Cell undervoltage threshold resolution
—
—
19.53125
1.16
—
—
mV/LSB
V
VGPIO_OT(TH)
GPIOx configured as ANx input overtemperature threshold from
POR
VGPIO_OT(RES)
VGPIO_UT(TH)
Temperature voltage threshold resolution
—
—
4.8828125
3.82
—
—
mV/LSB
V
GPIOx configured as ANx input undertemperature threshold from
POR
VGPIO_UT(RES)
Temperature voltage threshold resolution
—
4.8828125
—
mV/LSB
General purpose input/output GPIOx
VIH
VIL
Input high-voltage (3.3 V compatible)
2.0
—
—
—
V
Input low-voltage (3.3 V compatible)
Input hysteresis
—
1.0
—
V
VHYS
IIL
—
100
mV
nA
Input leakage current
Pins tristate, VIN = VCOM or AGND
−100
−30
—
100
IIDL
Differential Input Leakage Current GPIO 5,6
nA
V
GPIO 5,6 configured as digital inputs for current measurement
—
—
30
—
VOH
Output high-voltage IOH = −0.5 mA
VCOM
0.8
−
VOL
Output low-voltage IOL = +0.5 mA
—
—
0.8
VCOM
—
V
VADC
Analog ADC input voltage range for ratiometric measurements
Analog input open pin detect threshold
Internal open detection pull-down resistor
GPIO0 WU de-glitch filter
AGND
—
—
V
VOL(TH)
0.15
5.0
50
V
ROPENPD
tGPIO0_WU
tGPIO0_FLT
tGPIO2_SOC
tGPIOx_DIN
Reset input
VIH_RST
VIL_RST
3.8
—
—
kΩ
µs
µs
µs
µs
—
GPIO0 daisy chain de-glitch filter both edges
GPIO2 convert trigger de-glitch filter
—
20
—
—
2.0
—
—
GPIOx configured as digital input de-glitch filter
2.5
5.6
Input high-voltage (3.3 V compatible)
Input low-voltage (3.3 V compatible)
Input hysteresis
2.0
—
—
—
V
V
V
—
1.0
—
VHYS
—
0.6
MC33771BSDS
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Product short data sheet
Rev. 6.0 — 22 June 2020
15 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
—
Typ
100
100
Max
—
Unit
µs
tRESETFLT
RRESET_PD
SPI_COM_EN input
VIH
RESET de-glitch filter
Input logic pull down (RESET)
—
—
kΩ
Input high-voltage (3.3 V compatible)
Input low-voltage (3.3 V compatible)
Input hysteresis
2.0
—
—
—
—
—
1.0
—
—
V
VIL
—
V
VHYS
450
100
mV
kΩ
RSPI_COM_EN_PD
Input pull-down resistor (SPI_COM_EN)
Bus switch for TPL communication
RXTERM Bus termination resistor (open resistor when bus switch is closed)
—
150
—
Ω
Remark: If the bus switch is closed, then the termination resistor is open, else the termination resistor is connected. At the end of the daisy
chain, the switch must be open, so that the transmission line is properly terminated.
Digital interface
VFAULT_HA
IFAULT_CL
RFAULT_PD
VIH_COMM
FAULT output (high active, IOH = 1.0 mA)
FAULT output current limit
4.0
3.0
—
4.9
—
6.0
40
—
V
mA
kΩ
V
FAULT output pull-down resistance
Voltage threshold to detect the input as high
100
SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL (NOTE: needs
to be 3.3 V compatible)
—
—
2.0
VIL_COMM
Voltage threshold to detect the input as low
V
SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL
0.8
—
—
—
—
VHYS
Input hysteresis
mV
nA
SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL
80
ILOGIC_SS
Sleep state input logic current
CSB
−100
—
—
100
—
RSCLK_PD
RI_PU
Input logic pull-down resistance (SCLK/RDTX_IN–, SI/RDTX+)
Input logic pull-up resistance to VCOM (CSB, SDA, SCL)
Tristate SO input current 0 V to VCOM
20
100
—
kΩ
kΩ
µA
V
—
—
ISO_TRI
−2.0
2.0
—
VSO_HIGH
SO high-state output voltage with ISO(HIGH) = −2.0 mA
VCOM
0.4
−
—
VSO_LOW
SO, SDA, SLK low-state output voltage with ISO(HIGH) = −2.0 mA
CSB wake-up de-glitch filter, low to high transition
—
—
—
0.4
—
V
CSBWU_FLT
System timing
tCELL_CONV
50
µs
Time needed to acquire all 14 cell voltages and the current after an
on demand conversion
µs
µs
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
59
—
—
—
—
80
123
208
tSYNC
V/I synchronization time
ADC1-A,B at 13 bit, ADC2 at 13 bit
ADC1-A,B at 14 bit, ADC2 at 13 bit
ADC1-A,B at 15 bit, ADC2 at 13 bit
ADC1-A,B at 16 bit, ADC2 at 13 bit
—
—
—
—
48.16
53.50
64.16
85.50
—
—
—
—
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
16 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
tSYNC
V/I synchronization time
µs
ADC1-A,B at 13 bit, ADC2 at 14 bit
ADC1-A,B at 14 bit, ADC2 at 14 bit
ADC1-A,B at 15 bit, ADC2 at 14 bit
ADC1-A,B at 16 bit, ADC2 at 14 bit
—
—
—
—
52.14
57.48
68.14
89.48
—
—
—
—
tSYNC
V/I synchronization time
µs
µs
ADC1-A,B at 13 bit, ADC2 at 15 bit
ADC1-A,B at 14 bit, ADC2 at 15 bit
ADC1-A,B at 15 bit, ADC2 at 15 bit
ADC1-A,B at 16 bit, ADC2 at 15 bit
—
—
—
—
62.12
65.46
76.12
97.46
—
—
—
—
tSYNC
V/I synchronization time
ADC1-A,B at 13 bit, ADC2 at 16 bit
ADC1-A,B at 14 bit, ADC2 at 16 bit
ADC1-A,B at 15 bit, ADC2 at 16 bit
ADC1-A,B at 16 bit, ADC2 at 16 bit
—
—
—
—
120.51
117.84
112.51
113.39
—
—
—
—
tVPWR(READY)
tWAKE-UP
Time after VPWR connection for the IC to be ready for initialization
—
—
5.0
ms
µs
Sleep mode to normal mode device ready
Wake-up from fault
—
—
—
—
—
—
—
—
400
400
400
400
Wake-up from GPIO
Wake-up from network
Wake-up from CSB
Sleep mode to normal mode time after TPL bus wake-up
Time between wake pulses
—
—
1.0
—
ms
µs
s
tWAKE_DELAY
tIDLE
—
600
60
Idle timeout after POR
—
—
tWAKE_INIT
tBALANCE
tCYCLE
Wake-up signaling timeout after POR
Cell balance timer range
—
0.65
—
—
s
0.5
0.0
511
8.5
min
s
Cyclic acquisition timer range
—
tFAULT
Fault detection to activation of fault pin
Normal mode
µs
—
—
56
tDIAG
tEOC
Diagnostic mode timeout
0.047
1.0
8.5
s
SOC to data ready (includes post processing of data)
13-bit resolution
µs
—
—
—
—
148
201
307
520
—
—
—
—
14-bit resolution
15-bit resolution
16-bit resolution
tSETTLE
Time after SOC to begin converting with ADC1-A,B
—
12.28
—
µs
tSYS_MEAS1
Time needed to send an SOC command and read back 96 cell
voltages, 48 temperatures, 1 current, and 1 coulomb counter and
ADC1-A,B configured as follows:
ms
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
3.73
3.78
3.89
4.10
—
—
—
—
tSYS_MEAS2
Time needed to send an SOC command and read back 96
cell voltages, 1 current, and 1 coulomb counter and ADC1-A,B
configured as follows:
ms
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
2.64
2.69
2.80
3.01
—
—
—
—
MC33771BSDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
17 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
tCLST_TPL
Time needed to send an SOC command and read back 14 cell
voltages, 7 temperatures, 1 current, and 1 coulomb counter with TPL
communication working at 2.0 Mbps and ADC1-A,B configured as
follows:
ms
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
0.79
0.85
0.95
1.16
—
—
—
—
tCLST_SPI
Time needed to send an SOC command and read back 14 cell
voltages, 7 temperatures, 1 current, and 1 coulomb counter with SPI
communication working at 4.0 Mbps and ADC1-A,B configured as
follows:
ms
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
0.48
0.54
0.64
0.86
—
—
—
—
tI2C_DOWNLOAD
tI2C_ACCESS
Time to download EEPROM calibration after POR
—
—
—
1.0
—
ms
ms
EEPROM access time, EEPROM write (depends on device
selection)
5.0
tWAVE_DC_BITx
tWAVE_DC_BITx
tWAVE_DC_BITx
tWAVE_DC_BITx
Daisy chain duty cycle off time
tWAVE_DC_BITx = 00
µs
—
—
—
500
1.0
10
—
—
—
Daisy chain duty cycle off time
tWAVE_DC_BITx = 01
ms
ms
ms
Daisy chain duty cycle off time
tWAVE_DC_BITx = 10
Daisy chain duty cycle off time
tWAVE_DC_BITx = 11
—
—
—
100
—
tWAVE_DC_ON
tCOM_LOSS
SPI interface
FSCK
Daisy chain duty cycle on time
500
550
—
µs
Time out to reset the IC in the absence of communication
1024
ms
[1]
[1]
[1]
[1]
CLK/RDTX_IN– frequency
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0
—
—
—
15
15
—
—
—
—
40
40
40
—
—
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tSCK _H
tSCK _L
SCLK/RDTX_IN– high time (A)
SCLK/RDTX_IN– high time (B)
SCLK/RDTX_IN− period (A+B)
SCLK/RDTX_IN− falling time
SCLK/RDTX_IN− rising time
SCLK/RDTX_IN− setup time (O)
SCLK/RDTX_IN– hold time (P)
SI/RDTX_IN+ setup time (F)
SI/RDTX_IN+ hold time (G)
SO data valid, rising edge of SCLK/RDTX_IN− to SO data valid (I)
SO enable time (H)
125
125
250
—
tSCK
tFALL
tRISE
—
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
tSET
20
tHOLD
20
tSI_SETUP
tSI_HOLD
tSO_VALID
tSO_EN
40
40
—
—
tSO_DISABLE
tCSB_LEAD
tCSB_LAG
tTD
SO disable time (K)
—
CSB lead time (L)
100
100
1.0
CSB lag time (M)
Sequential data transfer delay (N)
MC33771BSDS
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© NXP B.V. 2020. All rights reserved.
Product short data sheet
Rev. 6.0 — 22 June 2020
18 / 29
NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
Symbol
Parameter
Min
Typ
Max
Unit
TPL interface
VRDTX INTH
VRDTX INHYS
tRES
Differential receiver threshold
—
—
—
580
100
2.35
—
—
—
mV
mV
µs
Differential receiver threshold hysteresis
Slave response after write command (echo)
[1] See Figure 4
7.5 Timing diagrams
CSB
N
M
P
K
O
L
A
B
Don't care level
SCLK
Don't care level
H
I
SO
SI
Tri-state
Tri-state
MSB
LSB
LSB
F
G
MSB
aaa-027848
Figure 4.ꢀLow-voltage SPI interface timing
Figure 5.ꢀTransformer communication signaling
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8 Packaging
8.1 Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current
package outline drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number.
Table 10.ꢀPackage Outline
Package
64-pin LQFP-EP
Suffix
Package outline drawing number
AE
98ASA10763D
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MC33771BSDS
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MC33771BSDS
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MC33771B_SDS
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MC33771BSDS
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Figure 6.ꢀPackage outline
MC33771BSDS
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9 Revision history
Table 11.ꢀRevision history
Document ID
Release date
Data sheet status
Change notice Supersedes
MC33771BSDS v.6.0
Modifications:
20200622
Product data sheet
—
—
—
MC33771BSDS v.5.0
MC33771BSDS v.1
—
Updated to align with full data sheet, MC33771B v.6.0
20180502 Technical data
Updated to align with full data sheet, MC33771B v.5.0
20180419 Product preview
MC33771BSDS v.5.0
Modifications:
MC33771BSDS v.1
MC33771BSDS
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10 Legal information
10.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
10.2 Definitions
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
10.4 Trademarks
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
SMARTMOS — is a trademark of NXP B.V.
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Part number breakdown ....................................4
Tab. 7.
Tab. 8.
Tab. 9.
Maximum ratings ...............................................9
Thermal ratings ............................................... 11
Static and dynamic electrical characteristics ... 11
Advanced orderable part table ..........................5
Basic orderable part table .................................5
Premium orderable part table ............................5
Pin definitions ....................................................6
Ratings vs. operating requirements ...................9
Tab. 10. Package Outline ..............................................20
Tab. 11. Revision history ...............................................25
Figures
Fig. 1.
Fig. 2.
Simplified application diagram, SPI use case ....2
Fig. 4.
Fig. 5.
Fig. 6.
Low-voltage SPI interface timing .....................19
Transformer communication signaling .............19
Package outline ...............................................24
Simplified application diagram, TPL use
case ...................................................................3
Pinout diagram ..................................................6
Fig. 3.
MC33771BSDS
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Contents
1
General description ............................................ 1
2
3
4
5
5.1
5.2
6
6.1
6.2
7
Features ............................................................... 1
Simplified application diagram ..........................2
Applications .........................................................3
Ordering information .......................................... 4
Part numbers definition ......................................4
Part numbers list ............................................... 5
Pinning information ............................................ 6
Pinout diagram .................................................. 6
Pin definitions .................................................... 6
General product characteristics ........................ 9
Ratings and operating requirements
7.1
relationship .........................................................9
Maximum ratings ............................................... 9
Thermal characteristics ....................................11
Electrical characteristics .................................. 11
Timing diagrams .............................................. 19
Packaging .......................................................... 20
Package mechanical dimensions .................... 20
Revision history ................................................ 25
Legal information ..............................................26
7.2
7.3
7.4
7.5
8
8.1
9
10
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 June 2020
Document identifier: MC33771BSDS
相关型号:
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