MC33880DWR2 [NXP]
BRUSH DC MOTOR CONTROLLER, 2A, PDSO28, MS-013AE, SOIC-28;
| 型号： | MC33880DWR2 |
| 厂家： | 
NXP |
| 描述： | BRUSH DC MOTOR CONTROLLER, 2A, PDSO28, MS-013AE, SOIC-28 电动机控制 信息通信管理 光电二极管 |
| 文件： | 总25页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33880
Rev. 6, 5/2008
Freescale Semiconductor
Advance Information
Configurable Octal Serial Switch
with Serial Peripheral Interface
I/O
33880
The 33880 device is an eight-output hardware-configurable high-
side/low-side switch with 8-bit serial input control. Two of the outputs
can be controlled directly via microcontroller for Pulse Width
Modulation (PWM) applications.
HIGH/LOW-SIDE SWITCH
The 33880 controls various inductive or incandescent loads by
directly interfacing with a microcontroller.
The circuit's innovative monitoring and protection features include
very low standby currents, “cascadable” fault reporting, internal 40 V
output clamping for low-side configurations, internal -20 V output
clamping for high-side configurations, output-specific diagnostics, and
independent shutdown of outputs.
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42345B
DWB SUFFIX
EW SUFFIX (PB-FREE)
98ARH99137A
Features
28-PIN SOICW
32-PIN SOICW
• Designed to Operate 5.5 V < VPWR < 24.5 V
• 8-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.8 A to 2.0 A) to Drive
Incandescent Lamps
• Output Voltage Clamp Is +45 V (Typical) (Low-Side Drive) and -
20 V (Typical) (High-Side Drive) During Inductive Switching
• Internal Reverse Battery Protection on VPWR
• Loss of Ground or Supply Will Not Energize Loads or Damage IC
• Maximum 5.0 µA IPWR Standby Current at 13 V VPWR up to 95°C
• RDS(ON) of 0.55 Ω at 25°C Typical
ORDERING INFORMATION
Temperature
Device
Package
28 SOICW
32 SOICW
Range (T )
A
MC33880DW/R2
MCZ33880EG/R2
MC33880DWB/R2
MCZ33880EW/R2
-40°C to 125°C
• Short Circuit Detect and Current Limit with Automatic Retry
• Independent Overtemperature Protection
• 32-Pin SOICW Has Pins 8, 9, 24, and 25 Grounded for Thermal
Performance
• Pb-Free Packaging Designated by Suffix Code EG and EW
V
V
S
PWR
33880
D1
D2
D3
D4
D5
D6
D7
D8
S1
S2
S3
S4
S5
S6
S7
S8
VPWR
5.0 V
High-Side
VDD
5.0 V
EN
CS
SCLK
DI
MOT
H-Bridge
MCU
SPI I/O
DO
IN5
IN6
GND
PWM
Low-Side
All Output Switches are High- or Low-Side Configurable
Figure 1. 33880 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
GND
~50 µA
__
Overvoltage
Shutdown/POR
Sleep State
CS
SCLK
DI
Internal
Bias
Charge
Pump
DO
OV, POR, SLEEP
SPI and
Interface
Logic
EN
Typical of All 8 Output Drivers
D1
D2
D3
D4
D7
D8
~50 µA
TLIM
SPI Bit 0
Drain
Outputs
Gate
Drive
IN5
Open
Load
Enable
Detect
Current
~650 µA
~50 µA
Control
Current
Limit
SPI Bit 4
IN5
+
–
IN6
S1
~50 µA
+
–
S2
S3
S4
S7
S8
_
+
Source
Outputs
~1.5 V Open/Short Threshold
Open/Short Comparator
D5
D6
Drain
Outputs
TLIM
Open
Load
Detect
Current
~650 µA
Gate
Drive
Control
Current
Limit
+
–
S5
S6
Source
Outputs
+
–
_
+
~1.5 V Open/Short
Open/Short Comparator
Threshold
Figure 2. 33880 Simplified Internal Block Diagram
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VDD
S8
S8
D8
S2
D2
S1
D1
D6
S6
IN6
EN
SCLK
DO
VPWR
S7
S7
D7
S4
D4
S3
D3
D5
S5
IN5
CS
DI
3
4
5
6
7
8
9
10
11
12
13
14
Figure 3. 28-Pin Connections
Table 1. SOICW 28-Pin Definitions
Pin
Pin Name
Number
Definition
1
2
GND
VDD
Digital ground.
Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V).
3, 4
5
S8
D8
Output 8 MOSFET source pins.
Output 8 MOSFET drain pin.
6
S2
Output 2 MOSFET source pin.
7
D2
Output 2 MOSFET drain pin.
8
S1
Output 1 MOSFET source pin.
9
D1
Output 1 MOSFET drain pin.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25, 26
27
28
D6
Output 6 MOSFET drain pin.
S6
Output 6 MOSFET source pin.
IN6
EN
SCLK
DI
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
Enable input. Allows control of outputs. Active high.
SPI control clock input pin.
SPI control data input pin from MCU to the 33880. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
CS
IN5
S5
D5
Output 5 MOSFET drain pin.
D3
Output 3 MOSFET drain pin.
S3
Output 3 MOSFET source pin.
D4
Output 4 MOSFET drain pin.
S4
Output 4 MOSFET source pin.
D7
Output 7 MOSFET drain pin.
S7
Output 7 MOSFET source pins.
VPWR
DO
Power supply pin to the 33880. VPWR has internal reverse battery protection.
SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
VDD
S8
S8
D8
S2
D2
TGND
TGND
S1
D1
D6
S6
IN6
EN
SCLK
DO
VPWR
S7
S7
D7
S4
D4
TGND
TGND
S3
D3
D5
S5
IN5
CS
9
10
11
12
13
14
15
16
DI
Figure 4. 32-Pin Connections
Table 2. SOICW 32-Pin Definitions
Pin
Pin Name
Number
Definition
1
2
GND
VDD
Digital ground.
Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V).
3, 4
S8
D8
Output 8 MOSFET source pins.
Output 8 MOSFETdrain pin.
Output 2 MOSFET source pin.
Output 2 MOSFET drain pin.
5
6
S2
7
D2
8, 9, 24, 25
TGND
Thermal Ground pins are connected internally to the substrate of the die and are used for heat transfer.
Connect thermal ground pins to the PCB ground and ground plane for heat sinking.
10
11
S1
D1
Output 1 MOSFET source pin.
Output 1 MOSFET drain pin.
12
D6
Output 6 MOSFETdrain pin.
13
S6
Output 6 MOSFET source pin.
14
IN6
EN
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
Enable input. Allows control of outputs. Active high.
SPI control clock input pin.
15
16
SCLK
DI
17
SPI control data input pin from MCU to the 33880. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
18
CS
IN5
S5
19
20
21
D5
Output 5 MOSFET drain pin.
22
D3
Output 3 MOSFET drain pin.
23
S3
Output 3 MOSFET source pin.
26
D4
Output 4 MOSFET drain pin.
27
S4
Output 4 MOSFET source pin.
28
D7
Output 7 MOSFET drain pin.
29, 30
31
S7
Output 7 MOSFET source pins.
VPWR
DO
Power supply pin to the 33880. VPWR has internal reverse battery protection.
SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
32
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VDD Supply Voltage (1)
VDD
-0.3 to 7.0
VDC
CS, DI, DO, SCLK, IN5, IN6, and EN (1)
VPWR Supply Voltage (1)
–
VPWR
–
-0.3 to 7.0
-16 to 50
VDC
VDC
VDC
Drain 1–8 (2)
-18 to 40
5.0 mA ≤ IOUT ≤ 0.3 A
Source 1–8 (3)
–
VDC
-28 to 40
5.0 mA ≤ IOUT ≤ 0.3 A
Output Voltage Clamp Low-Side Drive (4)
Output Voltage Clamp High-Side Drive (4)
Output Clamp Energy (5)
VOC
VOC
40 to 55
-15 to -25
50
VDC
VDC
mJ
V
ECLAMP
ESD Voltage (6)
Human Body Model
Machine Model
VESD1
VESD2
±2000
±200
Storage Temperature
TSTG
TC
TJ
-55 to 150
-40 to 125
-40 to 150
-40 to 150
°C
°C
°C
°C
W
Operating Case Temperature
Operating Junction Temperature
Maximum Junction Temperature
–
Power Dissipation (TA = 25°C) (7)
PD
1.3
1.7
28 SOIC, Case 751F-05
32 SOIC, Case 1324-02
Thermal Resistance, Junction-to-Ambient, 28 SOIC, Case 751F-05
RθJA
94
°C/W
°C/W
Thermal Resistance, Junction-to-Ambient, 32 SOIC, Case 1324-02
RθJA
RθJL
70
18
Thermal Resistance, Junction-to-Thermal Ground Leads, 32 SOIC, Case 1324-02
(6)
Peak Package Reflow Temperature During Reflow (5)
,
TPPRT
Note 6
°C
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Configured as low-side driver with 300 mA load as current limit.
3. Configured as high-side driver with 300 mA load as current limit.
4. With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver.
5. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), and ESD2 testing is performed
in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
7. Maximum power dissipation with no heatsink used.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Range
Fully Operational
VPWR(FO)
V
5.5
–
–
24.5
14
Supply Current
IPWR(ON)
IPWR(SS)
8.0
mA
Sleep State Supply Current (VDD and EN = 0 V, VPWR = 16 V)
Temperature = -40°C to 95°C
µA
–
–
2.0
5.0
5.0
20
Temperature = 95°C to 125°C
Overvoltage Shutdown
VOV
VOV(HYS)
VDD
25
0.15
4.75
0.5
27
0.8
–
30
2.5
V
V
Overvoltage Shutdown Hysteresis
Logic Supply Voltage
5.25
4.0
V
Logic Supply Current
IDD
2.6
4.3
150
mA
V
Logic Supply Undervoltage Lockout Threshold
Logic Supply Undervoltage Hysteresis
POWER OUTPUT
VDD(UNVOL)
VDD(UNVOL-HYS)
3.9
4.7
100
300
mV
Drain-to-Source ON Resistance (VPWR = 16 V)
IOUT = 0.25 A, TJ = 125°C
RDS(ON)
Ω
–
–
–
0.75
0.55
0.45
1.1
0.85
0.80
IOUT = 0.25 A, TJ = 25°C
IOUT = 0.25 A, TJ = -40°C
Output Self-Limiting Current High-Side and Low-Side Configurations
VPWR = 16 V
IOUT(LIM)
VOUTth(F)
IOCO
A
V
0.8
1.0
0.30
40
1.4
–
2.0
3.0
1.0
55
(9)
Output Fault Detect Threshold (8)
Outputs Programmed OFF
,
Output Off Open Load Detect Current (8)
Outputs Programmed OFF
mA
V
0.55
45
Output Clamp Voltage Low-Side Drive
ID = 10 mA
VOC(LSD)
VOC(HSD)
IOUT(LKG)
Output Clamp Voltage High-Side Drive
IS = -30 mA
V
-15
-20
-25
Output Leakage Current High-Side and Low-Side Configuration
VDD = 0 V, VDS = 16 V
µA
–
1.0
–
7.0
185
15
Overtemperature Shutdown (9)
Overtemperature Shutdown Hysteresis (9)
Notes
TLIM
155
5.0
°C
°C
TLIM(HYST)
10
8. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts.
9. This parameter is guaranteed by design but is not production tested.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (10)
VINLOGIC
0.8
–
2.2
V
IN5, IN6, and EN Input Logic Current
IN5, IN6, EN = 0 V
IIN5, IN6, EN
µA
-10
30
–
10
IN5, IN6, and EN Pull-Down Current
0.8 V to VDD
IIN5, IN6, EN
ISCK, SI, TriSO
IICS
µA
µA
µA
45
100
SCLK, DI, and Tri-State DO Input
0 V to VDD
-10
-10
–
–
10
10
CS Input Current
CS = VDD
IICS
VDOHIGH
VDOLOW
CIN
µA
V
CS Pull-Up Current
CS = 0 V
-30
–
–
-100
VDD
DO High-State Output Voltage
IDO-HIGH = -200 µA
VDD-0.8
DO Low-State Output Voltage
IDO-HIGH = 1.6 mA
V
–
–
–
–
0.4
20
Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (11)
pF
Notes
10. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
11. This parameter is guaranteed by design but is not production tested.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate Low-Side Configuration (12)
tR
tF
tR
tF
V/µs
V/µs
V/µs
V/µs
RL = 620 Ω
0.1
0.1
0.1
0.1
0.5
0.5
0.3
0.3
1.2
1.2
1.2
1.2
Output Slew Rate Low-Side Configuration (12)
RL = 620 Ω
Output Slew Rate High-Side Configuration (12)
RL = 620 Ω
Output Slew Rate High-Side Configuration (12)
RL = 620 Ω
Output Turn ON Delay Time, High-Side and Low-Side Configuration (13)
Output Turn OFF Delay Time, High-Side and Low-Side Configuration (13)
Output Fault Delay Time (14)
tDLY(ON)
tDLY(OFF)
tFAULT
1.0
1.0
15
30
–
50
µs
µs
µs
100
300
100
DIGITAL INTERFACE TIMING
Recommended Frequency of SPI Operation
–
–
–
4.0
4.0
6.0
10
MHz
Required Low State Duration on VDD for Reset (15)
tRESET
µs
VDD ≤ 0.2 V
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time (16)
tLEAD
tLAG
100
50
16
20
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDI(su)
–
–
tDI(HOLD)
tR(DI)
–
–
5.0
5.0
–
–
DI, CS, SCLK Signal Fall Time (16)
tF(DI)
–
–
Time from Falling Edge of CS to DO Low Impedance (17)
Time from Rising Edge of CS to DO High Impedance (18)
Time from Rising Edge of SCLK to DO Data Valid (19)
Notes
tDO(EN)
tDO(DIS)
tVALID
–
60
60
60
–
–
–
25
12. Output Rise and Fall time respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
13. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage.
14. Duration of fault before fault bit is set. Duration between access times must be greater than 300 µs to read faults.
15. This parameter is guaranteed by design but is not production tested.
16. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
17. Time required for output status data to be available for use at DO pin.
18. Time required for output status data to be terminated at DO pin
19. Time required to obtain valid data out from DO following the rise of SCLK.
33880
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 V
DD
t
t
LEAD
LAG
0.7 VDD
SCLK
0.2 V
DD
t
t
DI(SU) DI(HOLD)
0.7 V
0.2 V
DD
DD
DI
MSB in
t
t
t
DO(DIS)
DO(EN)
VALID
0.7 V
0.2 V
DD
DD
DO
MSB out
LSB out
Figure 5. SPI Timing Diagram
VDD = 5.0 V
VDD = 5.0 V
V
PWR = 13 V
33880
Under
Test
SCLK
DO
C = 200 pF
RL = 620 Ω
33880
Under
Test
Output
CS
L
CL
NOTE: CL represents the total capacitance of the test
fixture and probe.
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 6. Valid Data Delay Time
and Valid Time Test Circuit
Figure 8. Switching Time Test Circuit
VDD = 5.0 V
VPull-Up = 2.5 V
RL = 1.0 kΩ
33880
Under
Test
CS
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 7. Enable and Disable Time Test Circuit
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
tR(DI)
tF(DI)
tR(DI)
tF(DI)
<50 ns
90%
<50 ns
< 50 ns
< 50 ns
5.0 V
0
0.7 VDD
CS
5.0 V
0.7 VDD (2.5 V)
10%
50%
0.2 VDD (2.5 V)
0.2 VDD
SCLK
0
tDO(EN)
tDO(DIS)
VTri-State
DO
90%
tDLY(LH)
VOH
(Tri-State to Low)
0.7 VDD
10%
tSO(DIS)
0.2 VDD
tVALID
DO
VOL
tDO(EN)
tDO(DIS)
tr(DO)
(Low-to-High)
DO
VOH
90%
VOH
0.7 VDD
tDLY(HL)
VTri-State
(High-to-Low)
DO
10%
(Tri-State to High)
0.2 VDD
VOL
Figure 10. Enable and Disable Time Waveforms
Figure 9. Valid Data Delay Time and Valid Time
Waveforms
tR(DI)
tF(DI)
<50 ns
90%
<50 ns
5.0 V
0
CS
0.2 VDD (2.5 V)
0.7 VDD
10%
tDO(EN)
tDO(DIS)
VTri-State
DO
90%
(Tri-State to Low)
10%
tSO(DIS)
tDO(EN)
tDO(DIS)
VOH
90%
VTri-State
DO
10%
(Tri-State to High)
Figure 11. Turn-ON/OFF Waveforms
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
14
14
14
12
10
8
V
@ 16 V
V
@ 16 V
PWR
PWR
12
10
All Outputs ON
All Outputs OFF
8
6
6
4
4
2
2
-40 -25
0
25
50
75 100 125
-40 -25
0
25
50
75
100 125
TA, Ambient Temperature (°C)
T
A, Ambient Temperature (°C)
Figure 13. Sleep State IPWR vs. Temperature
Figure 12. IPWR vs. Temperature
70
60
50
40
30
20
10
1.4
1.2
1.0
0.8
0.6
0.4
0.2
T
= 25°C
A
V
@ 16 V
PWR
0
5.0
10
VPWR
15
20
25
-40 -25
0
25
TA, Ambient Temperature (°C)
Figure 15. RDS(ON) vs. Temperature @ 250 mA
50
75
100 125
Figure 14. Sleep State IPWR vs. VPWR
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.6
1.5
1.4
1.3
1.2
1.1
1.0
V
@ 16 V
PWR
V
@ 16 V
PWR
0
-40 -25
0
25
A, Ambient Temperature (°C)
Figure 17. Current Limit IOUT(LIM) vs. Temperature
50
75
100 125
5.0
10
VPWR (V)
Figure 16. RDS(ON) vs. VPWR @ 250 mA
15
20
25
T
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.4
V
@ 16 V
PWR
T
= 25°C
A
High-Side Configuration
1.2
1.0
0.8
0.6
0.4
0.2
0
5.0
10
VPWR (V)
Figure 19. Open Load Detect Current vs. VPWR
15
20
25
-40 -25
0
25
50
75
100 125
T
A, Ambient Temperature (°C)
Figure 18. Open Load Detect Current vs. Temperature
1.4
T
= 25°C
A
1.2
1.0
0.8
0.6
0.4
0.2
0
5.0
10
15
PWR (V)
20
25
V
Figure 20. Sleep State Output Leakage vs. VPWR
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33880 is an eight-output hardware configurable power
switch with 8-bit serial control. The 33880 incorporates
SMARTMOS™ 5 technology with CMOS logic, bipolar/MOS
analog circuitry, and independent double diffused DMOS
power output transistors. Many benefits are realized as a
direct result of using this mixed technology. A simplified
internal block diagram of the 33880 is shown in Figure 2,
page 2.
The 33880 device uses high-efficiency updrain power
DMOS output transistors exhibiting low drain-to-source ON
resistance values (RDS(ON) ≤ 0.55 Ω at 25°C) and dense
CMOS control logic. All outputs have independent voltage
clamps to provide fast inductive turn-off and transient
protection. Operational bias currents of less than 4.0 mA on
VDD and 12 mA on VPWR with any combination of outputs ON
are a direct result of using SMARTMOS™ 5 technology.
FUNCTIONAL PIN DESCRIPTION
the DI pin beginning with Output 8, followed by Output 7,
Output 6, and so on to Output 1. For each falling edge of the
SCLK while CS is logic low, a data bit instruction (on or off) is
loaded into the shift register per the data bit DI state. Eight
bits of entered information fills the shift register. To preserve
data integrity, do not transition DI as SCLK transitions from a
high to low logic state.
CHIP SELECT (CS)
The system MCU selects the 33880 to communicate
through the use of the CS pin. Whenever the pin is in a logic
low state, data can be transferred from the MCU to the 33880
device and vice versa. Clocked-in data from the MCU is
transferred from the 33880 shift register and latched into the
power outputs on the rising edge of the CS signal. On the
falling edge of the CS signal, output status information is
transferred from the power outputs status register into the
device's shift register. The falling edge of CS enables the DO
output driver. Whenever the CS pin goes to a logic low state,
the DO pin output is enabled, thereby allowing information to
be transferred from the 33880 to the MCU. To avoid any
spurious data, it is essential the high-to-low transition of the
CS signal occurs only when SCLK is in a logic low state.
DATA OUTPUT (DO)
The serial data output (DO) pin is the output from the shift
register. The DO pin remains tri-state until the CS pin goes to
a logic low state. All faults on the 33880 device are reported
as logic [1] through the DO data pin. Regardless of the
configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs
with non-faulted loads are reported as logic [0]. The first
positive transition of SCLK will make output eight status
available on DO pin. Each successive positive clock will
make the next output status available. The DI/DO shifting of
data follows a first-in-first-out protocol with both input and
output words transferring the most significant bit (MSB) first.
SYSTEM CLOCK (SCLK)
The system clock pin (SCLK) clocks the internal shift
registers of the 33880. The serial data input (DI) is latched
into the input shift register on the falling edge of the SCLK.
The serial data output pin (DO) shifts data out of the shift
register on the rising edge of the SCLK signal. False clocking
of the shift register must be avoided to guarantee validity of
data. It is essential the SCLK pin be in a logic low state
whenever chip select pin (CS) makes any transition. For this
reason, it is recommended the SCLK pin is commanded to a
logic low state when the device is not accessed (CS in logic
high state). When the CS is in a logic high state, any signal at
the SCLK and DI pin is ignored and the DO is tri-stated (high
impedance).
ENABLE (EN)
The EN pin on the 33880 device either enables or disables
the internal charge pump. The EN pin must be high for this
device to enhance the gates of the output drivers, perform
fault detection, and reporting. Active outputs during a low
transition of the EN pin will become active again when the EN
transitions high. If this feature is not required, it is
recommended the EN pin be connected to VDD
.
DATA INPUT (DI)
COMMAND INPUT (IN5 AND IN6)
This pin is used for serial instruction data input. DI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on DI will program
a specific output on. The specific output will turn on with the
rising edge of the CS signal. Conversely, a logic low state
present on the DI pin will program the output off. The specific
output will turn off with the rising edge of the CS signal. To
program the eight outputs of the 33880 device on or off, enter
The IN5 and IN6 pins command inputs allowing outputs
five and six to be used in PWM applications. IN5 and IN6 pins
are ORed with the SPI communication input. For SPI control
of outputs five and six, the IN5 and IN6 pins should be
grounded or held low by the microprocessor. In the same
manner, when using the PWM feature the SPI port must
command the outputs off. Maximum PWM frequency for each
output is 2.0 kHz.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
the load. All outputs may be configured individually as
desired. When Low-Side Drive is used, the 33880 limits the
positive transient for inductive loads to 45 V.
LOGIC POWER (VDD)
The VDD pin supplies logic power to the 33880 device and
is used for power-on reset (POR). To achieve low standby
current on VPWR supply, power must be removed from the
SOURCE OUTPUT (S1–S8)
VDD pin. The device will be in reset with all drivers off when
VDD is below 3.9 VDC
.
The S1–S8 pins are the source outputs of the 33880. For
High-Side Drive configurations, the source pins are
connected directly to the load. In Low-Side Drive
configurations the source is connected to ground. All outputs
may be configured individually as desired. When High-Side
drive is used, the 33880 will limit the negative transient for
inductive loads to -20 V.
OPEN DRAIN OUTPUT (D1–D8)
The D1–D8 pins are the open drain outputs of the 33880.
For High-Side Drive configurations, the drain pins are
connected to battery supply. In Low-Side Drive
configurations, the drain pins are connected to the low side of
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Master In Slave Out (MISO) line. On rising edge of CS data
stored in the input register is then transferred to the output
driver.
MCU INTERFACE DESCRIPTION
In operation, the 33880 functions as an eight-output serial
switch serving as a microcontroller (MCU) bus expander and
buffer, with fault management and fault reporting features. In
doing so, the device directly relieves the MCU of the fault
management functions. This device directly interfaces to an
MCU using a Serial Peripheral Interface (SPI) for control and
diagnostic readout. Figure 21 and Figure 24, page 16,
illustrate the basic SPI configuration between an MCU and
one 33880.
SCLK
Parallel Port
CS
DO
CS SCLK
DO DI
CS SCLK
DO DI
MC68xx
MCU
MISO
DI
with
SPI
Interface
MC68HCxx
Microcontroller
33880
33880
33880
33880
8 Outputs
8 Outputs
8 Outputs
DI
MOSI
MISO
MOSI
Shift Register
Shift Register
DO
Figure 22. 33880 SPI System Daisy Chain
SCLK
CS
Multiple 33880 devices can be controlled in a parallel input
fashion using the SPI. Figure 23 illustrates 24 loads being
controlled by three dedicated parallel MCU ports used for
chip select.
Receive
Buffer
To
Logic
Parallel
Ports
MOSI
DI
SCLK
SCLK
MISO
Figure 21. SPI Interface with Microcontroller
8 Outputs
DO
CS
All inputs are compatible with 5.0 V and 3.3 V CMOS logic
levels and incorporate positive logic. Whenever an input is
programmed to a logic low state (<0.8 V) the corresponding
output will be OFF. Conversely, whenever an input is
programmed to a logic high state (>2.2 V), the output being
controlled will be ON. Diagnostics are treated in a similar
manner. Outputs with a fault will feedback (via DO) to the
microcontroller as a logic [1] while normal operating outputs
will provide a logic [0].
MC68xx
Microcontroller
SPI
DI
SCLK
DO
8 Outputs
8 Outputs
CS
Figure 22 illustrates the Daisy Chain configuration using
the 33880. Data from the MCU is clocked daisy chain through
each device while the Chip Select (CS) bit is commanded low
by the MCU. During each clock cycle output status from the
daisy chain, the 33880 is being transferred to the MCU via the
DI
A
Parallel
Ports
SCLK
DO
B
C
CS
Figure 23. Parallel Input SPI Control
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
sent. Please note that the second byte the MCU sends to the
device is the command byte and will be transferred to the
outputs with rising edge of CS.
POWER CONSUMPTION
The 33880 device has been designed with one sleep and
one operational mode. In the sleep mode (VDD ≤ 2.0 V), the
current consumed by the VPWR pin is less than 25 µA. To
place the 33880 in the sleep mode, turn all outputs off, then
remove power from VDD and the EN (enable) input pin. Prior
to removing power from the device, it is recommended all
control inputs from the microcontroller are low. During normal
operation, 4.0 mA will be drawn from the VDD supply and
12 mA from the VPWR supply.
OVERTEMPERATURE FAULT
Overtemperature detect and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system clock or any other logic signal.
Each independent output shuts down at 155°C to 185°C.
When an output shuts down due to an overtemperature fault,
no other outputs are affected. The MCU recognizes the fault
by a one in the fault status register. After the 33880 device
has cooled below the switch point temperature and 15°C
hysteresis, the output will activate unless told otherwise by
the MCU via SPI to shut down.
PARALLELING OF OUTPUTS
Using MOSFETs as output switches allows the connection
of any combination of outputs together. RDS(ON) of MOSFETs
have an inherent positive temperature coefficient, providing
balanced current sharing between outputs without
destructive operation. The device can even be operated with
all outputs tied together. This mode of operation may be
desirable in the event the application requires lower power
dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON) while the outputs OFF
open load detect currents and the output current limits
increase correspondingly (by a factor of eight if all outputs are
paralleled). Paralleling outputs from two or more different IC
devices are possible but not recommended.
OVERVOLTAGE FAULT
An overvoltage condition on the VPWR pin will cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltage
threshold on the VPWR pin is specified as 25 V to 30 V with
1.0 V typical hysteresis. A VPWR overvoltage detect is
global, causing all outputs to be turned OFF.
FAULT LOGIC OPERATION
OUTPUT OFF OPEN LOAD FAULT
Fault logic of the 33880 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs
faulted, all status bits being received by the MCU will be zero.
When outputs are faulted (off state open circuit or on state
short circuit/overtemperature), the status bits being received
by the MCU will be one. The distinction between open circuit
fault and short circuit/overtemperature is completed via the
command word. For example, when a zero command bit is
sent and a one fault is received in the following word, the fault
is open/short-to-battery for high-side drive or open/short to
ground for low-side drive. In the same manner, when a one
command bit is sent and a one fault is received in the
following word the fault is a short-to-ground/overtemperature
for high-side drive or short-to-battery/overtemperature for
low-side drive. The timing between two write words must be
greater than 300 µs to allow adequate time to sense and
report the proper fault status.
An output OFF open load fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
output OFF open load fault is detected by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
An output off open load fault is indicated when the drain-
to-source voltage is less than the output threshold voltage
(VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the
load open in the OFF state when the VDS is less than 1.0 V.
This device has an internal 650 µA current source
connected from drain to source of the output MOSFET. This
prevents either configuration of the driver from having a
floating output. To achieve low sleep mode quiescent
currents, the open load detect current source of each driver
is switched off when VDD is removed.
During output switching, especially with capacitive loads,
a false output OFF open load fault may be triggered. To
prevent this false fault from being reported, an internal fault
filter of 100 µs to 300 µs is incorporated. A false fault
reporting is a function of the load impedance, RDS(ON), COUT
of the MOSFET, as well as the supply voltage, VPWR. The
rising edge of CS triggers the built-in fault delay timer. The
timer will time out before the fault comparator is enabled and
the fault is detected. Once the condition causing the open
load fault is removed, the device will resume normal
operation. The open load fault however, will be latched in the
output DO register for the MCU to read.
SPI INTEGRITY CHECK
It is recommended that one check the integrity of the SPI
communication with the initial power-up of the VDD and EN
pins. After initial system start-up or reset, the MCU will write
one 16-bit pattern to the 33880. The first eight bits read by the
MCU will be the fault status of the outputs, while the second
eight bits will be the first byte of the bit pattern. Bus integrity
is confirmed by the MCU receiving the same bit pattern it
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SHORTED LOAD FAULT
Drain-to-Source Clamp
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply or an output causing
the device to current limit (linear short).
Voltage (V = 45 V)
CL
Drain Voltage
Clamp Energy
There are two safety circuits progressively in operation
during load short conditions providing system protection:
Drain Current
(ID = 0.3 A)
(EJ = IA x VCL
)
1. The device’s output current is monitored in an analog
fashion using SENSEFET™ approach and current
limited.
Drain-to-Source ON
Voltage (V
)
DS(ON)
Current
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will remain off until cooled. The
device will then reassert the output automatically. The
cycle will continue until the fault is remove or the
command bit instructs the output off.
Area (I )
A
Time
GND
VBAT
Drain-to-Source ON
Voltage (V
)
DS(ON)
GND
Time
Current
Area (I )
A
Clamp Energy
UNDERVOLTAGE SHUTDOWN
(EJ = IA x VCL
)
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is
between 3.9 V and 4.6 V. When VDD goes below the
threshold, all outputs are turned OFF and the Fault Status
(FS) register is cleared. As VDD returns to normal levels, the
FS register will resume normal operation.
Source Current
(I = 0.3 A)
S
Source Clamp Voltage
Source Voltage
(V = -20 V)
CL
Figure 25. Output Voltage Clamping
SPI CONFIGURATIONS
An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V
and 9.0 V, the output will operate per the command word.
However, the status as reported by the serial data output
(DO) pin may not be accurate below 9.0 V VPWR. Proper
operation at VPWR voltages below 5.5 V cannot be
guaranteed.
The SPI configuration on the 33880 device is consistent
with other devices in the OSS family. This device may be
used in serial SPI or parallel SPI with the 33291 and 33298.
Different SPI configurations may be provided. For more
information, contact Analog Products Division.
OUTPUT VOLTAGE CLAMP
Each output of the 33880 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 45 V for low-side drive configurations and -20 V for
high-side drive configurations (see Figure 25). The total
energy clamped (EJ) can be calculated by multiplying the
current area under the current curve (IA) times the clamp
voltage (VCL).
REVERSE BATTERY
The 33880 has been designed with reverse battery
protection on the VPWR pin. However, the device does not
protect the load from reverse battery. During the reverse
battery condition, current will flow through the load via the
output MOSFET substrate diode. Under this circumstance
relays may energize and lamps will turn on. If load reverse
battery protection is desired, a diode must be placed in series
with the load.
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3 A, indicates the maximum
energy to be 50 mJ at 150°C junction temperature per output.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
On each SPI communication, an 8-bit command word is sent to the 33880 and an 8-bit fault word is received from the 33880.
The Most Significant Bit (MSB) is sent and received first (see below).
MSB
LSB
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Command Register Definition:
0 = Output Command Off
1 = Output Command On
Fault Register Definition:
0 = No fault
1 = Fault.
Table 6. Fault Operation
SERIAL OUTPUT (SO) PINS REPORTS
Overtemperature
Fault reported by Serial Output (DO) pin.
DO pin reports short to battery/supply or overcurrent condition.
Not reported.
Overcurrent
Output ON Open Load Fault
Output OFF Open Load Fault
DEVICE SHUTDOWNS
Overvoltage
DO pin reports output OFF open load condition.
Total device shutdown at V
= 25 V to 30 V. Resumes normal operation with proper voltage.
PWR
All outputs assuming the previous state upon recovery from overvoltage.
Overtemperature
Only the output experiencing an overtemperature fault shuts down. Output assumes previous state
upon recovery from overtemperature.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
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PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using “98ASB42345B”.
DW SUFFIX
EG SUFFIX (PB-FREE)
28-PIN
PLASTIC PACKAGE
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PACKAGING
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28-PIN
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PACKAGING
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PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
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Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
Implemented Revision History page
Converted to Freescale format and adjusted content to prevailing form and style
6/2006
4.0
•
Removed MC33880EG/R2 and MC33880EK/R2 from the ordering information and added
6/2007
5/2008
5.0
6
MCZ33880EG/R2 and MCZ33880EW/R2.
(6)
•
•
Added Peak Package Reflow Temperature During Reflow (5)
Updated data sheet to current format.
,
•
Changed 32 pin SOICW, pins 8, 9, 24, 25 from GND to TGND on page 4.
33880
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
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MC33880
Rev. 6
5/2008
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