MC33883HEGR2 [NXP]
H-Bridge Predriver, 1.0 A peak gate driver current, SOIC 20, Reel;
| 型号： | MC33883HEGR2 |
| 厂家： | 
NXP |
| 描述： | H-Bridge Predriver, 1.0 A peak gate driver current, SOIC 20, Reel 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总21页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33883
Rev 10.0, 10/2012
escale Semiconductor
Technical Data
H-Bridge Gate Driver IC
33883
The 33883 is an H-bridge gate driver (also known as a full-bridge
pre-driver) IC with integrated charge pump and independent high and
low side gate driver channels. The gate driver channels are
independently controlled by four separate input pins, thus allowing
the device to be optionally configured as two independent high side
gate drivers and two independent low side gate drivers. The low side
channels are referenced to ground. The high side channels are
floating.
H-BRIDGE GATE DRIVER IC
The gate driver outputs can source and sink up to 1.0 A peak
current pulses, permitting large gate-charge MOSFETs to be driven
and/or high pulse- width modulation (PWM) frequencies to be utilized.
A linear regulator is incorporated, providing a 15 V typical gate supply
to the low side gate drivers.
This device powered by SMARTMOS technology.
EG SUFFIX (PB-FREE)
98ASB42343B
Features
20-PIN SOICW
• VCC operating voltage range from 5.5 V up to 55 V
• VCC2 operating voltage range from 5.5 V up to 28 V
• CMOS/LSTTL compatible I/O
• 1.0 A peak gate driver current
• Built-in high side charge pump
ORDERING INFORMATION
Temperature
Device
(Add R2 Suffix for
Package
Range (T )
A
• Under-voltage lockout (UVLO)
Tape and Reel)
• Over-voltage lockout (OVLO)
• Global enable with <10 A Sleep mode
• Supports PWM up to 100 kHz
MC33883HEG
-40 °C to 125 °C
20 SOICW
V
V
BAT
BOOST
33883
CP_OUT
VCC
VCC2
G_EN
LR_OUT
GATE_HS1
SRC_HS1
GATE_LS1
GATE_HS2
SRC_HS2
GATE_LS2
C1
C2
DC
Motor
MCU
IN_HS1
IN_LS1
IN_HS2
IN_LS2
/2
GND
GND_A
Figure 1. 33883 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2012. All rights reserved.
RNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C1
C2
VCC2
VCC,
V
CC2
VCC
Undervolt-
age/Over-
voltage
VCC2
VCC
EN
C1
VCC
VDD
Charge
Pump
C2
CP_OUT
+5.0 V
VCC
VPOS
GND
VCC2
G_EN
VDD
GND2
CP_OUT
VCC2
EN
Linear
Reg
LR_OUT
GND
+14.5 V
LR_OUT
GND_A
HIGH- AND LOW-SIDE
CONTROL WITH CHARGE PUMP
GND2
Con-
CP_OUT
OU
VCC
BRG_EN
IN
Output
Driver
IN_HS1
IN_LS1
VDD/VPOS
Level Shift
Pulse
Generator
troland
Logic
GATE_HS
SRC_HS1
TSD1
TSD
1
HIGH-SIDE CHANNEL
Thermal Shutdown
BRG_EN
Con-
troland
Logic
LR_OUT
TSD1
OU
IN
VDD/VCC
Output
Driver
Pulse
Generator
GATE_LS1
Level Shift
GND1
LOW-SIDE CHANNEL
CP_OUT
OU
VCC
BRG_EN
Con-
troland
Logic
IN
Output
Driver
VDD/VPOS
Level Shift
Pulse
Generator
IN_HS2
IN_LS2
GATE_HS
SRC_HS2
TSD2
HIGH-SIDE CHANNEL
TSD
2
Thermal Shutdown
BRG_EN
Con-
troland
Logic
LR_OUT
TSD2
OU
IN
Output
Driver
VDD/VCC
Pulse
Generator
GATE_LS2
Level Shift
GND2
LOW-SIDE CHANNEL
GND
GND
GND_
Figure 2. 33883 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
2
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
1
20
19
VCC
G_EN
2
SRC_HS2
GATE_HS2
IN_HS2
IN_LS2
GATE_LS2
GND2
C2
CP_OUT
SRC_HS1
3
18
17
4
5
16
15
14
13
12
11
GATE_HS1
IN_HS1
6
7
IN_LS1
8
GATE_LS1
GND1
C1
9
GND_A
VCC2
10
LR_OUT
Figure 3. 33883 20-SOICW Pin Connections
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Table 1. 20-SOICW Pin Definitions
Pin
1
Pin Name
VCC
Formal Name
Supply Voltage 1
Definition
Device power supply 1.
2
C2
Charge Pump Capacitor
Charge Pump Out
External capacitor for internal charge pump.
3
CP_OUT
External reservoir capacitor for internal charge pump.
4
SRC_HS1 Source 1 Output High Side Source of high-side 1 MOSFET
5
GATE_HS Gate 1 Output High Side
1
Gate of high-side 1 MOSFET.
6
IN_HS1
IN_LS1
Input High Side 1
Input Low Side 1
Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH).
Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH).
Gate of low-side 1 MOSFET.
7
8
GATE_LS1 Gate 1 Output Low Side
9
GND1
LR_OUT
VCC2
GND_A
C1
Ground 1
Device ground 1.
10
11
12
13
14
15
16
17
18
Linear Regulator Output
Supply Voltage 2
Analog Ground
Charge Pump Capacitor
Ground 2
Output of internal linear regulator.
Device power supply 2.
Device analog ground.
External capacitor for internal charge pump.
Device ground 2.
GND2
GATE_LS2 Gate 2 Output Low Side
Gate of low-side 2 MOSFET.
IN_LS2
IN_HS2
Input Low Side 2
Input High Side 2
Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH).
Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH).
Gate of high-side 2 MOSFET.
GATE_HS Gate 2 Output High Side
2
19
20
SRC_HS2 Source 2 Output High Side Source of high-side 2 MOSFET.
G_EN
Global Enable
Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN
logic LOW = Sleep Mode).
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
CTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage 1
V
V
V
-0.3 to 65
-0.3 to 35
-0.3 to 18
-0.3 to 65
-2.0 to 65
250
CC
Supply Voltage 2 (1)
V
CC2
Linear Regulator Output Voltage
V
V
LR_OUT
CP_OUT
SRC_HS
High-Side Floating Supply Absolute Voltage
High-Side Floating Source Voltage
V
V
V
V
High-Side Source Current from CP_OUT in Switch ON State
High-Side Gate Voltage
mA
V
I
S
V
-0.3 to 65
-0.3 to 20
GATE_HS
High-Side Gate Source Voltage (2)
V
V
-
GATE_HS
V
SRC_HS
High-Side Floating Supply Gate Voltage
V
V
V
-
-0.3 to 65
CP_OUT
GATE_HS
Low-Side Gate Voltage
Wake-Up Voltage
V
V
V
V
V
V
V
-0.3 to 17
-0.3 to 35
-0.3 to 10
GATE_LS
V
G_EN
Logic Input Voltage
V
IN
Charge Pump Capacitor Voltage
Charge Pump Capacitor Voltage
ESD Voltage (3)
V
-0.3 to V
LR_OUT
C1
V
-0.3 to 65
C2
Human Body Model on All Pins (V
Supplies)
and V
as Two Power
CC2
CC
V
±1500
±130
ESD1
Machine Model
V
ESD2
Notes
1.
V
can sustain load dump pulse of 40 V, 400 ms, 2.0 .
CC2
2. In case of high current (SRC_HS>100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is
needed as shown in Figure 14.
3. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 ), ESD2 testing is performed in
ZAP
ZAP
accordance with the Machine Model (C
=200 pF, R
=0 ).
ZAP
ZAP
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Value
Unit
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ 25°C
Thermal Resistance (Junction to Ambient)
Operating Junction Temperature
W
°C/W
°C
P
D
1.25
100
R
JA
T
-40 to 150
-65 to 150
J
Storage Temperature
°C
T
STG
TPPRT
Peak Package Reflow Temperature During Reflow (4)
,
Note 5
(5)
°C
Notes
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OPERATING CONDITIONS
Supply Voltage 1 for Output High-Side Driver and Charge Pump
Supply Voltage 2 for Linear Regulation
V
5.5
5.5
–
–
–
55
28
V
V
V
CC
V
CC2
High-Side Floating Supply Absolute Voltage
V
V
+4
V
+11
CC
CP_OUT
CC
but < 65
LOGIC
Logic 1 Input Voltage (IN_LS and IN_HS)
Logic 0 Input Voltage (IN_LS and IN_HS)
Logic 1 Input Current
V
2.0
–
–
–
10
V
V
IH
V
0.8
IL
I
A
IN+
V
= 5.0 V
200
4.5
–
1000
IN
Wake-Up Input Voltage (G_EN)
Wake-Up Input Current (G_EN)
V
5.0
V
V
G_EN
CC2
I
A
G_EN
V
= 14 V
–
–
200
–
500
1.5
G_EN
Wake-Up Input Current (G_EN)
= 28 V
I
mA
V
G_EN2
V
G_EN
LINEAR REGULATOR
Linear Regulator
V
LR_OUT
V
V
V
@ V
@ I
from 15 V to 28 V, I
= 20 mA
from 0 mA to 20 mA
LOAD
12.5
-1.5
CC2
–
–
–
16.5
–
LR_OUT
LR_OUT
LR_OUT
CC2
V
LOAD
LOAD
4.0
–
@ I
= 20 mA, V
=5.5V, V
5.5V
CC
CC2
CHARGE PUMP
Charge Pump Output Voltage, Reference to VCC
V
V
CP_OUT
V
V
V
V
V
V
= 12 V, I
= 12 V, I
= 0 mA, C = 1.0 F
CP_OUT
7.5
7.0
2.3
1.8
7.5
7.0
–
–
–
–
–
–
–
–
–
–
–
–
CC
LOAD
LOAD
= 7.0 mA, C
= 1.0 F
CC
CP_OUT
= V
= V
= 5.5 V, I
= 5.5 V, I
= 0 mA, C
= 1.0 F
CC
CC
CC2
CC2
LOAD
LOAD
CP_OUT
= 7.0 mA, C
= 1.0 F
CP_OUT
= 55 V, I
= 0 mA, C
CP_OUT
= 1.0 F
CC
CC
LOAD
LOAD
= 55 V, I
= 7.0 mA, C
CP_OUT
= 1.0 F
Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see
Figure 13, page 17)
I
A
V
C1
-2.0
-1.5
–
–
2.0
–
Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages
(see Figure 13, page 17)
V
MIN
C1
33883
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Quiescent VCC Supply Current
IV
A
CCSLEEP
V
V
= 0 V and V
= 0 V and V
= 55 V
= 12 V
–
–
–
–
10
10
G_EN
G_EN
CC
CC
Operating VCC Supply Current (6)
IV
mA
CCOP
V
V
= 55 V and V
= 12 V and V
= 28 V
= 12 V
–
–
2.2
0.7
–
–
CC
CC
CC2
CC2
Additional Operating V
Supply Current for Each Logic Input Pin Active
= 28 V (7)
IV
mA
CC
CCLOG
–
–
5.0
V
= 55 V and V
CC2
CC
Quiescent VCC2 Supply Current
IV
A
CC2SLEEP
V
V
= 0 V and V
= 0 V and V
= 12 V
= 28 V
–
–
–
–
5.0
5.0
G_EN
G_EN
CC
CC
Operating VCC2 Supply Current (6)
IV
mA
mA
CC2OP
V
V
= 55 V and V
= 12 V and V
= 28 V
= 12 V
–
–
–
–
12
CC
CC
CC2
CC2
9.0
Additional Operating VCC2 Supply Current for Each Logic Input Pin Active
= 55 V and V
= 28 V (7)
IV
CC2LOG
V
CC
CC2
–
–
5.0
5.5
5.5
65
Undervoltage Shutdown VCC
Undervoltage Shutdown VCC2 (8)
Overvoltage Shutdown VCC
Overvoltage Shutdown VCC2
OUTPUT
UV
UV2
OV
4.0
4.0
57
5.0
5.0
61
31
V
V
V
V
OV2
29.5
35
Output Sink Resistance (Turned Off)
R
R
DS
DS
= 0 V (8)
SRC_HS
–
–
–
–
22
22
I
, V
discharge LSS = 50 mA
Output Source Resistance (Turned On)
= 20 V (8)
I
V
CP_OUT
charge HSS = 50 mA,
Charge Current of the External High-Side MOSFET Through GATE_HSn
Pin (9)
I
mA
V
CHARGE HSS
VMAX
–
–
100
–
200
18
Maximum Voltage (V
- V )
SRC_HS
GATE_HS
INH = Logic 1, I max = 5.0 mA
S
Notes
6. Logic input pin inactive (high impedance).
7. High-frequency PWM-ing (» 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to
remain within the package power handling rating.
8. The device may exhibit predictable behavior between 4.0 V and 5.5 V.
9. See Figure 5, page 12, for a description of charge current.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, -40C TA 125C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
Propagation Delay High Side and Low Side
= 5.0 nF, Between 50% Input to 50% Output (10) (see Figure 4)
t
ns
ns
ns
PD
–
–
–
200
80
300
180
180
C
LOAD
Turn-On Rise Time
= 5.0 nF, 10% to 90% (10)
t
R
C
,
,
(11) (see Figure 4)
(11) (see Figure 4)
LOAD
Turn-Off Fall Time
= 5.0 nF, 10% to 90% (10)
t
F
80
C
LOAD
10.
C
corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.
LOAD
11. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time).
33883
Analog Integrated Circuit Device Data
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Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
50%
50%
50%
IN_HS
or IN_LS
t
t
pd
pd
GATE_HS
or GATE_LS
50%
t
t
f
r
10% 90%
90% 10%
Figure 4. Timing Characteristics
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33883 is an H-bridge gate driver (or full-bridge pre-
driver) with integrated charge pump and independent high-
and low-side driver channels. It has the capability to drive
large gate-charge MOSFETs and supports high PWM
frequency. In sleep mode its supply current is very low.
FUNCTIONAL PIN DESCRIPTION
is in sleep mode. The device is enabled and fully operational
when the G_EN pin voltage is logic HIGH, typically 5.0 V.
SUPPLY VOLTAGE PINS (VCC AND VCC2)
The VCC and VCC2 pins are the power supply inputs to
the device. VCC is used for the output high-side drivers and
CHARGE PUMP OUT (CP_OUT)
the charge pump. VCC2 is used for the linear regulation. They
The CP_OUT pin is used to connect an external reservoir
capacitor for the charge pump.
can be connected together or independent with different
voltage values. The device can operate with VCC up to 55 V
and VCC2 up to 28 V.
CHARGE PUMP CAPACITOR PINS
The VCC and VCC2 pins have undervoltage (UV) and
overvoltage (OV) shutdown. If one of the supply voltage
drops below the undervoltage threshold or rises above the
overvoltage threshold, the gate outputs are switched LOW in
order to switch off the external MOSFETs. When the supply
returns to a level that is above the UV threshold or below the
OV threshold, the device resumes normal operation
(C1 AND C2)
The C1 and C2 pins are used to connect an external
capacitor for the charge pump.
LINEAR REGULATOR OUTPUT (LR_OUT)
The LR_OUT pin is the output of the internal regulator. It is
used to connect an external capacitor.
according to the established condition of the input pins.
INPUT HIGH- AND LOW-SIDE PINS
(IN_HS1, IN_HS2, AND IN_LS1, IN_LS2)
GROUND PINS
(GND_A, GND1 AND GND2)
The IN_HSn and IN_LSn pins are input control pins used
to control the gate outputs. These pins are 5.0 V CMOS-
compatible inputs with hysteresis. IN_HSn and IN_LSn
independently control GATE_HSn and GATE_LSn,
respectively.
These pins are the ground pins of the device. They should
be connected together with a very low impedance
connection.
During wake-up, the logic is supplied from the G_EN pin.
There is no internal circuit to prevent the external high-side
and low-side MOSFETs from conducting at the same time.
SOURCE OUTPUT HIGH-SIDE PINS (SRC_HS1
AND SRC_HS2)
The SRC_HSn pins are the sources of the external high-
side MOSFETs. The external high-side MOSFETs are
controlled using the IN_HSn inputs.
GATE HIGH- AND LOW-SIDE PINS
(GATE_HS1, GATE_HS2, AND GATE_LS1,
GATE_LS2)
The GATE_HSn and GATE_LSn pins are the gates of the
external high- and low-side MOSFETs. The external high-
and low-side MOSFETs are controlled using the IN_HSn and
IN_LSn inputs.
GLOBAL ENABLE (G_EN)
The G_EN pin is used to place the device in a sleep mode.
When the G_EN pin voltage is a logic LOW state, the device
33883
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Table 5. Functional Truth Table
Conditions
Sleep
G_EN IN_HSn IN_LSn Gate_HSn Gate_LSn
Comments
0
1
1
1
x
1
0
x
x
1
0
x
0
1
0
0
0
1
0
0
Device is in Sleep mode. The gates are at low state.
Normal mode. The gates are controlled independently.
Normal mode. The gates are controlled independently.
Normal
Normal
Undervoltage
The device is currently in fault mode. The gates are at
low state. Once the fault is removed, the 33883 recovers
its normal mode.
Overvoltage
1
1
1
x
1
x
x
x
1
0
0
x
0
x
0
The device is currently in fault mode. The gates are at
low state. Once the fault is removed, the 33883 recovers
its normal mode.
Overtemperature
on High-Side Gate Driver
The device is currently in fault mode. The high-side gate
is at low state. Once the fault is removed, the 33883
recovers its normal mode.
Overtemperature
on Low-Side Gate Driver
The device is currently in fault mode. The low-side gate
is at low state. Once the fault is removed, the 33883
recovers its normal mode.
x = Don’t care.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
The different voltages and current of the high-side gate
DRIVER CHARACTERISTICS
driver are illustrated in Figure 6. The output driver sources a
peak current of up to 1.0 A for 200 ns to turn on the gate. After
200 ns, 100 mA is continuously provided to maintain the gate
charged. The output driver sinks a high current to turn off the
gate. This current can be up to 1.0 A peak for a 100 nF load.
Figure 5 represents the external circuit of the high-side
gate driver. In the schematic, HSS represents the switch that
is used to charge the external high-side MOSFET through the
GATE_HS pin. LSS represents the switch that is used to
discharge the external high-side MOSFET through the
GATE_HS pin. A 180K internal typical passive discharge
resistance and a 18 V typical protection zener are in parallel
with LSS. The same schematic can be applied to the external
low-side MOSFET driver simply by replacing pin CP_OUT
with pin LR_OUT, pin GATE_HS with pin GATE_LS, and pin
SRC_HS with GND.
IN_HS1
0
HSSpulse_IN
0
CP_OUT
HSS DC_IN
HSS
0
I
GATE_HS
I
GATE_HS1
charge HSS
LSS_IN
HSSDC_IN
I
discharge LSS
I
charge HSS
1.0 A Peak
180
k
IN_HS1
LSS
100 mA Typical
HSSpulse_IN
0
0
18V
I
LSS_IN
discharge LSS
1.0 A Peak
SRC_HS1
I
GATE_HS
Figure 5. High-Side Gate Driver Functional Schematic
1.0 A Peak
100 mA Typical
0
-1.0 A Peak
Note GATE_HS is loaded with a 100 nF capacitor in the
chronograms. A smaller load will give lower peak and DC charge or
discharge currents.
Figure 6. High-Side Gate Driver Chronograms
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Analog Integrated Circuit Device Data
12
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
OPERATIONAL MODES
TURN-ON
TURN-OFF
For turn-on, the current required to charge the gate source
capacitor Ciss in the specified time can be calculated as
The peak current for turn-off can be obtained in the same
way as for turn-on, with the exception that peak current for fall
time, tf, is substituted for tr:
follows:
IP = Qg/tr = 80 nC/80 ns 1.0 A
IP = Qg/tf = 80 nC/80 ns 1.0 A
Where Qg is power MOSFET gate charge and tr is peak
current for rise time.
In addition to the dynamic current required to turn off or on
the MOSFET, various application-related switching scenarios
must be considered. These scenarios are presented in
Figure 7. In order to withstand high dV/dt spikes, a low
resistive path between gate and source is implemented
during the OFF-state.
Flyback spike charges low-
Flyback spike pulls down
high-side source VGS
Flyback spike charges low-
Flyback spike pulls down
high-side source VGS
side gate via C charge
side gate via C charge
.
.
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current I up to 2.0 A.
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current I up to 2.0 A.
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Delays turn-off of low-side
MOSFET.
Delays turn-off of high-
side MOSFET.
Causes increased uncon-
trolledturn-onofhigh-side
Causes increased uncon-
trolled turn-on of low-side
MOSFET.
VBAT
VBAT
VBAT
VBAT
C
C
C
C
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OFF
OFF
VGATE
-VDRN
GATE_HS
ILOAD
GATE_HS
ILOAD
GATE_HS
GATE_HS
ILOAD
ILOAD
L1
L1
L1
L1
C
C
iss
C
C
C
iss
iss
iss
C
C
C
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I
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VGATE
GATE_LS
OFF
GATE_LS
OFF
GATE_LS
GATE_LS
C
C
C
C
iss
iss
iss
iss
Driver Requirement:
Low Resistive Gate-
Source Path During
OFF-State
Driver Requirement:
Low Resistive Gate-
Source Path During
OFF-State. High Peak
Sink Current Capability
Driver Requirement:
High Peak Sink Current
Capability
Driver Requirement:
Low Resistive Gate-
Source Path During
OFF-State
Figure 7. OFF-State Driver Requirement
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
capacitor CCP_OUT provides peak current to the high-side
MOSFET through HSS during turn-on (3).
LOW-DROP LINEAR REGULATOR
The low-drop linear regulator is supplied by VCC2. If VCC2
exceeds 15.0 V, the output is limited to 14.5 V (typical).
V
LR_OUT
CP_OUT
The low-drop linear regulator provides the 5.0 V for the
logic section of the driver, the Vgs_ls buffered at LR_OUT, and
Tosc2
CCP
D1
C
the +14.5 V for the charge pump, which generates the
CP_OUT The low-drop linear regulator provides 4.0 mA
average current per driver stage.
CP_OUT
1
C1
C2
D2
In case of the full bridge, that means approximately
16 mA —8.0 mA for the high side and 8.0 mA for the low
side.
Tosc1
V
CC
Note: The average current required to switch a gate with
a frequency of 100 kHz is:
ICP = Qg * fPWM = 80 nC * 100 kHz = 8.0 mA
(3)
HSS
In a full-bridge application only one high side and one low
side switches on or off at the same time.
GATEH
GATE_HS
High-Side
MOSFET
LSS
Rg
CHARGE PUMP
The charge pump generates the high-side driver supply
voltage (CP_OUT), buffered at CCP_OUT. Figure 8 shows the
SRC_HS
charge pump basic circuit without load.
MOSFET
Low-Side
CP_OUT
(2)
D1
VLR_OUT
CCP
Pins
Ccp_ou
CCP_OUT
C2
OSC.
C1
Figure 9. High-Side Gate Driver
D2
(1)
VCC
Figure 8. Charge Pump Basic Circuit
When the oscillator is in low state [(1) in Figure 8], CCP is
charged through D2 until its voltage reaches VCC - VD2. When
the oscillator is in high state (2), CCP is discharged though D1
in CCP_OUT, and final voltage of the charge pump, VCP_OUT
,
is Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator
is about 330 kHz.
EXTERNAL CAPACITORS CHOICE
External capacitors on the charge pump and on the linear
regulator are necessary to supply high peak current
absorbed during switching.
Figure 9 represents a simplified circuitry of the high-side
gate driver. Transistors Tosc1 and Tosc2 are the oscillator-
switching MOSFETs. When Tosc1 is on, the oscillator is at
low level. When Tosc2 is on, the oscillator is at high level. The
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
C
C
CP_OUT
CP
CCP choice depends on power MOSFET characteristics
and the working switching frequency. Figure 10 contains two
diagrams that depict the influence of CCP value on VCP_OUT
Figure 11 depicts the simplified CCP_OUT current and
voltage waveforms. fPWM is the working switching frequency.
average voltage level. The diagrams represent two different
frequencies for two power MOSFETs, MTP60N06HD and
MPT36N06V.
Oscillator
High Side Turn On
in High
V
State Oscillator
CP_OUT
r
in Low
V
State
CP_OUT
Average
VCP_OUT
21
20 kHz
20.5
20
100 kHz
ICP_OUT
f
f=330kHz
PWM
19.5
19
18.5
18
Peak Current
5
25
45
65
85
Figure 11. Simplified CCP_OUT Current and Voltage
Waveforms
C
(nF)
CP
MTP60N06HD (Qg = 50 nC)
As shown above, at high-side MOSFET turn-on VCP_OUT
voltage decreases. This decrease can be calculated
according to the CCP_OUT value as follows:
21.5
21
20 kHz
Q
g
100 kHz
VCP_OUT
=
CCP_OUT
20.5
20
Where Qg is power MOSFET gate charge.
19.5
19
C
LR_OUT
CLR_OUT provides peak current needed by the low-side
MOSFET turn-on. VLR_OUT decrease is as follows:
18.5
5
25
45
65
85
Q
g
CCP(nF)
VLR_OUT
=
CLR_OUT
MTP36N06V (Qg = 40 nC)
Figure 10. VCP_OUT Versus CCP
TYPICAL VALUES OF CAPACITORS
The smaller the CCP value is, the smaller the VCP_OUT
value is. Moreover, for the same CCP value, when the
switching frequency increases, the average VCP_OUT level
In most working cases the following typical values are
recommended for a well-performing charge pump:
CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF
decreases. For most of the applications, a typical value of
33 nF is recommended.
These values give a typical 100 mV voltage ripple on
VCP_OUT and VLR_OUT with Qg = 50 nC.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
CTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
GATE PROTECTION
LOAD DUMP AND REVERSE BATTERY
The low-side driver is supplied from the built-in low-drop
regulator. The high-side driver is supplied from the internal
charge pump buffered at CP_OUT.
VCC and VCC2 can sustain load a dump pulse of 40 V and
double battery of 24 V. Protection against reverse polarity is
ensured by the external power MOSFET with the free-
wheeling diodes forming a conducting pass from ground to
The low-side gate is protected by the internal linear
regulator, which ensures that VGATE_LS does not exceed the
V
CC. Additional protection is not provided within the circuit.
To protect the circuit an external diode can be put on the
battery line. It is not recommended putting the diode on the
ground line.
maximum VGS. Especially when working with the charge
pump, the voltage at CP_OUT can be up to 65 V. The high-
side gate is clamped internally in order to avoid a VGS
exceeding 18 V.
TEMPERATURE PROTECTION
Gate protection does not include a fly-back voltage clamp
that protects the driver and the external MOSFET from a fly-
back voltage that can occur when driving inductive load. This
fly-back voltage can reach high negative voltage values and
needs to be clamped externally, as shown in Figure 12.
There is temperature shutdown protection per each half-
bridge. Temperature shutdown protects the circuitry against
temperature damage by switching off the output drivers. Its
typical value is 175°C with an hysteresis of 15°C.
DV/DT AT V
CC
LR_OUT
CP_OUT
VCC voltage must be higher than (SRC_HS voltage minus
M1
VCC
a diode drop voltage) to avoid perturbation of the high-side
driver.
OUT
IN
GATE_HS
Output
Driver
VGS < 14 V
In some applications a large dV/dt at pin C2 owing to
sudden changes at VCC can cause large peak currents
Under All
SRC_HS
Dcl
Conditions
flowing through pin C1, as shown in Figure 13.
L1
Inductive
Flyback Voltage
Clamp
For positive transitions at pin C2, the absolute value of the
minimum peak current, IC1min, is specified at 2.0 A for a
M2
tC1min duration of 600 ns.
OUT
IN
GATE_LS
Output
Driver
For negative transitions at pin C2, the maximum peak
current, IC1max, is specified at 2.0 A for a tC1max duration of
600 ns. Current sourced by pin C1 during a large dV/dt will
result in a negative voltage at pin C1 (Figure 13). The
minimum peak voltage VC1min is specified at -1.5 V for a
Figure 12. Gate Protection and Flyback Voltage Clamp
duration of tC1max = 600 ns. A series resistor with the charge
pump capacitor (Ccp) capacitor can be added in order to limit
the surge current.
33883
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
VCC
I
C1max
t
C1min
I(C1+C2)
0 A
tC1max
I
C1min
V(LR_OUT)
V(C1)
0 V
V
C1min
Figure 13. Limits of C1 Current and Voltage with Large Values of dV/dt
In the case of rapidly changing VCC voltages, the large dV/
DV/DT AT V
CC2
dt may result in perturbations of the high-side driver, thereby
forcing the driver into an OFF state. The addition of
capacitors C3 and C4, as shown in Figure 14, reduces the
dV/dt of the source line, consequently reducing driver
perturbation. Typical values for R3/R4 and C3/C4 are 10
and 10 nF, respectively.
When the external high-side MOSFET is on, in case of
rapid negative change of VCC2 the voltage (VGATE_HS
-
VSRC_HS) can be higher than the specified 18 V. In this case
a resistance in the SRC line is necessary to limit the current
to 5.0 mA max. It will protect the internal zener placed
between GATE_HS and SRC pins.
In case of high current (SRC_HS>100 mA) and high
voltage (>20 V) between GATE_HSX and SRC_HS an
external zener of 18 V is needed as shown in Figure 14.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
CAL APPLICATIONS
TYPICAL APPLICATIONS
VBAT VBOOST
33883
VCC
CCP_OUT
VCC
VCC2
G_EN
C1
CP_OUT
LR_OUT
VCC2
G_EN
M1
470 nF
CLR_OUT
470 nF
M3
R1
R2
50
50
R4
CCP
C1
C2
GATE_HS1
SRC_HS1
R3
18 V
33 nF
C2
10
C4
C3
10 nF
10
MCU
DC
10 nF
GATE_LS1
GATE_HS2
SRC_HS2
IN_HS1
IN_HS1
IN_LS1
IN_HS2
Motor
18 V
IN_LS1
IN_HS2
IN_LS2
GATE_LS2
GND
50
M4
M2
IN_LS2
50
Figure 14. Application Schematic with External Protection Circuit
33883
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the
98ASB42343B drawing number below. Dimensions shown are provided for reference ONLY.
DW SUFFIX
EG SUFFIX (PB-FREE)
20-PIN SOICW
PLASTIC PACKAGE
98ASB42343B
ISSUE J
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
SION HISTORY
PACKAGING DIMENSIONS
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
•
•
•
Implemented Revision History page
Updated to the current Freescale format and style
Added MCZ33883EG/R2 to the Ordering Information
Updated the package drawing to Rev. J
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
MAXIMUM RATINGS on page 4. Added note with instructions from www.freescale.com.
1/2007
9.0
•
•
•
•
Updated orderable part number from MCZ33883EG to MC33883HEG.
Updated Freescale form and style
Removed MC33883DW from the ordering information
Changed from Advance Information to Technical Data
10/2012
10.0
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC33883
Rev 10.0
10/2012
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