MC33897CTEF [NXP]
Transceiver, Physical Layer, Single Wire, CAN, 33.33 kbps or 83.33 kbps, SOIC 8, Rail;
| 型号： | MC33897CTEF |
| 厂家： | 
NXP |
| 描述： | Transceiver, Physical Layer, Single Wire, CAN, 33.33 kbps or 83.33 kbps, SOIC 8, Rail 电信 光电二极管 电信集成电路 |
| 文件： | 总19页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33897
Rev. 18.0, 4/2012
escale Semiconductor
Technical Data
Single Wire CAN Transceiver
33897
The 33897 series provides a physical layer for digital
communication using a Carrier Sense Multiple Access/Collision
Resolution (CSMA/CR) data link operating over a single wire medium.
This is more commonly referred to as single-wire Controller Area
Network (SWCAN).
SINGLE-WIRE CAN
TRANSCEIVER
The 33897 series operates directly from a vehicle's 12 V battery
system or a broad range of DC-power sources. It can operate at low or
high (33.33 kbps or 83.33 kbps) data rates. A high-voltage wake-up
feature allows the device to control the regulator used in support of the
MCU and other logic. The device includes a control pin that can be
used to put the module regulator into Sleep mode. The presence of a
defined wake-up voltage level on the bus will reactivate the control line
to turn the regulator and the system back ON.
EF (PB-FREE) SUFFIX
98ASB42565B
The device complies with the GMW3089v2.4 General Motors
Corporation specification.
14-PIN SOICN
Features
ORDERING INFORMATION
Temperature
• Waveshaping for low Electromagnetic Interference (EMI)
• Detects and automatically handles loss of ground
• Worst-case Sleep mode current of only 60 μA
• Current limit prevents damage due to bus shorts
• Built-in thermal shutdown on bus output
Device
Package
Range (T )
A
MCZ33897TEF/R2
*MC33897CTEF/R2
-40 to 125 °C
14 SOICN
• Protected against vehicular electrical transients
• Under-voltage lockout prevents false data with low battery
*Recommended device for all new designs
Power
source
Voltage
Regulator
Battery
EN
33897
VBATT
CNTL
V
CC
TXD
MCU
BUS
SWC Bus
RXD
MODE 0
MODE 1
LOAD
GND
4
Figure 1. 33897 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 - 2012. All rights reserved.
CE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Part No.
Load Voltage Sleep Mode
1.0 V Max
See Page
33897T
7
7
*33897CT
0.1 V Max
*Recommended device for all new designs
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
TXD BUS DRVR
MODE0
MODE1
HVWU Enable
BUS
Waveshaping Enable
Mode
Control
TXD Data
Disable
BUS RCVR
H
V
W
D
e
tect
RXD Data
Disable
TXD
RXD
Undervoltage
Detect
VBATT
Timer
OSC
Timers
Load Switch
LOAD
GND
CNTL
Figure 2. 33897 Simplified Internal Block Diagram
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
CONNECTIONS
PIN CONNECTIONS
33897
1
2
3
4
5
6
7
14
13
12
11
10
9
GND
TXD
GND
NC
MODE0
MODE1
RXD
BUS
LOAD
VBATT
CNTL
GND
NC
8
GND
Figure 3. 33897 Pin Connections
Table 2. Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section, beginning on page 12.
33897 Pin
Pin Name
Formal Name
Definition
Electrical Common Ground and Heat removal. A good thermal path will also reduce
the die temperature.
1, 7, 8, 14
GND
Ground
Data input here will appear on the BUS pin. A logic [0] will assert the bus, a logic [1]
will make the bus go to the recessive state.
2
3, 4
5
TXD
Transmit Data
Mode Control
Receive Data
These Pins control Sleep mode, Transmit Level, and Speed. They have weak pull-
downs.
MODE0,
MODE1
Open drain output of the data on BUS. A recessive bus = a logic [1], a dominant bus
= logic [0]. An external pull-up is required.
RXD
No internal connection to these Pins. Pin 13 can be connected to GND.
Provides a battery level logic signal.
6, 13
9
NC
No Connect
Control
Battery
Load
CNTL
VBATT
LOAD
Power input. An external diode is needed for reverse battery protection.
10
The external bus load resistor connects here to prevent bus pull-up in the event of
loss of module ground.
11
This pin connects to the bus through external components.
12
BUS
Bus
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Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Electrical Ratings
Supply Voltage
VBATT
VIN
VRXD
VCNTL
-0.3 to 40
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
V
V
V
V
V
Input Logic Voltage
RXD Pin Voltage
CNTL Pin Voltage
ESD Voltage(1)
Human Body Model
All Pins Except BUS
BUS Pin
V
ESD
±2000
±4000
±100
Machine Model
Thermal Ratings
Ambient Operating Temperature(1)
Junction Operating Temperature
Storage Temperature
T
-40 to 125
-40 to 150
-55 to 150
150
°C
°C
°C
A
T
J
TSTG
RθJA
Junction-to-Ambient Thermal Resistance
°C/W
°C
Peak Package Reflow Temperature During Reflow (2)
,
TPPRT
Note 3.
(3)
Notes
1. ESD testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω),
ZAP
ZAP
Machine Model (C
= 200 pF, R
= 0 Ω).
ZAP
ZAP
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and
enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions of -40 °C ≤ TA ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL
Quiescent Current
Sleep
5.0 V ≤ VBATT ≤ 13 V (4)
IQSLP
IQATDIS
IQATEN
–
–
–
45
–
60
4.0
9.0
μA
mA
mA
Awake with Transmitter Disabled
5.0 V ≤ VBATT ≤ 26.5 V
Awake with Transmitter Enabled
5.0 V ≤ VBATT ≤ 26.5 V
–
Under-voltage Shutdown
Under-voltage Hysteresis
VBATTUV
VUVHYS
TSD
4.0
0.1
–
–
5.0
0.5
V
V
Thermal Shutdown (5)
°C
5.0 V ≤ VBATT ≤ 26.5 V
150
10
–
–
190
20
Thermal Shutdown Hysteresis (5)
TSDHYS
°C
5.0 V ≤ VBATT ≤ 26.5 V
LOGIC I/O, MODE0, MODE1, TXD, RXD
Logic Input Low Level (MODE0, MODE1, and TXD)
VIL
VIH
IPD
V
V
5.0 V ≤ VBATT ≤ 26.5 V
–
2.0
10
–
–
–
–
–
0.8
–
Logic Input High Level (MODE0, MODE1, and TXD)
5.0 V ≤ VBATT ≤ 26.5 V
Mode Pin Pull-down Current (MODE0 and MODE1)
μA
V
Pin Voltage = 0.8 V, 5.0 V ≤ VBATT ≤ 26.5 V
50
Receiver Output Low (RXD)
VOL
IIN = 2.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V
0.45
CNTL
CNTL Output Low
VOLCNTL
V
V
IIN = 5.0 μA, 5.0 V ≤ VBATT ≤ 26.5 V
–
–
–
0.8
CNTL Output High
VOHCNTL
IOUT = 180 μA, 5.0 V ≤ VBATT ≤ 26.5 V
VBATT - 0.8
VBATT
Notes
4. After t
CNTLFDLY
5. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of -40 °C ≤ TA ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
LOAD
LOAD Voltage Rise (6)
VLDRISE
V
Normal Speed and Voltage Mode, Transmit High-
Voltage Mode, Transmit High Speed Mode
IIN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V
–
–
0.1
Sleep Mode
IIN = 7.0 mA
33897T
33897CT
–
–
–
–
1.0
0.1
IIN = 7.0 mA (7)
Loss of Battery
IIN = 7.0 mA
–
–
1.0
LOAD Leakage During Loss of Module Ground (8)
ILDLEAK
μA
μA
0.0 V ≤ VBATT ≤ 18 V
0.0 V ≤ VBATT ≤ 18 V
33897T
33897CT
0.0
-10
–
–
-90
10
BUS
Passive Out BUS Leakage
Passive In
ILEAK
0.0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V
Active In
0.0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V
BUS Leakage During Loss of Module Ground (9)
-5.0
-5.0
–
–
5.0
5.0
ILKAI
-10
0.0
0.0 V ≤ VBATT ≤ 18 V
0.0 V ≤ VBATT ≤ 18 V
33897T
33897CT
IBLKLOG
–
–
10
-90
High Voltage Wake-up Mode Output High Voltage
V
12 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
33897T
V
9.7
9.9
–
–
–
12.5
12.5
HVWUOHF
33897CT
V
HVWUOHO
5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω
Lesser of V
-
VBATT
BAT
1.5 or 9.7
High Speed Mode Output High Voltage
VOHHS
V
V
8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω
4.2
–
5.1
5.1
Normal Mode Output High Voltage
6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω
VNOHF
VNOHO
4.4
–
–
Lesser of VBATT
1.6 or 4.4
-
Lesser of VBATT
or 5.1
Notes
6. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode.
The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4.
7. 33897CT removes the diode drop during Sleep mode.
8. LOAD pin is at system ground voltage.
9. BUS pin is at system ground voltage
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
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CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of -40 °C ≤ TA ≤ 125 °C, unless otherwise stated. Voltages are relative to GND, unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS (CONTINUED)
BUS Low Voltage
VOL
V
mA
V
5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
-0.2
–
–
0.2
Short-circuit BUS Output Current
IBSC
Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V
-350
-100
Input Threshold
Awake
2.0
–
2.2
5.0 V ≤ VBATT ≤ 26.5 V
VBIA
VBISF
VBISO
Sleep
6.6
–
–
7.9
12 V ≤ VBATT ≤ 26.5 V
Sleep
Lesser of 6.6 V or
Lesser of 7.9 V or
5.0 V ≤ VBATT < 12 V
V
- 4.3
V
- 3.25
BATT
BATT
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of -40 °C ≤ TA ≤ 125 °C, unless otherwise stated. Voltages are relative to GND unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS
Normal Speed Rising Output Delay
tDLYNORMRO
μs
200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs
Measured from TXD = VIL to VBUS as follows:
2.0
–
6.3
Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (10)
Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (10)
Max Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (10)
Min Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (10)
Normal Speed Falling Output Delay
tDLYNORMFO
μs
200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs
Measured from TXD = VIH to VBUS as follows:
1.8
–
8.5
Max Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (10)
Min Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (10)
Max Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (10)
Min Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (10)
High Speed Rising Output Delay
tDLYHSRO
μs
75 Ω ≤ RL ≤ 135 Ω, 0.0 μs ≤ Load Time Constants ≤ 1.5 μs,
0.1
–
1.7
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = VIL to VBUS as follows:
Max Time to VBUS = 3.7 V (11)
Min Time to VBUS = 1.0 V (11)
High Speed Falling Output Delay
tDLYHSFO
μs
75 Ω ≤ RL ≤ 135 Ω, 0.0 μs ≤ Load Time Constants ≤ 1.5 μs,
0.04
–
3.0
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = VIH to VBUS as follows:
Max Time to VBUS = 1.0 V (11)
Min Time to VBUS = 3.7 V (11)
Notes
10.
11.
V
V
is the voltage at the BUSMOD node in Figure 6, page 13.
BUSMOD
is the voltage at the BUS pin in Figure 7, page 14.
BUS
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions of -40 °C ≤ TA ≤ 125 °C, unless otherwise stated. Voltages are relative to GND unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS (CONTINUED)
High Voltage Rising Output Delay
tDLYHVRO
μs
200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs
Measured from TXD=VIL to VBUS as follows:
Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (12)
Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (12)
Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V (12)
2.0
2.0
2.0
–
–
–
6.3
6.3
18
High Voltage Falling Output Delay
tDLYHVFO
μs
200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs,
12.0 V ≤ VBATT ≤ 26.5 V
Measured from TXD=VIH to VBUS as follows:
Max Time to VBUSMOD = 1.0 V (12)
Min Time to VBUSMOD = 3.7 V (12)
1.8
1.8
–
–
14
14
RECEIVER RXD
Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V)
t
μs
μs
RDLY
Awake
0.2
10
–
–
1.0
70
Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V)
t
RDLYSL
Sleep
CNTL
CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V)
t
300
–
1000
ms
CNTLFDLY
Notes
12.
V
is the voltage at the BUSMOD node in Figure 6, page 13.
BUSMOD
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
tDLYNORMFO
tDLYNORMRO
VIH
TXD
VIL
VNOHF
VBUSMOD
*
Bus
VBIA
VBIA
VBUSMOD
*
VIH
RXD
VIL
tRDLY
tRDLY
is the voltage at the BUSMOD node in Figure 7.
* V
BUSMOD
Figure 4. TXD, Bus and RXD Waveforms in Normal Mode
T
t
DLYHSFO
DLYHSRO
V
IH
TXD
V
IL
V
NOHF
V
BUS *
Bus
V
BIA
V
BIA
V
BUS *
V
IH
RXD
V
IL
t
t
RDLY
RDLY
* V
is the voltage at the BUS pin in Figure 8.
BUS
Figure 5. TXD, Bus and RXD Waveforms in High Speed Mode
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33897 Series is intended for use as a physical layer
device in a Single Wire CAN communications bus.
system communications where the radiated EMI of the higher
rate could be an issue.
Communications takes place from a single pin over a single
wire using a common ground for a current return path. Two
data rates are available, with the high rate used for factory or
assembly line communications and the lower for actual
Two pins control the mode of operation (sleep, low speed,
high speed, and high voltage wake-up).
FUNCTIONAL PIN DESCRIPTION
The 33897 Series is intended to be used with an MCU to
control its operation and to process and generate the data for
the bus.
MCU comes out of reset, before the driving signals have
been configured as outputs.
RXD DATA
GROUND PINS
The data received on the bus is translated to logic levels
on this pin. This pin is a logic high when the bus is in the
recessive state (near zero volts) and is logic low when the
bus is in either the normal or high voltage dominant state.
The four ground pins are not only for electrical conduction,
their number and locations at each of the four corners serve
also to remove heat from the IC. The biggest benefit of this is
obtained by putting a lot of copper on the PCB in this area
and, if ground is an internal layer, by adding numerous
plated-through connections to it with the largest diameter
holes the layout can use.
This is an open-drain type of output that requires an
external resistor to pull it up. When the device is in sleep
mode, the output will be off unless a high voltage wake-up
level is detected on the bus. If the wake-up level is detected,
the output will be driven by the data on the bus. If the level of
the data returns to normal level, the output will return to off
after a short delay unless a non-sleep mode condition is set
by the MCU.
TXD DATA
The data driven onto the SWCAN bus is inverted from the
TXD pin. A “1” driven on TXD will result in an undriven
(recessive) state (bus at near zero volts). When the TXD pin
is low, the output goes to a driven state. The voltage and
waveshaping in the driven state is determined by the levels
on the MODE0 and MODE1 Pins (refer to Table 6).
LOAD SWITCH
This switch is ON in all operating modes unless a loss of
ground is detected. If this happens, the switch is opened and
the resistor normally attached to its pin will no longer pass
current to or from the bus.
Table 6. Mode Control Logic Levels
Logic Level
Operation
MODE0
MODE1
CNTL OUTPUT
Sleep mode
0
0
1
1
0
1
0
1
This logic level signal is used to control a VCC regulator.
When the output is low, the VCC regulator is expected to
shutdown. This is normally used to shut down the MCU and
all the devices powered by VCC when the IC is in Sleep mode.
This is done to save power. When the part is taken out of the
Sleep mode by the higher than normal bus voltage, this pin is
asserted high and the VCC regulator brings its output up to the
regulated level. This starts the MCU, which controls the mode
of the IC. The MCU must change the mode signals to non-
Sleep mode levels in order to keep this pin from going low.
There is a delay to allow the MCU to fully wake-up and take
control after the high voltage signaling is removed before the
level on this output returns low. After a delay time, even if the
bus is at high voltage, the IC will return to Sleep mode if both
MODE pins are low.
High voltage wake-up mode
High speed mode
Normal mode
MODE CONTROL
The MODE pins control the transmitter filtering and BUS
voltage and the IC Sleep mode operation. Table 6 shows the
mode versus the logic levels on MODE0 and MODE1.
The MODE0 and MODE1 pins have a weak pull-down in
the IC so that in case the pins are not driven, the device will
enter the Sleep mode. This is usually the situation as the
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM COMPONENTS
VBATT INPUT
BUS I/O
This power input is not reverse battery protected and
should use an external diode to protect it from damage due
to reverse battery if this protection is desired. The voltage
drop of the diode must be taken into consideration when the
operating range of the system is being determined. This
diode is generally used to protect the entire module from
reverse battery and should be selected accordingly.
This input/output may require electrostatic discharge
(ESD) and/or EMI external circuitry. A set of components is
shown in the simplified application diagrams on page 15. The
value of the capacitor should be adjusted downward in direct
proportion to the added capacitance of the ESD or EMI
circuits. The series resistance of the inductor should be kept
below 3.5 Ω to prevent its voltage drop from significantly
degrading system noise margins.
FUNCTIONAL BLOCK DIAGRAM COMPONENTS
TIMER OSC
TXD BUS DRVR
This circuit generates a 500 kHz signal to be used for
internal logic. It is the reference for some of the required
delays.
This circuit drives the BUS. It can drive it with the higher
voltage wake-up signals when enabled by the Mode Control
circuit. It can also provide waveshaping for reduced EMI or
not provide it for the higher data rate mode. The actual data
is received on TXD at CMOS logic levels, then translated by
this circuit to the necessary operating voltages.
TIMERS
This circuit contains the timing logic used to hold the CNTL
active for the required time after the conditions for sleep
mode have been met. It is also used to keep the TXD driver
active for a period of time after it has generated a passive
level on the bus.
UNDER-VOLTAGE DETECT
This circuit monitors internal operating voltage to assure
proper operation of the part. If a low-voltage condition is
detected, it sends a signal to disable the BUS RCVR and
TXD BUS DRVR circuits. This prevents incorrect data from
being put on the bus or sent to the MCU.
MODE CONTROL
This circuit contains the control logic for the various
operating modes and conditions required for the IC.
LOAD SWITCH
The LOAD switch provides a path for an external resistor
connected to the BUS to be connected to ground. When a
loss of ground is detected, this switch is opened to prevent
the current that would normally be flowing to the ground from
the module from going back through the load resistor and
raising the bus level. The circuit is opened when the voltage
between GND and VBATT becomes too low as would be the
case if module ground were lost.
BUS RCVR
This circuit translates the levels on the BUS pin to a CMOS
level indicating the presence of a logic [0] or a logic [1]. It also
determines the presence of a high voltage wake-up (HVWU)
signal that is passed to Mode Control and Timers circuits. An
analog filter is used to “de-glitch” the high voltage wake-up
signal and prevent false exits from the Sleep mode.
BUS LOADING PARAMETERS
VBATT
100 pF
1.0 kΩ
47 μH
33897
BUSMOD
BUS
6.49 kΩ
6.49 kΩ
C
= 100 pF + (n -1) 220 pF
R=
NOM
(n -1)
LOAD
GND
Note: The letter ’n’ represents the number of nodes in the system.
Figure 6. Transmitter Delays in Normal and Transmit High Voltage Wake-up Modes
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CTIONAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM COMPONENTS
33897
BUS
6.49 kΩ
(n -1)
6.49 kΩ
130 Ω
C
= (n) 220 pF
R=
NOM
LOAD
GND
Note: The letter ’n’ represents the number of nodes in the system.
Figure 7. Transmitter Delays in Transmit High Speed Mode
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33897 can be used in applications where the module
includes a regulator that has the capability of going into Sleep
mode by having an Enable pin. See Figure 8. When the
module’s regulator is in Sleep mode, the module is turned off.
The module waits for a defined wake-up voltage level on the
bus. This wake-up voltage will activate the CNTL line, which
enables the regulator and turns the module back ON. This
feature allows the module to be more energy efficient since
the current consumption is significantly lowered when it goes
into sleep mode.
Power
Source
Battery
V
CC
100 nF
4.7 μF
Voltage
Regulator
100 pF
EN
VBATT
CNTL
1.0 kΩ
47 μH
2.7 kΩ
V
10 kΩ
CC
BUS
SWC BUS
TXD
47 pF
RXD
MODE0
LOAD
MCU
6.49 kΩ
MODE1
4
GND
33897
Figure 8. 33897 Typical Application Schematic
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Analog Integrated Circuit Device Data
Freescale Semiconductor
15
KAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the
98ASB42565B drawing number below. Dimensions shown are provided for reference ONLY.
EF (Pb-FREE) SUFFIX
14-pin SOICN
98ASB42565B
ISSUE J
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Analog Integrated Circuit Device Data
Freescale Semiconductor
16
PACKAGING
PACKAGE DIMENSIONS
EF (Pb-FREE) SUFFIX
14-pin SOICN
98ASB42565B
ISSUE J
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
SION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
•
•
Converted to Freescale format
Added A & B Versions
Updated Device Variation Table, and Note “* Recommended device for all new designs”
Added EF (Pb-Free) Devices, and higher soldering temperature
5/2005
9.0
•
•
•
Implemented Revision History page
Updated Simplified Application Diagrams
Updated Typical Application Schematic
8/2005
10.0
12/2005
1/2006
•
Added 33897C and D versions and Timing Diagrams
11.0
12.0
•
•
Updated Table 4, Static Electrical Characteristics - LOAD and BUS parameters
Updated Ordering Information.
•
Removed “Unless otherwise noted” from Static Electrical Characteristics & Dynamic Electrical
Characteristics table introductions
6/2006
8/2006
13.0
14.0
•
•
Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1.
Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes per Errata
MC33897TER, Revision 3 and specifying ESD variations
•
•
Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/
R2, MC33897DLEF/R2, and PC33897DLEF/R2
Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/
R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1.
Updated Device Variations on page 2 for “T” suffix products
Split out Human Body Model on page 5 to differentiate between T and non-T versions
Added Under-voltage Hysteresis on page 6
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 5. Added note with instructions to obtain this information from
www.freescale.com.
10/2006
15.0
•
•
•
•
6/2007
1/2011
•
Removed watermark, “Advance Information” from page 1.
16.0
17.0
•
•
•
•
Improved HBM ESD All Pins Except BUS to ±2.0 kV on MC33897CT
Added MC33897CTEKF/R2 to the ordering information
Removed all 8-Pin SOICN device information
Changed Short-circuit BUS Output Current to -100 mA (Approved by GM)
4/2012
•
Updated Quiescent Current IQSLP to 60 μA max.
18.0
33897
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits on the
information in this document.
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© 2012 Freescale Semiconductor, Inc.
Document Number: MC33897
Rev. 18.0
4/2012
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