MC33978AEKR2 [NXP]
Switch Detection Interface, 22-switches, 3.3 V / 5.0 V SPI , SOICW-EP 32, Reel;
| 型号： | MC33978AEKR2 |
| 厂家： | 
NXP |
| 描述： | Switch Detection Interface, 22-switches, 3.3 V / 5.0 V SPI , SOICW-EP 32, Reel |
| 文件： | 总65页 (文件大小：1022K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33978
Rev. 7.0, 8/2017
NXP Semiconductors
Advance Information
22 channel multiple switch detection
interface with programmable wetting
current
33978
34978
MULTIPLE SWITCH DETECTION INTERFACE
The 33978 is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI). This
SMARTMOS device also features a 24-to-1 analog multiplexer for reading the
input channels as analog inputs. The analog selected input signal is buffered and
provided on the AMUX output pin for the MCU to read.
Independent programmable wetting currents are available as needed for the
application. A battery and temperature monitor are included in the IC and
available via the AMUX pin.
ES SUFFIX (PB-FREE)
98ASA00656D
EK SUFFIX (PB-FREE)
98ASA10556D
The 33978 device has two modes of operation, Normal and Low-power mode
(LPM). Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors the change of state on
the switches. The LPM provides low quiescent current, which makes the 33978
ideal for automotive and industrial products requiring low sleep-state currents.
32-PIN QFN (WF-TYPE)
32-PIN SOICW-EP
Applications
• Automotive
• Heating ventilation and air conditioning (HVAC)
• Lighting
Features
• Central gateway/in-vehicle networking
• Gasoline engine management
• Industrial
• Fully functional operation 4.5 V ≤ VBATP ≤ 36 V
• Full parametric operation 6.0 V ≤ VBATP ≤ 28 V
• Operating switch input voltage range from -1.0 V to 36 V
• Eight programmable inputs (switches to battery or ground)
• 14 switch-to-ground inputs
• Selectable wetting current (2, 6, 8, 10, 12, 14, 16, or 20 mA)
• Interfaces directly to an MCU using 3.3 V / 5.0 V SPI protocol
• Selectable wake-up on change of state
• Programmable logic control (PLC)
• Process control, temperature control
• Input-output control (I/O Control)
• Single board computer
• Ethernet switch
• Typical standby current IBATP = 30 μA and IDDQ = 10 μA
• Active interrupt (INT_B) on change-of-switch state
• Integrated battery and temperature sensing
Notes
1. The IC is functional from 4.5 V < VBATP < 6.0 V, but with degraded parametric values. The parameters may not meet the minimum and maximum
specifications when VBATP drops below 6.0 V.
VDDQ
Battery
Power
Supply
33978
SG1
Battery
VBATP
SP0
Power
Supply
WAKE_B
MCU
SP1
VDDQ
INT_B
CS_B
INTB
SP7
SG0
CSB
MISO
MISO
MOSI
SCLK
MOSI
SCLK
AN0
AMUX
SG12
SG13
EP
GND
Figure 1. 33978 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2017.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General IC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Battery voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Power sequencing conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Input functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Oscillator and timer control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Temperature monitor and control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6 WAKE_B control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7 INT_B functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 AMUX functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.10 SPI control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3 Abnormal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
5
6
7
8
9
10 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
33978
NXP Semiconductors
2
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable part variations
Temperature (T )
Part number
Package
SOICW-EP 32 pins
Notes
A
MC33978EK
MC33978AEK
MC33978AES
MC34978EK
MC34978AEK
MC34978AES
Notes
(2), (3)
-40 °C to 125 °C
(2)
QFN (WF-TYPE) 32 pins
SOICW-EP 32 pins
(2), (3)
(2)
-40 °C to 105 °C
QFN (WF-TYPE) 32 pins
2. To order parts in tape and reel, add the R2 suffix to the part number.
3. Refer to errata MC33978ER ER01 for details on current conditions present on the MC33978EK and MC34978EK devices only.
33978
3
NXP Semiconductors
2
Internal block diagram
Inputs
Internal 2.5 V
VBATP
SG0
VBATP
VBATP, VDDQ
Internal 2.5 V/5.0 V
Power On Reset
Bandgap reference
Sleep Power
VBATP
VDDQ
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
GND
EP
SG0
Internal 2.5 V
To SPI
4.0 V
reference
SG1
Oscillator
and
VBATP
Clock control
SG2
SG5
VBATP
Internal 2.5 V
Temperature
Monitor and
Control
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
VDDQ
125 kΩ
Internal 2.5 V
SG5
To SPI
4.0 V
reference
WAKE_B
INT_B
WAKE_B control
1/6 Ratio
Internal 2.5 V
VDDQ
SGx
125 kΩ
VBATP
Interrupt
control
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
Internal 2.5 V
SG13
VDDQ
To SPI
4.0 V
reference
SPI Interface and
Control
125 kΩ
CS_B
SCLK
MOSI
MISO
SP0-7
VBATP
VDDQ
Mux control
24
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
VDDQ
+
-
AMUX
SP0
To SPI
4.0 V
SP1
reference
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (2.0 mA)
SP7
Figure 2. 33978 internal block diagram
33978
NXP Semiconductors
4
3
Pin connections
3.1
Pinout
Transparent Top View
GND
MOSI
SCLK
CS_B
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VBATP
MISO
VDDQ
AMUX
INT_B
SP7
SP6
SP5
SP4
SG13
SG12
SG11
SG10
SG9
SG8
SG7
WAKE_B
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
SP7
24
23
22
21
20
19
18
17
SP0
3
4
SP6
SP1
SP2
SP3
SG0
SG1
SG2
SG3
5
SP5
6
7
Exposed Pad
SP4
8
EK Suffix
Only
9
SG13
SG12
SG11
SG10
10
11
12
13
14
15
16
9
10 11 12 13 14 15 16
Figure 3. 33978 SOICW-EP and QFN (WF-Type) pinouts
3.2
Pin definitions
Table 2. 33978 pin definitions
Pin number Pin number
Pin name Pin function
Formal name
Definition
SOIC
QFN
1
2
3
4
29
GND
MOSI
SCLK
CS_B
Ground
Input/SPI
Input/SPI
Input/SPI
Ground
Ground for logic, analog
30
SPI Slave In
Serial Clock
Chip Select
SPI control data input pin from the MCU
SPI control clock input pin
31
32
SPI control chip select input pin
5–8
25–28
1 - 4
21 - 24
SP0–3
SP4–7
Programmable
Switches 0–7
Input
Input
Switch to programmable input pins (SB or SG)
Switch-to-ground input pins
9–15,
18–24
5 - 11
14 - 20
SG0–6,
SG7–13
Switch-to-Ground
Inputs 0–13
Battery supply input pin. Pin requires external reverse battery
protection
16
17
12
13
VBATP
Power
Battery Input
Wake-up
Open drain wake-up output. Designed to control a power supply
enable pin. Input used to allow a wake-up from an external event.
WAKE_B
Input/Output
Open-drain output to MCU. Used to indicate an input switch change
of state. Used as an input to allow wake-up from LPM via an external
INT_B falling event.
29
25
INT_B
Input/Output
Interrupt
30
31
26
27
AMUX
VDDQ
Output
Input
Analog Multiplex Output Analog multiplex output.
3.3 V/5.0 V supply. Sets SPI communication level for the MISO driver
Voltage Drain Supply
and I/O level buffer
33978
5
NXP Semiconductors
Table 2. 33978 pin definitions (continued)
Pin number Pin number
Pin name Pin function
Formal name
Definition
SOIC
QFN
32
28
MISO
EP
Output/SPI
Ground
SPI Slave Out
Exposed Pad
Provides digital data from the 33978 to the MCU.
It is recommended that the exposed pad is terminated to GND (pin 1)
and system ground.
33978
NXP Semiconductors
6
4
General product characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Electrical ratings
VBATP
Description (rating)
Min.
Max.
Unit
Notes
Battery Voltage
Supply Voltage
-0.3
-0.3
40
V
V
VDDQ
7.0
CS_B, MOSI,
MISO, SCLK
SPI Inputs/Outputs
-0.3
7.0
V
SGx, SPx
AMUX
Switch Input Range
AMUX
-14(4)
-0.3
38
7.0
7.0
40
V
V
V
V
INT_B
INT_B
-0.3
WAKE_B
WAKE_B
-0.3
ESD Voltage
• Human Body Model (HBM) (VBATP versus GND)
MC33978 and MC34978
MC33978A and MC34978A
• Human Body Model (HBM) (All other pins)
• Machine Model (MM)
• Charge Device Model (CDM) (Corners pins)
• Charge Device Model (CDM) (All other pins)
V
±2000
±4000
±2000
±200
±750
±500
ESD1-2
(5)
V
V
V
V
V
ESD1-3
ESD3-1
ESD2-1
ESD2-2
Contact Discharge
V
V
V
• VBATP(8)
• WAKE_B (series resistor 10 kΩ)
• SGx and SPx pins with 100 nF capacitor (100 Ω series R) based on external
protection performance(7)
±8000
±8000
±15000
ESD5-3
ESD5-4
ESD6-1
(6)
V
V
±8000
ESD6-2
• SGx and SPx pins with 100 nF capacitor (50 Ω series R)
Notes
4. Minimum value of -18 V is guaranteed by design for switch input voltage range (SGx, SPx).
5. ESD testing is performed in accordance AEC Q100, with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model
(MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM).
6. CZAP = 330 pF, RZAP = 2.0 kΩ (Powered and unpowered) / CZAP = 150 pF, RZAP = 330 Ω (Unpowered)
7. ±15000V capability in powered condition, ±8000V in all other conditions.
8. External component requirements at system level:
Cbulk = 100uF aluminum electrolytic capacitor
Cbypass= 100nF ±37 % ceramic capacitor
Reverse blocking diode from Battery to VBATP (0.6 V < VF < 1 V). See Figure 23, Typical application diagram.
33978
7
NXP Semiconductors
4.2
Thermal characteristics
Table 4. Thermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal ratings
Operating Temperature
• Ambient
TA
TJ
-40
-40
125
150
°C
• Junction
TSTG
TPPRT
Storage Temperature
-65
–
150
–
°C
°C
Peak Package Reflow Temperature During Reflow
Thermal resistance
Junction-to-Ambient, Natural Convection, Single-Layer Board
(9) (10)
RΘJA
RΘJB
RΘJC
• 32 SOIC-EP
• 32 QFN
79
94
°C/W
°C/W
°C/W
°C/W
,
Junction-to-Board
• 32 SOIC-EP
• 32 QFN
(11)
(12)
(13)
9.0
12
Junction-to-Case (Bottom)
• 32 SOIC-EP
3.0
2.0
• 32 QFN
Junction-to-Package (Top), Natural convection
Ψ
• 32 SOIC-EP
• 32 QFN
11
2.0
JT
Package dissipation ratings
Thermal Shutdown
TSD
• 32 SOIC-EP
• 32 QFN
155
3.0
185
15
°C
°C
Thermal Shutdown Hysteresis
• 32 SOIC-EP
TSDH
• 32 QFN
Notes
9. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
10. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board,
respectively.
11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
12. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
33978
NXP Semiconductors
8
4.3
Operating conditions
This section describes the operating conditions of the device. Conditions apply to the following data, unless otherwise noted.
Table 5. Operating conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
VBATP
VDDQ
Ratings
Min.
4.5
Max.
36
Unit
V
Notes
Battery Voltage
Supply Voltage
3.0
5.25
V
CS_B, MOSI,
MISO, SCLK
SPI Inputs / Outputs
3.0
5.25
V
SGx, SPx
AMUX, INT_B
WAKE_B
Switch Input Range
AMUX, INT_B
WAKE_B
-1.0
0.0
0.0
36
5.25
36
V
V
V
4.4
Electrical characteristics
4.4.1
Static electrical characteristics
Table 6. Static electrical characteristics
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Notes
Power input
VBATP Supply Voltage POR
VBATP(POR)
2.7
3.3
3.8
V
• VBATP Supply Power on Reset voltage.
VBATP Undervoltage Rising Threshold
VBATP Undervoltage Hysteresis
VBATPUV
VBATPUVHYS
VBATPOV
—
250
32
4.3
—
—
—
4.5
500
37
V
mV
V
VBATP Overvoltage Rising Threshold
VBATP Overvoltage Hysteresis
VBATPOVHYS
1.5
3.0
V
VBATP Supply Current
IBAT(ON)
—
7.0
12
mA
µA
• All switches open, Normal mode, Tri-state disabled (all channels)
VBATP Low-power Mode Supply Current (polling disabled)
• Parametric VBATP, 6.0 V < VBATP < 28 V
IBATP,IQ,LPM,P
IBATP,IQ,LPM,F
—
—
—
—
40
40
• Functional Low VBATP, 4.5 V < VBATP < 6.0 V
VBATP Polling Current
(14)
IPOLLING,IQ
—
—
—
—
20
µA
uA
• Polling 64 ms, 11 inputs of wake enabled
Normal mode (IVDDQ
)
IVDDQ,NORMAL
• SCLK, MOSI, WakeB = 0 V, CS_B, INT_B =VDDQ, no SPI
communication, AMUX selected no input
500
Logic Low-power mode Supply Current
• SCLK, MOSI = 0 V, CS_B, INT_B, WAKE_B = VDDQ, no SPI
communication
IVDDQ,LPM
—
—
—
10
µA
V
Ground Offset
VGNDOFFSET
-1.0
1.0
• Ground offset of Global pins to IC ground
VDDQUV
VDDQ Undervoltage Falling Threshold
VDDQ Undervoltage Hysteresis
2.2
—
—
2.8
V
VDDQUVHYS
150
350
mV
33978
9
NXP Semiconductors
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Notes
Switch input
Leakage (SGx/SPx pins) to GND
ILEAKSG_GND
—
—
—
—
2.0
2.0
2.4
μA
• Inputs tri-stated, analog mux selected for each input, voltage at
SGx = VBATP
Leakage (SGx/SPx pins) to Battery
ILEAKSG_BAT
μA
• Inputs tri-stated, analog mux selected for each input, voltage at
SGx = GND
SG Sustain current / Mode 0 Wetting current
• VBATP 6.0 to 28 V
ISUSSG
mA
1.6
2.0
SG Sustain current / Mode 0 Wetting current LV
• VBATP 4.5 V to 6.0 V
(15)
ISUSSGLV
ISUSSB
mA
mA
1.0
—
2.4
SB Sustain current / Mode 0 Wetting current
1.75
2.2
2.85
Wetting current level (SG & SB)
• Mode 1 = 6mA
6
• Mode 2 = 8mA
8
• Mode 3 = 10mA
• Mode 4 = 12mA
• Mode 5 = 14mA
• Mode 6 = 16mA
• Mode 7 = 20mA
10
12
14
16
20
IWET
IWETSG
IWETSGLV
IWETSB
—
—
mA
SG wetting current tolerance
• Mode 1 to 7
-10
—
10
%
SG wetting current tolerance LV (VBATP 4.5 to 6.0V)(15)
• Mode 1 = 6mA
2.0
2.0
2.0
2.0
2.0
2.0
2.0
—
—
—
—
—
—
—
6.6
8.8
• Mode 2 = 8mA
• Mode 3 = 10mA
• Mode 4 = 12mA
• Mode 5 = 14mA
• Mode 6 = 16mA
• Mode 7 = 20mA
11.0
13.2
15.4
17.6
22.0
mA
SB wetting current tolerance
• Mode 1 to 7
%
-20
—
—
—
20
10
(16), (17)
(18), (19)
(20)
IMATCH(SUS)
IMATCH(WET)
VICTHR
Sustain Current Matching Between Channels
Wetting Current Matching Between Channels
Switch Detection Threshold
%
%
V
—
—
6.0
4.3
3.7
4.0
Switch Detection Threshold Low Battery
• VBATP 4.5 V to 6.0 V
0.55 *
VBATP
VICTHRLV
—
4.3
V
(21)
VICTHRLPM
VICTHRH
Switch Detection Threshold Low-power Mode (SG only)
Switch Detection Threshold Hysteresis (4.0 V threshold)
100
80
—
—
300
300
mV
mV
Input Threshold 2.5 V,
VICTH2P5
2.0
2.5
3.0
V
• Used for Comp Only and for AMUX Hardwired Select (SG1/2/3)
Low-power Mode Polling Current SG
• VBATP 4.5 V to 28 V
IACTIVEPOLLSG
IACTIVEPOLLSB
0.7
1.0
2.2
1.44
2.85
mA
mA
Low-power Mode Polling Current SB
1.75
33978
NXP Semiconductors
10
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Notes
Digital interface
Tri-state Leakage Current (MISO)
IHZ
-2.0
—
—
—
2.0
DDQ * 0.7
—
μA
V
• VDDQ = 0.0 to VDDQ
Input Logic Voltage Thresholds
• SI, SCLK, CS_B, INT_B
VDDQ
0.25
*
VINLOGIC
V
Input Logic Hysteresis
VINLOGICHYS
300
mV
• SI, SCLK, CS_B, INT_B
VINLOGICWAKE
VINWAKEBHYS
Input Logic Voltage Threshold WAKE_B
Input Logic Voltage Hysteresis WAKE_B
0.8
1.25
—
1.7
V
200
800
mV
SCLK / MOSI Input Current
• SCLK / MOSI = 0 V
ISCLK, IMOSI
ISCLK, IMOSI
ICS_BH
-3.0
30
—
—
3.0
100
10
µA
µA
µA
kΩ
V
SCLK / MOSI Pull-down Current
• SCLK / MOSI = VDDQ
CS_B Input Current
• CS_B = VDDQ
-10
40
—
CS_B Pull-up Resistor to VDDQ
• CS_B = 0.0 V
RCS_BL
125
—
270
VDDQ
MISO High-side Output Voltage
• IOHMISO = -1.0 mA
VOHMISO
VDDQ – 0.8
MISO Low-side Output Voltage
• IOLMISO = 1.0 mA
VOLMISO
—
—
—
—
0.4
20
V
CIN
Input Capacitance on SCLK, MOSI, Tri-state MISO (GBD)
pF
Analog MUX output
Input Offset Voltage When Selected as Analog
• EK suffix (SOICW)
(22)
VOFFSET
-10
-15
—
—
10
15
mV
• ES suffix (QFN at TA = -40 °C to 25 °C)
Analog Operational Amplifier Output Voltage
• Sink 1.0 mA
VOLAMUX
—
—
—
50
—
mV
V
Analog Operational Amplifier Output Voltage
• Source 1.0 mA
VOHAMUX
VDDQ – 0.1
AMUX selectable outputs
Chip Temperature Sensor Coefficient
—
8.0
—
—
mV/°C
%
Temp-Coeff
VBATSNSACC
Battery Sense (SG5 config) Accuracy
• Battery voltage (SG5 input) divided by 6
• Accuracy over full temperature range
-5.0
5.0
Divider By 6 coefficient accuracy
(23)
VBATSNSDIV
-3.0
—
3.0
%
• Offset over operating voltage range (VBATP=6.0 V to 28 V)
33978
11
NXP Semiconductors
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol
INT_B
Characteristic
Min.
Typ.
Max.
Units
Notes
INT_B Output Low Voltage
• IOUT = 1.0 mA
VOLINT
—
0.2
0.5
V
INT_B Output High Voltage
• INT_B = Open-circuit
VOHINT
RPU
VDDQ – 0.5
—
125
—
VDDQ
270
1.0
V
Pull-up Resistor to VDDQ
40
—
kΩ
µA
Leakage Current INT_B
ILEAKINT_B
Temperature limit
tFLAG
• INT_B pulled up to VDDQ
Temperature Warning
• First flag to trip
105
120
135
°C
(24)
(24)
tLIM
tLIM(HYS)
Temperature Monitor
155
5.0
—
—
185
15
°C
°C
Temperature Monitor Hysteresis
WAKE_B
RWAKE_B(RPU)
WAKE_B Internal pull-up Resistor to VDDQ
40
125
—
270
kΩ
WAKE_B Voltage High
VWAKE_B(VOH)
VDDQ -1.0
VDDQ
V
• WAKE_B = Open-circuit
WAKE_B Voltage Low
VWAKE_B(VOL)
—
—
—
—
0.4
1.0
V
• WAKE_B = 1.0 mA (RPU to VBATP = 16 V)
WAKE_B Leakage
IWAKE_BLEAK
µA
• WAKE_B pulled up to VBATP = 16 V through 10 kΩ
Notes
14. Guaranteed by design
15. During low voltage range operation SG wetting current may be limited when there is not enough headroom between VBATP and SG pin voltage.
16. (ISUS(MAX)– ISUS(MIN)) X 100/ISUS(MIN)
17. Sustain current source (SGs only)
18. (IWET(MAX) – IWET(MIN)) X 100/IWET(MIN)
19. Wetting current source (SGs only)
20. The input comparator threshold decreases when VBATP ≤ 6.0 V.
21. SP (as SB) only use the 4.0 V VICTHR for LPM wake-up detection.
22. For applications requiring a tight AMUX offset through the whole operating range, it is recommended to use the MC33978AEK or MC34978AEK
(SOICW package) variant.
23. Calibration of divider ratio can be done at VBAT = 12 V, 25 °C to achieve a higher accuracy. See Figure 4 for AMUX offset linearity waveform
through the operating voltage range.
24. Guaranteed by characterization in the Development Phase, parameter not tested.
33978
NXP Semiconductors
12
4.4.2
Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics
TA = -40 °C to +125 °C. VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a
100 pF load on MISO, unless otherwise noted.
Symbol
General
Parameter
Min.
Typ.
Max.
Units
Notes
POR to Active time
tACTIVE
Switch input
tPULSE(ON)
250
340
450
µs
• Undervoltage to Normal mode
Pulse Wetting Current Timer
• Normal mode
17
—
20
—
—
—
58
23
18.5
15
ms
µs
%
Interrupt Delay Time
• Normal mode
tINT-DLY
tPOLLING_TIMER
tINT-TIMER
Polling Timer Accuracy
• Low-power mode
—
Interrupt Timer Accuracy
• Low-power mode
—
15
%
tACTIVEPOLLSGTI
Tactivepoll Timer SG
49.5
66.5
µs
ME
Tactivepoll Timer SB
• SBPOLLTIME=0
• SBPOLLTIME=1
tACTIVEPOLLSBTI
1.0
49.5
1.2
58
1.4
66.5
ms
µs
ME
Input Glitch Filter Timer
• Normal mode
tGLITCHTIMER
5.0
1.0
—
18
µs
LPM Debounce Additional Time
• Low-power mode
tDEBOUNCE
AMUX output
AMUXVALID
1.2
1.4
ms
AMUX Access Time (Selected Output to Selected Output)
• CMUX = 1.0 nF, Rising edge of CS_B to selected
(26)
—
—
—
μs
μs
AMUX Access Time (Tristate to ON)
AMUXVALIDTS
—
20
• CMUX = 1.0 nF, Rising edge of CS_B to selected
Oscillator
OSCTOLLPM
OSCTOLNOR
Interrupt
Oscillator Tolerance at 192 kHz in Low-power Mode
Oscillator Tolerance Normal Mode at 4.0 MHz
-15
-15
—
—
15
15
%
%
INT Pulse Duration
INTPULSE
90
100
110
µs
• Interrupt occurs or INT_B request
SPI interface
fOP
Transfer Frequency
—
—
—
8.0
—
MHz
ns
SCLK Period
• Figure 7 - 1
tSCK
tLEAD
tLAG
160
Enable Lead Time
• Figure 7 - 2
140
50
—
—
—
—
—
—
ns
ns
ns
Enable Lag Time
• Figure 7 - 3
SCLK High Time
• Figure 7 - 4
tSCKHS
56
33978
13
NXP Semiconductors
Table 7. Dynamic electrical characteristics (continued)
TA = -40 °C to +125 °C. VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a
100 pF load on MISO, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
SPI interface (continued)
SCLK Low Time
tSCKLS
tSUS
tHS
56
16
20
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• Figure 7 - 5
MOSI Input Setup Time
• Figure 7 - 6
MOSI Input Hold Time
• Figure 7 - 7
—
MISO Access Time
• Figure 7 - 8
tA
116
100
116
—
MISO Disable Time (25)
• Figure 7 - 9
tDIS
—
MISO Output Valid Time
• Figure 7 - 10
tVS
—
MISO Output Hold Time (No cap on MISO)
• Figure 7 - 11
tHO
20
—
Rise Time
(25)
(25)
tRO
30
• Figure 7 - 12
Fall Time
tFO
—
30
• Figure 7 - 13
CS_B Negated Time
• Figure 7 - 14
tCSN
500
—
WAKE-UP
(27)
tCSB_WAKEUP
LPM mode wake-up time triggered by edge of CS_B
—
755
1000
µs
Notes
25. Guaranteed by characterization.
26. AMUX settling time to be within the 10 mV offset specification. AMUXVALID is dependant of the voltage step applied on the input SGx/SPx pin or
the difference between the first and second channel selected as the multiplexed analog output. See Figure 9 for a typical AMUX access time VS
voltage step waveform.
27. The parameter is guaranteed at VBATP = 4.5 V to 28 V.
33978
NXP Semiconductors
14
Figure 4. Divide by 6 coefficient accuracy
LPM CLK
SG_Pin
tglitchTIMER
Input Glitch
filter timer
500ns
tINT-DLY
INT_B
Figure 5. Glitch filter and interrupt delay timers
LPM CLK
SG_Pin
tINT-DLY
INTPulse
INT_B
Figure 6. Interrupt pulse timer
33978
15
NXP Semiconductors
3
14
CSb
1
4
2
8
SCLK
5
10
9
11
DON'T
CARE
MISO
MOSI
DATA
MSB OUT
MSB IN
LSB OUT
12 13
7
6
DATA
LSB IN
Figure 7. SPI timing diagram
+5.0 V
4.0 V
VDDQ
1kohm
MISO
1.0 V
0 V
MISO
1kohm
9
CS_B
Figure 8. MISO loading for disable time measurement
AMUX settling time vs voltage step
Figure 9. AMUX access time waveform
33978
NXP Semiconductors
16
5
General description
The 33978 is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is
transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). Individually selectable input currents are available
in Normal and Low-power (LPM) modes, as needed for the application.
It also features a 24-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX
output pin for the MCU to read. A battery and temperature monitor are included in the IC and available via the AMUX pin.
The 33978 device has two modes of operation, Normal and Low-power mode (LPM). Normal mode allows programming of the device and
supplies switch contacts with pull-up or pull-down current as it monitors the change of state of switches. The LPM provides low quiescent
current, which makes the 33978 ideal for automotive and industrial products requiring low sleep-state currents.
5.1
Features
•
•
•
•
Fully functional operation from 4.5 V to 36 V
Full parametric operation from 6.0 V to 28 V
Low-power mode current IBATP = 30 μA and IDDQ = 10 μA
22 Switch detection channels
•
•
14 Switch-to-Ground (SG) inputs
Eight Programmable switch (SP) inputs
•
Switch-to-Ground (SG) or Switch-to-Battery (SB)
•
•
•
•
Operating switch input voltage range from -1.0 V to 36 V
Selectable wetting current (2, 6, 8, 10, 12, 14, 16, or 20 mA)
Programmable wetting operation (Pulse or Continuous)
Selectable wake-up on change of state
•
24 to 1 Analog Multiplexer
•
•
•
•
Buffered AMUX output from SG/SP channels
Integrated divider by 6 on SG5 for battery voltage sensing
Integrated die temperature sensing through AMUX output
Two or three pin hardwire AMUX selection.
•
•
Active interrupt (INT_B) on change-of-switch state
Direct MCU Interface through 3.3 V / 5.0 V SPI protocol
33978
17
NXP Semiconductors
5.2
Functional block diagram
33978 Functional Internal Block Diagram
Switch Status Detection
Input Power
VBATP
Battery Supply
VDDQ
Logic Supply
8 x Programmable Switch
14 x Switch to Ground
SG0 – SG13
SP0 – SP7
Bias & References
Switch to Ground (SG)
Only
Switch to Ground (SG)
Switch to Battery (SB)
1.25 V internal Bandgap
4.0 V SW detection reference.
Selectable Wetting Current Level
192 kHz
LPM Oscillator
4.0 MHz
Oscillator
Pulse/Continuous Wetting Current
Analog Multiplexer (AMUX)
Logic and Control
WAKE_B I/O
INT_B I/O
24 to 1 SPI AMUX select
Hardwire selectable
SPx/SGx Inputs to AMUX
Battery Voltage sensing (divided by 6 )
Die Temperature Sensing
SPI Serial Communication & Registers
Fault Detection and Protection
Over Temperature
OV Detection
Protection
Modes of Operation
Normal Mode
Low Power Mode
VBATP UV detect
SPI Error detect
SPI communication/
Switch status read
Programmable Polling/
Interrupt Time
HASH error detect
Figure 10. Functional block diagram
33978
NXP Semiconductors
18
6
General IC functional description
The 33978 device interacts with many connections outside the module and near the end user. The IC detects changes in switch state and
reports the information to the MCU via the SPI protocol. The input pins generally connected to switches located outside the module and
in proximity to battery in car harnesses. Consequently, the IC must have some external protection including an ESD capacitor and series
resistors, to ensure the energy from the various pulses are limited at the IC.
The IC requires a blocking diode be used on the VBATP pin to protect from a reverse battery condition. The inputs are capable of surviving
reverse battery without a blocking diode and also contain an internal blocking diode from the input to the power supply (VBATP), to ensure
there is no backfeeding of voltage/current into the IC, when the voltage on the input is higher than the VBATP pin.
6.1
Battery voltage ranges
The 33978 device operates from 4.5 V ≤ VBATP ≤ 36 V and is capable to withstand up to 40 V. The IC operates functionally from
4.5 V < VBATP < 6.0 V, but with degraded parametrics values. Voltages in excess of 40 V must be clamped externally in order to protect
the IC from destruction. The VBATP pin must be isolated from the main battery node by a diode.
6.1.1
Load dump (overvoltage)
During load dump the 33978 operates properly up to the VBATP overvoltage. Voltages greater than load dump (~32 V) causes the current
sources to be limited to ~2.0 mA, but the register values are maintained. Upon leaving this overvoltage condition, the original setup is
returned and normal operation begins again.
6.1.2
Jump start (double battery)
During a jump start (double battery) condition, the device functions normally and meets all the specified parametric values. No internal
faults are set and no abnormal operation noted as a result of operating in this range.
6.1.3
Normal battery range
The normal voltage range is fully functional with all parametrics in the given specification.
6.1.4
Low-voltage range (degraded parametrics)
In the VBATP range between 4.5 V to 6.0 V the 33978 functions normally, but has some degraded parametric values. The SPI functions
normally with no false reporting. The degraded parameters are noted in Table 6 and Table 7. During this condition, the input comparator
threshold is reduced from 4.0 V and remain ratiometrically adjusted, according to the battery level.
6.1.5
Undervoltage lockout
During undervoltage lockout, the MISO output is tri-stated to avoid any data from being transmitted from the 33978. Any CS_B pulses are
ignored in this voltage range. If the battery enters this range at any point (even during a SPI word), the 33978 ignores the word and enters
lockout mode. A SPI bit register is available to notify the MCU that the 33978 has seen an undervoltage lockout condition once the battery
is high enough to leave this range.
6.1.6
Power on reset (POR) activated
The Power on Reset is activated when the VBATP is within the 2.7 V to 3.8 V range. During the POR all SPI registers are reset to default
values and SPI operation is disabled. The 33978 is initialized after the POR is de-asserted. A SPI bit in the device configuration register
is used to note a POR occurrence and all SPI registers are reset to the default values.
6.1.7
No operation
The device does not function and no switch detection is possible.
33978
19
NXP Semiconductors
VBATP
(IC Level)
Battery Voltage
(System Level)
41 V
Over Voltage
37 V
40 V
Overvoltage
Functional
36 V
28 V
Load Dump
29 V
Normal Mode
Full Parametrics
Normal
Battery
6.0 V
4.5 V
7.0 V
Low Battery
5.5 V
Degraded Parametrics
Undervoltage lockout
POR
4.8 V
3.7 V
3.8 V
2.7 V
Reset
No Operation
0 V
0 V
Figure 11. Battery voltage range
6.2
Power sequencing conditions
The chip uses two supplies as inputs into the device for various usage. The pins are VBATP and VDDQ. The VBATP pin is the power
supply for the chip where the internal supplies are generated and power supply for the SG circuits. The VDDQ pin is used for the I/O buffer
supply to talk to the MCU or other logic level devices, as well as AMUX. The INT_B pin is held low upon POR until the IC is ready to
operate and communicate. Power can be applied in various ways to the 33978 and the following states are possible:
6.2.1
VBATP before VDDQ
The normal condition for operation is the application of VBATP and then VDDQ. The chip begin to operate logically in the default state but
without the ability to drive logic pins. When the VDDQ supply is available the chip is able to communicate correctly. The IC maintains its
logical state (register settings) with functional behavior consistent with logical state. No SPI communications can occur.
6.2.2
VDDQ before VBATP
The VDDQ supply in some cases may be available before the VBATP supply is ready. In this scenario, there is no back feeding current into
the VDDQ pin that could potentially turn on the device into an unknown state. VDDQ is isolated from VBATP circuits and the device is off
until VBATP is applied; when VBATP is available the device powers up the internal rails and logic within tACTIVE time. Communication is
undefined until the tACTIVE time and becomes available after this time frame.
6.2.3
VBATP okay, VDDQ lost
After power up, it is possible that the VDDQ may turn off or be lost. In this case, the chip remains in the current state but is not able to
communicate. After the VDDQ pin is available again, the chip is ready to communicate.
6.2.4
VDDQ okay, VBATP lost
After power up, the VBATP supply could be lost. The operation is consistent as when VDDQ is available before VBATP
.
33978
NXP Semiconductors
20
7
Functional block description
7.1
State diagram
IC OFF
VBATP applied
RESET
SPI RESET
command
VBAT too low:
POR
VBAT applied >
por
VBATP > UV
threshold
UV
OV / OT
Iwet-> Isus
VBATP > OV
or OT
Wait 50 μs
Read fuses
VBATP
UV
<
Not VBATP > OV
or OT
Run
Normal Mode
Detect change in switch
status (opn/close)
Wake
Event
SPI CMD
Polling time expires
Low Power
Mode
Polling
Polling timer initiates
Figure 12. 33978 state diagram
7.1.1
State machine
After power up, the IC enters into the device state machine, as illustrated in Figure 12. The voltage on VBATP begins to power the internal
oscillators and regulator supplies. The POR is based on the internal 2.5 V digital core rail. When the internal logic regulator reaches
approximately 1.8 V (typically 3.3 V on the VBATP node), the IC enters into the UV range. Below the POR threshold, the IC is in RESET
mode where no activity occurs.
33978
21
NXP Semiconductors
7.1.2
UV: undervoltage lockout
After the POR circuit has reset the logic, the IC is in undervoltage. In this state, the IC remembers all register conditions, but is in a lockout
mode, where no SPI communication is allowed. The AMUX is inactive and the current sources are off. The user does not receive a valid
response from the MISO, as it is disabled in this state. The chip oscillators (4.0 MHz for most normal mode activities, 192 kHz for LPM,
and limited normal mode functions) are turned on in the UV state. The chip moves to the Read fuses state when the VBATP voltage rises
above the UV threshold (~4.3 V rising). The internal fuses read in approximately 50 μs and the chip enters the Normal mode.
7.1.3
Normal mode
In normal mode, the chip operates as selected in the available registers. Any command may be loaded in normal mode, although not all
(Low-power mode) registers are used in the Normal mode. All the LPM registers must be programmed in Normal mode as the SPI is not
active in LPM. The Normal mode of the chip is used to operate the AMUX, communicate via the SPI, Interrupt the IC, wetting and sustain
currents, as well as the thresholds available to use. The WAKE_B pin is asserted (low) in Normal mode and can be used to enable a power
supply (ENABLE_B). Various fault detections are available in this mode including overvoltage, overtemperature, thermal warning, SPI
errors, and Hash faults.
7.1.4
Low-power mode
When the user needs to lower the IC current consumption, a low-power mode is used. The only method to enter LPM is through a SPI
word. After the chip is in low-power mode, the majority of circuitry is turned off including most power rails, the 4.0 MHz oscillator, and all
the fault detection circuits. This mode is the lowest current consumption mode on the chip. If a fault occurs while the chip is in this mode,
the chip does not see or register the fault (does not report via the SPI when awakened). Some items may wake the IC in this mode,
including the interrupt timer, falling edge of INT_B, CS_B, or WAKE_B (configurable), or a comparator only mode switch detection.
7.1.5
Polling mode
The 33978 uses a polling mode which periodically (selectable in LPM config register) interrogates the input pins to determine in what state
the pins are, and decide if there was a change of state from when the chip was in Normal mode. There are various configurations for this
mode, which allow the user greater flexibility in operation. This mode uses the current sources to pull-up (SG) or down (SB) to determine
if a switch is open or closed. More information is available in section 7.2, “Low-power mode operation".
In the case of a low VBATP, the polling pauses and waits until the VBATP rises out of UV or a POR occurs. The pause of the polling ensures
all of the internal rails, currents, and thresholds are up at the required levels to accurately detect open or closed switches. The chip does
not wake-up in this condition and simply waits for the VBATP voltage to rise or cause a POR.
After the polling ends, the chip either returns to the low-power mode, or enters Normal mode when a wake event was detected. Other
events may wake the chip as well, such as the falling edge of CS_B, INT_B, or WAKE_B (configurable). A comparator only mode switch
detection is always on in LPM or Polling mode, so a change of state for those inputs would effectively wake the IC in Polling mode as well.
If the Wake-up enable bits are disable on all channels (SG and SP) the device will not wake up with a change of state on any of the input
pins; in this case, the device will disable the polling timer to allow the lowest current consumption during low-power mode.
7.2
Low-power mode operation
Low-power mode (LPM) is used to reduce system quiescent currents. LPM may be entered only by sending the Enter Low-power mode
command. All register settings programmed in Normal mode are maintained while in LPM.
The 33978 exits LPM and enter Normal mode when any of the following events occur:
• Input switch change of state (when enabled)
• Interrupt timer expire
• Falling edge of WAKE_B (as set by the device configuration register)
• Falling edge of INT_B (with VDDQ = 5.0 V)
• Falling edge of CS_B (with VDDQ = 5.0 V)
• Power-ON Reset (POR)
The VDDQ supply may be removed from the device during LPM, however removing VDDQ from the device disables a wake-up from falling
edge of INT_B and CS_B. The IC checks the status of VDDQ after a falling edge of WAKE_B (as selected in the device configuration
register), INT_B and CS_B. The IC returns to LPM and does not report a Wake event, if VDDQ is low. If the VDDQ is high, the IC wakes up
and reports the Wake event. In cases where CS_B is used to wake the device, the first MISO data message is not valid.
33978
NXP Semiconductors
22
The LPM command contains settings for two programmable registers: the interrupt timer and the polling timer, as shown in Table 26. The
interrupt timer is used as a periodic wake-up timer. When the timer expires, an interrupt is generated and the device enters Normal mode.
The polling timer is used periodically to poll the inputs during Low-power mode to check for change of states. The tACTIVEPOLL time is the
length of time the part is active during the polling timer to check for change of state. The Low-power mode voltage threshold allows the
user to determine the noise immunity versus lower current levels that polling allows. Figure 14 shows the polling operation.
When polling and Interrupt timer coincide, the Interrupt timer wakes the device and the polling does not occur. When an input is determined
to meet the condition Open (when entering LPM), yet while Open (on polling event) the chip does not continue the polling event for that
input(s) to lower current in the chip (Figure 13 shows SG, SB is logically the same).
Compare voltage to initial
(Delta > 0.25 or > 4.0v)
End Polling (current off if
no change detected)
LPM Voltage threshold
(~0.25v)
Voltage on SG pin
55µs
Polling timer
(64ms def)
Figure 13. Low-power mode polling check
Go To LPM
CS_B
64ms (config)
Normal
Normal
Mode
LPM
Polling Time
Polling startup
Tactive time
20us
78us
58us
330uA
IC Current
20uA
0uA
X * 1mA SG
(2mA SB)
Load
Current
Figure 14. Low-power mode typical timing
33978
23
NXP Semiconductors
VBATP
VDDQ
Wake up from Interrupt
Timer expire
WAKE_B
INT_B
CS_B
SGn
Wake up from
Closed Switch
Power – up
Normal Mode
Tri-state
Command
Sleep
Command
Normal
Mode
Sleep
Command
Normal
Mode
Sleep
Command
Sleep Mode
Sleep Mode
Figure 15. Low-power mode to normal mode operation
7.3
Input functional block
The SGx pins are switch-to-ground inputs only (pull-up current sources).
The SPx pins are configurable as either switch to ground or switch to battery (pull-up and pull-down current sources).
The input is compared with a 4.0 V (input comparator threshold configurable) reference. Voltages greater than the input comparator
threshold value are considered open for SG pins and closed for SB configuration.
Voltages less than the input comparator threshold value are considered closed for SG pins and open for the SB configurations.
Programming features are defined in the SPI control register definition section of this data sheet.
The input comparator has hysteresis with the thresholds based on the closing of the switch (falling on SG, rising on SB).
The user must take care to keep power conditions within acceptable limits (package is capable of 2.0 W). Using many of the inputs with
continuous wetting current levels causes overheating of the IC and may cause an overtemperature (OT) event to occur.
33978
NXP Semiconductors
24
VBATP
Pre-reg = ~8v
6 - 20
mA
2.0
mA
1.0mA
(LPM)
To AMUX
To SPI
4.0 V ref comparator
Or
250mV Delta V
Or
2.5v Comparator only
Figure 16. SG block diagram
33978
25
NXP Semiconductors
VBATP
Pre-reg
6 - 20
mA
2.0
mA
1.0mA
(LPM)
To SPI
4.0 V ref comparator
2.0
mA
2
0mA
(LPM)
6 - 20
mA
Figure 17. SP block diagram
7.4
Oscillator and timer control functional block
Two oscillators are generated in this block. A 4.0 MHz clock is used in Normal mode only, as well as a Low-power mode 192 kHz clock,
which is on all the time. All timers are generated from these oscillators. The oscillator accuracy is 15 % for both, the 4.0 MHz clock and
the 192 kHz clock. No calibration is needed and the accuracy is over voltage and temperature.
7.5
Temperature monitor and control functional block
The device has multiple thermal limit (tLIM) cells to detect thermal excursions in excess of 155 °C. The tLIM cells from various locations on
the IC are logically ORed together and communicated to the MCU as one tLIM fault. When the tLIM value is seen, the wetting current is
lowered to 2.0 mA until the temperature has decreased beyond the tLIM(HYS) value (the sustain current remains on or as selected). A
hysteresis value of 15 °C exists to keep the device from cycling.
A thermal flag also exists to alert the system to increasing temperatures more than approximately 120 °C.
7.6
WAKE_B control functional block
The WAKE_B pin can operate as an open-drain output or a wake-up input. In the Normal Mode, the WAKE_B pin is LOW. In the Low-
power mode, the WAKE_B pin is pulled HIGH. The WAKE_B pin has an internal pull-up to VDDQ supply with an internal series diode to
allow an external pull-up to VBATP if required.
33978
NXP Semiconductors
26
As an input, in Low-power mode with the WAKE_B pin pulled HIGH, when commanded LOW by MCU, the falling edge of WAKE_B places
the MC33978 in Normal mode. In Low-power mode if VDDQ goes low, the WAKE_B pin can still wake the device based on the status of
the WAKE_B bit in the device configuration register, this allows the user to pull the WAKE_B pin up to VBATP such that it can be used in
VDDQ off setup.
As an output, WAKE_B pin can drive either an MCU input or the EnableB of a regulator (possibly for VDDQ). WAKE_B is driven Low during
Normal mode regardless of the state of VDDQ. When the 33978 is in LPM, the WAKE_B pin is released and is expected to be pulled up
internally to VDDQ or externally to VBATP. When a valid wake-up event is detected, the 33978 wakes up from LPM and the WAKE_B is
driven Low (regardless of the state of VDDQ).
7.7
INT_B functional block
INT_B is an input/output pin in the 33978 device to indicate an interrupt event has occurred, as well as receiving interrupts from other
devices when the INT_B pins are wired ORed. The INT_B pin is an open-drain output with an internal pull-up to VDDQ. In Normal mode,
a switch state change triggers the INT_B pin (when enabled). The INT_B pin and INT_B bit in the SPI register are latched on the falling
edge of CS_B. This permits the MCU to determine the origin of the interrupt. When two 33978 devices are used, only the device initiating
the interrupt has the INT_B bit set. The INT_B pin and INTflg bit are cleared 1.0 μs after the falling edge of CS B. The INT_B pin does not
clear with the rising edge of CS_B if a switch contact change has occurred while CS_B was Low.
In a multiple 33978 device system with WAKE_B High and VDDQ on (Low-power mode), the falling edge of INT_B places all 33978s in
Normal mode. The INT_B has the option of a pulsed output (pulsed low for INTpulse duration) or a latched low output. The default case is
the latched low operation; the pulsed option is selectable via the SPI.
An INT_B request by the MCU can be done by a SPI word and results in an INTPULSE of 100 μs duration on the INT_B pin.
The chip causes an INT_B assertion for the following cases:
1. A change of state is detected
2. Interrupt timer expires
3. Any Wake-up event
4. Any faults detected
5. After a POR, the INT_B pin states asserted during startup until the chip is ready to communicate
7.8
AMUX functional block
The analog voltage on switch inputs may be read by the MCU using the analog command (Table 43). Internal to the IC is a 24-to-1 analog
multiplexer. The voltage present on the selected input pin is buffered and made available on the AMUX output pin. The output pin is
clamped to a maximum of VDDQ regardless of the higher voltages present on the input pin. After an input has been selected as the analog,
the corresponding bit in the next MISO data stream is logic [0]. When selecting a channel to be read as analog input, the user can also
set the current level allowed in the AMUX output. Current level can be set to the programmed wetting current for the selected channel or
set to high-impedance as defined in Table 42.
When selecting an input to be sent to the AMUX output, that input is not polled or a wake-up enabled input from Low-power mode. The
user should set the AMUX to “No input selected” or “Temp diode” before entering Low-power mode. The AMUX pin is not active during
Low-power mode. The SG5 pin can also be used as a VBATP sense pin. An internal resistor divider of 1/6 is provided for conditioning the
VBATP higher voltage to a level within the 0 V to VDDQ range.
Besides the default SPI input selection method, the AMUX has two hardwire operation such that the user can select an specific input
channel by physically driving the SG1, SG2 or SG3 pin (HW 3-bit), or by driving the SG1 and SG2 pins (HW 2-bit) as shown in Table 9
and Table 10. When using the AMUX hardwired options, the SG1, SG2, and SG3 inputs use a 2.5 V input voltage threshold to read a
logic 0 or logic 1.
Table 8 shows the AMUX selection methods configurable by the Aconfig0 and Aconfig1 bits in the Device Configuration register.
Table 8. AMUX selection method
Aconfig1
Aconfig0
AMUX Selection method
0
0
1
1
0
1
0
1
SPI (def)
SPI
HW 2-bit
HW 3-bit
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27
NXP Semiconductors
Table 9. AMUX hardware 3-bit
Pins [SG3, SG2, SG1]
Output of AMUX
000
001
010
011
100
101
110
111
SG0
SG5
SG6
SG7
SG8
SG9
Temperature Diode
Battery Sense
Table 10. AMUX hardware 2-bit
Pins [SG2, SG1]
Output of AMUX
00
01
10
11
SG0
SG5
SG6
SG7
Since the device is required to meet the ±1.0 V offset with ground, it is imperative that the user bring the sensor ground back to the 33978
when using the AMUX for accurate measurements to ensure any ground difference does not impact the device operation.
7.9
Serial peripheral interface (SPI)
The 33978 contains a serial peripheral interface consisting of Serial Clock (SCLK), Serial Data Out (MISO), Serial Data In (MOSI), and
Chip Select Bar (CS_B). The SPI interface is used to provide configuration, control, and status functions; the user may read the registers
contents as well as read some status bits of the IC. This device is configured as an SPI slave.
All SPI transmissions to the 33978 must be done in exact increments of 32 bits (modulo 0 is ignored as well). The 33978 contains a data
valid method via SCLK input to keep non-modulo-32 bit transmissions from being written into the IC. The SPI module also provides a daisy
chain capability to accommodate MOSI to MISO wrap around (see Figure 21).
The SPI registers have a hashing technique to ensure that the registers are consistent with the programmed values. If the hashed value
does not match the register status, a SPI bit is set as well as an interrupt to alert the MCU to this issue.
7.9.1
Chip select low (CS_B)
The CS_B input selects this device for serial transfers. On the falling edge of CS_B, the MISO pin is released from tri-state mode, and all
status information are latched in the SPI shift register. While CS_B is asserted, register data is shifted in the MOSI pin and shifted out the
MISO pin on each subsequent SCLK. On the rising edge of CS_B, the MISO pin is tri-stated and the fault register reloaded (latched) with
the current filtered status data. To allow sufficient time to reload the fault registers, the CS_B pin must remain low for a minimum of tCSN
prior to going high again.
The CS_B input contains a pull-up current source to VDDQ to command the de-asserted state should an open-circuit condition occur.
This pin has threshold compatible voltages allowing proper operation with microprocessors using a 3.3 V to 5.0 V supply.
7.9.2
Serial clock (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has a threshold compatible voltages allowing
proper operation with microprocessors using a 3.3 V to 5.0 V supply.
When CS_B is asserted, both the Master Microprocessor and this device latch input data on the rising edge of SCLK. The SPI master
typically shifts data out on the falling edge of SCLK, while this device shifts data out on the rising edge of SCLK, to allow more time to
drive the MISO pin to the proper level.
33978
NXP Semiconductors
28
This input is used as the input for the modulo-32 bit counter validation. Any SPI transmissions which are NOT exact multiples of 32 bits
(i.e. clock edges) is treated as an illegal transmission. The entire frame is aborted and no information is changed in the configuration or
control registers.
7.9.3
Serial data output (MISO)
The MISO output pin is in a tri-state condition when CS_B is negated. When CS_B is asserted, MISO is driven to the state of the MSB of
the internal register and start shifting out the requested data from the MSB to the LSB. This pin supplies a “rail to rail” output, depending
on the voltage at the VDDQ pin.
7.9.4
Serial data input (MOSI)
The MOSI input takes data from the master microprocessor while CS_B is asserted. The MSB is the first bit of each word received on
MOSI and the LSB is the last bit of each word received on MOSI. This pin has threshold level compatible input voltages allowing proper
operation with microprocessors using a 3.3 V to 5.0 V (VDDQ) supply.
CS_B
Control word
Configure words
MOSI/
SCLK
...
20
31 30 29 28 27 26 25 24 23 22 21
3
2
1
0
MISO
INTflg
Fault Status
Switch Status Register
SG/SP input status
Figure 18. First SPI operation (after POR)
CS_B
CS_B
Next Control word
Next Configure words
Control word
Configure word
MOSI/
SCLK
MOSI/
SCLK
...
...
20
31 30 29 28 27 26 25 24 23 22 21
3
2
1
0
20
31 30 29 28 27 26 25 24 23 22 21
3
2
1
0
MISO
MISO
Previous Address
Previous command data
Control Word
Configure Word
Figure 19. SPI write operation
33978
29
NXP Semiconductors
CS_B
CS_B
Next Control word
Next Configure words
Control word (READ)
DON’T CARE
MOSI/
MOSI/
SCLK
SCLK
...
...
20
31 30 29 28 27 26 25 24 23 22 21
3
2
1
0
20
31 30 29 28 27 26 25 24 23 22 21
3
2
1
0
MISO
MISO
Previous Address
Previous command data
Control Word (READ)
Register Data
Figure 20. SPI read operation
CSb
SCLK
DI
DO
1st IC
CSb
CSb
SCLK
DI
SCLK
MISO
MISI
DO
MCU
2nd IC
CSb
SCLK
DI
DO
3rd IC
CSb
Don' t Care
- 3rd IC
- 2nd IC
- 1st IC
MOSI
MOSI
MOSI
MOSI- 1st IC
MCU MISO
MISO - 1st IC
MOSI-2nd IC
MISO
MOSI
- 2st IC
- 3rd IC
MISO - 3rd IC
MCU MOSI
- 3rd IC
- 2nd IC - 1st IC
MISO
Don' t Care
MISO
MISO
Figure 21. Daisy chain SPI operation
33978
NXP Semiconductors
30
7.10 SPI control register definition
A 32-bit SPI allows the system microprocessor to configure the 33978 for each input as well as read out the status of each input. The SPI
also allows the Fault Status and INTflg bits to be read via the SPI. The SPI MOSI bit definitions are given in Table 11:
Table 11. MOSI input register bit definition
Register #
0
Register name
Address
Rb/W
0
SPI check
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
02/03
04/05
06/07
08/09
0A/0B
0C/0D
16/17
18/19
1A/1B
1C/1D
1E/1F
20/21
22/23
24/25
26/27
28/29
2A/2B
2C/2D
2E/2F
30/31
32/33
34/35
36/37
39
Device configuration register
Tri-state SP register
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
Tri-state SG register
Wetting current level SP register
Wetting current level SG register 0
Wetting current level SG register 1
Continuous wetting current SP register
Continuous Wetting Current SG Register
Interrupt enable SP register
Interrupt enable SG register
Low-power mode configuration
Wake-up enable register SP
Wake-up enable register SG
Comparator only SP
Comparator only SG
LPM voltage threshold SP configuration
LPM voltage threshold SG configuration
Polling current SP configuration
Polling current SG configuration
Slow polling SP
Slow polling SG
Wake-up debounce SP
Wake-up debounce SG
Enter low-power mode
3A/3B
3E
AMUX control register
0/1
0
Read switch status
42
Fault status register
0
47
Interrupt request
1
49
Reset register
1
The 32-bit SPI word consists of a command word (8-bit) and three configure words (24-bit). The 8 MSB bits are the command bits that
select what type of configuration is to occur. The remaining 24-bits are used to select the inputs to be configured.
• Bit 31 - 24 = Command word: Use to select what configuration is to occur (example: setting wake-up enable command)
• Bit 23 - 0 = SGn input select word: Use these bits in conjunction with the command word to determine which input is setup.
Configuration registers may be read or written to. To read the contents of a configuration register, send the register address + ‘0’ on the
LSB of the command word; the contents of the corresponding register will be shifted out of the MISO buffer in the next SPI cycle. When
a Read command is sent, the answer (in the next SPI transaction) includes the Register address in the upper byte (see Figure 20).
33978
31
NXP Semiconductors
Read example:
• Send 0x0C00_0000 Receive: 8000_0000 (for example after a POR)
• Send 0x0000_0000 Receive: 0C00_0000 (address + register data)
The first response from the device after a POR event is a Read Status register (0x3Exxxxxx where x is the status of the inputs). This is
the same for exiting the Low-power mode (see Figure 18.).
To write into a configuration register, send the register Address + ‘1’ on the LSB of the command word and the configuration data on the
next 24 bits. The new value of the register will be shifted out of the MISO buffer in the next SPI cycle, along with the register address.
Table 7.10.1 provides a general overview of the functional SPI commands and configuration bits.
Table 12. Functional SPI register map
Commands
[31-25]
Address R/W
0000000
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI check
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Device Configuration
0000001 0/1
FS
INT
X
X
X
X
X
X
X
X
Tri-State Enable SP
0000010 0/1
0000011 0/1
0000100 0/1
0000101 0/1
0000110 0/1
FS
FS
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Tri-State Enable SG
X
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Wetting Current Level SP
Wetting Current Level SG 0
Wetting Current Level SG 1
SP7[2-0]
SG7[2-0]
INT
SP6[2-0]
SG6[2-0]
X
SP5[2-0]
SG5[2-0]
SG13[2-0]
SP4[2-0]
SG4[2-0]
SG12[2-0]
SP3[2-0]
SG3[2-0]
SG11[2-0]
SP2[2-0]
SG2[2-0]
SG10[2-0]
SP1[2-0]
SG1[2-0]
SG9[2-0]
SP0[2-0]
SG0[2-0]
SG8[2-0]
FS
FS
X
X
X
X
X
X
Continuous Wetting Current
Enable SP
0001011 0/1
0001100 0/1
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Continuous Wetting Current
Enable SG
FS
X
X
X
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Interrupt Enable SP
Interrupt Enable SG
0001101 0/1
0001110 0/1
FS
FS
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Low-power mode
configuration
0001111 0/1
FS
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
int3
int2
int2
int0 poll3 poll2 poll1 poll0
Wake-Up Enable SP
0010000 0/1
0010001 0/1
0010010 0/1
0010011 0/1
0010100 0/1
0010101 0/1
FS
FS
FS
FS
FS
FS
INT
INT
INT
INT
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Wake-Up Enable SG
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
LPM Comparator Only SP
LPM Comparator Only SG
LPM Voltage Threshold SP
LPM Voltage Threshold SG
X
X
X
X
X
X
X
X
X
X
X
X
LPM Polling current config
SP
0010110 0/1
0010111 0/1
FS
FS
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
LPM Polling current config
SG
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
LPM Slow Polling SP
0011000 0/1
0011001 0/1
0011010 0/1
0011011 0/1
FS
FS
FS
FS
FS
FS
INT
INT
INT
INT
INT
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
LPM Slow Polling SG
Wake-Up Debounce SP
Wake-Up Debounce SG
Enter Low-power mode
AMUX Channel Select SPI
X
X
X
X
X
X
0011100
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0011101 0/1
asett asel5 asel4 asel3 asel2 asel1 asel0
Read Switch Status
0011111
0100001
0
0
Fault Status
X
Interrupt Pulse Request
Reset
0100011
0100100
1
1
FS
X
INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes
28. FS = FAULT STATUS (available for reading on MISO return word)
29. INT = INTflg (available for reading on MISO return word)
33978
NXP Semiconductors
32
7.10.1 SPI check
The MCU may check the communication with the IC by using the SPI Check register. The MCU sends the command and the response
during the next SPI transaction will be 0x123456. The SPI Check command does not return Fault Status or INTflg bit, thus interrupts will
not be cleared.
Table 13. SPI check command
Register address
[31-25]
R
[24]
0
SPI data bits [23 - 0]
bits [23 - 16]
0000_0000
0000_000
bits [15 - 8]
0000_0000
bits [7 - 0]
0000_0000
MISO return word
0x00123456
7.10.2 Device configuration register
The device has various configuration settings that are global in nature. The configuration settings are as follows:
• When the 33978 is in the overvoltage region, a Logic [0] on the VBATP OV bit limits the wetting current on all input channels to 2 mA
and the 33978 will not be able to enter into the Low-power mode. A Logic [1] allows the device to operate normally even in the
overvoltage region. The OV flag will be set when the device enters in the OV region, regardless the value of the VBATP OV bit.
• WAKE_B can be used to enable an external power supply regulator to supply the VDDQ voltage rail. When the WAKE_B VDDQ check
bit is a Logic [0], the WAKE_B pin is expected to be pulled-up internally or externally to VDDQ and VDDQ is expected to go low,
therefore the 33978 does not wake-up on the falling edge of WAKE_B. A Logic [1], assumes the user is using an external pull-up to
VBATP or VDDQ (when VDDQ is not expected to be off) and the IC wakes up on a falling edge of WAKE_B.
• INT_B out is used to select how the INT_B pin operates when an interrupt occurs. The IC is able to pulse low [1] or latch low [0].
• Aconfig[1-0] is used to determine the method of selecting the AMUX output, either a SPI command or using a hardwired setup using
SG[3-1].
• Inputs SP0-7 may be programmable for switch-to-battery or switch-to-ground. These inputs types are defined using the settings
command. To set a SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set a SPn input for switch-to-
ground, a logic [0] for the appropriate bit must be set. The MCU may change or update the programmable switch register via software
at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] is placed in the serial output
response register.
33978
33
NXP Semiconductors
Table 14. Device configuration register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0000_001
0/1
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
SBPOLL
TIME
VBATP OV
disable
WAKE_B
VDDQ Check
Unused
INT_B out
Aconfig1
Aconfig0
0
0
0
0
1
0
0
0
Default on POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SP0
SP7
SP6
SP5
1
SP4
1
SP3
1
SP2
1
SP1
1
1
1
1
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0000_001[R/W]
INTflg
STATUS
Table 15. Device configuration bits definition
Bit
Functions
Default value
Description
23-14
Unused
0
Unused
Select the polling time for SP channels configured as SB.
• A logic [0] set the active polling timer to 1ms,
• A logic [1] sets the active polling timer to 55 μs.
13
12
SBPOLLTIME
0
0
VBATP Overvoltage protection
• 0 - Enabled
VBATP OV
Disable
• 1 - Disable
Enable/Disable WAKE_B to wake-up the device on falling edge when VDDQ is not present.
• 0 - WAKE_B is pulled up to VDDQ (internally and/or externally). WAKE_B is ignored while in LPM if VDDQ
is low.
• 1 - WAKE_B is externally pulled up to VBATP or VDDQ and wakes upon a falling edge of the WAKE_B pin
regardless of the VDDQ status.(VDDQ is not expected to go low)
WAKE_B
VDDQ Check
11
10
1
0
Interrupt pin behavior
Int_B_Out
Aconfig(1-0)
SP7 - SP0
• 0 - INT pin stays low when interrupt occurs
• 1 - INT pin pulse low and return high
Configure the AMUX output control method
• 00 - SPI (default)
• 01 - SPI
• 10 - HW 2bit
• 11 - HW 3bit
9-8
7-0
00
Refer to section 7.8, “AMUX functional block" for details on 2 and 3 bit hardwire configuration.
Configure the SP pin as Switch to Battery (SB) or Switch to ground (SG)
• 0 - Switch to Ground
1111_1111
• 1 - Switch to Battery
33978
NXP Semiconductors
34
7.10.3 Tri-state SP register
The tri-state command is use to set the input nodes as high-impedance (Table 16). By setting the tri-state register bit to logic [1], the input
is high-impedance regardless of the Wetting current setting. The configurable comparator (4.0 V default) on each input remains active.
The MCU may change or update the tri-state register via software at any time in Normal mode. The tri-state register defaults to 1 (inputs
are tri-stated). Any inputs in tri-state is still polled in LPM but the current source is not active during this time. The determination of change
of state occurs at the end of the tACTIVEPOLL and the wake-up decision is made.
Table 16. Tri-state SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0000_010
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
1
0
bit 6
SP6
1
0
0
0
0
0
0
bit 5
SP5
1
bit 4
SP4
1
bit 3
SP3
1
bit 2
SP2
1
bit 1
SP1
1
bit 0
SP0
1
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0000_010[R/W]
INTflg
7.10.4 Tri-state SG register
The tri-state command is used to set the input nodes as high-impedance (Table 17). By setting the tri-state register bit to logic [1], the
input is high-impedance regardless of the Wetting command setting. The configurable comparator (4.0 V default) on each input remains
active. The MCU may change or update the tri-state register via software at any time in Normal mode. The tri-state register defaults to 1
(inputs are tri-stated. Any inputs in tri-state is still polled in LPM but the current source is not active during this time. The determination of
change of state occurs at the end of the tACTIVEPOLL and the wake-up decision is made.
Table 17. Tri-state SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0000_011
0/1
Unused
0
0
0
bit 13
SG13
1
0
bit 12
SG12
1
0
bit 11
SG11
1
0
bit 10
SG10
1
0
0
bit 15
bit 14
bit 9
SG9
1
bit 8
SG8
1
Unused
Default on POR
0
0
bit 6
SG6
1
bit 7
SG7
1
bit 5
SG5
1
bit 4
SG4
1
bit 3
SG3
1
bit 2
SG2
1
bit 1
SG1
1
bit 0
SG0
1
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0000_011[R/W]
INTflg
STATUS
33978
35
NXP Semiconductors
7.10.5 Wetting current level SP register
The IC contains configurable wetting currents (Default = 16 mA). Three bits are used to control each individual input pin with the values
set in Table 18. The MCU may change or update the wetting current register via software at any time in Normal mode.
Table 18. Wetting current level SP register
Register address R/W
SPI data bits [23 - 0]
bit [20 - 18]
[31-25]
[24]
bit [23 - 21]
SP7 [2-0]
110
bit [17 - 16]
SP5[2-1]
11
0000_100
0/1
SP6[2-0]
110
bit [15]
SP5[0]
0
bit [14 - 12]
SP4 [2-0]
110
bit [11 - 9]
SP3[2-0]
110
bit [8]
SP2[2]
1
Default on POR
bit [7 - 6]
bit [5 - 3]
SP1[2-0]
110
bit [2 - 0]
SP0[2-0]
110
SP2[1-0]
10
MISO return word
bits [23 - 0]
Register Data
0000_100[R/W]
See Table 21 for the selectable Wetting Current level values for both SPx and SGx pins.
7.10.6 Wetting current level SG register 0
The IC contains configurable wetting currents (Default = 16 mA). Three bits are used to control each individual input pin with the values
set in Table 19. The MCU may change or update the wetting current register via software at any time in Normal mode.
Table 19. Wetting current level SG register 0
Register address R/W
SPI data bits [23 - 0]
bit [20 - 18]
[31-25]
[24]
bit [23 - 21]
SG7 [2-0]
110
bit [17 - 16]
SG5[2-1]
11
0000_101
0/1
SG6[2-0]
110
bit [15]
SG5[0]
0
bit [14 - 12]
SG4 [2-0]
110
bit [11 - 9]
SG3[2-0]
110
bit [8]
SG2[2]
1
Default on POR
bit [7 - 6]
bit [5 - 3]
SG1[2-0]
110
bit [2 - 0]
SG0[2-0]
110
SG2[1-0]
10
MISO return word
bits [23 - 0]
Register Data
0000_101[R/W]
See Table 21 for the selectable Wetting Current level values for both SPx and SGx pins.
33978
NXP Semiconductors
36
7.10.7 Wetting current level SG register 1
The IC contains configurable wetting currents (Default = 16 mA). Three bits are used to control each individual input pin with the values
set in Table 20. The MCU may change or update the wetting current register via software at any time in Normal mode.
Table 20. Wetting current level SG register 1
Register address R/W
SPI data bits [23 - 0]
bit [20 - 18]
[31-25]
[24]
bit [23 - 21]
bit [17 - 16]
SG13[2-1]
11
0000_110
0/1
Unused
0
bit [15]
SG13[0]
0
bit [14 - 12]
bit [11 - 9]
SG11[2-0]
110
bit [8]
SG12 [2-0]
110
SG10[2]
1
Default on POR
bit [7 - 6]
bit [5 - 3]
SG9[2-0]
110
bit [2 - 0]
SG8[2-0]
110
SG10[1-0]
10
MISO return word
bits [23 - 0]
Register Data
0000_110[R/W]
See Table 21 for the selectable Wetting Current level values for both SPx and SGx pins.
Table 21. SPx/SGx selectable wetting current levels
SPx/SGx[2-0]
Wetting Current Level
bit 2
bit 1
bit 0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
2.0 mA
6.0 mA
8.0 mA
10 mA
12 mA
14 mA
16 mA
20 mA
1
0
1
0
1
0
1
33978
37
NXP Semiconductors
7.10.8 Continuous wetting current SP register
Each switch input has a designated 20 ms timer. The timer starts when the specific switch input crosses the comparator threshold. When
the 20 ms timer expires, the contact current is reduced from the configured wetting current (16 mA) to the Sustain current. The wetting
current is defined to be an elevated level that reduces to the lower sustain current level after the timer has expired. With multiple wetting
current timers disabled, power dissipation for the IC must be considered.
The MCU may change or update the continuos wetting current register via software at any time in Normal mode. This allows the MCU to
control the amount of time wetting current is applied to the switch contact. Programming the continuos wetting current bit to logic [0]
operates normally with a higher wetting current followed by sustain current after 20 ms (pulsed Wetting current operation). Programming
to logic [1] enables the continuous wetting current (Table 22) and results in a full time wetting current level. The continuous wetting current
register defaults to 0 (pulse wetting current operation).
Table 22. Continuous wetting current SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0001_011
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0001_011[R/W]
INTflg
7.10.9 Continuous Wetting Current SG Register
Each switch input has a designated 20 ms timer. The timer starts when the specific switch input crosses the comparator threshold. When
the 20 ms timer expires, the contact current is reduced from the configured wetting current (16 mA) to 2.0 mA. The wetting current is
defined to be at an elevated level that reduces to the lower sustain current level after the timer has expired. With multiple wetting current
timers disabled, power dissipation for the IC must be considered.
The MCU may change or update the continuous wetting current register via software at any time in Normal mode. This allows the MCU
to control the amount of time wetting current is applied to the switch contact. Programming the continuos wetting current bit to logic [0]
operates normally with a higher wetting current followed by sustain current after 20 ms (Pulse wetting current operation). Programming to
logic [1] enables the continuous wetting current (Table 23) and results in a full time wetting current level. The continuous wetting current
register defaults to 0 (pulse wetting current operation).
33978
NXP Semiconductors
38
Table 23. Continuous wetting current SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0001_100
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
0001_100[R/W]
INTflg
Register Data
STATUS
Switch to
Switch to
Ground Closed
Ground open
IWET
Continuous wetting
current enabled
0 ma
0 ma
IWET
Continuous wetting
current disabled
ISUS=~2mA
20 ms
Figure 22. Pulsed/continuous wetting current configuration
33978
39
NXP Semiconductors
7.10.10 Interrupt enable SP register
The interrupt register defines the inputs that are allowed to Interrupt the 33978 Normal mode. Programming the interrupt bit to logic [0]
disables the specific input from generating an interrupt. Programming the interrupt bit to logic [1] enables the specific input to generate an
interrupt with switch change of state The MCU may change or update the interrupt register via software at any time in Normal mode. The
Interrupt register defaults to logic [1] (Interrupt enabled).
Table 24. Interrupt enable SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0001_101
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
1
0
bit 6
SP6
1
0
0
0
0
0
0
bit 5
SP5
1
bit 4
SP4
1
bit 3
SP3
1
bit 2
SP2
1
bit 1
SP1
1
bit 0
SP0
1
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0001_101[R/W]
INTflg
7.10.11 Interrupt enable SG register
The interrupt register defines the inputs that are allowed to Interrupt the 33978 Normal mode. Programming the interrupt bit to logic [0]
disables the specific input from generating an interrupt. Programming the interrupt bit to logic [1] enables the specific input to generate an
interrupt with switch change of state The MCU may change or update the interrupt register via software at any time in Normal mode. The
Interrupt register defaults to logic [1] (Interrupt enabled).
Table 25. Interrupt enable SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0001_110
0/1
Unused
0
0
0
bit 13
SG13
1
0
bit 12
SG12
1
0
bit 11
SG11
1
0
bit 10
SG10
1
0
0
bit 15
bit 14
bit 9
SG9
1
bit 8
SG8
1
Unused
Default on POR
0
0
bit 6
SG6
1
bit 7
SG7
1
bit 5
SG5
1
bit 4
SG4
1
bit 3
SG3
1
bit 2
SG2
1
bit 1
SG1
1
bit 0
SG0
1
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0001_110[R/W]
INTflg
STATUS
33978
NXP Semiconductors
40
7.10.12 Low-power mode configuration
The device has various configuration settings for the Low-power mode operation. The configuration settings are as follows:
int[3-0] is used to set the interrupt timer value. With the interrupt timer set, the IC wakes up after the selected timer expires and issue an
interrupt. This register can be selected to be OFF such that the IC does not wake-up from an interrupt timer.
poll[3-0] is used to set the normal polling rate for the IC. The polling rate is the time between polling events. The current sources become
active at this time for a time of tACTIVESGPOLLING or tACTIVESBPOLLING for SG or SB channels respectively.
Table 26. Low-power mode configuration register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0001_111
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
int3
0
bit 6
int2
0
bit 5
int1
0
0
bit 4
int0
0
0
0
0
0
bit 3
poll3
1
bit 2
poll2
1
bit 1
poll1
1
bit 0
poll0
1
0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0001_111[R/W]
INTflg
Table 27. Low-power mode configuration bits definition
Bit
Functions
Default value
Description
23 - 8
Unused
0
Unused
Set the Interrupt timer value
• 0000 - OFF
• 1000 - 4.0 ms
• 0001 - 6.0 ms
• 0010 - 12 ms
• 0011 - 24 ms
• 0100 - 48 ms
• 0101 - 96 ms
• 0110 - 192 ms
• 0111 - 394 ms
• 1001 - 8.0 ms
• 1010 - 16 ms
• 1011 - 32 ms
• 1100 - 64 ms
• 1101 - 128 ms
• 1110 - 256 ms
• 1111 - 512 ms
7 - 4
int[3-0]
0000
Set the polling rate for switch detection
• 0000 - 3.0 ms
• 0001 - 6.0 ms
• 0010 - 12 ms
• 0011 - 24 ms
• 0100 - 48 ms
• 0101 - 68 ms
• 0110 - 76 ms
• 0111 - 128 ms
• 1000 - 32 ms
• 1001 - 36 ms
• 1010 - 40 ms
• 1011 - 44 ms
• 1100 - 52 ms
• 1101 - 56 ms
• 1110 - 60 ms
3 - 0
poll[3-0]
1111
• 1111 - 64 ms (default)
33978
41
NXP Semiconductors
7.10.13 Wake-up enable register SP
The wake-up register defines the inputs that are allowed to wake the 33978 from Low-power mode. Programming the wake-up bit to
logic [0] disables the specific input from waking the IC (Table 28). Programming the wake-up bit to logic [1] enables the specific input to
wake-up with switch change of state The MCU may change or update the wake-up register via software at any time in Normal mode. The
Wake-up register defaults to logic [1] (wake-up enabled). If all channels (SG and SB) have the Wake-up bit disabled, the device disables
the polling timer to reduce the current consumption during Low-power mode.
Table 28. Wake-up enable SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_000
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
1
0
bit 6
SP6
1
0
0
0
0
0
0
bit 5
SP5
1
bit 4
SP4
1
bit 3
SP3
1
bit 2
SP2
1
bit 1
SP1
1
bit 0
SP0
1
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0010_000[R/W]
INTflg
7.10.14 Wake-up enable register SG
The wake-up register defines the inputs that are allowed to wake the 33978 from Low-power mode. Programming the wake-up bit to
logic [0] disables the specific input from waking the IC (Table 29). Programming the wake-up bit to logic [1] enables the specific input to
wake-up with any switch change of state The MCU may change or update the wake-up register via software at any time in Normal mode.
The Wake-up register defaults to logic [1] (wake-up enabled). If all channels (SG and SB) have the Wake-up bit disabled, the device
disables the polling timer to reduce the current consumption during Low-power mode.
Table 29. Wake-up enable SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_001
0/1
Unused
0
0
0
bit 13
SG13
1
0
bit 12
SG12
1
0
bit 11
SG11
1
0
bit 10
SG10
1
0
0
bit 15
bit 14
bit 9
SG9
1
bit 8
SG8
1
Unused
Default on POR
0
0
bit 6
SG6
1
bit 7
SG7
1
bit 5
SG5
1
bit 4
SG4
1
bit 3
SG3
1
bit 2
SG2
1
bit 1
SG1
1
bit 0
SG0
1
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0010_001[R/W]
INTflg
STATUS
33978
NXP Semiconductors
42
7.10.15 Comparator only SP
The comparator only register allows the input comparators to be active during LPM with no polling current. In this case, the inputs can
receive a digital signal on the order of the LPM clock cycle and wake-up on a change of state. This register is intended to be used for
signals that are driven by an external chip and drive to 5.0 V.
Table 30. Comparator only SP Register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_010
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0010_010[R/W]
INTflg
7.10.16 Comparator only SG
The comparator only register allows the input comparators to be active during LPM with no polling current. In this case, the inputs can
receive a digital signal on the order of the LPM clock cycle and wake-up on a change of state. This register is intended to be used for
signals that are driven by an external chip and drive to 5.0 V.
Table 31. Comparator only SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_011
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0010_011[R/W]
INTflg
STATUS
33978
43
NXP Semiconductors
7.10.17 LPM voltage threshold SP configuration
The 33978 is able to use different voltage thresholds to wake-up from LPM. When configured as SG, a Logic [0] means the input will use
the LPM delta voltage threshold to determine the state of the switch. A Logic [1] means the input uses the Normal threshold (VICTHR) to
determine the state of the switch. When configured as an SB, it only uses the 4.0 V threshold regardless the status of the LPM voltage
threshold bit. The user must ensure that the correct current level is set to allow the crossing of the normal mode threshold (typ. 4.0 V)
Table 32. LPM voltage threshold configuration SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_100
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0010_100[R/W]
INTflg
7.10.18 LPM voltage threshold SG configuration
This means the input uses the LPM delta voltage threshold to determine the state of the switch. A Logic [1] means the input uses the
Normal threshold to determine the state of the switch. The user must ensure that the correct current level is set to allow the crossing of
the normal mode threshold (typ. 4.0 V)
Table 33. LPM voltage threshold configuration SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_101
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0010_101[R/W]
INTflg
STATUS
33978
NXP Semiconductors
44
7.10.19 Polling current SP configuration
The normal polling current for LPM is 2.2 mA for SB channels and 1.0 mA for SG channels, A logic [0] selects the normal polling current
for each individual channel. The user may choose to select the IWET current value as defined in the wetting current level registers by writing
a Logic [1] on this bit; this will result in higher LPM currents but may be used in cases when a higher polling current is needed.
Table 34. Polling current configuration SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_110
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0010_110[R/W]
INTflg
7.10.20 Polling current SG configuration
A Logic [0] selects the normal polling current for LPM =1.0 mA. The user may choose to select the IWET current value as defined in the
wetting current registers for LPM by writing a Logic [1] in this bit; this results in higher LPM currents but may be used in cases when a
higher polling current is needed.
Table 35. Polling current configuration SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0010_111
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0010_111[R/W]
INTflg
STATUS
33978
45
NXP Semiconductors
7.10.21 Slow polling SP
The normal polling rate is defined in the Low-power mode configuration register. If the user is able to poll at a slower rate (4x) the LPM
current level decreases significantly. Setting the bit to [0] results in the input polling at the normal rate as selected. Setting the bit to [1]
results in the input being polled at a slower frequency at 4x the normal rate.
Table 36. Slow polling SP Register
Register Address R/W
SPI Data Bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0011_000
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO Return Word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0011_000[R/W]
INTflg
7.10.22 Slow polling SG
The normal polling rate is defined in the Low-power mode configuration register. If the user is able to poll at a slower rate (4x) the LPM
current level decreases significantly. Setting the bit to [0] results in the input polling at the normal rate as selected. Setting the bit to [1]
results in the input being polled at a slower frequency at 4x the normal rate.
Table 37. Slow Polling SG Register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0011_001
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0011_001[R/W]
INTflg
STATUS
33978
NXP Semiconductors
46
7.10.23 Wake-up debounce SP
The IC is able to extend the time that the active polling takes place to ensure that a true change of state has occurred in LPM and reduce
the chance that noise has impacted the measurement. If this bit is [0], the IC uses a voltage difference technique to determine if a switch
has changed sate. If this bit is set [1], the IC debounces the measurement by continuing to source the LPM polling current for an additional
1.2 ms and take the measurement based on the final voltage level. This helps to ensure that the switch is detected correctly in noisy
systems.
Table 38. Wake-up debounce SP register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0011_010
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
bit 7
SP7
0
0
bit 6
SP6
0
0
0
0
0
0
0
bit 5
SP5
0
bit 4
SP4
0
bit 3
SP3
0
bit 2
SP2
0
bit 1
SP1
0
bit 0
SP0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
Register Data
FAULT
STATUS
0011_010[R/W]
INTflg
7.10.24 Wake-up debounce SG
The IC is able to extend the time that the active polling takes place to ensure that a true change of state has occurred in LPM and reduce
the chance that noise has impacted the measurement. If this bit is [0], the IC uses a voltage difference technique to determine if a switch
has changed sate. If this bit is set [1], the IC debounces the measurement by continuing to source the LPM polling current for an additional
1.2 ms and take the measurement based on the final voltage level. This helps to ensure that the switch is detected correctly in noisy
systems.
Table 39. Slow polling SG Register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0011_011
0/1
Unused
0
0
0
bit 13
SG13
0
0
bit 12
SG12
0
0
bit 11
SG11
0
0
bit 10
SG10
0
0
0
bit 15
bit 14
bit 9
SG9
0
bit 8
SG8
0
Unused
Default on POR
0
0
bit 6
SG6
0
bit 7
SG7
0
bit 5
SG5
0
bit 4
SG4
0
bit 3
SG3
0
bit 2
SG2
0
bit 1
SG1
0
bit 0
SG0
0
MISO return word
bit [23]
FAULT
bit [22]
bits [21 - 0]
Register Data
0011_011[R/W]
INTflg
STATUS
33978
47
NXP Semiconductors
7.10.25 Enter low-power mode
Low-power mode (LPM) is used to reduce system quiescent currents. Low-power mode may be entered only by sending the Low-power
command. When returning to Normal mode, all register settings is maintained.
The Enter Low-power mode register is write only and has the effect of going to LPM and beginning operation as selected (polling, interrupt
timer). When returning form Low-power mode, the first SPI transaction will return the Fault Status and the intflg bit set to high, as well as
the actual status of the Input pins.
Table 40. Enter low-power mode command
Register address
[31-25]
W
[24]
1
SPI data bits [23 - 0]
bits [23 - 16]
0000_0000
bits [15 - 8]
0000_0000
bits [7 - 0]
0000_0000
-
0011_100
MISO return word
7.10.26 AMUX control register
The analog voltage on switch inputs may be read by the MCU using the analog command (Table 41). Internal to the33978 is a 24-to-1
analog multiplexer. The voltage present on the selected input pin is buffered and made available on the AMUX output pin. The AMUX
output pin is clamped to a maximum of VDDQ volts regardless of the higher voltages present on the input pin. After an input has been
selected as the analog, the corresponding bit in the next MISO data stream is logic [0].
Setting the current to wetting current (configurable) may be useful for reading sensor inputs. The MCU may change or update the analog
select register via software at any time in Normal mode. The analog select defaults to no input.
Table 41. Slow polling SG register
Register address R/W
SPI data bits [23 - 0]
[31-25]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0011_101
0/1
Unused
Unused
0
0
0
0
0
0
0
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Default on POR
0
0
bit 6
asett0
0
0
0
0
0
0
0
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unused
0
asel[5-0]
0
0
0
0
0
0
MISO return word
bit [23]
bit [22]
bits [21 - 0]
FAULT
STATUS
0011_101[R/W]
INTflg
Register Data
Table 42. AMUX current select
asett[0]
Zsource
0
1
hi Z (default)
IWET
33978
NXP Semiconductors
48
Table 43. AMUX channel select
asel 5
asel 4
asel3
0
asel 2
asel 1
asel 0
Analog channel select
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No Input Selected
SG0
0
0
SG1
0
SG2
0
SG3
0
SG4
0
SG5
0
SG6
1
SG7
1
SG8
1
SG9
1
SG10
SG11
SG12
SG13
SP0
1
1
1
1
0
SP1
0
SP2
0
SP3
0
SP4
0
SP5
0
SP6
0
SP7
0
Temp Diode
Battery Sense
1
7.10.27 Read switch status
The Read switch status register is used to determine the state of each of the inputs and is read only. All of the inputs (SGn and SPn) are
returned after the next command is sent. A Logic [1] means the switch is closed while a Logic [0] is an open switch.
Included in the status register are two more bits, the Fault Status bit and intflg bit. The Fault Status bit is a combination of the extended
status bits and the wetting current fault bits. If any of these bits are set, the Fault Status bit is set. The intflg bit is set when an interrupt
occurs on this device.
After POR, both the Fault Status bit and the intflg bit are set high to indicate an interrupt due to a POR occurred. The intflg bit will be
cleared upon reading the Read Switch Status register, and the Fault Status bit will remain high until the Fault status register is read and
thus the POR fault bit and all other fault flags are cleared.
The Fault Status and Intflg bits are semi-global flags, if a fault or an interrupt occurs, these bit will be returned after writing or reading any
command, except for the SPICheck and the Wetting Current configuration registers, which use those bits to set/display the device
configuration.
33978
49
NXP Semiconductors
Table 44. Read switch status command
Register address
[31-25]
R
SPI data bits [23 - 0]
[24]
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
FAULT
STATUS
0011_111
0
INTflg
SP7
SP6
SP5
SP4
SP3
SP2
1
bit 15
SP1
X
1
bit 14
SP0
X
X
bit 13
SG13
X
X
bit 12
SG12
X
X
bit 11
SG11
X
X
bit 10
SG10
X
X
X
bit 9
SG9
X
bit 8
SG8
X
Default After POR
bit 7
SG7
X
bit 6
SG6
X
bit 5
SG5
X
bit 4
SG4
X
bit 3
SG3
X
bit 2
SG2
X
bit 1
SG1
X
bit 0
SG0
X
MISO return word
bit [23]
bit [22]
bits [21-14]
SP7 -SP0 Switch Status
bits [13-0]
SG13 - SG0 Switch Status
FAULT
STATUS
0011_1110
INTflg
The fault/status diagnostic capability consists of one internal 24 bit register. The content of the fault/status register is shown in Table 45.
Bits 0 – 21 shows the status of each input where logic [1] is a closed switch and logic [0] is an open switch. In addition to input status
information, Fault status such as die over-temp, Hash fault, SPI errors, as well as interrupts are reported.
A SPI read cycle is initiated by a CS_B logic ‘1’ to ‘0’ transition, followed by 32 SCLK cycles to shift the fault / status registers out the MISO
pin. The INT_B pin is cleared 1.0 ms after the falling edge of CS_B. The fault is immediately set again if the fault condition is still present.
The Fault Status bit sets any time a Fault occurs, and the Fault register (Table 46) must be read in order to clear the Fault status flag.
The intflg bit sets any time an interrupt event occurs (change of state on switch, any fault status bit gets set). Any SPI message that will
return intflg bit will clear this flag (even if the event is still occurring, for example an overtemp, will cause an interrupt. The interrupt can be
cleared but the chip will not interrupt again based on the overtemp until that fault has gone away).
Table 45. MISO output register definition
MISO
Response
Sends
Bit 23 : Fault Status:
• 0 = No Fault
• 1 = Indicates a fault has occurred and should be viewed in the fault status register.
Bit 22 : Intflg:
• 0 = No Change of state
• 1 = Change of state detected.
Bit 21 – 0 : SPx /SGx input status:
• 0 = Open switch;
• 1 =Closed switch
33978
NXP Semiconductors
50
7.10.28 Fault status register
To read the fault status bits the user should first sent a message to the IC with the fault status register address followed by any given
second command. The MISO response from the second command will contain the fault flags information.
Table 46. Fault status register
Register address
[31-25]
R
[24]
0
SPI data bits [23 - 0]
bit 23
Unused
0
bit 22
INTflg
1
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
0100_001
Unused
0
bit 13
Unused
0
0
0
0
0
bit 9
0
bit 8
Unused
0
bit 15
bit 14
bit 12
bit 11
bit 10
SPI error
X
Hash Fault
X
0
0
0
0
Default After POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WAKE_B
Wake
UV
OV
TempFlag
X
OT
X
INT_B Wake
X
SPI Wake
X
POR
X
X
X
X
MISO return word
bit [23]
bit [22]
bits [21-0]
FAULT/FLAG BITS
FAULT
STATUS
0100_0010
INTflg
Table 47. MISO response for fault status command
Bit
Functions
Default value
Description
23
Unused
0
Unused
Reports that an Interrupt has occurred, user should read the status register to determine cause.
• Set: Various (SGx change of state, SPx change of state, Extended status bits).
• Reset: Clear of fault or read of Status register
22
21-11
10
INTflg
Unused
SPI error
X
0
Unused
Any SPI error generates a bit (Wrong address, incorrect modulo).
• Set: SPI message error.
X
• Reset: Read fault status register and no SPI errors.
SPI register and hash mismatch.
9
8
7
Hash Fault
Unused
UV
X
0
• Set: Mismatch between SPI registers and hash.
• Reset: No mismatch and SPI flag read.
Unused
Reports that low VBATP voltage was in undervoltage range
• Set: Voltage drops below UV level.
X
• Reset: VBATP rises above UV level and flag read (SPI)
Report that the voltage on VBATP was higher than OV threshold
• Set: Voltage at VBATP rises above overvoltage threshold.
• Reset: Overvoltage condition is over and flag read (SPI)
6
5
4
OV
Temp Flag
OT
X
X
X
Temperature warning to note elevated IC temperature
• Set: tLIM warning threshold is passed.
• Reset: Temperature drops below thermal warning threshold + hysteresis and flag read (SPI)
Tlim event occurred on the IC
• Set: Tlim warning threshold is passed.
• Reset: Temperature drops below thermal warning threshold + hysteresis and flag read (SPI)
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Table 47. MISO response for fault status command (continued)
Part awakens via an external INT_B falling edge
3
2
1
0
INT_B Wake
WAKE_B Wake
SPI Wake
X
X
X
X
• Set: INT_B Wakes the part from LPM (external falling edge)
• Reset: flag read (SPI).
Part awakens via an external WAKE_B falling edge
• Set: External WAKE_B falling edge seen
• Reset: flag read (SPI).
Part awaken via a SPI message
• Set: SPI message wakes the IC from LPM
• Reset: flag read (SPI).
Reports a POR event occurred.
POR
• Set: Voltage at VBATP pin dropped below VBATP(POR) voltage
• Reset: flag read (SPI)
7.10.29 Interrupt request
The MCU may request an Interrupt pulse of duration 100 μs by sending the Interrupt request command. After an Interrupt request
commands, the 33978 returns the Interrupt request command word, as well as the Fault status and INTflg bits set if a fault/interrupt event
occurred. Sending an interrupt request command does not set the INTflg bit itself.
Table 48. Interrupt request command
Register address
[31-25]
W
[24]
1
SPI data bits [23 - 0]
bits [23 - 16]
0000_0000
0100_011
bits [15 - 8]
0000_0000
bits [7 - 0]
0000_0000
MISO return word
bit [23]
bit [22]
bits [21-0]
FAULT
STATUS
0100_0111
INTflg
0
7.10.30 Reset register
Writing to this register causes all of the SPI registers to reset.
Table 49. Reset command
Register address
[31-25]
W
[24]
1
SPI data bits [23 - 0]
bits [23 - 16]
0000_0000
0100_100
bits [15 - 8]
0000_0000
bits [7 - 0]
0000_0000
MISO return word
bit [23]
bit [22]
bits [21-0]
FAULT
STATUS
0011_1110
INTflg
Switch Status
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8
Typical applications
8.1
Application diagram
Figure 23. Typical application diagram
8.2
Bill of materials
Table 50. Bill of materials
Item Quantity
Reference
Value
Description
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10,
C11, C12, C13, C14, C15, C16, C17, C18,
C19, C20, C21, C22, C25, C27
1
24
0.1 μF
CAP CER 0.1 uF 100 V X7R 10 % 0603
2
3
4
2
1
1
C23,C24
C26
1.0 nF
100 μF
-
CAP CER 1000 PF 100 V 10 % X7R 0603
CAP ALEL 100 μF 50 V 20 % -- SMD
DIODE RECT 3.0 A 50 V AEC-Q101 SMB
D1
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
R11, R12, R13, R14, R15, R16, R17, R18,
R19, R20, R21, R22
5
22
100 Ω
RES MF 100 Ω 0.5 W 1% 0805
6
7
8
9
1
1
1
1
R23
R25
R24
U1
10 kΩ
10 kΩ
RES MF 10 kΩ 0.5 W 5 % 0805 (optional)
RES MF 10 kΩ 0.5 W 5 % 0805
1.0 kΩ
RES MF 1 kΩ 0.5 W 5 % 0805
MC33978
IC MULTIPLE DETECTION SWITCH INTERFACE SOIC32
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8.3
Abnormal operation
The 33978 could be subject to various conditions considered abnormal as defined within this section.
8.3.1
Reverse battery
This device with applicable external components will not be damaged by exposure to reverse battery conditions of -14 V. This test is
performed for a period of one minute at 25 °C. In addition, this negative voltage condition does not force any of the logic level I/O pins to
a negative voltage less than -0.6 V at 10 mA or to a positive voltage greater the 5.0 V. This insures protection of the digital device
interfacing with this device.
8.3.2
Ground offset
The applicable driver outputs and/or current sense inputs are capable of operation with a ground offset of 1.0 V. The device will not be
damaged by exposure to this condition and will maintain specified functionality.
8.3.3
Shorts to ground
All I/Os of the device that are available at the module connector are protected against shorts to ground with maximum ground offset
considered (i.e. -1.0 V referenced to device ground or other application specific value). The device will not be damaged by this condition.
8.3.4
Shorts to battery
All I/Os of the device that are available at the module connector are protected against a short to battery (voltage value is application
dependent, there may be cases where short to jump start or load dump voltage values are required). The device will not be damaged by
this condition.
8.3.5
Unpowered shorts to battery
All I/Os of the device that are available at the module connector are protected against unpowered (battery to the module is open) shorts
to battery per application specifics. The device will not be damaged by this condition, will not enable any outputs nor backfeed onto the
power rails (VBATP, VDDQ) or the digital I/O pins.
8.3.6
Loss of module ground
The definition of a loss of ground condition at the device level is that all pins of the IC detects very low-impedance to battery. The
nomenclature is suited to a test environment. In the application, a loss of ground condition results in all I/O pins floating to battery voltage,
while all externally referenced I/O pins are at worst case pulled to ground. All applicable driver outputs and current sense inputs are
protected against excessive leakage current due to loads that are referenced to an external ground (high-side drivers).
8.3.7
Loss of module battery
The loss of battery condition at the parts level is that the power input pins of the IC see infinite impedance to the battery supply voltage
(depending upon the application) but there is some undefined impedance looking from these pins to ground. All applicable driver outputs
and current sense inputs are protected against excessive leakage current due to loads that are referenced to an external battery
connection (low-side drivers).
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9
Packaging
9.1
Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Table 51. Packaging information
Package
Suffix
EK
Package outline drawing number
98ASA10556D
98ASA00656D
32-Pin SOICW-EP
32-Pin QFN (WF-type)
ES
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33978
57
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10 Reference section
Table 52. 33978 reference documents
Reference
Description
CDF-AEC-Q100
Q-1000
Stress Test Qualification For Automotive Grade Integrated Circuits
Qualification Specification for Integrated Circuits
Specification Conformance
SQ-1001
ISO 7637
Electrical Disturbances from Conduction and Coupling
Electromagnetic Compatibility
ISO 61000
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11 Revision history
Revision
1.0
Date
Description of changes
3/2014
3/2014
•
Initial release
2.0
•
•
•
•
•
•
•
Removed Z from part numbers PCZ33978EK and PCZ33978ES in the Orderable part variations table
Major formatting and information arrangement
Updated Figure 1, 33978 simplified application diagram, removed CS_B pull-up resistor, not needed.
Added Industrial Part numbers MC34978EK and MC34978ES to Table 1
Table 3 Clarified Switch Input Range specification (not a differential voltage between inputs and VBATP)
Table 3 Reduced Human Body Model (HBM) (VBATP versus GND) to 2500 V
Table 3 VESD6-2 Series resistor corrected to 50 Ω, Added missing CZAP and RZAP conditions
•
•
•
•
•
•
Table 4 Updated Thermal Resistance specification
Added Figure 10, Functional block diagram
Added Figure 11, Battery voltage range
Added Figure 5, Glitch filter and interrupt delay timers and Figure 6, Interrupt pulse timer
Updated POR minimum specification to 2.7 V (previous 2.9 V)
Updated VBATP Normal mode maximum supply current to 12 mA (previous 8.0 mA)
•
Updated VDDQ undervoltage threshold maximum to 2.8 V (previous 2.7 V)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated sustain current at low battery to 2.4 mA (previous 2.0 mA)
Added a specification to cover the Normal mode switch detection threshold hysteresis.
Updated minimum limit on Switch detection threshold in LPM to 80 mV
Updated minimum ratio for switch threshold at low battery to 0.55x (previous 0.8x)
Fixed typo on Input threshold specifications to VDD*0.25 and VDD*0.7
Updated the INT_B VOL maximum level to 0.5 V (previous 0.4 V)
Updated limits on the POR to Active time to 250 μs (min) to 450 μs (max) (previous min was 40 μs)
Clarified Operating voltage range (4.5 V to 28 V)
Corrected WAKE_B Max rating to 40 V.
3.0
12/2014
Added Figure 19, SPI write operation and Figure 20, SPI read operation
Added Table 7.10.1, SPI check
Corrected Rb/W bits on Table 11 From 1/0 to 0/1
Clarified SPI Read/write operation and SPI registers information.
Updated VBATP(POR) maximum voltage to 3.8 V.
Updated VBATP under voltage hysteresis minimum voltage to 250 mV
Updated VBATP low-power mode supply current to 40 uA
Input logic voltage threshold WAKE_B typical value added at 1.25 V, max value updated to 1.7 V
Added new Specification for WAKE_B input logic hysteresis.
Clarified AMUX accuracy and Coefficient accuracy specifications, added Figure 4, Divide by 6 coefficient accuracy.
Update internal pull-up resistance to 270 KΩ (INT_B, WAKE_B, CS_B)
Low-power mode oscillator frequency centered at 192 KHz with +/- 15% tolerance.
Updated all timing specs derived from the 192 kHz oscillator (Low-power mode)
Added SBPOLLTIME (bit 13) selection functionality on 7.10.2, “Device configuration register"
Added SB Tactive Polling time specification (58 μs or 1.2 ms Typical)
Table 6 Clarified wetting current specification for SB and SG channels.
SB sustain Current and Low-power mode polling current SB Typical value centered at 2.2mA, Min = 1.75 mA and Max
= 2.65 mA, (+/- 20% tolerance).
•
•
•
•
Wetting current matching, Max value updated to 6%
Updated Switch detection Threshold in Low Voltage maximum value to 4.3 V.
Added Figure 22, Pulsed/continuous wetting current configuration
Removed section (Electrical Test requirement, Stress testing, and EMC consideration)
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Revision
Date
Description of changes
•
•
•
Changed VESD1-2 to ±2000
Changed ISUSSB max. value to 2.85 mA
4.0
12/2014
Changed IACTIVEPOLLSB max. value to 2.85 mA
•
•
•
•
Changed PC33978EK and PC34978EK parts to MC in the Orderable part variations table
Deleted PC33978ES and PC34978ES part numbers
Updated case outline
Added new part numbers MC33978AEK, MC33978AES, MC34978AEK, and MC34978AES to the Orderable part vari-
ations table
8/2015
8/2015
•
•
•
•
Updated AMUX specification for QFN package
Added thermal characteristics for QFN package
5.0
Updated VBATP HBM specification to 4.0 KV
Added additional line to VESD1-2 spec in Table 3 to show the max. value for MC33978/MC34978 and MC33978A/
MC34978A
8/2016
2/2017
•
Updated to NXP document form and style
Added note (4) to switch input voltage range in Table 3
Added a new parameter tCSB_WAKEUP to Table 7
6.0
7.0
•
•
8/2017
•
Updated the dynamic electrical characteristics condition statement in Table 7 (changed “VBATP = 4.5 V to 28 V” to
“VBATP = 6.0 V to 28 V”)
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Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to
anyproducts herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for
any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation, consequential or incidental damages.
"Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different
applications, and actual performance may vary over time. All operating parameters, including "typicals," must be
validated for each customer application by the customer's technical experts. NXP does not convey any license under
its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which
can be found at the following address:
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All other product or service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2017.
Document Number: MC33978
Rev. 7.0
8/2017
相关型号：
MC33981
High-Frequency, High-Current, Self-Protected High-Side Switch (4.0 mз up to 60 kHz)
MOTOROLA
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