MC33984NAR2 [NXP]
BUF OR INV BASED PRPHL DRVR, PQCC16, 12 X 12 MM, PLASTIC, QFN-16;
| 型号： | MC33984NAR2 |
| 厂家： | 
NXP |
| 描述： | BUF OR INV BASED PRPHL DRVR, PQCC16, 12 X 12 MM, PLASTIC, QFN-16 驱动 接口集成电路 驱动器 |
| 文件： | 总32页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document order number: MC33984
Rev 5.0, 08/2005
Freescale Semiconductor
Technical Data
Dual Intelligent High-Current
Self-Protected Silicon
High-Side Switch (4.0 mΩ)
33984
33984B
The 33984 is a dual self-protected 4.0 mΩ silicon switch used to
replace electromechanical relays, fuses, and discrete devices in
power management applications. The 33984 is designed for harsh
environments, and it includes self-recovery features. The device is
suitable for loads with high inrush current, as well as motors and all
types of resistive and inductive loads.
DUAL HIGH-SIDE SWITCH
4.0 mΩ
Programming, control, and diagnostics are implemented via the
Serial Peripheral Interface (SPI). A dedicated parallel input is
available for alternate and pulse-width modulation (PWM) control of
each output. SPI-programmable fault trip thresholds allow the device
to be adjusted for optimal performance in the application.
Bottom View
The 33984 is packaged in a power-enhanced 12 x 12 nonleaded
PQFN package with exposed tabs.
PNA SUFFIX
98ARL10521D
Features
16-TERMINAL PQFN (12 x 12)
• Dual 4.0 mΩ Max High-Side Switch with Parallel Input or SPI
Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control,
Watchdog Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-
Safe Pin Status, and Program Status
ORDERING INFORMATION
Temperature
Package
Device
Range (T )
A
MC33984NA/R2
-40°C to 125°C
16 PQFN
MC33984BPNA/R2
• Enhanced -16 V Reverse Polarity VPWR Protection
V
V
V
V
DD
DD
PWR
DD
33984
VDD VPWR
GND
I/O
I/O
FS
WAKE
SO
SI
HS1
SCLK
SCLK
CS
SI
CS
SO
MCU
LOAD
HS0
I/O
I/O
RST
IN0
I/O
IN1
LOAD
A/D
CSNS
GND
FSI
Figure 1. 33984 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations During a Reset Condition
Freescale Part No.
33984
Characteristics
Symbol
Min
Typ
Max
Unit
See Page
Input Logic Voltage Hysteresis
60
350
750
mV
10
10
VIN(HYS)
Input Logic Voltage Hysteresis
100
350
1200
mV
33984B
Note: ESD voltage qualifiction requirements for 33982B version include Charge Device Model (CDM), See Page 6.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
V
IC
Internal
Overvoltage
Protection
I
UP
Regulator
CS
SO
Programmable
Switch Delay
0 ms–525 ms
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
HS0
Selectable Overcurrent
SI
SCLK
FS
High Detection
100 A or 75 A
IN[0:1]
RST
WAKE
Selectable Over-
current Low Detection
Blanking Time
Selectable Overcurrent
Low Detection
Logic
7.5 A–25 A
0.15 ms–155 ms
Open Load
Detection
Overtemperature
Detection
HS0
HS1
I
R
DWN
DWN
HS1
Programmable
Watchdog
V
IC
310 ms–2500 ms
I
Selectable
UP
Output Current
Recopy
1/20500 or 1/41000
FSI
CSNS
GND
Figure 2. 33984 Simplified Internal Block Diagram
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
CSNS
WAKE
1
2
RST
IN0
FS
3
16
15
HS0
HS1
4
5
14
VPWR
13
GND
FSI
CS
6
7
SCLK
8
SI
VDD
9
10
11
SO
IN1
12
Figure 3. 33984 Terminal Connections (Transparent Top View)
Table 2. Terminal Definitions
Functional descriptions of many of these terminals can be found in the Functional Terminal Description section beginning on
page 10.
Terminal
Name
Terminal
Function
Terminal
Formal Name
Definition
This terminal is used to output a current proportional to the designated
HS0-1 output.
1
2
3
CSNS
WAKE
RST
Output
Input
Output Current Monitoring
This terminal is used to input a Logic [1] signal so as to enable the
watchdog timer function.
Wake
This input terminal is used to initialize the device configuration and
fault registers, as well as place the device in a low current sleep mode.
Input
Reset (Active Low)
This input terminal is used to directly control the output HS0.
4
5
IN0
FS
Input
Direct Input 0
This is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
Output
Fault Status (Active Low)
The value of the resistance connected between this terminal and
ground determines the state of the outputs after a watchdog timeout
occurs.
6
FSI
Input
Fail-Safe Input
This input terminal is connected to a chip select output of a master
microcontroller (MCU).
7
8
9
CS
SCLK
SI
Input
Input
Input
Chip Select (Active Low)
Serial Clock
This input terminal is connected to the MCU providing the required bit
shift clock for SPI communication.
This is a command data input terminal connected to the SPI Serial
Data Output of the MCU or to the SO terminal of the previous device
of a daisy chain of devices.
Serial Input
This is an external voltage input terminal used to supply power to the
SPI circuit.
10
11
VDD
SO
Input
Digital Drain Voltage
(Power)
This output terminal is connected to the SPI Serial Data Input terminal
of the MCU or to the SI terminal of the next device of a daisy chain of
devices.
Output
Serial Output
This input terminal is used to directly control the output HS1.
12
13
IN1
Input
Direct Input 1
Ground
This terminal is the ground for the logic and analog circuitry of the
device.
GND
Ground
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
TERMINAL CONNECTIONS
Table 2. Terminal Definitions
Functional descriptions of many of these terminals can be found in the Functional Terminal Description section beginning on
page 10.
Terminal
Name
Terminal
Function
Terminal
Formal Name
Definition
This terminal connects to the positive power supply and is the source
input of operational power for the device.
14
VPWR
Input
Positive Power Supply
Protected 4.0 mΩ high-side power output to the load.
Protected 4.0 mΩ high-side power output to the load.
15
16
HS1
HS0
Output
Output
High-Side Output 1
High-Side Output 0
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Electrical Ratings
Operating Voltage Range
Steady-State
VPWR
V
-16 to 41
-0.3 to 5.5
-0.3 to 7.0
VDD Supply Voltage
VDD
V
V
Input/Output Voltage (1)
VIN[0:1], RST, FSI
CSNS, SI, SCLK,
CS, FS
SO Output Voltage (1)
VSO
ICL(WAKE)
ICL(CSNS)
VHS
-0.3 to VDD+0.3
V
mA
mA
V
WAKE Input Clamp Current
CSNS Input Clamp Current
2.5
10
Output Voltage
Positive
41
Negative
-15
Output Current (2)
Output Clamp Energy (3)
ESD Voltage (4)
IHS[0:1]
30
A
J
ECL[0:1]
0.75
V
VESD1
Human Body Model (HBM)
33984, 33984B
±2000
±200
VESD2
VESD3
Machine Model (MM)
33984
33984B
Charge Device Model (CDM)
Corner Terminals (1, 12, 15, 16)
All Other Terminals (2, 11, 13, 14)
±750
±500
Thermal Ratings
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 150
°C
Thermal Resistance (5)
Junction-to-Case
°C/W
R
R
<1.0
20
JC
JA
θ
Junction-to-Ambient
θ
Peak Terminal Reflow Temperature During Solder Mounting (6)
TSOLDER
230
°C
Notes
1. Exceeding voltage limits on RST, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω); ESD2 testing is
performed in accordance with the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from HS to GND; ESD3 testing is performed in accordance with the Charge Device
Model (CDM), Robotic (Czap=4.0pF).
5. Device mounted on a 2s2p test board according to JEDEC JESD51-2.
6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Input
Battery Supply Voltage Range
Full Operational
VPWR
V
6.0
–
–
–
27
20
VPWR Operating Supply Current
Output ON, IHS0 and IHS1 = 0 A
IPWR(ON)
mA
mA
VPWR Supply Current
IPWR(SBY)
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD
RST = VLOGIC HIGH
,
–
–
5.0
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
IPWR(SLEEP)
µA
TJ = 25°C
TJ = 85°C
–
–
–
–
10
50
V
V
DD Supply Voltage
VDD(ON)
IDD(ON)
4.5
5.0
5.5
V
DD Supply Current
mA
No SPI Communication
3.0 MHz SPI Communication
–
–
–
–
1.0
5.0
V
DD Sleep State Current
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
VPWR(UVHYS)
VPWR(UVPOR)
–
28
0.2
5.0
–
–
32
5.0
36
1.5
6.0
–
µA
V
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown Threshold (7)
Undervoltage Hysteresis (8)
Undervoltage Power-ON Reset
Notes
0.8
5.5
0.25
–
V
V
V
–
5.0
V
7. This applies to all internal device logic supplied by VPWR and assumes the external VDD supply is within specification.
8. This applies when the undervoltage fault is not latched (IN[0:1] = 0).
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Output
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 25°C)
RDS(ON)
mΩ
V
V
V
PWR = 6.0 V
PWR = 10 V
PWR = 13 V
–
–
–
–
–
–
6.0
4.0
4.0
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 150°C)
RDS(ON)
mΩ
V
V
V
PWR = 6.0 V
PWR = 10 V
PWR = 13 V
–
–
–
–
–
–
10.2
6.8
6.8
Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25°C (9)
RDS(ON)
mΩ
VPWR = -12 V
–
–
8.0
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
SOCH = 0
SOCH = 1
IOCH0
IOCH1
80
60
100
75
120
90
Overcurrent Low Detection Levels (SOCL[2:0])
A
000
001
010
011
100
101
110
111
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
21
18
16
14
12
10
8.0
6.0
25
22.5
20
29
27
24
21
18
15
12
9.0
17.5
15
12.5
10
7.5
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
–
DICR D2 = 0
DICR D2 = 1
CSR0
CSR1
–
–
1/20500
1/41000
–
–
Current Sense Ratio (CSR0) Accuracy
CSR0_ACC
%
Output Current
5.0 A
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
10 A
12.5 A
15 A
20 A
25 A
Notes
9. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Output (continued)
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
5.0 A
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
10 A
12.5 A
15 A
20 A
25 A
Current Sense Clamp Voltage
CSNS Open; IHS[0:1] = 29 A
VCL(CSNS)
V
4.5
30
6.0
–
7.0
Open Load Detection Current (10)
IOLDC
100
µA
Output Fault Detection Threshold
Output Programmed OFF
VOLD(THRES)
V
2.0
3.0
4.0
Output Negative Clamp Voltage
VCL
V
0.5 A < IHS[0:1] < 2.0 A, Output OFF
-20
160
5.0
–
175
–
-15
190
20
Overtemperature Shutdown (11)
Overtemperature Shutdown Hysteresis (11)
Notes
TSD
°C
°C
TSD(HYS)
10. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of
an open load condition when the specific output is commanded OFF.
11. Guaranteed by process monitoring. Not production tested.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Control Interface
Input Logic High Voltage (12)
Input Logic Low Voltage (12)
VIH
VIL
0.7VDD
–
–
–
–
V
V
0.2VDD
Input Logic Voltage Hysteresis (13)
33984B
33984
VIN[0:1](HYS)
100
60
600
650
1200
750
mV
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
IDWN
VRST
5.0
4.5
–
–
20
5.5
20
µA
V
5.0
–
SO, FS Tri-State Capacitance (14)
Input Logic Pull-Down Resistor (RST) and WAKE
Input Capacitance (14)
CSO
pF
kΩ
pF
V
RDWN
CIN
100
–
200
4.0
400
12
WAKE Input Clamp Voltage (15)
VCL(WAKE)
I
CL(WAKE) < 2.5 mA
7.0
-2.0
0.8VDD
–
–
–
14
-0.3
–
WAKE Input Forward Voltage
CL(WAKE) = -2.5 mA
VF(WAKE)
V
V
I
SO High-State Output Voltage
OH = 1.0 mA
VSOH
I
–
FS, SO Low-State Output Voltage
OL = -1.6 mA
VSOL
V
I
0.2
0
0.4
5.0
20
SO Tri-State Leakage Current
CS > 0.7VDD
ISO(LEAK)
µA
µA
kΩ
-5.0
5.0
Input Logic Pull-Up Current (16)
CS, VIN[0:1] > 0.7 VDD
IUP
–
FSI Input Terminal External Pull-down Resistance
FSI Disabled, HS[0:1] Indeterminate
FSI Enabled, HS[0:1] OFF
RFS
RFSdis
–
0
6.5
1.0
7.0
19
–
RFSoffoff
RFSonoff
RFSonon
6.0
15
40
FSI Enabled, HS0 ON, HS1 OFF
FSI Enabled, HS[0:1] ON
17
Infinite
Notes
12. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage reference to VPWR
.
13. No hysteresis on FSI and wake pins. Parameter is guaranteed by processing monitoring but is not production tested.
14. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
15. The current must be limited by a series resistance when using voltages > 7.0 V.
16. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD
.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Power Output Timing
Output Rising Slow Slew Rate A (DICR D3 = 0) (17)
9.0 V < VPWR < 16 V
SRRA_SLOW
SRRB_SLOW
SRRA_FAST
SRRB_FAST
SRFA_SLOW
SRFB_SLOW
SRFA_FAST
SRFB_FAST
tDLY(ON)
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
µs
0.2
0.03
0.4
0.6
0.1
1.0
0.1
0.6
0.1
2.0
0.35
15
1.2
0.3
4.0
1.2
1.2
0.3
4.0
1.2
100
500
Output Rising Slow Slew Rate B (DICR D3 = 0) (18)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (17)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1) (18)
9.0 V < VPWR < 16 V
0.03
0.2
Output Falling Slow Slew Rate A (DICR D3 = 0) (17)
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0) (18)
9.0 V < VPWR < 16 V
0.03
0.8
Output Falling Fast Slew Rate A (DICR D3 = 1) (17)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (18)
9.0 V < VPWR < 16 V
0.1
Output Turn-ON Delay Time in Fast/Slow Slew Rate (19)
DICR = 0, DICR = 1
1.0
Output Turn-OFF Delay Time in Slow Slew Rate Mode (20)
DICR = 0
tDLY_SLOW(OFF)
tDLY_FAST(OFF)
fPWM
µs
20
230
Output Turn-OFF Delay Time in Fast Slew Rate Mode (20)
DICR = 1
µs
10
–
60
200
–
Direct Input Switching Frequency (DICR D3 = 0)
300
Hz
Notes
17. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V. These parameters are
guaranteed by process monitoring.
18. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = VPWR-3.5 V to VPWR-0.5 V. These parameters
are guaranteed by process monitoring.
19. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive
load.
20. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL = 5.0 Ω resistive load.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Power Output Timing (continued)
Symbol
Min
Typ
Max
Unit
Overcurrent Detection Blanking Time (OCLT[1:0])
ms
tOCL0
tOCL1
tOCL2
tOCL3
00
01
10
11
108
7.0
155
10
202
13
0.8
1.2
1.6
0.08
0.15
0.25
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (21)
tOCH
1.0
–
10
–
20
10
µs
µs
tCNSVAL
HS0 Switching Delay Time (OSD[2:0])
ms
000
001
010
011
100
101
110
111
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
–
0
–
55
75
95
110
165
220
275
330
385
150
225
300
375
450
525
190
285
380
475
570
665
HS1 Switching Delay Time (OSD[2:0])
ms
000
001
010
011
100
101
110
111
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
–
0
–
–
0
–
110
110
220
220
330
330
150
150
300
300
450
450
190
190
380
380
570
570
Watchdog Timeout (WD[1:0]) (22)
ms
00
01
10
11
tWDTO0
tWDTO1
tWDTO2
tWDTO3
434
207
620
310
806
403
1750
875
2500
1250
3250
1625
Notes
21. Time necessary for the CSNS to be within ±5% of the targeted value.
22. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured
watchdog timeouts.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
SPI Interface Characteristics
Symbol
Min
Typ
Max
Unit
Recommended Frequency of SPI Operation
fSPI
tWRST
tCS
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
(23)
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (24)
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (24)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (24)
Required High State Duration of SCLK (Required Setup Time) (24)
Required Low State Duration of SCLK (Required Setup Time) (24)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (24)
SI to Falling Edge of SCLK (Required Setup Time) (25)
tENBL
tLEAD
tWSCLKh
tWSCLKl
tLAG
–
50
–
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
Falling Edge of SCLK to SI (Required Setup Time) (25)
83
SO Rise Time
CL = 200 pF
–
25
50
SO Fall Time
CL = 200 pF
tFSO
ns
–
–
–
–
–
25
–
50
50
SI, CS, SCLK, Incoming Signal Rise Time (25)
tRSI
tRSI
ns
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Fall Time (25)
–
50
Time from Falling Edge of CS to SO Low Impedance (26)
Time from Rising Edge of CS to SO High Impedance (27)
tSO(EN)
tSO(DIS)
tVALID
–
145
145
65
Time from Rising Edge of SCLK to SO Data Valid (28)
0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF
–
65
105
Notes
23. RST low duration measured with outputs enabled and going to OFF or disabled condition.
24. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
25. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
26. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
27. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
28. Time required to obtain valid data out from SO following the rise of SCLK.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR
VPWR -0.5 V
S
SRFB_SLOW & SRFB_FAST
SRRB_SLOW & SRRB_FAST
VPWR-3.5V
SRRA_SLOW & SRRA_FAST
SRFA_SLOW & SRFA_FAST
0.5 V
HS
tDLY_SLOW(OFF) & tDLY_FAST(OFF)
t
DLY(ON)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load
Current
IOCLx
tOCH
Time
tOCLx
Figure 5. Overcurrent Shutdown
I
OCH0
OCH1
OCL0
I
I
IOCL1
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
t
OCL0
OCHx
OCL3
OCL2
OCL1
Figure 6. Overcurrent Low and High Detection
• During tochx, the device can reach up to Ioch0 overcurrent
level.
• During tocl3 or tocl2 or tocl1 or tocl0, the device can be
programmed to detect up to Iocl0.
Figure 6 illustrates the overcurrent detection level
(Ioclx, Iochx) the device can reach for each overcur-
rent detection blanking time (tochx, toclx):
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
TIMING DIAGRAMS
VIH
RST
0.2 VDD
0.2 VDD
VIL
tENBL
t CS
tWRST
VIH
0.7 V
DD
C
0.2V
DD
VIL
tRSI
t
WSCLKh
TrSI
t
LEAD
tLAG
VIH
0.7 VDD
SCLK
0.2 VDD
VIL
t
SI(SU)
t
WSCLKl
tFSI
t
SI(HOLD)
VIH
0.7V
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
0.2V
DD
V
IH
Figure 7. Input Timing Switching Characteristics
tRSI
tFSI
VOH
3.5 V
50%
SCLK
1.0 V
VOL
tSO(EN)
VOH
0.7 V
DD
SO
0.2 VDD
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
0.7 V
DD
High to Low
0.2 VDD
VOL
tSO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33984 is a dual self-protected 4.0 mΩ silicon switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes self-
recovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented
via the Serial Peripheral Interface (SPI). A dedicated parallel
input is available for alternate and Pulse Width Modulation
(PWM) control of each output. SPI-programmable fault trip
thresholds allow the device to be adjusted for optimal
performance in the application.
The 33984 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL TERMINAL DESCRIPTION
watchdog circuit and fail-safe operation are disabled. This
terminal incorporates an active internal pull-up current
source.
OUTPUT CURRENT MONITORING (CSNS)
This terminal is used to output a current proportional to the
designated HS0-1 output. That current is fed into a ground-
referenced resistor and its voltage is monitored by an MCU's
A/D. The channel to be monitored is selected via the SPI.
This terminal can be tri-stated through SPI.
CHIP SELECT (CS)
This input terminal is connected to a chip select output of
a master microcontroller (MCU). The MCU determines which
device is addressed (selected) to receive data by pulling the
CS terminal of the selected device Logic LOW, enabling SPI
communication with the device. Other unselected devices on
the serial link having their CS terminals pulled-up Logic HIGH
disregard the SPI communication data sent. This terminal
incorporates an active internal pull-up current source.
WAKE (WAKE)
This terminal is used to input a Logic [1] signal so as to
enable the watchdog timer function. An internal clamp
protects this terminal from high damaging voltages when the
output is current limited with an external resistor. This input
has a passive internal pulldown.
SERIAL CLOCK (SCLK)
RESET (RST)
This input terminal is connected to the MCU providing the
required bit shift clock for SPI communication. It transitions
This input terminal is used to initialize the device
configuration and fault registers, as well as place the device
in a low current sleep mode. The terminal also starts the
watchdog timer when transitioning from Logic LOW to Logic
HIGH. This terminal should not be allowed to be Logic HIGH
until VDD is in regulation. This terminal has a passive internal
one time per bit transferred at an operating frequency, fSPI
,
defined by the communication interface. The 50 percent duty
cycle CMOS-level serial clock signal is idle between
command transfers. The signal is used to shift data into and
out of the device. This input has an active internal pulldown
current source.
pulldown.
DIRECT IN 1 & 2 (INx)
SERIAL INPUT (SI)
This input terminal is used to directly control the output
HS0 and 1. This input has an active internal pulldown current
source and requires CMOS logic levels. This input may be
configured via SPI.
This is a command data input terminal connected to the
SPI Serial Data Output of the MCU or to the SO terminal of
the previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an active
internal pull-down current source. Device control is facilitated
by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the
falling edge of SCLK. The logic state of SI present upon the
rising edge of SCLK loads that bit command into the internal
command shift register.
FAULT STATUS (FS)
This is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. When a
device fault condition is detected, this terminal is active LOW.
Specific device diagnostic faults are reported via the SPI SO
terminal.
DIGITAL DRAIN VOLTAGE (VDD)
FAIL-SAFE INPUT (FSI)
This is an external voltage input terminal used to supply
power to the SPI circuit. In the event VDD is lost, an internal
The value of the resistance connected between this
terminal and ground determines the state of the outputs after
a watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HS0 only
is ON. When the FSI terminal is connected to GND, the
supply provides power to a portion of the logic, ensuring
limited functionality of the device. All device configuration
registers are reset.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
SERIAL OUTPUT (SO)
POSITIVE POWER SUPPLY (VPWR)
This output terminal is connected to the SPI Serial Data
Input terminal of the MCU or to the SI terminal of the next
device of a daisy chain of devices. This output will remain tri-
stated (high impedance OFF condition) so long as the CS
terminal of the device is Logic HIGH. SO is only active when
the CS terminal of the device is asserted Logic LOW. The
generated SO output signals are CMOS logic levels. SO
output data is available on the falling edge of SCLK and
transitions immediately on the rising edge of SCLK.
This terminal connects to the positive power supply and is
the source input of operational power for the device. The
VPWR terminal is a backside surface mount tab of the
package.
HIGH-SIDE OUTPUT 1 & 2 (HSx)
This termianl protects 4.0 mΩ high-side power output to
the load.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
operationAL modes
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33984 has four operating modes: Sleep, Normal,
Fault, and Fail-Safe. Table 6 summarizes details contained in
succeeding paragraphs.
input is capable of being pulled up to VPWR with a series of
limiting resistance that limits the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 15. As long as the WD bit (D7) of an
incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the
programmed value of the WDR the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-Safe mode until the
device is reinitialized.
Table 6. Fail-Safe Operation and Transitions to Other
33984 Modes
Mode
FS WAKE RST WDTO
Comments
Device is in Sleep mode.
All outputs are OFF.
Sleep
x
0
x
0
1
x
Normal mode. Watchdog
is active if enabled.
Normal
Fault
1
No
No
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI
terminal, regardless of the state of the various direct inputs
and modes (Table 7). In this mode, the SPI register content
is retained except for overcurrent high and low detection
levels and timing, which are reset to their default value
(SOCL, SOCH, and OCLT). Then the watchdog, overvoltage,
overtemperature, and overcurrent circuitry (with default
value) are fully operational.
The device is currently in
Fault mode. The faulted
output(s) is (are) OFF.
0
0
1
x
x
1
Watchdog has timed out
and the device is in Fail-
Safe mode. The outputs
are as configured with
the RFS resistor
1
1
1
0
1
1
1
1
0
Yes
connected to FSI. RST
and WAKE must be
transitioned to Logic [0]
simultaneously to bring
the device out of the Fail-
Safe mode or
Fail-
Safe
Table 7. Output State During Fail-Safe Mode
RFS (kΩ)
High-Side State
0
Fail-Safe Mode Disabled
Both HS0 and HS1 OFF
HS0 ON, HS1 OFF
momentarily tied the FSI
terminal to ground.
6.0
15
30
x = Don’t care.
Both HS0 and HS1 ON
SLEEP MODE
The default mode of the 33984 is the Sleep mode. This is
the state of the device after first applying battery voltage
(VPWR), prior to any I/O transitions. This is also the state of
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is Logic [1] when the
device is in fail-safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST
terminals from Logic [1] to Logic [0] or forcing the FSI
terminal to Logic [0]. Table 6 summarizes the various
methods for resetting the device from the latched Fail-Safe
mode.
the device when the WAKE and RST are both Logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to Logic [0]. The device will transition to the
Normal or Fail-Safe operating modes based on the WAKE
and RST inputs as defined in Table 6.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
NORMAL MODE
LOSS OF VDD
The 33984 is in Normal mode when:
• VPWR is within the normal voltage range.
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The two
outputs can still be driven by the direct inputs IN1:IN0. The
33984 uses the battery input to power the output MOSFET-
related current sense circuitry and any other internal logic
providing fail-safe device operation with no VDD supplied. In
this state, the watchdog, overvoltage, overtemperature, and
overcurrent circuitry are fully operational with default values.
•
RST terminal is Logic [1].
• No fault has occurred.
FAIL-SAFE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input
terminal transitions from Logic [0] to Logic [1]. The WAKE
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
• Overvoltage and undervoltage fault
FAULT MODE
The FS terminal will automatically return to Logic [1] when
the fault condition is removed, except for Overcurrent and in
some cases Undervoltage.
The 33984 indicates the following faults as they occur by
driving the FS terminal to Logic [0]:
• Overtemperature fault
• Open load fault
• Overcurrent fault (high and low)
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 17).
PROTECTION AND DIAGNOSIS FEATURES
The undervoltage protection can be disabled through SPI
(bit UV_dis = 1). In this case, the FS and UVF bit do not report
any undervoltage fault condition and the output state will not
be changed as long as battery voltage does not drop any
lower than 2.5 V.
OVERTEMPERATURE FAULT (NON-LATCHING)
The 33984 incorporates overtemperature detection and
shutdown circuitry in each output structure. Overtemperature
detection is enabled when an output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or
until the offending load is removed.
OPEN LOAD FAULT (NON-LATCHING)
The 33984 incorporates open load detection circuitry on
each output. Output open load fault (OLF) is detected and
reported as a fault condition when that output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
When experiencing this fault, the OTF fault bit will be set
in the status register and cleared after either a valid SPI read
or a power reset of the device.
OVERVOLTAGE FAULT (NON-LATCHING)
The 33984 shuts down the output during an overvoltage
fault (OVF) condition on the VPWR terminal. The output
The open load protection can be disabled trough SPI (bit
OL_dis).
remains in the OFF state until the overvoltage condition is
removed. When experiencing this fault, the OVF fault bit is
set in the bit OD1 and cleared after either a valid SPI read or
a power reset of the device.
OVERCURRENT FAULT (LATCHING)
The device has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent
The overvoltage protection and diagnostic can be disabled
trough SPI (bit OV_dis).
high detection levels (IOCH) for maximum device protection.
The two selectable, simultaneously active overcurrent
detection levels, defined by IOCH and IOCL, are illustrated in
UNDERVOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
Figure 6. The eight different overcurrent low detect levels
(IOCL0:IOCL7) are likewise illustrated in Figure 6.
The output(s) will latch off at some battery voltage below
6.0 V. As long as the VDD level stays within the normal
If the load current level ever reaches the selected
overcurrent low detect level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the effected output OFF.
specified range, the internal logic states within the device will
be sustained.
In the case where battery voltage drops below the
undervoltage threshold (VPWRUV) output will turn off, FS will
go to Logic [0], and the fault register UVF bit will be set to 1.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCL driver.
Two cases need to be considered when the battery level
recovers :
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
• If output(s) command is (are) low, FS will go to Logic [1]
but the UVF bit will remain set to 1 until the next read
operation.
REVERSE BATTERY
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gates are
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required.
• If the output command is ON, then FS will remain at
Logic [0]. The output must be turned OFF and ON again
to re-enable the state of output and release FS . The
UVF bit will remain set to 1 until the next read operation.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
GROUND DISCONNECT PROTECTION
disconnection. A 10K resistor needs to be added between
thewake pin and the rest of the circuitry in order to ensure that
the device turns off in case of ground disconnect and to
prevent this pin to exceed its maximum ratings
In the event the 33984 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
.
Table 8. Device Behavior in Case of Undervoltage
UV Disable
UV Enable
UV Enable
IN=0
(Falling or
UV Enable
IN=1
UV Enable
IN=1
IN=0
(Falling or
Rising
SPD4
IN=0
State
(VPWR Batter Voltage)∗∗
(Falling or
Rising VPWR) Rising VPWR)
(Falling VPWR) (Rising VPWR)
VPWR)
VPWR > VPWRUV
Output State
OFF
1
OFF
ON
1
OFF
0
OFF
FS State
1
1
0
SPI Fault Register UVF Bit
0
1 until next read
0
1
VPWRUV > VPWR > UVPOR Output State
FS State
OFF
0
OFF
OFF
0
OFF
0
OFF
1
0
SPI Fault Register UVF Bit
Output State
1
1 until next read
1
1
0
UVPOR > VPWR > 2.5 V∗
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
FS State
SPI Fault Register UVF Bit
Output State
1 until next read 1 until next read 1 until next read 1 until next read
0
2.5 V > VPWR > 0V
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
FS State
SPI Fault Register UVF Bit
Comments
1 until next read 1 until next read 1 until next read 1 until next read
0
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
∗ = Typical value; not guaranteed
∗∗ = While VDD remains within specified range.
LOGIC COMMANDS AND REGISTERS
while the serial output (SO) terminal shifts data information
out of the SO line driver on the rising edge of the SCLK signal.
It is important that the SCLK terminal be in a logic low state
whenever CS makes any transition. For this reason, it is
recommended that the SCLK terminal be in a Logic [0] state
whenever the device is not accessed (CS Logic [1] state).
SCLK has an active internal pull-down, IDWN. When CS is
Logic [1], signals at the SCLK and SI terminals are ignored
and SO is tri-stated (high impedance). See Figure 9 and
Figure 10.
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO terminals of the 33984 follow a first-in first-out
(D7/D0) protocol with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
SERIAL INPUT (SI)
SERIAL CLOCK (SCLK)
This is a serial interface (SI) command data input terminal.
SI instruction is read on the falling edge of SCLK. An 8-bit
stream of serial data is required on the SI terminal, starting
with D7 to D0. The internal registers of the 33984 are
Serial clocks (SCLK) the internal shift registers of the
33984 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
configured and controlled using a 4-bit addressing scheme,
as shown in Table 9. Register addressing and configuration
are described in Table 10. The SI input has an active internal
CHIP SELECT (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a Logic [0]
state, the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device
latches in data from the Input shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS
is Logic [0]. CS should transition from a Logic [1] to a Logic [0]
state only when SCLK is a Logic [0]. CS has an active internal
pull-down, IDWN
.
SERIAL OUTPUT (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high impedance state
until the CS terminal is put into a Logic [0] state. The SO data
is capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO
terminal changes states on the rising edge of SCLK and
reads out on the falling edge of SCLK. Fault and Input Status
descriptions are provided in Table 6.
pull-up, IUP
.
CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1. RST is a Logic [1] state during the above operation.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 9. Single 8-Bit Word SPI Communication
CS
SCLK
C K
S
SI
S
I
D
7
D
6
D
5
D
2
D
1
D
0
D
7
*
D
6
*
D
5
*
D
2
*
D
1
*
D
0
*
SO
O
D
7
O
D
6
O
D
5
O
D
2
O
D
1
O
D
0
D
7
D
6
D
5
D
2
D
1
D
0
Notes
1. RST is a Logic [1] state during the above operation.
2. D7:D0relate to the most recentorderedentry of data into the device.
3. D7*:D0* relateto the previous8 bits (lastcommandword)of data thatwas previously shifted into the device.
4. OD7:OD0 relate to thefirst8bits ofordered fault and statusdata out ofthedevice.
Figure 10. Multiple 8-Bit Word SPI Communication
is the watchdog bit and in some cases a register address bit
common to both outputs or specific to an output; the next
three bits, D6:D4, are used to select the command register;
and the remaining four bits, D3:D0, are used to configure and
control the outputs and their protection features.
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit
messages. A message is transmitted by the MCU starting
with the MSB, D7, and ending with the LSB, D0 (Table 9).
Each incoming command message on the SI terminal can be
interpreted using the following bit assignments: the MSB (D7)
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
Address x000—Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2:D0, determine the content of the first eight bits of SO data.
When register content is specific to one of the two outputs, bit
D7 is used to select the desired output (SOA3). In addition to
the device status, this feature provides the ability to read the
content of the OCR, SOCHLR, CDTOLR, DICR, OSDR,
WDR, NAR, and UOVR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data).)
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 10, summarizes the SI registers. The registers are
addressed via D6:D4 of the incoming SPI word (Table 9).
Table 9. SI Message Bit Assignment
Bit Sig SI Msg Bit
Message Bit Description
Address x001—Output Control Register (OCR)
Register address bit for output selection.
Also used for Watchdog: toggled to satisfy
watchdog requirements.
MSB
D7
The OCR register allows the MCU to control the outputs
through the SPI. Incoming message bit D0 reflects the
desired states of the high-side output HS0 (IN0_SPI): a
Logic [1] enables the output switch and a Logic [0] turns it
OFF. A Logic [1] on message bit D1 enables the Current
Sense (CSNS) terminal. Similarly, incoming message bit D2
reflects the desired states of the high-side output HS1
(IN1_SPI): Logic [1] enables the output switch and a Logic [0]
turns it OFF. A Logic [1] on message bit D3 enables the
CSNS terminal. In the event that the current sense is enabled
for both outputs, the current will be summed. Bit D7 is used
to feed the watchdog if enabled.
Register address bits.
D6:D4
D3:D1
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
LSB
D0
Address x010— Select Overcurrent High and Low
Register (SOCHLR)
Table 10. Serial Input Address and Configuration Bit
Map
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels,
Serial Input Data
SI
Register
respectively. Each output is independently selected for
configuration based on the state of the D7 bit; a write to this
register when D7 is Logic [0] will configure the current
detection levels for the HS0. Similarly, if D7 is Logic [1] when
this register is written, HS1 is configured. Each output can be
configured to different levels. In addition to protecting the
device, this slow blow fuse emulation feature can be used to
optimize the load requirements matching system
characteristics. Bits D2:D0 set the overcurrent low detection
level to one of eight possible levels, as shown in Table 11.
Bit D3 sets the overcurrent high detection level to one of two
levels, which is described in Table 12.
D7 D6 D5 D4
D3
D2
D1
D0
STATR
OCR
s
x
0
0
0
0
0
1
0
SOA2
SOA1
SOA0
CSNS1 IN1_SPI CSNS0 IN0_SPI
EN EN
SOCHLR
CDTOLR
DICR
s
s
s
0
0
1
1
1
0
0
1
0
SOCHs SOCL2s SOCL1s SOCL0s
OL DIS s CD DISs OCLT1s OCLT0s
FAST
SR s
CSNS IN DIS s A/Os
high s
OSDR
WDR
NAR
0
1
0
1
x
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
0
0
OSD2
OSD1
WD1
0
OSD0
WD0
0
0
0
0
UOVR
TEST
UV_dis OV_dis
Freescale Internal Use (Test)
x = Don’t care.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =
HS1.
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address x100—Direct Input Control Register (DICR)
Table 11. Overcurrent Low Detection Levels
The DICR register is used by the MCU to enable, disable,
or configure the direct IN terminal control of each output.
Each output is independently selected for configuration
based on the state of bit D7. A write to this register when bit
D7 is Logic [0] will configure the direct input control for the
HS0. Similarly, if D7 is Logic [1] when this register is written,
then HS1 is configured.
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
22.5
20
A Logic [0] on bit D1 will enable the output for direct control
by the IN terminal. A Logic [1] on bit D1 will disable the output
from direct control. While addressing this register, if the input
was enabled for direct control, a Logic [1] for the D0 bit will
result in a Boolean AND of the IN terminal with its
corresponding D0 message bit when addressing the OCR
register. Similarly, a Logic [0] on the D0 terminal results in a
Boolean OR of the IN terminal with the corresponding
message bits when addressing the OCR register.
17.5
15
12.5
10
7.5
The DICR register is useful if there is a need to
Table 12. Overcurrent High Detection Levels
independently turn on and off several loads that are PWM’d
at the same frequency and duty cycle with only one PWM
signal. This type of operation can be accomplished by
connecting the pertinent direct IN terminals of several
devices to a PWM output port from the MCU and configuring
each of the outputs to be controlled via their respective direct
IN terminal. The DICR is then used to Boolean AND the direct
IN(s) of each of the outputs with the dedicated SPI bit that
also controls the output. Each configured SPI bit can now be
used to enable and disable the common PWM signal from
controlling its assigned output.
Overcurrent High Detection
SOCH (D3)
(Amperes)
0
1
100
75
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state
of the D7 bit. A write to this register when bit 7 is Logic [0] will
configure the timeout for the HS0. Similarly, if D7 is Logic [1]
when this register is written, then HS1 is configured. Bits
D1:D0 allow the MCU to select one of four fault blanking
times defined in Table 13. Note that these timeouts apply
only to the overcurrent low detection levels. If the selected
overcurrent high level is reached, the device will latch off
within 20 µs.
A Logic [1] on bit D2 is used to select the high ratio (CSR1
1/41000) on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (CSR0
,
,
1/20500). A Logic [1] on bit D3 is used to select the high
speed slew rate for the selected output. The default value [0]
corresponds to the low speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register configures the device with a
programmable time delay that is active during Output ON
transitions initiated via SPI (not via direct input).
Table 13. Overcurrent Low Detection Blanking Time
A write to this register configures both outputs for different
delay. Whenever the input is commanded to transition from
Logic [0] to Logic [1], both outputs will be held OFF for the
time delay configured in the OSDR. The programming of the
contents of this register have no effect on device fail-safe
mode operation. The default value of the OSDR register is
000, equating to no delay. This feature allows the user a way
to minimize inrush currents, or surges, thereby allowing loads
to be switched ON with a single command. There are eight
selectable output switching delay times that range from 0 ms
to 525 ms. Refer to Table 14.
OCLT[1:0]
Timing
00
01
10
11
155 ms
10 ms
1.2 ms
150 µs
A Logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A Logic [1] on bit D3 disables the
open load (OL) detection feature.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SERIAL OUTPUT COMMUNICATION
(DEVICE STATUS RETURN DATA)
Table 14. Switching Delay
Turn ON Delay (ms) Turn ON Delay (ms)
When the CS terminal is pulled low, the output status
register is loaded. Meanwhile, the data is clocked out MSB-
(OD7-) first as the new message data is clocked into the SI
terminal. The first eight bits of data clocking out of the SO,
and following a CS transition, are dependant upon the
previously written SPI word.
OSD[2:0] (D2:D0)
HS0
HS1
000
001
010
011
100
101
110
111
0
0
75
0
150
225
300
375
450
525
150
150
300
300
450
450
Any bits clocked out of the SO terminal after the first eight
will be representative of the initial message bits clocked into
the SI terminal since the CS terminal first transitioned to a
Logic [0]. This feature is useful for daisy chaining devices as
well as message verification.
A valid message length is determined following a CS
transition of Logic [0] to Logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A
valid message length is a multiple of eight bits. At this time,
the SO terminal is tri-stated and the fault status register is
now able to accept new fault status information.
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1:D0. When D1:D0 bits are programmed for the desired
watchdog timeout period, the WD bit (D7) should be toggled
as well, ensuring the new timeout period is programmed at
the beginning of a new count sequence. Refer to Table 15.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a Logic [0] during SPI communication and/or for the
period of time since the last valid SPI communication, with
the following exceptions:
Table 15. Watchdog Timeout
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
WD[1:0] (D1:D0)
Timing (ms)
00
01
10
11
620
310
2500
1250
communication following an undervoltage VPWR
condition should be ignored.
• The RST terminal transition from a Logic [0] to Logic [1]
while the WAKE terminal is at Logic [0] may result in
incorrect data loaded into the status register. The SO
data transmitted to the MCU during the first SPI
communication following this condition should be
ignored.
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows
devices to not be affected by commands being clocked over
a daisy-chained SPI configuration, and by toggling the WD bit
(D7), the watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
SERIAL OUTPUT BIT ASSIGNMENT
The 8 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 16 summarizes the SO register content.
Address 1110—Undervoltage/Overvoltage Register
(UOVR)
Bit OD7 reflects the state of the watchdog bit (D7)
addressed during the prior communication. The value of the
previous D7 will determine which output the status
information applies to for the Fault (FLTR), SOCHLR,
CDTOLR, and DICR registers. SO data will represent
information ranging from fault status to register contents,
user selected by writing to the STATR bits D2:D0. Note that
the SO data will continue to reflect the information for each
output (depending on the previous D7 state) that was
selected during the most recent STATR write until changed
with an updated STATR write.
The UOVR register can be used to disable or enable
overvoltage and/or undervoltage protection. By default
(Logic [0]), both protections are active. When disabled, an
undervoltage or overvoltage condition fault will not be
reported in the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not
accessible with SPI during normal operation.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Previous Address SOA[2:0]=000
Previous Address SOA[2:0]=010
If the previous three MSBs are 000, bits OD6:OD0 will
reflect the current state of the Fault register (FLTR)
corresponding to the output previously selected with the bit
OD7 (Table 17).
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to Table 12), and the data in bits
OD2:OD0 contain the programmed overcurrent low detection
levels (refer to Table 13).
Previous Address SOA[2:0]=001
Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI
programmed bits, respectively. Data in bits OD3:OD2 contain
CSNS0 EN and IN0_SPI programmed bits, respectively.
Table 16. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
x
s
s
s
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
s
x
s
s
s
0
1
0
OTFs
OCHFs
OCLFs
OLFs
CSNS1 EN
SOCHs
UVF
OVF
CSNS0 EN
SOCL1s
OCLT1s
IN DIS s
OSD1
FAULTs
IN0_SPI
SOCL0s
OCLT0s
A/Os
0
0
0
1
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
IN1_SPI
SOCL2s
CD DIS s
OL DIS s
FAST SR s CSNS high s
FSM_HS0
FSM_HS1
OSD2
OSD0
WDTO
WD1
WD0
IN1 Terminal IN0 Terminal FSI Terminal
WAKE
Terminal
1
x
1
1
1
1
0
1
1
–
1
–
1
–
0
–
–
–
–
–
UV_dis
–
OV_dis
–
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
x = Don’t care.
Previous Address SOA[2:0]=100
The returned data contain the programmed values in the
DICR.
Table 17. Fault Register
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
OTF OCHFs OCLFs OLFs
UVF
OVF FAULTs
Previous Address SOA[2:0]=101
OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
OD6 (OTF) = Overtemperature Flag.
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS0) reflects the
state of the output HS0 in the Fail-Safe mode after a
watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status
of the watchdog circuitry. If WDTO bit is Logic [1], the
watchdog has timed out and the device is in Fail-Safe
mode. If WDTO is Logic [0], the device is in Normal
mode (assuming the device is powered and not in Sleep
mode), with the watchdog either enabled or disabled.
Bit OD3 (FSM_HS1) reflects the state of the output HS1
in the Fail-Safe mode after a watchdog timeout occurs.
OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.)
OD3 (OLFs) = Open Load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULTs) = This flag reports a fault and is reset by a read
operation.
Note The FS terminal reports a fault. For latched faults, this terminal
is reset by a new Switch ON command (via SPI or direct input IN).
Previous Address SOA[2:0]=011
Previous Address SOA[2:0] =110
Data returned in bits OD1 and OD0 are current values for
the overcurrent fault blanking time, illustrated in Table 13. Bit
OD2 reports if the overcurrent detection timeout feature is
active. OD3 reports if the open load circuitry is active.
• SOA3 = 0. OD3:OD0 return the state of the IN1, IN0,
FSI, and WAKE terminals, respectively (Table 18).
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
• SOA3 = 1. The returned data contain the programmed
values in the UOVR. Bit OD1 reflects the state of the
undervoltage protection and bit OD0 reflects the state of
the overvoltage protection. Refer to Table 16).
Table 18. Terminal Register
OD3
OD2
OD1
OD0
IN1 Terminal IN0 Terminal
FSI Terminal
WAKE Terminal
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2:OD0 are null, or 000.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
TYPICAL APPLICATIONS
LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
VPWR
VDD
Voltage
Regulator
VDD
VDD NC VPWR
VDD
VPWR
2.2 k
10 k
10
MCU
14
VDD
VPWR
HS
100nF
10µF
330µF
100nF
2
4
WAKE
IN0
1k
1k
15
16
I/O
I/O
12
8
IN1
1k
1k
33984
SCLK
CS
SCLK
CS
7
1k
3
I/O
RST
SO
SI
HS
11
9
SI
SO
I/O
1k
5
FS
LOAD
LOAD
1
13
CSNS
FSI
A/D
GND
6
1k
RI
Figure 11. Typical Applications
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
soldering information
PACKAGING
SOLDERING INFORMATION
• Convection: 225°C +5.0/-0°C
SOLDERING INFORMATION
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR)/Convection: 225°C +5.0/-0°C
The 33984 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 s to 40 s maximum.
The 33984 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10521D.
12
A
M
2X
12
1
0.1
C
PIN 1
INDEX AREA
12
15
16
M
2X
0.1 C
PIN NUMBER
REF. ONLY
B
0.1
C
2.20
1.95
2.2
2.0
0.05 C
4
DETAIL G
0.6
0.05
0.00
10X 0.2
0.1
SEATING PLANE
C
M
M
C A B
C
DETAIL G
0.95
0.55
0.1
0.05
VIEW ROTATED 90˚ CLOCKWISE
2X
9X 0.9
M
M
C A B
C
C A B
0.1
0.05
2X 1.075
5.0
4.6
1
12
1.1
0.6
6X
2.05
6X
1.55
13
2.5
2.1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
3.55
1.85
1.45
4X 1.05
5.5
5.1
14
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. MINIMUM METAL GAP SHOULD BE 0.25MM.
(2)
0.1 C A B
0.8
6X
0.4
16
15
(
10X 0.25)
2X 0.75)
0.1 C A
1.28
0.88
2X
(0.5)
(
2.25
1.75
0.15
0.05
(
10X 0.4)
(
10X 0.5)
6 PLACES
10.7
B
10.3
0.1 C A
B
B
11.2
10.8
0.1 C A
VIEW M-M
PNA SUFFIX
16-TERMINAL PQFN
NONLEADED PACKAGE
98ARL10521D
ISSUE B
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
PACKAGE DIMENSIONS
NOTES
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
PACKAGE DIMENSIONS
NOTES
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
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MC33984
Rev 5.0
08/2005
相关型号：
MC33984PNA/R2
Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз)
MOTOROLA
MC33988CHFK
Dual Intelligent High-current Self-protected Silicon High Side Switch (8.0 mOhm)
FREESCALE
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