MC33999EK [NXP]
1.2A SIPO BASED PRPHL DRVR, PDSO54, 0.65 MM PITCH, LEAD FREE, PLASTIC, SOIC-54;
| 型号： | MC33999EK |
| 厂家： | 
NXP |
| 描述： | 1.2A SIPO BASED PRPHL DRVR, PDSO54, 0.65 MM PITCH, LEAD FREE, PLASTIC, SOIC-54 驱动 CD 光电二极管 接口集成电路 驱动器 |
| 文件： | 总22页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33999
Rev. 6.0, 2/2014
escale Semiconductor
Technical Data
16-Output Switch with SPI
and PWM Control
33999
The 33999 is a 16-output low-side switch with a 24-bit serial input
control. It is designed for a variety of applications including inductive,
incandescent, and LED loads. The Serial Peripheral Interface (SPI)
provides both input control and diagnostic readout. Eight parallel inputs
are also provided for direct Pulse Width Modulation (PWM) control of
eight dedicated outputs. Additionally, an output-programmable PWM
input provides PWM of any combination of outputs. A dedicated reset
input provides the ability to clear all internal registers and turn all
outputs off.
POWER DUAL OCTAL SERIAL SWITCH WITH
SERIAL PERIPHERAL INTERFACE I/O
The 33999 directly interfaces with microcontrollers and is
compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33999,
in effect, serves as a bus expander and buffer with fault management
features that reduces the MCU’s fault management burden. This
device is powered by SMARTMOS technology.
EK SUFFIX (PB-FREE)
98ASA10506D
54-PIN SOICW EXPOSED PAD
Applications
Features
• Aircraft, automotive, and robotic systems
• Marine applications and farm equipment
• Actuator, small DC motor, LED and incandescent
lamp controls
• Other applications where low side switch control is
required
•
•
•
Designed to operate 5.0 V < VPWR < 27 V
24-Bit SPI for control and fault reporting, 3.3 V/5.0 V compatible
Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent
lamps
Output voltage clamp of +50 V during inductive switching
On/Off control of open load detect current (LED application)
VPWR standby current < 10 A
RDS(on) of 0.55 at 25 °C typical
Independent overtemperature protection
Output selectable for PWM control
Output ON short-to-VBAT and OFF short-to-ground/open detection
54-Pin Exposed Pad Package for Thermal Performance
•
•
•
•
•
•
•
•
V
V
PWR
BAT
3.3 V/5.0 V
33999
VDD
MCU
VPWR
SOPWR
SCLK
SCLK
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
Solenoid/Relay
CS
CS
MISO
MOSI
PWM
SI
SO
PWM
RST
RST
PWM0
LED
PWM1
PWM6
PWM7
PWM8
PWM9
PWM14
PWM15
Lamp
GND
Figure 1. 33999 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2007 - 2014. All rights reserved.
ERABLE PARTS
ORDERABLE PARTS
Table 1. Orderable Part Variations
Temperature (T )
Part Number
Package
A
MCZ33999EK/R2
-40 to 125 °C
54 SOICW-EP
33999
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
8
OUT0
2
Overvoltage
Detect
Voltage
Regulator
VDD
Bias
VDD
50 V
GE
OT
SF
OF
OVD
VDD
PWM
50
Gate
Control
OUT1–OUT15:
10 A
25 A
RB
SFPDB
3, 6, 7, 21, 22,
To Gates
1 to 15
25, 26, 29, 30,
33, 34, 48, 49,
52, 53
RST
47
SFL
CS
VRef
10 A
CS
23
SCLK
SI
SO
CSI
CSBI
Open
Input
Buffers
Load
Detect
Enable
ILIMIT
SCLK
20
RS
50 A
10 A
10 A
SI
32
SPI
Interface
Logic
GND Pins:
10–18
37–40
42–45
Short and
Open
Circuit
Serial D/O
Line Driver
Detect
SO
35
Overtemperature
Detect
SOPWR
5
From Detectors 1 to 15
PWM0
1
PWM0
10 A
10 A
10 A
10 A
10 A
10 A
10 A
10 A
PWM1
4
PWM1
PWM6
PWM7
PWM8
PWM9
PWM6
24
PWM7
27
PWM8
28
PWM9
31
PWM14
51
PWM14
PWM15
PWM15
54
Figure 2. 33999 Simplified Internal Block Diagram
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
CONNECTIONS
PIN CONNECTIONS
PWM0
OUT0
OUT1
PWM1
SOPWR
OUT2
OUT3
VPWR
NC
1
PWM15
OUT15
OUT14
PWM14
PWM
OUT13
OUT12
RST
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
2
3
4
5
6
7
8
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
NC
NC
NC
NC
SO
SCLK
OUT4
OUT5
CS
PWM6
OUT6
OUT7
PWM7
OUT11
OUT10
SI
PWM9
OUT9
OUT8
PWM8
Figure 3. 33999 Pin Connections
Table 2. 33999 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin
Name
Pin
Function
Pin Number
Formal Name
Definition
Parallel PWM control Input pins. Allows direct PWM control of
eight outputs.
1, 4, 24, 27, 28,
31, 51, 54
PWM0, PWM1,
PWM6–PWM9,
PWM14, PWM15
Input
PWMn Input
Low-side driver outputs.
2, 3, 6, 7, 21, 22,
25, 26, 29, 30, 33,
34, 48, 49, 52, 53
OUT0–OUT15
Output
Output 0–
Output 15
Power supply pin to the SO output driver.
Battery supply input pin.
5
8
SOPWR
VPWR
NC
Power
Input
N/C
SOPWR Supply
Battery Input
No Connect
These pins have no connection.
9, 10, 18, 19, 36,
37, 41, 45, 46
Ground for logic, analog, and power output devices.
11–17, 38–40,
42–44
GND
Ground
Ground
System Clock for internal shift registers of the 33999.
SPI control chip select input pin from MCU to 33999.
Serial data input pin to the 33999.
20
23
32
35
47
50
SCLK
CS
Input
Input
Input
Output
Input
Input
System Clock
Chip Select
Serial Input
Serial Output
Reset
SI
Serial data output pin.
SO
Active low reset input pin.
RST
PWM
PWM control input pin. Supports PWM on any combination of
outputs.
PWM Control Pin
33999
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage (1)
VPWR
SOPWR
VIN
-1.5 to 50
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 45
6.0
V
V
SPI Interface Logic Supply Voltage (1)
SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST, PWMn) (1)
Output Drain Voltage
V
V
VDS
Frequency of SPI Operation (2)
MHz
fSPI
Output Clamp Energy (3)
ECLAMP
50
mJ
V
ESD Voltage (4)
Human Body Model
Machine Model
VESD1
VESD2
±2000
±200
THERMAL RATINGS
Operating Temperature
Ambient
C
C
TA
TJ
-40 to 125
-40 to 150
-40 to 125
Junction
Case
TC
Storage Temperature
T
-55 to 150
1.7
STG
Power Dissipation (TA 25C) (5)
P
W
D
(7)
Peak Package Reflow Temperature During Reflow (6)
,
TPPRT
Note 7
°C
Thermal Resistance
C/W
Junction-to-Ambient (8)
R
75
8.0
1.2
JA
JL
Junction- to-Lead (9)
Junction-to-Flag
R
R
JC
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. This parameter is guaranteed by design but not production tested.
3. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
4. ESD data is available upon request. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500
) and the Machine Model (CZAP = 200 pF, RZAP = 0 ).
5. Maximum power dissipation with no heat sink used.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
8. Tested per JEDEC test JESD52-2 (single-layer PWB).
9. Tested per JEDEC test JESD51-8 (two-layer PWB).
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V SOPWR 5.5 V, 5.0 V VPWR 18 V, -40°C TC 125°C unless otherwise
noted. Typical values noted reflect the approximate parameter means at VPWR = 13 V, TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Range
Fully Operational
VPWR(
FO
V
)
5.0
–
–
27
Supply Current
IPWR(
mA
)
ON
All Outputs ON, IOUT = 0.3 A
4.0
8.0
Sleep State Supply Current at RST 0.2 SOPWR and/or SOPWR 0.5 V
Overvoltage Shutdown
IPWR(
–
1.0
31.5
1.4
3.2
–
10
35
A
V
)
SS
VOV
VOV (
27.5
0.6
–
Overvoltage Shutdown Hysteresis
2.3
4.0
5.5
500
10
V
)
HYS
VPWR(UV)
SOPWR
ISOPWR(RSTH)
ISOPWR(RSTL)
VPWR Undervoltage Shutdown
V
SPI Interface Logic Supply Voltage
3.1
100
-10
1.5
V
SPI Interface Logic Supply Current (RST Pin High)
SPI Interface Logic Supply Current (RST Pin Low)
SPI Interface Logic Supply Undervoltage Lockout Threshold
POWER OUTPUT
–
A
A
V
–
SOPWR(
UNVOL
2.5
3.0
)
Drain-to-Source ON Resistance (IOUT = 0.35 A, VPWR = 13 V)
RDS(ON)
T = 125C
–
–
–
0.75
0.55
0.45
1.1
–
J
T = 25C
J
–
T = -40C
J
Output Self-Limiting Current
Outputs Programmed ON
IOUT(
A
V
)
LIM
0.9
2.5
25
1.2
3.0
50
2.5
3.5
100
Output Fault Detect Threshold (10)
Outputs Programmed OFF
VOUT
(F)
TH
Output Off Open Load Detect Current (11)
IOCO
A
Outputs Programmed OFF (V
= 5.0 V, 13 V, 18 V)
PWR
Output Clamp Voltage
VCL
V
2.0 mA IOUT 200 mA
45
50
55
10
Output Leakage Current
IOUT(
LKG
A
)
SOPWR 2.0 V
-10
2.0
Overtemperature Shutdown (Outputs OFF) (12)
Overtemperature Shutdown Hysteresis (12)
Notes
TLIM
TLIM(
155
5.0
165
10
180
20
C
C
)
HYS
10. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts.
11. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded to be OFF.
12. This parameter is guaranteed by design but is not production tested.
33999
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V SOPWR 5.5 V, 5.0 V VPWR 18 V, -40°C TC 125°C unless otherwise
noted. Typical values noted reflect the approximate parameter means at VPWR = 13 V, TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (13)
VINLOGIC
VINRST
ISI
0.8
0.8
–
–
2.2
2.2
V
V
Input Logic Voltage Thresholds for RST
SI Pulldown Current
SI = 5.0 V
A
2.0
-30
2.0
10
-10
10
30
-2.0
30
CS Pullup Current
CS = 0 V
ICS
ISCLK
IRST
A
A
A
SCLK Pulldown Current
SCLK = 5.0 V
RST Pulldown Current
RST = 5.0 V
5.0
2.0
25
10
50
30
–
PWM and PWMn Pulldown Current
IPWM
VSOH
A
SO High-State Output Voltage
ISO-high = -1.6 mA
SOPWR
0.4
-
SOPWR
0.2
-
V
SO Low-State Output Voltage
VSOL
V
ISO-
= 1.6 mA
–
–
–
–
0.4
20
low
(14)
Input Capacitance on SCLK, SI, Tri-State SO, RST
Notes
CIN
pF
13. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, PWM, and PWMn.
14. This parameter is guaranteed by design but is not production tested.
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V SOPWR 5.25 V, 9.0 V VPWR 16 V, -40°C TC 125°C unless otherwise
noted. Typical values noted reflect the approximate parameter means at VPWR = 13 V, TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
SR
V/s
RL = 60 (15)
1.0
2.0
10
Output Turn ON Delay Time (16)
T
1.0
1.0
100
100
–
2.0
4.0
–
10
10
s
s
(
)
DLY ON
Output Turn OFF Delay Time (16)
Output ON Short Fault Disable Report Delay (17)
Output OFF Open Fault Delay Time (17)
Output PWM Frequency
T
(
)
DLY OFF
T
450
450
2.0
s
(
DLY SHORT)
T
–
s
(
)
DLY OPEN
T
–
kHz
FREQ
DIGITAL INTERFACE TIMING (23)
Required Low State Duration on VPWR for Reset
VPWR 0.2 V (18)
TRST
s
–
–
10
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SI, CS, SCLK Signal Rise Time (19)
T
100
50
16
20
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
LEAD
T
LAG
TSI(
–
–
)
SU
TSI(
HOLD
–
–
)
TR(SI)
TF(SI)
TSO(
5.0
5.0
–
–
SI, CS, SCLK Signal Fall Time (19)
–
–
Time from Falling Edge of CS to SO Low Impedance (20)
Time from Rising Edge of CS to SO High Impedance (21)
Time from Rising Edge of SCLK to SO Data Valid (22)
–
50
50
80
)
EN
TSO(
DIS
–
–
)
T
–
25
VALID
Notes
15. Output slew rate measured across a 60 resistive load.
16. Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.
17. Duration of fault before fault bit is set. Duration between access times must be greater than 450 s to read faults.
18. This parameter is guaranteed by design but is not production tested.
19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20. Time required for valid output status data to be available on SO pin.
21. Time required for output status data to be terminated at SO pin.
22. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
23. This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.
33999
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAM
TIMING DIAGRAM
CS
0.2 VDD
t
LAG
t
LEAD
0.7 VDD
0.2 VDD
SCLK
SI
tSI(su)
tSI(hold)
0.7 VDD
0.2 VDD
MSB IN
tSO(dis
tSO(en)
t
VALID
)
0.7 VDD
0.2 V
'
Don t
Care
SO
VTri-State
LSB OUT
MSB OUT
DD
Figure 4. SPI Timing Characteristics
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CurVES
ELECTRICAL PERFORMANCE CurVES
14
1.4
1.2
V
@ 13 V
PWR
12
10
8
T
= 125C
= 25C
A
1.0
0.8
0.6
0.4
0.2
T
A
T
= -40C
6
A
4
2
-40 -25
0
25
50
75
100
125
0
5
10
15
20
25
TA, Ambient Temperature (C)
VPWR (V)
Figure 8. RDS(ON) vs. VPWR
Figure 5. IPWR vs. Temperature
1.4
V
@ 13 V
PWR
1.2
1.0
0.8
0.6
0.4
0.2
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (C)
Figure 6. Sleep State IPWR vs. Temperature
1.4
1.2
1.0
0.8
0.6
0.4
V
@ 13 V
PWR
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (C)
Figure 7. RDS(ON) vs. Temperature
33999
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33999 is designed and developed for automotive and
industrial applications. It is a 16-output power switch having
24-bit serial control. The 33999 incorporates SMARTMOS
technology having CMOS logic, bipolar/MOS analog
circuitry, and independent DMOS power output transistors.
Many benefits are realized as a direct result of using this
mixed technology. Figure 2, page 3, illustrates a simplified
internal block diagram of the 33999.
FUNCTIONAL PIN DESCRIPTION
CS pin transitions to a logic low state. All faults on the 33999
are reported to the MCU as logic [1]. Conversely, normal
operating outputs with nonfaulted loads are reported as
logic [0]. On the falling edge of the CS signal, output fault
status information is transferred from the Power Outputs
Status register into the device’s SO Shift register. The first
eight positive transitions of SCLK will provide Any Fault (bit
23), Overvoltage Fault (bit 22), followed by six logic [0]s
(bits 21 to 16). The next 16 successive positive clock
provides fault status for output 15 to output 0. The SI/SO
shifting of data follows a first-in, first-out protocol with both
input and output words transferring the Most Significant Bit
(MSB) first.
CHIP SELECT (CS)
The system MCU selects which 33999 is to be
communicated with through the use of the Chip Select (CS)
pin. When the CS pin is in a logic low state, data can be
transferred from the MCU to the 33999 and vise versa.
Clocked-in data from the MCU is transferred from the 33999
Shift register and latched into the power outputs on the rising
edge of the CS signal. On the falling edge of the CS signal,
output fault status information is transferred from the Power
Outputs Status register into the device’s SO Shift register.
The SO pin output driver is enabled when CS is low, allowing
information to be transferred from the 33999 to the MCU. To
avoid any spurious data, it is essential the high-to-low
transition of the CS signal occur only when SCLK is in a logic
low state.
SO OUTPUT DRIVER POWER SUPPLY (SOPWR)
The SOPWR pin is used to supply power to the 33999 SO
output driver and Power-ON Reset (POR) circuit. To achieve
low standby current on VPWR supply, power must be
removed from the SOPWR pin. The 33999 will be in reset
with all drivers OFF when SOPWR is below 2.5 V. The 33999
does not detect overvoltage on the SOPWR supply pin.
SYSTEM CLOCK (SCLK)
The System Clock (SCLK) pin clocks the Internal Shift
register of the 33999. The Serial Input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal while the Serial Output (SO) pin shifts data information
out of the Shift register on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided, ensuring
validity of data. It is essential the SCLK pin be in a logic low
state whenever the Chip Select (CS) pin makes any
transition. For this reason, it is recommended, though not
necessary, that the SCLK pin is commanded to a low logic
state as long as the device is not accessed (CS in logic high
state). When the CS is in a logic high state, any signal at the
SCLK and SI pins is ignored and the SO is tri-stated (high
impedance).
OUTPUT/INPUT (OUT0–OUT15)
These pins are low-side output switches controlling the
load.
RESET (RST)
The Reset (RST) pin is the active low reset input pin used
to turn OFF all outputs, thereby clearing all internal registers.
BATTERY INPUT (VPWR)
The VPWR pin is used as the input power source for the
33999. The voltage on VPWR is monitored for overvoltage
protection and shutdown. An overvoltage condition (> 50 s)
on the VPWR pin causes the 33999 to shut down all outputs
until the overvoltage condition is removed. Upon return to
normal input voltage, the outputs respond as programmed by
the overvoltage bit in the Global Shutdown/Retry Control
register. The overvoltage threshold on the VPWR pin is
specified as 27.5 V to 35 V with 1.4 V typical hysteresis.
Following an overvoltage shutdown of output drivers, the
Overvoltage Fault and the Any Fault bits in the SO bit stream
will be logic [1].
SERIAL INPUT (SI)
The Serial Input (SI) pin is used to enter one of seven
serial instructions into the 33999. SI SPI bits are latched into
the Input Shift register on each falling edge of SCLK. The
Shift register is full after 24 bits of information are entered.
The 33999 operates on the command word on the rising edge
of CS. To preserve data integrity, exercise care to not
transition SI as the SCLK transitions from high-to-low state
(see Figure 4, page 9).
SERIAL OUTPUT (SO)
The Serial Output (SO) pin transfers fault status data from
the 33999 to the MCU. The SO pin remains tri-state until the
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
PWM CONTROL PIN (PWM)
PULSE WIDTH MODULE (PWMn)
The PWM Control pin is provided to support PWM of any
combination of outputs. Logic for PWM control is provided in
the Logic Commands and Registers section (page 16).
PWM0, PWM1, PWM6, PWM7, PWM8, PWM9, PWM14,
and PWM15 input pins allow direct PWM control of OUT0,
OUT1, OUT6, OUT7, OUT8, OUT9, OUT14, and OUT15,
respectively. Logic for PWM control is provided in the Logic
Commands and Registers section.
33999
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
33999. Data from the MCU is clocked daisy chain through
each device while the Chip Select bit (CS) is commanded low
by the MCU. During each clock cycle, output status from the
daisy-chained 33999s is being transferred back to the MCU
via the Master In Slave Out (MISO) line. On rising edge of CS,
data stored in the input register is then transferred to the
output driver. Daisy chain control of the 33999 requires
24 bits per device.
MCU INTERFACE DESCRIPTION
In operation the 33999 functions as a 16-output serial
switch serving as a microcontroller unit (MCU) bus expander
and buffer with fault management and fault reporting
features. In doing so, the device directly relieves the MCU of
the fault management functions.
The 33999 directly interfaces to an MCU, operating at
system clock serial frequencies up to 6.0 MHz using a Serial
Peripheral Interface (SPI) for control and diagnostic readout.
Figure 9 illustrates the basic SPI configuration between an
MCU and one 33999.
MC68HCXX
Microcontroller
33999
MC68HCXX
Microcontroller
MOSI
SI
33999
Shift Register
MISO
SO
SCLK
SCLK
MOSI
SI
CS
Shift Register
24-Bit Shift Register
To Logic
PWM1
PWM2
Parallel
Ports
MISO
SCLK
PWM
SO
RST
Receive
Buffer
RST
33999
Parallel
Ports
CS
SI
PWM
SO
Figure 9. 33999 SPI Interface with Microcontroller
SCLK
All inputs are compatible with 3.3 V/5.0 V CMOS logic
levels and incorporate positive logic. An input programmed to
a logic low state (< 0.8 V) has the corresponding output OFF.
Conversely, an input programmed to a logic high state
(> 2.2 V) has the output being controlled ON. Diagnostics is
treated in a similar manner—outputs with a fault will feed
back (via SO) to the microcontroller a logic [1], while normal
operating outputs will provide a logic [0].
CS
PWM
RST
Figure 10. 33999 SPI System Daisy Chain
Multiple 33999 devices can be controlled in a parallel input
fashion using the SPI. Figure 11, page 14, illustrates
potentially 32 loads being controlled by two dedicated
parallel MCU ports used for chip select.
The 33999 may be controlled and provide diagnostics
using a daisy chain configuration or in parallel mode.
Figure 10 shows the daisy chain configuration using the
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
MC68HCXX
Microcontroller
33999
MOSI
SI
Shift Register
MISO
SCLK
SO
SCLK
CS
PWM1
PWM2
PWM
Parallel
Ports
RST
SI
33999
SO
SCLK
CS
PWM
RST
Figure 11. Parallel Inputs SI Control
POWER CONSUMPTION
SPI INTEGRITY CHECK
The 33999 is designed with one Sleep mode and one
Operational mode. In Sleep mode (SOPWR 2.0 V), the
current consumed by the VPWR pin is less than 50 A.To
place the 33999 in Sleep mode, turn all outputs OFF and
remove power from the SOPWR pin. During normal
operation, 500 A is drawn from the SOPWR supply and
8.0 mA from the VPWR supply.
Checking the integrity of the SPI communication is
recommended upon initial power-up of the SOPWR pin. After
initial system startup or reset, the MCU writes one 48-bit
pattern to the 33999.
The first 24 bits read by the MCU is the fault status of the
outputs, while the second 24 bits is the first bit pattern sent.
By the MCU receiving the same bit pattern it sent, bus
integrity is confirmed. Please note the second 24 bits the
MCU sends to the 33999 are the command bits to program
registers or activate outputs on the rising edge of CS.
PARALLELING OF OUTPUTS
Using MOSFETs as output switches allows the connection
of any combination of outputs together. The RDS(ON) of
MOSFETs has an inherent positive temperature coefficient
providing balanced current sharing between outputs without
destructive operation. This mode of operation may be
desirable in the event the application requires lower power
dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON), while the Output Current
Limit increases correspondingly. Output OFF Open Load
Detect current may increase based on how the Output OFF
Open Load Detect is programmed. Paralleling outputs from
two or more different IC devices is possible but not
recommended.
OUTPUT OFF OPEN LOAD FAULT
An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
Output OFF Open Load Fault is detected by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
Each 33999 output has an internal 50 A pulldown current
source. The pulldown current is disabled on power-up and
must be enabled for Open Load Detect to function. Once
enabled, the 33999 will only shut down the pulldown current
in Sleep mode or when disabled via SPI.
Care must be taken when paralleling outputs for inductive
loads. The Output Voltage Clamp of the output drivers may
not match. One MOSFET output must be capable of the
inductive energy from the load turn OFF.
During output switching, especially with capacitive loads,
a false Output OFF Open Load Fault may be triggered. To
prevent this false fault from being reported, an internal fault
33999
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
filter of 100 µs to 450 µs is incorporated. The duration for
which a false fault may be reported is a function of the load
impedance, RDS(ON), COUT of the MOSFET, as well as the
supply voltage, VPWR. The rising edge of CS triggers the built-
in fault delay timer. The timer must time out before the fault
comparator is enabled to detect a faulted threshold. Once the
condition causing the Open Load Fault is removed, the
device resumes normal operation. The Open Load Fault,
however, will be latched in the output SO Response register
for the MCU to read.
each output. Each clamp independently limits the drain-to-
source voltage to 50 V. The total energy clamped (EJ) can be
calculated by multiplying the current area under the current
curve (IA) times the clamp voltage (VCL) (see Figure 12).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3 A, indicates the maximum
energy to be 50 mJ at 150C junction temperature per output.
Drain-to-Source Clamp
Drain Voltage
Voltage (VCL = 50 V)
SHORTED LOAD FAULT
Clamp Energy
Drain Current
(ID= 0.3 A)
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or by an output
experiencing a current greater than the current limit.
(EJ = IA x V
)
CL
Three safety circuits progressively in operation during load
short conditions afford system protection:
Drain-to-Source ON
Voltage (VDS(ON)
)
Current
Area (I )
A
1. The device’s output current is monitored in an analog
fashion using a SENSEFET approach and is current
limited.
Time
GND
Figure 12. Output Voltage Clamping
2. With the output in current limit, the drain-to-source
voltage increases. By setting the SFPD bit to 0, the
output shuts down on VDS > 2.7 V typical after 450 s.
REVERSE BATTERY PROTECTION
The 33999 device requires external reverse battery
protection on the VPWR pin.
3. The output thermal limit of the device is sensed and,
when attained, causes only the specific faulted output
to shut down. The device remains OFF until cooled.
The device then operates as programmed by the
shutdown/retry bit. The cycle continues until the fault is
removed or the command bit instructs the output OFF.
All outputs consist of a power MOSFET with an integral
substrate diode. During reverse battery condition, current will
flow through the load via the substrate diode. Under this
circumstance relays may energize and lamps will turn on. If
load reverse battery protection is desired, a diode must be
placed in series with the load.
All three protection schemes set the Fault Status bit (bit 23
in the SO Response register) to logic [1].
OVERTEMPERATURE FAULT
Overtemperature Detect circuits are specifically
incorporated for each individual output. The shutdown
following an overtemperature condition depends on the
control bit set in the Retry/Shutdown Control register. Each
independent output shuts down at 155C to 180C. When an
output shuts down due to an Overtemperature Fault, no other
outputs are affected. The MCU recognizes the fault by a
logic [1] in the Fault Status bit (bit 23 in the SO Response
register). After the 33999 has cooled below the switch point
temperature and 10C hysteresis, the output functions as
defined by the retry/shutdown bit 17 in the Global Shutdown/
Retry Control register.
UNDERVOLTAGE SHUTDOWN
An undervoltage SOPWR condition results in the global
shutdown of all outputs and reset of all control registers. The
undervoltage threshold is between 2.0 V and 3.0 V.
An undervoltage condition at the VPWR pin results in an
output shutdown and reset. The undervoltage threshold is
between 3.2 V and 3.5 V. When VPWR is between 5.0 V and
3.5 V, the output may operate per the command word and the
status is reported on SO pin, though this is not guaranteed.
OUTPUT VOLTAGE CLAMP
Each output of the 33999 incorporates an internal voltage
clamp to provide fast turn-OFF and transient protection of
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
CTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
The 33999 message set consists of seven messages as
INTRODUCTION
shown in Table 6. Bits 23 through 18 determine the specific
command and bits 15 through 0 determine how a specific
output will operate. The 33999 operates on the command
word on the rising edge of CS.
The 33999 provides flexible control of 16 low-side driver
outputs. The device allows PWM and ON/OFF control
through the use of several input command words. This
section describes the logic operation and command registers
of the 33999.
Note Upon Power-ON Reset all bits are defined as shown
in Table 6.
Table 6. SPI Control Commands
MSB
Bits
LSB
0
Commands
23 22 21 20 19 18
17
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
ON/OFF Control Register
0 = off, 1 = on
0
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Open Load Current
Enable
0 = disable, 1 = enable
0
0
0
0
0
1
X
X
0
0
0
0
0
0
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
Global Shutdown/Retry
Control
0 = shutdown, 1 = retry
0
0
0
0
0
0
0
0
1
1
0
1
Thermal
Bit 0
Over-
voltage
0
X
1
X
1
X
1
X
1
X
1
X
1
SFPD Control
X
X
1 = therm only, 0 = VDS
PWM Enable
0 = SPI only, 1 = PWM
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AND/OR Control
0 = PWM pin AND with
SPI
1 = PWM pin OR with SPI
Reset
0
0
0
0
1
0
1
0
0
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SO Response
0 = No Fault, 1 = Fault
Any Over-
Fault voltage
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
when VPWR returns to normal level. Setting the Overvoltage
bit to logic [1] will command outputs to resume their previous
state when VPWR returns to normal level. Bit 17 is the global
thermal bit. When bit 17 is set to logic [0], all outputs will shut
down when thermal limit is reached and remain off even after
cooled. With bit 17 set to logic [1], all outputs will shut down
when thermal limit is reached and will retry when cooled.
ON/OFF CONTROL REGISTER
To program the 16 outputs of the 33999 ON or OFF, a 24-
bit serial stream of data is entered into the SI pin. The first 8
bits of the control word are used to identify the on/off
command and the remaining 16 bits are used to turn ON or
OFF the specific output driver.
OPEN LOAD CURRENT ENABLE CONTROL
REGISTER
SHORT FAULT PROTECT DISABLE (SFPD)
CONTROL REGISTER
The Open Load Enable Control register is provided to
enable or disable the 50 A open load detect pulldown
current. This feature allows the device to be used in LED
applications. Power-ON Reset (POR) or the RST pin or the
RESET command disables the 50 A pulldown current. No
open load fault will be reported with the pulldown current
disabled. For open load to be active, the user must program
the Open Load Current Enable Control register with logic [1].
All outputs contain a current limit and thermal shutdown
with programmable retry. The SFPD control bits are used for
fast shutdown of the output when an overcurrent condition is
detected but thermal shutdown has not been achieved.
The SFPD Control register allows selection of specific
outputs for incandescent lamp loads and specific outputs for
inductive loads. By programming the specific SFPD bit as
logic [1], output will rely on Overtemperature Shutdown only.
Programming the specific SFPD bit as logic [0] will shut down
the output after 100 s to 450 s during turn on into short
circuit. The decision for shutdown is based on output drain-
to-source voltage (VDS) > 2.7 V. This feature is designed to
provide protection to loads that experience more than
expected currents and require fast shutdown. The 33999 is
designed to operate in both modes with full device protection.
GLOBAL SHUTDOWN/RETRY CONTROL
REGISTER
The Global Shutdown/Retry Control register allows the
user to select the global fault strategy for the outputs. The
Overvoltage control bit (bit 16) sets the operation of the
outputs when returning from overvoltage. Setting the
Overvoltage bit to logic [0] will force all outputs to remain OFF
33999
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PWM ENABLE REGISTER
SERIAL OUTPUT (SO) RESPONSE REGISTER
The PWM Enable register determines the outputs that are
PWM controlled. The first 8 bits of the 24 bit SPI message
word are used to identify the PWM enable command, and the
remaining 16 bits are used to enable or disable the PWM of
the output drivers.
Fault reporting is accomplished through the SPI interface.
All logic [1]s received by the MCU via the SO pin indicate
fault. All logic [0]s received by the MCU via the SO pin
indicate no fault. All fault bits are cleared on the positive edge
of CS. SO bits 15 to 0 represent the fault status of outputs 15
to 0. SO bits 21 to 16 will always return logic [0]. Bit 22
provides overvoltage condition status, and bit 23 is set when
any fault is present in the IC. The timing between two write
words must be greater than 450 s to allow adequate time to
sense and report the proper fault status.
A logic [1] in the PWM Enable register allows the user to
OR/AND the PWM input with SPI Control bit and disables the
specific parallel control input (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15).
A logic [0] in the PWM Enable register will disable the
PWM to a specific output and allow the user to use the
parallel PWM control inputs (PWM0, PWM1, PWM6, PWM7,
PWM8, PWM9, PWM14, and PWM15) and the SPI ON/OFF
Control bits. Power-ON Reset (POR) or the RST pin or the
RESET command will set the PWM enable register to
logic[0].
RESET COMMAND
The RESET command turns all outputs OFF and sets all
internal registers to their Power-ON Reset state (refer to
Table 6).
FAULT OPERATION
AND/OR Control Register
On each SPI communication, a 24-bit command word is
sent to the 33999 and a 24-bit fault word is received from the
33999.
The AND/OR Control register describes the condition by
which the PWM pin controls the output driver. A logic [0] in
the AND/OR Control register will AND the PWM pin with the
control bit in the SPI Control register. Likewise, a logic [1] in
the AND/OR Control register will OR the PWM pin with the
control bit in the ON/OFF Control register (see Figure 13).
The Most Significant Bit (MSB) is sent and received first.
Command Register Definition:
0 = Output Command Off
1 = Output Command On
SO Definition:
0 = No fault
1 = Fault
On/Off Control Bit
PWM Enable Bit
On/Off Control Bit
To Gate
Control
PWM IN
AND/OR Control Bit
On/Off control Bit
PWM IN
Figure 13. PWM Control Logic Diagram
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
CTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 7. Fault Operation
SERIAL OUTPUT (SO) PIN REPORTS
Overtemperature
Fault reported by Serial Output (SO) pin.
Overcurrent
SO pin reports short-to-battery/supply or overcurrent condition.
Not reported.
Output ON Open Load Fault
Output OFF Open Load Fault
DEVICE SHUTDOWNS
Overvoltage
SO pin reports output “OFF” open load condition.
Total device shutdown at VPWR = 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon
recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/
Retry Control register.
Overtemperature
Overcurrent
Only the output experiencing an overtemperature shuts down. Output may auto-retry or remain OFF
according to the control bits in the Global Shutdown/Retry Control register.
Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is
reached, device will enter overtemperature shutdown. Output will operate as programmed in the Global
Shutdown/Retry Control register. Fault flag in SO Response word will be set.
33999
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EK SUFFIX (PB-FREE)
54-PIN
98ASA10506D
REVISION C
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
KAGING
PACKAGE DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN
98ASA10506D
REVISION C
33999
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
Implemented Revision History page
•
•
2.0
2/2005
Converted to Freescale format
•
•
Updated status to “Advanced”
Changed orderable Part Number from PC33999EK/R2 to MC33999EK/R2
3.0
4/2006
•
Minor labeling corrections to 33999 Simplified Internal Block Diagram on page 3 - changed pins
SCLK to CS and CSB to SCLK.
4.0
4/2007
•
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 5. Added note with instructions from www.freescale.com.
Added MCZ33999EK/R2 to the Ordering Information.
•
•
•
5.0
6.0
1/2011
2/2014
Removed Part Number MC33999EK/R2 from the Ordering Information Table on page 1.
No technical changes. Revised back page. Updated document properties. Added SMARTMOS
sentence to last paragraph.
33999
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
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© 2014 Freescale Semiconductor, Inc.
Document Number: MC33999
Rev. 6.0
2/2014
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