MC33SA0528ACR2 [NXP]
SPECIALTY INTERFACE CIRCUIT, PQFP32;
| 型号： | MC33SA0528ACR2 |
| 厂家： | 
NXP |
| 描述： | SPECIALTY INTERFACE CIRCUIT, PQFP32 接口集成电路 |
| 文件： | 总40页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33SA0528
Rev. 3.0, 7/2016
NXP Semiconductors
Data sheet: Advance Information
Dual DSI master transceiver
33SA0528
The 33SA0528 is a third generation SMARTMOS standalone, dual-channel
distributed system interface (DSI) master device.
Each of the two independent channels contain a differential driver and a dual
adder receiver. The embedded DSI protocol engine converts the DSI data
between the physical interface and the two redundant SPI interfaces. The MCU
can control and configure the 33SA0528 and extract all of the slaves
transceivers data from it via the dual SPI.
Automotive restraint system
To ensure the communication reliability, the 33SA0528 uses an on-chip band
gap reference regulator to monitor all of the supply voltages, and uses an on-
chip oscillator to monitor the PLL clock for the external clock error detection.
Features
AC SUFFIX (PB-FREE)
98ASH70029A
• Two independent DSI master channels
• Supports command and response mode for slave configuration
• Supports periodic data collection mode (PDCM) for periodic slave data
transfers
32-PIN LQFP
Applications
• Automotive airbag and safety
• Industrial systems
• Sense and trigger applications
• Supports discovery mode for slave physical address self-programming
• 10 MHz 32-bit dual SPI: main SPI for device configuration and DSI operation,
and redundant SPI for safety purposes
• Point-to-point, parallel, daisy chain bus topologies
• Various diagnostic features
VCC5 VDSI
MCU
33SA0528
VDSI
V2P5A
VCC5
V2P5D
GNDA
GNDD
DSI Slaves Interfaces
GPIO
RSTB
SPI0_SCK
SPI0_CS
SPI0_MOSI
SPI0_MISO
SCK0
DH0
DL0
CS0B_D
MOSI0
MISO0
GNDP_DSI0
GNDP_DSI1
SPI1_SCK
SPI1_CS
SCK1
CS1B
SPI1_MOSI
SPI1_MISO
MOSI1
MISO1
DH1
DL1
CLKOUT
CLK_IN
CLK_OUT
CLK
GNDSUB
Figure 1. 33SA0528 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General IC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 DSI protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Clock and reset module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4
5
6
7
8
9
33SA0528
NXP Semiconductors
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1
Orderable parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable part variations
Temperature (T )
Part number
MC33SA0528AC
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
Notes
Package
A
(1)
-40 °C to 125 °C
32-PIN LQFP
33SA0528
3
NXP Semiconductors
2
Internal block diagram
Voltage Supplies Monitors
POR
VDSI
VCC5
Ch0 Driver/Receiver
Bus Driver
Bus Receiver
RSTB
Current Limiter
DH0
DL0
CLK_IN
Adder
CLK Monitor
and PLL
TS
CLK_OUT
Receiver Sum1
Receiver Sum2
CS0B_D
SPI0_D
Registers
and
SCLK0
MOSI0
MISO0
State Machine
DH1
DL1
CS1B
SCLK1
MOSI1
MISO1
GNDA
GNDD
V2P5A
V2P5D
Ch1 Driver/Receiver
SPI1
Registers
and
State Machine
Bandgap References
Internal
Voltages
GNDP_DSI
Figure 2. 33SA0528 simplified internal block diagram
33SA0528
NXP Semiconductors
4
3
Pin connections
3.1
Pinout diagram
32 21 30 29 28 27 26 25
24
MISO0
CLKOUT
MISO1
GNDSUB
CLKIN
NC
VDSI
DH0
1
2
3
4
5
6
7
8
23
22
21
20
19
18
17
GNDP_DSI0
DL0
GNDSUB
DH1
NC
GNDP_DSI1
DL1
NC
9
10 11 12 13 14 15 16
Figure 3. 33SA0528 32-pin LQFP pinout diagram
3.2
Pin definitions
A functional description of each pin can be found in the functional pin description section beginning on page 9.
Table 2. 33SA0528 pin definitions
Pin number
Pin name
Pin function
Definition
1
2
3
4
5
6
7
8
9
VDSI
DH0
Power
This supply input is used to provide the positive level output of buses
Output driver Bus 0 high-side
Ground Bus power return
Output driver Bus 0 low-side
GND_DSI0
DL0
GNDSUB
DH1
Ground
This pin must be tied to ground in the application.
Output driver Bus 1 high-side
GND_DSI1
DL1
Ground
Bus power return
Output driver Bus 1 low-side
RSTB
Reset
Input
A low level on this pin returns all registers to a known initial state.
Clocks data in from and out to DSI_SPI0. MISO0 data changes on the negative transition of SCLK0.
MOSI0 is sampled on the positive edge of SCLK0
10
11
12
SCK0
CS0B_D
SCK1
When this signal is high, SPI signals on DSI_SPI0 are ignored. Asserting this pin low starts a DSI_SPI0
transaction. The DSI_SPI0 transaction is signaled as completed when this signal returns high
Input
Input
Clocks data in from and out to DSI_SPI1. MISO1 data changes on the negative transition of SCLK1.
MOSI1 is sampled on the positive edge of SCLK1
33SA0528
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NXP Semiconductors
Table 2. 33SA0528 pin definitions(continued)
Pin number
Pin name
Pin function
Definition
When this signal is high, SPI signals on DSI_SPI1 are ignored. Asserting this pin low starts a DSI_SPI1
transaction. The DSI_SPI1 transaction is signaled as completed when this signal returns high
13
CS1B
Input
14
15
16
17
18
19
20
21
N.C
MOSI0
MOSI1
N.C
—
Input
Input
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
SPI data into DSI_SPI0. This data input is sampled on the positive edge of SCLK0
SPI data into DSI_SPI1. This data input is sampled on the positive edge of SCLK1
This pin is not internally connected and must be left unconnected or tied to ground in the application
This pin is not internally connected and must be left unconnected or tied to ground in the application
This pin is not internally connected and must be left unconnected or tied to ground in the application
4.0 MHz clock input
N.C
—
N.C
—
CLK_IN
GNDSUB
Input
Ground
This pin must be tied to ground in the application
DSI_SPI1 data sent to the MCU by this device. This data output changes on the negative edge of
SCLK1. When CS1B_D is high, this pin is high
22
23
24
MISO1
CLK_OUT
MISO0
Output
Output
Output
Output buffered clock signal that is input from CLK_IN
DSI_SPI0 data sent to the MCU by this device. This data output changes on the negative edge of
SCLK0. When CS0B_D is high, this pin is set at high impedance
25
26
27
28
29
30
GNDD
VCC5
N.C
Ground
Power
—
Ground for the digital circuits. Ground for IDDQ. This pin should be tied to MCU ground
Regulated 5.0 V input
This pin is not internally connected and must be left unconnected or tied to ground in the application
This pin is not internally connected and must be left unconnected or tied to ground in the application
0.1 μF capacitor should be connected between this pin and ground
N.C
—
V2P5D
V2P5A
Output
Output
0.1 μF capacitor should be connected between this pin and ground
Ground for the analog circuits. This pin is not connected internally to the other grounds on the chip. It
should be connected to a quiet ground on the board
31
32
GNDA
N.C
Ground
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
33SA0528
NXP Semiconductors
6
4
General product characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Electrical ratings
DSI bus voltage supply
Steady-state
VDSI
-0.3
10
V
•
VCC5
V2P5A
V2P5D
VLOGIC
ILOGIC
VBUS
VCC logic supply voltage
Regulated output voltage
Regulated output voltage
-0.3
-0.3
-0.3
-0.3
—
7.0
3.0
3.0
V
V
V
Voltage on logic input/output pins
Current on logic input/output pins
Voltage on DSI bus pins
Current on DSI bus pins
ESD voltage
V
+ 3.0
V
CC5
20
20
mA
V
-0.3
—
IBUS
200
mA
•
•
•
Human body model (HBM)
Machine model (MM)
Charge device model (CDM)
—
—
—
2000
150
500
(2)
VESD
V
Notes
2. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the machine model (MM)
(CZAP = 200 pF, RZAP = 0 Ω), and the charge device model.
4.2
Thermal characteristics
Table 4. Thermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Operating temperature
TA
TJ
•
•
Ambient
Junction
-40
-40
105
150
°C
TSTG
TSD
Storage temperature
Thermal shutdown (bus driver)
-55
150
195
°C
°C
155
33SA0528
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NXP Semiconductors
4.3
Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 5. Operating conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Min.
Max.
Unit
Notes
VDSI
Full characteristics are guaranteed
9.0
9.6
V
Some characteristics are out of specification, but the 33SA0528 can
communicate with the bus slaves
VDSI
8.8
9.0
V
Some characteristics are out of specification, but the VDSI monitor is active, so
the RNE bit is never set
VDSI
8.2
4.8
8.8
V
V
VCC5
Functional operating VCC5 voltage
5.25
4.4
Supply currents
This section describes the current consumption characteristics of the device, as well as the conditions for the measurements.
Table 6. Supply currents
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device. Typical values noted reflect the approximate parameter mean at TA = 25 °C.
Symbol
Ratings
Min.
Typ.
Max.
Unit
Notes
Current on DSI bus
8.0
18
96
11
24
13
30
•
•
•
9.6 V (disabled)
9.6 V (enabled 1.0 mA/channel)
9.6 V (enabled 40 mA/channel)
(3)
IVDSI
mA
mA
108
114
IVCC
Current on VCC5 supply
—
—
2.0
Notes
3. IOUT is the total current for all sensors connected to two DSI interfaces. For example: If 40 mA is flowing out (DHx to DLx) on each DSI channel,
then IOUT = 2 x 40 mA = 80 mA. The max. internal current flowing from VDSI to GND is ’28 mA + (80 mA/14) = 34 mA’. The max. total current is
flowing from VDSI (includes sensor current) is ’34 mA + 80 mA = 114 mA’. If the DSI channel-0 is enabled and 40 mA is flowing out (DHx to DLx),
the other DSI channel (ch1) is the disabled case. The max. internal current flowing from VDSI to GND is ’19 mA + (40 mA/14) = 22 mA’. The Max.
total current flowing from VDSI (include sensor current) is ’22 mA + 40 mA = 62 mA’.
33SA0528
NXP Semiconductors
8
5
General IC functional description
5.1
Block diagram
Power Supply
Monitoring
Clock Monitoring
and Reset
Main SPI
Redundant SPI
DSI Protocol Engine
Figure 4. 33SA0528 functional block diagram
5.2
Features
• Main SPI at 10 MHz and 32-bit frame size provides access to all main registers
• Redundant SPI with the same format provides access to redundant registers with slaves’ data, for safety purposes
• DSI protocol engine provides two independent channels to communicate and decode up to eight sensors
• Power supplies monitor detects and informs undervoltages on all four power pins (VDSI, VCC5, V2P5A, V2P5D)
• Internal PLL block generates 10 MHz stable frequency from 4.0 Mhz input clock
• Internal clock generator (no resonator) provides internal 4.0 MHz reference for clock frequency watchdog block
• Clock monitor sets proper flags if any abnormality is detected in clock or PLL frequencies
5.3
Functional description
The 33SA0528 is a DSI master device behaving as an interface between the MCU and the DSI slaves connected to the system bus. It
supports up to four slaves connected to each of the two available DSI channels, allowing for a total of eight slaves. The MCU can access
the registers in the 33SA0528 via two independent SPIs, the first one being for configuration purposes and to interact with the DSI slaves.
The second one provides full redundancy of slaves’ responses, which is designed for safety applications. The 33SA0528 can also act as
a DSI Companion Chip when working together with a DSI SBC, expanding this last chip’s capacity regarding the maximum number of DSI
slaves it can decode.
5.4
Communication
5.4.1 SPI
Both SPI channels share the same speed and format, so only one MCU configuration scheme is needed to communicate with the
33SA0528. The maximum frequency of this interface is clocked at 10 MHz and provided by the internal PLL, generated from the 4.0 MHz
clock input. Each command follows a 32-bit format, with the 5th byte being optional. The SPI is in-command full-duplex, which means the
33SA0528 responds during the same SPI frame in which it demands to read a register, meaning the device can write or read any register
in just one SPI command.
5.4.2 DSI
The 33SA0528 provides an interface for a DSI Differential bus, having two independent channels. Each channel can drive and decode up
to four slaves connected in either point-to-point, parallel, or resistor-based daisy-chained bus. For each channel, the DSI Receiver block
provides a doubled redundancy when composing the differential (high/send and low/return) values read from the bus, which makes this
device is ideal for safety applications. For more information on the DSI protocol, refer to its consortium web site: http://
www.dsiconsortium.org.
33SA0528
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NXP Semiconductors
6
Functional block description
6.1
SPI
6.1.1 Block diagram
SPI0
SPI1
SCK0
SCK1
CS0B_D
MOSI0
MISO0
CS1B
MOSI1
MISO1
To MCU
SPI0
To MCU
SPI1
Figure 5. SPI modules pins and block diagram
6.1.2 Timings and configuration
The timings and commands format is the same for both SPI modules.
tNEG
VIH
VIL
CSB
VIL
tLAG
tCYC
tLEAD
tF
tR
tHI
tLO
VIH
VIL
SCLK
MOSI
tSU
tH
VIH
VIH
X
MSB
MSB
LSB
tV
tDIS
VOH
VOL
X
LSB
MISO
Figure 6. SPI modules timings
33SA0528
NXP Semiconductors
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Table 7. SPI modules timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
tCYC
tHI
SPI clock cycle time
99
40
40
50
50
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
SPI clock high time
SPI clock low time
tLO
tLEAD
tLAG
SPI chip select lead time
SPI chip select lag time
Data setup time
tSU
10
10
—
—
—
—
—
—
—
—
—
—
25
50
10
ns
ns
ns
ns
ns
•
MOSI valid after SCK rising edge
Data hold time
tH
•
MOSI valid after SCK rising edge
Data valid time
tV
•
SCK falling edge to MISO valid, C = 50 pF
Output disable time
tDIS
•
CSB rise to MISO high-impedance
Rise time (30% VCC to 70% VCC
)
tR
•
SCK, MOSI
Fall time (70% VCC to 30% VCC
SCK, MOSI
Chip select negate timer (read/write)
)
tF
—
—
—
10
—
ns
ns
•
tNEG
600
6.1.3 Frame format
The SPI module transactions start with a command and address byte and can be followed by three or four bytes of data. The start of a
SPI transaction is signaled by the CSB signal being asserted low. The first bit sent (bit 7) of the first byte signals a read (bit = ‘0’) or write
(bit = ‘1’) operation. The last seven bits (bit 6 to 0) of the first byte indicate the address of the desired register. Both 4-byte access and 5-
byte access are valid for all register address. During a SPI transaction the 33SA0528 checks for SPI framing errors. A framing error is
defined as any number of clocks received which is neither 32 nor 40. If this occurs, all bits sent by the SPI master are discarded and no
registers are updated.
CSB
SCK
1st byte
REG ADDR
7 bits
2nd byte
3rd byte
4th byte
MOSI
MISO
DATA
DATA
DATA
Write/Read bit
N/A
DATA
DATA
DATA
Figure 7. SPI module frames format - 4 byte access
33SA0528
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NXP Semiconductors
CSB
SCK
1st byte
REG ADDR
7 bits
2nd byte
3rd byte
4th byte
5th byte
MOSI
MISO
DATA
DATA
DATA
DATA
Write/Read bit
N/A
DATA
DATA
DATA
DATA
5th byte is only available for SPI0 registers 0x00 and 0x10
Figure 8. SPI modules frames format - 5 bytes access
6.1.4 Register maps
Table 8. SPI0 register map
Address
Name
Type
2nd byte
3rd byte
4th byte
5th byte (optional)
0x00
0x01
0x02
0x04
0x06
0x08
0x0A
0x0B
0x0C
0x0E
0x10
0x11
0x12
0x14
0x16
0x18
0x1A
0x1B
0x1C
0x1E
0x40
0x41
0x42
CRM Tx/Rx Data Buffer D0
CRM Tx/Rx Data Buffer D0
PDCM Data Buffer D0R0
PDCM Data Buffer D0R1
PDCM Data Buffer D0R2
PDCM Data Buffer D0R3
PDCM Control D0
R/W
R
D0DATA2
D0DATA1
D0DATA1
D0DATA0
D0R0DATA1
D0R1DATA1
D0R2DATA1
D0R3DATA1
D0PDCM_DLY
D0DPC
D0DATA0
D0RES_STAT
D0R0DATA0
D0R1DATA0
D0R2DATA0
D0R3DATA0
N/A
D0RES_STAT
—
R
D0R0DATA2
D0R1DATA2
D0R2DATA2
D0R3DATA2
D0PDCM_CTRL
D0CTRL
—
R
—
R
—
R
—
R/W
R/W
R/W
R/W
R/W
R
—
Channel Control D0
PDCM Configuration D0
Channel Clear D0
D0STAT
—
D0CHIP_TIME
D0CLR
D0SID_R0R1
N/A
D0SID_R2R3
N/A
—
—
CRM Tx/Rx Data Buffer D1
CRM Tx/Rx Data Buffer D1
PDCM Data Buffer D1R0
PDCM Data Buffer D1R1
PDCM Data Buffer D1R2
PDCM Data Buffer D1R3
PDCM Control D1
D1DATA2
D1DATA1
D1DATA0
D1R0DATA1
D1R1DATA1
D1R2DATA1
D1R3DATA1
D1PDCM_DLY
D1DPC
D1DATA0
D1RES_STAT
D1R0DATA0
D1R1DATA0
D1R2DATA0
D1R3DATA0
N/A
D1RES_STAT
D1DATA1
—
—
—
—
—
—
—
—
—
—
—
—
R
D1R0DATA2
D1R1DATA2
D1R2DATA2
D1R3DATA2
D1PDCM_CTRL
D1CTRL
R
R
R
R/W
R/W
R/W
R/W
R
Channel Control D1
PDCM Configuration D1
Channel Clear D1
D1STAT
D1CHIP_TIME
D1CLR
D1SID_R0R1
N/A
D1SID_R2R3
N/A
NCKPTN
0xAA
0xAA
0xAA
CHKPTN
R
0x55
0x55
0x55
MASKID
R
MASKID
—
—
Notes
4. Dn registers refer to the DSI channel n, so D0 corresponds to channel 0 and D1 corresponds to channel 1.
5. Rm registers refer to the DSI slave addressed at m, so R0 corresponds to slave at address 0 and so on.
6. The registers that correspond to different DSI channels and addresses have the same format and description.
33SA0528
NXP Semiconductors
12
Table 9. SPI1 register map
Address
Name
Type
2nd byte
3rd byte
4th byte
5th byte (optional)
0x02
0x04
0x06
0x08
0x12
0x14
0x16
0x18
0x40
0x41
Notes
PDCM Data Buffer D0R0
PDCM Data Buffer D0R1
PDCM Data Buffer D0R2
PDCM Data Buffer D0R3
PDCM Data Buffer D1R0
PDCM Data Buffer D1R1
PDCM Data Buffer D1R2
PDCM Data Buffer D1R3
NCKPTN
R
R
R
R
R
R
R
R
R
R
D0R0DATA2
D0R1DATA2
D0R2DATA2
D0R3DATA2
D1R0DATA2
D1R1DATA2
D1R2DATA2
D1R3DATA2
0xAA
D0R0DATA1
D0R1DATA1
D0R2DATA1
D0R3DATA1
D1R0DATA1
D1R1DATA1
D1R2DATA1
D1R3DATA1
0xAA
D0R0DATA0
D0R1DATA0
D0R2DATA0
D0R3DATA0
D1R0DATA0
D1R1DATA0
D1R2DATA0
D1R3DATA0
0xAA
-
-
-
-
-
-
-
-
-
-
CHKPTN
0x55
0x55
0x55
•
These registers have the same format and description as their SPI0 counterparts, as they are just for redundancy purposes.
6.1.5 Registers description
6.1.5.1
CRM Tx/Rx data buffer Dn
Table 10. 2nd byte - DnDATA2
Bit
7
6
5
4
3
2
1
0
R
W
DnDATA[23]
0
DnDATA[22]
0
DnDATA[21]
0
DnDATA[20]
0
DnDATA[19]
0
DnDATA[18]
0
DnDATA[17]
0
DnDATA[16]
0
Reset
Table 11. 3rd byte - DnDATA1
Bit
7
6
5
4
3
2
1
0
R
W
DnDATA[15]
0
DnDATA[14]
0
DnDATA[13]
0
DnDATA[12]
0
DnDATA[11]
0
DnDATA[10]
0
DnDATA[9]
0
DnDATA[8]
0
Reset
Table 12. 4th byte - DnDATA
Bit
7
6
5
4
3
2
1
0
R
W
DnDATA[7]
0
DnDATA[6]
0
DnDATA[5]
0
DnDATA[4]
0
DnDATA[3]
0
DnDATA[2]
0
DnDATA[1]
0
DnDATA[0]
0
Reset
Table 13. 5th byte - DnRES_STAT
Bit
7
6
5
4
3
2
1
0
R
ER
-
-
UV
TE
RNE
0
1
33SA0528
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NXP Semiconductors
Table 13. 5th byte - DnRES_STAT
Bit
7
6
5
4
3
2
1
0
W
Reset
0
0
0
0
1
0
0
1
Table 14. CRM Tx/Rx data buffer Dn fields description
Field
Description
CRM data to transmit or CRM data received from slaves
DnDATA[23:0]
ER
If the DSI channel EN bit is set, and the 33SA0528 is not in PDCM, data is transmitted after being written to the register. Also,
slaves’ CRM data is written back to the buffer as soon as it is received through the bus.
Error bit
This bit indicates, for received data, there is either a CRC error, an undefined symbol error, or data mismatch between the dual
DSI receivers.
Undervoltage
UV
TE
This bit indicates VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
Transmit empty
This bit indicates there is no data in the transmit buffer.
Receiver not empty
RNE
This bit indicates there is data available that has been received from the slaves.
6.1.5.2
PDCM data buffer DnRm
Table 15. 2nd byte - DnRmDATA2
Bit
7
6
5
4
3
2
1
0
R
W
ER
-
RNE
UV
DnRmData[19] DnRmData[18] DnRmData[17] DnRmData[16]
Reset
0
0
0
0
0
0
0
0
Table 16. 3rd byte - DnRmDATA1
Bit
7
6
5
4
3
2
1
0
R
W
DnRmData[15] DnRmData[14] DnRmData[13] DnRmData[12] DnRmData[11] DnRmData[10] DnRmData[9]
DnRmData[8]
Reset
0
0
0
0
0
0
0
0
Table 17. 4th byte - DnRmDATA0
Bit
7
6
5
4
3
2
1
0
R
W
DnRmData[7]
DnRmData[6]
DnRmData[5]
DnRmData[4]
DnRmData[3]
DnRmData[2]
DnRmData[1]
DnRmData[0]
Reset
0
0
0
0
0
0
0
0
33SA0528
NXP Semiconductors
14
Table 18. PDCM data buffer DnRm fields description
Field
Description
PDCM data received from slaves
DnRmDATA[19:0]
DnRmDATA[19:16] represent the source ID field of the slave, and it is used as seed for CRC calculation.
Error bit
ER
This bit indicates, for received data, that there is either a CRC error, an undefined symbol error, or data mismatch between the
dual DSI receivers.
Undervoltage
UV
This bit indicates VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
Receiver not empty
RNE
This bit indicates there is data available that has been received from the slaves.
6.1.5.3
PDCM control Dn
Table 19. 2nd byte - DnPDCM_CTRL
Bit
7
6
5
4
3
2
1
0
R
W
DnBRC
0
-
-
-
-
-
DnAUTO
0
DnPDCM_EN
0
Reset
0
0
0
0
0
Table 20. 3rd byte - DnPDCM_DLY
Bit
7
6
5
4
3
2
1
0
R
W
DELAY[7]
0
DELAY[6]
0
DELAY[5]
0
DELAY[4]
0
DELAY[3]
0
DELAY[2]
0
DELAY[1]
0
DELAY[0]
0
Reset
Table 21. PDCM control Dn fields description
Field
Description
Broadcast read command
DnBRC
Each time this bit is set, a manual BRC is transmitted through the DSI bus. Only valid when DnPDCM_EN is 1 and DnAUTO is 0.
Automatic BRC
DnAUTO
DnPDCM_EN
DELAY[7:0]
When this bit is set, a BRC is transmitted automatically through the DSI bus every 500 µs. Write access to this bit is ignored when
DnPDCM_EN is 0.
Periodic data collection mode enable
Once this bit is set, the 33SA0528 enters PDCM, preventing any CRM communication or any configuration change. This bit can
be cleared by clearing the channel, by writing to the channel clear Dn register.
Broadcast read command delay
This bits set the delay to be applied to both manual and automatic BRCs, from BRC bit set to its transmission through the DSI bus.
It is calculated as
, with a range of 0 ‘~ 127.5 µs and a 0.5 µs step at 10 MHz.
Delay time = DELAY[7:0] × 5clockcounts
33SA0528
15
NXP Semiconductors
6.1.5.4
Channel control Dn
Table 22. 2nd byte - DnCTRL
Bit
7
6
5
4
3
2
1
0
R
W
0
0
0
0
UVDSI_ON
0
EN
0
BCK[1]
0
BCK[0]
0
Reset
0
0
0
0
Table 23. 3rd byte - DnDPC
Bit
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
DPC[2]
0
DPC[1]
0
DPC[0]
0
Reset
0
0
0
0
0
Table 24. 4th byte - DnSTAT
Bit
7
6
5
4
3
2
1
0
R
W
CFM3
w0c
0
CFM2
w0c
0
GNDA_OP
GNDD_OP
OCS
w0c
0
TS
w0c
0
0
UV
w0c
0
w0c
0
w0c
0
Reset
0
Table 25. Channel control Dn fields description
Field
Description
VDSI undervoltage monitor test function
This bit forces an undervoltage detection on the UVDSI monitor, for test purposes, by forcing its input to ground.
0: Normal operation. UVDSI module monitors the voltage in VDSI pin.
UVDSI_ON
1: Test operation. UVDSI is forced to ground, so the UV bit in status registers should be set.
DSI channel enable
EN
0: Disable the DSI channel, if conditions are met.
1: Enable the DSI channel, if conditions are met.
Buffer check mode
If both these bits are set simultaneously (in the same SPI transaction), the 33SA0528 enters BCM. Refer to the DSI protocol
engine module. Note that the BCK[1:0] bits have higher priority than EN and DPC[2:0], meaning if are three fields are written at
the same time, only BCK[1:0] is considered.
BCK[1:0]
DPC[2:0]
Discovery pulses count
If conditions are met, setting these bits transmits the set number of discovery pulses through the DSI bus. Refer to DSI protocol
engine on page 20 for required conditions.
Clock failure monitor flags
CFM3=0 and CFM2=0: Normal case. Each bit can be cleared by writing a 0 to them.
CFM3=1: The internal PLL in charge of generating the internal 10 MHz frequency is unlocked.
CFM2=1: The clock watchdog indicates CLKIN is out of its 4.0 MHz accepted range.
CFM3 and CFM2
GNDA open pin
GNDA_OP
GNDD_OP
OCS
0: Normal case. The bit can be cleared by writing a 0 to it.
1: GNDA pin is open.
GNDD open pin
0: Normal case. The bit can be cleared by writing a 0 to it.
1: GNDD pin is open.
Overcurrent shutdown
0: Normal case. The bit can be cleared by writing a 0 to it.
1: The DSI bus current limiter has worked for a certain amount of time. Refer to Power supply monitor on page 30.
33SA0528
NXP Semiconductors
16
Table 25. Channel control Dn fields description (continued)
Field
Description
Thermal shutdown
TS
UV
0: Normal case. The bit can be cleared by writing a 0 to it.
1: The DSI bus thermal limit has been reached. Refer to Power supply monitor on page 30.
Undervoltage
0: Normal case. The bit can be cleared by writing a 0 to it.
1: VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
6.1.5.5
PDCM configuration Dn
Table 26. 2nd byte - DnCHIP_TIME
Bit
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
CHIPTIME[1]
0
CHIPTIME[0]
0
Reset
0
0
0
0
0
0
Table 27. 3rd byte - DnSID_R0R1
Bit
7
6
5
4
3
2
1
0
R
W
SID_R0[3]
0
SID_R0[2]
0
SID_R0[1]
0
SID_R0[0]
0
SID_R1[3]
0
SID_R1[2]
0
SID_R1[1]
0
SID_R1[0]
0
Reset
Table 28. 4th byte - DnSID_R2R3
Bit
7
6
5
4
3
2
1
0
R
W
SID_R2[3]
0
SID_R2[2]
0
SID_R2[1]
0
SID_R2[0]
0
SID_R3[3]
0
SID_R3[2]
0
SID_R3[1]
0
SID_R3[0]
0
Reset
Table 29. PDCM configuration Dn fields description
Field
Description
DSI responses chip time
These bits set the chip duration to use when decoding the current responses from slaves in the DSI bus.
00: 3.0 µs
01: 3.5 µs
10: 4.0 µs
11: 4.5 µs
CHIPTIME[3:0]
SID_Rm[3:0]
Source ID
These bits set the expected source ID of the DSI slave at address m. These values are used as CRC seeds.
33SA0528
17
NXP Semiconductors
6.1.5.6
Channel clear Dn
Table 30. 2nd byte - DnCLR
Bit
7
6
5
4
3
2
1
0
R
W
DnCLR[7]
0
DnCLR[6]
0
DnCLR[5]
0
DnCLR[4]
0
DnCLR[3]
0
DnCLR[2]
0
DnCLR[1]
0
DnCLR[0]
0
Reset
Table 31. Channel clear Dn fields description
Field
Description
Channel clear
DnCLR[7:0]
When writing 0xFF to this byte, all the registers of the corresponding channel n are reset to its initial values.
6.1.5.7
NCKPTN
Table 32. 2nd byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
W
1
0
1
0
1
0
1
0
Reset
1
0
1
0
1
0
1
0
Table 33. 3rd byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
W
1
0
1
0
1
0
1
0
Reset
1
0
1
0
1
0
1
0
Table 34. 4th byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
W
1
0
1
0
1
0
1
0
Reset
1
0
1
0
1
0
1
0
Table 35. NCKPTN fields description
Field
Description
Inverted pattern check
0xAA
This register and its bytes are meant to check validate the communication with the device.
33SA0528
NXP Semiconductors
18
6.1.5.8
CHKPTN
Table 36. 2nd byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
W
0
1
0
1
0
1
0
1
Reset
0
1
0
1
0
1
0
1
Table 37. 3rd byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
W
0
1
0
1
0
1
0
1
Reset
0
1
0
1
0
1
0
1
Table 38. 4th byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
W
0
1
0
1
0
1
0
1
Reset
0
1
0
1
0
1
0
1
Table 39. CHKPTN fields description
Field
Description
Pattern check
0x55
This register and its bytes are meant to check validate the communication with the device.
6.1.5.9
MASKID
Table 40. 2nd byte - MASKID
Bit
7
6
5
4
3
2
1
0
R
W
MASKID[7]
MASKID[6]
MASKID[5]
MASKID[4]
MASKID[3]
MASKID[2]
MASKID[1]
MASKID[0]
Reset
Table 41. MASKID fields description
Field
Description
Mask ID
MASKID[7:0]
These bits indicate the chip's silicon revision number
33SA0528
19
NXP Semiconductors
6.1.6 Electrical characteristics
Table 42. SPI modules electrical characteristics
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
I/O logic levels (CSB, MOSI, SCK)
VIH
VIL
VHYST
•
•
•
Input high-voltage
Input low-voltage
Input hysteresis
2.0
—
0.1
—
—
0.35
—
0.9
0.8
V
Input capacitance
CI
—
0.0
—
—
—
10
pF
V
•
CSB, MOSI, and SCK
Output low voltage
VOL
0.5
•
MISO pin = 1.0 mA
Output high voltage
VOH
VCC5 - 0.5
V
•
MISO pin = -1.0 mA
Output leakage current
•
•
MISO pin = 0 V
MISO pin = VCC5
IMISO
-10
-10
—
—
10
10
μA
SCK, CSB pull-up current
VOUT = VCC5 - 2.0 V
IPU
-50
5.0
-30
10
-10
13
μA
μA
•
MOSI pull-down current
VOUT = 1.0 V
IPD
•
6.2
DSI protocol engine
6.2.1 Block diagram
SPI
DSI Channel 1
DSI Channel 0
DH1
DL1
GNDP_DSI1
DH0
DL0
GNDP_DSI0
CH0
CH1
To DSI3 bus
(slaves)
Figure 9. DSI modules pins and block diagram
33SA0528
NXP Semiconductors
20
6.2.2 DSI implementation parameters
6.2.2.1
Bus driver
VDSI
VHIGH
Bus Receiver
DnH
DnL
Differential voltage
(DnH – DnL)
VLOW
Current
Limitation
SPI
DSI Logic
Hi Z
Figure 10. DSI bus driver block diagram
CS0B
2V
tSE_DLY
Command
VHIGH
V
HIGH-0.6
VHIGH-0.9
VHIGH-1.1
DnH
V
HIGH-1.4
VLOW
tSLEW
VHIGH
0.9*VHIGH
VHIGH-0.3
VHIGH-0.9
VHIGH-1.1
VLOW
tDISC_PULSE
tDISC_Per
0.1*VHIGH
GND
tEN_Rise
Figure 11. DSI bus voltages timings
33SA0528
21
NXP Semiconductors
Table 43. Bus driver characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VHIGH
VLOW
DSI voltage level high (DnH open, DnL open)
DSI voltage level low (DnH open, DnL open)
DSI high level voltage drift
7.5
—
—
—
VHIGH - 1.8
150
V
V
VHIGH - 2.2
VHIGH_Drift
-150
—
—
mV
mV
W
Common mode voltage peak to peak during single bit signal
High-side output resistance
—
100
RHIGH
RLOW
RM
—
3.0
3.0
—
5.4
Low-side output resistance
—
5.4
W
Total output resistance (RHIGH + RLOW
Communication data rate
)
—
10
W
DRATE
—
125
—
kbps
Command start delay (CS0B rising edge to command start edge)
tSE_DLY
•
•
PDCM (DnPDCM_DLY = 0)
CRM
—
—
—
—
1.5
5.0
μs
tSLEW
tEN_Rise
tDISC_PULSE
tDISC_PER
Voltage signal slew rate
Bus enable rising time
2.0
—
—
—
6.0
10
V/μs
μs
Self discovery pulse width
Self discovery pulse period
15
16
17
μs
120
125
130
μs
6.2.2.2
Bus receiver
DHn
Adder 1
Receiver
Decision
Logic
Adder 1
Receiver
SPI0 Data buffer
SPI1 Data buffer
Adder 2
Receiver
Decision
Logic
Adder 2
Receiver
DLn
Figure 12. DSI bus receiver block diagram
The bus receiver presents doubled redundancy for safety purposes. It consists of two receivers and two independent decision logics.
•
•
The first decision logic checks data integrity of the first receiver (referring to the second receiver), and transfers this data to SPI0
data buffer.
The second decision logic checks data integrity of the second receiver (referring to the first receiver), and transfers this data to SPI1
data buffer.
The only case where ER bit is not set is given by satisfying all three conditions below. Any other case sets an ER bit.
•
•
•
Receiver 1 CRC is OK
Receiver 2 CRC is OK
Receiver 1 XOR (bitwise) receiver 2 is OK
33SA0528
NXP Semiconductors
22
VH
2*Iresp
VH-1.1V
90%
VL
tRESP_START_CRM
10%
Iq+2.1mA
tSLEW_RESP
Iq
2*Iresp
Iresp
IQ
0A
tVLD
CS0B
Can read response data
Slave N response
Slave N+1 response
tIPS
tCHIP
Figure 13. DSI bus currents timings
Table 44. Bus receiver characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Total slaves quiescent current
Min.
Typ.
Max.
Unit
Notes
IQ_TOTAL
-
-
40
mA
IRESP_TH_LOW_
IQ_TOTAL
+5.0
IQ_TOTAL
+7.0
Response current low threshold (receiver 1)
Response current high threshold (receiver 1)
Response current low threshold (receiver 2)
Response current high threshold (receiver 2)
-
-
-
-
mA
mA
mA
mA
DnH
IRESP_TH_HIGH_
IQ_TOTAL
+15
IQ_TOTAL
+20
DnH
IRESP_TH_LOW_
IQ_TOTAL
+5.0
IQ_TOTAL
+7.0
ADDER
IRESP_TH_HIGH_
IQ_TOTAL
+15
IQ_TOTAL
+20
ADDER
tRESP_START_CRM Response start time in command and response mode
280
21
295
-
310
45
μs
mA/μs
μs
tSLEW_RESP
tCHIP_CRM
Response current slew rate
Chip time in command and response mode
4.75
5.0
5.25
33SA0528
23
NXP Semiconductors
Table 44. Bus receiver characteristics (continued)
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
tVLD
tIPS
Data valid time
-
-
-
1.0
-
μs
Inter packet separation
3.0
chips
6.2.3 Block logic and operation
Buffer Check
Mode
BCK[1:0]
BCK0 | BCK1
DnCLR[7:0]
Enabled
POR
DPC[2:0]
EN
EN
Command and
Response
Mode
Send
Discovery
Pulses
Disabled
DnCLR[7:0]
PDCM_EN
Periodic Data
Collection Mode
Figure 14. DSI block main states diagram for channel n
There are three states in the DSI protocol engine’s logic for each channel: disabled, enabled and buffer check mode. In the disabled state,
all SPI data buffers are reset to their initial values and any write access to the Tx buffer is ignored. The enabled state contains two modes,
command and response mode, and periodic data collection mode. In command and response mode, the MCU can request the 33SA0528
to transceive any data (Tx/Rx buffers) or DSI discovery pulses to the DSI slaves in the bus. In periodic data collection mode, the DSI
master stores and decodes four slaves responses per channel after every broadcast read command is sent through the DSI bus, which
happens every 500 μs if in auto mode, or manually each time the DnBRC bit is set.
33SA0528
NXP Semiconductors
24
6.2.3.1
Command and response mode
Command
(Manchester encoded)
Voltage
Current
Response
(Tri-level current moduration)
Figure 15. DSI Command and response mode operating principle
In this mode, any data written to the CRM Tx/Rx data buffer registers by the MCU, via SPI0, is outputted through the DSI bus as
Manchester encoded voltage pulses, composing a command. The DSI slaves connected to the bus then receive this command and, if
applicable, send back their responses following a tri-level current modulation, as detailed in the DSI protocol specification. The response
is decoded by the DSI block and stored back to the corresponding CRM Tx/Rx Data Buffer register.
When TE is 0, write access
to Tx buffer is ignored.
Write to
Tx buffer
Read from Write to
Tx buffer Tx buffer
SPI Tx
MCU can read Rx buffer in any
cases.
SPI Transaction
SPI Rx
TE bit:
RNE bit:
1
0
1
0
1
0
1
0
Command
at least 500us
Response
Figure 16. Command and response mode behavior on TE and RNE bits
The DSI voltage command is transmitted through the DSI bus immediately after the MCU completes writing data, via SPI0, to the CRM
Tx/Rx data buffer register. This is not valid if the elapsed time from the start of the previous command is less than 500 μs. If the MCU
writes data to the CRM Tx buffer when the TE bit is set (TE=1) and 500 μs have not yet elapsed from the start of the previous command,
a new command is queued and outputted once this time is concluded. When the TE bit is cleared (TE=0), any MCU write operation to the
CRM Tx buffer are ignored. However, the MCU can read the CRM Rx Data Buffer at any time.
Received data is stored
New data arrives
Overwrite data and status
RNE=0
RNE=1
Rx Data Buffer register is read by MCU
Clear other status bits
Figure 17. Command and response mode RNE bit behavior
33SA0528
25
NXP Semiconductors
If a DSI slave response is detected by the receiver logic, the RNE bit is set (RNE=1), indicating there is new data in the buffer. When the
MCU reads the Rx data buffer register, the RNE bit clears (RNE=0). If another DSI slave response is detected with the receiver not being
empty, the Rx data buffer overwrites with the new data and the RNE bit is kept set (RNE=1).
To enter into command and response mode, the corresponding EN bit from the channel control register must be set (EN=1). If BCK[1:0]
bits and EN bit are set in the same SPI transaction, the operation on the EN bit is ignored as the BCK bits have higher priority.
There are two ways to exit this mode (note that data buffers are cleared entering into disabled mode):
•
•
Clear the corresponding EN bit (EN=0).
Write 0xFF to the DnCLR byte of the channel clear register in SPI0.
6.2.3.2
Discovery pulses
The 33SA0528 can send DSI discovery commands as detailed in the DSI protocol specification, for the automatic addressing of the slaves
connected to the bus (discovery mode). For this, the device must first enter command and response mode.
Command and
Response
Mode
DPC[2:0]
t<16us
t<109 μs
VHIGH
tELAPSED = 16 μs
Decrement DPC[2:0]
VLOW
tELAPSED = 109 μs AND
DPC[2:0] is not 0
DPC[2:0] = 0
Figure 18. Send discovery pulses behavior
When writing a non-zero value to the DPC[2:0] bits of the corresponding channel control register, a series of voltages pulses are sent
through the DSI bus, between VLOW and VHIGH. The number of pulses is the value written to the DPC bits and, as detailed in the DSI
protocol specification, it must be equal or higher to the number of DSI slaves to be addressed. Once all the pulses have been transmitted,
the device goes back to command and response mode.
6.2.3.3
Periodic data collection mode
BRC
BRC
353.8 μs
226 μs
112.8 μs
1st slot
2nd slot
3rd slot
4th slot
DnR0DataBuffer
DnR1DataBuffer
DnR2DataBuffer
DnR3DataBuffer
Figure 19. DSI periodic data collection mode operating principle
33SA0528
NXP Semiconductors
26
In this mode, the 33SA0528 can send special voltage pulses through the DSI bus, called broadcast read commands, after which it stores
all received responses to the corresponding SPI0 and SPI1 PDCM data buffer registers. The responses must be separated following a
TDMA approach, as defined in the DSI protocol specification.
Slot boundary
Correct data
Error
Correct data
Error
Figure 20. Periodic data collection mode time slots
The current-modulated responses from the DSI slaves must be contained between the boundaries of one of the four available time slots.
Each time slot has an associated PDCM data buffer DnRm register. If two or more responses overlap each other, the ER bit of the
corresponding data buffer register is set (ER=1).
Table 45. Periodic data collection mode time slots and data buffer registers
Address
Time slot
SPI0 data buffer
SPI1 data buffer
1
2
3
4
20 - 112.8 μs
112.8 - 226 μs
226 - 353.8 μs
353.8 - 500 μs
PDCM data buffer DnR0
PDCM data buffer DnR1
PDCM data buffer DnR2
PDCM data buffer DnR3
PDCM data buffer DnR0
PDCM data buffer DnR1
PDCM data buffer DnR2
PDCM data buffer DnR3
The 33SA0528 features two modes for transmitting the BRC: manual mode for single shot transmissions, and automatic mode where a
BRC is sent every 500 μs.
CS0B
This access is ignored.
W, DnBRC=1
W, DnBRC=1
MOSI
DnPDCM_DLY[7:0] x 5 clk
DnBRC=1
DnBRC bit is cleared
DnH
Figure 21. Periodic data collection mode manual BRC
If the DnAUTO bit is cleared (DnAUTO=0), the device works in manual mode, so a single BRC transmits through the DSI bus when setting
the corresponding DnBRC bit (DnBRC=1) in the PDCM control register of SPI0. Any subsequent write access to the DnBRC bit is ignored
until the DSI BRC pulse is transmitted and the DnBRC bit gets cleared (DnBRC=0). The transmission occurs after the configured PDCM
delay has elapsed from the moment the BRC bit was set. The delay is calculated as five clock times the value on the corresponding
PDCM_DLY[7:0] bits.
33SA0528
27
NXP Semiconductors
CS0B
MOSI
W, DnAUTO=1
500 μs
DnH
Figure 22. Periodic data collection mode automatic BRC
At the moment the DnAUTO bit is set (DnAUTO=1), a BRC transmits right after the SPI0 transmission finishes, and with a periodicity of
500 μs. Write access to this bit is ignored when the corresponding DnPDCM_EN bit is cleared (DnPDCM_EN=0).
New data arrives
Overwrite data and status
Received data is stored
RNE=0
RNE=0
RNE=1
2 clock cycles
Rx Data Buffer register is read by MCU
Clear other status bits
Figure 23. Periodic data collection mode RNE bit behavior
For each of the PDCM data buffer registers, when a DSI slave response is detected by the receiver logic the RNE bit is set (RNE=1),
indicating there is new data in the buffer. When the MCU reads the Rx data buffer register, the RNE bit is cleared (RNE=0). If another DSI
slave response is detected with the receiver not being empty, the Rx data buffer overwrites with the new data and the RNE bit is cleared
(RNE=0) and then reset after two clock cycles (RNE=1).
To enter into periodic data collection mode, the corresponding PDCM_EN bit from the PDCM control register must be set (PDCM_EN=1).
To exit this mode, a 0xFF must be written to the corresponding DnCLR[7:0] bits (note that all of the corresponding channel registers are
cleared as they enter into disabled mode).
6.2.3.4
Buffer check mode
This mode tests and verifies the state of the buffers (for stuck-at bits checking, for example) by routing them internally to other registers.
When in this mode, all data written to the SPI0 Tx buffer registers is not transmitted over the DSI bus, but instead copied to each of the
periodic data buffer registers, both in SPI0 and SPI1. This action sets the associated RNE bits of the Rx registers. The Tx bytes to Rx
bytes routing are done as follows:
33SA0528
NXP Semiconductors
28
CRM Tx Data Buffer Dn
DnData2[19:16] DnData1
DnData0
PDCM Data Buffer DnR0
PDCM Data Buffer DnR0
DnData2[19:16]
DnData1
DnData0
DnData0
DnData2[19:16]
DnData1
DnData0
DnData0
.
.
.
.
.
.
PDCM Data Buffer DnR3
PDCM Data Buffer DnR3
DnData2[19:16]
DnData1
DnData2[19:16]
DnData1
SPI0 registers
SPI1 registers
Figure 24. Buffer check mode bytes routing
To enter into this mode, both BCK0 and BCK1 bits must be set in the same SPI0 transaction.
There are two ways to exit this mode and so, go back to the disabled state:
1. Clear any of BCK0 or BCK1 bits by writing a 0 to them.
2. Clear the channel by writing the CLR[7:0] bits.
6.3
Bus driver protection
The bus driver has a current limiter and protection circuit with the following features.
•
•
•
Limiting the current output through DHn and DLn to a specific value.
Overcurrent shutdown of the corresponding DSI channel (current over threshold for a specified time).
Thermal shutdown of the corresponding DSI channel (temperature over threshold for a specified time).
The corresponding bits in the SPI registers are set to indicate the condition met.
Table 46. Bus driver protection characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
High-side current limit (sink)
Min.
Typ.
Max.
Unit
Notes
ILIM_DNH(SINK)
100
-200
100
—
—
—
—
200
-120
200
mA
mA
mA
mA
ILIM_DNH(SOURCE) High-side current limit (source)
ILIM_DNL(SINK) Low-side current limit (sink)
ILIM_DNL(SOURCE) Low-side current limit (source)
Disabled high-side leakage
-200
-120
ILK_DNH
CT
RT, HT
•
•
•
DHn ≤ VDSI
DHn ≤ VDSI
VDSI < DHn < 16 V
-35
-10
-1000
—
—
—
10
10
1000
μA
33SA0528
29
NXP Semiconductors
Table 46. Bus driver protection characteristics (continued)
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Disabled low-side leakage
ILK_DNL
-10
-1000
—
—
10
1000
μA
•
•
DHn ≤ VDSI
VDSI < DHn < 16 V
tOCS_DLY
230
320
560
μs
Overcurrent shutdown delay
6.4
Power supply monitor
This block is responsible of monitoring the voltages on pins VDSI, VCC5, V2P5A, and V2P5D.
6.4.1 Monitor behavior
6.4.1.1
VDSI
If the voltage on this pin drops below the defined voltage threshold for longer than the voltage threshold mask time, the 33SA0528
continues to send queued DSI commands, but takes following actions:
•
•
Not setting any RNE bit in the data buffer registers
Setting UV bits in the data buffer registers and DnSTAT registers
These actions continues until one of following condition is applied:
•
•
•
The device is reset by POR
DnCLR[7:0] bits are set to 0xFF in one SPI transaction
EN bits in DnCTRL registers are cleared and then reset (EN = 0 then EN = 1)
Finally, if VDSI falls below the VDSI voltage reset threshold, the device is reset.
6.4.1.2
VCC5
If VCC5 voltage falls below its undervoltage threshold, the 33SA0528 is reset. In the case of VCC5 rising, the device is activated after a
specific deglitch time from the threshold crossing point. In the case of VCC5 falling, the device is reset after a specific deglitch time from
the threshold crossing point.
6.4.1.3
V2P5A and V2P5D
If any of the voltages fall below the corresponding threshold level, the 33SA0528 resets.
6.4.2 Electrical parameters
Table 47. Power supply monitor characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VDSI_UV
tDSI_UV
VDSI_RST
tDSI_RST
VDSI voltage low threshold
Deglitch time
8.2
13
8.5
16
—
8.8
25
V
μs
V
VDSI voltage reset threshold
Deglitch time (analog)
—
5.5
12.5
4.0
6.0
μs
33SA0528
NXP Semiconductors
30
Table 47. Power supply monitor characteristics (continued)
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VCC5_UV1
VCC5 undervoltage threshold for system reset
4.5
4.65
4.8
V
When VCC5 ramps up, time delay from VCC5 pass over the
undervoltage threshold to start reset recovery
tCC5_UV1_RISE
tCC5_UV1_FALL
13
13
16
16
25
25
μs
μs
When VCC5 ramps down, time delay from VCC5 pass below the
undervoltage threshold to reset activation
V2P5A_UV
V2P5D_UV
Internal analog supply undervoltage threshold
2.0
2.0
0.5
0.5
0.2
0.2
13
2.175
2.175
1.0
2.35
2.35
2.5
4.0
0.4
0.4
25
V
V
Internal digital supply undervoltage threshold
t2P5A_UV
Internal analog supply undervoltage detection deglitch time
Internal digital supply undervoltage detection deglitch time
Analog ground connection open detection threshold
Digital ground connection open detection threshold
Deglitch time of analog ground connection open detection
Deglitch time of digital ground connection open detection
μs
μs
V
t2P5D_UV
1.0
VGNDA_OPEN
VGNDD_OPEN
tGNDA_OPEN
tGNDD_OPEN
0.3
0.3
V
16
μs
μs
13
16
25
6.5
Clock and reset module
6.5.1 Block diagram
CLKOUT
V2P5AV2P5D
scan clock
CFM2 signal
Clockfrequency
watchdog
CFM2 flag
Frequency
Divider
(4.0 MHz±5%)
Oscillator
(fINTCLK=8.0 MHz±5%)
Clockgenerator
(No resonator)
CFM3 signal
pll lock
CFM3 flag
Frequency
Divider
(10MHz±1%)
DSI_CLOCK10 MHz±1%
DSI3
20 MHz±1%
PLL Block
CLKIN
GNDD
External clock
From MCU
4.0 MHz±1%
Figure 25. Clock module pins and block diagram
33SA0528
31
NXP Semiconductors
The clock module takes a 4.0 MHz clock source from the CLKIN pin. This frequency is usually provided by the MCU. As an output, it
provides this same frequency through a buffer connected to the CLKOUT pin.
This module has an internal frequency generator used as reference to detect abnormalities in CLKIN. If any abnormality is detected, the
CFM2 bit of the channel control registers in SPI0 is set (CFM2=1).
The clock module also includes a PLL block that generates a 10 MHz frequency from CLKIN. This generated frequency is used for the
DSI protocol engine logic. If the PLL block is unstable (i.e. PLL unlocked), the CFM3 bit of the channel control registers in SPI0 is set
(CFM3=1).
When any of both CFM2 or CFM3 bits are set, the 10 MHz frequency is tied to low level, meaning the DSI protocol engine is not functional,
as it is lacking its input clock. Each flag can be cleared (CFMx=0) by writing a 0 to it via SPI communication.
6.5.2 Electrical parameters
Table 48. Clock and reset module characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
I/O logic levels (RSTB, CLKIN)
VIH
VIL
VHYST
•
•
•
Input high-voltage
Input low-voltage
Input hysteresis
2.0
—
0.1
—
—
0.35
—
0.9
0.8
V
Input capacitance
RSTB and CLK
CI
—
—
—
20
pF
V
•
Output low-voltage
VOL
0.0
0.5
•
CLKOUT pin = 1.0 mA
Output high-voltage
VOH
IRSTBPD
IPD
VCC5 - 0.5
100
—
200
10
—
400
13
V
•
CLKOUT pin = 1.0 mA
RSTB pull-down resistor
kΩ
μA
CLKIN pull-down current
5.0
•
VOUT = 1.0 V
fINTCLK
Internal clock frequency
-5.0%
3.50
4.09
—
8.0
3.76
4.26
—
+5.0%
3.91
4.58
64
MHz
MHz
MHz
μs
fCLKIN_WD_FALL
fCLKIN_WD_RISE
tCLKIN_WD
External input clock watchdog unusual fall frequency
External input clock watchdog unusual rise frequency
Clock frequency watchdog detect time
tCLKIN_TRAN
External input clock transfer function design guarantee
—
—
10
ns
CLKIN input frequency for PLL operating
•
•
•
PLL ratio vs. CLKIN
3.76 MHz ≤ CLKIN ≤ 4.24 MHz
V2P5D > 2.0 V
fCLKIN_OP
4.95
5.0
5.05
tCLKIN_HI
tCLKIN_LO
tCLKIN_PER
tCLKIN_LH
CLKIN periods time high
75
75
245
—
—
—
—
—
ns
ns
ns
ns
ns
ns
μs
μs
CLKIN periods time low
CLKIN period
250
—
255
100
100
25
CLKIN transition time for low to high
CLKIN transition time for high to low
CLKIN clock edge jitter for PLL operating
PLL lock time for first lock
PLL lock time for re-lock
tCLKIN_HL
—
—
tCLKIN_JITT
tPLL_LOCK
tPLL_RELOCK
-25
—
—
10
15
40
—
30
33SA0528
NXP Semiconductors
32
7
Typical applications
7.1
Introduction
The 33SA0528 is a standalone, dual-channel DSI transceiver. This means it can act on its own as a direct interface between an MCU and
up to eight DSI slaves. The MCU communicates with the 33SA0528 via its SPI0 (for device configuration and DSI operation) and its
SPI1(for DSI slaves’ data redundancy). The device can also work as a companion chip for a DSI system basis chip master. In this case,
the 33SA0528 is used to expand the channels of the DSI SBC, increasing in turn the maximum number of slaves which can be connected
to the system. The main advantage of the companion chip operation is the SBC master’s internal safing logic can access the 33SA0528
DSI data, making this configuration ideal for safety applications.
7.2
Application diagram
5.0 V 9.0 V
MCU
33SA0528
VDSI
VCC5
V2P5A
V2P5D
0.1 μF 0.1 μF
6.8 μF 2.2 μF
GNDA
GNDD
MMA2712
GPIO
RSTB
SPI0_SCK
SPI0_CS
SPI0_MOSI
SPI0_MISO
SCK0
DH0
DL0
CS0B_D
MOSI0
MISO0
2200 pF
2200 pF
GNDP_DSI0
GNDP_DSI1
SPI1_SCK
SPI1_CS
SCK1
CS1B
MOSI1
MISO1
SPI1_MOSI
SPI1_MISO
DH1
DL1
CLKOUT
CLK_IN
CLK_OUT
CLK
GNDSUB
Figure 26. 33SA0528 typical application schematic as standalone transceiver
33SA0528
33
NXP Semiconductors
MCU
DSI Master SBC
SPI0_CS0
SPI0_CS1
SPI0_CS2
CS0B_A
CS0B_D
CS0B_S
SCK0
MOSI0
MISO0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
CS1B
SCK1
SPI1_CS0
SPI1_SCK
MOSI1
MISO1
SPI1_MOSI
SPI1_MISO
SPI1_CS1
BP0
VCC5
VBUCK
33SA0528
VDSI
VCC5
V2P5A
V2P5D
0.1 μF 0.1 μF
2.2 μF 2.2 μF
GNDA
GNDD
Freescale MMA2712
GPIO
RSTB
SCK0
DH0
DL0
CS0B_D
MOSI0
MISO0
2200 pF
2200 pF
GNDP_DSI0
GNDP_DSI1
SCK1
CS1B
MOSI1
MISO1
DH1
DL1
CLKOUT
CLK_IN
CLK_OUT
CLK
GNDSUB
Figure 27. 33SA0528 typical application schematic as a companion chip
7.3
Layout recommendations
NXP recommends placing the components as described below:
•
•
•
•
•
VDSI to ground 2.2 μF capacitor to be placed close to the chip
VCC5 to ground 2.2 μF capacitor to be placed close to the chip
V2P5A to GNDA 0.1 μF capacitor to be placed close to GNDA pin
V2P5D to GNDD 0.1 μF capacitor to be placed close to GNDD pin
DHn, DLn to GNDP_DSIn 2200 pF capacitors to be placed close to the corresponding GNDP_DSIn pin
33SA0528
NXP Semiconductors
34
8
Packaging
8.1
Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
Package Outline Drawing Number
32-Pin LQFP
AC
98ASH70029A
33SA0528
35
NXP Semiconductors
33SA0528
NXP Semiconductors
36
33SA0528
37
NXP Semiconductors
33SA0528
NXP Semiconductors
38
9
Revision history
Revision
Date
Description of Changes
1.0
1/2015
•
Initial release
•
•
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Minor corrections to form and style - No technical content changes
Changed document status to Advance Information
Changed orderable part number from PC to MC.
Corrected definitions for pins 5, 6, 7, 8, and 24 in Table 2
Updated document form and style
2.0
3.0
2/2015
5/2016
6/2016
7/2016
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Corrected the title of Table 9
Corrected address names in Table 8
33SA0528
39
NXP Semiconductors
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Document Number: MC33SA0528
Rev. 3.0
7/2016
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