MC34911BAC [NXP]
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32;
| 型号： | MC34911BAC |
| 厂家： | 
NXP |
| 描述： | 0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32 驱动 接口集成电路 |
| 文件： | 总92页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C
Document Number: MC33911
Rev. 9.0, 01/2014
Freescale Semiconductor
Technical Data
LIN System Basis Chip with DC
Motor Pre-driver
33911
The 33911G5/BAC is a Serial Peripheral Interface (SPI) controlled
System Basis Chip (SBC), combining many frequently used functions
in an MCU based system, plus a Local Interconnect Network (LIN)
transceiver. The 33911 has a 5.0 V, 50 mA/60 mA low dropout
regulator with full protection and reporting features. The device
provides full SPI readable diagnostics and a selectable timing
watchdog for detecting errant operation. The LIN Protocol Specification
2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry that
can be disabled for higher data rates.
SYSTEM BASIS CHIP WITH LIN
2ND GENERATION
One 50 mA/60 mA high side switch and two 150 mA/160 mA low side
switches with output protection are available. All outputs can be pulse-
width modulated (PWM). Two high voltage inputs are available for use
in contact monitoring, or as external wake-up inputs. These inputs can
be used as high voltage Analog Inputs. The voltage on these pins is
divided by a selectable ratio and available via an analog multiplexer.
The 33911 has three main operating modes: Normal (all functions
available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1, L2),
cyclic sense and forced wake-up), and Stop (VDD on with limited current
capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense,
forced wake-up and external reset).
AC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP
The 33911 is compatible with LIN Protocol Specification 2.0, 2.1, and
SAEJ2602-2. This device is powered by SMARTMOS technology.
Applications
• Window Lift
Features
• Mirror switch
• Door lock
• Sunroof
• Full-duplex SPI interface at frequencies up to 4.0 MHz
• LIN transceiver capable of up to 100 kbps with wave shaping
• One 50 mA/60 mA high side and two 150 mA/60 mA low side
protected switches
• Light control
• Two high voltage analog/logic Inputs
• Configurable window watchdog
• 5.0 V low drop regulator with fault detection and low voltage reset
(LVR) circuitry
33911
V
BAT
VSENSE
VS1
VS2
HS1
L1
L2
LIN INTERFACE
LIN
VDD
PWMIN
ADOUT0
LS1
LS2
M
MCU
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
WDCONF
RST
Figure 1. 33911 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2009 - 2014. All rights reserved.
MC33911G5AC/MC3433911G5AC
1
Orderable Parts
The 33911G5 data sheet is within MC33911G5 Product Specifications Pages 3 to 47
The 33911BAC data sheet is within MC33911BAC Product Specifications pages 48 to 88
Table 1. Orderable Part Variations
Device
Temperature
Package
Generation
1. Increase ESD GUN IEC61000-4-2 (gun test contact with
150 pF, 330 test conditions) performance to achieve
6.0 kV min on the LIN pin.
MC33911G5AC/R2
-40 to 125°C
2. Immunity against ISO7637 pulse 3b
2.5
3. Reduce EMC emission level on LIN
32-LQFP
4. Improve EMC immunity against RF – target new
specification including 3 x 68 pF
MC34911G5AC/R2
-40 to 85°C
5. Comply with J2602 conformance test
MC33911BAC/R2
MC34911BAC/R2
-40 to 125°C
-40 to 85°C
2.0
Initial release
33911
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
MC33911G5 PRODUCT SPECIFICATIONS PAGES 3 TO 47
MC33911G5 PRODUCT SPECIFICATIONS
PAGES 3 TO 47
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
MC33911G5AC/MC3433911G5AC
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ
VS2
VS1
VDD
INTERRUPT CONTROL
AGND
MODULE
LVI, HVI,
ALL OT (VDD,HS,LS,LIN,SD)
VOLTAGE REGULATOR
RESET CONTROL
MODULE
LVR, WD, EXT ΜC
LS1
LOW SIDE
CONTROL
MODULE
WINDOW
WATCHDOG
MODULE
LS2
PWMIN
PGND
VS2
MISO
MOSI
SCLK
CS
HIGH SIDE
CONTROL
MODULE
HS1
SPI
&
CONTROL
VBAT
SENSE MODULE
VSENSE
CHIP TEMPERATURE
SENSE MODULE
ADOUT0
ANALOG INPUT
MODULE
WAKE-UP MODULE
L1
L2
DIGITAL INPUT MODULE
RXD
TXD
LIN PHYSICAL
LAYER
LIN
LGND
WDCONF
Figure 2. 33911G5 Simplified Internal Block Diagram
33911
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
PIN CONNECTIONS
PIN CONNECTIONS
RXD
TXD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC*
L1
MISO
L2
MOSI
NC*
NC*
LS1
PGND
LS2
SCLK
CS
* See Recommendation in Table below
ADOUT0
PWMIN
Figure 3. 33911 Pin Connections
Table 1. 33911 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.
Pin
Pin Name
Formal Name
Definition
This pin is the receiver output of the LIN interface which reports the state of
the bus voltage to the MCU interface.
1
RXD
Receiver Output
This pin is the transmitter input of the LIN interface which controls the state of
the bus output.
2
3
TXD
Transmitter Input
SPI Output
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the
high-impedance state.
MISO
SPI (Serial Peripheral Interface) data input.
4
5
6
7
8
MOSI
SCLK
SPI Input
SPI Clock
SPI (Serial Peripheral Interface) clock Input.
SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
CS
SPI Chip Select
Analog Output Pin 0
PWM Input
ADOUT0
PWMIN
High Side and Low Side Pulse Width Modulation Input.
Bidirectional Reset I/O pin - driven low when any internal reset source is
asserted. RST is active low.
9
RST
Internal Reset I/O
Interrupt output pin, indicating wake-up events from Stop mode or events from
Normal and Normal request modes. IRQ is active low.
Internal Interrupt
Output
10
IRQ
NC
This pin must not be connected.
11 & 30
Not Connected
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
MC33911G5AC/MC3433911G5AC
PIN CONNECTIONS
Table 1. 33911 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.
Pin
Pin Name
Formal Name
Definition
This input pin is for configuration of the watchdog period and allows the
disabling of the watchdog.
Watchdog
Configuration Pin
12
13
14
WDCONF
LIN
This pin represents the single-wire bus transmitter and receiver.
LIN Bus
This pin is the device LIN ground connection. It is internally connected to the
PGND pin.
LGND
LIN Ground Pin
15,16, 20 &
21
This pin must not be connected or connected to ground.
Relay drivers low side outputs.
NC
Not Connected
Low Side Outputs
Power Ground Pin
Wake-up Inputs
17
19
LS2
LS1
This pin is the device low side ground connection. It is internally connected to
the LGND pin.
18
PGND
These pins are the wake-up capable digital inputs(1). In addition, all Lx inputs
can be sensed analog via the analog multiplexer.
22
23
L2
L1
This pin must not be connected or connected to VS2.
High side switch output.
24
25
NC
Not Connected
HS1
High Side Output
26
27
VS2
VS1
These pins are device battery level power supply pins. VS2 is supplying the
HS1 driver while VS1 supplies the remaining blocks.(2)
Power Supply Pin
This pin can be left opening or connected to any potential ground or power
supply
28
29
31
NC
VSENSE
VDD
Not Connected
Battery voltage sense input.(3)
Voltage Sense Pin
Voltage Regulator
Output
+5.0 V main voltage regulator output pin.(4)
This pin is the device analog ground connection.
32
AGND
Analog Ground Pin
Notes
1. When used as digital input, a series 33 k resistor must be used to protect against automotive transients.
2. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
3. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery
connections. It is strongly recommended to connect a 10 k resistor in series with this pin for protection purposes.
4. External capacitor (2.0 µF < C < 100 µF; 0.1 < ESR < 10 ) required.
33911
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2
Normal Operation (DC)
V
V
-0.3 to 27
-0.3 to 40
SUP(SS)
VSUP(PK)
Transient Conditions (load dump)
Supply Voltage at VDD
VDD
-0.3 to 5.5
V
V
Input / Output Pins Voltage(5)
V
-0.3 to VDD +0.3
-0.3 to 11
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD
IN
Interrupt Pin (IRQ)(6)
V
IN(IRQ)
HS1 Pin Voltage (DC)
V
-0.3 to VSUP +0.3
-0.3 to 45
V
V
V
HS
LS1 and LS2 Pin Voltage (DC)
V
LS
L1 and L2 Pin Voltage
V
-18 to 40
±100
Normal Operation with a series 33k resistor (DC)
LxDC
V
Transient input voltage with external component (according to ISO7637-2)
(See Figure 5, page 20)
LxTR
VSENSE Pin Voltage (DC)
VVSENSE
-27 to 40
V
V
LIN Pin Voltage
VBUSDC
VBUSTR
-18 to 40
Normal Operation (DC)
-150 to 100
Transient input voltage with external component (according to ISO7637-2)
(See Figure 4, page 20)
VDD Output Current
I
Internally Limited
A
VDD
Notes
5. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
6. Extended voltage range for programming purpose only.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ESD Capability
AECQ100
V
Human Body Model - JESD22/A114 (C
= 100 pF, R
= 1500 )
ZAP
ZAP
V
V
V
±8.0k
±6.0k
±2000
LIN Pin
ESD1-1
ESD1-2
ESD1-3
L1 and L2
all other Pins
Charge Device Model - JESD22/C101 (C
= 4.0 pF
ZAP
V
V
±750
±500
Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)
All other Pins (Pins 2-7, 10-15, 18-23, 26-31)
ESD2-1
ESD2-2
According to LIN Conformance Test Specification / LIN EMC Test
Specification, August 2004 (C = 150 pF, R = 330 )
ZAP
ZAP
Contact Discharge, Unpowered
LIN pin with 220 pF
V
V
V
V
±20k
±11k
ESD3-1
ESD3-2
ESD3-3
ESD3-4
LIN pin without capacitor
VS1/VS2 (100 nF to ground)
Lx inputs (33 k serial resistor)
>±12k
±6000
According to IEC 61000-4-2 (C
= 150 pF, R
= 330 )
ZAP
ZAP
Unpowered
±8000
±8000
±8000
LIN pin with 220 pF and without capacitor
VS1/VS2 (100 nF to ground)
V
V
V
ESD4-1
ESD4-2
ESD4-3
Lx inputs (33 k serial resistor)
THERMAL RATINGS
Operating Ambient Temperature (7)
T
C
A
33911
34911
-40 to 125
-40 to 85
Operating Junction Temperature
Storage Temperature
T
-40 to 150
-55 to 150
C
C
J
TSTG
RJA
Thermal Resistance, Junction to Ambient
C/W
Natural Convection, Single Layer board (1s)(7), (8)
Natural Convection, Four Layer board (2s2p)(7), (9)
85
56
Thermal Resistance, Junction to Case(10)
RJC
23
C/W
Peak Package Reflow Temperature During Reflow(11), (12)
TPPRT
Note 12
°C
Notes
7. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
8. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
10. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
11. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
12. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and
enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33911
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY VOLTAGE RANGE (VS1, VS2)
VSUP
5.5
–
–
–
–
18
27
40
V
V
V
Nominal Operating Voltage
Functional Operating Voltage(13)
Load Dump
VSUPOP
VSUPLD
–
SUPPLY CURRENT RANGE (VSUP = 13.5 V)
Normal Mode (IOUT at V
= 10 mA), LIN Recessive State(14)
IRUN
–
4.5
10
mA
µA
DD
Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State(14), (15),
ISTOP
(16) (17)
,
5.5 V < VSUP < 12 V
VSUP = 13.5 V
–
–
–
47
62
80
90
13.5 V < VSUP < 18 V
180
400
Sleep Mode, VDD OFF, LIN Recessive State(14), (16)
5.5 V < VSUP < 12 V
ISLEEP
µA
–
–
–
27
33
35
48
VSUP = 13.5 V
160
300
13.5 V VSUP < 18 V
Cyclic Sense Supply Current Adder(18)
ICYCLIC
–
10
–
µA
V
SUPPLY UNDER/OVER-VOLTAGE DETECTIONS
Power-On Reset (BATFAIL)(19)
Threshold (measured on VS1)(18)
Hysteresis (measured on VS1)(18)
VBATFAIL
1.5
–
3.0
0.9
3.9
–
VBATFAIL_HYS
VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
V
Threshold (measured on VS1)
Hysteresis (measured on VS1)
VSUV
VSUV_HYS
5.55
–
6.0
0.2
6.6
–
VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
VSOV
VSOV_HYS
Threshold (measured on VS1)
Hysteresis (measured on VS1)
18
–
19.25
1.0
20.5
–
Notes
13. Device is fully functional. All features are operating.
14. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
15. Total IDD current (including loads) below 100 µA.
16. Stop and Sleep modes current will increase if VSUP exceeds13.5 V.
17. This parameter is guaranteed after 90 ms.
18. This parameter is guaranteed by process monitoring but not production tested.
19. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
VOLTAGE REGULATOR(20) (VDD)
Normal Mode Output Voltage
1.0 mA < I < 50 mA; 5.5 V < V
Symbol
Min
Typ
Max
Unit
VDDRUN
V
< 27 V
SUP
4.75
60
5.00
110
5.25
200
VDD
Normal Mode Output Current Limitation
Dropout Voltage(21)
IVDDRUN
mA
V
VDDDROP
I
= 50 mA
–
0.1
0.25
VDD
Stop Mode Output Voltage
< 5.0 mA
V
V
DDSTOP
I
4.75
6.0
5.0
13
5.25
36
VDD
Stop Mode Output Current Limitation
Line Regulation
I
mA
mV
VDDSTOP
LR
Normal Mode, 5.5 V < V
Stop Mode, 5.5 V < V
< 18 V; I
= 10 mA
VDD
RUN
–
–
–
–
25
25
SUP
LR
STOP
< 18 V; I
= 1.0 mA
VDD
SUP
Load Regulation
mV
°C
LD
Normal Mode, 1.0 mA < I
Stop Mode, 0.1 mA < I
< 50 mA
RUN
–
–
–
–
80
50
VDD
LD
STOP
< 5.0 mA
VDD
Over-temperature Prewarning (Junction)(22)
Interrupt generated, VDDOT Bit Set
T
PRE
90
–
115
13
140
–
Over-temperature Prewarning Hysteresis(22)
Over-temperature Shutdown Temperature (Junction)(22)
Over-temperature Shutdown Hysteresis(22)
RST INPUT/OUTPUT PIN (RST)
T
°C
°C
°C
PRE_HYS
T
150
–
170
13
190
–
SD
T
SD_HYS
VDD Low Voltage Reset Threshold
VRSTTH
VOL
4.3
4.5
4.7
V
V
Low-state Output Voltage
IOUT = 1.5 mA; 3.5 V VSUP 27 V
0.0
–
0.9
High-state Output Current (0 V < VOUT < 3.5 V)
IOH
-150
-250
-350
µA
Pull-down Current Limitation (internally limited)
VOUT = VDD
IPD_MAX
mA
1.5
-0.3
–
–
–
8.0
Low-state Input Voltage
High-state Input Voltage
Notes
VIL
VIH
0.3 x VDD
VDD +0.3
V
V
0.7 x VDD
20. Specification with external capacitor 2.0 µF < C < 100 µF and 100 m ESR 10
21. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).
22. This parameter is guaranteed by process monitoring but not production tested.
33911
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
MISO SPI OUTPUT PIN (MISO)
Low-state Output Voltage
= 1.5 mA
Symbol
Min
Typ
Max
Unit
VOL
V
V
I
0.0
VDD -0.9
-10
–
–
–
1.0
VDD
10
OUT
High-state Output Voltage
IOUT = -250 µA
VOH
Tri-state Leakage Current
ITRIMISO
µA
0 V VMISO VDD
SPI INPUT PINS (MOSI, SCLK, CS)
Low-state Input Voltage
VIL
VIH
IIN
-0.3
–
–
0.3 x VDD
VDD +0.3
V
V
High-state Input Voltage
0.7 x VDD
MOSI, SCLK Input Current
µA
0 V VIN VDD
-10
10
–
10
30
CS Pull-up Current
0 V < VIN < 3.5 V
IPUCS
µA
20
INTERRUPT OUTPUT PIN (IRQ)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
VOH
IOUT
V
V
0.0
VDD -0.8
–
–
–
–
0.8
VDD
2.0
High-state Output Voltage
IOUT = -250 µA
Leakage Current
mA
VDD VOUT V
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
Low-state Input Voltage
VIL
VIH
-0.3
–
–
0.3 x VDD
VDD +0.3
V
V
High-state Input Voltage
0.7 x VDD
Pull-up current
IPUPWMIN
µA
0 V < VIN < 3.5 V
10
20
30
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
HIGH SIDE OUTPUT HS1 PIN (HS1)
Symbol
Min
Typ
Max
Unit
Output Drain-to-Source On Resistance
TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V
RDS(ON)
–
–
–
–
–
–
7.0
10
14
TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(23)
TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(23)
Output Current Limitation(24)
0 V < VOUT < VSUP - 2.0 V
ILIMHS1
mA
60
–
90
250
7.5
Open Load Current Detection(25)
IOLHS1
ILEAK
5.0
mA
µA
Leakage Current
-0.2 V < VHS1 < VS2 + 0.2 V
–
–
10
Short-circuit Detection Threshold(26)
5.5 V < VSUP < 27 V
VTHSC
V
VSUP -2.0
–
–
Over-temperature Shutdown(27), (31)
THSSD
140
–
160
10
180
–
°C
°C
Over-temperature Shutdown Hysteresis(31)
THSSD_HYS
LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2)
Output Drain-to-Source On Resistance
RDS(ON)
–
–
–
–
–
–
2.5
4.5
10
TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V
TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V
TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V
Output Current Limitation(28)
2.0 V < VOUT < VSUP
ILIMLSX
mA
160
–
275
7.5
350
12
Open Load Current Detection(29)
IOLLSX
ILEAK
mA
µA
Leakage Current
-0.2 V < VOUT < VS1
–
–
–
–
10
VSUP +5.0
–
Active Output Energy Clamp
IOUT = 150 mA
VCLAMP
V
V
VSUP +2.0
2.0
Short-circuit Detection Threshold(26)
5.5 V < VSUP < 27 V
VTHSC
Over-temperature Shutdown(30), (31)
Over-temperature Shutdown Hysteresis(31)
Notes
TLSSD
140
–
160
10
180
–
°C
°C
TLSSD_HYS
23. This parameter is production tested up to TA = 125°C, and guaranteed by process monitoring up to TJ = 150°C.
24. When over-current occurs, the corresponding high side stays ON with limited current capability and the HS1CL flag is set in the HSSR
25. When open load occurs, the flag (HS1OP) is set in the HSSR
26. HS and LS automatically shutdown if HSOT or LSOT occurs or if the HVSE flag is enabled and an over-voltage occurs.
27. When over-temperature shutdown occurs, the high side is turned off. All flags in HSSR are set.
28. When over-current occurs, the corresponding low side stays ON with limited current capability and the LSxCL flag is set in the LSSR
29. When open load occurs, the flag (LSxOP) is set in the LSSR.
30. When over-temperature shutdown occurs, both low sides are turned off. All flags in LSSR are set.
31. Guaranteed by characterization but not production tested
33911
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
L1 AND L2 INPUT PINS (L1 AND L2)
Symbol
Min
Typ
Max
Unit
Low Detection Threshold(32)
5.5 V < VSUP < 27 V
VTHL
VTHH
VHYS
IIN
V
V
2.0
3.0
0.4
2.5
3.5
0.8
3.0
4.0
1.4
High Detection Threshold(32)
5.5 V < VSUP < 27 V
Hysteresis(32)
V
5.5 V < VSUP < 27 V
Input Current(33)
µA
k
-0.2 V < VIN < VS1
-10
–
10
Analog Input Impedance(34)
RLXIN
800
1300
2000
Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0
LXDS (Lx Divider Select) = 0
)
RATIOLX
0.95
3.42
1.0
3.6
1.05
3.78
LXDS (Lx Divider Select) = 1
Analog Output offset Ratio
LXDS (Lx Divider Select) = 0
LXDS (Lx Divider Select) = 1
VRATIOLx-
mV
%
OFFSET
-80
-22
6.0
2.0
80
22
Analog Inputs Matching
LXMATCHING
LXDS (Lx Divider Select) = 0
LXDS (Lx Divider Select) = 1
96
96
100
100
104
104
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)(35)
External Resistor Range
R
20
–
–
200
15
k
EXT
Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)(36)
WD
-15
%
ACC
ANALOG MULTIPLEXER
Temperature Sense Analog Output Voltage
TA = -40°C
VADOUT0_TEMP
V
2.0
2.8
3.6
-
2.8
3.6
4.6
T
A = 25°C
3.0
TA = 125°C
Temperature Sense Analog Output Voltage per characterization(37)
TA = 25°C
VADOUT0_25
V
3.1
3.15
3.2
Internal Chip Temperature Sense Gain
STTOV
9.0
9.9
10.5
10.2
12
mV/K
mV/K
Internal Chip Temperature Sense Gain per characterization at 3
temperatures(37) See Figure 16, Temperature Sense Gain
STTOV_3T
10.5
VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0
5.5 V < VSUP < 27 V
)
RATIOVSENSE
5.0
5.25
5.5
Notes
32. The unused Lx pins must be connected to ground.
33. Analog multiplexer input disconnected from Lx input pin.
34. Analog multiplexer input connected to Lx input pin.
35. For VSUP 4.7 to 18 V
36. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k
37. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed
by production test.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per
characterization(38)
RATIOVSENSECZ
5.5 <VSUP< 27 V
5.15
-30
5.25
-10
5.35
30
0
VSENSE Output Related Offset
OFFSETVSENSE
mV
mV
VSENSE Output Related Offset per characterization(38)
OFFSETVSENSE_
CZ
-30
-12.6
ANALOG OUTPUT (ADOUT0)
Maximum Output Voltage
-5.0 mA < IO < 5.0 mA
VOUT_MAX
V
V
VDD -0.35
0.0
–
–
VDD
0.35
Minimum Output Voltage
-5.0 mA < IO < 5.0 mA
VOUT_MIN
RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
V
V
0.0
–
–
0.8
High-state Output Voltage
IOUT = -250 µA
VOH
VDD -0.8
VDD
TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)
Low-state Input Voltage
VIL
VIH
-0.3
0.7 x VDD
10
–
–
0.3 x VDD
VDD +0.3
30
V
V
High-state Input Voltage
Pin Pull-up Current, 0 V < VIN < 3.5 V
IPUIN
20
µA
LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0)
LIN Under Voltage threshold
VTH_UNDER_
VOLTAGE
V
Positive and Negative threshold (VTHP, VTHN
)
5.0
6.0
Hysteresis (VTHP - VTHN
Notes
)
VJ2602_DEG
400
mV
38. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed
by production test.
33911
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(39)
Operating Voltage Range
Symbol
Min
Typ
Max
Unit
VBAT
VSUP
8.0
7.0
18
18
40
V
V
Supply Voltage Range
Voltage Range within which the device is not destroyed
VSUP_NON_OP
IBUS_LIM
-0.3
V
Current Limitation for Driver Dominant State
Driver ON, VBUS = 18 V
mA
40
-1.0
–
90
–
200
–
Input Leakage Current at the receiver
Driver off; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
IBUS_PAS_REC
IBUS_NO_GND
mA
µA
Leakage Output Current to GND
Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT
–
20
1.0
Control unit disconnected from ground(40)
mA
GNDDEVICE = VSUP; VBAT = 12 V; 0 < V
< 18 V
-1.0
–
BUS
V
Disconnected; VSUP_DEVICE = GND; 0 V < V
< 18 V(41)
BUS
IBUSNO_BAT
VBUSDOM
VBUSREC
µA
BAT
–
–
–
–
100
0.4
Receiver Dominant State
Receiver Recessive State
VSUP
VSUP
VSUP
0.6
0.475
–
–
Receiver Threshold Center
(VTH_DOM + VTH_REC)/2
VBUS_CNT
0.5
0.525
Receiver Threshold Hysteresis
VHYS
VSUP
(VTH_REC - VTH_DOM
)
–
–
0.175
Voltage Drop at the serial Diode in pull-up path
VBAT_SHIFT
VSERDIODE
VSHIFT_BAT
VSHIFT_GND
VBUSWU
0.4
0
1.0
11.5%
11.5%
5.8
V
VBAT
VBAT
V
GND_SHIFT
0
LIN Wake-up threshold from Stop or Sleep Mode(42)
5.3
30
LIN Pull-up Resistor to V
SUP
RSLAVE
20
140
–
60
k
Over-temperature Shutdown(43)
TLINSD
160
10
180
–
°C
Over-temperature Shutdown Hysteresis
TLINSD_HYS
°C
Notes
39. Parameters guaranteed for 7.0 V VSUP 18 V.
40. Loss of local ground must not affect communication in the residual network.
41. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition.
42. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale
does not guarantee this parameter during the product's life time.
43. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
SPI INTERFACE TIMING (SEE Figure 13, PAGE 23)
SPI Operating Frequency
Symbol
Min
Typ
Max
Unit
f
t
–
–
–
–
–
–
–
–
–
4.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MHz
ns
SPIOP
SCLK Clock Period
250
110
110
100
100
40
CLK
PS
SCLK Clock High Time(44)
t
ns
SCLKH
W
SCLK Clock Low Time(44)
t
ns
SCLKL
W
Falling Edge of CS to Rising Edge of SCLK(44)
Falling Edge of SCLK to CS Rising Edge(44)
MOSI to Falling Edge of SCLK(44)
Falling Edge of SCLK to MOSI(44)
MISO Rise Time(44)
t
ns
LEAD
tLAG
ns
t
ns
SISU
t
40
ns
SIH
tRSO
ns
C = 220 pF
L
–
–
40
40
–
–
MISO Fall Time(44)
t
ns
ns
FSO
C = 220 pF
L
Time from Falling or Rising Edges of CS to:(44)
- MISO Low-impedance
t
0.0
0.0
–
–
50
50
SOEN
- MISO High-impedance
t
SODIS
Time from Rising Edge of SCLK to MISO Data Valid(44)
t
ns
VALID
0.2 x VDD MISO 0.8 x VDD, CL = 100 pF
0.0
–
75
RST OUTPUT PIN
Reset Low-level Duration After VDD High (see Figure 12, page 23)
Reset Deglitch Filter Time
t
0.65
350
1.0
1.35
900
ms
ns
RST
t
480
RSTDF
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period(45)
t
ms
PWD
External Resistor REXT = 20 k (1%)
External Resistor REXT = 200 k (1%)
Without External Resistor REXT (WDCONF Pin Open)
8.5
79
10
94
11.5
108
205
110
150
Notes
44. This parameter is guaranteed by process monitoring but not production tested.
45. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k
33911
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
L1 AND L2 INPUTS
Lx Filter Time Deglitcher(46)
t
8.0
20
38
s
WUF
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation(46)
tSTOP
s
–
–
5.0
205
270
+35
Normal Request Mode Timeout (see Figure 12, page 23)
Cyclic Sense ON Time from Stop and Sleep Mode(47)
Cyclic Sense Accuracy(46)
t
110
130
-35
150
200
ms
µs
%
NRTOUT
TON
Delay Between SPI Command and HS/LS Turn On(48)
9.0 V < VSUP < 27 V
tS-
s
ON
–
–
–
–
–
–
10
10
10
Delay Between SPI Command and HS/LS Turn Off(48)
9.0 V < VSUP < 27 V
tS-OFF
s
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)(46)
tSNR2N
s
s
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
tWUCS
tWUSPI
9.0
90
15
—
80
N/A
Minimum Time Between Rising and Falling Edge on the CS
t2CS
4.0
—
—
s
s
J2602 DEGLITCHER
VSUP Deglitcher(49)
(DIS_J2602 = 0)
tJ2602_DEG
35
50
70
Notes
46. This parameter is guaranteed by process monitoring but not production tested.
47. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale
does not guarantee this parameter during the product's life time.
48. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.
49. This parameter has not been monitoring during operating life test.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL
LAYER SPECIFICATION(50), (51)
Duty Cycle 1:
D1
D2
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
0.396
—
—
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V VSUP18 V
Duty Cycle 2:
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
—
—
0.581
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V VSUP18 V
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION(50), (52)
Duty Cycle 3:
D3
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
0.417
—
—
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V VSUP18 V
Duty Cycle 4:
D4
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
—
—
0.590
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V VSUP18 V
Notes
50. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 6, page 21.
51. See Figure 7, page 21.
52. See Figure 8, page 21.
33911
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
V/s
s
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SR
—
20
—
FAST
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(53)
Propagation Delay and Symmetry(54)
tREC_PD
Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
)
—
4.2
—
6.0
2.0
tREC_SYM
-2.0
Bus Wake-up Deglitcher (Sleep and Stop Modes)(55),(59), (56)
tPROPWL
42
70
95
s
s
Bus Wake-up Event Reported
From Sleep Mode(57)
tWAKE_SLEEP
tWAKE_STOP
—
—
1500
35
From Stop Mode(58)
9.0
27
TXD Permanent Dominant State Delay
tTXDDOM
0.65
1.0
1.35
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
PWMIN pin(59)
fPWMIN
kHz
Max. frequency to drive HS and LS output pins
10
Notes
53. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 6, page 21.
54. See Figure 9, page 22
55. See Figure 10, page 22 for Sleep and Figure 11, page 22 for Stop mode.
56. This parameter is tested on automatic tester but has not been monitoring during operating life test.
57. The measurement is done with 1.0 µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when V reaches 3.0 V.
DD
See Figure 10, page 22. The delay depends of the load and capacitor on VDD
.
58. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,
page 22.
59. This parameter is guaranteed by process monitoring but not production tested.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
33911
TRANSIENT PULSE
GENERATOR
1.0 nF
LIN
(
NOTE
)
GND
PGND LGND AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 4. Test Circuit for Transient Test Pulses (LIN)
33911
Transient Pulse
Generator
(Note)
1.0 nF
L1, L2
10 k
GND
PGND LGND AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.
Figure 5. Test Circuit for Transient Test Pulses (Lx)
VSUP
R0
LIN
TXD
R0 AND C0 COMBINATIONS:
RXD
• 1.0 K and 1.0 nF
• 660 and 6.8 nF
• 500 and 10 nF
C0
Figure 6. Test Circuit for LIN Timing Measurements
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
t
t
BUS_REC(MIN)
BUS_DOM(MAX)
VLIN_REC
74.4% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
58.1% V
SUP
TH
LIN
Thresholds of
receiving node 2
42.2% V
28.4% V
SUP
TH
REC(MIN)
SUP
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD
tBIT
tBIT
t
t
BUS_REC(MIN)
BUS_DOM(MAX)
VLIN_REC
77.8% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
61.6% V
SUP
TH
LIN
Thresholds of
receiving node 2
38.9% V
25.1% V
SUP
TH
REC(MIN)
SUP
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 8. LIN Timing Measurements for Slow Slew Rate
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VLIN_REC
0.6% V
SUP
V
BUSREC
V
SUP
LIN BUS SIGNAL
0.4% V
SUP
V
BUSDOM
RXD
t
t
REC_PDF
REC_PDR
Figure 9. LIN Receiver Timing
V
LIN_REC
LIN
5.0 V
VBUSWU
DOMINANT LEVEL
3.0 V
VDD
t
WAKE_SLEEP
t
WL
PROP
Figure 10. LIN Wake-up Sleep Mode Timing
V
LIN_REC
LIN
5.0 V
VBUSWU
DOMINANT LEVEL
t
IRQ
WAKE_STOP
t
WL
PROP
Figure 11. LIN Wake-up Stop Mode Timing
33911
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
V
SUP
V
DD
RST
t
NRTOUT
t
RST
Figure 12. Power On Reset and Normal Request Timeout Timing
t
PSCLK
CS
t
t
WSCLKH
LEAD
t
LAG
SCLK
t
WSCLKL
t
t
SIH
SISU
MOSI
MISO
UNDEFINED
D0
DON’T CARE
D7
DON’T CARE
t
VALID
t
SODIS
t
SOEN
D0
D7
DON’T CARE
Figure 13. SPI Timing Characteristics
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33911 was designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
33911 is well suited to perform relay control in applications
such as a window lift, sunroof, etc. via the LIN bus.
which include a current and voltage sense port and two wake-
up capable pins. An internal voltage regulator provides power
to a MCU device.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with 3-wire bus systems, where one wire is
used for communication, one for battery, and one for ground.
Power switches are provided on the device configured as
high side and low side outputs. Other ports are also provided,
FUNCTIONAL PIN DESCRIPTION
See Figure 1, 33911 Simplified Application Diagram, page 1,
for a graphic representation of the various pins referred to in
the following paragraphs. Also, see the pin diagram on
page 5 for a description of the pin locations in the package.
MASTER IN SLAVE OUT PIN (MISO)
The MISO pin sends data to an SPI-enabled MCU. It is a
digital tri-state output used to shift serial data to the
microcontroller. Data on this output pin changes on the
positive edge of the SCLK. When CS is High, this pin will
remain in the high-impedance state.
RECEIVER OUTPUT PIN (RXD)
The RXD pin is a digital output. It is the receiver output of the
LIN interface and reports the state of the bus voltage: RXD
Low when LIN bus is dominant, RXD High when LIN bus is
recessive.
CHIP SELECT PIN (CS)
CS is an active low digital input. It must remain low during a
valid SPI communication and allow for several devices to be
connected in the same SPI bus without contention. A rising
edge on CS signals the end of the transmission and the
moment the data shifted in is latched. A valid transmission
must consist of 8 bits only.
TRANSMITTER INPUT PIN (TXD)
The TXD pin is a digital input. It is the transmitter input of the
LIN interface and controls the state of the bus output
(dominant when TXD is Low, recessive when TXD is High).
While in STOP mode, a low-to-high level transition on this pin
will generate a wake-up condition for the 33911.
This pin has an internal pull-up to force recessive state in
case the input is left floating.
ANALOG MULTIPLEXER PIN (ADOUT0)
LIN BUS PIN (LIN)
The ADOUT0 pin can be configured via the SPI to allow the
MCU A/D converter to read the several inputs of the Analog
Multiplexer, including the VSENSE, L1, L2 input voltages,
and the internal junction temperature.
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is
compliant to the LIN bus specification 2.0, 2.1, and SAE
J2602-2.
PWM INPUT CONTROL PIN (PWMIN)
The LIN interface is only active during Normal mode. See
Table 5, Operating Modes Overview.
This digital input can control the high side and low sides
drivers in Normal Request and Normal mode.
SERIAL DATA CLOCK PIN (SCLK)
To enable PWM control, the MCU must perform a write
operation to the High Side Control Register (HSCR) or the
Low Side Control Register (LSCR).
The SCLK pin is the SPI clock input. MISO data changes on
the positive transition of the SCLK. MOSI is sampled on the
negative edge of the SCLK.
This pin has an internal 20 A current pull-up.
MASTER OUT SLAVE IN PIN (MOSI)
The MOSI digital pin receives SPI data from the MCU. This
data input is sampled on the negative edge of SCLK.
33911
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
by VBAT through a load, both low sides will have a VDS
voltage equal to the clamping value, as stated in the
specification.
RESET PIN (RST)
This bidirectional pin is used to reset the MCU in case the
33911 detects a reset condition, or to inform the 33911 that
the MCU has just been reset. After release of the RST pin,
Normal Request mode is entered.
DIGITAL/ANALOG PINS (L1 AND L2)
The Lx pins are multi purpose inputs. They can be used as
digital inputs, which can be sampled by reading the SPI and
used for wake-up when 33911 is in low power mode or used
as analog inputs for the analog multiplexer. When used to
sense voltage outside the module, a 33 kohm series resistor
must be used on each input.
The RST pin is an active low filtered input and output formed
by a weak pull-up and a switchable pull-down structure which
allows this pin to be shorted either to VDD or to GND during
software development, without the risk of destroying the
driver.
When used as wake-up inputs L1 and L2 can be configured
to operate in cyclic-sense mode. In this mode the high side
switch is configured to be periodically turned on and sample
the wake-up inputs. If a state change is detected between two
cycles a wake-up is initiated. The 33911 can also wake-up
from Stop or Sleep by a simple state change on L1 and L2.
INTERRUPT PIN (IRQ)
The IRQ pin is a digital output used to signal events or faults
to the MCU while in Normal and Normal Request mode or to
signal a wake-up from Stop mode. This active low output will
transition to high only after the interrupt is acknowledged by
a SPI read of the respective status bits.
When used as analog inputs, the voltage present on the Lx
pins is scaled down by an selectable internal voltage divider
and can be routed to the ADOUT0 output through the analog
multiplexer.
WATCHDOG CONFIGURATION PIN (WDCONF)
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure
the window watchdog period. When connected directly to
ground, the watchdog will be disabled. When this pin is left
open, the watchdog period is fixed to its lower precision
internal default value (150 ms typical).
Note: If an Lx input is selected in the analog multiplexer, it will
be disabled as a digital input and remains disabled in low
power mode. No wake-up feature is available in that
condition.
When an Lx input is not selected in the analog multiplexer,
the voltage divider is disconnected from that input.
GROUND CONNECTION PINS (AGND, PGND,
LGND)
HIGH SIDE OUTPUT PIN (HS1)
The AGND, PGND and LGND pins are the Analog and Power
ground pins.
This high side switch is able to drive loads such as relays or
lamps. Its structure is connected to the VS2 supply pin. The
pin is short-circuit protected and also protected against
overheating.
The AGND pin is the ground reference of the voltage
regulator.
The PGND and LGND pins are used for high current load
return as in the relay-drivers and LIN interface pin.
HS1 is controlled by SPI and can respond to a signal applied
to the PWMIN input pin.
Note: PGND, AGND and LGND pins must be connected
together.
The HS1 output can also be used during low-power mode for
the cyclic-sense of the wake inputs.
LOW SIDE PINS (LS1 AND LS2)
POWER SUPPLY PINS (VS1 AND VS2)
LS1 and LS2 are the low side driver outputs. Those outputs
are short-circuit protected and include active clamp circuitry
to drive inductive loads. Due to the energy clamp voltage on
this pin, it can raise above the battery level when switched off.
The switches are controlled through the SPI and can be
configured to respond to a signal applied to the PWMIN input
pin.
Those are the battery level voltage supply pins. In an
application, VS1 and VS2 pins must be protected against
reverse battery connection and negative transient voltages
with external components. These pins sustain standard
automotive voltage conditions such as a load dump at 40 V.
The high side switch (HS1) is supplied by the VS2 pin. All
other internal blocks are supplied by the VS1 pin.
Both low side switches are protected against overheating. In
case of VS1 disconnection and the low sides are still supplied
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VOLTAGE SENSE PIN (VSENSE)
+5.0 V MAIN REGULATOR OUTPUT PIN (VDD)
This input can be connected directly to the battery line. It is
protected against battery reverse connection. The voltage
present in this input is scaled down by an internal voltage
divider, and can be routed to the ADOUT0 output pin and
used by the MCU to read the battery voltage.
An external capacitor has to be placed on the VDD pin to
stabilize the regulated output voltage. The VDD pin is
intended to supply a microcontroller. The pin is current limited
against shorts to GND and over-temperature protected.
During Stop mode, the voltage regulator does not operate
with its full drive capabilities and the output current is limited.
The ESD structure on this pin allows for excursion up to
+40 V and down to -27 V, allowing this pin to be connected
directly to the battery line. It is strongly recommended to
connect a 10 kohm resistor in series with this pin for
protection purposes.
During Sleep mode, the regulator output is completely shut
down.
33911
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
The VDD regulator is ON and delivers its full current
capability.
INTRODUCTION
The 33911 offers three main operating modes: Normal (Run),
Stop, and Sleep (Low Power). In Normal mode, the device is
active and is operating under normal application conditions.
The Stop and Sleep modes are low power modes with wake-
up capabilities.
If an external resistor is connected between the WDCONF
pin and the Ground, the window watchdog function will be
enabled.
The wake-up inputs (L1 and L2) can be read as digital inputs
or have its voltage routed through the analog-multiplexer.
In Stop mode, the voltage regulator still supplies the MCU
with VDD (limited current capability), while in Sleep mode the
voltage regulator is turned off (VDD = 0 V).
Wake-up from Stop mode is initiated by a wake-up interrupt.
Wake-up from Sleep mode is done by a reset and the voltage
regulator is turned back on.
The LIN interface has slew rate and timing compatible with
the LIN protocol specification 2.0, 2.1 and SAEJ2602. The
LIN bus can transmit and receive information.
The high side and low side switches are active and have
PWM capability according to the SPI configuration.
The selection of the different modes is controlled by the
MOD1:2 bits in the Mode Control Register (MCR).
The interrupts are generated to report failures for VSUP over/
under-voltage, thermal shutdown, or thermal shutdown
prewarning on the main regulator.
Figure 14 describes how transitions are done between the
different operating modes. Table 5, gives an overview of the
operating modes.
SLEEP MODE
The Sleep mode is a low power mode. From Normal mode,
the device enters into Sleep mode by sending one SPI
command through the Mode Control Register (MCR), or (VDD
low > 150 ms) with VSUV = 0. When in Reset mode, a VDD
RESET MODE
The 33911 enters the Reset mode after a power up. In this
mode, the RST pin is low for 1.0 ms (typical value). After this
delay, it enters the Normal Request mode and the RST pin is
driven high.
under-voltage condition with no VSUP under-voltage (VSUV
=
0) will send the device to Sleep mode. All blocks are in their
lowest power consumption condition. Only some wake-up
sources (wake-up inputs with or without cyclic sense, forced
wake-up and LIN receiver) are active. The 5.0 V regulator is
OFF. The internal low-power oscillator may be active if the IC
is configured for cyclic-sense. In this condition, the high side
switch is turned on periodically and the wake-up inputs are
sampled.
The Reset mode is entered if a reset condition occurs (VDD
low, watchdog trigger fail, after wake-up from Sleep mode,
Normal Request mode timeout occurs).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the
device after the Reset mode, or after a wake-up from Stop
mode.
Wake-up from Sleep mode is similar to a power-up. The
device goes in Reset mode except that the SPI will report the
wake-up source and the BATFAIL flag is not set.
In Normal Request mode, the VDD regulator is ON, the
RESET pin is High, and the LIN is operating in RX Only
mode.
STOP MODE
As soon as the device enters in the Normal Request mode an
internal timer is started for 150 ms (typical value). During
these 150 ms, the MCU must configure the Timing Control
Register (TIMCR) and the Mode Control Register (MCR) with
MOD2 and MOD1 bits set = 0, to enter the Normal mode. If
within the 150 ms timeout, the MCU does not command the
33911 to Normal mode, it will enter in Reset mode. If the
WDCONF pin is grounded in order to disable the watchdog
function, it goes directly in Normal mode after the Reset
mode.
The Stop mode is the second low power mode, but in this
case the 5.0 V regulator is ON with limited current drive
capability. The application MCU is always supplied while the
33911 is operating in Stop mode.
The device can enter into Stop mode only by sending the SPI
command. When the application is in this mode, it can wake-
up from the 33911 side (for example: cyclic sense, force
wake-up, LIN bus, wake inputs) or the MCU side (CS, RST
pins). Wake-up from Stop mode will transition the 33911 to
Normal Request mode and generates an interrupt except if
the wake-up event is a low to high transition on the CS pin or
comes from the RST pin.
NORMAL MODE
In Normal mode, all 33911 functions are active and can be
controlled by the SPI interface and the PWMIN pin.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Normal Request Timeout Expired (tNRTOUT
)
V
Low
DD
VDD High and
Power Up
Reset Delay (t
) Expired
RST
Power
Normal
Reset
Down
Request
VDD Low
Normal
WD Failed
VDDLOW(>tN
T) Expired
R
T
O
U
and VSUV = 0
Sleep Command
Wake-up(Reset)
Sleep
Stop
VLow
DD
Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF pin connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via SPI
Sleep Command: Sleep command sent via SPI
Wake-up from Stop mode: L1 or L2 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
Wake-up from Sleep mode: L1 or L2 state change, LIN bus wake-up, Periodic wake-up.
Figure 14. Operating Modes and Transitions
33911
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 5. Operating Modes Overview
Normal
Mode
Function
Reset Mode Normal Request Mode
Stop Mode
Sleep Mode
VDD
LSx
Full
Full
SPI/PWM(60)
SPI/PWM(60)
SPI
Full
SPI/PWM
SPI/PWM
SPI
Stop
-
-
-
-
-
-
-
-
-
HS1
Note(61)
-
Note(62)
-
Analog Mux
Lx
Inputs
Inputs
Wake-up
Wake-up
LIN
Rx-Only
Full/Rx-Only Rx-Only/Wake-up Wake-up
Watchdog
150 ms (typ.) timeout
VSUP/VDD
On(63)/Off
VSUP/VDD
-
-
-
Voltage Monitoring VSUP/VDD
Notes
VDD
60. Operation can be controlled by the PWMIN input.
61. HS1 switch can be configured for cyclic sense operation in Stop mode.
62. HS1 switch can be configured for cyclic sense operation in Sleep mode.
63. Windowing operation when enabled by an external resistor.
High-voltage Interrupt:
INTERRUPTS
Interrupts are used to signal a microcontroller that a
peripheral needs to be serviced. The interrupts which can be
generated, change according to the operating mode. While in
Normal and Normal Request modes, the 33911 signals
through interrupts special conditions which may require a
MCU software action. Interrupts are not generated until all
pending wake-up sources are read in the Interrupt Source
Register (ISR).
Signals when the supply line (VS1) voltage increases above
the VSOV threshold (VSOV).
Over-temperature Prewarning:
Signals when the 33911 temperature has reached the pre-
shutdown warning threshold. It is used to warn the MCU that
an over-temperature shutdown in the main 5.0 V regulator is
imminent.
While in Stop mode, interrupts are used to signal wake-up
events. Sleep mode does not use interrupts. Wake-up is
performed by powering-up the MCU. In Normal and Normal
Request mode the wake-up source can be read by SPI.
LIN Over-temperature Shutdown / TXD Stuck At
Dominant / RXD Short-circuit:
These signal fault conditions within the LIN interface will
cause the LIN driver to be disabled. In order to restart the
operation, the fault must be removed and TXD must go
recessive.
The interrupts are signaled to the MCU by a low logic level of
the IRQ pin, which will remain low until the interrupt is
acknowledged by a SPI read command of the ISR register.
The IRQ pin will then be driven high.
Interrupts are only asserted while in Normal, Normal Request
and Stop mode. Interrupts are not generated while the RST
pin is low.
High Side Over-temperature Shutdown:
Signals a shutdown in the high side output.
The following is a list of the interrupt sources in Normal and
Normal Request modes. Some of these can be masked by
writing to the SPI - Interrupt Mask Register (IMR).
Low Side Over-temperature Shutdown:
Signals a shutdown in the low side outputs.
Low-voltage Interrupt:
Signals when the supply line (VS1) voltage drops below the
VSUV threshold (VSUV).
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
In order to select and activate direct wake-up from Lx inputs,
RESET
the Wake-up Control Register (WUCR) must be configured
with appropriate LxWE inputs enabled or disabled. The
wake-up input’s state is read through the Wake-up Status
Register (WUSR).
To reset a MCU the 33911 drives the RST pin low for the time
the reset condition lasts.
After the reset source is removed, the state machine will drive
the RST output low for at least 1.0 ms (typical value) before
driving it high.
Lx inputs are also used to perform cyclic-sense wake-up.
Note: Selecting an Lx input in the analog multiplexer before
entering low power mode will disable the wake-up capability
of the Lx input
In the 33911, four main reset sources exist:
5.0 V Regulator Low-voltage-Reset (VRSTTH
)
The 5.0 V regulator output VDD is continuously monitored
against brown outs. If the supply monitor detects that the
voltage at the VDD pin has dropped below the reset threshold
Wake-up from Wake-up inputs (L1 and L2) with cyclic
sense timer enabled
The SBCLIN can wake-up at the end of a cyclic sense period
if on one of the two wake-up input lines (L1-L2) a state
change occurs. The HS1 switch can be activated in Sleep or
Stop modes from an internal timer. Cyclic sense and force
wake-up are exclusive. If cyclic sense is enabled, the force
wake-up can not be enabled.
VRSTTH the 33911 will issue a reset. In case of over-
temperature, the voltage regulator will be disabled and the
voltage monitoring will issue a VDDOT Flag independently of
the VDD voltage.
Window Watchdog Overflow
In order to select and activate the cyclic sense wake-up from
Lx inputs, before entering in low power modes (Stop or Sleep
modes), the following SPI set-up has to be performed:
If the watchdog counter is not properly serviced while its
window is open, the 33911 will detect an MCU software run-
away and will reset the microcontroller.
In WUCR: select the Lx input to WU-enable.
In HSCR: enable the desired HS1.
Wake-up From Sleep Mode
• In TIMCR: select the CS/WD bit and determine the
cyclic sense period with CYSTx bits.
• Perform Go to Sleep/Stop command.
During Sleep mode, the 5.0 V regulator is not active, hence
all wake-up requests from Sleep mode require a power-up/
reset sequence.
Forced Wake-up
External Reset
The 33911 can wake-up automatically after a predetermined
time spent in Sleep or Stop mode. Cyclic sense and Forced
wake-up are exclusive. If Forced wake-up is enabled, the
Cyclic Sense can not be enabled.
The 33911 has a bidirectional reset pin which drives the
device to a safe state (same as Reset mode) for as long as
this pin is held low. The RST pin must be held low long
enough to pass the internal glitch filter and get recognized by
the internal reset circuit. This functionality is also active in
Stop mode.
To determine the wake-up period, the following SPI set-up
has to be sent before entering in low power modes:
After the RST pin is released, there is no extra tRST to be
considered.
• In TIMCR: select the CS/WD bit and determine the low
power mode period with CYSTx bits.
• In HSCR: The HS1 bit must be disabled.
WAKE-UP CAPABILITIES
CS Wake-up
Once entered into one of the low-power modes (Sleep or
Stop) only wake-up sources can bring the device into Normal
mode operation.
While in Stop mode, a rising edge on the CS will cause a
wake-up. The CS wake-up does not generate an interrupt,
and is not reported on SPI.
In Stop mode, a wake-up is signaled to the MCU as an
interrupt, while in Sleep mode the wake-up is performed by
activating the 5.0 V regulator and resetting the MCU. In both
cases the MCU can detect the wake-up source by accessing
the SPI registers and reading the Interrupt Source Register.
There is no specific SPI register bit to signal a CS wake-up or
external reset. If necessary this condition is detected by
excluding all other possible wake-up sources.
LIN Wake-up
While in the low-power mode, the 33911 monitors the activity
on the LIN bus. A dominant pulse larger than tPROPWL
followed by a dominant to recessive transition will cause a
LIN wake-up. This behavior protects the system from a short
to ground bus condition. The bit RXONLY = 1 from LINCR
Register disables the LIN wake-up from Stop mode.
Wake-up from Wake-up inputs (L1 and L2) with cyclic
sense disabled
The wake-up lines are dedicated to sense state changes of
external switches and wake-up the MCU (in Sleep or Stop
mode).
33911
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WINDOW OPEN
FOR WATCHDOG
CLEAR
While in Stop mode, the 33911 can wake-up when the RST
pin is held low long enough to pass the internal glitch filter.
Then, the 33911 will change to Normal Request or Normal
modes depending on the WDCONF pin configuration. The
RST wake-up does not generate an interrupt and is not
reported via SPI.
From Stop mode, the following wake-up events can be
configured:
WD TIMING X 50%
WD TIMING X 50%
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
WD PERIOD (t
)
PWD
WD TIMING SELECTED BY RESISTOR
ON WDCONF PIN
• RST wake-up
Figure 15. Window Watchdog Operation
From Sleep mode, the following wake-up events can be
configured:
To disable the watchdog function in Normal mode the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset mode.
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the Watchdog Status Register (WDSR).
• LIN wake-up
WINDOW WATCHDOG
The 33911 includes a configurable window watchdog which
is active in Normal mode. The watchdog can be configured by
an external resistor connected to the WDCONF pin. The
resistor is used to achieve higher precision in the timebase
used for the watchdog.
The watchdog timebase can be further divided by a prescaler
which can be configured by the Timing Control Register
(TIMCR). During Normal Request mode, the window
watchdog is not active but there is a 150 ms (typ.) timeout for
leaving the Normal Request mode. In case of a timeout, the
33911 will enter into Reset mode, resetting the
microcontroller before entering again into Normal Request
mode.
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33911 will reset the MCU, in the
same way as when the watchdog overflows.
FAULTS DETECTION MANAGEMENT
The 33911 has the capability to detect faults like an over or
under-voltage on VS1, TxD in permanent Dominant State,
Over-temperature on HS, LIN. It is able to take corrective
actions accordingly. Most of faults are monitoring through
SPI and the Interrupt pin. The microcontroller can also take
actions.
The following table summarizes all fault sources the device is
able to detect with associated conditions. The status for a
device recovery and the SPI or pins monitoring are also
described.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 6. Fault Detection Management Conditions
MONITORING(65)
BLOCK
FAULT
MODE
CONDITION
FALLOUT
RECOVERY
REG (FLAG,
INTERRUPT
BIT)
V
<3.0 V (typ)
SUP
All modes
-
Condition gone
VSR (BATFAIL, 0)
-
BATTERY FAIL
then power-up
In Normal mode, HS
and LS shutdown if
bit HVSE=1 (reg
MCR)
Condition gone, to
re-enable HS or LS
write to HSCR or
LSCR registers
IRQ low +
VSUP OVER-
VOLTAGE
V
> 19.25 V (typ)
< 6.0 V (typ)
VSR (VSOV,3)
SUP
SUP
(66)
ISR (0101)
Normal, Normal
Request
IRQ low + ISR
(0101)
VSUP UNDER-
VOLTAGE
V
V
-
VSR (VSUV,2)
Power Supply
VDD UNDER-
VOLTAGE
(64)
All except Sleep
< 4.5 V (typ)
Reset
-
-
DD
Condition gone
Temperature >
115°C (typ)
IRQ low + ISR
(0101)
VDD OVER-TEMP
PREWARNING
-
VSR (VDDOT,1)
-
All except Low
Power modes
Temperature >
170°C (typ)
VDD shutdown,
Reset then Sleep
VDD OVER-
TEMPERATURE
-
RXD pin shorted to
GND or 5 V
LINSR,
(RXSHORT,3)
RXD PIN SHORT
CIRCUIT
LIN trans shutdown
LIN transmitter re-
enabled once the
conditionisgoneand
TXD is high
TXD PIN
PERMANENT
DOMINANT
Normal, Normal
Request
TXD pin low for more
than 1s (typ)
IRQ low + ISR
(0100)
LIN
LINSR (TXDOM,2)
LINSR (LINOT,1)
(66)
LIN transmitter
shutdown
Temperature >
160°C (typ)
LIN DRIVER OVER-
TEMPERATURE
Condition gone, to
re-enable HS1 write
to HSCR reg
HIGH SIDE DRIVER
OVER-
TEMPERATURE
Temperature >
160°C (typ)
HS1 thermal
shutdown
All flags in HSSR
are set
IRQ low + ISR
(0010)
(66)
Current through HS1
< 5.0 mA (typ)
HS1 OPEN-LOAD
DETECTION
Normal, Normal
Request
-
HSSR (HS1OP,1)
HSSR (HS1CL,0)
High Side
Condition gone
-
Current through HS1
tends to rise above
the current limit
60 mA (min)
HS1 on with limited
current capability
60 mA (min)
HS1 OVER-
CURRENT
Condition gone, to
re-enable LS write to
LSCR reg
LOW SIDE DRIVERS
OVER-
TEMPERATURE
Temperature >
160°C (typ)
Both LS thermal
shutdown
All flags in LSSR are IRQ low + ISR
(66)
set
(0011)
LSSR (LS1OP,1)
LSSR (LS2OP,3)
LSSR (LS1CL,0)
LS1 OPEN-LOAD
LS2 OPEN-LOAD
LS1 OVER-CURRENT
Current through LSx
< 7.5 mA (typ)
Normal, Normal
Request
-
Low Side
-
-
Current through LSx
tends to rise above
the current limit
LSx on with limited
current capability
160 mA (min)
LSSR (LS2CL,2)
LS2 OVER-CURRENT
160 mA (min)
The MCU did not
command the device
to Normal mode
within the 150 ms
timeout after reset
NORMAL REQUEST
TIME-OUT EXPIRED
Normal Request
Reset
Reset
-
-
Watchdog
WD timeout or WD
clear within the
window closed
-
WATCHDOG
TIMEOUT
Normal
Normal
WDSR (WDTO, 3)
WDSR (WDERR, 2)
WD internal lower
precision timebase
150 ms (typ)
Connect WDCONF
to a resistor or to
GND
WDCONF pin is
floating
WATCHDOG ERROR
Notes
64. When in Reset mode a VDD under-voltage condition combined with no V
under-voltage (VSUV=0) will send the device to Sleep mode.
SUP
65. Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop
modes
66. Unless masked, If masked IRQ remains high and the ISR flags are not set.
33911
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
The graph below illustrates the internal chip temp sense
obtained per characterization at 3 temperatures with 3
different lots and 30 samples.
TEMPERATURE SENSE GAIN
The analog multiplexer can be configured via SPI to allow the
ADOUT0 pin to deliver the internal junction temperature of
the device.
Temperature Sense Analog Output Voltage
5
4.5
4
3.5
3
2.5
2
-50
0
50
100
150
Temperature (°C)
Figure 16. Temperature Sense Gain
The high side switch is controlled by the bit HS1 in the High
Side Control Register (HSCR).
HIGH SIDE OUTPUT PINS HS1
This output is one high side driver intended to drive small
resistive loads or LEDs incorporating the following features:
PWM Capability (direct access)
• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
The high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If the bit HS1 and PWMHS1 are set in the High Side Control
Register (HSCR), then the HS1 driver is turned on if the
PWMIN pin is high and turned of if the PWMIN pin is low.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Interrupt
Control
VDD
HVSE
VDD
Module
PWMIN
PWMHS1
VS2
MOD1:2
HS1
High Side Driver
charge pump
open load detection
on/off
Control
current limitation
over-temperture shutdown (interrupt maskable)
high voltage shutdown (maskable)
HS1OP
Status
HS1CL
HS1
Wakeup
Module
Figure 17. High Side Drivers HS1
Open Load Detection
High-voltage Shutdown
The high side driver signals an open load condition if the
current through the high side is below the open load current
threshold.
In case of a high voltage condition and if the high voltage
shutdown is enabled (bit HVSE in the Mode Control Register
(MCR) is set the high side driver is shut down.
The open load condition is indicated with the bit HS1OP in the
High Side Status Register (HSSR).
A write to the High Side Control Register (HSCR), when the
high voltage condition is gone, will re-enable the high side
driver.
Current Limitation
Sleep And Stop Mode
The high side driver has an output current limitation. In
combination with the over-temperature shutdown the high-
side driver is protected against over-current and short-circuit
failures.
The high side driver can be enabled to operate in Sleep and
Stop mode for cyclic sensing. Also see Table 5,
Operating Modes Overview.
When the driver operates in the current limitation area, it is
indicated with the bit HS1CL in the HSSR.
LOW SIDE OUTPUT PINS LS1 AND LS2
Note: If the driver is operating in current limitation mode,
excessive power might be dissipated.
These outputs are two low side drivers intended to drive
relays incorporating the following features:
• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• Active clamp (for driving relays)
• High-voltage shutdown (software maskable)
Over-temperature Protection (HS Interrupt)
The high side driver is protected against over-temperature. In
case of an over-temperature condition, the high side driver is
shut down and the event is latched in the Interrupt Control
Module. The shutdown is indicated as HS Interrupt in the
Interrupt Source Register (ISR).
The low side switches are controlled by the bit LS1:2 in the
Low Side Control Register (LSCR).
A thermal shutdown of the high side driver is indicated by
setting the HS1OP and HS1CL bits simultaneously.
To protect the device against over-voltage when an inductive
load (relay) is turned off. An active clamp will re-enable the
low side FET if the voltage on the LS1 or LS2 pin exceeds a
certain level.
If the bit HSM is set in the Interrupt Mask Register (IMR), then
an interrupt (IRQ) is generated.
A write to the High Side Control Register (HSCR), when the
over-temperature condition is gone, will re-enable the high
side driver.
33911
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
PWM Capability (direct access)
If both the bits LS1 and PWMLS1 are set in the Low Side
Control Register (LSCR), then the LS1 driver is turned on if
the PWMIN pin is high and turned off if the PWMIN pin is low.
The same applies to the LS2 and PWMLS2 bits for the LS2
driver.
Each low side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
VDD
Interrupt
Control
VDD
HVSE
Module
PWMIN
PWMLSx
active
clamp
LSx
MOD1:2
Low Side Driver
(active clamp)
Open-load Detection
on/off
LSx
Control
Current Limitation
Over-temperture Shutdown (interrupt maskable)
High-voltage shutdown (maskable)
LSxOP
LSxCL
Status
PGND
Figure 18. Low Side Drivers LS1 and LS2
Open Load Detection
A write to the Low Side Control Register (LSCR), when the
high-voltage condition is gone, will re-enable the low side
drivers.
Each low side driver signals an open load condition if the
current through the low side is below the open load current
threshold.
Sleep And Stop Mode
The open load condition is indicated with the bit LS1OP and
LS2OP in the Low Side Status Register (LSSR).
The low side drivers are disabled in Sleep and Stop mode.
Also see Table 5, Operating Modes Overview.
Current Limitation
LIN PHYSICAL LAYER
Each low side driver has a current limitation. In combination
with the over-temperature shutdown the low side drivers are
protected against over-current and short-circuit failures.
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification
and has the following features:
When the drivers operate in current limitation, this is indicated
with the bits LS1CL and LS2CL in the LSSR.
• LIN physical layer 2.0, 2.1 and SAEJ2602 compliant
• Slew rate selection
Note: If the drivers are operating in current limitation mode
excessive power might be dissipated.
• Over-temperature shutdown
• Advanced diagnostics
Over-temperature Protection (LS Interrupt)
Both low side drivers are protected against over-temperature.
In case of an over-temperature condition both low side
drivers are shut down and the event is latched in the Interrupt
Control Module. The shutdown is indicated as an LS Interrupt
in the Interrupt Source Register (ISR).
The LIN driver is a low side MOSFET with thermal shutdown.
An internal pull-up resistor with a serial diode structure is
integrated, so no external pull-up components are required
for the application in a slave node. The fall time from
dominant to recessive and the rise time from recessive to
dominant is controlled. The symmetry between both slopes is
guaranteed.
If the bit LSM is set in the Interrupt Mask Register (IMR) then
an Interrupt (IRQ) is generated.
A write to the Low Side Control Register (LSCR), when the
over-temperature condition is gone, will re-enable the low
side drivers.
LIN Pin
The LIN pin offers a high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
High-voltage Shutdown
In case of a high-voltage condition and if the high-voltage
shutdown is enabed (bit HVSE in the Mode Control Register
(MCR) is set both low sides drivers are shut down.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
WAKE-UP
MODULE
LIN
Wake-up
MOD1:2
LSR0:1
VS1
LIN DRIVER
J2602
RXONLY
RXSHORT
TXDOM
LINOT
Slope and Slew Rate Control
Over-temperature Shutdown (interrupt maskable)
30 K
LIN
TXD
SLOPE
CONTROL
LGND
WAKE-UP
FILTER
RXD
RECEIVER
Figure 19. LIN Interface
Slew Rate Selection
Over-temperature Shutdown (LIN Interrupt)
The slew rate can be selected for optimized operation at 10.4
and 20 kBit/s as well as a fast baud rate for test and
programming. The slew rate can be adapted with the bits
LSR1:0 in the LIN Control Register (LINCR). The initial slew
rate is optimized for 20 kBit/s.
The output low side FET is protected against over-
temperature conditions. In case of an over-temperature
condition, the transmitter will be shut down and the LINOT bit
in the LIN Status Register (LINSR) is set.
If the LINM bit is set in the Interrupt Mask Register (IMR), an
Interrupt IRQ will be generated.
J2602 Conformance
The transmitter is automatically re-enabled once the
condition is gone and TXD is high.
To be compliant with the SAE J2602-2 specification, the
J2602 feature has to be enabled in the LINCR Register (bit
DIS_J2602 sets to 0). The LIN transmitter is disabled in case
of a VSUP under-voltage condition occurs and TXD is in
Recessive State: the LIN bus goes in Recessive State and
RXD goes high. The LIN transmitter is not disabled if TXD is
in Dominant State. A deglitcher on Vsup (tJ2602_DEG) is
implemented to avoid false switching.
RXD Short-circuit Detection (LIN Interrupt)
The LIN transceiver has a short-circuit detection for the RXD
output pin. If the device transmits and in case of a short-
circuit condition, either 5.0 V or Ground, the RXSHORT bit in
the LIN Status Register (LINSR) is set and the transmitter is
shut down.
If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled
and the communication TXD-LIN-RXD works for VSUP down
to 4.6 V (typical value) and then the communication is
interrupted.
If the LINM bit is set in the Interrupt Mask Register (IMR), an
Interrupt IRQ will be generated.
The transmitter is automatically re-enabled once the
condition is gone (transition on RXD) and TXD is high.
The (DIS_J2602) bit is set per default to 0.
A read of the LIN Status Register (LINSR) without the RXD
pin short-circuit condition will clear the bit RXSHORT.
33911
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
TXD Dominant Detection (LIN Interrupt)
STOP Mode And Wake-up Feature
The LIN transceiver monitors the TXD input pin to detect a
stuck in dominant (0 V) condition. In case of a stuck condition
(TXD pin 0 V for more than 1 second (typ.)), the transmitter is
shut down and the TXDOM bit in the LIN Status Register
(LINSR) is set.
During Stop mode operation, the transmitter of the physical
layer is disabled. The receiver is still active and able to detect
wake-up events on the LIN bus line.
A dominant level longer than TPROPWL followed by a rising
edge will generate a wake-up interrupt, and will be reported
in the Interrupt Source Register (ISR). Also see Figure 11.
If the LINM bit is set in the IMR, an Interrupt IRQ will be
generated.
SLEEP Mode And Wake-up Feature
The transmitter is automatically re-enabled once TXD is high.
A read of the LIN Status Register (LINSR) with the TXD pin
at 5.0 V will clear the bit TXDOM.
During Sleep mode operation, the transmitter of the physical
layer is disabled. The receiver must be active to detect wake-
up events on the LIN bus line.
LIN Receiver Operation Only
A dominant level longer than TPROPWL followed by a rising
edge will generate a system wake-up (Reset), and will be
reported in the Interrupt Source Register (ISR). Also see
Figure 10.
While in Normal mode, the activation of the RXONLY bit
disables the LIN TXD driver. In case of a LIN error condition,
this bit is automatically set. If Stop mode is selected with this
bit set, the LIN wake-up functionality is disabled and the RXD
pin will reflect the state of the LIN bus.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
• MISO—Master-in Slave-out
• SCLK—Serial Clock
33911 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between a microcontroller (master) and the 33911.
A complete data transfer via the SPI consists of 1 byte. The
master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
information (S3:S0).
The interface consists of four pins (see Figure 20):
•
CS—Chip Select
• MOSI—Master-out Slave-in
CS
Register Write Data
A0 C3 C2
MOSI
MISO
A3
A2
A1
C1
C0
S0
Register Read Data
VMS LINS HSS LSS S3
S2
S1
SCLK
Read Data Latch
Write Data Latch
Rising: 33911 changes MISO/
MCU changes MOSI
Falling: 33911 samples MOSI/
MCU samples MISO
Figure 20. SPI Protocol
During the inactive phase of the CS (HIGH), the new data
transfer is prepared.
The rising edge of the Chip Select CS indicates the end of the
transfer and latches the write data (MOSI) into the register.
The CS high forces MISO to the high-impedance state.
The falling edge of the CS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
Register reset values are described along with the reset
condition. Reset condition is the condition causing the bit to
be set to its reset value. The main reset conditions are:
With the rising edge of the SPI clock (SCLK), the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock (SCLK), the data is sampled by the receiver.
- Power-On Reset (POR): the level at which the logic is reset
and BATFAIL flag sets.
The data transfer is only valid if exactly 8 sample clock edges
are present during the active (low) phase of CS.
- Reset mode
- Reset done by the RST pin (ext_reset)
33911
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
Table 7. System Status Register
BIT
Adress(A3:A0)
Register Name / Read/Write Information
SYSSR - System Status Register
7
6
5
4
$0 - $F
R
VMS
LINS
HSS
LSS
Table 8 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 8. SPI Register Overview
BIT
Adress(A3:A0)
Register Name / Read/Write Information
3
2
0
1
0
MOD1
BATFAIL
BATFAIL
L1WE
L1
MCR - Mode Control Register
VSR - Voltage Status Register
VSR - Voltage Status Register
WUCR - Wake-up Control Register
WUSR - Wake-up Status Register
WUSR - Wake-up Status Register
LINCR - LIN Control Register
W
R
HVSE
MOD2
VDDOT
VDDOT
L2WE
L2
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
VSOV
VSUV
VSUV
0
R
VSOV
W
R
0
-
-
R
-
-
L2
L1
W
R
DIS_J2602
RXSHORT
RXSHORT
0
RXONLY
TXDOM
TXDOM
PWMHS1
-
LSR1
LINOT
LINOT
0
LSR0
0
LINSR - LIN Status Register
LINSR - LIN Status Register
R
0
HSCR - High Side Control Register
HSSR - High Side Status Register
HSSR - High Side Status Register
LSCR - Low Side Control Register
LSSR - Low Side Status Register
LSSR - Low Side Status Register
W
R
HS1
-
HS1OP
HS1OP
LS2
HS1CL
HS1CL
LS1
R
-
-
W
R
PWMLS2
LS2OP
LS2OP
PWMLS1
LS2CL
LS2CL
WD2
LS1OP
LS1OP
WD1
LS1CL
LS1CL
WD0
CYST0
WDWO
WDWO
MX0
R
TIMCR - Timing Control Register
W
CS/WD
$A
CYST2
WDERR
WDERR
MX2
CYST1
WDOFF
WDOFF
MX1
WDSR - Watchdog Status Register
WDSR - Watchdog Status Register
AMUXCR - Analog Multiplexer Control Register
CFR - Configuration Register
R
R
WDTO
WDTO
LXDS
0
$B
$C
$D
W
W
W
R
CYSX8
LSM
0
0
IMR - Interrupt Mask Register
HSM
ISR3
ISR3
LINM
ISR1
VMM
ISR0
ISR0
$E
$F
ISR - Interrupt Source Register
ISR2
ISR - Interrupt Source Register
R
ISR2
ISR1
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
REGISTER DEFINITIONS
System Status Register - SYSSR
HS1CL
HS1OP
HSS
The System Status Register (SYSSR) is always transferred
with every SPI transmission and gives a quick system status
overview. It summarizes the status of the Voltage Monitor
Status (VMS), LIN Status (LINS), High Side Status (HSS),
and the Low Side Status (LSS).
Figure 23. High Side Status
LSS - Low Side Switch Status
Table 9. System Status Register
S7
S6
S5
S4
This read-only bit indicates that one or more bits in the LSSR
are set.
Read
VMS
LINS
HSS
LSS
1 = Low Side Status bit set
0 = None
VMS - Voltage Monitor Status
This read-only bit indicates that one or more bits in the VSR
are set.
LS1CL
1 = Voltage Monitor bit set
0 = None
LS1OP
LSS
LS2CL
LS2OP
BATFAIL
Figure 24. Low Side Status
Mode Control Register - MCR
VDDOT
VMS
VSUV
VSOV
The Mode Control Register (MCR) allows switching between
the operation modes and to configure the 33911. Writing the
MCR will return the VSR.
Figure 21. Voltage Monitor Status
Table 10. Mode Control Register - $0
LINS - LIN Status
This read-only bit indicates that one or more bits in the LINSR
are set.
C3
C2
C1
C0
Write
HVSE
0
MOD2
MOD1
1 = LIN Status bit set
0 = None
Reset
Value
1
0
-
-
-
-
Reset
Condition
POR
POR
LINOT
LINS
TXDOM
HVSE - High-Voltage Shutdown Enable
This write-only bit enables/disables automatic shutdown of
the high side and the low side drivers during a high-voltage
VSOV condition.
RXSHORT
Figure 22. LIN Status
1 = automatic shutdown enabled
0 = automatic shutdown disabled
HSS - High Side Switch Status
This read-only bit indicates that one or more bits in the HSSR
are set.
MOD2, MOD1 - Mode Control Bits
These write-only bits select the operating mode and allow
clearing the watchdog in accordance with Table 7 Mode
Control Bits.
1 = High Side Status bit set
0 = None
33911
Analog Integrated Circuit Device Data
40
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Wake-up Control Register - WUCR
Table 11. Mode Control Bits
This register is used to control the digital wake-up inputs.
Writing the WUCR will return the Wake-up Status Register
(WUSR).
MOD2
MOD1
Description
0
0
1
1
0
1
0
1
Normal mode
Stop mode
Table 13. Wake-up Control Register - $2
Sleep mode
C3
C2
C1
C0
Normal mode + Watchdog Clear
Write
0
0
L2WE
L1WE
Voltage Status Register - VSR
Reset
Value
1
1
1
1
Returns the status of the several voltage monitors. This
register is also returned when writing to the Mode Control
Register (MCR).
Reset
Condition
POR, Reset mode or ext_reset
Table 12. Voltage Status Register - $0/$1
LxWE - Wake-up Input x Enable
S3
S2
S1
S0
This write-only bit enables/disables which Lx inputs are
enabled. In Stop and Sleep mode the LxWE bit determines
which wake inputs are active for wake-up. If one of the Lx
inputs is selected on the analog multiplexer, the
corresponding LxWE is masked to 0.
Read
VSOV
VSUV
VDDOT
BATFAIL
VSOV - VSUP Over-voltage
This read-only bit indicates an over-voltage condition on the
VS1 pin.
1 = Wake-up Input x enabled.
0 = Wake-up Input x disabled.
1 = Over-voltage condition.
0 = Normal condition.
Wake-up Status Register - WUSR
This register is used to monitor the digital wake-up inputs and
is also returned when writing to the WUCR.
VSUV - VSUP Under-voltage
This read-only bit indicates an under-voltage condition on the
VS1 pin.
Table 14. Wake-up Status Register - $2/$3
1 = Under-voltage condition.
0 = Normal condition.
S3
S2
S1
S0
Read
-
-
L2
L1
VDDOT - Main Voltage Regulator Over-temperature
Warning
Lx - Wake-up input x
This read-only bit indicates that the main voltage regulator
temperature reached the Over-temperature Prewarning
Threshold.
This read-only bit indicates the status of the corresponding Lx
input. If the Lx input is not enabled, then the according Wake-
up status will return 0.
1 = Over-temperature Prewarning
0 = Normal
After a wake-up from Stop or Sleep mode these bits also
allow to determine which input has caused the wake-up, by
first reading the Interrupt Status Register (ISR) and then
reading the WUSR. The source of the wake-up is only
reported on the first WUCR or WUSR access.
BATFAIL - Battery Fail Flag.
This read-only bit is set during power-up and indicates that
the 33911 had a Power-On-Reset (POR).
1 = Lx pin high, or Lx is the source of the wake-up.
0 = Lx pin low, disabled or selected as an analog input.
Any access to the MCR or VSR will clear the BATFAIL flag.
1 = POR Reset has occurred
LIN Control Register - LINCR
0 = POR Reset has not occurred
This register controls the LIN physical interface block. Writing
the LIN Control Register (LINCR) returns the LIN Status
Register (LINSR).
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
RXSHORT - RXD Pin Short-circuit
Table 15. LIN Control Register - $4
This read-only bit indicates a short-circuit condition on the
RXD pin (shorted either to 5.0 V or to Ground). The short-
circuit delay must be a worst case of 8µs to be detected and
to shut down the driver. To clear this bit, it must be read after
the condition is gone (transition detected on RXD pin). The
LIN driver is automatically re-enabled once the condition is
gone and TXD is high.
C3
C2
C1
C0
Write
DIS_J2602
RXONLY
LSR1
LSR0
Reset
Value
0
0
0
0
1 = RXD short-circuit condition.
0 = None.
POR, Reset
mode, ext_reset
or LIN failure
gone*
Reset
Condition
POR
POR
TXDOM - TXD Permanent Dominant
* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set,
the flag resets automatically when the failure is gone.
This read-only bit signals the detection of a TXD pin stuck at
dominant (Ground) condition and the resultant shutdown in
the LIN transmitter. This condition is detected after the TXD
pin remains in dominant state for more than 1 second (typical
value).
J2602 - LIN Dominant Voltage Select
This write-only bit controls the J2602 circuitry. If the circuitry
is enabled (bit sets to 0), the TXD-LIN-RXD communication
works down to the battery under-voltage condition is
detected. Below, the bus is in recessive state. If the circuitry
is disabled (bit sets to 1), the communication TXD-LIN-RXD
works down to 4.6 V (typical value).
To clear this bit, it must be read after TXD has gone high. The
LIN driver is automatically re-enabled once TXD goes High.
1 = TXD stuck at dominant fault detected.
0 = None.
LINOT - LIN Driver Over-temperature
0 = Enabled J2602 feature.
1 = Disabled J2602 feature.
This read-only bit signals that the LIN transceiver was
shutdown due to over-temperature. The transmitter is
automatically re-enabled after the over-temperature
condition is gone and TXD is high. The LINOT bit is cleared
after SPI read once the condition is gone.
RXONLY - LIN Receiver Operation Only
This write-only bit controls the behavior of the LIN transmitter.
In Normal mode, the activation of the RXONLY bit disables
the LIN transmitter. In case of a LIN error condition, this bit is
automatically set.
1 = LIN over-temperature shutdown
0 = None
In Stop mode this bit disables the LIN wake-up functionality,
and the RXD pin will reflect the state of the LIN bus.
High Side Control Register - HSCR
This register controls the operation of the high side driver.
Writing to this register returns the High Side Status Register
(HSSR).
1 = only LIN receiver active (Normal mode) or LIN wake-up
disabled (Stop mode).
0 = LIN fully enabled.
Table 18. High Side Control Register - $6
LSRx - LIN Slew-Rate
C3
C2
C1
C0
This write-only bit controls the LIN driver slew-rate in
accordance with Table 16.
Write
0
PWMHS1
0
HS1
Table 16. LIN Slew Rate Control
Reset
Value
0
0
0
0
LSR1
LSR0
Description
0
0
1
1
0
1
0
1
Normal Slew Rate (up to 20 kb/s)
Slow Slew Rate (up to 10 kb/s)
Fast Slew Rate (up to 100 kb/s)
Reserved
Reset
Condition
POR, Reset mode, ext_reset, HS1
over-temp or (VSOV & HVSE)
POR
PWMHS1 - PWM Input Control Enable.
This write-only bit enables/disables the PWMIN input pin to
control the high side switch. The high side switch must be
enabled (HS1 bit).
LIN Status Register - LINSR
This register returns the status of the LIN physical interface
block and is also returned when writing to the LINCR.
1 = PWMIN input controls HS1 output.
0 = HS1 is controlled only by SPI.
Table 17. LIN Status Register - $4/$5
HS1 - HS1 Switch Control.
S3
S2
S1
S0
This write-only bit enables/disables the high side switch.
1 = HS1 switch on.
Read
RXSHORT
TXDOM
LINOT
0
0 = HS1 switch off.
33911
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Status Register - HSSR
1 = PWMIN input controls LSx.
0 = LSx is controlled only by SPI.
This register returns the status of the high side switch and is
also returned when writing to the HSCR.
LSx - LSx switch control.
Table 19. High Side Status Register - $6/$7
This write-only bit enables/disables the corresponding low
side switch.
S3
S2
S1
S0
1 = LSx switch on.
0 = LSx switch off.
Read
-
-
HS1OP
HS1CL
Low Side Status Register - LSSR
High Side thermal shutdown
This register returns the status of the low side switches and
is also returned when writing to the LSCR.
A thermal shutdown of the high side driver is indicated by
setting the HS1OP and HS1CL bits simultaneously.
Table 21. Low Side Status Register - $8/$9
HS1OP - High Side Switch Open-Load Detection
C3
C2
C1
C0
This read-only bit signals that the high side switch is
conducting current below a certain threshold indicating
possible load disconnection.
Read
LS2OP
LS2CL
LS1OP
LS1CL
1 = HS1 Open Load detected (or thermal shutdown)
0 = Normal
Low Side thermal shutdown
A thermal shutdown of the low side drivers is indicated by
setting all LSxOP and LSxCL bits simultaneously.
HS1CL - High Side Current Limitation
This read-only bit indicates that the high side switch is
operating in current limitation mode.
LSxOP - Low Side Switch Open-Load Detection
1 = HS1 in current limitation (or thermal shutdown)
0 = Normal
This read-only bit signals that the low side switches are
conducting current below a certain threshold indicating
possible load disconnection.
Low Side Control Register - LSCR
1 = LSx Open Load detected (or thermal shutdown)
0 = Normal
This register controls the operation of the low side drivers.
Writing the Low Side Control Register (LSCR) will also return
the Low Side Status Register (LSSR).
LSxCL - Low Side Current Limitation
This read-only bit indicates that the respective low side switch
is operating in current limitation mode.
Table 20. Low Side Control Register - $8
1 = LSx in current limitation (or thermal shutdown)
0 = Normal
C3
C2
C1
C0
Write
PWMLS2 PWMLS1
LS2
LS1
Timing Control Register - TIMCR
Reset
Value
0
0
0
0
This register allows to configure the watchdog, the cyclic
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
Reset
Condition
POR, Reset mode, ext_reset, LSx
over-temp or (VSOV & HVSE)
POR
PWMLx - PWM input control enable.
This write-only bit enables/disables the PWMIN input pin to
control the respective low side switch. The corresponding low
side switch must be enabled (LSx bit).
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Table 22. Timing Control Register - $A
Table 24. Cyclic Sense and Force Wake-up Interval
CYSX8(67) CYST2
CYST1
CYST0
Interval
C3
C2
C1
C0
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No cyclic sense(68)
20 ms
WD2
WD1
WD0
Write
CS/WD
0
CYST2
CYST1
CYST0
0
40 ms
Reset
Value
0
60 ms
-
-
0
0
0
0
80 ms
Reset
Condition
0
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
1120 ms
POR
0
0
CS/WD - Cyclic Sense or Watchdog prescaler select
1
This write-only bit selects which prescaler is being written to
the Cyclic Sense/Forced Wake-up prescaler or the Watchdog
prescaler.
1
1
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
1
1
WDx - Watchdog Prescaler
1
1
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 23. This configuration is valid only if
windowing watchdog is active.
Notes
67. bit CYSX8 is located in Configuration Register (CFR)
68. No Cyclic Sense and no Force Wake up available.
Table 23. Watchdog Prescaler
Watchdog Status Register - WDSR
WD2
WD1
WD0
Prescaler Divider
This register returns the Watchdog status information and is
also returned when writing to the TIMCR.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
Table 25. Watchdog Status Register - $A/$B
4
S3
S2
S1
S0
6
Read
WDTO
WDERR WDOFF
WDWO
8
10
12
14
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by either
a watchdog timeout or by an attempt to clear the Watchdog
within the window closed.
CYSTx - Cyclic Sense Period Prescaler Select
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
This write-only bits selects the interval for the wake-up cyclic
sensing together with the bit CYSX8 in the Configuration
Register (CFR) (see Configuration Register - CFR on page
45).
1 = Last reset caused by watchdog timeout
0 = None
This option is only active if the high side switch is enabled
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in Table 24.
WDERR - Watchdog Error
This read-only bit signals the detection of a missing watchdog
resistor. In this condition the watchdog is using the internal,
lower precision timebase. The Windowing function is
disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
33911
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WDOFF - Watchdog Off
Configuration Register - CFR
This read-only bit signals that the watchdog pin connected to
Ground and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
This register controls the cyclic sense timing multiplier.
Table 28. Configuration Register - $D
C3
C2
C1
C0
1 = Watchdog is disabled
0 = Watchdog is enabled
Write
0
CYSX8
0
0
Reset
Value
0
0
0
0
WDWO - Watchdog Window Open
This read-only bit signals when the watchdog window is open
for clears. The purpose of this bit is for testing. Should be
ignored in case WDERR is High.
Reset
Condition
POR, Reset mode
or ext_reset
POR
POR
POR
1 = Watchdog window open
0 = Watchdog window closed
CYSX8 - Cyclic Sense Timing x 8.
This write-only bit influences the cyclic sense and Forced
Wake-up period as shown in Table 24.
Analog Multiplexer Control Register - MUXCR
1 = Multiplier enabled
0 = None
This register controls the analog multiplexer and selects the
divider ration for the Lx input divider.
Interrupt Mask Register - IMR
Table 26. Analog Multiplexer Control Register -$C
This register allows masking of some of the interrupt sources.
No interrupt will be generated to the MCU and no flag will be
set in the ISR register. The 5.0V Regulator over-temperature
prewarning interrupt and Under-voltage (VSUV) interrupts
can not be masked and will always cause an interrupt.
C3
LXDS
1
C2
MX2
0
C1
MX1
0
C0
MX0
0
Write
Reset Value
Reset Condition
Writing to the IMR will return the ISR.
POR
POR, Reset mode or ext_reset
Table 29. Interrupt Mask Register - $E
LXDS - Lx Analog Input Divider Select
C3
HSM
1
C2
LSM
1
C1
LINM
1
C0
VMM
1
This write-only bit selects the resistor divider for the Lx analog
inputs. Voltage is internally clamped to VDD.
Write
Reset Value
Reset Condition
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)
POR
MXx - Analog Multiplexer Input Select
HSM - High Side Interrupt Mask
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 27.
This write-only bit enables/disables interrupts generated in
the high side block.
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
Table 27. Analog Multiplexer Channel Select
LSM - Low Side Interrupt Mask
MX2
MX1
MX0
Meaning
This write-only bit enables/disables interrupts generated in
the low side block.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Reserved
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
Die Temperature Sensor
VSENSE input
L1 input
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
L2 input
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
Reserved
Reserved
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
MC33911G5AC/MC3433911G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
VMM - Voltage Monitor Interrupt Mask
This register is also returned when writing to the Interrupt
Mask Register (IMR).
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the VSUP over-voltage interrupt.
Table 30. Interrupt Source Register - $E/$F
1 = Interrupts Enabled
0 = Interrupts Disabled
S3
S2
S1
S0
Read
ISR3
ISR2
ISR1
ISR0
Interrupt Source Register - ISR
ISRx - Interrupt Source Register
This register allows the MCU to determine the source of the
last interrupt or wake-up respectively. A read of the register
acknowledges the interrupt and leads IRQ pin to high, in case
there are no other pending interrupts. If there are pending
interrupts, IRQ will be driven high for 10µs and then be driven
low again.
These read-only bits indicate the interrupt source following
Table 31. If no interrupt is pending then all bits are 0.
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Table 31. Interrupt Sources
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
no interrupt
no interrupt
none
Lx Wake-up from Stop and Sleep mode
-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
LIN Interrupt (RXSHORT, TXDOM, LIN OT)
Voltage Monitor Interrupt
(High Voltage)
highest
-
-
LIN Wake-up
Voltage Monitor Interrupt
(Low Voltage and VDD over-temperature)
Forced Wake-up
0
1
1
0
-
lowest
33911
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
TYPICAL APPLICATION
TYPICAL APPLICATION
The 33911 can be configured in several applications. The
figure below shows the 33911 in the typical Slave Node
Application.
V
BAT
D1
C2
C1
VDD
Interrupt
Control Module
Voltage Regulator
IRQ
C4
C3
LVI, HVI, HTI, OCI
AGND
VDD
Reset
Control Module
LVR, HVR, HTR, WD,
LS1
RST
IRQ
Low Side Control
Module
HB Type Relay
LS2
RST
PGND
Window
R1
Motor Output
Watchdog Module
PWMIN
TIMER
High Side Control
Module
HS1
MISO
MOSI
SCLK
CS
Chip Temp Sense Module
VBAT Sense Module
SPI
&
CONTROL
SPI
VSENSE
MCU
R2
R3
L1
L2
Analog Input Module
ADOUT0
A/D
Wake Up Module
Digital Input Module
RXD
TXD
LIN Physical Layer
SCI
LIN
LIN
C5
Typical Component Values:
C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF
R1 = 10 k; R2 = R3 = 10 kR4 = 20 k-200 k
R4
Recommended Configuration of the not Connected Pins (NC):
Pin 15, 16, 20, 21 = GND
Pin 11, 30 = open (floating)
Pin 24 = open (floating) or VS2
Pin 28 = this pin is not internally connected and may be used for PCB routing
optimization.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
MC33911BAC / MC34911BAC
MC33911BAC PRODUCT SPECIFICATIONS PAGES 48 TO 88
MC33911BAC PRODUCT SPECIFICATIONS
PAGES 48 TO 88
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
MC33911BAC / MC34911BAC
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ
VS2
VS1
VDD
INTERRUPT
CONTROL
AGND
MODULE
LVI, HVI, HTI, OCI
VOLTAGE REGULATOR
RESET CONTROL
MODULE
LVR, HVR, HTR, WD
LS1
LOW SIDE
CONTROL
MODULE
WINDOW
WATCHDOG
MODULE
LS2
PGND
PWMIN
VS2
HIGH SIDE
CONTROL
MODULE
MISO
MOSI
SCLK
HS1
SPI
&
CONTROL
VBAT
SENSE MODULE
VSENSE
CS
CHIP TEMPERATURE
SENSE MODULE
ADOUT0
L1
ANALOG INPUT
MODULE
WAKE-UP MODULE
L2
DIGITAL INPUT MODULE
RXD
TXD
LIN PHYSICAL
LAYER
LIN
LGND
WDCONF
Figure 25. 33911BAC Simplified Internal Block Diagram
33911
Analog Integrated Circuit Device Data
49
Freescale Semiconductor
MC33911BAC / MC34911BAC
PIN CONNECTIONS
PIN CONNECTIONS
RXD
TXD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC*
L1
MISO
L2
MOSI
NC*
NC*
LS1
PGND
LS2
SCLK
CS
* Special Configuration Recommended /
Mandatory for Marked NC Pins
ADOUT0
PWMIN
Figure 26. 33911 Pin Connections
Table 32. 33911 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section.
Pin
Pin Name
Formal Name
Definition
This pin is the receiver output of the LIN interface which reports the state of
the bus voltage to the MCU interface.
1
RXD
Receiver Output
This pin is the transmitter input of the LIN interface which controls the state of
the bus output.
2
3
TXD
Transmitter Input
SPI Output
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the
high-impedance state.
MISO
SPI (Serial Peripheral Interface) data input.
SPI (Serial Peripheral Interface) clock Input.
SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
4
5
6
7
8
MOSI
SCLK
SPI Input
SPI Clock
CS
SPI Chip Select
Analog Output Pin 0
PWM Input
ADOUT0
PWMIN
High side and low side pulse-width modulation input.
Bidirectional reset I/O pin - driven low when any internal reset source is
asserted. RST is active low.
9
RST
IRQ
Internal Reset I/O
Interrupt output pin, indicating wake-up events from Stop mode or events from
Normal and Normal Request modes. IRQ is active low.
Internal Interrupt
Output
10
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
MC33911BAC / MC34911BAC
PIN CONNECTIONS
Table 32. 33911 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section.
Pin
Pin Name
Formal Name
Definition
This input pin is for configuration of the watchdog period and
allows the disabling of the watchdog.
Watchdog
Configuration Pin
12
WDCONF
This pin represents the single-wire bus transmitter and receiver.
13
14
LIN
LIN Bus
This pin is the device LIN ground connection. It is internally connected to the
PGND pin.
LGND
LIN Ground Pin
17
19
LS2
LS1
Relay drivers low side outputs.
Low Side Outputs
Power Ground Pin
This pin is the device low side ground connection. It is internally connected to
the LGND pin.
18
PGND
These pins are the wake-up capable digital inputs(69). In addition, all LX inputs
can be sensed analog via the analog multiplexer.
22
23
L2
L1
Wake-Up Inputs
High Side Output
Power Supply Pin
Voltage Sense Pin
High side switch output.
25
HS1
26
27
VS2
VS1
These pins are device battery level power supply pins. VS2 is supplying the
HS1 driver while VS1 supplies the remaining blocks.(70)
Battery voltage sense input. (71)
29
31
32
VSENSE
VDD
Voltage Regulator
Output
+5.0V main voltage regulator output pin. (72)
This pin is the device analog ground connection.
AGND
Analog Ground Pin
Notes
69. When used as a digital input, a series 33 k resistor must be used to protect against automotive transients.
70. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
71. This pin can be connected directly to the battery line for voltage measurements. The pin is self-protected against reverse battery
connections. It is strongly recommended to connect a 10 k resistor in series with this pin for protection purposes.
72. External capacitor (2.0 µF < C < 100 µF; 0.1< ESR < 10 ) required.
33911
Analog Integrated Circuit Device Data
51
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 33. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2
Normal Operation (DC)
V
V
-0.3 to 27
-0.3 to 40
SUP(SS)
VSUP(PK)
Transient Conditions (load dump)
Supply Voltage at VDD
VDD
-0.3 to 5.5
V
V
Input / Output Pins Voltage(73)
V
-0.3 to VDD +0.3
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD
IN
Interrupt Pin (IRQ)(74)
V
-0.3 to 11
-0.3 to VSUP +0.3
-0.3 to 45
IN(IRQ)
HS1 Pin Voltage (DC)
V
V
V
V
HS1
LS1 and LS2 Pin Voltage (DC)
V
LS
L1 and L2 Pin Voltage
V
-18 to 40
±100
Normal Operation with a series 33k resistor (DC)
LxDC
V
Transient input voltage with external component (according to ISO7637-2)
(See Figure 28)
LxTR
VSENSE Pin Voltage (DC)
VVSENSE
-27 to 40
V
V
LIN Pin Voltage
VBUSDC
VBUSTR
-18 to 40
Normal Operation (DC)
-150 to 100
Transient input voltage with external component (according to ISO7637-2)
(See Figure )
VDD output current
I
Internally Limited
A
V
VDD
ESD Voltage
V
V
±8000
±2000
±150
Human Body Model - LIN Pin(75)
Human Body Model - all other Pins(75)
Machine Model(76)
ESD1-1
ESD1-2
V
ESD2
Charge Device Model(77)
V
V
±750
±500
ESD3-1
ESD3-2
Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)
All other Pins (Pins 2-7, 10-15, 18-23, 26-31)
NC Pin Voltage (NC pins 11, 15, 16, 20, 21, 24, 28 and 30)(78)
VNC
Note 78
Notes
73. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
74. Extended voltage range for programming purpose only.
75. Testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500
ZAP
ZAP
76. Testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0
ZAP
ZAP
77. Testing is performed in accordance with the Charge Device Model, Robotic (C
= 4.0 pF
ZAP
78. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application shown on page 88.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
52
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 33. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
THERMAL RATINGS
Operating Ambient Temperature(79)
T
C
A
33911
34911
-40 to 125
-40 to 85
Operating Junction Temperature
Storage Temperature
T
-40 to 150
-55 to 150
C
C
J
TSTG
RJA
Thermal Resistance, Junction to Ambient
C/W
Natural Convection, Single Layer board (1s)(80), (81)
Natural Convection, Four Layer board (2s2p)(80), (82)
85
56
Thermal Resistance, Junction to Case(83)
Peak Package Reflow Temperature During Reflow(84), (85)
Notes
RJC
23
C/W
TPPRT
Note 85
°C
79. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.
80. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
81. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
82. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
83. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
84. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
85. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33911
Analog Integrated Circuit Device Data
53
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY VOLTAGE RANGE (VS1, VS2)
VSUP
5.5
–
–
–
–
18
27
40
V
V
V
Nominal Operating Voltage
Functional Operating Voltage(86)
Load Dump
VSUPOP
VSUPLD
–
SUPPLY CURRENT RANGE (VSUP = 13.5 V)
Normal Mode (IOUT at V
= 10 mA), LIN Recessive State(87)
IRUN
–
4.5
10
mA
µA
DD
Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State(87), (88), (89)
ISTOP
5.5 V < VSUP < 12 V
VSUP = 13.5 V
–
–
48
58
80
90
Sleep Mode, VDD OFF, LIN Recessive State(87), (89)
5.5 V < VSUP < 12 V
ISLEEP
µA
–
–
27
37
35
48
12 V VSUP < 13.5 V
Cyclic Sense Supply Current Adder(90)
ICYCLIC
–
10
–
µA
V
SUPPLY UNDER/OVER VOLTAGE DETECTIONS
Power-On Reset (BATFAIL)(91)
Threshold (measured on VS1)(90)
Hysteresis (measured on VS1)(90)
VBATFAIL
1.5
–
3.0
0.9
3.9
–
VBATFAIL_HYS
VSUP Under-voltage Detection (VSUV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
V
Threshold (measured on VS1)
Hysteresis (measured on VS1)
VSUV
VSUV_HYS
5.55
–
6.0
1.0
6.6
–
VSUP Over-voltage Detection (VSOV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
VSOV
VSOV_HYS
Threshold (measured on VS1)
Hysteresis (measured on VS1)
18
–
19.25
1.0
20.5
–
Notes
86. Device is fully functional. All features are operating.
87. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
88. Total IDD current (including loads) below 100 µA.
89. Stop and Sleep modes current will increase if VSUP exceeds 13.5 V.
90. This parameter is guaranteed by process monitoring but not production tested.
91. The flag is set during power-up sequence. To clear the flag, a SPI read must be performed.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
54
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
VOLTAGE REGULATOR(92) (VDD)
Normal Mode Output Voltage
1.0 mA < I < 50 mA; 5.5 V < V
Symbol
Min
Typ
Max
Unit
VDDRUN
V
< 27 V
SUP
4.75
60
5.00
110
5.25
200
VDD
Normal Mode Output Current Limitation
Dropout Voltage(93)
IVDDRUN
mA
V
VDDDROP
I
= 50 mA
–
0.1
0.25
VDD
Stop Mode Output Voltage
< 5.0 mA
V
V
DDSTOP
I
4.75
6.0
5.0
12
5.25
36
VDD
Stop Mode Output Current Limitation
Line Regulation
I
mA
mV
VDDSTOP
LR
Normal Mode, 5.5 V < V
Stop Mode, 5.5 V < V
< 18 V; I
= 10 mA
VDD
RUN
–
–
20
25
25
SUP
LR
STOP
< 18 V; I
= 1.0 mA
VDD
5.0
SUP
Load Regulation
mV
°C
LD
Normal Mode, 1.0 mA < I
Stop Mode, 0.1 mA < I
< 50 mA
RUN
–
–
15
10
80
50
VDD
LD
STOP
< 5.0 mA
VDD
Over-temperature Prewarning (Junction)(94)
Interrupt generated, Bit VDDOT Set
T
PRE
110
–
125
10
140
–
Over-temperature Prewarning hysteresis(94)
Over-temperature Shutdown Temperature (Junction)(94)
Over-temperature Shutdown hysteresis(94)
Notes
T
°C
°C
°C
PRE_HYS
T
155
–
170
10
185
–
SD
T
SD_HYS
92. Specification with external capacitor 2.0 µF < C < 100 µF and 100 m ESR 10
93. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).
94. This parameter is guaranteed by process monitoring but not production tested.
33911
Analog Integrated Circuit Device Data
55
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
RST INPUT/OUTPUT PIN (RST)
Symbol
Min
Typ
Max
Unit
VDD Low-Voltage Reset Threshold
VRSTTH
VOL
4.3
4.5
4.7
V
V
Low-state Output Voltage
IOUT = 1.5 mA; 3.5 V VSUP 27 V
0.0
–
0.9
High-state Output Current (0 < VOUT < 3.5 V)
IOH
-150
-250
-350
µA
Pull-down Current Limitation (internally limited)
VOUT = VDD
IPD_MAX
mA
1.5
-0.3
–
–
–
8.0
Low-state Input Voltage
High-state Input Voltage
VIL
VIH
0.3 x VDD
VDD +0.3
V
V
0.7 x VDD
MISO SPI OUTPUT PIN (MISO)
Low-state Output Voltage
VOL
V
V
I
= 1.5 mA
0.0
VDD -0.9
-10
–
–
–
1.0
VDD
10
OUT
High-state Output Voltage
IOUT = -250 µA
VOH
Tri-state Leakage Current
ITRIMISO
µA
0 V VMISO VDD
SPI INPUT PINS (MOSI, SCLK, CS)
Low-state Input Voltage
VIL
VIH
IIN
-0.3
–
–
0.3 x VDD
VDD +0.3
V
V
High-state Input Voltage
0.7 x VDD
MOSI, SCLK Input Current
µA
0 V VIN VDD
-10
10
–
10
30
CS Pull-up Current
0 V < VIN < 3.5 V
IPUCS
µA
20
INTERRUPT OUTPUT PIN (IRQ)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
VOH
VOH
V
V
0.0
VDD -0.8
–
–
–
–
0.8
VDD
2.0
High-state Output Voltage
IOUT = -250 µA
Leakage Current
mA
VDD VOUT V
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
Low-state Input Voltage
VIL
VIH
-0.3
–
–
0.3 x VDD
VDD +0.3
V
V
High-state Input Voltage
0.7 x VDD
Pull-up current
IPUPWMIN
µA
0 V < VIN < 3.5 V
10
20
30
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
56
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
HIGH SIDE OUTPUT HS1 PIN (HS1)
Symbol
Min
Typ
Max
Unit
Output Drain-to-Source On resistance
TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V
RDS(ON)
–
–
–
–
–
–
7.0
10
14
TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(95)
TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(95)
Output Current Limitation(96)
0 V < VOUT < VSUP - 2.0 V
ILIMHS1
mA
60
–
120
5.0
250
7.5
Open Load Current Detection(97)
IOLHS1
ILEAK
mA
µA
Leakage Current
-0.2 V < VHS1 < VS2 + 0.2 V
–
–
10
Short-circuit Detection Threshold(98)
5.5 V < VSUP < 27 V
VTHSC
V
VSUP -2
–
–
Over-temperature Shutdown(99), (104)
THSSD
150
–
165
10
180
–
°C
°C
Over-temperature Shutdown Hysteresis(104)
THSSD_HYS
LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2)
Output Drain-to-Source On resistance
RDS(ON)
–
–
–
–
–
–
2.5
4.5
10
TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V
TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V
TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V
Output Current Limitation (100)
2.0 V < VOUT < VSUP
ILIMLSX
mA
160
–
275
8.0
350
12
Open Load Current Detection(101)
IOLLSX
ILEAK
mA
µA
Leakage Current
-0.2 V < VOUT < VS1
–
–
–
–
10
VSUP +5
–
Active Output Energy Clamp
IOUT = 150 mA
VCLAMP
V
V
VSUP +2
Short-circuit Detection Threshold(102)
5.5 V < VSUP < 27 V
VTHSC
2.0
Over-temperature Shutdown(103), (104)
Over-temperature Shutdown Hysteresis(104)
Notes
TLSSD
150
–
165
10
180
–
°C
°C
TLSSD_HYS
95. This parameter is production tested up to TA = 125°C and guaranteed by process monitoring up to TJ = 150°C.
96. When over-current occurs, the High Side stays ON with limited current capability and the HS1CL flag is set in the HSSR
97. When open Load occurs, the flag (HS1OP) is set in the HSSR
98. When short-circuit occurs and if the HVSE flag is enabled, HS1 automatically shut down.
99. When over-temperature Shutdown occurs, the High Side is turned off. All flags in HSSR are set.
100. When over-current occurs, the corresponding Low Side stays ON with limited current capability and the LSxCL flag is set in the LSSR
101. When open load occurs, the flag (LSxOP) is set in the LSSR.
102. When short-circuit occurs and if the HVSE flag is enabled, both LS automatically shut down.
103. When over-temperature shutdown occurs, both Low Sides are turned off. All flags in LSSR are set.
104. Guaranteed by characterization but not production tested
33911
Analog Integrated Circuit Device Data
57
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
L1 AND L2 INPUT PINS (L1, L2)
Symbol
Min
Typ
Max
Unit
Low Detection Threshold
5.5 V < VSUP < 27 V
VTHL
VTHH
VHYS
IIN
V
V
2.0
3.0
0.5
2.5
3.5
1.0
3.0
4.0
1.5
High Detection Threshold
5.5 V < VSUP < 27 V
Hysteresis
V
5.5 V < VSUP < 27 V
Input Current(105)
-0.2 V < VIN < VS1
µA
k
-10
–
10
–
Analog Input Impedance(106)
RLxIN
800
1550
Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0
LXDS (Lx Divider Select) = 0
)
RATIOLx
0.95
3.42
1.0
3.6
1.05
3.78
LXDS (Lx Divider Select) = 1
Analog Output offset Ratio
LXDS (Lx Divider Select) = 0
LXDS (Lx Divider Select) = 1
VRATIOLx-
mV
%
OFFSET
-80
-22
0.0
0.0
80
22
Analog Inputs Matching
LxMATCHING
LXDS (Lx Divider Select) = 0
LXDS (Lx Divider Select) = 1
96
96
100
100
104
104
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
External Resistor Range
R
20
–
–
200
15
k
EXT
Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)(107)
WD
-15
%
ACC
ANALOG MULTIPLEXER
Internal Chip Temperature Sense Gain
STTOV
–
10.5
5.25
–
mV/K
mV
VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0
5.5 V < VSUP < 27 V
)
RATIOVSENSE
5.0
5.5
VSENSE Output Related Offset
-40°C < TA < -20°C
OFFSETVSENSE
-30
-45
–
–
30
45
ANALOG OUTPUT (ADOUT0)
Maximum Output Voltage
-5.0 mA < IO < 5.0 mA
VOUT_MAX
V
V
VDD -0.35
0.0
–
–
VDD
0.35
Minimum Output Voltage
-5.0 mA < IO < 5.0 mA
VOUT_MIN
Notes
105. Analog Multiplexer input disconnected from Lx input pin.
106. Analog Multiplexer input connected to Lx input pin.
107. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in k
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
58
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 34. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
V
V
0.0
–
–
0.8
High-state Output Voltage
IOUT = -250 µA
VOH
VDD -0.8
VDD
TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)
Low-state Input Voltage
VIL
VIH
-0.3
0.7 x VDD
10
–
–
0.3 x VDD
VDD +0.3
30
V
V
High-state Input Voltage
Pin Pull-up Current, 0 V < VIN < 3.5 V
LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(108)
IPUIN
20
µA
Output Current Limitation
IBUSLIM
mA
Dominant State, VBUS = 18 V
40
120
200
Leakage Output Current to GND
Dominant State; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
IBUS_PAS_REC
-1.0
–
–
–
–
mA
µA
20
Recessive State; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS
VBAT
IBUS_NO_GND
-1.0
–
–
–
1.0
mA
GND Disconnected; GNDDEVICE = VSUP; VBAT = 12 V; 0 V < V
18 V
<
BUS
V
Disconnected; VSUP_DEVICE = GND; 0 V < V
< 18 V
BUS
IBUS
100
µA
BAT
Receiver Input Voltages
Receiver Dominant State
Receiver Recessive State
VSUP
VBUSDOM
VBUSREC
VBUS_CNT
VHYS
–
0.6
0.475
–
–
–
0.4
–
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM
0.5
–
0.525
0.175
)
LIN Transceiver Output Voltage
V
VLIN_REC
VLIN_DOM_0
VLIN_DOM_1
VSUP-1
Recessive State, TXD HIGH, I
= 1.0 µA
–
–
1.4
2
OUT
–
–
Dominant State, TXD LOW, 500 External Pull-up Resistor, LDVS = 0
Dominant State, TXD LOW, 500 External Pull-up Resistor, LDVS = 1
1.1
1.7
LIN Pull-up Resistor to V
SUP
RSLAVE
TLINSD
20
150
–
30
165
10
60
180
–
k
°C
°C
Over-temperature Shutdown(109)
Over-temperature Shutdown Hysteresis
TLINSD_HYS
Notes
108. Parameters guaranteed for 7.0 V VSUP 18 V.
109. When over-temperature shutdown occurs, the LIN bus goes into a recessive state and the flag LINOT in the LINSR is set.
33911
Analog Integrated Circuit Device Data
59
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 35. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions,
unless otherwise noted.
Characteristic
SPI INTERFACE TIMING (see Figure 36)
Symbol
Min
Typ
Max
Unit
SPI Operating Frequency
f
t
–
–
–
–
–
–
–
–
–
4.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MHz
ns
SPIOP
SCLK Clock Period
250
110
110
100
100
40
CLK
PS
SCLK Clock High Time(110)
t
ns
SCLKH
W
SCLK Clock Low Time(110)
t
ns
SCLKL
W
Falling Edge of CS to Rising Edge of SCLK(110)
Falling Edge of SCLK to CS Rising Edge(110)
MOSI to Falling Edge of SCLK(110)
Falling Edge of SCLK to MOSI(110)
MISO Rise Time(110)
t
ns
LEAD
tLAG
ns
t
ns
SISU
t
40
ns
SIH
tRSO
ns
C = 220 pF
L
–
–
40
40
–
–
MISO Fall Time(110)
t
ns
ns
FSO
C = 220 pF
L
Time from Falling or Rising Edges of CS to:(110)
- MISO Low-impedance
t
0.0
0.0
–
–
50
50
SOEN
- MISO High -impedance
t
SODIS
Time from Rising Edge of SCLK to MISO Data Valid(110)
t
ns
VALID
0.2 x VDD MISO 0.8 x VDD, CL = 100 pF
0.0
–
75
RST OUTPUT PIN
Reset Low-Level Duration after VDD High (see Figure 35)
Reset Deglitch Filter Time
t
0.65
350
1.0
1.35
900
ms
ns
RST
t
600
RSTDF
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period (111)
t
ms
PWD
External Resistor REXT = 20 k (1%)
External Resistor REXT = 200 k (1%)
Without External Resistor REXT (WDCONF pin open)
8.5
79
10
94
11.5
108
205
110
150
Notes
110. This parameter is guaranteed by process monitoring but not production tested.
111. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in k
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
60
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 35. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions,
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
L1 AND L2 INPUTS
Wake-up Filter Time
t
8.0
20
38
s
WUF
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at the End of a SPI Stop
Command) and Stop Mode Activation(112)
tSTOP
s
–
–
5.0
Normal Request Mode Timeout (see Figure 35)
t
110
150
205
ms
NRTOUT
tS-ON
Delay Between SPI Command and HS/LS Turn On(113)
9.0 V < VSUP < 27 V
s
–
–
–
–
–
–
10
10
10
Delay Between SPI Command and HS/LS Turn Off(113)
9.0 V < VSUP < 27 V
tS-OFF
s
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)(112)
tSNR2N
s
s
Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
tWUCS
tWUSPI
9.0
90
15
—
80
N/A
Minimum Time Between Rising and Falling Edge on the CS
t2CS
4.0
—
—
s
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(114), (115)
Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs
D1
7.0 V VSUP18 V
0.396
—
—
—
Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs
D2
7.6 V VSUP18 V
—
0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC(114), (116)
Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs
D3
s
s
7.0 V VSUP18 V
0.417
—
—
—
—
Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs
D4
7.6 V VSUP18 V
0.590
Notes
112. This parameter is guaranteed by process monitoring but not production tested.
113. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to an external load.
114. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 29.
115. See Figure 30.
116. See Figure 31.
33911
Analog Integrated Circuit Device Data
61
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 35. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33911 and -40°C TA 85°C for the
34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions,
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
V/s
s
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SR
—
20
—
FAST
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(117)
Propagation Delay and Symmetry(118)
tREC_PD
Propagation Delay Receiver, tREC_PD = max (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR
)
—
3.0
—
6.0
2.0
tREC_SYM
-2.0
Bus Wake-up Deglitcher (Sleep and Stop Modes)(119)
tPROPWL
42
70
95
s
s
Bus Wake-up Event Reported
From Sleep Mode(120)
From Stop Mode(121)
tWAKE
tWAKE
—
—
1500
17
9.0
13
TXD Permanent Dominant State Delay
tTXDDOM
0.65
1.0
1.35
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
PWMIN pin(122)
fPWMIN
kHz
Max. frequency to drive HS and LS output pins
10
Notes
117. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 29.
118. See Figure 32.
119. See Figure 33 for Sleep and Figure 34 for Stop mode.
120. The measurement is done with 1.0 µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when V reaches 3.0V.
DD
See Figure 33. The delay depends of the load and capacitor on VDD
.
121. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 34.
122. This parameter is guaranteed by process monitoring but not production tested.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
62
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
33911
TRANSIENT PULSE
GENERATOR
1.0nF
LIN
(
NOTE
)
GND
PGND LGND AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 27. Test Circuit for Transient Test Pulses (LIN)
33911
TRANSIENT PULSE
GENERATOR
(NOTE)
1.0nF
L1, L2
10k
GND
PGND LGND AGND
NOTE: Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 28. Test Circuit for Transient Test Pulses (Lx)
VSUP
R0
LIN
TXD
R0 AND C0 COMBINATIONS:
• 1.0 K and 1.0 nF
• 660 and 6.8 nF
RXD
C0
• 500 and 10 nF
Figure 29. Test Circuit for LIN Timing Measurements
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
63
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
t
- MAX
t
- MIN
REC
DOM
74.4% V
60.0% V
SUP
SUP
t
- MIN
DOM
58.1% V
40.0% V
58.1% V
40.0% V
SUP
SUP
SUP
SUP
LIN
28.4% V
SUP
28.4% V
SUP
42.2% V
SUP
t
- MIN
REC
t
- MAX
t
(MIN)
BUS_DOM
DOM
t
(MAX)
BUS_REC
RXD
t
t
RREC
RDOM
Figure 30. LIN Timing Measurements for Normal Slew Rate
TXD
tBIT
tBIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
t
- MAX
t
- MIN
REC
DOM
77.8% V
60.0% V
SUP
SUP
t
- MIN
DOM
61.6% V
40.0% V
61.6% V
40.0% V
SUP
SUP
SUP
SUP
LIN
25.1% V
SUP
25.1% V
SUP
38.9% V
SUP
t
- MIN
REC
t
- MAX
t
(MIN)
BUS_DOM
DOM
t
(MAX)
BUS_REC
RXD
t
t
RREC
RDOM
Figure 31. LIN Timing Measurements for Slow Slew Rate
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
64
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VLIN_REC
V
BUSrec
V
SUP
LIN BUS SIGNAL
V
BUSdom
RXD
t
RX_PDF
t
RX_PDR
Figure 32. LIN Receiver Timing
V
LIN_REC
LIN
0.4 V
SUP
DOMINANT LEVEL
VDD
t
WL
t
WAKE
PROP
Figure 33. LIN Wake-up Sleep Mode Timing
V
LIN_REC
LIN
0.
0.4 VSUP
Dominant Level
IRQ
tWAKE
tPROPWL
Figure 34. LIN Wake-up Stop Mode Timing
33911
Analog Integrated Circuit Device Data
65
Freescale Semiconductor
MC33911BAC / MC34911BAC
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
V
SUP
V
DD
RST
t
NRTOUT
t
RST
Figure 35. Power On Reset and Normal Request Timeout Timing
t
PSCLK
CS
t
t
WSCLKH
LEAD
t
LAG
SCLK
t
WSCLKL
t
t
SIH
SISU
MOSI
MISO
UNDEFINED
D0
DON’T CARE
D7
DON’T CARE
t
VALID
t
SODIS
t
SOEN
D0
D7
DON’T CARE
Figure 36. SPI Timing Characteristics
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
66
MC33911BAC / MC34911BAC
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33911 was designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
33911 is well suited to perform relay control in applications
like window lift, sunroof, etc. via a LIN bus.
which include a voltage sense port and two wake-up capable
pins. An internal voltage regulator provides power to a MCU
device.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with 3-wire bus systems, where one wire is
used for communication, one for battery, and one for ground.
Power switches are provided on the device configured as
high side and low side outputs. Other ports are also provided,
FUNCTIONAL PIN DESCRIPTION
See Figure 1, 33911 Simplified Application Diagram, for a
graphic representation of the various pins referred to in the
following paragraphs. Also, see the 33911 Pin Connections
diagram for a description of the pin locations in the package.
CHIP SELECT (CS)
CS is an active low digital input. It must remain low during a
valid SPI communication and allow for several devices to be
connected in the same SPI bus without contention. A rising
edge on CS signals the end of the transmission and the
moment the data shifted in is latched. A valid transmission
must consist of 8 bits only.
RECEIVER OUTPUT (RXD)
The RXD pin is a digital output. It is the receiver output of the
LIN interface and reports the state of the bus voltage: RXD
Low when LIN bus is dominant, RXD High when LIN bus is
recessive.
While in STOP mode a low-to-high level transition on this pin
will generate a wake-up condition.
ANALOG MULTIPLEXER (ADOUT0)
TRANSMITTER INPUT (TXD)
The ADOUT0 pin can be configured via the SPI to allow the
MCU A/D converter to read the several inputs of the Analog
Multiplexer, including the VSENSE, L1, L2 input voltages and
the internal junction temperature.
The TXD pin is a digital input. It is the transmitter input of the
LIN interface and controls the state of the bus output
(dominant when TXD is Low, recessive when TXD is High).
This pin has an internal pull-up to force recessive state in
case the input is left floating.
PWM INPUT CONTROL (PWMIN)
This digital input can control the high side and low side
drivers in Normal Request and Normal mode.
LIN BUS (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is
compliant to the LIN bus specification 2.0.
To enable PWM control, the MCU must perform a write
operation to the High Side Control Register (HSCR), or the
Low Side Control Register (LSCR).
The LIN interface is only active during Normal and Normal
Request modes.
This pin has an internal 20 A current pull-up.
RESET (RST)
SERIAL DATA CLOCK (SCLK)
This bidirectional pin is used to reset the MCU in case the
33911 detects a reset condition, or to inform the 33911 that
the MCU was just reset. After release of the RST pin Normal
Request mode is entered.
The SCLK pin is the SPI clock input pin. MISO data changes
on the negative transition of the SCLK. MOSI is sampled on
the positive edge of the SCLK.
The RST pin is an active low filtered input and output formed
by a weak pull-up and a switchable pull-down structure,
which allows this pin to be shorted either to VDD or to GND
during software development without the risk of destroying
the driver.
MASTER OUT SLAVE IN (MOSI)
The MOSI digital pin receives SPI data from the MCU. This
data input is sampled on the positive edge of SCLK.
MASTER IN SLAVE OUT (MISO)
INTERRUPT (IRQ)
The MISO pin sends data to a SPI-enabled MCU. It is a digital
tri-state output used to shift serial data to the microcontroller.
Data on this output pin changes on the negative edge of the
SCLK. When CS is High, this pin will remain in high-
impedance state.
The IRQ pin is a digital output used to signal events or faults
to the MCU while in Normal and Normal Request mode or to
signal a wake-up from Stop mode. This active low output will
transition high only after the interrupt is acknowledged by a
SPI read of the respective status bits.
33911
Analog Integrated Circuit Device Data
67
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
power mode. No wake-up feature is available in that
condition.
WATCHDOG CONFIGURATION (WDCONF)
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure
the window watchdog period. When connected directly to
ground, the watchdog will be disabled. When this pin is left
open, the watchdog period is fixed to its lower precision
internal default value (150 ms, typical).
When an Lx input is not selected in the analog multiplexer,
the voltage divider is disconnected from that input.
HIGH SIDE OUTPUT (HS1)
This high side switch is able to drive loads such as relays or
lamps. Its structure is connected to the VS2 supply pin. The
pin is short-circuit protected and also protected against
overheating.
GROUND CONNECTIONS (AGND, PGND, LGND)
The AGND, PGND and LGND pins are the Analog and Power
ground pins.
HS1 is controlled by SPI and can respond to a signal applied
to the PWMIN input pin.
The AGND pin is the ground reference of the voltage
regulator.
The HS1 output can also be used during low-power mode for
the cyclic-sense of the wake inputs.
The PGND and LGND pins are used for high-current load
return as in the relay-drivers and LIN interface pin.
POWER SUPPLIES (VS1 AND VS2)
Note: PGND, AGND and LGND pins must be connected
together.
These are the battery level voltage supply pins. In
application, VS1 and VS2 pins must be protected against a
reverse battery connection and negative transient voltages
with external components. These pins sustain standard
automotive voltage conditions such as a load dump at 40V.
LOW SIDES (LS1 AND LS2)
LS1 and LS2 are the low side driver outputs. Those outputs
are short-circuit protected and include active clamp circuitry
to drive inductive loads. Due to the energy clamp voltage on
this pin, it can raise above the battery level when switched off.
The switches are controlled through the SPI and can be
configured to respond to a signal applied to the PWMIN input
pin.
The high side switch (HS1) is supplied by the VS2 pin, all
other internal blocks are supplied by the VS1 pin.
VOLTAGE SENSE (VSENSE)
This input can be connected directly to the battery line. It is
protected against a battery reverse connection. The voltage
present on this input is scaled down by an internal voltage
divider, and can be routed to the ADOUT0 output pin and
used by the MCU to read the battery voltage.
Both low side switches are protected against overheating.
DIGITAL/ANALOGS (L1 AND L2)
The Lx pins are multi purpose inputs. They can be used as
digital inputs, which can be sampled by reading the SPI and
used for wake-up when 33911 is in low-power mode or used
as analog inputs for the analog multiplexer. When used to
sense voltage outside the module, a 33kohm series resistor
must be used on each input.
The ESD structure on this pin allows for excursion up to
+40 V and down to -27 V, allowing this pin to be connected
directly to the battery line. It is strongly recommended to
connect a 10kohm resistor in series with this pin for protection
purposes.
When used as wake-up inputs L1 and L2 can be configured
to operate in cyclic sense mode. In this mode, the high side
switch is configured to be periodically turned on and sample
the wake-up inputs. If a state change is detected between two
cycles, a wake-up is initiated. The 33911 can also wake-up
from Stop or Sleep by a simple state change on L1 and L2.
+5.0 V MAIN REGULATOR OUTPUT (VDD)
An external capacitor must be placed on the VDD pin to
stabilize the regulated output voltage. The VDD pin is
intended to supply a microcontroller. The pin is current limited
against shorts to GND and over-temperature protected.
When used as an analog input, the voltage present on the Lx
pins are scaled down by a selectable internal voltage divider
and can be routed to the ADOUT0 output through the analog
multiplexer.
During Stop mode, the voltage regulator does not operate
with its full drive capabilities and the output current is limited.
During Sleep mode the regulator output is completely shut
down.
Note: If an Lx input is selected in the analog multiplexer, it will
be disabled as a digital input and remains disabled in low-
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
68
MC33911BAC / MC34911BAC
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33911 - Functional Block Diagram
High Side Drivers
HS1
Window Watchdog
Digital / Analog Input
Low Side Driver
LS1 - LS2
Voltage & Temperature
Sense
WakeUp
Voltage Regulator
VDD
Reset & IRQ Logic
SPI Interface
LIN Physical Layer
Interface LIN
LIN Interface / Control
LS/HS - PMW Control
Analog Output 0
Analog Circutry
MCU Interface and Output Control
Drivers
Figure 37. Functional Internal Block Diagram
MCU INTERFACE
ANALOG CIRCUITRY
The 33911 is designed to operate under automotive
operating conditions. A fully configurable window watchdog
circuit will reset the connected MCU in case of an overflow.
The 33911 is providing its control and status information
through a standard 8-Bit SPI interface. Critical system events
such as low or high-voltage/temperature conditions as well as
over-current conditions in any of the driver stages can be
reported to the connected MCU via IRQ or RST.
Two low-power modes are available with several different
wake-up sources to reactivate the device. Two analog / digital
inputs can be sensed or used as the wake-up source.
Both low side and both high side driver outputs can be
controlled via the SPI register as well as PWMIN input.
The device is capable of sensing the supply voltage
(VSENSE), the internal chip temperature (CTEMP) as well as
the motor current using an external sense resistor.)
The integrated LIN physical layer interface can be configured
via the SPI register and its communication is driven through
the RXD and TXD device pin.
All internal analog sources are multiplexed to the ANOUT0
pin.
HIGH SIDE DRIVER
One current and temperature protected high side driver with
PWM capability is provided to drive small loads such as
status LED’s or small lamps.
VOLTAGE REGULATOR OUTPUTS
The driver can be configured for periodic sense during low-
power modes.
One voltage regulators is implemented on the 33911. The
VDD main regulator output is designed to supply an MCU
with a precise 5.0 V.
LOW SIDE DRIVERS
LIN PHYSICAL LAYER INTERFACE
Two current and temperature protected low side drivers with
PWM capability are provided to drive H-Bridge type relays for
power motor applications.
The 33911 provides a LIN 2.0 compatible LIN physical layer
interface with selectable slew rate and various diagnostic
features.
33911
Analog Integrated Circuit Device Data
69
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
NORMAL MODE
INTRODUCTION
In Normal mode, all 33911 functions are active and can be
controlled by the SPI interface and the PWMIN pin.
The 33911 offers three main operating modes: Normal (Run),
Stop, and Sleep (Low-power). In Normal mode, the device is
active and operating under normal application conditions.
The Stop and Sleep modes are low-power modes with wake-
up capabilities.
The VDD regulator is ON and delivers its full current
capability.
If an external resistor is connected between the WDCONF
pin and the Ground, the window watchdog function will be
enabled.
In Stop mode, the voltage regulator still supplies the MCU
with VDD (limited current capability), and in Sleep mode the
voltage regulator is turned off (VDD = 0 V).
Wake-up from Stop mode is initiated by a wake-up interrupt.
Wake-up from Sleep mode is done by a reset and the voltage
regulator is turned back on.
The wake-up inputs (L1 and L2) can be read as digital inputs
or have its voltage routed through the analog multiplexer.
The LIN interface has slew rate and timing compatible with
the LIN protocol specification 2.0. The LIN bus can transmit
and receive information.
The selection of the different modes is controlled by the
MOD1:2 bits in the Mode Control Register (MCR).
The high side and the low side switches are active and have
PWM capability according to the SPI configuration.
Figure 38 describes how transitions are done between the
different operating modes, and Table 36, gives an overview
of the operating modes.
The interrupts are generated to report failures for VSUP over/
under-voltage, thermal shutdown or thermal shutdown
prewarning on the main regulator.
RESET MODE
The 33911 enters the Reset mode after a power up. In this
mode, the RST pin is low for 1.0 ms (typical value). After this
delay, the 33911 enters the Normal Request mode and the
RST pin is driven high.
SLEEP MODE
The Sleep mode is a low-power mode. From Normal mode,
the device enters the Sleep mode by sending one SPI
command through the MCR. All blocks are in their lowest
power consumption condition. Only some wake-up sources
(wake-up inputs with or without cyclic sense, forced wake-up,
and LIN receiver) are active. The 5.0 V regulator is OFF. The
internal low-power oscillator may be active if the IC is
configured for cyclic sense. In this condition, the high side
switches are turned on periodically and the wake-up inputs
are sampled.
The Reset mode is entered if a reset condition occurs (VDD
low, Watchdog trigger fail, after a wake-up from Sleep mode,
or a Normal Request mode timeout).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the
device after the Reset mode, or after a wake-up from Stop
mode.
Wake-up from Sleep mode is similar to a power-up. The
device goes into Reset mode except that the SPI will report
the wake-up source, and the BATFAIL flag is not set.
In Normal Request mode, the VDD regulator is ON, the Reset
pin is high and the LIN is operating in RX Only mode.
As soon as the device enters the Normal Request mode, an
internal timer is started for 150 ms (typical value). During
these 150 ms, the MCU must configure the Timing Control
Register (TIMCR) and the MCR with MOD2 and MOD1 bits
set = 0, to enter in Normal mode. If within the 150 ms timeout
the MCU does not command the 33911 to Normal mode, it
will enter in Reset mode. If the WDCONF pin is grounded in
order to disable the watchdog function, the 33911 goes
directly in Normal mode after the Reset mode. If the
STOP MODE
The Stop mode is the second low-power mode, but in this
case the 5.0 V regulator is ON with limited current drive
capability. The application MCU is always supplied while the
33911 is operating in Stop mode.
The device can enter the Stop mode only by sending a SPI
command. When the application is in this mode, it can wake-
up from the 33911 side (for example: cyclic sense, force
wake-up, LIN bus, wake inputs) or the MCU side (CS, RST
pins). Wake-up from Stop mode will transition the 33911 to
Normal Request mode and generate an interrupt, except if
the wake-up event is a low to high transition on the CS pin or
comes from the RST pin.
WDCONF pin is open, the 33911 stays typically for 150 ms in
Normal Request before entering in Normal mode.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
70
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Normal Request Timeout Expired (t
)
NRTOUT
V
LOW
DD
V
HIGH AND
DD
Power Up
RESET DELAY (tRST) EXPIRED
POWER
DOWN
NORMAL
REQUEST
RESET
V
LOW
DD
NORMAL
WD FAILED
V
LOW (>t ) EXPIRED
NRTOUT
DD
AND VSUV = 0
SLEEP COMMAND
WAKE-UP (RESET)
STOP
SLEEP
V
LOW
DD
Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF pin connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via SPI
Sleep Command: Sleep command sent via SPI
wake-up from Stop mode: Lx state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
wake-up from Sleep mode: Lx state change, LIN bus wake-up, Periodic wake-up.
Figure 38. Operating Modes and Transitions
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
71
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 36. Operating Modes Overview
Function
VDD
Reset Mode
Normal Request Mode
Normal Mode
Full
Stop Mode
Sleep Mode
Full
Full
SPI/PWM(123)
SPI/PWM(123)
SPI
Stop
-
LSx
-
SPI/PWM
SPI/PWM
SPI
-
-
HS1
-
Note(124)
Note(125)
Analog Mux
Lx
-
-
-
-
Inputs
Inputs
Wake-up
Wake-up
LIN
-
Rx-Only
full/Rx-Only
On(126)/Off
On
Rx-Only/Wake-up
Wake-up
Watchdog
VSENSE
-
150 ms (typ.) timeout
On
-
-
-
On
VDD
Notes
123. Operation can be controlled by the PWMIN input.
124. HS switch can be configured for cyclic sense operation in Stop mode.
125. HS switch can be configured for cyclic sense operation in Sleep mode.
126. Windowing operation when enabled by an external resistor.
High-voltage Interrupt
INTERRUPTS
Interrupts are used to signal a microcontroller that a
peripheral needs to be serviced. The interrupts which can be
generated change according to the operating mode. While in
Normal and Normal Request modes, the 33911 signals
through interrupts special conditions which may require a
MCU software action. Interrupts are not generated until all
pending wake-up sources are read in the Interrupt Source
Register (ISR).
The high-voltage interrupt signals when the supply line (VS1)
voltage increases above the VSOV threshold (VSOV).
Over-temperature Prewarning
Over-temperature prewarning signals when the 33911
temperature has reached the pre-shutdown warning
threshold. It is used to warn the MCU that an over-
temperature shutdown in the main 5.0 V regulator is
imminent.
While in Stop mode, interrupts are used to signal wake-up
events. Sleep mode does not use interrupts, wake-up is
performed by powering-up the MCU. In Normal and Normal
Request mode the wake-up source can be read by the SPI.
LIN Over-current Shutdown / Over-temperature
Shutdown / TXD Stuck At Dominant / RXD Short-Circuit
The interrupts are signaled to the MCU by a low logic level of
the IRQ pin, which will remain low until the interrupt is
acknowledged by a SPI read. The IRQ pin will then be driven
high.
These signal fault conditions within the LIN interface will
cause the LIN driver to be disabled, except for the LIN over-
current. In order to restart an operation, the fault must be
removed and must be acknowledged by reading the SPI.
Interrupts are only asserted while in Normal, Normal Request
and Stop mode. Interrupts are not generated while the RST
pin is low.
The LINOC bit functionality in the LIN Status Register
(LINSR) is to indicate that an LIN over-current occurred and
the driver stays enabled.
Following is a list of the interrupt sources in Normal and
Normal Request modes, some of those can be masked by
writing to the SPI-Interrupt Mask Register (IMR).
High Side Over-temperature Shutdown
The high side over-temperature shutdown signals a
shutdown in the high side output.
Low-voltage Interrupt
The low-voltage interrupt signals when the supply line (VS1)
voltage drops below the VSUV threshold (VSUV).
Low Side Over-temperature Shutdown
The low side over-temperature shutdown signals a shutdown
in the low side outputs.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
72
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
In order to select and activate direct wake-up from Lx inputs,
RESET
the Wake-up Control Register (WUCR) must be configured
with appropriate LxWE inputs enabled or disabled. The
wake-up inputs state are read through the Wake-up Status
Register (WUSR).
To reset an MCU, the 33911 drives the RST pin low for the
time the reset condition lasts.
After the reset source has been removed, the state machine
will drive the RST output low for at least 1ms (typical value)
before driving it high.
Lx inputs are also used to perform cyclic sense wake-up.
Note: Selecting an Lx input in the analog multiplexer before
entering low-power mode will disable the wake-up capability
of the Lx input.
In the 33911 four main reset sources exist:
5.0 V Regulator Low-voltage-Reset (VRSTTH
)
The 5.0 V regulator output VDD is continuously monitored
against brown outs. If the supply monitor detects that the
voltage at the VDD pin has dropped below the reset threshold
Wake-up from Wake-up inputs (L1-L2) with cyclic sense
timer enabled
The SBCLIN can wake-up at the end of a cyclic sense period
if on one of the two wake-up input lines (L1-L2), a state
change occurs. The HS1 switch is activated in Sleep or Stop
modes from an internal timer. Cyclic sense and force wake-
up are exclusive. If cyclic sense is enabled, the force wake-
up can not be enabled.
VRSTTH the 33911 will issue a reset. In case of an over-
temperature, the voltage regulator will be disabled and the
voltage monitoring will issue a VDDOT Flag independently of
the VDD voltage.
Window Watchdog Overflow
In order to select and activate the cyclic sense wake-up from
Lx inputs, before entering in low-power modes (Stop or Sleep
modes), the following SPI set-up has to be performed:
If the watchdog counter is not properly serviced while its
window is open, the 33911 will detect an MCU software run-
away and will reset the microcontroller.
• In WUCR: select the Lx input to WU-enable.
• In HSCR: enable HS1.
• In TIMCR: select the CS/WD bit and determine the
cyclic sense period with CYSTx bits.
Wake-Up From Sleep Mode
During Sleep mode, the 5.0 V regulator is not active. Hence,
all wake-up requests from Sleep mode require a power-up/
reset sequence.
• Perform Go to Sleep/Stop command.
Forced Wake-up
External Reset
The 33911 can wake-up automatically after a predetermined
time spent in Sleep or Stop mode. Cyclic sense and forced
wake-up are exclusive. If forced wake-up is enabled, the
cyclic sense can not be enabled.
The 33911 has a bidirectional reset pin which drives the
device to a safe state (same as Reset mode) for as long as
this pin is held low. The RST pin must be held low long
enough to pass the internal glitch filter and get recognized by
the internal reset circuit. This functionality is also active in
Stop mode.
To determine the wake-up period, the following SPI set-up
has to be sent before entering in low-power modes:
After the RST pin is released, there is no extra tRST to be
considered.
• In TIMCR: select the CS/WD bit and determine the low-
power mode period with CYSTx bits.
• In HSCR: the HS1 bit must be disabled.
WAKE-UP CAPABILITIES
CS Wake-up
Once entered into one of the low-power modes (Sleep or
Stop) only wake-up sources can bring the device into Normal
mode operation.
While in Stop mode, a rising edge on the CS will cause a
wake-up. The CS wake-up does not generate an interrupt
and is not reported on the SPI.
In Stop mode, a wake-up is signaled to the MCU as an
interrupt, while in Sleep mode, the wake-up is performed by
activating the 5.0 V regulator and resetting the MCU. In both
cases, the MCU can detect the wake-up source by accessing
the SPI registers. There is no specific SPI register bit to signal
a CS wake-up or external reset. If necessary, this condition is
detected by excluding all other possible wake-up sources.
LIN Wake-up
While in the low-power mode the 33911 monitors the activity
on the LIN bus. A dominant pulse larger than tPROPWL
followed by a dominant to recessive transition will cause a
LIN wake-up. This behavior protects the system from a short-
to ground bus condition.
Wake-up from Wake-up inputs (L1-L2) with cyclic sense
disabled
The wake-up lines are dedicated to sense state changes of
external switches, and wake-up the MCU (in Sleep or Stop
mode).
33911
Analog Integrated Circuit Device Data
73
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WINDOW OPEN
FOR WATCHDOG
CLEAR
While in Stop mode, the 33911 can wake-up when the RST
pin is held low long enough to pass the internal glitch filter.
Then, it will change to Normal Request or Normal modes
depending on the WDCONF pin configuration. The RST
wake-up does not generate an interrupt and is not reported
via the SPI.
From Stop mode, the following wake-up events can be
configured:
WD TIMING X 50%
WD TIMING X 50%
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
WD PERIOD (t
)
PWD
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
• RST wake-up
Figure 39. Window Watchdog Operation
From Sleep mode, the following wake-up events can be
configured:
To disable the watchdog function in Normal mode, the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset mode.
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the WDSR.
• LIN wake-up
WINDOW WATCHDOG
The 33911 includes a configurable window watchdog which
is active in Normal mode. The watchdog can be configured by
an external resistor connected to the WDCONF pin. The
resistor is used to achieve higher precision in the timebase
used for the watchdog.
The watchdog timebase can be further divided by a prescaler
which can be configured by the Timing Control Register
(TIMCR). During Normal Request mode, the window
watchdog is not active but there is a 150 ms (typ.) timeout for
leaving the Normal Request mode. In case of a timeout, the
33911 will enter into Reset mode, resetting the
microcontroller before entering again into Normal Request
mode.
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33911 will reset the MCU, in the
same way as when the watchdog overflows.
HIGH SIDE OUTPUT PIN HS1
This output is one high side driver intended to drive small
resistive loads or LEDs incorporating the following features:
• PWM capability (software maskable)
• Open-load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
The high side switch is controlled by the HS1 bit in the High
Side Control Register (HSCR).
PWM Capability (direct access)
The high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If the HS1 bit and PWMHS1 is set in the HSCR, then the HS1
driver is turned on if the PWMIN pin is high, and turned off if
the PWMIN pin is low.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
74
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Interrupt
Control
VDD
HVSE
VDD
Module
PWMIN
PWMHS1
VS2
MOD1:2
HS1
High Side - Driver
charge pump
open load detection
on/off
Control
current limitation
overtemperture shutdown (interrupt maskable)
high voltage shutdown (maskable)
HS1OP
Status
HS1CL
HS1
Wakeup
Module
Figure 40. High Side Driver HS1
Open Load Detection
Module. The shutdown is indicated as an HS Interrupt in the
Interrupt Source Register (ISR).
The high side driver signals an open-load condition if the
current through the high side is below the open-load current
threshold.
A thermal shutdown of the high side driver is indicated by
setting the HS1OP and HS1CL bits simultaneously.
If the bit HSM is set in the Interrupt Mask Register (IMR) than
an interrupt (IRQ) is generated.
The open-load condition is indicated with the HS1OP bits in
the High Side Status Register (HSSR).
A write to the High Side Control Register (HSCR), when the
over-temperature condition is gone, will re-enable the high
side driver.
Current Limitation
The high side driver has an output current limitation. In
combination with the over-temperature shutdown, the high
side driver is protected against over-current and short-circuit
failures.
High-voltage Shutdown
In case of a high-voltage condition, and if the high-voltage
shutdown is enabled (bit HVSE in the Mode Control Register
(MCR) is set), the high side driver is shut down.
When the driver operates in the current limitation area, it is
indicated with the bit HS1CL in the HSSR.
A write to the HSCR, when the high-voltage condition is gone,
will re-enable the high side driver.
Note: If the driver is operating in current limitation mode
excessive power might be dissipated.
Sleep And Stop Mode
Over-temperature Protection (HS Interrupt)
The high side driver can be enabled to operate in Sleep and
Stop mode for cyclic sensing. Also see Table 36,
Operating Modes Overview.
The high side driver is protected against over-temperature. In
case of an over-temperature condition, the high side driver is
shut down and the event is latched in the Interrupt Control
33911
Analog Integrated Circuit Device Data
75
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
To protect the device against over-voltage when an inductive
load (relay) is turned off, an active clamp will re-enable the
low side FET if the voltage on the LS1 or LS2 pin exceeds a
certain level.
LOW SIDE OUTPUT PINS LS1 AND LS2
These outputs are two low side drivers intended to drive
relays incorporating the following features:
• PWM capability (software maskable)
• Open load detection
PWM Capability (direct access)
• Current limitation
Each low side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
• Over-temperature shutdown (with maskable interrupt)
• Active clamp (for driving relays)
• High-voltage shutdown (software maskable)
If both the LS1 and PWMLS1 bits are set in the LSCR, then
the LS1 driver is turned on if the PWMIN pin is high, and
turned off if the PWMIN pin is low. The same applies to the
LS2 and PWMLS2 bits for the LS2 driver.
The low side switches are controlled by the bit LS1:2 in the
Low Side Control Register (LSCR).
VDD
Interrupt
Control
VDD
HVSE
Module
PWMIN
PWMLSx
active
clamp
LSx
MOD1:2
Low Side - Driver
on/off
(active clamp)
LSx
Open-load Detection
Current Limitation
Over-temperture Shutdown (interrupt maskable)
High-voltage Shutdown (maskable)
Control
LSxOP
LSxCL
Status
PGND
Figure 41. Low Side Drivers LS1 and LS2
Open Load Detection
drivers are shut down and the event is latched in the Interrupt
Control Module. The shutdown is indicated as an LS Interrupt
in the Interrupt Source Register (ISR).
Each low side driver signals an open-load condition if the
current through the low side is below the open-load current
threshold.
If the bit LSM is set in the Interrupt Mask Register (IMR), then
an Interrupt (IRQ) is generated.
The open-load condition is indicated with the bit LS1OP and
LS2OP in the Low Side Status Register (LSSR).
A write to the Low Side Control Register (LSCR), when the
over-temperature condition is gone, will re-enable the low
side drivers.
Current Limitation
Each low side driver has a current limitation. In combination
with the over-temperature shutdown, the low side drivers are
protected against over-current and short-circuit failures.
High-voltage Shutdown
In case of a high voltage condition, and if the high-voltage
shutdown is enabed (bit HVSE in the Mode Control Register
(MCR) is set), both low side drivers are shut down.
When the drivers operate in current limitation, this is indicated
with the LS1CL and LS2CL bits in the LSSR.
A write to the LSCR, when the high-voltage condition is gone,
will re-enable the low side drivers.
Note: If the drivers are operating in current limitation mode
excessive power might be dissipated.
Sleep And Stop Mode
Over-temperature Protection (LS Interrupt)
The low side drivers are disabled in Sleep and Stop mode.
Also see Table 36, Operating Modes Overview.
Both low side drivers are protected against over-temperature.
In case of an over-temperature condition both low side
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
76
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
• LIN dominant voltage level selection
LIN PHYSICAL LAYER
The LIN driver is a low side MOSFET with over-current and
thermal shutdown. An internal pull-up resistor with a serial
diode structure is integrated, so no external pull-up
components are required for the application in a slave node.
The fall time from dominant to recessive and the rise time
from recessive to dominant is controlled. The symmetry
between both slopes is guaranteed.
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification
and has the following features:
• LIN physical layer 2.0 compliant
• Slew rate selection
• Over-current shutdown
• Over-temperature shutdown
• LIN pull-up disable in Stop and Sleep modes
• Advanced diagnostics
LIN Pin
The LIN pin offers a high susceptibility immunity level from
external disturbance, guaranteeing communication.
INTERRUPT
CONTROL
MODULE
WAKE-UP
MODULE
High-voltage
Shutdown
High Side
Interrupt
LIN
Wake-up
MOD1:2
LSR0:1
LINPE
VS1
LIN – DRIVER
LDVS
Slope and Slew Rate Control
Over-current Shutdown (interrupt maskable)
Over-temperature Shutdown (interrupt maskable)
RXONLY
RXSHORT
TXDOM
LINOT
LINOC
30K
LIN
TXD
RXD
SLOPE
CONTROL
LGND
WAKE-UP
FILTER
RECEIVER
Figure 42. LIN Interface
Slew Rate Selection
Control Register (MCR). The bit LINPE also changes the Bus
wake-up threshold (VBUSWU).
The slew rate can be selected for optimized operation at 10.4
and 20 kBit/s as well as a fast baud rate for test and
programming. The slew rate can be adapted with the LSR1:0
bits in the LIN Control Register (LINCR). The initial slew rate
is optimized for 20 kBit/s.
This feature will reduce the current consumption in STOP and
SLEEP modes. It also improves performance and safe
operation.
Current Limit (LIN Interrupt)
LIN Pull-up Disable In Stop And Sleep Modes
The output low side FET is protected against over-current
conditions. If an over-current condition occurs (e.g. LIN bus
short to VBAT), the transmitter will not be shut down. The bit
LINOC in the LIN Status Register (LINSR) is set.
In case of a LIN bus short to GND or LIN bus leakage during
low-power mode, the internal pull-up resistor on the LIN pin
can be disconnected by clearing the LINPE bit in the Mode
33911
Analog Integrated Circuit Device Data
77
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
If the LINM bit is set in the Interrupt Mask Register (IMR) an
Interrupt IRQ will be generated.
A read of the LINSR with the TXD pin is high will clear the bit
TXDOM.
Over-temperature Shutdown (LIN Interrupt)
LIN Dominant Voltage Level Selection
The output low side FET is protected against over-
temperature conditions. If an over-temperature condition
occurs, the transmitter will be shut down and the LINOT bit in
the LINSR is set.
The LIN dominant voltage level can be selected by the LDVS
bit in the LIN Control Register (LINCR).
LIN Receiver Operation Only
If the LINM bit is set in the IMR an Interrupt IRQ will be
generated.
While in Normal mode, the activation of the RXONLY bit
disables the LIN TXD driver. If a LIN error condition occurs,
this bit is automatically set. If a low-power mode is selected
with this bit set, the LIN wake-up functionality is disabled.
Then in STOP mode, the RXD pin will reflect the state of the
LIN bus.
The transmitter is automatically re-enabled once the
condition is gone and TXD is high.
A read of the LINSR with the TXD pin high will re-enable the
transmitter.
STOP Mode And Wake-up Feature
RXD Short-circuit Detection (LIN Interrupt)
During Stop mode operation, the transmitter of the physical
layer is disabled. If the LIN-PU bit was set in the Stop mode
sequence, the internal pull-up resistor is disconnected from
VSUP and a small current source keeps the LIN pin in the
recessive state. The receiver is still active and able to detect
wake-up events on the LIN bus line.
The LIN transceiver has a short-circuit detection for the RXD
output pin. In case of a short-circuit condition, either 5.0 V or
Ground, the RXSHORT bit in the LINSR is set and the
transmitter is shutdown.
If the LINM bit is set in the IMR an Interrupt IRQ will be
generated.
A dominant level longer than tPROPWL followed by a rising
edge will generate a wake-up interrupt and will be reported in
the Interrupt Source Register (ISR). Also see Figure 34.
The transmitter is automatically re-enabled once the
condition is gone (transition on RXD) and TXD is high.
A read of the LINSR without the RXD pin short-circuit
condition will clear the RXSHORT bit.
SLEEP Mode And Wake-up Feature
During Sleep mode operation, the transmitter of the physical
layer is disabled. If the LIN-PU bit was set in the Sleep mode
sequence, the internal pull-up resistor is disconnected from
TXD Dominant Detection (LIN Interrupt)
The LIN transceiver monitors the TXD input pin to detect
stuck-in-dominant (0 V) condition. If a stuck condition occurs
(TXD pin 0V for more than 1 second (typ.), the transmitter is
shut down and the TXDOM bit in the LINSR is set.
VSUP and a small current source keeps the LIN pin in
recessive state. The receiver must still active to detect wake-
up events on the LIN bus line.
If the bit LINM is set in the IMR an Interrupt IRQ will be
generated.
A dominant level longer than tPROPWL followed by a rising
edge will generate a system wake-up (Reset), and will be
reported in the ISR. Also see Figure 33.
The transmitter is automatically re-enabled once TXD is high.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
78
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
• MISO—Master-In Slave-Out
• SCLK—Serial Clock
33911 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between a microcontroller (master) and the 33911.
A complete data transfer via the SPI consists of 1 byte. The
master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
information (S3:S0).
The interface consists of four pins (see Figure 43):
•
CS—Chip Select
• MOSI—Master-Out Slave-In
CS
Register Write Data
A0 C3 C2
MOSI
MISO
A3
A2
A1
C1
C0
S0
Register Read Data
VMS LINS HSS LSS S3
S2
S1
SCLK
Read Data Latch
Write Data Latch
Rising Edge of SCLK
Falling Edge of SCLK
Change MISO/MISO Output
Sample MISO/MISO Input
Figure 43. SPI Protocol
During the inactive phase of the CS (HIGH), the new data
transfer is prepared.
The rising edge of the Chip Select (CS) indicates the end of
the transfer and latches the write data (MOSI) into the
register. The CS high forces MISO to the high-impedance
state.
The falling edge of the CS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
Register reset values are described along with the reset
condition. Reset condition is the condition causing the bit to
be set to its reset value. The main reset conditions are:
With the rising edge of the SPI clock (SCLK), the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock (SCLK), the data is sampled by the receiver.
- Power-On Reset (POR): level at which the logic is reset and
BATFAIL flag sets.
The data transfer is only valid if exactly 8 sample clock edges
are present during the active (low) phase of CS.
- Reset mode
- Reset done by the RST pin (ext_reset)
33911
Analog Integrated Circuit Device Data
79
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
Table 37. System Status Register
BIT
Adress(A3:A0)
Register Name / Read/Write Information
SYSSR - System Status Register
7
6
5
4
$0 - $F
R
VMS
LINS
HSS
LSS
Table 38 summarizes the SPI Register content for Control
Information (C3:C0)=W and status information (S3:S0) = R.
Table 38. SPI Register Overview
BIT
Adress(A3:A0)
Register Name / Read/Write Information
3
2
LINPE
VSUV
VSUV
-
1
0
MCR - Mode Control Register
VSR - Voltage Status Register
VSR - Voltage Status Register
WUCR - Wake-up Control Register
WUSR - Wake-up Status Register
WUSR - Wake-up Status Register
LINCR - LIN Control Register
W
R
HVSE
MOD2
VDDOT
VDDOT
L2WE
L2
MOD1
BATFAIL
BATFAIL
L1WE
L1
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
VSOV
R
VSOV
W
R
-
-
-
R
-
LDVS
RXSHORT
RXSHORT
-
-
L2
L1
W
R
RXONLY
TXDOM
TXDOM
PWMHS1
-
LSR1
LINOT
LINOT
-
LSR0
LINOC
LINOC
HS1
LINSR - LIN Status Register
LINSR - LIN Status Register
R
HSCR - High Side Control Register
HSSR - High Side Status Register
HSSR - High Side Status Register
LSCR - Low Side Control Register
LSSR - Low Side Status Register
LSSR - Low Side Status Register
W
R
-
HS1OP
HS1OP
LS2
HS1CL
HS1CL
LS1
R
-
-
W
R
PWMLS2
LS2OP
LS2OP
PWMLS1
LS2CL
LS2CL
WD2
LS1OP
LS1OP
WD1
LS1CL
LS1CL
WD0
R
TIMCR - Timing Control Register
W
CS/WD
$A
CYST2
WDERR
WDERR
MX2
CYST1
WDOFF
WDOFF
MX1
CYST0
WDWO
WDWO
MX0
WDSR - Watchdog Status Register
WDSR - Watchdog Status Register
AMUXCR - Analog Multiplexer Control Register
CFR - Configuration Register
R
R
WDTO
WDTO
LXDS
-
$B
$C
$D
W
W
W
R
CYSX8
LSM
-
-
IMR - Interrupt Mask Register
HSM
ISR3
ISR3
LINM
ISR1
VMM
$E
$F
ISR - Interrupt Source Register
ISR2
ISR0
ISR - Interrupt Source Register
R
ISR2
ISR1
ISR0
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
80
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
REGISTER DEFINITIONS
System Status Register - SYSSR
HS1CL
HS1OP
HSS
The System Status Register (SYSSR) is always transferred
with every SPI transmission and gives a quick system status
overview. It summarizes the status of the Voltage Status
Register (VSR), LIN Status Register (LINSR), High Side
Status Register (HSSR), and the Low Side Status Register
(LSSR).
Figure 46. High Side Status
LSS - Low Side Switch Status
Table 39. System Status Register
This read-only bit indicates that one or more bits in the LSSR
are set.
S7
S6
S5
S4
1 = Low Side Status bit set
0 = None
Read
VMS
LINS
HSS
LSS
VMS - Voltage Monitor Status
This read-only bit indicates that one or more bits in the VSR
are set.
LS1CL
LS1OP
LSS
LS2CL
1 = Voltage Monitor bit set
0 = None
LS2OP
BATFAIL
Figure 47. Low Side Status
Mode Control Register - MCR
VDDOT
VMS
VSUV
VSOV
The Mode Control Register (MCR) allows to switch between
the operation modes and to configure the 33911. Writing the
MCR will return the VSR.
Figure 44. Voltage Monitor Status
Table 40. Mode Control Register - $0
LINS - LIN Status
C3
HVSE
1
C2
LINPE
1
C1
C0
This read-only bit indicates that one or more bits in the LINSR
are set.
Write
MOD2
MOD1
1 = LIN Status bit set
0 = None
Reset Value
Reset Condition
-
-
-
-
POR
POR
HVSE - High-Voltage Shutdown Enable
LINOC
LINOT
LINS
This write-only bit enables/disables automatic shutdown of
the high side and the low side drivers during a high-voltage
VSOV condition.
TXDOM
RXSHORT
1 = automatic shutdown enabled
0 = automatic shutdown disabled
Figure 45. LIN Status
LINPE - LIN pull-up enable.
HSS - High Side Switch Status
This write-only bit enables/disables the 30 kLIN pull-up
resistor in STOP and SLEEP modes. This bit also controls
the LIN bus wake-up threshold.
This read-only bit indicates that one or more bits in the HSSR
are set.
1 = High Side Status bit set
0 = None
1 = LIN pull-up resistor enabled
0 = LIN pull-up resistor disabled
33911
Analog Integrated Circuit Device Data
81
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
MOD2, MOD1 - Mode Control Bits
Any access to the MCR or Voltage Status Register (VSR) will
clear the BATFAIL flag.
These write-only bits select the operating mode and allow to
clear the watchdog in accordance with Table 41, Mode
Control Bits.
1 = POR Reset has occurred
0 = POR Reset has not occurred
Table 41. Mode Control Bits
Wake-up Control Register - WUCR
MOD2
MOD1
Description
This register is used to control the digital wake-up inputs.
Writing the Wake-up Control Register (WUCR) will return the
Wake-up Status Register (WUSR).
0
0
1
1
0
1
0
1
Normal Mode
Stop Mode
Sleep Mode
Table 43. Wake-up Control Register - $2
Normal Mode + watchdog Clear
C3
C2
C1
C0
Voltage Status Register - VSR
Write
0
0
L2WE
L1WE
Returns the status of the several voltage monitors. This
register is also returned when writing to the Mode Control
Register (MCR).
Reset
Value
1
1
1
1
Reset Condition
POR, Reset mode or ext_reset
Table 42. Voltage Status Register - $0/$1
S3
S2
S1
S0
LxWE - Wake-up Input x Enable
Read
VSOV
VSUV
VDDOT BATFAIL
This write-only bit enables/disables which Lx inputs are
enabled. In Stop and Sleep mode the LxWE bit determines
which wake inputs are active for wake-up. If one of the Lx
inputs is selected on the analog multiplexer, the
corresponding LxWE is masked to 0.
VSOV - VSUP Over-voltage
This read-only bit indicates an over-voltage condition on the
VS1 pin.
1 = Wake-up Input x enabled.
0 = Wake-up Input x disabled.
1 = Over-voltage condition.
0 = Normal condition.
Wake-up Status Register - WUSR
VSUV - VSUP Under-voltage
This register is used to monitor the digital wake-up inputs and
is also returned when writing to the WUCR.
This read-only bit indicates an under-voltage condition on the
VS1 pin.
1 = Under-voltage condition.
0 = Normal condition.
Table 44. Wake-Up Status Register - $2/$3
S3
S2
S1
S0
VDDOT - Main Voltage Regulator Over-temperature
Warning
Read
-
-
L2
L1
This read-only bit indicates that the main voltage regulator
temperature reached the Over-temperature Prewarning
Threshold.
Lx - Wake-up input x
This read-only bit indicates the status of the corresponding Lx
input. If the Lx input is not enabled then the according Wake-
Up status will return 0.
1 = Over-temperature Prewarning
0 = Normal
After a wake-up form Stop or Sleep mode these bits also
allow to determine which input has caused the wake-up, by
first reading the Interrupt Status Register (ISR) and then
reading the WUSR.
BATFAIL - Battery Fail Flag.
This read-only bit is set during power-up and indicates that
the 33911 had a Power On Reset (POR).
1 = Lx Wake-up.
0 = Lx Wake-up disabled or selected as analog input.
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
82
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LIN Control Register - LINCR
LIN Status Register - LINSR
This register controls the LIN physical interface block. Writing
the LIN Control Register (LINCR) returns the LIN Status
Register (LINSR).
This register returns the status of the LIN physical interface
block and is also returned when writing to the LIN Control
Register (LINCR).
Table 45. LIN Control Register - $4
Table 47. LIN Status Register - $4/$5
C3
C2
C1
C0
S3
S2
S1
S0
Write
LDVS
RXONLY
LSR1
LSR0
Read
RXSHORT
TXDOM
LINOT
LINOC
Reset
Value
0
0
0
0
RXSHORT - RXD Short-circuit
This read-only bit indicates a short-circuit condition on RXD
(shorted either to 5.0V or to Ground). The short-circuit delay
must be 8µs worst case to be detected and to shutdown the
driver. To clear this bit, it must be read after the condition is
gone (transition detected on RXD). The LIN driver is
automatically re-enabled once the condition is gone.
POR, Reset
mode or
ext_reset
POR, Reset mode,
ext_reset or LIN
failure gone*
Reset
Condition
POR
* LIN failure gone: if LIN failure (overtemp, TxD/RxD short) was set, the flag
resets automatically when the failure is gone.
1 = RxD short-circuit condition.
0 = None.
LDVS - LIN Dominant Voltage Select
This write-only bit controls the LIN Dominant voltage:
1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7 V typ)
0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1 V typ)
TXDOM - TXD Permanent Dominant
This read-only bit signals the detection of a TXD pin stuck at
dominant (Ground) condition and the resultant shutdown in
the LIN transmitter. This condition is detected after the TXD
pin remains in dominant state for more than 1 second typical
value.
RXONLY - LIN Receiver Operation Only.
This write-only bit controls the behavior of the LIN transmitter.
In Normal mode the activation of the RXONLY bit disables
the LIN transmitter. In case of a LIN error condition this bit is
automatically set.
To clear this bit, it must be read after TXD has gone high. The
LIN driver is automatically re-enabled once TXD goes high.
1 = TXD stuck at dominant fault detected.
0 = None.
In Stop mode this bit disables the LIN wake-up functionality
and the RXD pin will reflect the state of the LIN bus.
1 = only LIN receiver active (Normal mode) or LIN wake-up
disabled (Stop mode).
LINOT - LIN Driver Over-temperature Shutdown
This read-only bit signals that the LIN transceiver was shut-
down due to over-temperature. The transmitter is
automatically re-enabled after the over-temperature
condition is gone and TXD is high. The LINOT bit is cleared
after SPI read once the condition is gone.
0 = LIN fully enabled.
LSRx - LIN Slew-rate
This write-only bit controls the LIN driver slew-rate in
accordance with Table 46.
1 = LIN over-temperature shutdown
0 = None
Table 46. LIN Slew-rate Control
LSR1
LSR0
Description
LINOC - LIN Driver Over-current Shutdown
0
0
1
1
0
1
0
1
Normal Slew-Rate (up to 20 kb/s)
Slow Slew-Rate (up to 10 kb/s)
Fast Slew-Rate (up to 100 kb/s)
Reserved
This read-only bit signals an over-current condition occurred
on the LIN pin. The LIN driver is not shut down but an IRQ is
generated. To clear this bit, it must be read after the condition
is gone.
1 = LIN over-current shutdown
0 = None
33911
Analog Integrated Circuit Device Data
83
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
Low Side Control Register - LSCR
This register controls the operation of the high side driver.
Writing to this register returns the High Side Status Register
(HSSR).
This register controls the operation of the low side drivers.
Writing the Low Side Control Register (LSCR) will also return
the Low Side Status Register (LSSR).
Table 48. High Side Control Register - $6
Table 50. Low Side Control Register - $8
C3
C2
C1
C0
C3
C2
C1
C0
Write
0
PWMHS1
0
HS1
Write
PWMLS2
PWMLS1
LS2
LS1
Reset
Value
0
0
0
0
Reset
Value
0
0
0
0
Reset
Condition
POR, Reset mode, ext_reset, HS1
over-temp or (VSOV & HVSE)
POR
Reset
Condition
POR, Reset mode, ext_reset, LSx
over-temp or (VSOV & HVSE)
POR
PWMHS1 - PWM Input Control Enable.
PWMLx - PWM input control enable.
This write-only bit enables/disables the PWMIN input pin to
control the high side switch. The high side switch must be
enabled (HS1 bit).
This write-only bit enables/disables the PWMIN input pin to
control the respective low side switch. The corresponding low
side switch must be enabled (LSx bit).
1 = PWMIN input controls HS1 output.
0 = HS1 is controlled only by SPI.
1 = PWMIN input controls LSx.
0 = LSx is controlled only by SPI.
HS1 - High Side Switch Control.
LSx - LSx switch control.
This write-only bit enables/disables the high side switch.
1 = HS1 switch on.
This write-only bit enables/disables the corresponding low
side switch.
0 = HS1 switch off.
1 = LSx switch on.
0 = LSx switch off.
High Side Status Register - HSSR
This register returns the status of the high side switch and is
also returned when writing to the High Side Control Register
(HSCR).
Low Side Status Register - LSSR
This register returns the status of the low side switches and
is also returned when writing to the LSCR.
Table 49. High Side Status Register - $6/$7
Table 51. Low Side Status Register - $8/$9
S3
S2
S1
S0
C3
C2
C1
C0
Read
-
-
HS1OP
HS1CL
Read
LS2OP
LS2CL
LS1OP
LS1CL
High Side thermal shutdown
Low Side thermal shutdown
A thermal shutdown of the high side drivers is indicated by
setting the HS1OP and HS1CL bits simultaneously.
A thermal shutdown of the low side drivers is indicated by
setting all LSxOP and LSxCL bits simultaneously.
HS1OP - High Side Switch Open-Load Detection
LSxOP - Low Side Switch Open-Load Detection
This read-only bit signals that the high side switch is
conducting current below a certain threshold indicating
possible load disconnection.
This read-only bit signals that the low side switches are
conducting current below a certain threshold indicating
possible load disconnection.
1 = HS1 Open Load detected (or thermal shutdown)
0 = Normal
1 = LSx Open-load detected (or thermal shutdown)
0 = Normal
HS1CL - High Side Current Limitation
LSxCL - Low Side Current Limitation
This read-only bit indicates that the high side switch is
operating in current limitation mode.
This read-only bit indicates that the respective low side switch
is operating in current limitation mode.
1 = HS1 in current limitation (or thermal shutdown)
0 = Normal
1 = LSx in current limitation (or thermal shutdown)
0 = Normal
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
84
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This option is only active if the high side switch is enabled
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in Table 54.
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
Table 54. Cyclic Sense Interval
CYSX8(127) CYST2
CYST1
CYST0
Interval
Table 52. Timing Control Register - $A
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No cyclic sense
20ms
C3
C2
C1
C0
40ms
WD2
WD1
WD0
Write
CS/WD
60ms
CYST2
CYST1
CYST0
80ms
Reset
Value
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
1120ms
-
-
0
0
0
Reset
Condition
POR
CS/WD - Cyclic Sense or Watchdog prescaler select.
This write-only bit selects which prescaler is being written to,
the Cyclic Sense prescaler or the watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = watchdog Prescaler select
WDx - Watchdog Prescaler
Notes
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 53. This configuration is valid only if
windowing watchdog is active.
127. bit CYSX8 is located in Configuration Register (CFR)
Watchdog Status Register - WDSR
This register returns the watchdog status information and is
also returned when writing to the TIMCR.
Table 53. Watchdog Prescaler
WD2
WD1
WD0
Prescaler Divider
Table 55. Watchdog Status Register - $A/$B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
S3
S2
S1
S0
4
Read
WDTO
WDERR WDOFF
WDWO
6
8
WDTO - Watchdog Timeout
10
12
14
This read-only bit signals the last reset was caused by either
a watchdog timeout or by an attempt to clear the watchdog
within the window closed.
Any access to this register or the TIMCR will clear the WDTO
bit.
CYSTx - Cyclic Sense Period Prescaler Select
1 = Last reset caused by watchdog timeout
0 = None
This write-only bits selects the interval for the wake-up cyclic
sensing together with the bit CYSX8 in the Configuration
Register (CFR) (see Configuration Register - CFR).
33911
Analog Integrated Circuit Device Data
85
Freescale Semiconductor
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WDERR - Watchdog Error
MXx - Analog Multiplexer Input Select
This read-only bit signals the detection of a missing watchdog
resistor. In this condition the watchdog is using the internal,
lower precision timebase. The Windowing function is
disabled.
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 57.
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
Table 57. Analog Multiplexer Channel Select
MX2
MX1
MX0
Meaning
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected to
Ground and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Reserved
Die Temperature Sensor
VSENSE input
L1 input
1 = Watchdog is disabled
0 = Watchdog is enabled
L2 input
Reserved
WDWO - Watchdog Window Open
Reserved
This read-only bit signals when the watchdog window is open
for clears. The purpose of this bit is for testing. Should be
ignored in case WDERR is High.
Configuration Register - CFR
1 = Watchdog window open
0 = Watchdog window closed
This register controls the cyclic sense timing multiplier.
Table 58. Configuration Register - $D
Analog Multiplexer Control Register - MUXCR
C3
C2
C1
C0
This register controls the analog multiplexer and selects the
divider ration for the Lx input divider.
Write
0
CYSX8
0
0
Table 56. Analog Multiplexer Control Register -$C
Reset
Value
0
0
0
0
C3
C2
C1
C0
POR, Reset
mode or
ext_reset
Reset
Condition
POR
POR
POR
Write
LXDS
MX2
MX1
MX0
Reset
Value
1
0
0
0
CYSX8 - Cyclic Sense Timing x 8.
Reset
Condition
This write-only bit influences the cyclic sense period as
shown in Table 54.
POR
POR, Reset mode or ext_reset
1 = Multiplier enabled
0 = None
LXDS - Lx Analog Input Divider Select
This write-only bit selects the resistor divider for the Lx analog
inputs. Voltage is internally clamped to VDD.
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
86
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Interrupt Mask Register - IMR
LINM - LIN Interrupts Mask
This register allow to mask some of interrupt sources. The
respective flags within the Interrupt Source Register (ISR) will
continue to work but will not generate interrupts to the MCU.
The 5.0 V Regulator over-temperature prewarning interrupt
and Under Voltage (VSUV) interrupts can not be masked and
will always cause an interrupt.
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
Writing to the Interrupt Mask Register (IMR) will return the
ISR.
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the VSUP over-voltage interrupt.
Table 59. Interrupt Mask Register - $E
1 = Interrupts Enabled
0 = Interrupts Disabled
C3
C2
C1
C0
Write
HSM
LSM
LINM
VMM
Interrupt Source Register - ISR
Reset
Value
1
1
1
1
This register allows the MCU to determine the source of the
last interrupt or wake-up respectively. A read of the register
acknowledges the interrupt and leads IRQ pin to high, in case
there are no other pending interrupts. If there are pending
interrupts, IRQ will be driven high for 10 µs and then be
driven low again.
Reset
Condition
POR
HSM - High Side Interrupt Mask
This register is also returned when writing to the IMR.
This write-only bit enables/disables interrupts generated in
the high side block.
Table 60. Interrupt Source Register - $E/$F
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
S3
S2
S1
S0
Read
ISR3
ISR2
ISR1
ISR0
LSM - Low Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the low side block.
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
Table 61. If no interrupt is pending than all bits are 0.
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
In case more than one interrupt is pending, than the interrupt
sources are handled sequentially multiplex.
Table 61. Interrupt Sources
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
no interrupt
no interrupt
none
Lx Wake-up from Stop mode-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
highest
-
-
LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN Wake-up
0
0
1
1
0
1
1
0
Voltage Monitor Interrupt
Voltage Monitor Interrupt
(High-voltage)
(Low-voltage and VDD over-temperature)
-
Forced Wake-up
lowest
33911
Analog Integrated Circuit Device Data
87
Freescale Semiconductor
MC33911G5AC/MC3433911G5AC
TYPICAL APPLICATION
LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATION
The 33911 can be configured in several applications. The figure below shows the 33911 in the typical Slave Node Application.
V
BAT
D1
C2
C1
VDD
IRQ
Interrupt
Control Module
LVI, HVI, HTI, OCI
Voltage Regulator
C4
C3
AGND
VDD
Reset
Control Module
LVR, HVR, HTR, WD,
LS1
RST
IRQ
Low Side Control
Module
HB Type Relay
LS2
RST
PGND
Window
R1
Motor Output
Watchdog Module
PWMIN
TIMER
High Side Control
Module
HS1
MISO
MOSI
SCLK
CS
Chip Temp Sense Module
VBAT Sense Module
SPI
&
CONTROL
SPI
VSENSE
MCU
R2
R3
L1
L2
Analog Input Module
ADOUT0
A/D
Wake Up Module
Digital Input Module
RXD
TXD
LIN Physical Layer
SCI
LIN
LIN
C5
Typical Component Values:
R4
C1 = 47µF; C2 = C4 = 100nF; C3 = 10µF; C5 = 220pF
R1 = 10k; R2 = R3 = 10kR4 = 20k-200k
Recommended Configuration of the not Connected Pins (NC):
Pin 15, 16, 20, 21 = GND
Pin 11, 30 = open (floating)
Pin 24 = open (floating) or VS2
Pin 28 = this pin is not internally connected and may be used for PCB routing
optimization.
33911
Analog Integrated Circuit Device Data
88
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under
Available Documentation column select Packaging Information.
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
89
IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK-
AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTA-
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33911
Analog Integrated Circuit Device Data
90
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
5/2007
•
Initial Release
Several textual corrections
Page 11: “Analog Output offset Ratio” (LXDS=1) changed to “Analog Output offset” +/-22mV
Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5
Page 12: Common mode input impedance corrected to 75k
Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release
1.0
•
•
•
•
•
9/2007
2.0
9/2007
2/2008
•
•
Revision number incremented at engineering request.
Changed Functional Block Diagram on page 24.
3.0
4.0
•
•
•
Datasheet updated according to the Pass1.2 silicon version electrical parameters
Add Maximum Rating on IBUS_NO_GND parameter
Added L1 and L2, Temperature Sense Analog Output Voltage per characterization(37), Internal Chip
Temperature Sense Gain per characterization at 3 temperatures(37) See Figure 16, Temperature Sense Gain,
VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38), and VSENSE Output
Related Offset per characterization(38) parameters
•
•
Added Temperature Sense Gain section
11/2008
5.0
Minor corrections to ESD Capability, (17), Cyclic Sense ON Time from Stop and Sleep Mode(47), Lin Bus Pin
(LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin (MISO), Low
Side Pins (LS1 and LS2), Digital/analog Pins (L1 and L2), Normal Request Mode, Sleep Mode, LIN Over-
temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions,
Lin Physical Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only,
SPI Protocol, Lx - Wake-up input x, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit
Updated Freescale form and style
•
•
2/2009
3/2009
Added explanation for pins Not Connected (NC).
6.0
7.0
•
•
Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 14.
Combined Complete Data sheet for Part Numbers MC33911BAC and MC34911BAC to the back of this data
3/2010
sheet.
8.0
9.0
•
•
Changed ESD Voltage for Machine Model from ±200 to ±150
No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to last
paragraph.
01/2014
33911
Analog Integrated Circuit Device Data
Freescale Semiconductor
91
Information in this document is provided solely to enable system and software implementers to use Freescale products.
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2014 Freescale Semiconductor, Inc.
Document Number: MC33911
Rev. 9.0
01/2014
相关型号：
MC34911G5AC
System Basis Chip, LIN, 1x 5.0V/60mA LDOs, DC Motor Predriver, Enhanced EMC, QFP 32, Tray
NXP
MC34911G5ACR2
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
NXP
MC34912BAC
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
NXP
MC34912BACR2
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
NXP
©2020 ICPDF网 联系我们和版权申明