MC56F83683VLH [NXP]
Digital Signal Processor;
| 型号： | MC56F83683VLH |
| 厂家： | 
NXP |
| 描述： | Digital Signal Processor 外围集成电路 |
| 文件： | 总60页 (文件大小：1069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MC56F836XXDS
Rev. 1.6, 09/2019
NXP Semiconductors
Data Sheet: Technical Data
MC56F836XXDS
MC56F836xx
Supports MC56F836xx
Features
• Communication interfaces
– Up to three high-speed queued SCI (QSCI) modules
with LIN slave functionality
– Up to two queued SPI (QSPI) modules
– Two I2C/SMBus ports
– One FlexCAN module, with Flexible Data-rate
(CAN-FD) supported
– One USB2.0 controller with integrated PHY
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. On a single chip,
each device combines the processing power of a DSP
and the functionality of an MCU, with a flexible set of
peripherals to support many target applications:
– Industrial control
– Home appliances
– General-purpose inverters
• Timers
– Smart sensors, fire and security systems
– Switched-mode power supply and power
management
– Two 16-bit quad timer (2 x 4 16-bit timer)
– Two Periodic Interval Timers (PITs)
• Security and integrity
– Power distribution systems
– Cyclic Redundancy Check (CRC) generator
– Windowed Computer operating properly (COP)
watchdog
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Uninterruptible power supplies (UPS)
– Solar inverter
– External Watchdog Monitor (EWM)
– Medical monitoring applications
• Clocks
• DSC based on 32-bit 56800EX core
– Up to 100 MIPS at 100 MHz core frequency
– DSP and MCU functionality in a unified, C-efficient
architecture
– On-chip relaxation oscillators: 200 kHz, and 48
MHz IRC
– Crystal / resonator oscillator
• System
• On-chip memory
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-Module Crossbar and Event Generator
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
– Up to 2×128 KB dual partition flash memory with
ECC protection
– Up to 64 KB data/program RAM
– Both on-chip flash memory and RAM can be
mapped into both program and data memory spaces
– 32 KB boot ROM supports boot from SCI, I2C and
CAN
• Operating characteristics
– Single supply: 2.7 V to 3.6 V
– 5 V–tolerant I/O (except for 3.3 V RESETB and
USB_DP/USB_DM pins)
– Operation ambient temperature: V temperature
option: -40°C to 105°C
• Analog
– Two high-speed, 8-ch external and 2-ch internal, 12-
bit ADCs with dynamic x1, x2, and x4
programmable amplifier
– Four analog comparators with integrated 8-bit DAC
references
• 100-pin LQFP, 80-pin LQFP, and 64-pin LQFP
packages
• Two standard FlexPWM modules with up to 2x8 PWM
outputs
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Overview............................................................................................3
5.2 Moisture handling ratings........................................................20
5.3 ESD handling ratings.............................................................. 20
5.4 Voltage and current operating ratings..................................... 20
General............................................................................................... 22
6.1 General characteristics............................................................ 22
6.2 AC electrical characteristics....................................................23
6.3 Nonswitching electrical specifications....................................23
6.4 Switching specifications..........................................................29
6.5 Thermal specifications............................................................ 30
Peripheral operating requirements and behaviors..............................31
7.1 Core modules...........................................................................31
7.2 System modules.......................................................................33
7.3 Clock modules.........................................................................33
7.4 Memories and memory interfaces...........................................35
7.5 Analog..................................................................................... 37
7.6 PWMs and timers....................................................................42
7.7 Communication interfaces.......................................................42
Design Considerations....................................................................... 48
8.1 Thermal design considerations................................................48
8.2 Electrical design considerations..............................................50
8.3 Power-on Reset design considerations....................................51
Obtaining package dimensions.......................................................... 52
1.1 Product Family........................................................................ 3
1.2 56800EX 32-bit Digital Signal Controller (DSC) core...........4
1.3 Operation Parameters.............................................................. 4
1.4 Interrupt Controller................................................................. 5
1.5 Peripheral highlights............................................................... 5
1.6 Block diagrams........................................................................11
Ordering parts.....................................................................................13
2.1 Determining valid orderable parts...........................................14
2.2 Part number list....................................................................... 14
Part identification...............................................................................14
3.1 Description.............................................................................. 14
3.2 Format..................................................................................... 14
3.3 Fields....................................................................................... 14
3.4 Example...................................................................................15
Terminology and guidelines...............................................................15
4.1 Definition: Operating requirement..........................................15
4.2 Definition: Operating behavior............................................... 16
4.3 Definition: Attribute................................................................16
4.4 Definition: Rating....................................................................16
4.5 Result of exceeding a rating....................................................17
4.6 Relationship between ratings and operating requirements......17
4.7 Guidelines for ratings and operating requirements................. 18
4.8 Definition: Typical value........................................................ 18
4.9 Typical value conditions......................................................... 19
Ratings................................................................................................19
5.1 Thermal handling ratings........................................................ 19
6
2
3
7
4
8
9
10 Pinout................................................................................................. 52
10.1 Signal Multiplexing and Pin Assignments..............................52
10.2 Pinout diagrams.......................................................................55
11 Product documentation.......................................................................58
12 Revision history................................................................................. 59
5
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Overview
1 Overview
1.1 Product Family
The following table lists major features, including features that differ among members of
the family. Features not listed are shared by all members of the family.
Table 1. MC56F836xx Family
Feature
MC56F83
686 683
689
663
Core frequency (MHz)
Flash memory (KB)
RAM (KB)
100
256
64
256
64
256
64
128
48
ROM (KB)
32
Yes
4
Inter-module Xbar
Event Generator
Windowed Watchdog
External Watchdog Monitor
eDMA
1
1
4-Ch
Internal OSC
200 kHz / 48 MHz
External Crystal Oscillator
Comparator
Yes (4 MHz ~ 16 MHz)
4
Cyclic ADC channels (External + Internal)
Standard PWM
Timers
2 x (8+2)
2 x 8 1
2 x 8
1 x 8 + 1 x 6 2
2 x 4
Periodic Interval Timers
CAN-FD
2
1
2
I2C/SMBus
QSCI
3
2
3
2
2
1
QSPI
USB 2.0 FS/LS
GPIO
1
—
82
68
54
Operating Temperature
LQFP package pin count
105℃
100 LQFP
80 LQFP
64 LQFP
1. The outputs of PWMB_3A and PWMB_3B are available through the on-chip inter-module crossbar (XBAR).
2. The outputs of PWMB are available through XBAR. PWMA_3A/PWMB_3B coupled with XB_OUT10/XB_OUT11.
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Overview
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation Parameters
• Up to 100 MHz operation mode
• Operation ambient temperature:
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Peripheral highlights
-40 oC to 105oC
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
1.5 Peripheral highlights
1.5.1 Flex Pulse Width Modulator (FlexPWM)
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• PWMA with accumulative fractional clock calculation
• Arbitrary PWM edge placement
• PWM outputs can be configured as complementary output pairs or independent
outputs
• Dedicated time-base counter with period and frequency control per submodule
• Independent top and bottom deadtime insertion for each complementary pair
• Independent control of both edges of each PWM output
• Enhanced input capture and output compare functionality on each input:
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Peripheral highlights
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
• Synchronization of submodule to external hardware (or other PWM) is supported.
• Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
• Multiple output trigger events can be generated per PWM cycle via hardware.
• Support for double-switching PWM outputs
• Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Individual software control of each PWM output
• All outputs can be programmed to change simultaneously via a FORCE_OUT event.
• PWMX pin can optionally output a third PWM signal from each submodule
• Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
• Direct phase shift controls among each submodule
• Trigger signal can share the same load frequency as reload signal in each submodule
1.5.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency up to 25 MHz, having period as low as 40 ns
• Single conversion time of 10 ADC clock cycles
• Additional conversion time of 8 ADC clock cycles
• Support of analog inputs for single-ended and differential (including unipolar
differential) conversions
• Sequential and parallel scan modes. Parallel mode includes simultaneous and
independent scan modes.
• Samples of each ADC have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for hardware-triggering and software-triggering conversions
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Peripheral highlights
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 8 conversion results.
• Current injection protection
1.5.3 Periodic Interrupt Timer (PIT) Modules
• 16-bit counter with programmable count modulo
• PIT0 is master and PIT1 is slave (if synchronizing both PITs)
• The output signals of both PIT0 and PIT1 are internally connected to a peripheral
crossbar module
• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from
Wait/Stop modes.
• In addition to its existing bus clock (up to 100 MHz), 3 alternate clock sources for
the counter clock are available:
• Crystal oscillator output
• 48 MHz/6
• On-chip low-power 200 kHz oscillator
1.5.4 Inter-Module Crossbar and Event Generator (EVTG) logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
comparators, quad-timers, FlexPWMs, EWM, and select I/O pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• The EVTG module mainly includes two parts: Two AND/OR/INVERT (known
simply as the AOI) modules and one configurable Flip-Flop. It supports the
generation of a configurable number of EVENT signals. The inputs are from crossbar
(XBAR) outputs, and the outputs feed to XBAR inputs.
1.5.5 Comparator
• Full rail-to-rail comparison range
• Support for high and low speed modes
• Selectable input source includes external pins and internal DACs
• Programmable output polarity
• 8-bit programmable DAC as a voltage reference per comparator
• Three programmable hysteresis levels
• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
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Peripheral highlights
1.5.6 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
1.5.7 Queued Serial Communications Interface (QSCI) modules with
LIN Slave Functionality
• Operating clock can be up to two times the CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
• 16-bit integer and 3-bit fractional baud rate selection
• Full-duplex or single-wire operation
• Programmable 8-bit or 9-bit data format
• Error detection capability
• Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
• Support for Local Interconnect Network (LIN) slave operation
1.5.8 Queued Serial Peripheral Interface (QSPI) modules
• Maximum 25 Mbit/s baud rate
• Selectable baud rate clock sources for low baud rate communication
• Baud rate as low as the maximum Baud rate / 4096
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four-word-deep FIFOs available on transmit and receive buffers
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB or LSB as first bit transmitted)
1.5.9 Inter-Integrated Circuit (I2C)/System Management Bus (SMBus)
modules
• Compatible with I2C bus standard
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Peripheral highlights
• Support for System Management Bus (SMBus) specification, version 2
• Multi-master operation
• General call recognition
• 10-bit address extension
• Start/Repeat and Stop indication flags
• Support for dual slave addresses or configuration of a range of slave addresses
• Programmable glitch input filter
1.5.10 Flexiable Controller Area Network (FlexCAN) module
This device utilizes the FlexCAN which is configured with 32 message buffers and DMA
support as well as CAN-FD (Flexible Data-rate). The FlexCAN module is a
communication controller implementing the CAN protocol according to the CAN 2.0B
protocol specification. The interface between CAN engine and CPU is done via a
mailbox system (Message Buffers) stored in embedded RAM.
• Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol
specification and CAN protocol specification, Version 2.0 B
• Supports DMA request
• Flexible message buffers (MBs), totaling 32 message buffers of 8 bytes data length
each, configurable as Rx or Tx
• SRAM array for 32 message buffer and individual mask registers.
1.5.11 Universal Serial Bus (USB) 2.0 controller
• Low Speed (1.5 Mbit/s) / Full Speed (12 Mbit/s)
• Device mode only in this device
• IRC48M with clock recovery block to eliminate the on-board crystal
• USB1.1 PHY included
1.5.12 Windowed Computer Operating Properly (COP) watchdog
• Programmable windowed timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
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Clock sources
• System bus (IPBus up to 100 MHz)
• 48 MHz/6
• Support for interrupt generation
1.5.13 External Watchdog Monitor (EWM)
• Monitors external circuit as well as the software flow
• Programmable timeout period
• Interrupt capability prior to timeout
• Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 48 MHz/6
1.5.14 Power supervisor
• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;
CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical warn low-voltage interrupt (LVI 2.2 V)
• Peripheral low-voltage warning interrupt (LVI 2.7 V)
1.5.15 Phase-locked loop
• Output frequency range is optimized from 150 MHz to 450 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
• Detection of loss of lock and loss of reference clock
• Ability to power down
1.5.16 Clock sources
1.5.16.1 On-chip oscillators
• IRC48M
• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT
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Clock sources
1.5.16.2 Crystal oscillator
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.5.17 Cyclic Redundancy Check (CRC) generator
• Hardware 16/32-bit CRC generator
• High-speed hardware CRC calculation
• Programmable initial seed value
• Programmable 16/32-bit polynomial
• Error detection for all single, double, odd, and most multi-bit errors
• Option to transpose input data or output data (CRC result) bitwise or bytewise,1
which is required for certain CRC standards
• Option for inversion of final CRC result
1.5.18 General Purpose I/O (GPIO)
• 5 V tolerance (except RESETB and USB_DP/USB_DM pins)
• Individual control of peripheral mode or GPIO mode for each pin
• Programmable push-pull or open drain output
• Configurable pullup or pulldown on all input pins
• All pins (except JTAG, RESETB and USB_DP/USB_DM pins) default to be GPIO
inputs
• 2 mA / 9 mA capability
• Controllable output slew rate
1.6 Block diagrams
The 56800EX core is based on a modified dual Harvard-style architecture, consisting of
three execution units operating in parallel, and allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
enable straightforward generation of efficient and compact code for the DSP and control
functions. The instruction set is also efficient for C compilers, to enable rapid
development of optimized control applications.
1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user
software must perform the bytewise transposition.
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Clock sources
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the
56800EX system buses communicate with internal memories, and the IPBus interface
and the internal connections among the units of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
DSP56800EX Core
Program Control Unit
ALU1
ALU2
Address
Generation
Unit
PC
LA
LA2
HWS0
HWS1
FIRA
Instruction
Decoder
R0
R1
(AGU)
R2
Interrupt
Unit
Program
Memory
M01
N3
R3
OMR
R4
SR
LC
LC2
R5
Looping
Unit
N
SP
FISR
XAB1
XAB2
PAB
Data/
Program
RAM
PDB
CDBW
CDBR
XDB2
A2
B2
C2
D2
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Bit-
Manipulation
Unit
IPBus
Interface
Data
Y
Enhanced
OnCE™
Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU Multi-Bit Shifter
Figure 1. 56800EX basic block diagram
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Ordering parts
USB RAM
2KB
Boot ROM
32KB
JTAG
Program Bus
Core Data Bus
EOnCE
S3b
M0
56800EX CPU
Program/Data Flash
Up to 256KB
Program
Controller
(PC)
Address
Generation
Unit (AGU)
S0
S1
M1
M2
Secondary Data Bus
dual partition flash
memory with ECC
4
Arithmetic
Logic Unit
(ALU)
Bit
Manipulation
Unit
M4
M3
Data/Program RAM
Up to 64KB
S3a S2
eDMA Controller
Watchdog (COP)
Interrupt Controller
Internal 48MHz
Crysral OSC
Power Management
Controller (PMC)
Internal 200kHz
PLL
System Integration
Module (SIM)
Periodic Interrupt
Timer (PIT) 0,1
CRC
Peripheral Bus
QSCI
0,1,2
I2C
0,1
QSPI
0,1
Quad Timer
A & B
USB
2.0
FlexPWM B
FlexCAN
FlexPWM A
Inter ModuleCrossbarInputs
Inter Module Crossbar Outputs
Event
Generator
GPIO & Peripheral MUX
Inter-Module
Crossbar
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
Package
Pins
Compartors With
8bit DAC A,B,C,D
ADC B
12Bit
ADC A
12Bit
EWM
Peripheral Bus
Figure 2. System diagram
2 Ordering parts
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Part identification
2.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F83
2.2 Part number list
The following table shows a part number list for this device.
Table 2. Part numbers
Part Number
MC56F83689VLL
Flash Size
Temperature
Package
256 KB
256 KB
256 KB
128 KB
105℃
105℃
105℃
105℃
100 LQFP
80 LQFP
64 LQFP
64 LQFP
MC56F83686VLK
MC56F83683VLH
MC56F83663VLH
3 Part identification
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.2 Format
Part numbers for this device have the following format: Q 56F8 3 C F P T PP N
3.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
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Terminology and guidelines
Values
Field
Description
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
3
DSC subfamily
• 3
C
F
Maximum CPU frequency (MHz)
Primary program flash memory size
• 6 = 100 MHz
• 6 = 128 KB
• 8 = 256 KB
P
Pin count
• 3 = 64
• 6 = 80
• 9 = 100
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LH = 64LQFP
• LK = 80LQFP
• LL = 100LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
3.4 Example
This is an example part number: MC56F83689VLL
4 Terminology and guidelines
4.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
4.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
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Terminology and guidelines
4.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
4.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
4.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
4.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
4.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
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Terminology and guidelines
4.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
4.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
4.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
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NXP Semiconductors
17
Terminology and guidelines
4.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
4.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
4.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
4.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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NXP Semiconductors
Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
4.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
5 Ratings
5.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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NXP Semiconductors
19
Ratings
5.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 3. ESD/Latch-up Protection
Characteristic1
Min
Max
Unit
Notes
ESD for Human Body
–2000
+2000
V
2
5
Model (VHBM
ESD for Charge Device
Model (VCDM
)
–500
–750
–100
+500 3
+750 4
+100
V
)
Latch-up current at TA=
85°C (ILAT) (V part)
mA
6
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
2. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
3. All pins except the corner pins
4. Corner pins only
5. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
6. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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NXP Semiconductors
Ratings
5.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device
reliability or cause permanent damage to the device.
NOTE
If the voltage difference between VDD and VDDA or VSS and
VSSA is too large, then the device can malfunction or be
permanently damaged. The restrictions are:
• At all times, it is recommended that the voltage
difference of VDD - VSS be within +/-200 mV of the
voltage difference of VDDA - VSSA, including power
ramp up and ramp down; see additional requirements in
Table 5. Failure to do this recommendation may result in a
harmful leakage current through the substrate, between the
VDD/VSS and VDDA/VSSA pad cells. This harmful
leakage current could prevent the device from operating
after power up.
• At all times, to avoid permanent damage to the part, the
voltage difference between VDD and VDDA must
absolutely be limited to 0.3 V; see Table 4.
• At all times, to avoid permanent damage to the part, the
voltage difference between VSS and VSSA must
absolutely be limited to 0.3 V; see Table 4.
Table 4. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Supply Voltage Range
Symbol
VDD
Notes1
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.4
-0.3
—
Max
4.0
4.0
4.0
0.3
0.3
5.5
4.0
4.0
4.0
-5.0
20.0
25
Unit
V
Analog Supply Voltage Range
ADC High Voltage Reference
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
VDDA
VREFHx
ΔVDD
ΔVSS
VIN
V
V
V
V
Pin Group 1
Pin Group 2
Pin Group 4
Pin Group 3
V
RESET Input Voltage Range
VIN_RESET
VOSC
VINA
V
Oscillator Input Voltage Range
V
Analog Input Voltage Range
V
Input clamp current, per pin (VIN < VSS - 0.3 V), 2, 3
Output clamp current, per pin4
VIC
mA
mA
mA
VOC
—
Contiguous pin DC injection current—regional limit sum
of 16 contiguous pins
IICont
-25
Output Voltage Range (normal push-pull mode)
VOUT
Pin Group 1, 2
-0.3
4.0
V
Table continues on the next page...
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NXP Semiconductors
21
General
Table 4. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V) (continued)
Characteristic
Symbol
Notes1
Min
-0.3
-0.3
Max
5.5
Unit
V
Output Voltage Range (open drain mode)
RESET Output Voltage Range
VOUTOD
Pin Group 1
Pin Group 2
VOUTOD_RE
4.0
V
SET
Ambient Temperature
TA
V temperature
V temperature
-40
-40
-55
105
125
150
°C
°C
°C
Junction Temperature
Tj
Storage Temperature Range (Extended Industrial)
TSTG
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
2. Continuous clamp current
3. All 5 volt tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode
connection to VDD. If VIN greater than VDIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current
limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required.
4. I/O is configured as push-pull mode.
6 General
6.1 General characteristics
The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTL-
compatible digital inputs, except 3.3 V for RESET, USB_DP/USB_DM pins. The term
“5 V–tolerant” refers to the capability of an I/O pin, built on a 3.3 V–compatible process
technology, to withstand a voltage up to 5.5 V without damaging the device.
5 V–tolerant I/O is desirable because many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–
compatible I/O voltage levels . This 5 V–tolerant capability therefore offers the power
savings of 3.3 V I/O levels combined with the ability to receive 5 V levels without
damage.
Absolute maximum ratings in Table 4 are stress ratings only, and functional operation at
the maximum is not guaranteed. Stress beyond these ratings may affect device reliability
or cause permanent damage to the device.
Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in Table 4 over the following supply ranges: VSS=VSSA=0V,
VDD=VDDA=3.0V to 3.6V, CL≤50 pF, fOP=100MHz.
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NXP Semiconductors
General
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-
impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
6.2 AC electrical characteristics
Tests are conducted using the input levels specified in Table 7. Unless otherwise
specified, propagation delays are measured from the 50% to the 50% point, and rise and
fall times are measured between the 10% and 90% points, as shown in Figure 3.
Low
High
V
IH
90%
50%
10%
Midpoint1
Fall Time
Input Signal
V
IL
Rise Time
The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 3. Input signal measurement references
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data1
Data2 Valid
Data2
Data3 Valid
Data3
Data
Data Invalid State
Tri-stated
Data Active
Data Active
Figure 4. Signal states
6.3 Nonswitching electrical specifications
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23
General
6.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is monotonically and greater
than 100 μs.
Table 5. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Characteristic
Symbol
VDD, VDDA
VREFHA
VREFHB
ΔVDD
ΔVSS
Notes1
Min
Typ
Max
3.6
Unit
V
Supply voltage
2.7
3.3
ADC (Cyclic) Reference Voltage High
VDDA
V
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Input Voltage High (digital inputs)
RESET Input Voltage High
-0.2
0
0
0.2
0.2
V
V
V
V
V
V
-0.2
VIH
Pin Group 1
Pin Group 2
0.7 x VDD
0.7 x VDD
5.5
VIH_RESET
VIL
—
VDD
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
XTAL driven by an external clock source
Oscillator Input Voltage Low
Pin Groups 1, 2
Pin Group 4
0.3 x VDD
VDD + 0.3
VIHOSC
2.0
VILOSC
IOH
Pin Group 4
-0.3
0.8
V
Output Source Current High (at VOH min.)
• Programmed for low drive strength
Pin Group 1
Pin Group 1
—
—
-2
-9
mA
• Programmed for high drive strength
Output Source Current Low (at VOL max.)2, 3
• Programmed for low drive strength
IOL
Pin Groups 1, 2
Pin Groups 1, 2
—
—
2
9
mA
• Programmed for high drive strength
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
2. Total IO sink current and total IO source current are limited to 75 mA each
3. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive
injection currents of 16 contiguous pins—is 25 mA.
6.3.2 LVD and POR operating requirements
Table 6. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic
Symbol
POR
Min
Typ
2.0
Max
Unit
V
POR Assert Voltage1
POR Release Voltage2
LVI_2p7 Threshold Voltage
POR
2.7
2.73 3
V
V
Table continues on the next page...
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NXP Semiconductors
General
Table 6. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
(continued)
Characteristic
Symbol
Min
Typ
Max
Unit
LVI_2p2 Threshold Voltage
2.23 3
V
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
3. Value is based on the fact that the bandgap is trimmed.
6.3.3 Voltage and current operating behaviors
The following table provides information about power supply requirements and I/O pin
characteristics.
Table 7. DC Electrical Characteristics at Recommended Operating Conditions
Characteristic
Output Voltage High
Output Voltage Low
Symbol
VOH
Notes 1
Min
VDD - 0.5
—
Typ
—
Max
—
Unit
V
Test Conditions
IOH = IOHmax
Pin Group 1
VOL
Pin Groups
1, 2
—
0.5
V
IOL = IOLmax
Digital Input Current High
IIH
Pin Group 1
Pin Group 2
—
0
+/- 2.5
µA
VIN = 2.4 V to 5.5 V
VIN = 2.4 V to VDD
pull-up enabled or
disabled
Comparator Input Current
High
IIHC
IIHOSC
IIL
Pin Group 3
Pin Group 3
—
—
0
0
+/- 2
+/- 2
µA
µA
µA
VIN = VDDA
VIN = VDDA
VIN = 0V
Oscillator Input Current
High
Digital Input Current Low
Pin Groups
1, 2
—
0
+/- 0.5
2, 3
pull-up disabled
Internal Pull-Up
Resistance
RPull-Up
RPull-Down
IILC
20
20
—
—
—
—
—
0
50
kΩ
kΩ
µA
µA
µA
—
—
Internal Pull-Down
Resistance
50
Comparator Input Current
Low
Pin Group 3
Pin Group 3
+/- 2
+/- 2
+/- 1
VIN = 0V
VIN = 0V
—
Oscillator Input Current
Low
Output Current 2, 3
IILOSC
IOZ
0
Pin Groups
1, 2
0
High Impedance State
Schmitt Trigger Input
Hysteresis
VHYS
Pin Groups 0.06 × VDD
1, 2
—
—
V
—
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
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NXP Semiconductors
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General
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
2. See the following figure "IIN/IOZ vs. VIN (typical; pull-up & pull-down disabled) (design simulation)" .
3. To minimize the excessive leakage ( > 1 μA) current from digital pin, input signal should NOT stay between 1.1 V and 0.9
× VDD for prolonged time.
V (volt)
Figure 5. IIN/IOZ vs. VIN (typical; pull-up & pull-down disabled) (design simulation)
6.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 8. Reset, stop, wait, and interrupt timing
Characteristic
Symbol
Typical Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
tRDA
tIF
16 1
865 × TOSC + 8 × T
361.3
—
ns
ns
ns
—
—
—
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
570.9
1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns. Recommended a capacitor of up to 0.1 µF on RESET.
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NXP Semiconductors
General
NOTE
In Table 8, T = system clock cycle and TOSC = oscillator clock
cycle. For an operating frequency of 100MHz, T=10 ns. At 4
MHz (used coming out of reset and stop modes), T=250 ns.
Table 9. Power mode transition behavior
Symbol
Description
Typical
Max
Unit Notes1
TPOR
After a POR event, the amount of delay from when VDD reaches
2.7 V to when the first instruction executes (over the operating
temperature range).
430
495
µs
STOP mode to RUN mode
LPS mode to LPRUN mode
VLPS mode to VLPRUN mode
WAIT mode to RUN mode
8.61
358
9.90
411
µs
µs
µs
µs
µs
µs
2
3
4
5
3
4
1090
0.347
351
1254
0.399
404
LPWAIT mode to LPRUN mode
VLPWAIT mode to VLPRUN mode
1070
1231
1. Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from
respective stop/wait mode.
2. Clock configuration: CPU clock=4 MHz. System clock source is from 48 MHz/6 in normal mode.
3. CPU clock = 100 kHz . Exit by an interrupt on PORTA GPIO.
4. Using 64 kHz external clock; CPU Clock = 32 kHz. Exit by an interrupt on PORTA GPIO.
5. Clock configuration: CPU and system clocks= 100 MHz. Bus Clock = 100 MHz. Exit by interrupt on PORTA GPIO
6.3.5 Power consumption operating behaviors
Table 10. Current Consumption (mA)
Mode
Maximum
Frequency
Conditions1
Typical at
3.3 V, 25 °C
Maximum
at 3.6 V,
105 °C
1
1
IDD
IDDA IDD
6.1
IDDA
RUN
100 MHz
• 100 MHz Core and Peripheral clock
• Regulators are in full regulation
• Internal Oscillator on
46.7
65.6
8.8
• PLL powered on
• Continuous MAC instructions with fetches from Program
Flash
• All peripheral modules enabled.
• ADC/DAC ( all 8-bit DACs) powered on and clocked
• Comparator powered on
WAIT
100 MHz
• 100 MHz Core and Peripheral clock
• Regulators are in full regulation
• Internal Oscillator on
21.8
—
37.5
—
• PLL powered on
• Processor Core in WAIT state
• All Peripheral modules enabled.
• ADC/Comparator powered off
Table continues on the next page...
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NXP Semiconductors
27
General
Table 10. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions1
Typical at
3.3 V, 25 °C
Maximum
at 3.6 V,
105 °C
1
1
IDD
IDDA IDD
IDDA
STOP
4 MHz
• 4 MHz Core and Peripheral clock
• Regulators are in full regulation
• Internal Oscillator on
5.2
—
20.0
—
• PLL powered off
• Processor Core in STOP state
• All peripheral module and core clocks are off
• ADC/Comparator powered off
LPRUN
2 MHz
• 100 kHz Core and Peripheral clock from Relaxation
Oscillator's (ROSC) low speed clock
• 48 MHz Internal Oscillator disabled
• Regulators are in standby
1.1
—
15.0
—
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except cyclic ADCs. all 8-
bit DACs enabled.
• Simple loop with running from platform instruction buffer
LPWAIT
LPSTOP
VLPRUN
2 MHz
• 100 kHz Core and Peripheral clock from Relaxation
Oscillator's (ROSC) low speed clock
• 48 MHz Internal Oscillator disabled
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except cyclic ADCs. all 8-
bit DACs enabled.
1.1
1.0
0.6
—
—
—
15.0
14.0
12.0
—
—
—
• Processor core in wait mode
2 MHz
• 100 kHz Core and Peripheral clock from Relaxation
Oscillator's (ROSC) low speed clock
• 48 MHz Internal Oscillator disabled
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral modules
disabled and clocks gated off
• Processor core in stop mode
200 kHz
• 32 kHz Core and Peripheral clock from a 64 kHz external
clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• Repeat NOP instructions
• All peripheral modules, except COP and EWM, disabled
and clocks gated off
• Simple loop running from platform instruction buffer
VLPWAIT
200 kHz
• 32 kHz Core and Peripheral clock from a 64 kHz external
clock source
0.6
—
12.0
—
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
Table continues on the next page...
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NXP Semiconductors
General
Table 10. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions1
Typical at
3.3 V, 25 °C
Maximum
at 3.6 V,
105 °C
1
1
IDD
IDDA IDD
IDDA
• All peripheral modules, except COP, disabled and clocks
gated off
• Processor core in wait mode
VLPSTOP
200 kHz
• 32 kHz Core and Peripheral clock from a 64 kHz external
clock source
0.6
—
12.0
—
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby.
• Small regulator is disabled.
• PLL disabled
• All peripheral modules, except COP, disabled and clocks
gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads.
6.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
6.3.7 Capacitance attributes
Table 11. Capacitance attributes
Description
Symbol
CIN
Min.
—
Typ.
10
Max.
—
Unit
pF
Input capacitance
Output capacitance
COUT
—
10
—
pF
6.4 Switching specifications
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General
6.4.1 Device clock specifications
Table 12. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYSCLK
Device (system and core) clock frequency
• using relaxation oscillator
0.001
0
100
100
100
MHz
MHz
• using external clock source
fBUS
Bus clock
—
6.4.2 General switching timing
Table 13. Switching timing
Symbol Description
GPIO pin interrupt pulse width1
Min
Max
Unit
Notes
1.5
IP Bus
Clock
Cycles
2
Synchronous path
Port rise and fall time (high drive strength), slew disabled,
2.7V ≤ VDD ≤ 3.6V
5.5
1.5
8.2
3.2
15.1
6.8
ns
ns
ns
ns
3
4
3
4
Port rise and fall time (high drive strength), slew enabled,
2.7V ≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength), slew disabled, 2.7V
≤ VDD ≤ 3.6V
17.8
9.2
Port rise and fall time (low drive strength), slew enabled, 2.7V
≤ VDD ≤ 3.6V
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. The greater synchronous and asynchronous timing must be met.
3. 75 pF load
4. 15 pF load
6.5 Thermal specifications
6.5.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol
TJ
Description
Grade
Min
–40
–40
Max
125
105
Unit
°C
Die junction temperature
Ambient temperature
V
V
TA
°C
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NXP Semiconductors
Peripheral operating requirements and behaviors
6.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type
Symbol
Description
64 LQFP
80 LQFP
100 LQFP
Unit
Notes
1
Four-layer
(2s2p)
RθJA
Thermal
44
42
46
°C/W
2
2
resistance,
junction to
ambient
(natural
convection)
Single-layer
(1s)
RθJC
Thermal
resistance,
junction to
case
14
13
16
°C/W
°C/W
—
ΨJT
Thermal
1.2
1.0
1.4
characterizati
on parameter,
junction to
package top
outside
center
(natural
convection)
1. Thermal test board meets JEDEC specification for this package (JESD51-9).
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
7 Peripheral operating requirements and behaviors
7.1 Core modules
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31
Peripheral operating requirements and behaviors
7.1.1 JTAG timing
Table 15. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
TCK clock pulse width
fOP
tPW
tDS
tDH
tDV
tTS
DC
50
5
SYS_CLK/16
MHz
ns
Figure 6
Figure 6
Figure 7
Figure 7
Figure 7
Figure 7
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
5
ns
—
—
ns
ns
1/f
OP
t
t
PW
PW
V
IH
V
V
V
M
M
TCK
(Input)
IL
V
= V + (V – V )/2
IL IH IL
M
Figure 6. Test clock input timing diagram
TCK
(Input)
t
t
DH
DS
TDI
TMS
Input Data Valid
(Input)
t
DV
TDO
(Output)
Output Data Valid
t
TS
TDO
(Output)
Figure 7. Test access port timing diagram
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7.2 System modules
7.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper
operations, the voltage regulator requires using at minimum 4.4 µF capacitors in total on
each VCAP pin. Ceramic and tantalum capacitors tend to provide better performance
tolerances. The output voltage can be measured directly on the VCAP pin. The
specifications for this regulator are shown in Table 16.
Table 16. Regulator 1.2 V parameters
Characteristic
Output Voltage 1
Short Circuit Current 2
Symbol
VCAP
ISS
Min
1.08
—
Typ
1.22
600
—
Max
1.32
—
Unit
V
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
1
minute
1. Value is after trim
2. Guaranteed by design
Table 17. Bandgap electrical specifications
Characteristic
Reference Voltage (after trim)
Symbol
Min
Typ
Max
Unit
VREF
—
1.221
—
V
1. Typical value is trimmed at 25℃. There could be 50 mV variation due to temperature change.
7.3 Clock modules
7.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 18. External clock operation timing requirements
Characteristic
Symbol
fosc
Min
Typ
Max
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock pulse width2
External clock input rise time3
—
—
50
tPW
8
—
trise
—
—
—
—
1
ns
External clock input fall time4
tfall
—
1
—
ns
Input high voltage overdrive by an external clock
Input low voltage overdrive by an external clock
Vih
0.7×VDD
—
V
Vil
0.3×VDD
V
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System modules
1. See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.
V
IH
External
Clock
90%
50%
10%
90%
50%
10%
t
V
IL
t
fall
rise
t
t
PW
PW
Note: The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 8. External clock timing
7.3.2 Phase-Locked Loop timing
Table 19. Phase-Locked Loop timing
Characteristic
PLL input reference frequency1
PLL output frequency2
Symbol
fref
Min
8
Typ
8
Max
Unit
MHz
MHz
µs
16
450
81
fop
150
30
—
PLL lock time3
tplls
Allowed Duty Cycle of input reference
tdc
40
50
60
%
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 100 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
7.3.3 External crystal or resonator requirement
Table 20. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
7.3.4 200 kHz RC Oscillator Timing
Table 21. 200 kHz RC Oscillator Oscillator Electrical Specifications
Characteristic
Symbol
Min
193
48
Typ
Max
206
52
Unit
200 kHz Output Frequency1
TA: -40°C to 105°C
200 kHz output
200
10
kHz
µs
Stabilization Time
Output Duty Cycle
tstab
50
%
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NXP Semiconductors
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1. Frequency after factory trim
7.3.5 IRC48M specifications
Table 22. IRC48M specifications
Symbol
VDD
Description
Min.
2.7
—
Typ.
—
Max.
3.6
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
400
48
500
—
μA
Internal reference frequency
—
MHz
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency over
temperature
—
—
0.5
—
1.0
0.1
%firc48m
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency over
%fhost
1
2
voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is
enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function
(USB_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). Only applicable
to devices/packages that contain USB.
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by setting:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1
7.4 Memories and memory interfaces
7.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
7.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm8
Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk128k Erase Flash Block high-voltage time for 128 KB
—
13
113
904
ms
ms
1
1
—
104
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System modules
1. Maximum time based on expectations at cycling end-of-life.
7.4.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 256 KB program flash
Min.
Typ.
Max.
Unit
Notes
trd1blk1k
—
—
1.0
ms
trd1sec2k Read 1s Section execution time (2 KB flash)
—
—
—
—
—
—
—
90
75
95
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
• 128 KB program flash
40
tpgm8
150
2
tersblk128k
—
110
925
ms
tersscr
trd1all
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
15
—
115
2.6
ms
ms
μs
2
1
trdonce
—
30
tpgmonce Program Once execution time
90
—
μs
tersall
tvfykey
tersallu
Erase All Blocks execution time
225
—
1850
30
ms
μs
2
1
2
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
225
1850
ms
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
7.4.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
IDD_ERS
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
7.4.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
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NXP Semiconductors
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1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
7.5 Analog
7.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters
Table 27. 12-bit ADC Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Recommended Operating Conditions
Supply Voltage1
VDDA
Vrefhx
fADCCLK
RAD
3
3.3
3.6
VDDA
25
V
V
VREFH (in external reference mode)
ADC Conversion Clock2
Conversion Range3
VDDA-0.6
0.6
MHz
V
VREFH – VREFL
VREFH
Fully Differential
– (VREFH – VREFL
VREFL
)
Single Ended/Unipolar
Input Voltage Range (per input)4
External Reference
VADIN
V
VREFL
VSSA
VREFH
VDDA
Internal Reference
Timing and Power
Conversion Time5
tADC
8
ADC Clock
Cycles
ADC Power-Up Time (from adc_pdn)
ADC RUN Current (per ADC block)
tADPU
60
ADC Clock
Cycles
IADRUN
2.45
0.1
mA
µA
ADC Powerdown Current (adc_pdn
enabled)
IADPWRDWN
VREFH Current (in external mode)
Accuracy (DC or Absolute)
Integral non-Linearity6
Differential non-Linearity6
Monotonicity
IVREFH
190
225
µA
INL
1.5
0.6
2.2
0.8
LSB7
LSB7
DNL
GUARANTEED
Offset8
VOFFSET
mV
5
5
Fully Differential
Single Ended/Unipolar
Gain Error
EGAIN
SNR
0.996 to
1.004
0.990 to 1.010
AC Specifications9
Signal to Noise Ratio
68
dB
Table continues on the next page...
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System modules
Table 27. 12-bit ADC Electrical Specifications (continued)
Characteristic
Symbol
THD
Min
Typ
71
Max
Unit
dB
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to Noise plus Distortion
Effective Number of Bits
Gain = 1x (Fully Differential)
Gain = 2x (Fully Differential)
Gain = 4x (Fully Differential)
Gain = 1x (Single Ended/Unipolar)
Gain = 2x (Single Ended/Unipolar)
Gain = 4x (Single Ended/Unipolar)
Variation across channels10
ADC Inputs
SFDR
SINAD
ENOB
72
dB
66
dB
—
bits
10.7
10.3
9.9
10.2
10.0
9.7
0.1
Input Leakage Current
Temperature sensor slope
Temperature sensor voltage at 25 °C
Disturbance
IIN
1
nA
mV/°C
V
TSLOPE
VTEMP25
-2.96
1.59
Input Injection Current 11
Channel to Channel Crosstalk12
Memory Crosstalk13
IINJ
3
mA
dB
dB
pF
ISOXTLK
MEMXTLK
CADI
-82
-71
Input Capacitance
1.2
2.4
4.8
Sampling Capacitor
• 1x mode
• 2x mode
• 4x mode
1. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed
2. ADC clock duty cycle is 45% ~ 55%
3. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
4. In unipolar mode, positive input must be ensured to be always greater than negative input.
5. First conversion takes 10 clock cycles.
6. INL/DNL is measured from VIN = VREFL to VIN = VREFH using Histogram method at x1 gain setting
7. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain Setting
8. Offset measured at 2048 code
9. Measured converting a 1 kHz input full scale sine wave; the measurement mode is Gain = 1x (Fully Differential).
10. When code runs from internal RAM
11. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
12. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk)
13. From a previously sampled channel with 50 kHz full-scale input to the channel being sampled with DC input (memory
crosstalk).
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7.5.1.1 Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and both S1 and S2 are dependent on
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
+
ohm
+Resistor
50
(ADC ClockRate) x CADI
NOTE
Resistor=1200 ohm@gain1×, or 730 ohm@gain2×, or 500
ohm@gain4×
C1
Channel Mux
equivalent resistance
S1
50 ESD
Resistor
Analog Input
C1
C1
Resistor(value see the note)
S1
S1
S/H
1
2
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock
frequency
S1
S2
Figure 9. Equivalent circuit for A/D loading
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System modules
7.5.2 CMP and 8-bit DAC electrical specifications
Table 28. Comparator and 8-bit DAC electrical specifications
Symbol
VDD
Description
Min.
3.0
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, high-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
300
36
μA
μA
V
—
—
VSS
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis
• CR0[HYSTCTR] = 001
—
mV
VH
—
—
—
—
5
13
48
mV
mV
mV
mV
• CR0[HYSTCTR] = 012
25
55
80
• CR0[HYSTCTR] = 102
105
148
• CR0[HYSTCTR] = 112
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
25
—
0.5
70
V
V
—
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)3
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)3
—
60
200
ns
Analog comparator initialization delay4
—
—
—
40
7
—
—
—
μs
μA
V
IDAC8b
8-bit DAC current adder (enabled)
Vreference 8-bit DAC reference inputs, Vin1 and Vin2
VDD
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
–1
–1
—
—
1
1
LSB5
LSB
DNL
1. Measured with input voltage range limited to 0 to VDD
2. Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8
3. Input voltage range: 0.1VDD≤Vin≤0.9VDD, step = 100mV, across all temperature. Does not include PCB and PAD delay.
4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/256
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Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
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PWMs and timers
7.6 PWMs and timers
7.6.1 PWM characteristics
Table 29. PWM timing parameters
Characteristic
Symbol
Min
Typ
Max
Unit
MHz
ns
PWM clock frequency
100
Delay for fault input activating to PWM output deactivated
1
33
7.6.2 Quad Timer timing
Parameters listed are guaranteed by design.
Table 30. Timer timing
Characteristic
Timer input period
Symbol
PIN
Min1
2T + 6
1T + 3
20
Max
—
Unit
ns
See Figure
Figure 12
Figure 12
Figure 12
Figure 12
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
10
—
ns
1. T = clock cycle. For 100 MHz operation, T = 10 ns.
Timer Inputs
P
P
INHL
INHL
P
IN
Timer Outputs
P
P
OUTHL
OUTHL
P
OUT
Figure 12. Timer timing
7.7 Communication interfaces
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NXP Semiconductors
PWMs and timers
7.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design.
Table 31. SPI timing
Characteristic
Cycle time
Master
Symbol
Min
Max
Unit
See Figure
tC
Figure 13
Figure 14
Figure 15
Figure 16
Figure 16
35
35
—
—
ns
ns
Slave
Enable lead time
Master
tELD
tELG
tCH
—
—
—
ns
ns
17.5
Slave
Enable lag time
Master
Figure 16
—
—
—
ns
ns
17.5
Slave
Clock (SCK) high time
Master
Figure 13
Figure 14
Figure 15
Figure 16
Figure 16
16.6
16.6
—
—
ns
ns
Slave
Clock (SCK) low time
tCL
16.6
16.6
—
—
ns
ns
Master
Slave
Data set-up time required for inputs
tDS
Figure 13
Figure 14
Figure 15
Figure 16
Figure 13
Figure 14
Figure 15
Figure 16
Figure 16
16.5
1
—
—
ns
ns
Master
Slave
Data hold time required for inputs
tDH
1
3
—
—
ns
ns
Master
Slave
Access time (time to data active
from high-impedance state)
tA
5
5
—
—
ns
ns
Slave
Disable time (hold time to high-
impedance state)
tD
Figure 16
Slave
Data valid for outputs
Master
tDV
Figure 13
Figure 14
Figure 15
Figure 16
—
—
5
ns
ns
15
Slave (after enable edge)
Table continues on the next page...
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PWMs and timers
Table 31. SPI timing (continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Figure 13
Figure 14
Figure 15
Figure 16
Figure 13
Figure 14
Figure 15
Figure 16
Figure 13
Figure 14
Figure 15
Figure 16
Data invalid
Master
tDI
0
0
—
—
ns
ns
Slave
Rise time
Master
Slave
tR
—
—
1
1
ns
ns
Fall time
Master
Slave
tF
—
—
1
1
ns
ns
SS
(Input)
SS is held high on master
t
C
t
R
t
F
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
R
t
CL
SCLK (CPOL = 1)
(Output)
t
t
DH
CH
t
DS
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t (ref)
DI
t
DI
DV
MOSI
(Output)
Master MSB out
Bits 14–1
Master LSB out
t
t
R
F
Figure 13. SPI master timing (CPHA = 0)
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NXP Semiconductors
PWMs and timers
SS
(Input)
SS is held High on master
t
C
t
F
t
R
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
CL
SCLK (CPOL = 1)
(Output)
t
CH
t
DS
t
R
t
DH
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t
(ref)
DI
t
DV
t (ref)
DV
DI
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t
t
R
F
Figure 14. SPI master timing (CPHA = 1)
SS
(Input)
t
C
t
F
t
ELG
t
CL
t
R
SCLK (CPOL = 0)
(Input)
t
CH
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
CH
t
F
t
t
A
R
t
D
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DS
DV
t
t
DI
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 15. SPI slave timing (CPHA = 0)
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PWMs and timers
SS
(Input)
t
F
t
C
t
R
t
CL
SCLK (CPOL = 0)
(Input)
t
CH
t
ELG
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
t
DV
CH
t
R
t
t
D
t
A
F
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DV
DS
t
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 16. SPI slave timing (CPHA = 1)
7.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design.
Table 32. SCI timing
Characteristic
Baud rate1
Symbol
BR
Min
—
Max
Unit
Mbit/s
μs
See Figure
—
(fMAX/16)
1.04/BR
1.04/BR
RXD pulse width
TXD pulse width
RXDPW
TXDPW
0.965/BR
0.965/BR
Figure 17
Figure 18
μs
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
-14
14
2
%
%
—
—
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
Minimum break character length
TBREAK
13
11
—
—
Master
node bit
periods
—
—
Slave node
bit periods
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.200 MHz
depending on part number) or 2x bus clock (max. 200 MHz) for the devices.
MC56F836xx, Rev. 1.6, 09/2019
46
NXP Semiconductors
PWMs and timers
RXD
SCI receive
data pin
RXD
PW
(Input)
Figure 17. RXD pulse width
TXD
SCI transmit
data pin
TXD
PW
(output)
Figure 18. TXD pulse width
7.7.3 Inter-Integrated Circuit Interface (I2C) timing
Table 33. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Minimum Maximum
Unit
SCL Clock Frequency
fSCL
0
0
400
—
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
Data set-up time
5,
5,
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
6
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
300
20 +0.1Cb
300
ns
6
tSU; STO
tBUF
4
—
—
0.6
1.3
—
—
µs
µs
Bus free time between STOP and
START condition
4.7
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF.
4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
47
Design Considerations
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 19. Timing definition for fast and standard mode devices on the I2C bus
7.7.4 FlexCAN switching specifications
See the "General switching timing" section.
8 Design Considerations
8.1 Thermal design considerations
An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA × PD)
where
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
PD = Power dissipation in the package (W).
The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
MC56F836xx, Rev. 1.6, 09/2019
48
NXP Semiconductors
Design Considerations
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-
case thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA
where
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W).
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (ΨJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = hermal characterization parameter (°C/W)
PD = Power dissipation in package (W).
The thermal characterization parameter is measured per JESD51–2 specification using a
40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
49
Design Considerations
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-to-
case thermal resistance.
8.2 Electrical design considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA
Ceramic and tantalum capacitors tend to provide better tolerances.
.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
MC56F836xx, Rev. 1.6, 09/2019
50
NXP Semiconductors
Design Considerations
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.1 µF–4.7 µF.
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
reset state during normal operation if JTAG converter is not present. Furthermore,
configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.
• During reset and after reset but before I/O initialization, all the GPIO pins are at tri-
state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
8.3 Power-on Reset design considerations
8.3.1 Improper power-up sequence between VDD/VSS and VDDA/
VSSA:
It is recommended that VDD be kept within 100 mV of VDDA at all times, including
power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may
cause a leakage current through the substrate, between the VDD and VDDA pad cells.
This leakage current could prevent operation of the device after it powers up. The voltage
difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid
permanent damage to the part (See Table 4). Also see Table 5.
8.3.2 Heavy capacitive load on power supply output:
In some applications, the low cost DC/DC converter may not regulate the output voltage
well before it reaches the regulation point, which is roughly around 2.7V. However, the
device might exit power-on reset at around 2.3V. If the initialization code enables the
PLL to run the DSC at full speed right after reset, then the high current will be pulled by
DSC from the supply, which can cause the supply voltage to drop below the operation
voltage; see the captured graph (Figure 20). This can cause the DSC fail to start up.
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
51
Obtaining package dimensions
Figure 20. Supply Voltage Drop
A recommended initialization sequence during power-up is:
1. After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
2. Configure the peripherals (except the ADC) to the desired settings; the ADC should
stay in low power mode.
3. Power up the PLL.
4. After the PLL locks, switch the clock from PLL prescale to postscale.
5. Configure the ADC.
9 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing's document number:
Drawing for package
64-pin LQFP
Document number to be used
98ASS23234W
80-pin LQFP
98ASS23174W
100-pin LQFP
98ASS23308W
10 Pinout
MC56F836xx, Rev. 1.6, 09/2019
52
NXP Semiconductors
Pinout
10.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The SIM module is responsible for
selecting which ALT functionality is available on each pin.
100
80
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
—
1
33
1
—
1
GPIOB8
TCK
GPIOB8
TCK
CMPD_O
GPIOD2
GPIOD4
EXTAL
XTAL
XB_IN8
CLKIN0
XB_OUT11
2
2
2
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
VDD
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
VDD
3
3
3
4
4
4
5
5
5
TXD0
TB0
TB1
XB_IN2
CLKO0
6
6
6
RXD0
CMPD_O
PWMA_2X
7
—
—
7
—
—
—
—
7
8
VSS
VSS
9
GPIOD6
GPIOD5
GPIOC3
GPIOC4
GPIOA10
GPIOA9
VSS
GPIOD6
GPIOD5
GPIOC3
GPIOC4
GPIOA10
GPIOA9
VSS
TXD2
RXD2
TA0
XB_IN4
XB_OUT8
XB_OUT9
RXD0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
8
XB_IN5
9
CMPA_O
CMPB_O
CLKIN1
10
—
—
11
12
13
—
14
15
16
17
18
19
8
TA1
XB_IN8
EWM_OUT_B
—
—
—
—
9
CMPD_IN3
CMPD_IN2
VCAP
VCAP
GPIOA7
GPIOA8
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA7
GPIOA8
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
ANA7
—
10
11
12
13
14
15
CMPD_IN1
ANA6
ANA5
ANA4+CMPD_IN0
ANA0+CMPA_IN3
ANA1+CMPA_IN0
CMPC_O
ANA2+VREFHA+CMPA_
IN1
25
20
16
GPIOA3
GPIOA3
ANA3+VREFLA+CMPA_
IN2
26
27
28
29
30
31
32
33
21
22
23
24
25
26
27
28
17
18
19
20
21
22
23
24
GPIOB7
GPIOC5
GPIOB6
GPIOB5
GPIOB4
VDDA
GPIOB7
GPIOC5
GPIOB6
GPIOB5
GPIOB4
VDDA
ANB7+CMPB_IN2
XB_IN7
ANB6+CMPB_IN1
ANB5+CMPC_IN2
ANB4+CMPC_IN1
VSSA
VSSA
GPIOB0
GPIOB0
ANB0+CMPB_IN3
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NXP Semiconductors
53
Pinout
100
80
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
34
35
36
29
30
31
25
26
27
GPIOB1
VCAP
GPIOB1
VCAP
ANB1+CMPB_IN0
GPIOB2
GPIOB2
ANB2+VERFHB+CMPC_
IN3
37
38
39
40
41
42
32
—
—
—
—
34
—
—
—
—
—
28
GPIOA11
VSS_USB
USB_DP
USB_DM
VDD_USB
GPIOB3
GPIOA11
CMPC_O
XB_IN9
XB_OUT10
USB_SOFOUT
VSS_USB
USB_DP
USB_DM
VDD_USB
GPIOB3
ANB3+VREFLB+CMPC_
IN0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
35
36
—
—
37
38
39
40
—
41
42
43
44
45
46
47
48
49
50
51
52
—
—
53
54
55
56
57
58
—
—
29
30
—
—
—
—
31
32
—
33
34
35
36
—
—
37
38
39
40
41
42
—
—
43
44
45
46
—
—
—
—
VDD
VDD
VSS
VSS
GPIOF11
GPIOF15
GPIOD7
GPIOG11
GPIOC6
GPIOC7
GPIOG10
GPIOC8
GPIOC9
GPIOC10
GPIOF0
GPIOF10
GPIOF9
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
GPIOG8
GPIOG9
VSS
GPIOF11
GPIOF15
GPIOD7
GPIOG11
GPIOC6
GPIOC7
GPIOG10
GPIOC8
GPIOC9
GPIOC10
GPIOF0
GPIOF10
GPIOF9
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
GPIOG8
GPIOG9
VSS
TXD0
XB_IN11
XB_IN10
XB_IN7
CLKO0
XB_IN3
TXD0
RXD0
XB_OUT11
TB3
MISO1
MOSI1
TA2
CMP_REF
XB_IN8
XB_IN8
XB_IN9
TXD0
SS0_B
SS0_B
PWMB_2X
MISO0
SCLK0
MOSI0
XB_IN6
TXD2
XB_OUT6
PWMA_2X
RXD0
XB_IN4
XB_OUT8
XB_OUT9
XB_IN5
MISO0
TB2
SCLK1
PWMA_FAULT6
PWMA_FAULT7
SCL1
PWMB_FAULT6
PWMB_FAULT7
TXD1
XB_OUT10
XB_OUT11
RXD2
CANTX
CANRX
SCL1
SDA1
RXD1
XB_OUT6
XB_OUT7
XB_OUT8
XB_OUT9
PWMA_0X
PWMA_1X
MISO1
SDA1
MOSI1
TXD1
PWMA_0X
PWMA_1X
TA2
PWMA_FAULT6
PWMA_FAULT7
XB_OUT10
RXD1
PWMB_0X
PWMB_1X
TA3
XB_OUT11
VDD
VDD
GPIOE0
GPIOE1
GPIOG2
GPIOG3
GPIOE8
GPIOE9
GPIOE0
GPIOE1
GPIOG2
GPIOG3
GPIOE8
GPIOE9
PWMA_0B
PWMA_0A
PWMB_0B
PWMB_0A
PWMB_2B
PWMB_2A
XB_OUT4
XB_OUT5
XB_OUT4
XB_OUT5
PWMA_FAULT0
PWMA_FAULT1
XB_OUT8
XB_OUT9
MC56F836xx, Rev. 1.6, 09/2019
54
NXP Semiconductors
Pinout
100
80
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
59
60
61
62
63
64
—
—
65
66
67
68
69
70
71
—
—
—
72
73
74
75
76
77
78
79
80
47
48
49
50
—
—
—
—
51
52
53
54
—
55
56
—
—
—
—
57
58
59
60
61
62
63
64
GPIOE2
GPIOE3
GPIOE2
GPIOE3
GPIOC13
GPIOF1
GPIOG0
GPIOG1
GPIOG4
GPIOG5
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOG6
GPIOC14
GPIOC15
GPIOF12
GPIOF13
GPIOF14
GPIOG7
VCAP
PWMA_1B
XB_OUT6
XB_OUT7
PWMA_1A
TA3
GPIOC13
GPIOF1
GPIOG0
GPIOG1
GPIOG4
GPIOG5
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOG6
GPIOC14
GPIOC15
GPIOF12
GPIOF13
GPIOF14
GPIOG7
VCAP
XB_IN6
EWM_OUT_B
CLKO1
XB_IN7
CMPD_O
PWMB_1B
PWMB_1A
PWMB_3B
PWMB_3A
PWMA_2B
PWMA_2A
PWMA_3B
PWMA_3A
PWMA_FAULT4
SDA0
XB_OUT6
XB_OUT7
PWMA_FAULT2
PWMA_FAULT3
XB_IN2
XB_OUT10
XB_OUT11
XB_OUT8
XB_OUT9
XB_OUT10
XB_OUT11
XB_OUT8
XB_IN3
XB_IN4
PWMB_2B
PWMB_2A
TB2
XB_IN5
PWMB_FAULT4
XB_OUT4
PWMA_FAULT4
PWMA_FAULT5
SCL0
XB_OUT5
MISO1
PWMB_FAULT2
PWMB_FAULT1
PWMB_FAULT0
PWMB_FAULT5
MOSI1
SCLK1
PWMA_FAULT5
XB_OUT9
CLKIN2 (USB optional)
GPIOF6
GPIOF7
VDD
GPIOF6
GPIOF7
VDD
TB2
TB3
PWMA_3X
CMPC_O
PWMB_3X
SS1_B
XB_IN2
XB_IN3
VSS
VSS
TDO
TDO
GPIOD1
GPIOD3
GPIOD0
TMS
TMS
TDI
TDI
10.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
55
Pinout
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TCK
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
VDD
GPIOE3
GPIOE2
GPIOE9
GPIOE8
GPIOG3
GPIOG2
GPIOE1
GPIOE0
VDD
2
3
4
5
6
7
8
VSS
9
GPIOD6
GPIOD5
GPIOC3
GPIOC4
GPIOA10
GPIOA9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
GPIOG9
GPIOG8
GPIOF5
GPIOF4
GPIOF3
GPIOF2
GPIOC12
GPIOC11
GPIOF9
GPIOF10
GPIOF0
GPIOC10
GPIOC9
GPIOC8
GPIOG10
VCAP
GPIOA7
GPIOA8
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
Figure 21. 100-pin LQFP
MC56F836xx, Rev. 1.6, 09/2019
56
NXP Semiconductors
Pinout
1
TCK
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOD6
GPIOD5
GPIOC3
GPIOC4
VSS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GPIOE3
GPIOE2
GPIOG3
GPIOG2
GPIOE1
GPIOE0
VDD
2
3
4
5
6
7
8
VSS
9
GPIOF5
GPIOF4
GPIOF3
GPIOF2
GPIOC12
GPIOC11
GPIOF9
GPIOF10
GPIOF0
GPIOC10
GPIOC9
GPIOC8
10
11
12
13
14
15
16
17
18
19
20
VCAP
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
Figure 22. 80-pin LQFP
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
57
Product documentation
TCK
RESETB
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOE3
GPIOE2
GPIOE1
GPIOE0
VDD
2
3
4
5
6
VSS
7
GPIOF5
GPIOF4
GPIOF3
GPIOF2
GPIOC12
GPIOC11
GPIOF0
GPIOC10
GPIOC9
GPIOC8
8
9
10
11
12
13
14
15
16
Figure 23. 64-pin LQFP
11 Product documentation
The documents listed in Table 34 are required for a complete description and to
successfully design using the device. Documentation is available from local NXP
distributors, NXP sales offices, or online at www.nxp.com.
MC56F836xx, Rev. 1.6, 09/2019
58
NXP Semiconductors
Revision history
Table 34. Device documentation
Topic
Description
Document Number
DSP56800E/DSP56800EX
Reference Manual
Detailed description of the 56800EX family architecture, 32-bit
digital signal controller core processor, and the instruction set
DSP56800ERM
MC56F83xxx Reference Manual Detailed functional description and programming model
MC56F83XXXRM
MC56F836XXDS
MC56F836xx Data Sheet
Electrical and timing specifications, pin descriptions, and
package information (this document)
MC56F83xxx Errata
Details any chip issues that might be present
MC56F83XXX_0N64Y
12 Revision history
The following table summarizes changes to this document since the release of the
previous version.
Table 35. Revision history
Rev.
Date
Substantial Changes
1.6
09/2019 Initial public release
MC56F836xx, Rev. 1.6, 09/2019
NXP Semiconductors
59
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Document Number MC56F836XXDS
Revision 1.6, 09/2019
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