MC68EC030CFE25C [NXP]

32-BIT, 25MHz, MICROPROCESSOR, CQFP132, LEAD FREE, CERAMIC, QFP-132;


型号：	MC68EC030CFE25C
厂家：	NXP
描述：	32-BIT, 25MHz, MICROPROCESSOR, CQFP132, LEAD FREE, CERAMIC, QFP-132
文件：	总44页 (文件大小：499K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

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SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded

Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for

the requirements of embedded control applications. The MC68EC030 is optimized to maintain

performance while using cost-effective memory subsystems. The rich instruction set and addressing

mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear

migration path for M68000 systems. The main features of the MC68EC030 are as follows:

• Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

• Burst-Mode Bus Interface for Efficient DRAM Access

• On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

• Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

• 25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

• Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

Additional features of the MC68EC030 include:

• Complete 32-Bit Nonmultiplexed Address and Data Buses

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

• Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

• Pipelined Architecture with Increased Parallelism Allows:

– Internal Caches Accesses in Parallel with Bus Transfers

– Overlapped Instruction Execution

• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),

Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

• Complete Support for Coprocessors with the M68000 Coprocessor Interface

• Internal Status Indication for Hardware Emulation Support

• 4-Gbyte Direct Addressing Range

• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density

NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

µ MOTOROLA

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INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer

unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on

one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the

32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor

interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated

controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with

accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030

as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from

external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to

the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four

long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can

reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used

to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the

average access time for operand fetches is minimized.

The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)

memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the

MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating

system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

20 MHz

OSC.

MC88916

MC68EC030

(40 MHz)

BUS CLOCK

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

(80 MHz)

Figure 1. MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the

autonomous nature of these blocks. The bus controller consists of the address and data pads, the

multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus

cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.

Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the

micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

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information. The instruction pipe and other individual control sections provide the secondary decode of

instructions and generate the actual control signals that result in the decoding and interpretation of

nanoROM and microROM information.

The instruction and data cache blocks operate independently from the rest of the machine, storing

information read by the bus controller for future use with very fast access time. Each cache resides on its

own address bus and data bus, allowing simultaneous access to both. The data and instruction caches

are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data

cache uses a write-through policy with programmable write allocation for cache misses.

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The ACU contains two access control registers that are used to define memory segments ranging in size

from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and

function code. Each segment can be marked as cacheable or non cacheable to control cache accesses

to that memory space.

PROGRAMMING MODEL

As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general-

purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,

a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling

(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are

used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and

quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are

address registers that may be used as software stack pointers or base address registers. In addition, the

address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–

D7, A0–A7) can be used as index registers.

16 15

DATA

REGISTERS

16 15

ADDRESS

REGISTERS

16 15

(USP)

USER STACK

POINTER

PROGRAM

COUNTER

8 7

CONDITION CODE

CCR

Figure 3. User Programming Model

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16 15

A7'

INTERRUPT

(ISP)

STACK POINTER

A7"

(MSP)

MASTER

STACK POINTER

STATUS

(CCR)

VECTOR

BASE REGISTER

VBR

SFC

DFC

ALTERNATE FUNCTION

CODE REGISTERS

CACHE CONTROL

CACR

CACHE ADDRESS

CAAR

AC0

ACCESS CONTROL

AC1

ACU STATUS

ACUSR

Figure 4. Supervisor Programming Model Supplement

The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following

condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits

indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt

state (M).

SYSTEM BYTE

USER BYTE

15 14 13 12 11 10

INTERRUPT

PRIORITY MASK

TRACE ENABLE

SUPERVISOR/USER STATE

EXTEND

NEGATIVE

ZERO

MASTER/INTERRUPT STATE

CONDITION

CODES

OVERFLOW

CARRY

Figure 5. Status Register

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All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the

MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The

MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow

instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are

important for software program development and debug.

The vector base register (VBR) is used to determine the run-time location of the exception vector table in

memory; thus, each separate vector table for each process or task can properly manage exceptions

independent of each other.

The M68000 Family processors distinguish address spaces as supervisor/user, program/data, and CPU

space. These five combinations are specified by the function code pins (FC0/FC1/FC2) during bus

cycles, indicating the particular address space. Using the function codes, the memory subsystem

(hardware) can distinguish between supervisor accesses and user accesses as well as program accesses,

data accesses, and CPU space accesses. To support the full privileges of the supervisor, the alternate

function code registers allow the supervisor to specify the function code for an access by appropriately

preloading the SFC/DFC registers.

The cache registers allow supervisor software manipulation of the on-chip instruction and data caches.

Control and status accesses to the caches are provided by the cache control register (CACR); the cache

address register (CAAR) specifies the address for those cache control functions that require an address.

The access control registers are accessible by the supervisor only. The access control registers are used

to define two memory spaces with caching restrictions. The ACU status register (ACUSR) is used to show

the result of PTEST operations on the ACU.

DATA TYPES AND ADDRESSING MODES

Seven basic data types are supported by the MC68EC030:

• Bits

• Bit Fields (String of consecutive bits, 1–32 bits long)

• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)

• Byte Integers (8 bits)

• Word Integers (16 bits)

• Long-Word Integers (32 bits)

• Quad-Word Integers (64 bits)

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In addition, operations on other data types, such as memory addresses, status word data, etc., are

provided in the instruction set. The coprocessor mechanism allows direct support of floating-point data

types with the MC68881/MC68882 floating-point coprocessors as well as specialized user-defined data

types and functions. The 18 addressing modes, listed in Table 1, include nine basic types:

• Register Direct

• Register Indirect

• Register Indirect with Index

• Memory Indirect

• Program Counter Indirect with Displacement

• Program Counter Indirect with Index

• Program Counter Memory Indirect

• Absolute

• Immediate

The register indirect addressing modes support postincrement, predecrement, offset, and indexing.

These capabilities are particularly useful for handling advanced data structures common to sophisticated

applications and high-level languages. The program counter relative mode also has index and offset

capabilities; this addressing mode is generally required to support position- independent software. In

addition to these addressing modes, the MC68EC030 provides data operand sizing and scaling; these

features provide performance enhancements to the programmer.

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Table 1. MC68EC030 Addressing Modes

Addressing Modes

Data Register Direct

Address Register Direct

Syntax

Address Register Indirect

(An)

Address Register Indirect with Postincrement

Address Register Indirect with Predecrement

Address Register Indirect with Displacement

(An);pl

-(An)

(d ,An)

Address Register Indirect with Index (8-Bit Displacement) (d ,An,Xn)

Address Register Indirect with Index (Base Displacement)

(bd,An,Xn)

Memory Indirect

Memory Indirect Postindexed

Memory Indirect Preindexed

([bd,An],Xn,od)

([bd,An,Xn],od)

Program Counter Indirect with Displacement

(d ,PC)

Program Counter Indirect with Index

PC Indirect with Index (8-Bit Displacement)

PC Indirect with Index (Base Displacement)

(d ,PC,Xn)

(bd,PC,Xn)

Program Counter Memory Indirect

PC Memory Indirect Postindexed

PC Memory Indirect Preindexed

([bd,PC],Xn,od)

([bd,PC,Xn],od)

Absolute Data Addressing

Absolute Short

Absolute Long

xxx.W

xxx.L

Immediate

#<data>

NOTES:

d , d

Data Register, D0–D7

Address Register, A0–A7

A twos-complement or sign-extended displacement; added as part of

the effective address calculation; size is 8 (d ) or 16 (d ) bits;

when omitted, assemblers use a value of zero.

Address or data register used as an index register; form is

Xn.SIZE*SCALE, where SIZE is .W or .L (indicates index register

size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by

SCALE); use of SIZE and/or SCALE is optional.

A twos-complement base displacement; when present, size can be

16 or 32 bits.

Outer displacement added as part of effective address calculation

after any memory indirection; use is optional with a size of 16 or 32

bits.

<data>

( )

Program Counter

Immediate value of 8, 16, or 32 bits

Effective Address

[ ]

Used as indirect address to long-word address.

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INSTRUCTION SET OVERVIEW

The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on

bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The

MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it

supports all instructions of previous family members.

Table 2. Instruction Set

Mnemonic

Description

Mnemonic

Description

ABCD

ADD

ADDA

ADDI

ADDQ

ADDX

AND

ANDI

ASL,ASR

Bcc

BCHG

BCLR

BFCHG

BFCLR

BFEXTS

BEFXTU

BFFFO

BFINS

BFSET

BFTST

BKPT

BRA

BSET

BSR

BTST

CAS

CAS2

CHK

Add Decimal with Extend

Add

Add Address

Add Immediate

Add Quick

Add with Extend

Logical AND

Logical AND Immediate

Arithmetic Shift Left and Right

Branch Conditionally

Test Bit and Change

Test Bit and Clear

Test Bit Field and Change

Test Bit Field and Clear

Signed Bit Field Extract

Unsigned Bit Field Extract

Bit Field Find First One

Bit Field Insert

Test Bit Field and Set

Test Bit Field

Breakpoint

Branch

Test Bit and Set

Branch to Subroutine

Test Bit

Compare and Swap Operands

Compare and Swap Dual Operands

Check Register Against Bound

Check Register Against Upper and Lower

Bounds

Clear

Compare

Compare Address

Compare Immediate

Compare Memory to Memory

Compare Register Against Upper and

Lower Bounds

Test Condition, Decrement and Branch

Signed Divide

MOVE

Move

Move Address

MOVEA

MOVE CCR

MOVE SR

MOVE USP

MOVEC

MOVEM

MOVEP

MOVEQ

MOVES

MULS

MULU

NBCD

NEG

Move Condition Code Register

Move Status Register

Move User Stack Pointer

Move Control Register

Move Multiple Registers

Move Peripheral

Move Quick

Move Alternate Address Space

Signed Multiply

Unsigned Multiply

Negate Decimal with Extend

Negate

Negate with Extend

No Operation

Logical Complement

Logical Inclusive OR

Logical Inclusive OR Immediate

Pack BCD

Push Effective Address

No Effect

NEGX

NOP

NOT

ORI

PACK

PEA

PFLUSH

PLOAD

PMOVE

PTEST

RESET

ROL, ROR

ROXL, ROXR

RTD

RTE

RTR

RTS

SBCD

Scc

No Effect

Move to/from ACx Registers

Test Address in ACx Registers

Reset External Devices

Rotate Left and Right

Rotate with Extend Left and Right

Return and Deallocate

Return from Exception

Return and Restore Codes

Return from Subroutine

Subtract Decimal with Extend

Set Conditionally

CHK2

CLR

CMP

CMPA

CMPI

CMPM

CMP2

STOP

SUB

SUBA

Stop

Subtract

Subtract Address

Subtract Immediate

Subtract Quick

Subtract with Extend

Swap Register Words

Test Operand and Set

Trap

Trap Conditionally

Trap on Overflow

Test Operand

DBcc

SUBI

DIVS,DIVSL

DIVU, DIVUL

EOR

EORI

EXG

EXT, EXTB

ILLEGAL

JMP

SUBQ

SUBX

SWAP

TAS

Unsigned Divide

Logical Exclusive OR

Logical Exclusive OR Immediate

Exchange Registers

Sign Extend

Take Illegal Instruction Trap

Jump

TRAP

TRAPcc

TRAPV

TST

JSR

LEA

LINK

Jump to Subroutine

Load Effective Address

Link and Allocate

UNLK

UNPK

Unlink

Unpack BCD

LSL, LSR

Logical Shift Left and Right

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Coprocessor Instructions

cpBCC

cpDBcc

Branch Conditionally

Test Coprocessor Condition,

Decrement and Branch

cpRESTORE

cpSAVE

cpScc

Restore Internal State of Coprocessor

Save Internal State of Coprocessor

Set Conditionally

cpGEN

Coprocessor General Instruction

cpTRAPcc

Trap Conditionally

Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds

checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)

offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030

can be used on the MC68040 for even more performance. The memory management unit (MMU)

instructions of the MC68030, and MC68040 are not supported by the MC68EC030.

INSTRUCTION AND DATA CACHES

Studies have shown that typical programs spend most of their execution time in a few main routines or

tight loops. This phenomenon, known as locality of reference, has an impact on program performance.

The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can be

used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to

provide the system with two on-chip caches, one for instructions and one for data.

MC68EC030 CACHE GOALS

Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030

embedded controller caches. The first design goal was to reduce the external bus activity of the CPU

even more than was accomplished with the MC68020. The second design goal was to increase effective

CPU throughput as larger memory sizes or slower memories increased average access time. By placing a

high-speed cache between the controller and the rest of the memory system, the effective memory

access time becomes:

=R *t + (1-R )*t

h cache h ext

acc

where t

acc

is the effective system access time, t

is the cache access time, t is the access time of

ext

cache

the rest of the system, and R is the hit ratio or the percentage of time that the data is found in the cache.

Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial

CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower

and less expensive memories can be used for the same controller performance.

The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are

accessed in less time than is required for external accesses, providing improvement in the access time for

items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be

found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time

required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time

for items found in the caches even further. Third, the autonomous nature of the caches allows instruction

stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.

The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently

so that several internal instructions (those that do not require any external accesses) can execute while

the controller is performing an external access for a previous instruction.

INSTRUCTION CACHE

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The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting

of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with

address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed of

the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry),

and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the

MC68EC030 whenever a cache miss occurs; using the burst transfer capability, up to four long words can

be filled in one burst operation. The caches cannot be manipulated directly by the programmer except by

the use of the CACR, which provides cache clearing and cache entry clearing facilities. The caches can

also be enabled/disabled by this register. Finally, the system hardware can disable the on-chip caches at

any time by asserting the CDIS signal.

LONG WORD

SELECT

TAG

INDEX

F F F

C C C

2 1 0

A A A A A A A A A A A A A A A A A A A A A A A A

ACCESS ADDRESS

2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

TAG

1 OF 16

SELECT

DATA FROM INSTRUCTION

CACHE DATA BUS

TAG REPLACE

VALID

DATA TO INSTRUCTION

CACHE HOLDING REGISTER

ENTRY HIT

CACHE CONTROL LOGIC

COMPARATOR

LINE HIT

CACHE SIZE = 64 (LONG WORDS)

LINE SIZE = 4 (LONG WORDS)

SET SIZE = 1

Figure 6. On-Chip Instruction Cache Organization

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DATA CACHE

The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the

tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly

specifying the address space associated with each line. The data cache employs a write-through policy

with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data

cache and the external device are updated with the new data. If a write cycle generates a cache miss, the

external device is updated, and a new data cache entry can be replaced or allocated for that address,

depending on the state of the write-allocate (WA) bit in the CACR.

LONG-WORD

SELECT

TAG

INDEX

F F F

C C C

2 1 0

A A A A A A A A A A A A A A A A A A A A A A A A

ACCESS ADDRESS

2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

TAG

1 OF 16

SELECT

DATA FROM DATA

CACHE DATA BUS

TAG REPLACE

VALID

DATA TO EXECUTION

UNIT

ENTRY HIT

CACHE CONTROL LOGIC

COMPARATOR

LINE HIT

CACHE SIZE = 64 (LONG WORDS)

LINE SIZE = 4 (LONG WORDS)

SET SIZE = 1

Figure 7. On-Chip Data Cache Organization

OPERAND TRANSFER MECHANISM

The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the

chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,

can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is

determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size

acknowledge (DSACKx) signals. Synchronous bus cycles, compatible with the synchronous bus on the

MC68030, are terminated with the synchronous termination (STERM) signal and always transfer 32-bits

of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,

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thereby increasing possible performance. Burst mode transfers can be used to fill lines of the instruction

and data caches when the MC68EC030 asserts cache burst request (CBREQ). After completing the first

cycle with STERM, subsequent cycles may accept data on every clock cycle where STERM is asserted

until the burst is completed. Use of this mode can further increase the available bus bandwidth in systems

that use DRAMs with page, nibble, or static-column mode operation.

ASYNCHRONOUS TRANSFERS

Though the MC68EC030 has a full 32-bit data bus, it offers the ability to automatically and dynamically

downsize its bus to 8 or 16 bits if peripheral devices are unable to accommodate the entire 32 bits. This

feature allows the programmer to write code that is not bus-width specific. For example, long-word (32 bit)

accesses to peripherals may be used in the code; yet, the MC68EC030 will transfer only the amount of

data that the peripheral can manage. This feature allows the peripheral to define its port size as 8, 16, or

32 bits wide, and the MC68EC030 will dynamically size the data transfer accordingly, using multiple bus

cycles when necessary. Hence, programmers are not required to program for each device port size or

know the specific port size before coding; hardware designers have the flexibility to choose hardware

implementations regardless of software implementations.

The dynamic bus sizing mechanism is invoked by DSACKx and occurs on a cycle-by-cycle basis. For

example, if the controller is executing an instruction that requires reading a long-word operand, it will

attempt to read 32 bits during the first bus cycle to a long-word address boundary. If the port responds

that it is 32 bits wide, the MC68EC030 latches all 32 bits of data and continues. If the port responds that it

is 16 bits wide, the MC68EC030 latches the 16 valid bits of data and continues. An 8-bit port is handled

similarly but has four bus read cycles. Each port is fixed in the assignment to particular sections of the data

bus. However, the MC68EC030 has no restrictions concerning the alignment of operands in memory;

long-word operands need not be aligned to long-word address boundaries. When misaligned data

requires multiple bus cycles, the MC68EC030 automatically runs the minimum number of bus cycles.

Instructions must still be aligned to word boundaries.

The timing of asynchronous bus cycles is also determined by the assertion of DSACKx on a cycle-by-

cycle basis. If the DSACKx signals are valid 1.5 clocks after the beginning of the bus cycle (with the

appropriate setup time), the cycle terminates in the minimum amount of time (corresponding to three-

clock-cycle total). The cycle can be lengthened by delaying DSACKx (effectively inserting wait states in

one-clock increments) until the device being accessed is able to terminate the cycle. This flexibility gives

the controller the ability to communicate with devices of varying speeds while operating at the fastest rate

possible for each device.

The asynchronous transfer mechanism allows external errors to abort cycles upon the assertion of bus

error (BERR) or allows individual bus cycles to be retried with the simultaneous assertion of BERR and

HALT.

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SYNCHRONOUS TRANSFERS

Synchronous bus cycles are terminated by asserting STERM, which automatically indicates that the bus

transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be

performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup

time. However, the bus cycle may be lengthened by delaying STERM (inserting wait states in one-clock

increments) until the device being accessed is able to terminate the cycle. After the assertion of STERM,

these cycles may be aborted upon the assertion of BERR, or they may be retried with the simultaneous

assertion of BERR and HALT.

BURST READ CYCLES

The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to

the overall system performance. The on-chip caches are organized with a line size of four long words;

there is only one tag for the four long words in a line. Since locality of reference is present to some

degree in most programs, filling of all four entries when a single entry misses can be advantageous,

especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data

can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be

performed only when the MC68EC030 requests them (with the assertion of CBREQ) and only when the

first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (CBACK) input

is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original AS, DS,

R/W, address, function code, and size outputs asserted and latches 32 bits from the data bus at the end

of each subsequent clock cycle that has STERM asserted. This procedure continues until the burst is

complete (the entire block has been transferred), BERR is asserted in lieu of or after STERM, the cache

inhibit in (CIIN) input is asserted, or the CBACK input is negated. The cache preloading allowed by the

bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal

performance impact.

EXCEPTIONS

The types of exceptions and the exception processing sequence are discussed in the following

paragraphs.

TYPES OF EXCEPTIONS

Exceptions can be generated by either internal or external causes. The externally generated exceptions

are interrupts, BERR, and RESET. Interrupts are requests from peripheral devices for controller action;

whereas, BERR and RESET are used for access control and controller restart. The internally generated

exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,

TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction

execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is

processed. The other internally generated exceptions are caused by illegal instructions, instruction

fetches from odd addresses, and privilege violations.

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EXCEPTION PROCESSING SEQUENCE

Exception processing occurs in four steps. During the first step, an internal copy is made of the status

bit is set, putting the controller into the supervisor state. Also, the T1 and T0 bits are negated, allowing

the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the

interrupt priority mask is also updated.

In the second step, the vector number of the exception is determined. For interrupts, the vector number

is obtained by a controller read that is classified as an interrupt acknowledge cycle. For coprocessor-

detected exceptions, the vector number is included in the coprocessor exception primitive response.

For all other exceptions, internal logic provides the vector number. This vector number is then used to

generate the address of the exception vector.

The third step is to save the current controller status. The exception stack frame is created and filled on

the current supervisor stack. To minimize the amount of machine state that is saved, various stack frame

sizes are used to contain the controller state, depending on the type of exception and where it occurred

during instruction execution. If the exception is an interrupt and the M-bit is set, the M-bit is then cleared,

and the short four-word exception stack frame that is saved on the master stack is also saved on the

interrupt stack. If the exception is a reset, the M-bit is simply cleared, and the reset vector is accessed.

The MC68EC030 provides the same extensions to the exception stacking process as the MC68020,

MC68030, and MC68040. If the M-bit is set, the master stack pointer (MSP) is used for all task-related

exceptions. When a nontask-related exception occurs (i.e., an interrupt), the M bit is cleared, and the

interrupt stack pointer (ISP) is used. This feature allows all the task's stack area to be carried within a single

controller control block, and new tasks can be initiated by simply reloading the MSP and setting the M-bit.

The fourth and last step of exception processing is the same for all exceptions. The exception vector

offset is determined by multiplying the vector number by four. This offset is then added to the contents of

the vector base register (VBR) to determine the memory address of the exception vector. The new

program counter is fetched from the exception vector. The instruction at the address given in the

exception vector is fetched, and normal instruction decoding and execution is started.

STATUS and REFILL

The MC68EC030 provides the STATUS and REFILL signals to identify internal microsequencer activity

associated with the processing of data pipelined in the pipeline. Since bus cycles are independently

controlled and scheduled by the bus controller, information concerning the processing state of the

microsequencer is not available by monitoring bus signals by themselves. The internal activity identified

by the STATUS and REFILL signals include instruction boundaries, some exception conditions, when

the microsequencer has halted, and instruction pipeline refills. STATUS and REFILL track only the

internal microsequencer activity and are not directly related to bus activity.

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ACCESS CONTROL

Two access control registers are provided on the MC68EC030 to control cachability of accesses for two

independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is

specified in the corresponding ACx register with a base address, a base mask, function code, function

code mask, and read/write mask. A typical use for an access control register is to designate a block of

memory containing I/O devices as non-cachable.

COPROCESSOR INTERFACE

The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The

interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of

these extensions are the addition of specialized data operands for the existing data types or, for the case

of floating point, the inclusion of new data types and operations implemented by the

MC68881/MC68882 floating-point coprocessors.

SIGNAL DESCRIPTION

Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.

IPL0

FUNCTION

FC0–FC2

A0–A31

D0–D31

IPL1

CODES

INTERRUPT

CONTROL

IPL2

IPEND

AVEC

ADDRESS

BUS

DATA

BUS

SIZ0

SIZ1

BUS ARBITRATION

CONTROL

TRANSFER

SIZE

BGACK

OCS

ECS

R/W

RMC

RESET

HALT

BERR

BUS EXCEPTION

CONTROL

MC68EC030

SYNCHRONOUS

BUS CONTROL

STERM

ASYNCHRONOUS

BUS CONTROL

DBEN

REFILL

STATUS

DSACK0

DSACK1

EMULATOR

SUPPORT

CDIS

CIIN

CIOUT

CBREQ

CBACK

CLK

CACHE

CONTROL

(10)

GND (14)

Figure 8. Functional Signal Groups

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Table 3. Signal Index

Signal Name

Mnemonic

Function

Function Codes

FC0–FC2

3-bit function code used to identify the address space of each bus

cycle.

Address Bus

Data Bus

A0–A31

D0–D31

32-bit address bus.

32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus

cycle.

Size

SIZ0–SIZ1

Indicates the number of bytes remaining to be transferred for this

cycle. These signals, together with A0 and A1, define the active

sections of the data bus.

Operand Cycle Start

OCS

Identical operation to that of ECS except that OCS is asserted only

during the first bus cycle of an operand transfer

External Cycle Start

Read/Write

Provides an indication that a bus cycle is beginning.

Defines the bus transfer as a controller read or write.

ECS

R/W

RMC

Read-Modify-Write Cycle

Provides an indicator that the current bus cycle is part of an indivisible

read-modify-write operation.

Address Strobe

Data Strobe

Indicates that a valid address is on the bus.

Indicates that valid data is to be placed on the data bus by an external

device or has been replaced by the MC68EC030.

Data Buffer Enable

Provides an enable signal for external data buffers.

DBEN

Data Transfer and Size

Acknowledge

Bus response signals that indicate the requested data transfer

operation has completed. In addition, these two lines indicate the size

of the external bus port on a cycle-by-cycle basis and are used for

asynchronous transfers.

DSACK0,

DSACK1

Synchronous

Termination

Bus response signal that indicates a port size of 32 bits and that data

may be latched on the next falling clock edge.

STERM

CIIN

Cache Inhibit In

Prevents data from being loaded into the MC68EC030 instruction and

data caches.

Cache Inhibit Out

Reflects the CI bit in ACx registers; indicates that external caches

should ignore these accesses.

CIOUT

Cache Burst Request

Indicates a burst request for the instruction or data cache.

Indicates that the accessed device can operate in burst mode.

CBREQ

CBACK

Cache Burst

Acknowledge

Interrupt Priority Level

Interrupt Pending

Autovector

Provides an encoded interrupt level to the controller.

Indicates that an interrupt is pending.

IPL0–IPL2

IPEND

AVEC

Requests an autovector during an interrupt acknowledge cycle.

Indicates that an external device requires bus mastership.

Indicates that an external device may assume bus mastership.

Indicates that an external device has assumed bus mastership.

System reset.

Bus Request

Bus Grant

Bus Grant Acknowledge

Reset

BGACK

RESET

HALT

BERR

Halt

Indicates that the controller should suspended bus activity.

Indicates that an erroneous bus operation is being attempted.

Dynamically disables the on-chip cache to assist emulator support.

Indicates when the MC68EC030 is beginning to fill pipeline.

Indicates the state of the microsequencer.

Bus Error

Cache Disable

Pipe Refill

CDIS

REFILL

STATUS

Microsequencer Status

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Clock

CLK

Clock input to the controller.

Table 3. Signal Index – Continued

Mnemonic Function

Signal Name

Power Supply

Power supply.

Ground

GND

Ground connection.

Do not connect.

No Connect

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ELECTRICAL SPECIFICATIONS

MAXIMUM RATINGS

The device contains circuitry to

Rating

Symbol

Value

Unit

protect the inputs against damage

due to high static voltages or

electric fields; however, normal

precautions should be taken to

avoid application of voltages higher

than maximum-rated voltages to

these high-impedance circuits.

Tying unused inputs to the

appropriate logic voltage level (e.g.,

Supply Voltage

Input Voltage

-0.3 to +7.0

-0.5 to +7.0

Operating Temperature Range

Minimum Ambient Temperature

Maximum Ambient Temperature

°C

Storage Temperature Range

-55 to 150

stg

either GND or

)

enhances

reliability of operation.

THERMAL CHARACTERISTICS-- PGA PACKAGE

Characteristic

Symbol Value Rating

Thermal Resistance - Plastic

Junction to Ambient

Junction to case

^oC/W

θ_JA

TBD

θ_JC

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in ^oC can be obtained from:

T =T +(P

•

JA)

(1)

where:

= Ambient Temperature, ^oC

= Package Thermal Resistance, Junction-to-Ambient, ^oC/W

INT

= P

+ P

INT I/O

= I

^XV , Watts — Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

I/O

For most applications, P <P

I/O INT

and can be neglected.

The following is an approximate relationship between P and T (if P

I/O

is neglected):

P =K ÷ (T +273^oC)

(2)

(3)

Solving Equations (1) and (2) for K gives:

K=P • (T + 273^oC) +

•P

JA D

where K is a constant pertaining to the particular part. K can be determined from equation (3) by

measuring P (at thermal equilibrium) for a known T . Using this value of K, the values of P and T can

be obtained by solving equations (1) and (2) iteratively for any value of T .

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The total thermal resistance of a package (

) can be separated into two components,

and

representing the barrier to heat flow from the semiconductor junction to the package (case) surface (

)

and from the case to the outside ambient air (

). These terms are related by the equation:

(4)

JA JC

is device related and cannot be influenced by the user. However,

is user dependent and can

be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal

convection. Thus, good thermal management on the part of the user can significantly reduce so that

in equation (1) results in a lower

approximately equals;

. Substitution of

for

semiconductor junction temperature.

Values for thermal resistance presented in this document, unless estimated, were derived using the

procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for

MC68XX Microcomponent Devices,” and are provided for design purposes only. Thermal measurements

are complex and dependent on procedure and setup. User derived values for thermal resistance may

differ.

AC ELECTRICAL SPECIFICATION DEFINITIONS

The AC specifications presented consist of output delays, input setup and hold times, and signal skew

times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more

other signals.

The measurement of the AC specifications is defined by the waveforms shown in Figure 9. To test the

parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in Figure 9.

Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in

Figure 9. Inputs are specified with minimum setup and hold times, and are measured as shown. Finally,

the measurement for signal-to-signal specifications is also shown.

Note that the testing levels used to verify conformance to the AC specifications does not affect the

guaranteed DC operation of the device as specified in the DC electrical specifications.

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DRIVE

TO 2.4 V

2.0 V

0.8 V

CLK

0.8 V

DRIVE TO

0.5 V

2.0 V

0.8 V

2.0 V

0.8 V

VALID

OUTPUT n

VALID

OUTPUTS(1) CLK

OUTPUTS(2) CLK

OUTPUT n + 1

2.0 V

0.8 V

2.0 V

0.8 V

VALID

OUTPUT n

VALID

OUTPUT n+1

2.0 V

0.8 V

DRIVE TO

2.4 V

2.0 V

0.8 V

VALID

INPUT

INPUTS(3) CLK

DRIVE TO

0.5 V

DRIVE

2.0 V

0.8 V

2.0 V

0.8 V

TO 2.4 V

VALID

INPUT

INPUTS(4) CLK

ALL SIGNALS(5)

DRIVE

TO 0.5 V

2.0 V

0.8 V

2.0 V

0.8 V

NOTES:

1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.

2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.

3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.

4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.

5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.

LEGEND:

A. Maximum output delay specification.

B. Minimum output hold time.

C. Minimum input setup time specification.

D. Minimum input hold time specification.

E. Signal valid to signal valid specification (maximum or minimum).

F. Signal valid to signal invalid specification (maximum or minimum).

Figure 9. Drive Levels and Test Points for AC Specifications

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DC ELECTRICAL SPECIFICATIONS

(V =5.0 Vdc ± 5%; GND=0Vdc; temperature in defined ranges)

Characteristics

Input High Voltage

Symbol

Min

Max

Unit

2.0

Input Low Voltage

GND

-0.5

0.8

Input Leakage Current

-2.5

2.5

µA

BERR,BR, BGACK, CLK,.IPL0–IPL2,

GND≤V ,≤V

in CC

AVEC,

CDIS, DSACK0, DSACK1

HALT, RESET

-20

Hi-Z (Off-State) Leakage

Current

-20

2.4

—

µA

A0-A31, AS, DBEN, DS, D0-D31, FC0-FC2,

R/W, RMC, SIZ0-SIZ1

TSI

@ 2.4 V/0.5 V

Output High Voltage

A0–A31, AS, BG, D0–D31, DBEN, DS,

ECS, R/W, IPEND

OH = 400 µA

OCS, RMC, SIZ0–SIZ1, FC0–FC2

CBREQ, CIOUT, STATUS, REFILL

Output Low Voltage

—

0.5

A0–A31, FC0–FC2, SIZ0–SIZ1, BG, D0–D31

OL = 3.2 mA

OL = 5.3 mA

CBREQ, AS, DS, R/W, RMC, DBEN,

OL = 2.0 mA

IPEND

OL = 10.7 mA

STATUS, REFILL, CIOUT, ECS, OCS

HALT,RESET

Power Dissipation (T =0C)

—

2.6

Capacitance (see Note)

= 0 V, T =25C, f=1 MHz

Load Capacitance

—

130

ECS, OCS

CIOUT, STATUS, REFILL

All Other

NOTE: Capacitance is periodically sampled rather than 100% tested.

AC ELECTRICAL SPECIFICATIONS — CLOCK INPUT (see Figure 10)

Num.

Characteristic

25MHz

40 MHz

Unit

Min Max Min Max

Frequency of Operation

Cycle Time Clock

12.5

MHz

2,3

4,5

Clock Pulse Width Measured from 1.5 V to 1.5 V

Clock Rise and Fall Times

11.5

—

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2.0 V

0.8 V

Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.

The voltage swing through this range should start outside and pass through the range so that the rise or fall will be

linear between 0.8 V and 2.0 V.

NOTE:

Figure 10. Clock Input Timing Diagram

AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES

(V =5.0Vdc ± 5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)

Num.

Characterstics

25MHz

40 MHz

Unit

Min Max Min Max

Clock High to Function Code, Size, RMC, IPEND,CIOUT,

Address Valid

Clock High to ECS, OCS Asserted

—

Function Code, Size, RMC, IPEND, CIOUT, Address Valid to

Negating Edge of ECS

Clock High to Function Code Size, RMC, CIOUT, Address Data

—

High

Impedance

Clock High to Function Code Size, RMC, IPEND, CIOUT, Address

Invalid

Clock Low to AS, DS Asserted, CBREQ Valid

AS to DS Assertion Skew (Read)

AS Asserted to DS Asserted (Write)

ECS Width Asserted

-10

—

-6

9A¹

9B¹⁴

—

10A

10B⁷

OCS Width Asserted

ECS, OCS Width Negated

Function Code, Size, RMC, CIOUT, Address Valid to AS Asserted

(and DS Asserted, Read)

—

Clock Low to AS, DS, CBREQ Negated

Clock Low to ECS/OCS Negated

12A

AS, DS Negated to Function Code, Size, RMC CIOUT, Address

Invalid

—

AS (and DS Read) Width Asserted (Asynchronous Cycle)

—

14A¹¹DS Width Asserted (Write)

14B

AS (and DS, Read) Width Asserted (Synchronous Cycle)

AS, DS Width Negated

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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES

(Continued)

Num.

Characterstics

25MHz

40 MHz

Unit

Min Max Min Max

15A⁸

DS Negated to AS Asserted

—

Clock High to AS, DS, R/W, DBEN, CBREQ High Impedance

AS, DS Negated to R/W Invalid

Clock High to R/W High

Clock High to R/W Low

R/W High to AS Asserted

R/W Low to DS Asserted (Write)

Clock High to Data-Out Valid

—

Data-Out Valid to Negating Edge of AS

AS, DS Negated to Data-Out Invalid

25¹¹

25A^9,11DS Negated to DBEN Negated (Write)

26¹¹

Data-Out Valid to DS Asserted (Write)

Data-In Valid to Clock Low (Setup)

27A

Late BERR/HALT Asserted to Clock Low (Setup)

AS, DS Negated to DSACKx, BERR, HALT, AVEC Negated

(Asynchronous Hold)

28¹²

Clock Low to DSACKx, BERR, HALT, AVEC Negated

(Synchronous Hold)

28A¹²

29¹²

AS, DS Negated to Data-In Invalid (Asynchronous Hold)

—

29A¹²AS, DS Negated to Data-In High Impedance

30¹²

Clock Low to Data-In Invalid (Synchronous Hold)

30A¹²Clock Low to Data-In High Impedance (Read followed by Write)

—

31²

31A³

DSACKx Asserted to Data-In Valid (Asynchronous Data Setup)

DSACKx Asserted to DSACKx Valid (Skew)

RESET Input Transition Time

1.5

3.5

1.5

—

1.5

3.5

1.5

—

Clks

Clock Low to BG Asserted

Clock Low to BG Negated

Clks

BR Asserted to BG Asserted (RMC Not Asserted)

BGACK Asserted to BG Negated

BGACK Asserted to BR Negated

BG Width Negated

1.5

37A⁶

39A

BG Width Asserted

—

Clock High to DBEN Asserted (Read)

Clock Low to DBEN Negated (Read)

Clock Low to DBEN Asserted (Write)

Clock High to DBEN Negated (Write)

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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES

(Concluded)

Num.

Characterstics

25 MHz

40 MHz

Unit

Min Max Min Max

R/W Low to DBEN Asserted (Write)

—

DBEN Width Asserted

Asynchronous Read

Asynchronous Write

—

45⁵

DBEN Width Asserted

Synchronous Read

Synchronous Write

—

45A⁹

46A

47A

47B

48⁴

R/W Width Asserted (Asynchronous Write or Read)

R/W Width Asserted (Synchronous Write or Read)

Asynchronous Input Setup Time to Clock Low

Asynchronous Input Hold Time from Clock Low

DSACKx Asserted to BERR, HALT Asserted

Data-Out Hold from Clock High

100

—

R/W Asserted to Data Bus Impedance Change

RESET Pulse Width (Reset Instruction)

BERR Negated to HALT Negated (Rerun)

BGACK Negated to Bus Driven

512

Clks

58¹⁰

59¹⁰

60¹³

61¹³

Clks

BG Negated to Bus Driven

Synchronous Input Valid to Clock High (Setup Time)

Clock High to Synchronous Input Invalid (Hold Time)

Clock Low to STATUS, REFILL Asserted

Clock Low to STATUS, REFILL Negated

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NOTES:

1. This number can be reduced to 5 ns if strobes have equal loads.

2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx low to data setup time

(#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the

data-in clock low setup time (#27) for the following clock cycle and BERR must only satisfy the late

BERR low to clock low setup time (#27A) for the following clock cycle.

3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or

DSACK1 to DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1.

4. This specification applies to the first (DSACK0 or DSACK1) DSACKx signal asserted. In the absence of

DSACKx, BERR is an asynchronous input using the asynchronous input setup time (#47A).

5. DBEN may stay asserted on consecutive write cycles.

6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded,

BG may be reasserted.

7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit

followed immediately by another cache hit, a cache miss, or an operand cycle.

8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time

for DS negated to AS asserted (specification #13A in the MC68881/MC68882 User's Manual).

Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that

the MC68EC030 does not meet the MC68881/MC68882 requirements.

9. This specification allows a system designer to guarantee data hold times on the output side of data

buffers that have output enable signals generated with DBEN. The timing on DBEN precludes its use

for synchronous READ cycles with no wait states.

10. These specifications allow system designers to guarantee that an alternate bus master has stopped

driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence.

11. DS will not be asserted for synchronous write cycles with no wait states.

12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock

(synchronous). The designer is free to use either time.

13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of

the clock while AS is asserted. These values are specified relative to the high level of the rising clock

edge. The values originally published were specified relative to the low level of the rising clock edge.

14. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS

(allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (spec 8B of the

MC68881/MC68882 User's Manual).

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CLK

A31-A0

FC2-FC0

SIZ1-SIZ0

RMC

12A

10A

ECS

OCS

R/W

DBEN

DSACK0

DSACK1

31A

D31-D0

BERR

HALT

29A

27A

47A

ALL

ASYNCHRONOUS

INPUTS

CIIN

47B

CBREQ

Figure 11. Asynchronous Read Cycle Timing Diagram

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CLK

A31-A0, FC2-FC0

SIZ1-SIZ0

12A

RMC

ECS

10B

10A

OCS

15A

14A

R/W

25A

DBEN

DSACK0

DSACK1

31A

D31-D0

BERR

HALT

27A

CIOUT

Figure 12. Asynchronous Write Cycle Timing Diagram

MOTOROLA

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLK

A31-A0, FC2-FC0

SIZ1-SIZ0

RMC

ECS

12A

OCS

14B

46A

R/W

DBEN

45A

CIOUT

CBREQ

DSACK0/DSACK1

STERM

CIIN

30A

CBACK

D31-D0

Figure 13. Synchronous Read Cycle Timing Diagram

MC68EC030 TECHNICAL DATA

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLK

A31-A0, FC2-FC0

SIZ1-SIZ0

RMC

ECS

12A

OCS

14B

46A

R/W

45A

DBEN

D31-D0

DSACK0/DSACK1

STERM

28A

BERR

HALT

28A

27A

CBREQ

Figure 14. Synchronous Write Cycle Timing Diagram

MOTOROLA

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLK

A31-A0

D31-D0

FC2-FC0

SIZ1-SIZ0

ECS

OCS

R/W

DBEN

DSACK0

DSACK1

37A

BGACK

39A

Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.

The voltage swing through this range should start outside and pass through the range so that the rise or fall will be

linear between 0.8 V and 2.0 V.

NOTE:

Figure 15. Bus Arbitration Timing Diagram

MC68EC030 TECHNICAL DATA

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLK

IPEND

CDIS

47A

STATUS

REFILL

Figure 16. Other Signal Timings

MOTOROLA

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MECHANICAL DATA

PIN ASSIGNMENTS — PIN GRID ARRAY (RC SUFFIX)

D31 D28 D26

D25 D23 D21

D27 D24 D22

D19 D18 D16

D20 D17 D14

D15 D13

D11

DBEN ECS D29

D12

CIIN SIZ0 R/W D30 GND VCC GND GND GND D10

CBREQ DS SIZ1 VCC

CBACK AS GND

VCC D5

GND STATUS REFILL

VCC CDIS IPL0

GND IPL2 IPL1

VCC RESET NC

MC68EC030

BERR HALT VCC

BOTTOM

VIEW

STERM DSACK1 GND

DSACK0 VCC GND

CLK AVEC GND

GND

VCC A6

GND VCC GND A18 GND A11 A9

A14 A12

A30 A28 A26 A24 A23 A21 A19 A17 A15

10 11

NC IPEND

FC2

FC0 OCS VCC

FC1 CIOUT BGACK A1

A31 A29 A27 A25 A22 A20 A16

RMC BG

A13 A10

12 13

NOTE

The MC68030 has four additional guide pins not present on the

MC68EC030. Therefore, an MC68EC030 fits in a socket designed

for the MC68030, but the MC68030 does not necessary fit in a

socket intended for the MC68EC030.

The Vcc and GND pins are separated into three groups to provide individual power

supply connections for the address bus buffers, data bus buffers, and all other output

buffers and internal logic

Pin Group

VCC

C6, D10

L6, K10

GND

C5, C7, C9, E11

J11, L9, L7, L5

J 3

Address Bus

Data Bus

ECS, SIZx, DS, AS, DBEN, CBREQ, R/W

FC0–FC2, RMS, OCS, CIOUT, BG

Internal Logic, RESET, STATUS, REFILL,

Misc

H3, F2, F11, H11

L8, G3, F3, G11

MC68EC030 TECHNICAL DATA

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

MC68EC030

RP SUFFIX PACKAGE

CASE 789F-01

2 3 4 5 6

9 10 11 12 13

D 124 PL

0.76 (0.030)

0.17(0.007)

T A

MILLIMETERS

INCHES

DIM

MIN

MAX

MIN

MAX

34.04

35.05

1.340

1.380

NOTES:

2.92

0.44

3.18

0.55

0.115

0.017

0.135

0.022

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2.54 BSC

0.100 BSC

CONTROLLING DIMENSION: INCH

4.32

1.02

2.79

4.95

1.52

3.81

0.195

0.170

0.040

0.110

DIMENSION D INCLUDES LEAD FINISH.

0.060

0.150

30.48 BSC

1.200 BSC

MOTOROLA

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or

design. Motorola does not assume any liability arising out of the application or use of any product or circuit described

herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could

create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,

affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and

the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action

Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution: P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive Blakelands, Milton Keynes, MK14 5BP,

England.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.

ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial

Estate, Tai Po, N.T., Hong Kong.

µ MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Part Number

Keyword

Contains

Advanced | Parametrics

Home Products Applications Support

About Freescale

Where to Buy | Contact Us

Freescale > 68K/ColdFire > 68K M680X0 > MC68030

MC68030 : Enhanced 32-Bit Processor

The MC68030 provides a code-compatible upgrade path to the MC68020. It

offers enhanced performance through additional cache, a memory

management unit, and a bursting data bus. The MC68EC030 offers a lower

cost embedded solution by removing the memory management unit.

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MC68030 Features

● On-Chip Memory Management Unit (MC68030)

● Internal Harvard Architecture

● 256 Byte Instruction and Data Caches

● Dynamic Bus Sizing

● Burst Memory Interface

● 18 MIPS @ 50MHz

● Available in 16, 20, 25, 33, 40, and 50 MHz

● MC68EC030 Available in 25 and 40 MHz

Return to Top

Core

I/O

CPU

Operating

Ambient Ambient

L1 Cache

Operating Operating

Performance Frequency

Temp

(Min)

(oC)

Temp Instructional

(Max)

(oC)

Product Family

68K/ColdFire

Voltage

(Spec)

(V)

Voltage

(Max)

(V)

(Max)

(MIPS)

(Max)

(MHz)

(Max)

(kByte)

16,

20,

25,

33,

40,

-40,

70,

0.256

L1 Cache Data

(Max)

Bus Interface

32-bit

Other Peripherals

MMU

Package Description

Availability

(kByte)

CQUAD 132,

PGA 128

0.256

Production Now

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MC68030 Parametrics

MC68030 Documentation

Documentation

Brochure

Size Rev Date Last

Order

Name

68K ColdFire Product Portfolio

Vendor ID Format

Modified Availability

FREESCALE

html

10/14/2002

CFPITCHPAK

Data Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MC68EC030TS Second-Generation

32-Bit Enhanced Embedded Controller

FREESCALE

pdf

169

10/22/1997

MC68EC030TS

Packaging Information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

68030 RC Package Pinout and Case

Diagram

FREESCALE

pdf

541

MC68030RC

Product Change Notices

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MC68030 (RP Package Addendum) -

PCN #2560

MC68030 /68EC030 TQFP End-of-Life FREESCALE

Announcement- PCN#2921

Standardize Packing Quantity for

68030/68040 - PCN #2999

PCN #5325 Citizen RP Package

Discontinuance

Laser Marking of MC68020RC/030RC FREESCALE

Devices, PCN #5826

68020/030 RP Package Discontinuance, FREESCALE

PCN #6093

FREESCALE

html

PCN2560

PCN2921

PCN2999

PCN5325

PCN5826

PCN6093

PCNR00268

2/28/1997

6/30/1997

html

txt

FREESCALE

8/19/1997

FREESCALE

12/22/1999

8/22/2000

11/21/2000

txt

FREESCALE

F91C Mask Set Introduction #R00268

html

8/22/1995

4/04/1995

Additional Passivatrion Machines for

FREESCALE

PCNR00272

the 68030- PCN

html

#MPU-PCN-95-R00272

Die Attach Change for Ceramic Quad FREESCALE

Flat Packages (CQFP)- PCN #R00281

PCNR00281

PCNR00282

html

8/15/1995

8/22/1995

Addendum to PCN#

FREESCALE

MPU-PCN-95-R00268 #R00282

Introduction of F91C (0.8 Micron

68030) in Plastic Packages - PCN#

MPU-PCN-95-R00283

Moisture Sensitivity Level change for FREESCALE

144 TQFP Products - PCN# R00320

FREESCALE

PCNR00283

html

8/23/1995

PCNR00320

PCNR00321

7/13/1996

8/05/1996

MC68030 Alternate Wafer Fab and

Mask Set Introduction - PCN #R00321

FREESCALE

html 22

Reference Manual

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

68000 Family Programmer's Reference FREESCALE

Manual

2338

M68000PRM

pdf

txt

FREESCALE

M68000PRMER

68K Programmer's Ref. Manual Errata

MC68030 Enhanced 32-Bit

FREESCALE

3863

1/01/1992

MC68030UM

Microprocessor User's Manual

pdf

(Complete)

MC68030 Enhanced Microprocessor

User's Manual (Part 1 of 2)

FREESCALE

1/01/1992

4/17/1996

MC68030UM-P1

MC68030UM-P2

MC68EC030UM

pdf 855

pdf 781

pdf 72

MC68030 User's Manual (Part 2 of 2)

MC68EC030 32-Bit Embedded

Controller User's Manual Addendum

Reliability and Quality Information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

FREESCALE

pdf

160

12/31/1998

REL4Q98QI

Product Reliability Information 4Q98

Reports or Presentations

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

FREESCALE

txt

MC680X0OPTAPP

Optimizing 680X0 Applications

Roadmap

Size Rev Date Last

Order

Name

ColdFire Performance Roadmap

Vendor ID Format

FREESCALE

Modified Availability

10/23/2002

COLDFIRERD

pdf

Selector Guide

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

32-Bit Embedded Processors Selector FREESCALE

Guide

600

10/04/2004

SG1001

pdf

Return to Top

MC68030 Design Tools

Hardware Tools

Emulators/Probes/Wigglers

Size Rev

Order

Availability

Name

Vendor ID Format

AVOCET

HMI-200-68030

HMI-200-68030 In-Circuit Emulator

Software

Application Software

Code Examples

Size Rev

Order

Name

Vendor ID Format

# Availability

Dhrystone 1.1 Benchmark C Source Code

File

Dhrystone 2.1 Benchmarking Part 1 (C

Header File)

Dhrystone 2.1 Benchmarking Part 1 (C

Source)

Dhrystone 2.1 Benchmarking Part 3 (C

Source)

Memory Test Software for the M68000

Family

Ackerman Benchmark With a Downloadable FREESCALE

C Source Code File

Fibonacci Benchmark With Downloadable C FREESCALE

Source Code File

Sieve Benchmark With Downloadable C

Source Code File

FREESCALE

txt

68KDHRY1

68KDHRY2-P1

68KDHRY2-P2

68KDHRY2-P3

M68000MTS

M68KACKBM

M68KFIBBM

M68KSIEBM

FREESCALE

txt

2.1

FREESCALE

txt

FREESCALE

txt

FREESCALE

pdf

115

txt

FREESCALE

Board Support Packages

Size Rev

Order

Name

Vendor ID

Format

# Availability

Metrowerks BSPs for Freescale

Metrowerks BSPs are tested, certified and

frozen, ensuring a fully operational tool chain,

kernel and board specific modules that are ready

to use together within a fixed configuration for

specific hardware reference platforms.

CWS-BSP

METROWERKS

Libraries

Vendor

Size Rev

Order

Name

Format

# Availability

KwikPeg GUI

KADAK's KwikPeg Graphical User Interface (GUI) is

derived from PEG, a professional, high-quality graphic

system created by Swell Software, Inc. to enable you,

the embedded system developer, to easily add graphics

to your products.

PN311-1

KADAK

Operating Systems

Size Rev

Order

Name

Vendor ID Format

# Availability

CMX-RTX

CMX

CMX-RTX

ThreadX

RTOS. Royalty-free real-time operating system

(RTOS) for embedded applications. ThreadX is

small, fast, and royalty-free making it ideal for

high-volume electronic products.

THREADX

EXPRESSLOG

AMX 68000

AMX is a full featured RTOS for the 68k family

including the MC680x0 and MC683xx. AMX has

been tested on the GreenSpring Platfrom332 and

Freescale M68EC040, M68332EVK, MVME133

and M68360QUADS boards.

PN532-1

KADAK

Protocol Stacks

Size Rev

Order

Name

Vendor ID Format

# Availability

CMX TCP/IP

CMX

CMX TCP/IP

KwikNet

The KwikNet TCP/IP Stack enables you to add

networking features to your products with a

minimum of time and expense. KwikNet is a

compact, high performance stack built with

KADAK's characteristic simplicity, flexibility and

reliability.

PN713-1

KADAK

Mocana Embedded SSH Server

MOCANA SSH SERVER: Supports Freescale

chipsets out of the box. Small (50KB), fast (2-3x

faster than OpenSSH), trusted. Supports all major

cryptos. Royalty free, source code license. FREE

EVAL: http://www.mocana.com/evaluate.html

Mocana Embedded SSL/TLS Client

MOCANA SSL/TLS CLIENT: Supports Freescale

chipsets out of the box. Small (50KB), fast (2-3x

MOC_SSH_SVR

MOCANA

MOC_SSL_CLIENT

MOC_SSL_SVR

faster than OpenSSL), trusted. Supports all major

cryptos. Royalty free, source code license. FREE

EVAL: http://www.mocana.com/evaluate.html

Mocana Embedded SSL/TLS Server

MOCANA SSL/TLS SERVER: Supports

Freescale chipsets out of the box. Small (50KB),

fast (2-3x faster than OpenSSL), trusted. Supports

all major cryptos. Royalty free, source code

license. FREE EVAL:

MOCANA

http://www.mocana.com/evaluate.html

Software Tools

Assemblers

Size Rev

Order

Availability

Name

Vendor ID Format

FREESCALE

arc

M68000AS332

M68000ASMBLR

M68000ASS_SIM

M68000UNIX

AS332.ARC-Freeware

68K Assembler v 2.71

FREESCALE

lzh

FREESCALE

zip

157

68000 Assembler/Simulator for MS-DOS

68K Assembler-Berkeley UNIX

FREESCALE

arc

FREESCALE

zip

114

M68000XASS

ADX-68K

M680x0 cross assembler MS-DOS

AVOCET

ADX-68K Macro Assembler-Linker and IDE

Code Translation

Size Rev

Order

Availability

Name

Vendor ID Format

FREESCALE

txt

M68000BFP

S-Record to C-Struct or Binary File Program

MicroAPL Limited's ColdFire Assembler Converter

-- FREE!

Assembly-language source-code translation tool,

converts M680x0 and CPU32 assembly- language

code to optimized ColdFire assembly- language.

Compatible with the main ColdFire toolsets.

1.2.7

PORTASM68K

MICROAPL

html

Compilers

Size Rev

Order

Name

Vendor ID Format

# Availability

Amiga Port of Matthew Brandt's CC68K

Compiler

FREESCALE

html

M68000AMPRT

M68000CPLR

FREESCALE

html

68K Compiler

TASKING 68K/ColdFire

The 68K/ColdFire software development toolset

consists of a C/C++/EC++ compiler, macro

assembler, linker/locator, libraries, CrossView Pro

debugger and EDE (Embedded Development

Environment).

68K_COMPILER

ALTIUMLTD

680X0 C Compiler and Assembler

C compiler and assembler for the 68000, 68010,

68020 and CPU32 microprocessors.

C680X0NT

DIAB

CROSS

WINDRIV

Diab C/C++ Compiler

Debuggers

Size Rev

Order

Name

Vendor ID

Format

# Availability

Metrowerks NetROM

A Flexible Platform for Accelerated

Embedded Development: NetROM is a

revolutionary product for embedded software

developers. It provides a flexible debugging

platform that combines high-speed target

communication and debugging capabilties

CWNETROM540A

METROWERKS

Return to Top

Orderable Parts Information

Part Number

Budgetary

Price

QTY

1000+

($US)

Application/

Qualification

Tier

Tape

and

Reel

Pb-Free

Terminations

Package

Description

Status

Info

Order

COMMERCIAL,

INDUSTRIAL

PGA 128

MC68030CRC25C

MC68030CRC33C

MC68030FE16C

Yes

Available $62.64

Available $71.37

Available $31.15

COMMERCIAL,

INDUSTRIAL

CQUAD

132

COMMERCIAL,

INDUSTRIAL

CQUAD

132

COMMERCIAL,

INDUSTRIAL

MC68030FE20C

MC68030FE25C

Yes

Available $31.15

Available $39.27

CQUAD

132

COMMERCIAL,

INDUSTRIAL

CQUAD

132

COMMERCIAL,

INDUSTRIAL

MC68030FE33C

MC68030RC16C

MC68030RC20C

MC68030RC25C

MC68030RC33C

MC68030RC40C

MC68030RC50C

MC68EC030CFE25C

Yes

Available $39.27

Available $41.71

Available $47.41

Available $52.67

Available $58.38

Available $29.84

COMMERCIAL,

INDUSTRIAL

PGA 128

COMMERCIAL,

INDUSTRIAL

COMMERCIAL,

INDUSTRIAL

COMMERCIAL,

INDUSTRIAL

COMMERCIAL,

INDUSTRIAL

COMMERCIAL,

INDUSTRIAL

CQUAD

132

COMMERCIAL,

INDUSTRIAL

CQUAD

132

COMMERCIAL,

INDUSTRIAL

MC68EC030FE25C

Yes

Available $20.71

CQUAD

132

COMMERCIAL,

INDUSTRIAL

MC68EC030FE25CB1

MC68EC030FE40C

Yes

Available

CQUAD

132

COMMERCIAL,

INDUSTRIAL

Available $28.71

NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.

Return to Top

MC68EC030CFE25C [NXP]

相关型号：

MC68EC030FE25C

MC68EC030FE25CB1

MC68EC030FE40C

MC68EC040

MC68EC040FE20B

MC68EC040FE25B

MC68EC040FE33B

MC68EC040RC20

MC68EC040RC20B

MC68EC040RC25B

MC68EC040RC33

MC68EC040RC33B