MC68HC05V7CFN [NXP]
IC,MICROCONTROLLER,8-BIT,6805 CPU,CMOS,LDCC,68PIN,PLASTIC;
| 型号： | MC68HC05V7CFN |
| 厂家： | 
NXP |
| 描述： | IC,MICROCONTROLLER,8-BIT,6805 CPU,CMOS,LDCC,68PIN,PLASTIC 时钟 微控制器 外围集成电路 |
| 文件： | 总170页 (文件大小：980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
HC05V7GRS/D
REV 1.0
68HC05V7
SPECIFICATION
REV 1.0
(General Release)
August 12, 1994
MCU System Design Group
Oak Hill, Texas
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
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Freescale Semiconductor, Inc.
HC05V7GRS/D
REV 1.0
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Freescale Semiconductor, Inc.
MC68HC05V7 Specification Rev. 1.0
TABLE OF CONTENTS
SECTION 1
GENERAL DESCRIPTION ..............................................1
1.1
1.2
1.3
1.4
FEATURES.................................................................................1
MASK OPTIONS ........................................................................2
PIN ASSIGNMENTS...................................................................2
MCU STRUCTURE ....................................................................8
FUNCTIONAL PIN DESCRIPTION ............................................9
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
1.5.11
1.5.12
1.5.13
1.5.14
1.5.15
1.5.16
1.5.17
V
V
V
V
V
V
.....................................................................................9
BATT
AND V ........................................................................9
DD
SS
.....................................................................................9
.....................................................................................9
......................................................................................9
SSA1
SSA2
CCA
AND V
.................................................................9
REFH
REFL
OSC1, OSC2.......................................................................10
RESET ................................................................................11
IRQ (MASKABLE INTERRUPT REQUEST) .......................11
PA0-PA7..............................................................................11
PB0-PB5, PB6/TCMP, PB7/TCAP ......................................11
PC0-PC7 .............................................................................11
AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7........................12
PWM....................................................................................12
PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO .........................12
BUS, LOAD, REXT1, REXT2..............................................12
V
.....................................................................................12
IGN
SECTION 2
MEMORY MAP ..............................................................13
2.1
2.2
2.3
2.4
2.5
SINGLE-CHIP MODE MEMORY MAP.....................................13
I/O AND CONTROL REGISTERS............................................13
RAM..........................................................................................14
ROM .........................................................................................15
EEPROM ..................................................................................15
SECTION 3
EEPROM........................................................................21
3.1
EEPROM PROGRAMMING REGISTER $1C ..........................21
CPEN - Charge Pump Enable.............................................21
ER1:ER0 - Erase Select Bits...............................................21
LATCH.................................................................................22
EERC - EEPROM RC Oscillator Control.............................22
EEPGM - EEPROM Programming Power Enable...............22
OPERATION IN STOP AND WAIT...........................................24
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
SECTION 4
CPU CORE.....................................................................25
4.1
REGISTERS............................................................................. 25
ACCUMULATOR (A) .......................................................... 25
INDEX REGISTER (X)........................................................ 25
STACK POINTER (SP)....................................................... 26
PROGRAM COUNTER (PC) .............................................. 26
CONDITION CODE REGISTER (CCR).............................. 26
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
SECTION 5
INTERRUPTS.................................................................29
5.1
5.2
5.3
5.4
CPU INTERRUPT PROCESSING ........................................... 29
RESET INTERRUPT SEQUENCE........................................... 32
SOFTWARE INTERRUPT (SWI) ............................................. 32
HARDWARE INTERRUPTS .................................................... 32
EXTERNAL INTERRUPT (IRQ)............................................... 32
IRQ CONTROL/STATUS REGISTER (ICSR) $1F ............. 34
EXTERNAL INTERRUPT TIMING...................................... 36
16-BIT TIMER INTERRUPT..................................................... 37
MDLC INTERRUPT.................................................................. 37
SPI INTERRUPT...................................................................... 37
8-BIT TIMER INTERRUPT....................................................... 38
5.5
5.5.1
5.5.2
5.6
5.7
5.8
5.9
SECTION 6
RESETS..........................................................................39
6.1
6.2
EXTERNAL RESET (RESET).................................................. 39
INTERNAL RESETS ................................................................ 40
POWER-ON RESET (POR)................................................ 40
OPERATION IN STOP AND WAIT..................................... 40
COMPUTER OPERATING PROPERLY RESET (COPR).. 42
LOW-VOLTAGE RESET (LVR) .......................................... 43
ILLEGAL ADDRESS........................................................... 44
DISABLED STOP INSTRUCTION...................................... 44
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
SECTION 7
POWER SUPPLY AND REGULATION........................................ 45
7.1
INTERNAL POWER SUPPLY.................................................. 45
PRIMARY 5V REGULATOR............................................... 45
SECONDARY REGULATOR.............................................. 45
MISCELLANEOUS REGISTER ............................................... 46
IGNS - Ignition status bit..................................................... 46
OCE - Output compare enable ........................................... 46
PDC - Power Down Control ................................................ 46
POWER MODING.................................................................... 47
REGULATOR CONTROL LOGIC ............................................ 49
MASK OPTIONS................................................................. 50
POWER SUPPLY CONFIGURATION ..................................... 53
DECOUPLING RECOMMENDATIONS.............................. 53
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.4.1
7.5
7.5.1
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
SECTION 8
LOW-POWER MODES ..................................................57
8.1
8.1.1
8.1.2
STOP INSTRUCTION ..............................................................57
STOP MODE.......................................................................57
WAIT INSTRUCTION..........................................................59
SECTION 9
PARALLEL I/O...............................................................61
9.1
PORT A AND PORT C .............................................................61
PORT A/C DATA REGISTERS ............................................61
PORT A/C DATA DIRECTION REGISTER..........................62
PORT A/C I/O PIN INTERRUPTS.......................................62
PORT B ....................................................................................62
PORT B DATA REGISTER ..................................................63
PORT B DATA DIRECTION REGISTER .............................63
PORT D AND PORT E .............................................................63
PORT F.....................................................................................64
PORT F DATA REGISTER ..................................................64
PORT F DATA DIRECTION REGISTER..............................64
9.1.1
9.1.2
9.1.3
9.2
9.2.1
9.2.2
9.3
9.4
9.4.1
9.4.2
SECTION 10
A/D CONVERTER.........................................................65
10.1
ANALOG SECTION..................................................................65
RATIOMETRIC CONVERSION ..........................................65
10.1.1
10.1.2
10.1.3
10.2
10.3
10.4
10.5
10.6
10.7
V
AND V
...............................................................65
REFH
REFL
ACCURACY AND PRECISION...........................................65
CONVERSION PROCESS.......................................................65
DIGITAL SECTION...................................................................65
A/D STATUS AND CONTROL REGISTER (ADSCR)..............66
A/D DATA REGISTERS ...........................................................67
A/D DURING WAIT MODE.......................................................68
A/D DURING STOP MODE......................................................68
SECTION 11
16-BIT TIMER ...............................................................69
11.1
11.2
11.3
11.4
COUNTER REGISTER - $18:$19, $1A:$1B.............................70
OUTPUT COMPARE REGISTER - $16:$17 ............................70
INPUT CAPTURE REGISTER - $14:$15 .................................71
TIMER CONTROL REGISTER (TCR) - $12.............................72
ICIE - Input Capture Interrupt Enable..................................72
OCIE - Output Compare Interrupt Enable ...........................72
TOIE - Timer Overflow Interrupt Enable..............................72
TON - Timer On...................................................................72
IEDG - Input Edge...............................................................72
OLVL - Output Level............................................................72
TIMER STATUS REGISTER (TSR) - $13 ................................72
ICF - Input Capture Flag......................................................73
OCF - Output Compare Flag...............................................73
TOF - Timer Overflow Flag..................................................73
Bits 0-4 - Not used...............................................................73
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.5
11.5.1
11.5.2
11.5.3
11.5.4
MOTOROLA
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11.6
11.7
TIMER DURING WAIT MODE ................................................. 73
TIMER DURING STOP MODE ................................................ 73
SECTION 12
CORE TIMER ................................................................75
12.1
CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08.... 76
CTOF - Core Timer Over Flow............................................ 76
RTIF - Real Time Interrupt Flag.......................................... 76
TOFE - Timer Over Flow Enable ........................................ 76
RTIE - Real Time Interrupt Enable...................................... 76
TOFC - Timer Over Flow Flag Clear................................... 76
RTFC - Real Time Interrupt Flag Clear............................... 77
RT1:RT0 - Real Time Interrupt Rate Select........................ 77
COMPUTER OPERATING PROPERLY (COP) RESET.......... 77
CORE TIMER COUNTER REGISTER (CTCR) $09 ................ 78
TIMER DURING WAIT MODE ................................................. 78
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
12.1.7
12.2
12.3
12.4
SECTION 13
PULSE WIDTH MODULATOR......................................79
13.1
13.2
13.2.1
13.2.2
13.3
FUNCTIONAL DESCRIPTION................................................. 79
REGISTERS............................................................................. 81
PWM CONTROL................................................................. 81
PWM DATA REGISTERS................................................... 82
PWM DURING WAIT MODE.................................................... 82
PWM DURING STOP MODE................................................... 82
PWM DURING RESET ............................................................ 82
13.4
13.5
SECTION 14
SERIAL PERIPHERAL INTERFACE.............................83
14.1
SPI SIGNAL DESCRIPTION.................................................... 83
Master In Slave Out (MISO/PF3)........................................ 84
Master Out Slave In (MOSI/PF2)........................................ 84
Serial Clock (SCK/PF1) ...................................................... 84
Slave Select (SS/PF0) ........................................................ 85
FUNCTIONAL DESCRIPTION................................................. 85
SPI REGISTERS...................................................................... 87
Serial Peripheral Control Register (SPCR)......................... 87
Serial Peripheral Status Register (SPSR)........................... 88
Serial Peripheral Data I/O Register (SPDR) ....................... 89
SPI IN STOP MODE ............................................................... 90
SPI IN WAIT MODE ................................................................. 90
14.1.1
14.1.2
14.1.3
14.1.4
14.2
14.3
14.3.1
14.3.2
14.3.3
14.4
14.5
SECTION 15
MESSAGE DATA LINK CONTROLLER.......................91
15.1
OUTLINE.................................................................................. 92
MDLC OPERATING MODES ............................................. 93
MODE DESCRIPTIONS ..................................................... 93
MDLC CPU INTERFACE ......................................................... 95
OUTLINE ............................................................................ 95
MDLC CONTROL REGISTER (MCR) $0E......................... 96
MDLC STATUS REGISTER (MSR) $0F............................. 99
15.1.1
15.1.2
15.2
15.2.1
15.2.2
15.2.3
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
15.2.4
15.2.5
15.3
15.3.1
15.3.2
15.3.3
15.4
15.4.1
15.4.2
15.4.3
15.5
15.5.1
15.5.2
15.5.3
15.5.4
15.5.5
15.6
15.6.1
15.6.2
15.6.3
15.7
15.7.1
15.7.2
15.7.3
15.7.4
15.7.5
15.7.6
15.7.7
MDLC TX CONTROL REGISTER (MTCR) $10................100
MDLC RX STATUS REGISTER (MRSR) $11...................101
MDLC Rx/Tx BUFFERS .........................................................103
OUTLINE...........................................................................103
RX BUFFERS....................................................................105
TX BUFFER ......................................................................106
MDLC PROTOCOL HANDLER ..............................................108
OUTLINE...........................................................................108
Rx & Tx SHIFT REGISTERS ............................................108
STATE MACHINE .............................................................109
MDLC MUX INTERFACE .......................................................112
Rx DIGITAL FILTER..........................................................112
J1850 FRAME FORMAT...................................................114
J1850 VPW SYMBOLS.....................................................116
J1850 VPW VALID/INVALID BITS & SYMBOLS ..............117
MESSAGE ARBITRATION ...............................................121
MDLC PHYSICAL INTERFACE .............................................123
OUTLINE...........................................................................123
MUX INTERFACE SIGNALS ............................................126
PINS..................................................................................127
MDLC APPLICATION NOTES ...............................................128
INITIALIZATION................................................................128
TRANSMITTING A MESSAGE .........................................128
RECEIVING A MESSAGE ................................................128
RECEIVING A MESSAGE IN BLOCK MODE...................129
MDLC STOP MODE..........................................................130
MDLC WAIT MODE ..........................................................130
CONTROLLING EXTERNAL VOLTAGE
REGULATORS................................................................130
SECTION 16
INSTRUCTION SET....................................................133
16.1
16.2
16.3
16.4
16.5
16.6
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
16.6.6
16.6.7
16.6.8
16.6.9
16.6.10
REGISTER/MEMORY INSTRUCTIONS ................................133
READ-MODIFY-WRITE INSTRUCTIONS..............................133
BRANCH INSTRUCTIONS.....................................................134
BIT MANIPULATION INSTRUCTIONS...................................134
CONTROL INSTRUCTIONS ..................................................135
ADDRESSING MODES..........................................................135
IMMEDIATE ......................................................................136
DIRECT.............................................................................136
EXTENDED.......................................................................136
RELATIVE.........................................................................136
INDEXED, NO OFFSET....................................................136
INDEXED, 8-BIT OFFSET ................................................136
INDEXED, 16-BIT OFFSET ..............................................137
BIT SET/CLEAR................................................................137
BIT TEST AND BRANCH..................................................137
INHERENT........................................................................137
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
SECTION 17
ELECTRICAL SPECIFICATIONS................................139
17.1
MAXIMUM RATINGS............................................................. 139
THERMAL CHARACTERISTICS ........................................... 139
DC ELECTRICAL CHARACTERISTICS................................ 140
REGULATOR ELECTRICAL CHARACTERISTICS............... 141
CONTROL TIMING ................................................................ 142
A/D CONVERTER CHARACTERISTICS............................... 143
DC ELECTRICAL CHARACTERISTICS................................ 144
CONTROL TIMING ................................................................ 145
LVR TIMING DIAGRAM......................................................... 146
SPI TIMING............................................................................ 147
MDLC ELECTRICAL SPECIFICATIONS............................... 150
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
17.11.1
17.11.2
17.11.3
ABSOLUTE MAXIMUM RATINGS ................................... 150
OPERATING CONDITIONS ............................................. 150
TRANSMITTER D.C. ELECTRICA
CHARACTERISTICS...................................................... 150
TRANSMITTER A.C. ELECTRICAL
17.11.4
CHARACTERISTICS...................................................... 151
RECEIVER D.C. ELECTRICAL CHARACTERISTICS ..... 151
TRANSMITTER VPW SYMBOL TIMINGS ....................... 151
RECEIVER VPW SYMBOL TIMINGS .............................. 152
17.11.5
17.11.6
17.11.7
SECTION 18
05V7 BEHAVIOR DURING EMULATION....................155
18.1
18.2
18.3
COP........................................................................................ 155
MDLC ..................................................................................... 155
REGULATOR......................................................................... 155
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
LIST OF FIGURES
Figure 1-1:
Figure 1-2:
Figure 1-3:
Figure 1-4:
Figure 1-5:
Figure 1-6:
Figure 1-7:
MC68HC05V7 Pin Assignments (56 pin package)................................3
MC68HC05V7 Pin Assignments (68-pin PLCC package).....................4
MC68HC05V7 Pin Assignments (64-pin QFP)......................................5
MC68HC05V7 Bonding Diagram Circuit Side Up..................................6
MC68HC05V7 Bonding Diagram Circuit Side Down.............................7
MC68HC05V7 Block Diagram...............................................................8
Oscillator Connections.........................................................................10
Figure 2-1:
Figure 2-2:
Figure 2-3:
Figure 2-4:
Figure 2-5:
Figure 2-6:
MC68HC05V7 Single-Chip Mode Memory Map.................................13
MC68HC05V7 I/O Registers Memory Map .........................................14
MC68HC05V7 I/O Registers $0000-$000F.........................................16
MC68HC05V7 I/O Registers $0010-$001F.........................................17
MC68HC05V7 I/O Registers $0020-$002F.........................................18
MC68HC05V7 I/O Registers $0030-$003F.........................................19
Figure 3-1:
Figure 4-1:
Programming Register.........................................................................21
MC68HC05 Programming Model ........................................................25
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Interrupt Processing Flowchart............................................................31
IRQ Function Block Diagram...............................................................33
IRQ Status & Control Register.............................................................35
External Interrupts Timing Diagram.....................................................37
Figure 6-1:
Figure 6-2:
Figure 6-3:
Reset Block Diagram...........................................................................39
RESET and POR Timing Diagram ......................................................41
COP Watchdog Timer Location...........................................................43
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Miscellaneous Register .......................................................................46
MC68HC05V7 Power Moding Flow Diagram ......................................48
Regulator Startup ................................................................................49
Using the 68HC05V7 with an External Regulator................................51
Power Moding Block Diagram .............................................................52
MC68HC05V7 On-chip Power Supply Configuration ..........................53
HC705V8 Internal Power Routing .......................................................54
Figure 8-1:
Figure 8-2:
Stop Recovery Timing Diagram...........................................................58
STOP/WAIT Flowcharts.......................................................................59
MOTOROLA
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Figure 9-1:
Figure 9-2:
Figure 9-3:
Port A and Port C I/O Circuitry............................................................ 61
Port B I/O Circuitry .............................................................................. 63
Port D and Port E Circuitry.................................................................. 64
Figure 10-1:
Figure 10-2:
A/D Status and Control Register......................................................... 66
A/D Data Register ............................................................................... 67
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
16-Bit Timer Block Diagram ................................................................ 69
Timer Control Register - $12............................................................... 72
Timer Status Register - $13 ................................................................ 72
TCAP Timing....................................................................................... 74
Figure 12-1:
Figure 12-2:
Figure 12-3:
Core Timer Block Diagram.................................................................. 75
Core Timer Control and Status Register............................................. 76
Timer Counter Register....................................................................... 78
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
PWM Block Diagram........................................................................... 79
PWM Waveform Examples (POL = 1)................................................. 80
PWM Waveform Examples (POL = 0)................................................. 80
PWM Write Sequences....................................................................... 81
PWM Control Register ........................................................................ 81
PWM Data Register ............................................................................ 82
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Figure 14-5:
Figure 14-6:
Data Clock Timing Diagram ................................................................ 84
Serial Peripheral Interface Block Diagram .......................................... 86
Serial Peripheral Interface Master-Slave Interconnection................... 87
SPI Control Register (SPCR).............................................................. 87
Serial Peripheral Rate Selection ......................................................... 88
SPI Status Register (SPSR)................................................................ 88
Figure 15-1:
Figure 15-2:
Figure 15-3:
Figure 15-4:
Figure 15-5:
Figure 15-6:
Figure 15-7:
Figure 15-8:
Figure 15-9:
Figure 15-10:
Figure 15-11:
Figure 15-12:
MDLC Operating Modes State Diagram ............................................. 93
MDLC User Registers ......................................................................... 95
MDLC Control Register (MCR) ........................................................... 96
MDLC Status Register (MSR)............................................................. 99
MDLC Tx Control Register (MTCR) .................................................. 100
MDLC Rx Status Register (MRSR)................................................... 101
MDLC Rx/Tx Buffers Outline............................................................. 105
MDLC Protocol Handler Outline........................................................ 108
MDLC Rx Digital Filter Block Diagram .............................................. 112
J1850 Bus Message Format (VPW).................................................. 114
J1850 VPW Symbols ........................................................................ 116
J1850 VPW Passive Symbols........................................................... 118
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Figure 15-13:
Figure 15-14:
Figure 15-15:
Figure 15-16:
J1850 VPW EOF and IFS Symbols...................................................119
J1850 VPW Active Symbols..............................................................120
J1850 VPW Bitwise Arbitration..........................................................121
MDLC Physical Interface Outline.......................................................125
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
Figure 17-5:
Figure 17-6:
SPI MASTER TIMING (CPHA = 0)....................................................148
SPI MASTER TIMING (CPHA = 1)....................................................148
SPI SLAVE TIMING (CPHA = 0).......................................................149
SPI SLAVE TIMING (CPHA = 1).......................................................149
Transmitter A.C. Electrical Characteristics........................................151
Variable Pulse Width Modulation (VPW) Symbol Timings ................153
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MC68HC05V7 Specification Rev. 1.0
LIST OF TABLES
Table 3-1:
Table 3-2:
Erase Mode Select ..............................................................................22
EEPROM Write/Erase Cycle Reduction..............................................23
Table 5-1:
Table 6-1:
Table 10-1:
Table 12-1:
Table 13-1:
Vector Address for Interrupts and Reset .............................................29
COP Watchdog Timer Recommendations ..........................................43
A/D Channel Assignments...................................................................67
RTI and COP Rates at 2.1 MHz ..........................................................77
PWM Clock Rate .................................................................................81
Table 15-1:
Table 15-2:
Table 15-3:
MDLC Transmit Abort Function Summary...........................................97
MDLC Rate Selection..........................................................................98
MDLC J1850 Bus Error Summary.....................................................111
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MC68HC05V7 Specification Rev. 1.0
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MC68HC05V7 Specification Rev. 1.0
SECTION 1
GENERAL DESCRIPTION
The Motorola MC68HC05V7 microcontroller is a custom HC05 based MCU featuring a
Message Data Link Controller (MDLC) module and on-chip power regulation (ROM version
of the MC68HC705V8). The device is available packaged in a 56-pin SDIP, 68-pin PLCC,
or 64-pin QFP. A functional block diagram of the MC68HC05V7 is shown in Figure 1-6.
1.1
FEATURES
• Low cost, HC05 Core
• 10K Bytes of User ROM
• 384 Bytes of User RAM
• 128 Bytes of byte erasable EEPROM
-
Byte writeable
-
Byte, Block or Bulk erasable
• Message Data Link Controller (MDLC) module
• 16 channel 8-bit A/D converter (8 channels available in 56 SDIP version)
• Full function Serial Peripheral Interface (SPI)
• On-Chip Oscillator for Crystal/Ceramic Resonator
• 8-bit timer with Real Time Interrupt
• 16-bit timer with 1 input capture and 1 output compare
• 38 frequency 6-bit PWM
• COP Watchdog System
• 22 general purpose I/O pins, 16 with interrupt wake-up capability
6 I/O pins muxed with Timer and SPI pins. 16 Input Only pins muxed with
A/D.
• Mask option Low Voltage Reset (LVR).
• On-chip 5V MCU power regulator (mask option to disable)
• Power Saving STOP and WAIT Mode Instructions
(Mask Selectable STOP Instruction Disable)
SECTION 1: GENERAL DESCRIPTION
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MC68HC05V7 Specification Rev. 1.0
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, or frequency specified in the following sections will refer to the
nominal values. The exact values and their tolerance or limits are
specified in SECTION 17 ELECTRICAL SPECIFICATIONS.
1.2
MASK OPTIONS
The following mask options are available:
• Sensitivity on IRQ Interrupt, Edge- and Level-Sensitive or Edge-Sensitive
Only
• Selectable COP Watchdog System
• Selectable Low Voltage Reset (LVR)
• Selectable STOP Instruction Disable
• Selectable on-chip power supply regulator
• Selectable option to allow regulator wakeup on a rising edge of the MDLC
Bus
• Selectable option to tie the regulator output to V
when turned off
SS
1.3
PIN ASSIGNMENTS
The MC68HC05V7 requires 64 bond pads for all I/O and power supply functions. The
device is available in a 56-pin SDIP package where the 8 A/D channels associated with
Port E are not bonded out (AN8 thru AN15). The device is also available in the 68 pin PLCC
and 64 pin QFP packages.
The pin out for the 56-pin SDIP, the 68-pin PLCC, and the 64-pin QFP packages are shown
in the following figures. The pad positions are also in the following figures.
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MC68HC05V7 Specification Rev. 1.0
.
PWM
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
V
OSC2
OSC1
RST
SSD
2
DD
3
4
5
6
IRQ
7
PF3/MISO
PF2/MOSI
PF1/SCLK
PF0/SS
PB0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PB1
PB2
PB3
PB4
PB5
PB6/TCMP
PB7/TCAP
PD7/AN7
PD6/AN6
PD5/AN5
PD4/AN4
PD3/AN3
V
SSA2
LOAD
BUS
V
BATT
REXT2
REXT1
V
REFL
V
SSA1
V
V
V
V
IGN
CCA
V
DD
REFH
PD2/AN2
PD1/AN1
SSD
PD0/AN0
Note:This pin assignment is subject to change
Figure 1-1: MC68HC05V7 Pin Assignments (56-pin package)
SECTION 1: GENERAL DESCRIPTION
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Pin numbers
60 PC7
59 PC6
58 PC5
57 PC4
56 PC3
55 PC2
54 PC1
53 PC0
PF3/MISO 10
PF2/MOSI 11
PF1/SCLK 12
PF0/SS 13
PB0 14
PB1 15
PB2 16
PB3 17
52 PE7/AN15
51 PE6/AN14
50 PE5/AN13
49 PE4/AN12
48 PD7/AN7
47 PD6/AN6
46 PD5/AN5
45 PD4/AN4
44 PD3/AN3
PB4 18
PB5 19
PB6/TCMP 20
PB7/TCAP 21
V
22
SSA2
LOAD 23
BUS 24
V
25
BATT
N.C. 26
Figure 1-2: MC68HC05V7 Pin Assignments (68-pin PLCC package)
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MC68HC05V7 Specification Rev. 1.0
Pin numbers
48 PC6
PF3/MISO
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC5
PC4
PC3
PC2
PC1
PC0
PE7/AN15
PE6/AN14
PE5/AN13
PE4/AN12
PD7/AN7
PD6/AN6
PD5/AN5
PD4/AN4
PD3/AN3
PF2/MOSI
PF1/SCLK
PF0/SS
PB0
PB1
PB2
PB3
PB4
PB5 10
PB6/TCMP 11
PB7/TCAP 12
V
13
SSA2
LOAD 14
BUS 15
V
16
BATT
Figure 1-3: MC68HC05V7 Pin Assignments (64-pin QFP)
SECTION 1: GENERAL DESCRIPTION
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PF3/MISO
PF2/MOSI
PF1/SCLK
PF0/SS
PB0
PC7
PC6
PC5
PC4
PC3
PB1
PC2
PB2
PC1
PB3
PC0
PE7/AN15
PE6/AN14
PE5/AN13
PE4/AN12
PD7/AN7
PD6/AN6
PD5/AN5
PD4/AN4
PD3/AN3
PB4
PB5
PB6/TCMP
PB7/TCAP
V
SSA2
LOAD
BUS
V
BATT
Figure 1-4: MC68HC05V7 Bonding Diagram
Circuit Side Up
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PF3/MISO
PF2/MOSI
PF1/SCLK
PF0/SS
PB0
PC7
PC6
PC5
PC4
PC3
PB1
PC2
PB2
PC1
PC0
PB3
PE7/AN15
PE6/AN14
PE5/AN13
PE4/AN12
PD7/AN7
PD6/AN6
PD5/AN5
PD4/AN4
PD3/AN3
PB4
PB5
PB6/TCMP
PB7/TCAP
V
SSA2
LOAD
BUS
V
BATT
Figure 1-5: MC68HC05V7 Bonding Diagram
Circuit Side Down
SECTION 1: GENERAL DESCRIPTION
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1.4
MCU STRUCTURE
The overall block diagram of the MC68HC05V7 is shown in Figure 1-6.
PF3/MISO
PF2/MOSI
PF1/SCLK
PF0/SS
OSC 1
OSCILLATOR
÷2
OSC 2
SPI
PC7 *
PC6 *
PC5 *
PC4 *
PC3 *
PC2 *
PC1 *
PC0 *
RESET
WATCHDOG
ALU
IRQ
CPU CONTROL
AD0/PD0
68HC05 CPU
AD1/PD1
AD2/PD2
AD3/PD3
AD4/PD4
AD5/PD5
AD6/PD6
AD7/PD7
ACCUM
CPU REGISTERS
INDEX REG
PB7/TCAP
PB6/TCMP
PB5
0 0 0 0 0 0 0 0 1 1 STK PTR
1
PROGRAM COUNTER
PB4
PB3
V
COND CODE REG 1 1 1 H I N Z C
REFH
V
PB2
REFL
PB1
AD8/PE0
AD9/PE1
PB0
SRAM -384 BYTES
AD10/PE2
AD11/PE3
AD12/PE4
AD13/PE5
AD14/PE6
AD15/PE7
PA7 *
PA6 *
PA5 *
PA4 *
PA3 *
PA2 *
PA1 *
PA0 *
USER ROM -10K BYTES
EEPROM -128 BYTES
8-BIT TIMER with RTI
E not bonded out
-pin SDIP
16-BIT TIMER with
1 IPC & 1 OPC
V
SSA1
1 Channel
38 frequency, 6-bit PWM
PWM
BUS
Interrupt
MDLC
Internal
LOAD
REXT1
REXT2
LVR
V
DD
V
BATT
MCU POWER SUPPLY
REGULATION
V
IGN
CLKIN
V
V
SSA2
CCA
To A/D
V
CC
V
DD
V
DD
V
SSD
V
SSD
* IRQ Interrupt Capability
Figure 1-6: MC68HC05V7 Block Diagram
MOTOROLA
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1.5
FUNCTIONAL PIN DESCRIPTION
The following paragraphs give a description of the general function of each pin.
1.5.1
Power is supplied to the device through the V
V
BATT
pin. The on-chip voltage regulator uses
BATT
this voltage to derive the internal V supply for the MCU. The V
pin is also used to
DD
BATT
power the MDLC and should still be connected even when the Voltage Regulator is not
used. See SECTION 7 POWER SUPPLY AND REGULATION.
1.5.2
V
AND V
DD SS
These pins are provided to allow the internally generated V
supply to be externally
DD
decoupled. The short rise and fall times of the MCU supply current transients place very
high short-duration current demands on the internal power supply. To prevent noise
problems, special care should be taken to provide good power supply bypassing at the
MCU by using bypass capacitors with good high-frequency characteristics that are
positioned as close to the MCU supply pins as possible. Two sets of V and V pins are
DD
SS
required to maintain on-chip supply noise to within acceptable limits. Each supply pin pair
will require its own decoupling capacitor. See SECTION 7 POWER SUPPLY AND
REGULATION.
1.5.3
V
SSA1
V
is a separate ground pad, which provides a ground return for the A/D subsystem. To
SSA1
prevent digital noise contamination, this pin should be connected directly to a low
impedance ground reference point.
1.5.4
V
SSA2
V
is a separate ground pad, which provides a ground return for the MDLC analog
SSA2
subsystem. To prevent digital noise contamination, this pin should be connected directly to
a low impedance ground reference point.
1.5.5
V
CCA
V
is a separate supply pin providing power to the analog subsystems of the MDLC and
CCA
A/D converter. This pin should be connected to the V
pin externally. To prevent
DD
contamination from the digital supply, this pin should be adequately decoupled to a low
impedance ground reference. See SECTION 7 POWER SUPPLY AND REGULATION.
1.5.6
V
AND V
REFH REFL
V
is the positive (high) reference voltage for the A/D subsystem. V
is the negative
REFH
REFL
(low) reference voltage for the A/D subsystem. V
and V
should be isolated from
REFH
REFL
the digital supplies to prevent any loss of accuracy from the A/D converter.
SECTION 1: GENERAL DESCRIPTION
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1.5.7 OSC1, OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator. OSC1 is the input
to the oscillator inverter. The output (OSC2) will always reflect OSC1 inverted except when
the device is in STOP mode, which forces OSC2 high. The OSC1, and OSC2 pins can
accept the following sets of components:
1. A crystal as shown in Figure 1-7(a)
2. A ceramic resonator as shown in Figure 1-7(a)
3. An external clock signal as shown in Figure 1-7(b)
The frequency, f
, of the oscillator or external clock source is divided by two to produce
OSC
the internal operating frequency, f .
OP
1.5.7.1
Crystal Oscillator
The circuit in Figure 1-7(a) shows a typical oscillator circuit for an AT-cut, parallel resonant
crystal. The crystal manufacturer’s recommendations should be followed, as the crystal
parameters determine the external component values required to provide maximum
stability and reliable start-up. The load capacitance values used in the oscillator circuit
design should include all stray capacitances. The crystal and components should be
mounted as close as possible to the pins for start-up stabilization and to minimize output
distortion and radiated emissions.
MCU
MCU
OSC1
OSC2
OSC1
OSC2
unconnected
External Clock
(a) Crystal or
Ceramic Resonator
Connections
(b)External
Clock Source
Connection
Figure 1-7: Oscillator Connections
Ceramic Resonator Oscillator
1.5.7.2
In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The
circuit in Figure 1-7(a) is for a ceramic resonator. The resonator manufacturer’s
recommendations should be followed, as the resonator parameters determine the external
component values required for maximum stability and reliable starting. The load
capacitance values used in the oscillator circuit design should include all stray
capacitances. The ceramic resonator and components should be mounted as close as
possible to the pins for start-up stabilization and to minimize output distortion and radiated
emissions.
MOTOROLA
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1.5.7.3
External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1
input. The OSC2 pin should be left unconnected, as shown in Figure 1-7(b).
1.5.8
RESET
This pin can be used as an input to reset the MCU to a known start-up state by pulling it to
the low state. The RESET pin contains an internal Schmitt trigger to improve its noise
immunity as an input. The RESET pin has an internal pulldown device that pulls the RESET
pin low when there is an internal COP Watchdog reset, POR, illegal address reset, a
disabled STOP instruction reset, or an internal low voltage reset. Refer to SECTION 6
RESETS.
1.5.9
IRQ (MASKABLE INTERRUPT REQUEST)
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt
function has a mask option to select either negative edge-sensitive triggering or both
negative edge-sensitive and low level-sensitive triggering. The IRQ input requires an
external resistor to V for “wire-OR” operation, if desired. If the IRQ pin is not used, it must
DD
be tied to the V supply. The IRQ pin contains an internal Schmitt trigger as part of its input
DD
to improve noise immunity. Each of the PA0 thru PA7 and PC0 thru PC7 I/O pins may be
connected as an OR function with the IRQ interrupt function. This capability allows
keyboard scan applications where the transitions on the I/O pins will behave the same as
the IRQ pin. The edge or level sensitivity selected by a mask option for the IRQ pin does
not apply to the I/O pin interrupt. The I/O pin interrupt is always negative edge sensitive.
See SECTION 5 INTERRUPTS for more details on the interrupts.
1.5.10
PA0-PA7
These eight I/O lines comprise Port A. The state of any pin is software programmable and
all Port A lines are configured as inputs during power-on or reset. All eight pins are
connected via an internal gate to the IRQ interrupt function. When the IRQ interrupt function
is enabled, all the Port A pins will act as negative edge sensitive IRQ sources. See
SECTION 9 PARALLEL I/O for more details on the I/O ports.
1.5.11
PB0-PB5, PB6/TCMP, PB7/TCAP
These eight I/O lines comprise Port B. The state of any pin is software programmable and
all Port B lines are configured as inputs during power-on or reset. See SECTION 9
PARALLEL I/O for more details on the I/O ports. PB6 and PB7 are also shared with timer
functions. The TCAP pin controls the input capture feature for the on-chip 16-bit timer. The
TCMP pin provides an output for the output compare feature of the on-chip 16-bit timer. See
SECTION 11 16-BIT TIMER for more details on the operation of the timer subsystem.
1.5.12
PC0-PC7
These eight I/O lines comprise Port C. The state of any pin is software programmable and
all Port C lines are configured as inputs during power-on or reset. All eight pins are
connected via an internal gate to the IRQ interrupt function. When the IRQ interrupt function
SECTION 1: GENERAL DESCRIPTION
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is enabled, all the Port C pins will act as negative edge sensitive IRQ sources. See
SECTION 9 PARALLEL I/O for more details on the I/O ports.
1.5.13
AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7
When the A/D converter is disabled, PD0-PD7 and PE0-PE7 are general purpose input
pins. The A/D converter is disabled upon exiting from reset. When the A/D converter is
enabled, one of these pins is the analog input to the A/D converter. The A/D control register
contains control bits to direct which of the analog inputs are to be converted at any one
time. A digital read of this pin when the A/D converter is enabled results in a read of logical
zero from the selected analog pin. A digital read of the remaining pins gives their correct
(digital) values. A/D inputs AD8-AD15 (Port E) are not bonded out in the 56-pin package.
See SECTION 10 A/D CONVERTER for more details on the operation of the A/D
subsystem.
1.5.14
PWM
This pin provides an output for the pulse width modulation feature of the on-chip
programmable timer. See SECTION 13 PULSE WIDTH MODULATOR for more details on
the operation of the PWM subsystem.
1.5.15
PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO
These four I/O lines comprise Port F. The state of any pin is software programmable and
all Port F lines are configured as inputs during power-on or reset. See SECTION 9
PARALLEL I/O for more details on the I/O ports. When the SPI subsystem is enabled, PF0-
PF3 become the data, clock and select lines for the SPI. See SECTION 14 SERIAL
PERIPHERAL INTERFACE for more details on the operation of the SPI subsystem.
1.5.16
BUS, LOAD, REXT1, REXT2
These pins provide the I/O interface and external biasing functions for the MDLC
subsystem. See SECTION 15 MESSAGE DATA LINK CONTROLLER for more details on
the operation of the MDLC subsystem. The regulator control logic monitors the BUS pin and
latches a rising edge to re-enable the primary voltage regulator if this mask option is
enabled.
1.5.17
V
IGN
The V
pin is used by the internal voltage regulator power moding circuitry to indicate that
IGN
the regulator should power up. Its state is reflected in the IGNS bit of the MISC register.
The input voltage levels on this pin are ratioed to the voltage on V . See the electrical
BATT
specifications. A smaller secondary regulator remains alive to power the V
pin logic
IGN
when the primary voltage regulator is powered down, allowing the power moding logic to
recognize and latch a rising edge on this pin and re-enable the primary regulator (power-
up). See SECTION 7 POWER SUPPLY AND REGULATION for a more detailed
description.
The V
pin has no function when the option to disable the on-chip voltage regulator is
IGN
selected and should be tied low.
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SECTION 2
MEMORY MAP
2.1
SINGLE-CHIP MODE MEMORY MAP
When the MC68HC05V7 is in the Single-Chip Mode the I/O and peripherals, user RAM,
EEPROM and user ROM are all active as shown in Figure 2-1.
$0000
0000
$0000
I/O
64 Bytes
I/O
Registers
$003F
$0040
0063
0064
64 bytes
(see Figure 2-
2)
User RAM
(128 Bytes)
$00BF
$00C0
0191
0192
Stack
(64 Bytes)
$003F
$00FF
$0100
0255
0256
User RAM
192 Bytes
$01BF
$01C0
0447
0448
COP Watchdog Timer
unused
$3FF0
$3FF1
$3FF2
$3FF3
$3FF4
$3FF5
$3FF6
$3FF7
Unused
128 Bytes
0575
0576
$023F
$0240
8-Bit Timer (High Byte)
8-Bit Timer (Low Byte)
SPI (High Byte)
User EEPROM
128 Bytes
0703
0704
$02BF
$02C0
Unused
4928 Bytes
SPI (Low Byte)
$15FF
$1600
5631
5632
MDLC (High Byte)
MDLC (Low Byte)
2
Selfcheck/E test
ROM 512 Byes
16-Bit Timer Vector (High Byte) $3FF8
16-Bit Timer Vector (Low Byte) $3FF9
$17FF
$1800
6143
6144
User ROM
10208 Bytes
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
$3FFA
$3FFB
$3FFC
$3FFD
$3FFE
$3FFF
$3FDF
$3FE0
16351
16352
Selfcheck Vectors
ROM 16 Bytes
$3FEF
$3FF0
16367
16368
User Vectors ROM
16 Bytes
$3FFF
16383
Figure 2-1: MC68HC05V7 Single-Chip Mode Memory Map
2.2
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000-$003F. The overall organization of
these registers is shown in Figure 2-2. The bit assignments for each register are shown in
SECTION 2: MEMORY MAP
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Figure 2-3, Figure 2-4, Figure 2-5 and Figure 2-6. Reading from unimplemented bits will
return unknown states, and writing to unimplemented bits will be ignored.
MDLC Tx Data Register 0
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
$0000
$0020
MDLC Tx Data Register 1
MDLC Tx Data Register 2
MDLC Tx Data Register 3
MDLC Tx Data Register 4
MDLC Tx Data Register 5
MDLC Tx Data Register 6
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
MDLC Tx Data Register 7
MDLC Tx Data Register 8
MDLC Tx Data Register 9
MDLC Tx Data Register 10
Port E Data Register
Unused
8-Bit Timer Status & Control
8-Bit Timer Counter Register
SPI Control Register
$0008
$0028
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0029
$002A
$002B
$002C
$002D
$002E
$002F
SPI Status Register
SPI Data Register
Unused
Port F Data Register
Unused
Port F Data Direction Register
MDLC Control Register
Miscellaneous Register
MDLC Status Register
MDLC Tx Control Register
PWM Data Register
PWM Control Register
Unused
$0010
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
MDLC Rx Status Register
16-Bit Timer Control Register
16-Bit Timer Status Register
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
Unused
MDLC Rx Data Register 0
MDLC Rx Data Register 1
MDLC Rx Data Register 2
MDLC Rx Data Register 3
Input Capture Register (high)
Input Capture Register (low)
Output Compare Register (high)
Output Compare Register (low)
MDLC Rx Data Register 4
MDLC Rx Data Register 5
16 Bit Timer Count Register (high)
16 Bit Timer Count Register (low)
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0039
$003A
$003B
$003C
$003D
$003E
$003F
MDLC Rx Data Register 6
MDLC Rx Data Register 7
Alt. Count Register (high)
Alt. Count Register (low)
EEPROM Program Register
MDLC Rx Data Register 8
MDLC Rx Data Register 9
A/D Data Register
MDLC Rx Data Register10
Reserved
A/D Status & Control Register
IRQ Control and Status Register
Figure 2-2: MC68HC05V7 I/O Registers Memory Map
2.3
RAM
The total RAM consists of 384 bytes (including the stack). The stack begins at address
$00FF and proceeds down to $00C0 (64 bytes). Using the stack area for data storage or
temporary work locations requires care to prevent it from being overwritten due to stacking
from an interrupt or subroutine call.
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NOTE: The stack is located in the middle of the RAM address space. Data written
to addresses within the stack address range could be overwritten during
stack activity.
2.4
ROM
There are a total of 10752 bytes of user ROM on chip. This includes 10208 bytes of user
ROM for user program storage, 512 bytes of EEPROM test and selfcheck ROM, 16 bytes
of selfcheck vectors and 16 bytes for user vectors and the COP update location.
2.5
EEPROM
This device contains 128 bytes of EEPROM. Programming the EEPROM is performed by
the user on a single-byte basis by manipulating the Programming Register, located at
address $001C. Refer to SECTION 3 EEPROM for programming details.
SECTION 2: MEMORY MAP
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READ
WRITE
ADDR
REGISTER
7
6
5
4
3
2
1
0
R
$0000 PORT A DATA
PA7
PB7
PA6
PB6
PA5
PB5
PA4
PB4
PA3
PB3
PA2
PB2
PA1
PB1
PA0
PB0
W
R
$0001 PORT B DATA
W
R
$0002 PORT C DATA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
W
R
$0003 PORT D DATA
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
W
R
$0004 PORT A DATA DIRECTION
$0005 PORT B DATA DIRECTION
$0006 PORT C DATA DIRECTION
$0007 UNUSED
DDRA7
DDRB7
DDRC7
DDRA6
DDRB6
DDRC6
DDRA5
DDRB5
DDRC5
DDRA4
DDRB4
DDRC4
DDRA3
DDRB3
DDRC3
DDRA2
DDRB2
DDRC2
DDRA1
DDRB1
DDRC1
DDRA0
DDRB0
DDRC0
W
R
W
R
W
R
W
R
CTOF
D7
RTIF
D6
$0008 8 BIT TIMER STATUS/CONTROL
$0009 8 BIT TIMER COUNTER
$000A SPI CONTROL REGISTER
$000B SPI STATUS REGISTER
$000C SPI DATA REGISTER
$000D UNUSED
TOFE
D5
RTIE
D4
RT1
D1
RT0
D0
W
R
TOFC
D3
RTFC
D2
W
R
SPIE
SPIF
SPE
MSTR
MODF
CPOL
SPD3
CPHA
SPD2
SPR1
SPD1
IE
SPR0
W
R
WCOL
W
R
SPD7
SPD6
TXAB
SPD5
R1
SPD4
R0
SPD0
WCM
W
R
W
R
$000E MDLC CONTROL REGISTER
$000F MDLC STATUS REGISTER
RXBM
W
R
TXMS
RXMS
W
UNIMPLEMENTED
ONE TIME WRITE
Figure 2-3: MC68HC05V7 I/O Registers $0000-$000F
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READ
WRITE
ADDR
REGISTER
7
6
5
4
3
2
1
0
R
W
R
$0010 MDLC TX CONTROL REGISTER
$0011 MDLC RX STATUS REGISTER
$0012 TIMER CONTROL REGISTER
$0013 TIMER STATUS REGISTER
$0014 INPUT CAPTURE HIGH
$0015 INPUT CAPTURE LOW
$0016 OUTPUT COMPARE HIGH
$0017 OUTPUT COMPARE LOW
$0018 TIMER COUNTER HIGH
$0019 TIMER COUNTER LOW
$001A ALT. COUNTER HIGH
TC3
RC3
TC2
RC2
TON
TC1
RC1
TC0
RC0
W
R
ICIE
ICF
OCIE
OCF
TOIE
TOF
IEDG
OLVL
W
R
W
R
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
W
R
W
R
15
7
14
6
13
5
12
4
11
3
10
2
9
8
W
R
1
9
0
W
R
15
7
14
13
5
12
4
11
3
10
8
W
R
6
2
1
0
W
R
15
14
13
12
4
11
3
10
9
8
0
W
R
$001B ALT. COUNTER LOW
7
6
5
2
1
W
R
$001C EEPROM PROGRAMMING
$001D A/D DATA
CPEN
D6
ER1
D4
CH4
ER0
D3
LATCH
D2
CH2
EERC
D1
CH1
EEPGM
D0
W
R
D7
D5
W
R
COCO
$001E A/D STATUS AND CONTROL
$001F IRQ CONTROL AND STATUS
ADRC
ADON
CH3
CH0
0
W
R
IRQF
IRQPAF IRQPCF
IRQE
IRQPAE IRQPCE
W
IRQA
UNIMPLEMENTED
ONE TIME WRITE
Figure 2-4: MC68HC05V7 I/O Registers $0010-$001F
SECTION 2: MEMORY MAP
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READ
WRITE
ADDR
REGISTER
7
6
5
4
3
2
1
0
R
$0020 MDLC TX DATA REGISTER 0
$0021 MDLC TX DATA REGISTER 1
$0022 MDLC TX DATA REGISTER 2
$0023 MDLC TX DATA REGISTER 3
$0024 MDLC TX DATA REGISTER 4
$0025 MDLC TX DATA REGISTER 5
$0026 MDLC TX DATA REGISTER 6
$0027 MDLC TX DATA REGISTER 7
$0028 MDLC TX DATA REGISTER 8
$0029 MDLC TX DATA REGISTER 9
$002A MDLC TX DATA REGISTER 10
$002B PORT E DATA
W
R
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
D7
D6
D5
D4
D3
D2
D1
D0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
W
R
$002C PORT F DATA
PF3
PF2
PF1
PF0
W
R
$002D UNUSED
W
R
$002E PORT F DATA DIRECTION
$002F MISCELLANEOUS
DDRF3
DDRF2
DDRF1
DDRF0
W
R
IGNS
OCE
PDC
W
Figure 2-5: MC68HC05V7 I/O Registers $0020-$002F
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READ
WRITE
ADDR
REGISTER
7
6
5
4
3
2
1
0
R
$0030 PWM DATA
POL
PSA1
PSA0
D5
D4
D3
PSB3
D2
PSB2
D1
PSB1
D0
PSB0
W
R
$0031 PWM CONTROL
W
R
$0032 UNUSED
W
R
$0033 UNUSED
D6
D5
D4
D3
D2
D1
D0
W
R
D7
$0034 MDLC RX DATA REGISTER 0
$0035 MDLC RX DATA REGISTER 1
$0036 MDLC RX DATA REGISTER 2
$0037 MDLC RX DATA REGISTER 3
$0038 MDLC RX DATA REGISTER 4
$0039 MDLC RX DATA REGISTER 5
$003A MDLC RX DATA REGISTER 6
$003B MDLC RX DATA REGISTER 7
$003C MDLC RX DATA REGISTER 8
$003D MDLC RX DATA REGISTER 9
$003E MDLC RX DATA REGISTER 10
$003F RESERVED
W
R
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
UNIMPLEMENTED
Figure 2-6: MC68HC05V7 I/O Registers $0030-$003F
SECTION 2: MEMORY MAP
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MC68HC05V7 Specification Rev. 1.0
SECTION 3
EEPROM
The MC68HC05V7 contains EEPROM memory. This section describes the programming
mechanisms.
3.1
EEPROM PROGRAMMING REGISTER $1C
The contents and use of the programming register are discussed below.
$1C
-
CPEN
0
-
ER1
0
ER0
0
LATCH EERC EEPGM
RESET:
0
0
0
0
0
Figure 3-1: Programming Register
NOTE: Any reset including LVR will abort any write in progress when it is
asserted. Data written to the addressed byte will therefore be
indeterminate.
3.1.1
CPEN - Charge Pump Enable
When set, CPEN enables the charge pump which produces the internal programming
voltage. This bit should be set with the LATCH bit. The programming voltage will not be
available until EEPGM is set. The charge pump should be disabled when not in use. CPEN
is readable and writable and is cleared by reset.
3.1.2
ER1:ER0 - Erase Select Bits
ER1 and ER0 form a 2-bit field which is used to select one of three erase modes: byte,
block, or bulk. Table 3-1 shows the modes selected for each bit configuration. These bits
are readable and writable and are cleared by reset.
In byte erase mode, only the selected byte is erased. In block mode, a 32-byte block of
EEPROM is erased. The EEPROM memory space is divided into four 32-byte blocks
($0240-$025F, $0260-$027F, $0280-$029F, $02A0-$02BF), and doing a block erase to
any address within a block will erase the entire block. In bulk erase mode, the entire 128
byte EEPROM section is erased.
SECTION 3: EPROM and EEPROM
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Table 3-1: Erase Mode Select
ER1
ER0
MODE
0
0
1
0
1
0
No Erase
Byte Erase
Block Erase
1
1
Bulk Erase
3.1.3
LATCH
When set, LATCH configures the EEPROM address and data bus for programming. When
LATCH is set, writes to the EEPROM array cause the data bus and the address bus to be
latched. This bit is readable and writable, but reads from the array are inhibited if the
LATCH bit is set and a write to the EEPROM space has taken place. When clear, address
and data buses are configured for normal operation. Reset clears this bit.
3.1.4
When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU
clock. After setting the EERC bit, delay a time t
to allow the RC oscillator to stabilize.
EERC - EEPROM RC Oscillator Control
RCON
This bit is readable and writable and should be set by the user when the internal bus
frequency falls below 1.5 MHz. Reset clears this bit.
3.1.5
EEPGM - EEPROM Programming Power Enable
EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM
turns on the charge pump and enables the programming (or erasing) power to the
EEPROM array. When clear, this power is switched off. This will enable pulsing of the
programming voltage to be controlled internally. This bit can be read at any time, but can
only be written to if LATCH=1. If LATCH is not set, then EEPGM cannot be set. Reset clears
this bit.
3.1.6
To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write data to
the desired address, and then set EEPGM for a time t
PROGRAMMING/ERASING PROCEDURES
.
EEPGM
In general, all bits should be erased before being programmed. However, if write/erase
cycling is a concern, a procedure can be followed to minimize the cycling of each bit in each
EEPROM byte. The erased state is 1; therefore, if any bits within the byte need to be
changed from a 0 to a 1, the byte must be erased before programming. The decision
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SECTION 3: EPROM and EEPROM
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whether to erase a byte before programming is summarized in Table 3-2.
Table 3-2: EEPROM Write/Erase Cycle Reduction
EEPROM Data To Be
Programmed
EEPROM Data Before
Programming
Erase Before
Programming?
0
0
1
1
0
1
0
1
No
No
Yes
No
To erase a byte of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 0 and ER0 = 1, write to
the address to be erased, and set EEPGM for a time t
.
EBYT
To erase a block of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 1 and ER0 = 0, write to
any address in the block, and set EEPGM for a time t
.
EBLOCK
For a bulk erase, set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any address
in the array, and set EEPGM for a time t
.
EBULK
To terminate the programming or erase sequence, clear EEPGM, delay for a time t
to
FPV
allow the programming voltage to fall, and then clear LATCH and CPEN to free up the
buses. Following each erase or programming sequence, clear all programming control bits.
The following program is an example of the EEPROM programming sequence using the
timer to implement the required delay and assuming a 2.1 MHz bus frequency.
TSR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0013
$0018
$0019
$0016
$0017
6
$001C
6
4
3
2
1
0
TIMER STATUS REGISTER
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
TIMER OUTPUT COMPARE REGISTER (HIGH)
TIMER OUTPUT COMPARE REGISTER (LOW)
OCF BIT OF TSR
PROGRAM REGISTER
CHARGE PUMP ENABLE
ERASE SELECT 1
ERASE SELECT 0
TCNTH
TCNTL
TCMPH
TCMPL
OCF
PROG
CPEN
ER1
ER0
LATCH
EERC
EEPGM
LATCH BIT
RC/OSC SELECTOR
EE PROGRAM BIT
EESTART EQU
SUMPIN EQU
$0240
$FF
STARTING ADDRESS OF EEPROM
DUMMY DATA
ORG
$1800
START
EQU
*
BSET
BSR
EERC,PROG
DELAY
SELECT RC OSC
RC OSC STABILIZATION
SECTION 3: EPROM and EEPROM
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BSET
BSET
BCLR
BCLR
LDA
CPEN,PROG
LATCH,PROG
ER1,PROG
ER0,PROG
#SUMPIN
TURN ON CHARGE PUMP
ENABLE LATCH BIT
ENSURE PROGRAM (NOT ERASE)
ENSURE PROGRAM (NOT ERASE)
GET DATA
STA
EESTART
BSET
JSR
BCLR
JSR
BCLR
BCLR
LDA
EEPGM, PROG
DELAY
EEPGM,PROG
DELAY
LATCH,PROG
CPEN,PROG
#SUMPIN
ENABLE PROGRAMMING POWER
WAIT FOR PROGRAM TIME
CLEAR EEPGM
WAIT FOR PROG VOLTAGE TO FALL
CLEAR LATCH
DISABLE CHARGE PUMP
CMP
EESTART
VERIFY
BNE
OUT1
CLC
RTS
SEC
CLEAR CARRY BIT FOR NO ERROR
FLAG AN ERROR
OUT
OUT1
RTS
* THIS ROUTINE GIVES ABOUT A 10 MS DELAY FOR A 2.1Mhz BUS.
* THE SAME DELAY ROUTINE IS USED IN THIS EXAMPLE FOR SIMPLICITY,
* USING THE LONGEST DELAY TIME. USERS WILL WANT TO WRITE SHORTER
* DELAY ROUTINES FOR APPLICATIONS IN WHICH SPEED IS IMPORTANT.
DELAY
EQU
LDA
ADD
STA
LDA
STA
BRCLR
RTS
*
TCNTH
#$15
TCMPH
TCNTL
TCMPL
OCF,TSR,*
READ MS BYTE OF TIMER COUNTER
ADD OFFSET
STORE BACK IN O/P COMPARE MS BYTE
READ LS BYTE OF TCR
STORE INTO O/P COMPARE LS BYTE
WAIT FOR OCF FLAG TO OCCUR
3.2
OPERATION IN STOP AND WAIT
The RC oscillator for the EEPROM is automatically disabled when entering STOP mode.
The user may want to ensure that the RC oscillator is disabled before entering WAIT mode
to help conserve power.
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SECTION 3: EPROM and EEPROM
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SECTION 4
CPU CORE
The MC68HC05V7 has a 16K memory map. Therefore it uses only the lower 14 bits of the
address bus. In the following discussion the upper 2 bits of the address bus can be ignored.
Also, the STOP instruction may be selected to act as either the normal STOP instruction or
pull a reset by means of a mask option. All other instructions and registers behave as
described in this chapter.
4.1
REGISTERS
The MCU contains five registers that are hard-wired within the CPU and are not part of the
memory map. These five registers are shown in Figure 4-1 and are described in the
following paragraphs.
7
6
5
4
3
2
1
0
ACCUMULATOR
INDEX REGISTER
A
X
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
1
1
STACK POINTER
SP
PC
CC
0
0
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 4-1: MC68HC05 Programming Model
ACCUMULATOR (A)
4.1.1
The accumulator is a general purpose 8-bit register, as shown in Figure 4-1. The CPU uses
the accumulator to hold operands and results of arithmetic calculations or nonarithmetic
operations. The accumulator is unaffected by a reset of the device.
4.1.2
INDEX REGISTER (X)
The index register shown in Figure 4-1 is an 8-bit register that can perform two functions:
• Indexed addressing
• Temporary storage
SECTION 4: CPU CORE
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In indexed addressing with no offset, the index register contains the low byte of the operand
address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset,
the CPU finds the operand address by adding the index register contents to an 8-bit
immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand
address by adding the index register contents to a 16-bit immediate value
The index register can also serve as an auxiliary accumulator for temporary storage. The
index register is unaffected by a reset of the device.
4.1.3
STACK POINTER (SP)
The stack pointer shown in Figure 4-1 is a 16-bit register internally. In devices with memory
maps less than 64 Kbytes the unimplemented upper address lines are ignored. The stack
pointer contains the address of the next free location on the stack. During a reset or the
reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is
then decremented as data is pushed onto the stack and incremented as data is pulled from
the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011.
The six least significant register bits are appended to these ten fixed bits to produce an
address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64
($40) locations. If 64 locations are exceeded, the stack pointer wraps around and writes
over the previously stored information. A subroutine call occupies two locations on the
stack and an interrupt uses five locations.
4.1.4
PROGRAM COUNTER (PC)
The program counter shown in Figure 4-1 is a 16-bit register internally. In devices with
memory maps less than 64 Kbytes the unimplemented upper address lines are ignored.
The program counter contains the address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next sequential memory
location every time an instruction or operand is fetched. Jump, branch, and interrupt
operations load the program counter with an address other than that of the next sequential
location.
4.1.5
CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 4-1 is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be
individually tested by a program, and specific actions can be taken as a result of their state.
The condition code register should be thought of as having three additional upper bits that
are always ones. Only the interrupt mask is affected by a reset of the device. The following
paragraphs explain the functions of the lower five bits of the condition code register.
4.1.5.1
Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the
accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is
required for binary-coded decimal (BCD) arithmetic operations.
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4.1.5.2
Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts
are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt
mask is automatically set after the CPU registers are saved on the stack, but before the
interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the
interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt
mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the
interrupt mask to its state before the interrupt was encountered. After any reset, the
interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), STOP, or WAIT
instructions.
4.1.5.3
Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical operation, or
data manipulation was negative. (Bit 7 of the result was a logical one.)
The negative bit can also be used to check an often-tested flag by assigning the flag to bit
7 of a register or memory location. Loading the accumulator with the contents of that
register or location then sets or clears the negative bit according to the state of the flag.
4.1.5.4
Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical operation, data
manipulation, or data load operation was zero.
4.1.5.5
Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the
last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is
also set or cleared during bit test and branch instructions and during shifts and rotates. This
bit is not set by an INC or DEC instruction.
SECTION 4: CPU CORE
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SECTION 5
INTERRUPTS
The MCU can be interrupted seven different ways:
1. Nonmaskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. External Interrupt via IRQ on PA0-PA7, PC0-PC7
4. Internal 16-bit Timer Interrupt (TIMER)
5. Internal Serial Peripheral Interface Interrupt (SPI)
6. Internal MDLC Interrupt (MDLC)
7. Internal 8-bit Timer Interrupt
5.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not
cause the current instruction execution to be halted, but are considered pending until the
current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in Table 5-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $3FF2 thru $3FFF as
defined in Table 5-1.
Table 5-1: Vector Address for Interrupts and Reset
CPU
Interrupt
Flag
Name
Register
Interrupts
Vector Address
N/A
N/A
N/A
N/A
N/A
N/A
Reset
Software
External Interrupts **
16-bit Timer Interrupts
MDLC Interrupt
RESET
SWI
IRQ
TIMER
MDLC
SPI
$3FFE-$3FFF
$3FFC-$3FFD
$3FFA-$3FFB
$3FF8-$3FF9
$3FF6-$3FF7
$3FF4-$3FF5
$3FF2-$3FF3
TSR
OCF,ICF,TOF
TXMS,RXMS
SPIF
MSR
SPSR
CTCSR
SPI Interrupt
8 bit Timer Interrupts
TOFE,RTIE
TIMER,RTI
** External interrupts include IRQ, PORTA and PORTC sources
SECTION 5: INTERRUPTS
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The M68HC05 CPU does not support interruptible instructions, therefore, the maximum
latency to the first instruction of the interrupt service routine must include the longest
instruction execution time plus stacking overhead.
Latency = (Longest instruction execution time + 10) x t
secs
CYC
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume at the next instruction that was to be executed when the
interrupt took place. Figure 5-1 shows the sequence of events that occur during interrupt
processing.
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FROM
RESET
I-BIT
IN CCR
SET?
Y
N
IRQ
EXTERNAL
INTERRUPT
Y
CLEAR IRQ
REQUEST
LATCH
N
Y
Y
INTERNAL
16 BIT TIMER
INTERRUPT
N
INTERNAL
MDLC
INTERRUPT
N
Y
Y
INTERNAL
SPI
INTERRUPT
N
INTERNAL
8 BIT TIMER
INTERRUPT
STACK
PC, X, A, CCR
N
FETCH NEXT
INSTRUCTION
SET I BIT IN
CC REGISTER
LOAD PC FROM
APPROPRIATE
VECTOR
Y
SWI
INSTRUCTION
?
N
Y
RTI
INSTRUCTION
?
N
RESTORE REGISTERS
FROM STACK:
EXECUTE
INSTRUCTION
CCR, A, X, PC
Figure 5-1: Interrupt Processing Flowchart
SECTION 5: INTERRUPTS
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5.2
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a
similar manner, as shown in Figure 5-1. A low level input on the RESET pin or internally
generated RST signal causes the program to vector to its starting address which is
specified by the contents of memory locations $3FFE and $3FFF. The I-bit in the condition
code register is also set. The MCU is configured to a known state during this type of reset
as described in SECTION 6 RESETS.
5.3
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is executed
regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the
SWI instruction executes after interrupts that were pending before the SWI was fetched, or
before interrupts generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and $3FFD.
5.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is
set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables
the hardware interrupts. There are two types of hardware interrupts which are explained in
the following sections.
5.5
EXTERNAL INTERRUPT (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ
function is shown in Figure 5-2.
NOTE: The BIH and BIL instructions will only apply to the level on the IRQ pin
itself, and not to the output of the logic OR function with the Port A and
Port C IRQ interrupts. The state of the individual Port A and Port C pins
can be checked by reading the appropriate Port A and Port C pins as
inputs.
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to BIH & BIL
instruction
sensing
IRQ Pin
V
D
IRQ
LATCH
IRQF
IRQ Vector Fetch
R
RST
IRQA
LEVEL
(MASK option)
IRQE
PA0
V
D
DDRA0
DDRA7
IRQPAF
IRQPA
LATCH
R
PA7
to IRQ
processing
in CPU
IRQPAE
PC0
V
D
DDRC0
IRQPCF
IRQPC
LATCH
DDRC7
PC7
R
IRQPCE
Figure 5-2: IRQ Function Block Diagram
The IRQ pin is one source of an external interrupt. All Port A pins (PA0 thru PA7) and/or all
Port C pins (PC0 thru PC7) act as other external interrupt sources. These sources each
have their own interrupt latch but are all combined into a single external interrupt request.
The Port A and Port C interrupt sources are negative (falling) edge sensitive only. Note
that all Port A pins and all Port C pins are ANDed together, if configured as an input, to form
the negative edge signal which sets the corresponding flag bits. A high to low transition on
any Port A or Port C pin configured as an input will therefore set the respective flag bit. If a
Port A or Port C pin is an input and is not used as a switch input in the system, it must
remain high to prevent spurious interrupts from occurring. Refer to 9.1.3 PORT A/C I/O PIN
INTERRUPTS for more detail on Port A/Port C interrupts.The IRQ pin interrupt source may
be selected to be either edge sensitive or edge and level sensitive through a mask option
or an MOR bit. If the EDGE sensitive interrupt option is selected for the IRQ pin, only the
SECTION 5: INTERRUPTS
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IRQ latch output can activate an IRQF flag which creates an interrupt request to the CPU
to generate the external interrupt sequence.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to the following cases:
• Falling edge on the IRQ pin.
• Falling edge on any Port A or Port C pin with IRQ enabled.
If the LEVEL option selected, the active low state of the IRQ pin can also activate an IRQF
flag, which creates an IRQ request to the CPU to generate the IRQ interrupt sequence.
When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to the
following cases:
• Low level on the IRQ pin.
• Falling edge on the IRQ pin.
• Falling edge on any Port A or Port C pin with IRQ enabled.
The IRQE enable bit controls whether an active IRQF flag (IRQ pin interrupt) can generate
an IRQ interrupt sequence. The IRQPAE enable bit controls whether an active IRQPAF flag
(Port A interrupt) can generate an IRQ interrupt sequence. The IRQPCE enable bit controls
whether an active IRQPCF flag (Port C interrupt) can generate an IRQ interrupt sequence.
The IRQ interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $3FFA and $3FFB.
The IRQF latch is automatically cleared by entering the interrupt service routine to maintain
compatibility with existing M6805 interrupt servicing protocol. To allow the user to identify
the source of the interrupt, the port interrupt flags (IRQPAF and IRQPCF) are not cleared
automatically. These flags must be cleared within the interrupt handler prior to exit in order
to prevent repeated re-entry. This is achieved by writing a logic one to the IRQA (IRQ
acknowledge) bit, which will clear all pending IRQ interrupts (including a pending IRQ pin
interrupt).
The interrupt request flags (IRQPAF and IRQPCF) are read only and cannot be cleared by
writing to them. The acknowledge flag always reads as a logic 0. Together, these features
permit the safe use of read-modify-write instructions (for example, BSET, BCLR) on the
ICSR.
NOTE: Although read modify write instruction use is allowable on the ICSR, shift
operations should be avoided due to the possibility of inadvertently setting
the IRQA.
5.5.1
IRQ CONTROL/STATUS REGISTER (ICSR) $1F
The IRQ interrupt function is controlled by the ICSR located at $001F. All unused bits in the
ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset.
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.
7
IRQE
1
6
IRQPAE
0
5
IRQPCE
0
4
0
3
2
1
0
0
R
IRQF
IRQPAF
IRQPCF
ICSR
$001F
W
IRQA
reset
0
0
0
0
0
Figure 5-3: IRQ Status & Control Register
IRQA - IRQ Interrupt Acknowledge
5.5.1.1
The IRQA acknowledge bit clears an IRQ interrupt by clearing the IRQ, IRQPA and IRQPC
latches. This is achieved by writing a logic one to the IRQA acknowledge bit. Writing a logic
zero to the IRQA acknowledge bit will have no effect on the any of the IRQ latches. If either
the IRQ, IRQPA or IRQPC latch is not cleared within the IRQ service routine the CPU will
re-enter the IRQ interrupt sequence continuously until the IRQ latches are all cleared. The
IRQA is useful for cancelling unwanted or spurious interrupts which may have occurred
while servicing the initial IRQ interrupt. The IRQA acknowledge bit will always read as a
logic zero. The IRQA function is activated by reset.
NOTE: The IRQ latch is cleared automatically during the IRQ vector fetch. The
IRQPA and IRQPC latches are not cleared automatically (to permit
interrupt source differentiation) and must be cleared from within the IRQ
service routine.
5.5.1.2
IRQPCF - Port C IRQ Interrupt Request
The IRQPCF flag bit indicates that a Port C IRQ request is pending. Writing to the IRQPCF
flag bit will have no effect on it. The IRQPCF flag bit must be cleared by writing a logic one
to the IRQA acknowledge bit. In this way an additional IRQPCF flag bit that is set while in
the service routine can be ignored by clearing the IRQPCF flag bit before exiting the service
routine. If the additional IRQPCF flag bit is not cleared in the IRQ service routine and the
IRQPCE enable bit remains set, the CPU will re-enter the IRQ interrupt sequence
continuously until either the IRQPCF flag bit or the IRQPCE enable bit is clear. This bit is
operational regardless of the state of the IRQPCE bit. The IRQPCF bit is cleared by reset.
5.5.1.3
IRQPAF - Port A IRQ Interrupt Request
The IRQPAF flag bit indicates that a Port A IRQ request is pending. Writing to the IRQPAF
flag bit will have no effect on it. The IRQPAF flag bit must be cleared by writing a logic one
to the IRQA acknowledge bit. In this way an additional IRQPAF flag bit that is set while in
the service routine can be ignored by clearing the IRQPAF flag bit before exiting the service
routine. If the additional IRQPAF flag bit is not cleared in the IRQ service routine and the
IRQPAE enable bit remains set, the CPU will re-enter the IRQ interrupt sequence
continuously until either the IRQPAF flag bit or the IRQPAE enable bit is clear. This bit is
operational regardless of the state of the IRQPAE bit. The IRQPAF bit is cleared by reset.
SECTION 5: INTERRUPTS
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5.5.1.4 IRQF - IRQ Interrupt Request
The IRQF flag bit indicates that an IRQ request is pending. Writing to the IRQF flag bit will
have no effect on it. The IRQF flag bit is cleared when the IRQ vector is fetched prior to the
service routine being entered. The IRQF flag bit can also be cleared by writing a logic one
to the IRQA acknowledge bit to clear the IRQ latch. In this way any additional IRQF flag bit
that is set while in the service routine can be ignored by clearing the IRQF flag bit before
exiting the service routine. If the additional IRQF flag bit is not cleared in the IRQ service
routine and the IRQE enable bit remains set, the CPU will re-enter the IRQ interrupt
sequence continuously until either the IRQF flag bit or the IRQE enable bit is clear. The IRQ
latch is cleared by reset. This flag can be set only when the IRQE enable is set.
5.5.1.5
IRQPCE - Port C IRQ Interrupt Enable
The IRQPCE bit controls whether the IRQPCF flag bit can or cannot initiate an IRQ interrupt
sequence. If the IRQPCE enable bit is set the IRQPCF flag bit can generate an interrupt
sequence. If the IRQPCE enable bit is cleared the IRQPCF flag bit cannot generate an
interrupt sequence. Reset clears the IRQPCE enable bit, thereby disabling Port C IRQ
interrupts. In addition, reset also sets the I-bit, which masks all interrupt sources. Execution
of the STOP or WAIT instructions does not effect the IRQPCE bit.
5.5.1.6
IRQPAE - Port A IRQ Interrupt Enable
The IRQPAE bit controls whether the IRQPAF flag bit can or cannot initiate an IRQ interrupt
sequence. If the IRQPAE enable bit is set the IRQPAF flag bit can generate an interrupt
sequence. If the IRQPAE enable bit is cleared the IRQPAF flag bit cannot generate an
interrupt sequence. Reset clears the IRQPAE enable bit, thereby disabling Port A IRQ
interrupts. In addition, reset also sets the I-bit, which masks all interrupt sources. Execution
of the STOP or WAIT instructions does not effect the IRQPAE bit.
NOTE: The IRQPAE and IRQPCE mask bits must be set prior to entering STOP
or WAIT modes if Port IRQ interrupts are to be enabled.
5.5.1.7
IRQE - IRQ Interrupt Enable
The IRQE bit controls whether the IRQF flag bit can or cannot initiate an IRQ interrupt
sequence. If the IRQE enable bit is set the IRQF flag bit can generate an interrupt
sequence. If the IRQE enable bit is cleared the IRQF flag bit cannot bet set and therefor
cannot generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling
IRQ interrupts once the I-bit is cleared. Execution of the STOP or WAIT instructions causes
the IRQE bit to be set in order to allow the external IRQ to exit these modes. In addition,
reset also sets the I-bit, which masks all interrupt sources.
5.5.2
External Interrupt Timing
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and
external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched
immediately following the falling edge of the IRQ source. It is then synchronized internally
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and serviced as specified by the contents of $3FFA and $3FFB.The IRQ timing diagram is
shown in Figure 5-4.
IRQ
tILIH
tILIL
IRQ1 (Port)
tILIH
.
.
.
IRQn (Port)
IRQ
(MCU)
Figure 5-4: External Interrupts Timing Diagram
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger is
available as a mask option for the IRQ pin only.
5.6
16 BIT TIMER INTERRUPT
There are three different timer interrupt flags that cause a timer interrupt whenever they are
set and enabled. The interrupt flags are in the Timer Status Register (TSR), and the enable
bits are in the Timer Control Register (TCR). Any of these interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
location $3FF8 and $3FF9.
5.7
MDLC INTERRUPT
The MDLC Transmit Message Successful and Receive Message Successful interrupts are
respectively generated by the TXMS and RXMS bits of the MDLC Status Register (MSR).
In addition a wake-up from STOP or WAIT mode can also generate an interrupt from the
MDLC. The MDLC Interrupt Enable (IE) bit is located in the MDLC Control Register (MCR).
Provided the IE bit is set (and the CCR I bit is clear), all interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
location $3FF6 and $3FF7.
5.8
SPI INTERRUPT
There are two different SPI interrupt flags that cause an SPI interrupt whenever they are
set and enabled. The interrupt flags are in the SPI Status Register (SPSR), and the enable
bits are in the SPI Control Register (SPCR). Either of these interrupts will vector to the
SECTION 5: INTERRUPTS
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same interrupt service routine, located at the address specified by the contents of memory
locations $3FF4 and $3FF5.
5.9
8-BIT TIMER INTERRUPT
This timer can create two types of interrupts. A timer overflow interrupt will occur whenever
the 8 bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real time interrupt
will occur whenever the programmed time elapses and the enable bit RTIE is set. See
SECTION 12 CORE TIMER. This interrupt will vector to the interrupt service routine located
at the address specified by the contents of memory locations $3FF2 and $3FF3.
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SECTION 6
RESETS
The MCU can be reset from six sources: one external input and five internal restart
conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 6-1. All the
internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure
6-2 for reset timing detail.
To IRQ
logic
IRQ/V
TST
D
Mode
Select
LATCH
RESET
R
(pulse width = 3 x E-clk)
CLOCKED
ONE-SHOT
PH2
OSC
Data
Address
COP Watchdog
(COPR)
Low-Voltage
Reset (LVR)
CPU
RST
V
V
DD
DD
S
D
LATCH
To other
peripherals
Power-On Reset
(POR)
PH2
Illegal Address
(ILLADDR)
Address
Disabled STOP
instruction
STOPEN
Figure 6-1: Reset Block Diagram
6.1
EXTERNAL RESET (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a Schmitt
trigger input gate to provide an upper and lower threshold voltage separated by a minimum
amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below
the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the RST signal and reset the CPU and
peripherals. Termination of the external RESET input or the internal COP Watchdog reset
are the only reset sources that can alter the operating mode of the MCU.
NOTE: Activation of the RST signal is generally referred to as reset of the device,
unless otherwise specified.
SECTION 6: RESETS
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The RESET pin can also act as an open drain output. It will be pulled to a low state by an
internal pulldown that is activated by any reset source. This RESET pulldown device will
only be asserted for 3-4 cycles of the internal clock, PH2 (PH2 period = E clock period) or
as long as an internal reset source is asserted. When the external RESET pin is asserted,
the pulldown device will be turned on for only the 3-4 internal clock cycles.
6.2
INTERNAL RESETS
The five internally generated resets are the initial power-on reset function, the COP
Watchdog Timer reset, the illegal address detector, the low-voltage reset, and the disabled
STOP instruction. Termination of the external RESET input or the internal COP Watchdog
Timer are the only reset sources that can alter the operating mode of the MCU. The other
internal resets will not have any effect on the mode of operation when their reset state ends.
All internal resets will also assert (pull to logic zero) the external RESET pin for the duration
of the reset or 3-4 internal clock cycles, whichever is longer.
6.2.1
POWER-ON RESET (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The
POR is strictly for power turn-on conditions and is not able to detect a drop in the power
supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal
processor bus clock cycles (PH2) after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function
is active at the end of this 4064 cycle delay, the RST signal will remain in the reset condition
until the other reset condition(s) end.
POR will activate the RESET pin pulldown device connected to the pin. V
must drop
DD
below V
in order for the internal POR circuit to detect the next rise of V .
DD
POR
6.2.2
OPERATION IN STOP AND WAIT
If enabled, the LVR supply voltage sense option is active during STOP and WAIT. Any reset
source can bring the MCU out of STOP or WAIT modes.
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Figure 6-2: RESET and POR Timing Diagram
SECTION 6: RESETS
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6.2.3 COMPUTER OPERATING PROPERLY RESET (COPR)
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within
a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-
out, an internal reset is generated to reset the MCU. Regardless of an internal or external
RESET, the MCU comes out of a COP reset according to the standard rules of mode
selection.
The COP reset function is enabled or disabled by a mask option and is verified during
production testing.
The COP Watchdog reset will activate the internal pulldown device connected to the
RESET pin.
6.2.3.1
RESETTING THE COP
Preventing a COP reset is done by writing a “0” to the COPF bit. This action will reset the
counter and begin the time-out period again. The COPF bit is bit 0 of address $3FF0. A
read of address $3FF0 will return user data programmed at that location.
6.2.3.2
COP DURING WAIT MODE
The COP will continue to operate normally during WAIT mode. The software should pull the
device out of WAIT mode periodically and reset the COP by writing to the COPF bit to
prevent a COP reset.
6.2.3.3
COP DURING STOP MODE
When the STOP enable mask option is selected, STOP mode disables the oscillator circuit
and thereby turns the clock off for the entire device. The COP counter will be reset when
STOP mode is entered. If a reset is used to exit STOP mode, the COP counter will be held
in reset during the 4064 cycles of start up delay. If any operable interrupt is used to exit
STOP mode, the COP counter will not be reset during the 4064 cycle start up delay and
will have that many cycles already counted when control is returned to the program.
6.2.3.4
COP WATCHDOG TIMER CONSIDERATIONS
The COP Watchdog Timer is active in all modes of operation if enabled by a mask option.
If the COP Watchdog Timer is selected by a mask option, any execution of the STOP
instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the
oscillator to halt and prevent the COP Watchdog Timer from timing out. Therefore, it is
recommended that the STOP instruction should be disabled if the COP Watchdog Timer
is enabled.
If the COP Watchdog Timer is selected by a mask option, the COP will reset the MCU when
it times out. Therefore, it is recommended that the COP Watchdog should be disabled for
a system that must have intentional uses of the WAIT Mode for periods longer than the
COP time-out period.
The recommended interactions and considerations for the COP Watchdog Timer, STOP
instruction, and WAIT instruction are summarized in Table 6-1.
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Table 6-1: COP Watchdog Timer Recommendations
IF the following conditions exist:
STOP Instruction
THEN the
COP Watchdog Timer
should be as follows:
WAIT Time
converted to reset
WAIT Time Less than
Enable or disable COP
by mask option
COP Time-Out
converted to reset
Acts as STOP
WAIT Time More than
Disable COP
by mask option
COP Time-Out
any length
WAIT Time
Disable COP
by mask option
6.2.3.5
COP REGISTER
The COP register is shared with the MSB of an unimplemented User Interrupt Vector as
shown in Figure 6-3. Reading this location will return whatever user data has been
programmed at this location. Writing a “0” to the COPR bit in this location will clear the COP
watchdog timer.
READ
WRITE
REGISTER
ADDR
$3FF0
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
R
x
UNIMPLEMENTED VECTOR &
COP WATCHDOG TIMER
W
COPR
UNIMPLEMENTED
Figure 6-3: COP Watchdog Timer Location
LOW-VOLTAGE RESET (LVR)
The internal low voltage (LVR) reset is generated when V falls below the LVR threshold
6.2.4
DD
V
and will be released following a POR delay starting when V rises above V
.
LVRI
DD
LVRR
The LVR threshold is tested to be above the minimum operating voltage of the
microcontroller and is intended to ensure that the CPU will be held in reset when the V
BATT
supply voltage is below reasonable operating limits. However, it should be noted that the
LVR monitors V not V . A mask option is provided to disable the LVR when the
DD
BATT
device is expected to normally operate at low voltages. Note that the V rise and fall slew
DD
rates (S
and S
) must be within the specification for proper LVR operation. If the
VDDR
VDDF
specification is not met, the circuit will operate properly following a delay of V /Slew rate.
DD
The LVR will generate the RST signal that will reset the CPU and other peripherals. As it is
not possible to determine the level of the internal V at the point V
recovers (and POR
DD
BATT
is not intended to detect a loss of V ), an LVR will always recover using a POR delay. The
DD
low voltage reset will activate the internal pulldown device connected to the RESET pin.
SECTION 6: RESETS
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If any other reset function is active at the end of the LVR reset signal, the RST signal will
remain in the reset condition until the other reset condition(s) end.
6.2.5
ILLEGAL ADDRESS
An illegal address reset is generated when the CPU attempts to fetch an instruction from
either unimplemented address space ($01C0 to $023F and $02C0 to $17FF) or I/O
address space ($0000 to $003F).
The illegal address reset will activate the internal pulldown device connected to the RESET
pin.
6.2.6
DISABLED STOP INSTRUCTION
When the mask option is selected to disable the STOP instruction, execution of a STOP
instruction results in an internal reset. This activates the internal pulldown device
connected to the RESET pin.
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SECTION 7
POWER SUPPLY AND REGULATION
The MC68HC05V7 contains a low-power CMOS on-chip fixed voltage regulator to provide
internal power to the MCU from an external DC source. The MCU features separate analog
and digital power and ground pins to help decrease common-mode noise contamination of
the analog subsystems. The supply pins are also grouped in adjacent pairs to permit
optimal decoupling and to minimize radiated RF emissions.
7.1
INTERNAL POWER SUPPLY
The on-chip voltage regulation and power supply control circuitry is comprised of four
elements: the primary regulator, the secondary regulator, the power mode control, and the
LVR circuitry. The primary internal regulator can be disabled through register control bits.
When it is desired to use an external voltage regulator, regulated power must be provided
to both sets of V /VSS pins. When the primary regulator is disabled, the regulator input
DD
pin (V
) is still used to power the MDLC’s physical interface.
BATT
7.1.1
PRIMARY 5V REGULATOR
The primary 5V regulator accepts a regulated input supply and provides a regulated 5V
supply to all the digital sections of the device with the exception of the V and power
IGN
supply control logic. The output of this regulator is also connected to the V
pins to allow
DD
for decoupling of the digital supply pins (V ), to supply a decoupled and/or filtered supply
DD
to the analog supply pin (V
) and to provide an external power source for off chip usage.
CCA
The regulator requires an external 10 uF capacitor for stability.
See Figure 7-6 : MC68HC05V7 On-chip Power Supply Configuration for the most
suitable supply pin and external capacitor connections.
The primary regulator can be disabled through software by clearing the PDC bit of the
MISCELLANEOUS register (see Figure 7-1). Once disabled, the regulator can only be
enabled by a rising edge on the V
or BUS (if mask option enabled) pins. When disabled,
IGN
the primary regulator output will be connected to V if the V
mask option has been
SS
DDC
selected. This prevents unintentional device operation using current sourced through
external pullup components.
Any loss of V
sufficient to trigger an LVR will cause the device to be reset. The device
BATT
will remain in the reset state for the duration of the LVR condition or until the internal V
DD
drops below the functional level of the device, at which point reset no longer has meaning.
If the drop in V that triggers an LVR is transient, the internal RST will be asserted for
BATT
a minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay).
7.1.2 SECONDARY REGULATOR
The secondary regulator provides an independent supply to the small amount of power
supply control logic required to provide some of the power moding functions. The
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secondary regulator is always enabled (regardless of the mask option selection) but
consumes significantly less power than the primary regulator. The secondary regulator will
provide sufficient voltage to the control logic provided V
remains above the minimum
BATT
voltage.
7.2
MISCELLANEOUS REGISTER
The software power supply management functions are performed through the
MISCELLANEOUS register located at $002F. Although the OCE bit of the
MISCELLANEOUS register is unrelated to the power supply, it will be described here.
READ
WRITE
REGISTER
ADDR
$002F
7
6
5
0
4
0
3
0
2
0
1
0
0
IGNS
R
MISCELLANEOUS REGISTER
OCE
PDC
W
reset
-
0
-
-
-
-
-
-
UNIMPLEMENTED
Figure 7-1: Miscellaneous Register
IGNS - Ignition status bit
This is a read only status bit which indicates the state of the V
7.2.1
pin.
IGN
0 - The V
1 - The V
pin is less than the V level for this pin.
IL
IGN
IGN
pin is greater than the V level for this pin.
IH
WARNING: There is not hysteresis or hardware debounce on the V
pin and hence, in
IGN
the state of this bit. This bit cannot be read unless the Regulator option is enabled.
See 17.3 DC ELECTRICAL CHARACTERISTICS for V and V levels.
IH
IL
7.2.2
OCE - Output compare enable
This bit controls the function of the PB6 pin.
0 - PB6 functions as a normal I/O pin.
1 - PB6 becomes the TCMP output pin for the 16-bit timer.
See SECTION 11 16-BIT TIMER for a description of the TCMP function.
Reset clears this bit.
7.2.3
PDC - Power Down Control
This bit controls the internal primary voltage regulator.
0 - Disables the internal primary voltage regulator.
1 - Enables the internal primary voltage regulator.
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This bit has no affect unless the regulator option is set. This bit is not affected by reset and
must be initialized by software.
7.3
POWER MODING
A flow diagram depicting all conditions that the MCU could enter is shown in Figure 7-2.
The chip can be operated in one of three distinct power modes. The first mode is "Power
off". In this mode, the chip is not being powered from any source. The V
pin voltage is
BATT
below that required by the regulator circuit to provide an output voltage that is within
regulation limits.
The second mode is "Standby power". In this mode, the V
voltage is above the
BATT
required minimum, but the user has not turned the primary regulator on. The secondary
regulator and the power mode logic are powered up. Standby mode can be exited by either
reducing the V
voltage or by turning the primary regulator on.
BATT
The third mode is "Power up" mode. In this mode, the CPU and peripherals can perform
their normal processing tasks. The only way to exit from this mode is to lose regulator
output power. Losing regulator output power can happen in one of three ways: 1) the V
BATT
voltage can fall below the required minimum level causing V to fall below minimum, 2)
DD
software can turn the primary regulator off, and 3) some sort of fault on the external V
DD
pin. In any case, the LVR reset will be asserted to protect the system as the V voltage is
DD
falling.
Transitioning between these states is referred to as power moding.
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Power Off
Mode
no
V
>min
yes
BATT
Standby Power
Mode
no
V
IGN
or
BUS
yes
Primary Reg.
Enabled
POR Delay
Power up
Mode
LVR
(chip reset)
Steady State
Condition
no
V >min
DD
yes
Decision
yes
Primary Reg.
Disabled
no
pdc=0
Transition
Figure 7-2: MC68HC05V7 Power Moding Flow Diagram
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7.4
REGULATOR CONTROL LOGIC
The ignition state monitor pin, V , or the MDLC BUS pin (provided the MDLCPU mask
IGN
option is selected) allows the user to wake-up the primary power supply and subsequently
the MCU. A positive transition applied to either pin will enable the primary regulator. The
state of the V
pin can be determined by reading the IGNS bit of the MISCELLANEOUS
IGN
register. The primary regulator can be disabled by clearing the PDC bit in the
MISCELLANEOUS register. The BUS or V pin need not be low to write the PDC bit.
IGN
Once the regulator has been disabled, a rising edge on V
regulator.
or BUS will re-enable the
IGN
To ensure the validity of the PDC bit during a V transition, the PDC bit is always copied
DD
into a latch powered by the secondary regulator. The bit is copied during a write to the
MISCELLANEOUS register. When the regulator is powered up by a rising edge of BUS or
V
, the latch that contains the copy of the PDC bit will be initialized to a 1 and may have
IGN
a different value than the PDC bit itself. Software should always initialize the PDC bit to a
1. The latch will be set on the rising edge of V or BUS. This will give the primary
IGN
regulator, CPU, and software ample time to start up and initialize the PDC bit to a 1. At this
point, the MCU will transition to the Power Up Mode. (See Figure 7-2.)
In order to ensure that the primary regulator starts up when V
voltage is applied to the
BATT
MCU, a low to high transition should be provided on the V
minimum level, shown in Figure 7-3.
pin once V
reaches
IGN
BATT
Voltage
V
>min
BATT
V
BATT
Min
BATT
V
IGN
V
V
<= 0.4*V
IGN
BATT
time
Figure 7-3: Regulator Startup
NOTE: Once enabled, the regulator can only be disabled through software.
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NOTE: If the LVR option is enabled, reset will be asserted when V drops to the
DD
appropriate level.
NOTE: Before the PDC bit is written to a 0, the state of the IGNS bit should be
debounced in software. This will ensure that the primary regulator does
not power up with any bounce that may be present on Vign.
7.4.1
MASK OPTIONS
The regulator has three mask options associated with it. The first one is the MDLCPU
option. If this option is enabled, a rising edge on the MDLC BUS pin or the V pin can
IGN
bring the primary regulator out of the Standby power mode. If this option is not enabled,
only the V pin will bring the primary regulator out of the Standby power mode.
IGN
The second mask option is the V
option. This option, if enabled, will enable an active
DDC
pulldown device, connected between V and V , to turn on when the primary regulator
DD
SS
is disabled. This option should not be selected if an external voltage regulator is being used.
The third mask option is the regulator enable option. If it is not desired to use the on-board
voltage regulator, this option should not be selected. In this case the secondary regulator
will still remain active in order to properly keep the primary regulator turned off. While the
regulator is not enabled the MDLCPU option will remain operational but will serve no
purpose. The V
option and the MISCELLANEOUS register will continue to operate
DDC
normally. The V
function (V to V clamping device) uses the PDC bit to determine
DD SS
DDC
when to turn the clamping device on. If this option is enabled and the PDC bit is written to
a "0", the clamping device will turn on. It will not turn off until a rising edge is detected on
V
or a rising edge on the BUS pin is detected provided the MDLCPU option is selected.
IGN
If the configuration shown in Figure 7-4 is used with the regulator enable option selected,
the MDLCPU and V options may be selected. In addition, software must write a ’1’ to
DDC
the PDC bit in the miscellaneous register to initialize it after power-up. This prevents read-
modify-write instructions to the MISCELLANEOUS register from accidentally clearing the
PDC bit.
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V
BATT
705V8
V
BATT
External
+5 Volts
V
Regulator
DD
0.1µ
MCU
V
V
DD
0.1µ
0.1µ
CCA
V
IGN
V ,V
SS SS
V
V
SSA1
SSA2
Figure 7-4: Using the 68HC05V7 with an External Regulator
If the regulator enable option is not selected, the MDLCPU option and the PDC bit have no
affect. The V
option will remain available.
DDC
Figure 7-5 is a block diagram of the regulator control circuit. It illustrates how the
MISCELLANEOUS register bits, V , BUS and the Mask options interact in the power
IGN
moding scheme.
SECTION 7: POWER SUPPLY AND REGULATION
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V
V
BATT
Secondary
Regulator
(VEE)
Primary
Regulator
MDLC PU
Mask Option
DDC
Mask Option
enable
V
DD
V
EE
latch
D Q
latch
D Q
S
R
Q
BUS
V
EE
V
Q
BATT
latch
D
C
V
IGN
Q
R
latch
D
Q
s
IGNS
...
Misc. Reg.
PDC
Figure 7-5: Power Moding Block Diagram
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7.5
POWER SUPPLY CONFIGURATION
The recommended decoupling and interconnection of the various power supply pins is shown in
Figure 7-6. Note that this diagram does not reflect actual pin location or order.
V
BATT
V
Supply
IGN
V
V
IGN
IGN
Internal (digital)
and V
Logic
R*
C*
Ignition
V
DD
CC
Secondary
Regulator
ENABLE
Primary
5v regulator
>= Min V
V
BATT
BATT
V
V
DD
DD
10 uF
0.1uF
0.1uF
Required for
Regulator
stability
V
V
SS
SS
V
0.1uF
SSA1
A/D Converter
MDLC Analog
EPROM
V
CCA
0.1uF
Single Point
Ground
V
SSA2
* RC values should be chosen to provide a V
voltage of <= 0.4*V
once V
IGN
BATT BATT
reaches minimum level.
Note: The 10 uF capacitor should be placed on the V pin closest to the V
pin.
DD
IGN
Figure 7-6: MC68HC05V7 On-chip Power Supply Configuration
7.5.1
DECOUPLING RECOMMENDATIONS
To provide effective decoupling and to reduce radiated RF emissions, the small decoupling
capacitors must be located as close to the supply pins as possible. The self-inductance of these
capacitors and the parasitic inductance and capacitance of the interconnecting traces
determines the self-resonant frequency of the decoupling network. Too low a frequency will
reduce decoupling effectiveness and could increase radiated RF emissions from the system. A
low value capacitor (470 pF to 0.01 uF) placed in parallel with the other capacitors will improve
the bandwidth and effectiveness of the network.
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PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PE7/AN
PE6/AN
PE5/AN
PE4/AN
PD7/AN
PD6/AN
PD5/AN
PD4/AN
PD3/AN
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PF3/MISO
PF2/MOSI
PF1/SCLK
PF0/SS
PB0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Digital Logic
Blocks
PB1
PB2
PB3
PB4
PB5
PB6/TCMP
PB7/TCAP
DLC
V
SSA2
A/D
Regulator
LOAD
BUS
R
V
PP
N.C.
R ~ 40 ohns
68-pin PLCC package shown
Figure 7-7: HC705V8 Internal Power Routing
1) V to V
(pins 30 & 31): On-chip regulator output decoupling. As with any reg-
DD
SSD
ulator, the output must be adequately decoupled to maintain stability of the regulator.
Decouple with at least 10 uF tantalum or aluminum electrolytic bulk in parallel with 0.1uF
ceramic or polystyrene capacitor for high frequency (HF) stability. Locate both capacitors
as close as possible to the V and V
pins, ensuring the HF capacitor is closest. The
DD
SSD
two V
pins should be externally connected together.
SSD
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The effect of not connecting the two V
pins together is under evaluation and it is recom-
DD
mended that they be connected at this time.
2) V to V (pins 3 & 4): MCU internal digital power decoupling. These pins are
DD
SSD
connected to the on-chip regulator output via a small resistance. Decouple with a 0.1uF
ceramic or polystyrene capacitator. If the self-resonance frequency of the decoupling cir-
cuit (assume 4nH per bond wire) is too low, add a 0.01uF or smaller capacitor in parallel to
increase the bandwidth of the decoupling network. Ensure the smaller capacitor is located
closest to the V and V
pins.
DD
SSD
3) V
to V
and V
: Analog subsystem power supply pins. These pins are
CCA
SSA1
SSA2
internally isolated from the digital V and V supplies. The V pin provides a ground
SSA1
DD
SS
return for the A/D subsystem. The V
pin provides a ground return for the DLC sub-
SSA2
system. The analog supply pins should be appropriately filtered to prevent any external
noise effecting the analog subsystems. The V and V pins should be brought
SSA1
SSA2
together with the digital ground at a single point which has a low (HF) impedance to
ground to prevent common mode noise problems. If this is not practical, then the V
SSA1
and V
printed circuit board (PCB) traces should be routed in such a manner that digi-
SSA2
tal ground return current is impeded from passing through the analog input ground refer-
ence as shown in the single sided PCB example below.
Poor Analog Grounding
V7
ANx
Shielded cable,
Twisted pair, etc.
V
SSA VSSD
AIN
V7
GND
ANx
VSSA
VSSD
Shielded cable, Twisted pair, etc.
AIN
AGND
Better Analog Grounding
GND
To System GND
SECTION 7: POWER SUPPLY AND REGULATION
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SECTION 8
LOW-POWER MODES
The MC68HC05V7 is capable of running in one of several low-power operational modes.
The WAIT and STOP instructions provide two modes that reduce the power required for
the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and
WAIT instructions are not normally used if the COP Watchdog Timer is enabled. A mask
option is provided to convert the STOP instruction to an internal reset. The flow of the STOP
and WAIT modes is shown in Figure 8-2.
8.1
STOP INSTRUCTION
The STOP instruction can result in one of two operations depending on the Mask Options.
If the STOP option is enabled, the STOP instruction operates like the STOP in normal
MC68HC05 family members and places the device in the low power STOP Mode. If the
STOP option is disabled, the STOP instruction will cause a chip reset when executed.
8.1.1
STOP MODE
Execution of the STOP instruction, with the proper mask option, places the MCU in its
lowest power consumption mode. In the STOP Mode the internal oscillator is turned off,
halting all internal processing, including the COP Watchdog Timer.
During the STOP mode, the TCR bits are altered to remove any pending timer interrupt
request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit
in the CCR is cleared and the IRQE mask is set in the ICSR to enable external interrupts.
All other registers and memory remain unaltered. All input/output lines remain unchanged.
The processor can be brought out of the STOP mode only by an external interrupt or reset.
The MCU can be brought out of the STOP Mode by only one of the following:
• IRQ pin external interrupt
• Externally or internally generated RESET
• Falling edge on any Port A or Port C pin (if enabled)
• Rising edge on the MDLC BUS pin
When exiting the STOP Mode, the internal oscillator will resume after a 4064 internal
processor clock cycle oscillator stabilization delay, as shown in Figure 8-1.
NOTE: Execution of the STOP instruction with the proper mask option will cause
the oscillator to stop and therefore disable the COP Watchdog Timer. If
the COP Watchdog Timer is to be used, the STOP Mode should be
disabled by selecting the proper mask option. See 6.2.3.4 COP
WATCHDOG TIMER CONSIDERATIONS for more details.
SECTION 8: LOW-POWER MODES
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1
OSC1
t
t
RL
RESET
LIH
2
IRQ
t
4064 t
ILCH
cyc
3
IRQ
MDLC BUS
IDLE
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
3FFE
3FFE
3FFE
3FFE
3FFF
Notes:
RESET OR INTERRUPT
VECTOR FETCH
1. Represents the internal gating of the OSC1 pin.
2. IRQ pin edge-sensitive mask option or Port A/C pin.
3. IRQ pin level and edge sensitive mask option.
Figure 8-1: Stop Recovery Timing Diagram
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STOP
WAIT
STOP Mask
Option En-
abled?
N
Reset Chip
Y
Stop External Oscillator,
Stop Internal Timer Clock,
and Reset Startup Delay
External Oscillator Active,
and Internal
Timer Clock Active
Stop Internal Processor Clock,
Clear I-Bit in CCR,
Stop Internal Processor Clock,
Clear I-Bit in CCR,
Y
Y
External
External
RESET?
RESET?
N
N
IRQ
External
IRQ
External
Y
Y
Interrupt?
Interrupt?
Restart External Oscillator,
and Stabilization Delay
N
N
TIMER
Internal
MDLC
Bus
Y
Y
Interrupt?
Edge?
End
of Startup
N
N
Y
Delay
MDLC
Bus
Edge?
Port A
or C Falling
Edge?
Y
Y
N
Restart
Internal Processor Clock
N
N
Port A
or C Falling
Edge?
1. Fetch Reset Vector
or
2. Service Interrupt
a. Stack
Y
N
b. Set I-Bit
c. Vector to Interrupt Routine
Figure 8-2: STOP/WAIT Flowcharts
8.1.2
WAIT INSTRUCTION
The WAIT instruction places the MCU in a low-power mode, which consumes more power
than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending
all processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the timer or a reset to be generated from the COP
Watchdog Timer. Execution of the WAIT instruction automatically clears the I-bit in the
Condition Code Register. All other registers, memory, and input/output lines remain in their
previous states.
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If timer interrupts are enabled, a TIMER interrupt will cause the processor to exit the WAIT
Mode and resume normal operation. The Timer may be used to generate a periodic exit
from the WAIT Mode. The MCU can be brought out of the WAIT Mode by one of the
following:
• TIMER interrupt from either timer
• IRQ pin external interrupt
• Externally or internally generated RESET
• Falling edge on any Port A or Port C pin (if enabled)
• Rising edge on the MDLC BUS pin
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SECTION 9
PARALLEL I/O
In the Single-Chip Mode there are 28 bidirectional I/O lines arranged as three 8-bit I/O ports
(Ports A, B and C) and one 4-bit I/O port (Port F), and 16 input only lines arranged as two
8-bit ports (Ports D and E). The individual bits in the I/O ports are programmable as either
inputs or outputs under software control by the data direction registers (DDRs). The Port A
and Port C pins also have the additional properties of acting as additional IRQ interrupt
input sources.
9.1
PORT A AND PORT C
Port A and Port C are 8-bit bidirectional ports which share all of their pins with the IRQ
interrupt system as shown in Figure 9-1. Each pin is controlled by the corresponding bits in
a data direction register and a data register. The Port A Data Register is located at address
$0000.The Port C Data Register is located at address $0002. The Port A Data Direction
Register (DDRA) is located at address $0004. The Port C Data Direction Register (DDRC)
is located at address $0006. Reset clears DDRA and DDRC. The Data Registers are
unaffected by reset.
Read $0004/06
Write $0004/06
Data Direction
Register Bit
I/O
Pin
Write $0000/02
Read $0000/02
Output
Data
Register Bit
Internal HC05
Data Bus
Reset
(RST)
to IRQ interrupt system
Port A/C Bits 0 thru 7
Figure 9-1: Port A and Port C I/O Circuitry
PORT A/C DATA REGISTERS
9.1.1
Each Port A/C I/O pin has a corresponding bit in the Port A/C Data Register. When a Port
A/C pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin. When a Port A/C pin is programmed as an input, any
SECTION 9: PARALLEL I/O
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read of the Port A/C Data Register will return the logic state of the corresponding I/O pin.
The Port A/C data register is unaffected by reset.
9.1.2
PORT A/C DATA DIRECTION REGISTER
Each Port A/C I/O pin may be programmed as an input by clearing the corresponding bit in
the DDRA/C, or programmed as an output by setting the corresponding bit in the DDRA/C.
The DDRA can be accessed at address $0004. The DDRC can be accessed at address
$0006. The DDRA and DDRC are cleared by reset.
9.1.3
PORT A/C I/O PIN INTERRUPTS
The inputs of all eight bits of Port A and Port C are ANDed into the IRQ input of the CPU.
Each port has its own interrupt request latch to enable the user to differentiate between the
IRQ sources. The port IRQ inputs are falling edge sensitive only. Any Port A or Port C pin
can be disabled as an interrupt input by setting the corresponding DDR bit. Any Port A or
Port C pins that are outputs will not cause a port interrupt when the pin transitions from a 1
to a 0. However, since all inputs pins are ANDed together to form the interrupt signal, any
input pin that remains low will inhibit the interrupt flag bit from being set when subsequent
pins transition low.
NOTE: The BIH and BIL instructions will only apply to the level on the IRQ pin
itself, and not to the internal IRQ input to the CPU. Therefore BIH and BIL
cannot be used to obtain the result of the logical combination of the eight
pins of Port A or Port C.
9.2
PORT B
Port B is an 8-bit bidirectional port. Each Port B pin is controlled by the corresponding bits
in a data direction register and a data register as shown in Figure 9-2. PB6 and PB7 are
shared with 16 Bit Timer functions. See SECTION 11 16-BIT TIMER. The Port B Data
Register is located at address $0001. The Port B Data Direction Register (DDRB) is located
at address $0005. Reset clears the DDRB register. The Port B Data Register is unaffected
by reset
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.
Read $0005
Write $0005
Data Direction
Register Bit
I/O
Pin
Write $0001
Read $0001
Output
Data
Register Bit
Internal HC05
Data Bus
Reset
(RST)
Figure 9-2: Port B I/O Circuitry
9.2.1
PORT B DATA REGISTER
Each Port B I/O pin has a corresponding bit in the Port B Data Register. When a Port B pin
is programmed as an output the state of the corresponding data register bit determines the
state of the output pin. When a Port B pin is programmed as an input, any read of the Port
B Data Register will return the logic state of the corresponding I/O pin. The Port B data
register is unaffected by reset. PB7 serves as the TCAP input and PB6 serves as the TCMP
output if the OCE bit in the MISC Register is set. See 7.2 MISCELLANEOUS REGISTER.
9.2.2
PORT B DATA DIRECTION REGISTER
Each Port B I/O pin may be programmed as an input by clearing the corresponding bit in
the DDRB, or programmed as an output by setting the corresponding bit in the DDRB. The
DDRB can be accessed at address $0005. The DDRB is cleared by reset.
9.3
PORT D AND PORT E
Port D is an 8-bit input only port that shares all of its pins with the A/D converter (AN0
through AN7) as shown in Figure 1-6. The Port D Data Register is located at address
$0003. Port E is an 8-bit input only port which also shares all of its pins with the A/D
converter (AN8 through AN15). The Port E Data Register is located at address $002B.
When the A/D converter is active, one of these 16 input ports may be selected by the A/D
multiplexer for conversion. A logical read of a selected input port will always return 0.
NOTE: Port E is not bonded out in the 56-pin SDIP packaged version.
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V
SS
Read $0003/2B
Input
Pin
To A/D Channel Select Logic
To A/D Sampling Circuitry
Internal HC05
Data Bus
Figure 9-3: Port D and Port E Circuitry
9.4
PORT F
Port F is a 4-bit bidirectional port which shares all of its pins with the SPI subsystem. If the
SPI is enabled, Port F3-1 are disabled as regular I/O pins. PF0 can still function as an
output if the DDR bit is set. Each Port F pin is controlled by the corresponding bits in a data
direction register and a data register. The Port F Data Register is located at address $002C.
The Port F Data Direction Register (DDRF) is located at address $002E. Reset clears the
DDRF register. The Port F Data Register is unaffected by reset. Port F is shared with the
SPI.
9.4.1
PORT F DATA REGISTER
Each Port F I/O pin has a corresponding bit in the Port F Data Register. When a Port F pin
is programmed as an output the state of the corresponding data register bit determines the
state of the output pin. When a Port F pin is programmed as an input, any read of the Port
F Data Register will return the logic state of the corresponding I/O pin. The Port F data
register may be read even if the SPI subsystem is enabled. The Port F data register is
unaffected by reset.
9.4.2
PORT F DATA DIRECTION REGISTER
Each Port F I/O pin may be programmed as an input by clearing the corresponding bit in
the DDRF, or programmed as an output by setting the corresponding bit in the DDRF. The
DDRF can be accessed at address $002E. If the SPI subsystem is enabled (SPE bit is set),
the DDRF bit corresponding to PF0 will determine the function of the PF0 pin. If DDRF0 is
cleared, the PF0 pin functions as a SS (slave select) input to the SPI. If DDRF0 is set, then
PF0 can serve as a normal output pin. When the SPI subsystem is enabled, the DDRF3-1
bits are set or cleared according to the required pin function. The DDRF is cleared by reset.
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SECTION 10
A/D CONVERTER
The MC68HC705V7 includes a 16 channel, 8-bit, multiplexed input, successive
approximation A/D converter. When the device is packaged (in a 56-pin SDIP), pin number
restrictions require that 8 channels, AN8 through AN15, are not bonded out.
10.1 ANALOG SECTION
10.1.1
RATIOMETRIC CONVERSION
The A/D is ratiometric, with two dedicated pins supplying the reference voltages (V
REFH
and V
. An input voltage equal to V
converts to $FF (full scale) and an input
REFL
REFH
)
voltage equal to V
converts to $00. An input voltage greater than V
will convert
REFL
REFH
to $FF with no overflow indication. For ratiometric conversions, the source of each analog
input should use V
as the supply voltage and be referenced to V
.
REFH
REFL
10.1.2
V
AND V
REFH REFL
The reference supply for the converter uses two dedicated pins rather than being driven by
the system power supply lines because the voltage drops in the bonding wires of those
heavily loaded pins would degrade the accuracy of the A/D conversion. V
and V
REFH
REFL
can be any voltage between V
and V
, as long as V
> V
; however, the
SSA1
CCA
REFH
REFL
accuracy of conversions is tested and guaranteed only for V
= V
SSA1
REFL
and V
= V
.
REFH
CCA
10.1.3
ACCURACY AND PRECISION
The 8-bit conversions shall be accurate to within ± 1 1/2 LSB including quantization.
10.2 CONVERSION PROCESS
The A/D reference inputs are applied to a precision internal digital-to-analog converter.
Control logic drives this D/A and the analog output is successively compared to the
selected analog input which was sampled at the beginning of the conversion time. The
conversion process is monotonic and has no missing codes.
10.3 DIGITAL SECTION
10.3.1
CONVERSION TIMES
Each channel of conversion takes 32 clock cycles, which must be at a frequency equal to
or greater than 1 MHz.
SECTION 10: A/D CONVERTER
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10.3.2 INTERNAL VS. MASTER OSCILLATOR
If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC oscillator
(nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by
setting the ADRC bit in the A/D Status and Control Registers to 1. In STOP mode, the
internal RC oscillator is turned off automatically, though the A/D subsystem remains
enabled (ADON remains set). In WAIT mode the A/D subsystem remains functional. See
10.6 A/D DURING WAIT MODE.
When the internal RC oscillator is being used as the conversion clock, three limitations
apply:
1. The Conversion Complete Flag (COCO) must be used to determine when
a conversion sequence has been completed, due to the frequency
tolerance of the RC oscillator and its asynchronism with regard to the
MCU E clock.
2. The conversion process runs at the nominal 1.5 MHz rate but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU E clock so conversion time is limited to a
maximum of one channel per E cycle.
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be turned off, and the system clock used as the
conversion clock.
10.3.3
MULTI-CHANNEL OPERATION
A multiplexer allows the A/D converter to select one of sixteen external analog signals and
four internal reference sources.
10.4 A/D STATUS AND CONTROL REGISTER (ADSCR)
The following paragraphs describe the function of the A/D Status and Control Register.
$1E
COCO
0
ADRC
0
ADON
0
CH4
0
CH3
0
CH2
0
CH1
0
CH0
0
RESET:
Figure 10-1: A/D Status and Control Register
COCO - Conversions Complete
10.4.1
This read-only status bit is set when a conversion is completed, indicating that the A/D Data
Register contains valid results. This bit is cleared whenever the A/D Status and Control
Register is written and a new conversion is automatically started, or whenever the A/D Data
Register is read. Once a conversion has been started by writing to the A/D Status and
Control Register, conversions of the selected channel will continue every 32 cycles until the
A/D Status and Control Register is written again. In this continuous conversion mode the
A/D Data Register will be filled with new data, and the COCO bit set, every 32 cycles. Data
from the previous conversion will be overwritten regardless of the state of the COCO bit
prior to writing.
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10.4.2
ADRC - RC Oscillator Control
When ADRC is set, the A/D section runs on the internal RC oscillator instead of the CPU
clock. The RC oscillator requires a time t
during this time.
to stabilize, and results can be inaccurate
RCON
10.4.3
ADON - A/D On
When the A/D is turned on (ADON = 1), it requires a time t
for the current sources to
ADON
stabilize, and results can be inaccurate during this time. This bit turns on the charge pump.
10.4.4 CH4:CH0 - Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of twenty A/
D channels, including four internal references. Channels $0-7 correspond to Port D input
pins on the MCU. Channels $8-F correspond to Port E input pins on the MCU and are not
bonded out in 56 pin packaged parts. Channels $10-13 are used for internal reference
points. In Single-Chip Mode, channel $13 is reserved and converts to $00. The following
table shows the signals selected by the channel select field.
Table 10-1: A/D Channel Assignments
CH4:CH0
Signal
00-07
08-0F
10
AN0-7
AN8-15
VREFH
*
*
11
(VREFH-
VREFL)/2
12
13
VREFL
*
Factory
Test
14
Unused
* Accuracy not guaranteed for internal channels
10.5 A/D DATA REGISTERS
An 8-bit result register is provided. This register is updated each time the COCO bit is set.
D7
D6
D5
D4
D3
D2
D1
D0
$1D
Figure 10-2: A/D Data Register
SECTION 10: A/D CONVERTER
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10.6 A/D DURING WAIT MODE
The A/D converter continues normal operation during WAIT mode. To decrease power
consumption during WAIT, it is recommended that both the ADON and ADRC bits in the A/
D Status and Control Registers be cleared if the A/D converter is not being used. If the A/
D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that
the ADRC bit be cleared.
NOTE: As the A/D converter continues to function normally in WAIT mode, the
COCO bit is not cleared.
10.7 A/D DURING STOP MODE
In STOP mode the comparator and charge pump are turned off and the A/D ceases to
function. Any pending conversion is aborted. When the clocks begin oscillation upon
leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize
enough to provide conversions to the specified accuracy. Normally, the delays built into the
device when coming out of STOP mode are sufficient for this purpose, therefore no explicit
delays need to be built into the software.
NOTE: Although the comparator and charge pump are disabled in STOP mode,
the A/D Data and Status/Control registers are not modified. Disabling the
A/D prior to entering STOP mode will not effect the STOP mode current
consumption.
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SECTION 11
16-BIT TIMER
The timer consists of a 16-bit, free-running counter driven by a fixed divide-by-four
prescaler. This timer can be used for many purposes, including input waveform
measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds. Figure 11-1: 16-Bit Timer Block
Diagram.
Because the timer has a 16-bit architecture, each specific functional segment (capability)
is represented by two registers. These registers contain the high and low byte of that
functional segment. Access of the high byte inhibits that specific timer function until the low
byte is also accessed.
NOTE: The I bit in the CCR should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt
does not occur.
Internal Bus
Internal
Processor
Clock
High
Byte
Low
Byte
8-Bit
Buffer
∏∏∏
/4
High Low
Byte Byte
$16
$17
Output
Compare
Register
High
Byte
Low
Byte
Input
Capture
Register
16-Bit Free
Running
Counter
$14
$15
$18
$19
Counter
Alternate
Register
$1A
$1B
Edge
Detect
Circuit
Overflow
Detect
Circuit
Output
Compare
Circuit
D
Q
CLK
C
Timer
Output
Level
Reg.
$13
Status ICF OCF TOF
Reg.
Timer
Control RESET
Reg.
$12
ICIE OCIE TOIE IEDG OLVL
Output Edge
Level Input
(TCMP) (TCAP)
PB6 PB7
Interrupt
Circuit
Figure 11-1: 16-Bit Timer Block Diagram
SECTION 11: 16-BIT TIMER
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11.1 COUNTER REGISTER - $18:$19, $1A:$1B
The key element in the programmable timer is a 16-bit, free-running counter or counter
register, preceded by a prescaler that divides the internal processor clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0
MHz. The counter is incremented during the low portion of the internal bus clock. Software
can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two locations, $18-$19
(counter register) or $1A-$1B (counter alternate register). A read from only the least
significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the
time of the read. If a read of the free-running counter or counter alternate register first
addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to
a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the
MSB several times. This buffer is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate register,
if the MSB is read, the LSB must also be read to complete the sequence.
The counter alternate register differs from the counter register in one respect: a read of the
counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter
alternate register can be read at any time without the possibility of missing timer overflow
interrupts due to clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is a read-only register
but only when the timer is enabled. During a power-on reset, the counter is also preset to
$FFFC and begins running only after the TON bit in the TIMER control register is set.
Because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler,
the value in the free-running counter repeats every 262,144 internal bus clock cycles.
When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also
be enabled when counter roll-over occurs by setting its interrupt enable bit (TOIE).
NOTE: The I bit in the CCR should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt
does not occur.
11.2 OUTPUT COMPARE REGISTER - $16:$17
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB)
and $17 (LSB). The output compare register is used for several purposes, such as
indicating when a period of time has elapsed. All bits are readable and writable and are not
altered by the timer hardware or reset. If the compare function is not needed, the two bytes
of the output compare register can be used as storage locations.
The output compare register contents are continually compared with the contents of the
free-running counter. If a match is found, the corresponding output compare flag (OCF) bit
is set and the corresponding output level (OLVL) bit is clocked to an output level register.
The output compare register values and the output level bit should be changed after each
successful comparison to establish a new elapsed time-out. An interrupt can also
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accompany a successful output compare provided the corresponding interrupt enable bit
(OCIE) is set. After a processor write cycle to the output compare register containing the
MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The
user must write both bytes (locations) if the MSB is written first. A write made only to the
LSB ($17) will not inhibit the compare function. The free-running counter is updated every
four internal bus clock cycles. The minimum time required to update the output compare
register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level register regardless of
whether the output compare flag (OCF) is set or clear.
11.3 INPUT CAPTURE REGISTER - $14:$15
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are
used to latch the value of the free-running counter after the corresponding input capture
edge detector senses a defined transition. The level transition that triggers the counter
transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This
delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each
proper signal transition regardless of whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds
to the most recent input capture.
After a read of the input capture register MSB ($14), the counter transfer is inhibited until
the LSB ($15) is also read. This characteristic causes the time used in the input capture
software routine and its interaction with the main program to determine the minimum pulse
period. A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
NOTE: The Input Capture pin (TCAP) and the Output Compare pin (TCMP) are
shared with PB7 and PB6 respectively. The timer’s TCAP input is always
connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the
MISCELLANEOUS control register is set. See 7.2.2OCE - Output
compare enable.
SECTION 11: 16-BIT TIMER
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11.4 TIMER CONTROL REGISTER (TCR) - $12
The TCR is a read/write register containing six control bits. Three bits control interrupts
associated with the timer status register flags ICF, OCF and TOF.
$12
ICIE
0
OCIE
0
TOIE
0
0
0
0
0
TON
0
IEDG
0
OLVL
0
RESET
Figure 11-2: Timer Control Register - $12
11.4.1
11.4.2
11.4.3
11.4.4
ICIE - Input Capture Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
TOIE - Timer Overflow Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
TON - Timer On
When disabled, the timer is initialized to the reset condition.
1 - Timer enabled
0 - Timer disabled
11.4.5
IEDG - Input Edge
Value of input edge determines which level transition on TCAP pin will trigger free-
running counter transfer to the input capture register. Reset clears this bit.
1 - Positive edge
0 - Negative edge
11.4.6
OLVL - Output Level
Value of output level is clocked into output level register by the next successful
output compare and will appear on the TCMP pin.
1 - High output
0 - Low output
11.5 TIMER STATUS REGISTER (TSR) - $13
The TSR is a read-only register containing three status flag bits.
$13
ICF
0
OCF
0
TOF
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 11-3: Timer Status Register - $13
SECTION 11: 16-BIT TIMER
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11.5.1
ICF - Input Capture Flag
1 - Flag set when selected polarity edge is sensed by input capture edge
detector
0 - Flag cleared when TSR and input capture low register ($15) are
accessed
Reset clears this bit.
11.5.2 OCF - Output Compare Flag
1 - Flag set when output compare register contents match the free-running
counter contents
0 - Flag cleared when TSR and output compare low register ($17) are
accessed
Reset clears this bit.
11.5.3
TOF - Timer Overflow Flag
1 - Flag set when free-running counter transition from $FFFF to $0000
occurs
0 - Flag cleared when TSR and counter low register ($19) are accessed
Reset clears this bit.
11.5.4
Bits 0-4 - Not used
Always read zero.
Accessing the timer status register satisfies the first condition required to clear status bits.
The remaining step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The MSB of the free-running counter is read but not for the purpose of
servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as the free-
running counter (at address $18 and $19); therefore, this alternate register can be read at
any time without affecting the timer overflow flag in the timer status register.
11.6 TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active if turned on prior
to entering wait mode. If interrupts are enabled, a timer interrupt will cause the processor
to exit the WAIT mode.
11.7 TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds the last count value if STOP is exited
by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if the
TIMER is on and at least one valid input capture edge occurs at the TCAP pin, the input
SECTION 11: 16-BIT TIMER
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capture detect circuit is armed. This does not set any timer flags nor wake up the MCU, but
when the MCU does wake up, there is an active input capture flag and data from the first
valid edge that occurred during the STOP mode. If RESET is used to exit STOP mode, then
no input capture flag or data remains, even if a valid input capture edge occurred.
t
t
t
TH
TLTL
TL
TCAP
Figure 11-4: TCAP Timing
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SECTION 12
CORE TIMER
The Core Timer for this device is a 12-stage multifunctional ripple counter. The features
include Timer Over Flow, Power-On Reset (POR), Real Time Interrupt (RTI), and COP
Watchdog Timer.
Internal Bus
8
8
COP
Clear
Internal Peripheral Clock (Ε)
2
E/2
CTCR
$09 Core Timer Counter Register (CTCR)
9
10
E / 2
E/2
5-bit counter
div
/4
12
E / 2
TCBP
14
E / 2
13
E / 2
12
E / 2
11
E / 2
POR
RTI Select Circuit
Overflow
Detect
Circuit
RTI
out
CTCSR
Timer Control &
$08
CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0
Status Register
COP Watchdog
Timer (÷8)
Interrupt Circuit
3
2
To Interrupt
Logic
To Reset
Logic
Figure 12-1: Core Timer Block Diagram
SECTION 12: CORE TIMER
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As seen in Figure 6-1, the internal peripheral clock is divided by four then drives an 8-bit
ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by
accessing the Core Timer Counter Register (CTCR) at address $09. A timer overflow
function is implemented on the last stage of this counter, giving a possible interrupt rate of
the Internal Peripheral clock(E)/1024. This point is then followed by two more stages, with
the resulting clock (E/2048) driving the Real Time Interrupt circuit (RTI). The RTI circuit
consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further
divided by eight to drive the mask optional COP Watchdog Timer circuit. The RTI rate
selector bits, and the RTI and CTOF enable bits and flags are located in the Timer Control
and Status Register at location $08.
12.1 CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08
The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real
time interrupt rate select bits. Figure 12-2 shows the value of each bit in the CTCSR when
coming out of reset.
$08
CTOF
0
RTIF
0
TOFE
0
RTIE
0
TOFC
0
RTFC
0
RT1
1
RT0
1
RESET:
Figure 12-2: Core Timer Control and Status Register
CTOF - Core Timer Over Flow
12.1.1
CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00.
Clearing the CTOF is done by writing a ‘1’ to TOFC. Writing to this bit has no effect. Reset
clears CTOF.
12.1.2
RTIF - Real Time Interrupt Flag
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The
clock frequency that drives the RTI circuit is E/2**11 (or E/2048) with three additional
divider stages giving a maximum interrupt period of 7.8 milliseconds at a bus rate of 2.1
MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (1
of 4 selection) stage goes active. Clearing the RTIF is done by writing a “1” to RTFC.
Writing has no effect on this bit. Reset clears RTIF.
12.1.3
TOFE - Timer Over Flow Enable
When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset
clears this bit.
12.1.4
RTIE - Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset
clears this bit.
12.1.5
TOFC - Timer Over Flow Flag Clear
When a “1” is written to this bit, CTOF is cleared. Writing a “0” has no effect on the CTOF
bit. This bit always reads as zero.
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12.1.6
RTFC - Real Time Interrupt Flag Clear
When a “1” is written to this bit, RTIF is cleared. Writing a “0” has no effect on the RTIF bit.
This bit always reads as zero.
12.1.7
RT1:RT0 - Real Time Interrupt Rate Select
These two bits select one of four taps from the Real Time Interrupt circuit. Table 12-1 shows
the available interrupt rates with a 2.1 and 1.05MHz bus clock. Reset sets these two bits
which selects the lowest periodic rate and gives the maximum time in which to alter these
bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period
is imminent or uncertain. If the selected tap is modified during a cycle in which the counter
is switching, an RTIF could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 12-1: RTI and COP Rates at 2.1 MHz
RTI RATE
RT1:RT0
MIN. COP RATES
2.1 MHz
0.97 ms
1.05 MHz
1.95 ms
2.1 MHz
1.05 MHz
13.65ms
11
14 11
2 /E
(2 -2 )/E
00
01
10
11
6.83 ms
13.65 ms
27.31 ms
54.61 ms
12
15 12
2 /E
(2 -2 )/E
1.95 ms
3.90 ms
7.80 ms
3.90 ms
7.80 ms
15.60 ms
27.31ms
54.61ms
109.23ms
13
16 13
2 /E
(2 -2 )/E
14
17 14
2 /E
(2 -2 )/E
12.2 COMPUTER OPERATING PROPERLY (COP) RESET
The COP watchdog timer function is implemented on this device by using the output of the
RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table
12-1. If the COP circuit times out, an internal reset is generated and the normal reset vector
is fetched. Preventing a COP time-out, or clearing the COP, is accomplished by writing a
“0” to bit 0 of address $3FF0. When the COP is cleared, only the final divide by eight stage
(output of the RTI) is cleared.
If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the
MCU. In addition the RESET pin will be pulled low for a minimum of 3 E Clock cycle for
emulation purposes. During a chip reset (regardless of the source), the entire Core Timer
counter chain is cleared.
The COP will remain enabled after execution of the WAIT instruction and all associated
operations apply. If the STOP instruction is disabled, execution of STOP instruction will
cause an internal reset.
This COP’s objective is to make it impossible for this part to become “stuck” or “locked-up”
and to be sure the COP is able to “rescue” the part from any situation where it might entrap
itself in an abnormal or unintended behavior. This function is a mask option.
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12.3 CORE TIMER COUNTER REGISTER (CTCR) $09
The Timer Counter Register is a read-only register which contains the current value of the
8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU
clock (E/4) and can be used for various functions including a software input capture.
Extended time periods can be attained using the TOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter.
$09
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12-3: Timer Counter Register
The power-on cycle clears the entire counter chain and begins clocking the counter. After
4064 cycles, the power-on reset circuit is released which again clears the counter chain and
allows the device to come out of reset. At this point, if RESET is not asserted, the timer will
start counting up from zero and normal device operation will begin. When RESET is
asserted anytime during operation (other than POR), the counter chain will be cleared.
12.4 TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If interrupts are
enabled, a timer interrupt will cause the processor to exit the WAIT mode. The COP is
always enabled while in user mode.
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SECTION 13
PULSE WIDTH MODULATOR
The pulse width modulator (PWM) system has one 6-bit channel (PWMA). Preceding the
6-bit (÷64) PWM are two programmable prescalers.The PWM frequency is selected by
choosing the desired divide option from the programmable prescalers. Note that the PWM
clock input is f , which is twice the bus frequency. The PWM frequency will be f
/
osc
osc
(PSA+PSB+64) where PSA and PSB are the values selected by the A and B prescaler and
64 comes from the 6-bit modulus counter. See Table 13-1 for precise values. E is the
internal bus frequency fixed to half of the external oscillator frequency.
f
osc
RCLK
SCLK
Integer divide
6-BIT COUNTER
÷1, ÷8, ÷16
÷1-16
(÷64)
PWM
PIN LOGIC
MODULUS &
COMPARATOR
PWMA
PWM DATA
REGISTER
PWM DATA
BUFFER
PWM CONTROL REGISTER and BUFFER
Figure 13-1: PWM Block Diagram
13.1 FUNCTIONAL DESCRIPTION
The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM
Data Register yields an “low” output (0%), but a $3F yields a duty of 63/64. To achieve the
100% duty (“high” output), the polarity control bit is set to zero while the data register has
$00 in it.
When not in use, the PWM system can be shut off to save power by clearing the clock rate
select bits PSA0 and PSA1 in PWMCR.
Writes to the PWM data register are buffered and can therefore be performed at any time
without affecting the output signal. When the PWM subsystem is enabled, a write to the
PWM Control Register will become effective immediately.
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When the PWM subsystem is enabled, a write to the PWM Data Register will not become
effective until the following condition has been met.
• The end of the current PWM period has occurred, at which time the new
data value is loaded into the PWM Data Register.
However, should a write to the registers be performed when the PWM subsystem is
disabled, the data is transferred immediately. All Registers are updated after the PWM Data
Register is written to and the end of a PWM cycle occurs.
The PWM output can have an active high or an active low pulse under software control
using the POL (polarity) bit as shown in Figure 13-2 and Figure 13-3.
T
$05
$3F
$1F
PWM register = $x0
Figure 13-2: PWM Waveform Examples (POL = 1)
T
$05
$3F
$1F
PWM register = $x0
Figure 13-3: PWM Waveform Examples (POL = 0)
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13.2 REGISTERS
Associated with the PWM system, there is a PWM data register and a control register. The
following registers can be written to and read at any time. Data written to the data register
is held in a buffer and transferred to the PWM Data Register at the end of a PWM cycle.
Reads of this register will always result in the read of the PWM Data Register and not the
buffer.
Upon RESET the user should write to the data register prior to enabling the PWM system
(for example, prior to setting the PSA and PSB bits for PWM input clock rate). This will
avoid an erroneous duty cycle from being driven. During regular user mode the user should
write to the PWM Data data register after writing the PWM Control Register.
Y
POR
OR RESET
N
Write PWM CONTROL
Write PWM Data 1
Initialize PWM Data 0
Write PWM CONTROL
Figure 13-4: PWM Write Sequences
PWM CONTROL
13.2.1
PSA1
0
PSA0
0
--
--
--
--
PSB3
0
PSB2
0
PSB1
PSB0
0
$31
RESET:
0
Figure 13-5: PWM Control Register
PSA1, PSA0, PSB3-PSB0- PWM Clock Rate
These bits select the input clock rate and determines the period, as shown in Table 13-1.
Note that some output frequencies can be obtained with more than one combination of PSA
Table 13-1: PWM Clock Rate
PSA1:PSA0
PSB3-PSB0
RCLK
SCLK
PWM OUT
00
01
xxxx
off
off
off
0000-1111
f
/1
f
/1-f /16
f
/64-
osc
osc
osc
osc
f
/1024
osc
10
0000-1111
f
/8
f
/8-f /128
f
/512-
osc
osc
osc
osc
f
/8192
osc
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Table 13-1: PWM Clock Rate
PSA1:PSA0
PSB3-PSB0
0000-1111
RCLK
/16
SCLK
PWM OUT
/1024-
11
f
f
/16-f
256
/
f
osc
osc
osc
osc
f
/16384
osc
and PSB values. For instance a PWM output of E/512 can be obtained with either
PSA1:PSA0 = 10 and PSB3-PSB0 = 0001 or PSA1:PSA0 = 01 and PSB3-PSB0 = 1000.
This scheme allows for 38 unique frequency selections.
13.2.2
PWM DATA REGISTERS
The PWM system has one 8-bit data register which hold the duty cycle for each PWM
output in the least significant 6 bits. The data bits in this register are unaffected by RESET.
$30
POL
1
-
D5
—
D4
—
D3
—
D2
—
D1
—
D0
—
RESET:
—
Figure 13-6: PWM Data Register
POL - PWM Polarity
1 = PWM pulse is active high.
0 = PWM pulse is active low.
13.3 PWM DURING WAIT MODE
The PWM continues normal operation during WAIT mode. To decrease power
consumption during WAIT, it is recommended that the rate select bits in the PWM Control
Register be cleared if the PWM is not being used.
13.4 PWM DURING STOP MODE
In STOP mode the oscillator is stopped causing the PWM to cease functioning. Any signal
in process is aborted in whatever phase the signal happens to be in.
13.5 PWM DURING RESET
Upon RESET the PSA0 and PSA1 bits in PWM CONTROL are cleared. This disables the
PWM system and sets the PWMA output low. The user should write to the data registers
prior to enabling the PWM system (for example, prior to setting PSA1 or PSA0). This will
avoid an erroneous duty cycle from being driven.
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SECTION 14
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) is an interface which allows several MC68HC05
MCUs, or MC68HC05 MCU plus peripheral devices, to be interconnected within a single
printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI
format, the clock is not included in the data stream and must be furnished as a separate
signal. An SPI system may be configured in one containing one master MCU and several
slave MCUs, or in a system in which an MCU is capable of being a master or a slave.
Features include:
• Full duplex, three-wire synchronous transfers
• Master or slave operation
• Internal MCU clock divided by 2 (maximum) master bit frequency
• Internal MCU clock (maximum) slave bit frequency
• Four programmable master bit rates
• Programmable clock polarity and phase
• End of transmission interrupt flag
• Write collision flag protection
• Master-Master mode fault protection capability
14.1 SPI SIGNAL DESCRIPTION
The four basic signals (MOSI, MISO, SCK, SS) are described in the following paragraphs.
Each signal function is described for both the master and slave mode.
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The SPI forces the direction on some of the pin to output in order to function properly.
SS
SCK
(CPOL=0, CPHA=0)
SCK
(CPOL=0, CPHA=1)
SCK
(CPOL=1, CPHA=0)
SCK
(CPOL=1, CPHA=1)
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 14-1: Data Clock Timing Diagram
Master In Slave Out (MISO/PF3)
14.1.1
The MISO line is configured as an input in a master device and as an output in a slave
device. It is one of the two lines that transfer serial data in one direction, with the most
significant bit sent first. The MISO line of a slave device is placed in the high-impedance
state if the slave is not selected.
14.1.2
Master Out Slave In (MOSI/PF2)
The MOSI line is configured as an output in a master device and as an input in a slave
device. It is one of the two lines that transfer serial data in one direction with the most
significant bit sent first.
14.1.3
Serial Clock (SCK/PF1)
The master clock is used to synchronize data movement both in and out of the device
through its MOSI and MISO lines. The master and slave devices are capable of exchanging
a byte of information during a sequence of eight clock cycles. Since SCK is generated by
the master device, this line becomes an input on a slave device.
As shown in Figure 14-1, four possible timing relationships may be chosen by using control
bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and
slave devices must operate with the same timing. The master device always places data
on the MOSI line a half-cycle before the clock edge (SCK), in order for the slave device to
latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a
slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
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14.1.4
Slave Select (SS/PF0)
The slave select (SS) input line is used to select a slave device. It has to be low prior to
data transactions and must stay low for the duration of the transaction.The SS line on the
master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the SPSR.
When CPHA=0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS
must go high between successive characters in an SPI message. When CPHA=1, SS may
be left low for several SPI characters. In cases where there is only one SPI slave MCU, its
SS line could be tied to V as long as CPHA=1 clock modes are used. The SS pin is
SS
shared with the PF0 pin. See 9.4PORT F for additional information on the SS pin.
14.2 FUNCTIONAL DESCRIPTION
Figure 14-2 shows a block diagram of the serial peripheral interface circuitry. When a
master device transmits data to a slave via the MOSI line, the slave device responds by
sending data to the master device via the master’s MISO line. This implies full duplex
transmission with both data out and data in synchronized with the same clock signal. Thus,
the byte transmitted is replaced by the byte received and eliminates the need for separate
transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that
the I/O operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data
transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This
condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data
byte is shifted, the SPIF flag of the SPSR is set.
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S
M
PF3/
MISO
INTERNAL
MCU CLOCK
MSB
LSB
M
S
PF2/
MOSI
8-BIT SHIFT REG
DIVIDER
READ DATA BUFF
÷2
÷4 ÷16 ÷32
CLOCK
SPI CLOCK (MASTER)
S
SELECT
CLOCK
LOGIC
PF1/
SCK
M
PF0/
SS
MSTR
SPE
SPI CONTROL
SPI STATUS REGISTER
SPI CONTROL REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 14-2: Serial Peripheral Interface Block Diagram
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL
bit in the SPCR, until data is written to the shift register, at which point eight clocks are
generated to shift the eight bits of data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock
at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is
received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift
register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from the master to shift
the data out on the slave’s MISO line.
Figure 14-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
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MASTER
SLAVE
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI CLOCK
GENERATOR
SCK
SS
SCK
SS
V
DD
Figure 14-3: Serial Peripheral Interface Master-Slave Interconnection
14.3 SPI REGISTERS
There are three registers in the SPI which provide control, status, and data storage
functions. These registers are called the serial control register (SPCR), serial peripheral
status register (SPSR), and serial peripheral data I/O register (SPDR) and are described in
the following paragraphs.
14.3.1
Serial Peripheral Control Register (SPCR)
$0A
SPIE
0
SPE
0
—
0
MSTR
0
CPOL
0
CPHA
1
SPR1
U
SPR0
U
RESET:
Figure 14-4: SPI Control Register (SPCR)
SPIE - Serial Peripheral Interrupt Enable
0 = SPIF interrupts disabled
1 = SPI interrupt is SPIF=1
SPE - Serial Peripheral System Enable
0 = SPI system off
1 = SPI system on. Port F becomes SPI pins. SS is a special case. See 9.4
PORT F for additional information.
MSTR - Master Mode Select
0 = Slave mode
1 = Master mode
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CPOL - Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, a steady
state low value is produced at the SCK pin of the master device. Conversely, if
this bit is set, the SCK pin will idle high. This bit is also used in conjunction with
the clock phase control bit to produce the desired clock-data relationship
between master and slave. Figure 14-1: Data Clock Timing Diagram.
CPHA - Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPOL bit can be thought of as
simply inserting an inverter in series with the SCK line. The CPHA bit selects one
of two fundamentally different clocking protocols. When CPHA=0, the shift clock
is the OR of SCK with SS. As soon as SS goes low, the transaction begins and
the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin
may be thought of as a simple output enable control. Figure 14-1: Data Clock
Timing Diagram.
SPR1 and SPR0 - SPI Clock Rate Selects
These two bits select one of four baud rates (Figure 14-5) to be used as SCK if
the device is a master; however, they have no effect in the slave mode.
INT MCU CLOCK
DIVIDED BY
SPR1
SPR0
0
0
1
1
0
1
0
1
2
4
16
32
Figure 14-5: Serial Peripheral Rate Selection
Serial Peripheral Status Register (SPSR)
14.3.2
$0B
SPIF
0
WCOL
0
—
0
MODF
0
—
0
—
0
—
0
—
0
RESET:
Figure 14-6: SPI Status Register (SPSR)
SPIF - SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of data transfer
between the processor and external device. If SPIF goes high, and if SPIE is set,
a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished
by reading the SPSR (with SPIF set) followed by an access of the SPDR. Unless
SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited.
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WCOL - Write Collision
The write collision bit is set when an attempt is made to write to the serial
peripheral data register while data transfer is taking place. If CPHA is zero, a
transfer is said to begin when SS goes low and the transfer ends when SS goes
high after eight clock cycles on SCK. When CPHA is one, a transfer is said to
begin the first time SCK becomes active while SS is low and the transfer ends
when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading
the SPSR (with WCOL set) followed by an access to SPDR.
Bit 5 - Not implemented
This bit always reads zero.
MODF - Mode Fault
The mode fault flag indicates that there may have been a multi-master conflict
for system control and allows a proper exit from system operation to a reset or
default system state. The MODF bit is normally clear, and is set only when the
master device has its SS pin pulled low. Setting the MODF bit affects the internal
serial peripheral interface system in the following ways:
• SPI interrupt is generated if SPIE=1.
• SPE bit is cleared. This disables the SPI.
• MSTR bit is cleared, thus forcing the device into the slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set),
followed by a write to the SPCR. Control bits SPE and MSTR may be restored
to their original state by user software after the MODF bit has been cleared. It is
also necessary to restore DDRD after a mode fault.
Bits 3-0 - Not Implemented
These bits always read zero.
14.3.3
Serial Peripheral Data I/O Register (SPDR)
$0C
SPD7
-
SPD6
-
SPD5
-
SPD4
-
SPD3
-
SPD2
-
PSD1
-
SPD0
-
RESET:
The serial peripheral data I/O register is used to transmit and receive data on the serial bus.
Only a write to this register will initiate transmission/reception of another byte, and this will
only occur in the master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read.
The first SPIF must be cleared by the time a second transfer of the data from the shift
register to the read buffer is initiated, or an overrun condition will exist. In cases of overrun,
the byte that causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into
the shift register for transmission.
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14.4 SPI IN STOP MODE
When the MCU enters the STOP mode, the baud rate generator which drives the SPI shuts
down. This essentially stops all master mode SPI operation; thus, the master SPI is unable
to transmit or receive any data. If the STOP instruction is executed during an SPI transfer,
that transfer is halted until the MCU exits the stop mode (provided it is an exit resulting from
a viable interrupt source). If the stop mode is exited by a reset, then the appropriate control/
status bits are cleared and the SPI is disabled. If the device is in the slave mode when the
STOP instruction is executed, the slave SPI will still operate. It can still accept data and clock
information in addition to transmitting its own data back to a master device.
At the end of a possible transmission with a slave SPI in the stop mode, no flags are set until
a viable interrupt results in an MCU "wake up". Caution should be observed when operating
the SPI (as a slave) during the stop mode because none of the protection circuitry (write
collision, mode fault, etc.) is active.
It should also be noted that when the MCU enters the stop mode all enabled output drivers
(MISO, MOSI, and SCLK ports) remain active and any sourcing currents from these outputs
will be part of the total supply current required by the device.
14.5 SPI IN WAIT MODE
The SPI subsystem remains active in wait mode. Therefore, it is consuming power. If it is
desired to reduce power, the SPI should be shut off prior to entering wait mode. A non-
resetexit from wait mode will result in the state of the SPI being unchanged. A reset exit will
return the SPI to its reset state, which is disabled.
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SECTION 15
MESSAGE DATA LINK CONTROLLER
The Message Data Link Controller (MDLC) provides access to an external serial
communication multiplex bus, operating according to the SAE J1850 protocol.
Key features of the MDLC include:
• SAE J1850 compatible
• GM Class 2 compatible
• 10.4 kbps variable pulse width (VPW) bit format
• Digital noise filter
• Collision detection
• Two 11-byte Receive Buffers, one 11-byte Transmit Buffer
• Hardware CRC generation and checking
• Two power saving modes with automatic wake up on network activity
• Polling and CPU interrupts available
• Receive Block mode supported
• Coexists with devices supporting 4x mode
• Auto retry following loss of arbitration
• In-frame Response not supported
• Low Voltage Protection
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15.1 OUTLINE
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
The CPU Interface contains the software addressable registers and provides the link
between the CPU and the Tx and Rx Buffers. The Tx and Rx Buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The Protocol Handler is
responsible for the encoding and decoding of data bits and special message symbols
during transmission and reception. The MUX Interface provides the link between the MDLC
digital section and the analog Physical Interface. The wave shaping, driving, and digitizing
of data is performed by the Physical Interface.
NOTE: The bus data rate depends upon the microcontroller oscillator frequency
(fOSC) and the MDLC rate selection control bits (R0, R1). The correct
combination for the application must be chosen in order for J1850 bus
communications to take place. See 15.2.2.3 R1, R0 - Rate Select.
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15.1.1
MDLC OPERATING MODES
The MDLC has five main modes of operation that interact with the power supplies, pins, the
and rest of the MCU as shown below.
Power Off
V
> V
(Min.) and
DD
mdlc
V
≤ V
(Min.)
DD
mdlc
Any MCU reset source asserted
Reset
Any MCU reset source asserted
(from any mode)
(COP, ILLADDR, P.U., RESET, LVR, POR
DISABLED STOP)
No MCU reset source asserted
Run
Network activity or
other MCU wake-up
RXMS=1 or
other MCU wake-up
MDLC Stop
MDLC Wait
STOP instruction or
(WAIT instruction and WCM=1)
(WAIT instruction and WCM=0)
Figure 15-1: MDLC Operating Modes State Diagram
15.1.2
15.1.2.1
MODE DESCRIPTIONS
Power Off
This mode is entered from the Reset mode whenever the MCU supply voltage V drops
DD
below the minimum specified value to guarantee correct MDLC operation. In order to
ensure that the MDLC does not enter an unknown state, it will first be placed in the Reset
mode before being powered down. In this mode, the pin input and output specifications are
not guaranteed.
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15.1.2.2
Reset
This mode is entered from the Power Off mode whenever the MCU supply voltage V
DD
rises above the minimum specified value and some MCU reset source is asserted. In order
to prevent an unknown state from being entered and to guarantee correct operation, the
internal MCU reset will be asserted while the MDLC module is being powered up.
This mode is entered from any other mode whenever the MCU supply voltage V drops
DD
below the minimum value for correct MDLC operation. When this occurs, the MDLC module
will reenter the Reset mode before being powered down to prevent an unknown state from
being entered.
The Reset mode is also entered from any other mode as soon as one of the MCU’s possible
reset sources (for example, POR, COP watchdog, Reset pin etc.) is asserted.
In this mode, the internal MDLC voltage references are operative, V is supplied to the
DD
internal circuits, which are held in their reset state and the internal MDLC system clock is
running. Registers will assume their reset condition. Outputs are held in their programmed
reset state, inputs and network activity are ignored.
15.1.2.3
Run
This mode is entered from the Reset mode after all MCU reset sources are no longer
asserted. It is entered from the MDLC Wait mode whenever a message is successfully
received.
It is entered from the MDLC Stop mode whenever network activity is sensed though
messages will not be received properly until the clocks have stabilized and the CPU is also
in the Run mode.
In this mode, normal network operation takes place. The user should ensure that all MDLC
transmissions have ceased before exiting this mode.
15.1.2.4
MDLC Wait
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and if the WCM bit in the MCR register is previously
cleared.
In this mode, the MDLC internal clocks continue to run but the physical interface circuitry is
placed in a low power mode and awaits a valid network message. If a valid network
message is successfully received (RXMS=1) a CPU interrupt request will be generated.
15.1.2.5
MDLC Stop
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set.
In this mode, the MDLC internal clocks are stopped but the physical interface circuitry is
placed in a low power mode and awaits network activity. If network activity is sensed, then
a CPU interrupt request will be generated, restarting the MDLC internal clocks.
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15.2 MDLC CPU INTERFACE
15.2.1
OUTLINE
The CPU Interface provides the interface between the CPU and the MDLC. It consists of 4
user registers. A full description of each register follows:
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
Addr
Name
$000E
$000F
$0010
$0011
MCR
MSR
MTCR
MRSR
Figure 15-2: MDLC User Registers
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15.2.2
MDLC CONTROL REGISTER (MCR) $0E
This register is used to configure and control the MDLC.
Bit 7
RXBM
0
Bit 6
TXAB
0
Bit 5
R1
1
Bit 4
R0
0
Bit 3
Bit 2
Bit 1
Bit 0
WCM
0
-
-
IE
RESET
0
0
0
Figure 15-3: MDLC Control Register (MCR)
All bits may be read in all modes of MCU operation.
Bits 0, 4 and 5 may be written to only once after reset after which they become read only
bits.
Bit 1 may always be written.
Bits 6 and 7 may only be set by the CPU, clears are ignored. These bits are cleared
automatically by the MDLC when the appropriate action is completed.
15.2.2.1
RXBM - Receive Block Mode
This bit is set to indicate to the MDLC that the next incoming message will be a block
message. (See 15.7.4 RECEIVING A MESSAGE IN BLOCK MODE).
If this bit is set and the Rx Buffer being loaded with data bytes received from the multiplex
bus is filled or the last byte of the current block message has been received, a CPU
interrupt request is generated (if the IE bit is set) and the Rx Message Successful (RXMS)
bit will be set, just as in normal message reception. Additional incoming bytes will be placed
into the next available Rx Buffer.
The RC3-0 bits of the MRSR register only reflect the byte count of the Rx Buffer available
to the CPU and not a cumulative value of the number of bytes in the block message.
Once set, this bit can only be cleared automatically by the MDLC. It will be cleared following
the successful reception of a message or immediately upon the receiver detecting an error
(CRC, invalid bit etc.), reverting the MDLC to its usual mode of operation in which normal
message lengths are expected. This bit will also be cleared if both Rx Buffers fill, they are
not serviced and further data bytes are received (Block mode ’overflow’ occurs).
The receiver will compute a cumulative CRC throughout the reception of a block message,
and will not treat the CRC calculation as complete until an End of Data (EOD) symbol is
received. At this time the MDLC will automatically clear the RXBM bit indicating to the
programmer that the block message has ended.
15.2.2.2
TXAB - Transmit Abort
This bit is set by the programmer to abort an in-progress transmission. The subsequent
actions depend upon what the transmitter is doing at the point in time when the CPU
interface recognizes this command.
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If this command is recognized by the MDLC while one of the first seven bits of a byte is
being transmitted (non-byte boundary) then the transmission of the bit will be completed
and no further bits will be sent.
If this command is recognized while the last bit of a byte is being transmitted (byte
boundary) then the transmission of the bit will first be completed. In order to avoid receiving
nodes from interpreting the aborted transmission at a byte boundary as being the end of a
normal message, the MDLC will then send two extra logic one bits.
This guarantees that no aborted message will be an integral number of bytes in length and
cannot be mistaken for a valid transmission.
Arbitration will be performed on any extra bits sent, allowing any other nodes which are also
transmitting to continue. Should the MDLC lose arbitration during the first extra logic one
sent, the second extra logic one will not be sent and no further attempts to send the
message will be made.
If this command is recognized after a write to the MDLC Transmit Control Register (MTCR),
thus initiating a transmission, but before the message has begun to be sent on the J1850
bus, then no attempt to transmit that message will be made until a subsequent write to the
MTCR is made.
If this command is recognized between automatic transmission retry attempts, such as
those following a loss of arbitration, all further attempts to resend the message will be
suppressed.
This bit is automatically cleared after the abort takes place or after it is determined that the
MDLC was not transmitting anyway. Refer to Table 15-1: MDLC Transmit Abort
Function Summary for a summary of the operation of the TXAB bit.
The programmer must never write to the MTCR register while the TXAB bit is set, as this
may have unpredictable results.
Table 15-1: MDLC Transmit Abort Function Summary
Transmit Abort Command
MDLC Action
Command recognized on
non-byte boundary
MDLC will terminate transmission immediately
Command recognized on
byte boundary
MDLC will transmit up to two extra ones
MDLC will not transmit the message
Command recognized
before the message has
started on the J1850 bus
Command recognized
during retry
MDLC will not retry to transmit the message
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15.2.2.3
These bits determine the operating frequency of the MDLC.
The nominal frequency (f ) of the MUX Interface clock must always be 1.048576 MHz
R1, R0 - Rate Select
mdlc
in order for J1850 bus communication to take place. Therefore, the value programmed into
these bits is dependant upon the chosen MCU system clock frequency per the following
table.
Table 15-2: MDLC Rate Selection
Clock Frequency
R1
R0
Division
fMDLC
fOSC =1.048576 MHz
(fOP=524Khz)
0
0
1
1.048576 MHz
fOP=1.048576 MHz
fOP=2.097152 MHz
fOP=4.194304 MHz
0
1
1
1
0
1
1
2
4
1.048576 MHz
1.048576 MHz
1.048576 MHz
In the case of R1=R0=0, the oscillator clock is used instead of E clock.
The case of R1=R0=1 must not be selected for the MC68HC05V7 and MC68HC705V8.
15.2.2.4
IE - Interrupt Enable
This bit determines whether the MDLC will generate CPU interrupt requests in the Run
mode. Clearing the IE bit will not prevent CPU interrupt requests when exiting the MDLC
Stop or MDLC Wait modes.
When set, the MDLC will generate CPU interrupt requests. Interrupt requests will be
maintained until all of the interrupt request sources are cleared, by performing the specified
actions upon the MDLC registers.
When clear, the MDLC will not generate CPU interrupt requests. Interrupts that were
pending at the time that this bit is cleared may be lost.
15.2.2.5
WCM - Wait Clock Mode
This bit determines the operation of the MDLC during CPU Wait mode. See 15.7.6 MDLC
WAIT MODE for more details on its use.
When set, the MDLC internal operating clocks will be stopped during CPU Wait mode.
When clear, the MDLC internal operating clocks will stay running during CPU Wait mode.
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15.2.3
MDLC STATUS REGISTER (MSR) $0F
This register indicates the transmit and receive status of the MDLC.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TXMS
0
Bit 2
RXMS
0
Bit 1
Bit 0
0
0
0
0
0
0
RESET
0
0
0
0
0
0
Figure 15-4: MDLC Status Register (MSR)
All bits may be read in all modes of MCU operation.
Bits 0,1, 4, 5, 6, and 7 will always read as zeros and can never be written to.
Bits 2 and 3 are reflective of CPU interrupt request signals and are asserted as long as their
respective CPU interrupt request is pending. Neither bit is affected by CPU interrupt
requests generated when the MDLC ’wakes up’ from MDLC Stop or MDLC Wait mode.
All writes to this register are ignored in all modes of MCU operation.
15.2.3.1
TXMS - Transmitted Message Successfully
When set this bit indicates that the Tx Buffer contents have been sent successfully.
An access of the Tx Control Register (MTCR) will clear this bit.
15.2.3.2
RXMS - Received Message Successfully
When set, this bit indicates that one of the Rx Buffers contains a new message.
This bit can only be cleared if both Rx Buffers are empty. If only one message has been
received into an Rx Buffer by the MDLC, any access (read or write) of the MDLC Rx Status
Register (MRSR) will clear the RXMS bit.
If a second message is received after the RXMS bit has been cleared by the CPU as it is
retrieving the first message, the RXMS bit will immediately be set again, and will remain set
until the MRSR is accessed once the last message received is made available to the CPU.
If both Rx Buffers contain a received message, the RXMS bit will simply remain set until the
MRSR register is accessed once the last message received is made available to the CPU.
15.2.3.3
TXMS and RXMS Interrupts
If either the TXMS or the RXMS bit is set, and if interrupts are enabled, an interrupt request
will be made to the CPU. The interrupt service routine may poll these bits to establish the
cause of the interrupt. The mechanism for clearing each of these bits will also clear the
associated CPU interrupt request.
Alternatively, if interrupts are disabled, the CPU may poll these bits periodically to see if a
change in status has occurred.
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The MDLC will attempt to receive every message that it sends, so the RXMS bit will usually
be set a short time after the TXMS bit is set.
Because these bits act independently, cannot be written to, and have separate clearing
mechanisms, it is not possible to inadvertently miss an interrupt.
15.2.3.4
Clearing Wake Up Interrupts
Although no flag bit is affected by the MDLC waking up from MDLC Stop Mode (entered by
’STOP’ or ’WAIT’ with WCM bit set previously) due to network activity, the CPU interrupt
request that is generated by the wake up is cleared by an access of the MRSR register.
15.2.4
MDLC TX CONTROL REGISTER (MTCR) $10
This register controls the operation of the MDLC transmitter, including the Tx Buffer.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TC3
0
Bit 2
TC2
0
Bit 1
TC1
0
Bit 0
TC0
0
0
0
0
0
RESET
0
0
0
0
Figure 15-5: MDLC Tx Control Register (MTCR)
All bits may be read in all modes of MCU operation.
Bits 4, 5, 6, and 7 will always read as zeros and can never be written to.
Bits 0, 1, 2, and 3 can be written to in all modes of MCU operation.
15.2.4.1
TC0,1,2,3 - Transmit Count
These bits determine the length of the message body (not including the CRC byte) to be
sent. Internally, they are reset to $00 following a reset.
The programmer should first determine that the MDLC is ready to transmit, then load the
message header and data bytes into the Tx Buffer, and finally write the length of the body
of the message (excluding CRC byte) into this register.
This will cause the MDLC to initiate transmission of the contents of the Tx Buffer according
to the J1850 protocol. Once the last byte has been sent, a Cyclic Redundancy Check
(CRC) byte will automatically be appended to the end of the message body.
Once the CRC has been successfully sent, a CPU interrupt request will be generated (if the
Interrupt Enable (IE) bit is set) and the Tx Message Successful (TXMS) bit will be set in the
MSR register.
An access of this register will clear the CPU interrupt request and the TXMS bit.
The valid range of values that may be written to this register is $01 to $0B. Since the Tx
Buffer is 11 bytes long, any value greater than or equal to $0C written to this register will
create a Tx Buffer overflow error and cause the MDLC to not transmit that message.
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Attempts to send a zero byte message body length (value of $00 written to MTCR) will also
prevent the MDLC from transmitting that message.
Writing a value within the valid range to this register will initiate a transmission regardless
of whether any new data has been loaded into the Tx Buffer. Failure to supply new data
before this register is written to will result in the MDLC transmitting whatever data happens
to be in the Tx Buffer at the time of the write.
Do not write to this register while the TXAB bit in the MCR register is set.
This register will be automatically cleared at the end of any transmission, whether it was
successful, unsuccessful or aborted.
15.2.5
MDLC RX STATUS REGISTER (MRSR) $11
This register reports the status of the MDLC receiver, including the Rx Buffer.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
RC3
RC2
RC1
RC0
RESET
0
0
0
0
0
0
0
0
Figure 15-6: MDLC Rx Status Register (MRSR)
All bits may be read in all modes of MCU operation.
Bits 4, 5, 6, and 7 will always read as zeros and can never be written to.
Bits 0, 1, 2, and 3 can be written to in all modes of MCU operation.
15.2.5.1
RC0,1,2,3 - Receive Count
These bits reflect the number of bytes of the message body in the Rx Buffer available to
the CPU. As a message is being received, the data is placed into successive locations of
one of the two Rx Buffers. The Rx Buffer being filled is not visible to the programmer.
A running count of the number of bytes received is kept internally. The maximum count is
11 bytes. The CRC is not placed in the Rx Buffer and is not counted in the final indicated
message length.
Once the message has been received error-free, the Rx Buffer is placed into the MCU’s
memory map, the MRSR is updated with the count of the number of data bytes received, a
CPU interrupt request is generated if the Interrupt Enable (IE) bit is set and the Rx Message
Successful (RXMS) bit will be set in the MSR.
When the programmer has finished analyzing the received message, a write to this register
will signal to the MDLC that the programmer no longer needs the contents of the Rx Buffer.
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The Rx Buffer will then be released back to the MDLC. If another message is available in
the second Rx Buffer at this time, the new message will then be made available to the CPU.
Following a write to the MRSR to release the Rx Buffer, this register should not be
accessed again until the RXMS bit is again verified to be set. This procedure will ensure
that the MRSR value does not change while it is being accessed by the CPU.
If, while performing the above operations, another message begins to arrive then the
second message will be placed in a duplicate Rx Buffer. The MDLC will always present the
oldest available message to the programmer, therefore only one Rx Buffer appears in the
memory map while the other one is filled with a newer message.
If both Rx Buffers are filled when a third new message arrives, the third message will be
ignored and the prior messages within the Rx Buffers will not be affected.
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15.3 MDLC Rx/Tx BUFFERS
The Rx and Tx Buffers provide the interface between the CPU Interface and the Protocol
Handler. They provide buffering of data being sent and received, reducing the frequency of
interrupts to the CPU. Please refer to the MCU memory map for details on the starting and
ending addresses of these buffers within the overall memory map.
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
15.3.1
OUTLINE
During all modes of MCU operation, the Rx and Tx Buffers are mapped as registers.
Memory mapping these buffers requires the MDLC to supply the user with a count of the
number of bytes in each received message and allows the user to tell the MDLC the length
of a message to be transmitted.
Access arbitration is simplified by the following rules:
• The user must not read the Rx Buffer until the MDLC signals that an entire
message has been received (Receive Message Successful bit (RXMS) in
the MDLC Status Register (MSR) is set).
• The user returns the Rx Buffer resource to the MDLC by writing any value
to the MDLC Receive Status Register (MRSR).
• The user must not write to the Tx Buffer after the MDLC has been told to
transmit the message (length of message has been written to the MDLC
Transmit Control Register (MTCR)).
• The user must wait until the MDLC has sent the message (indicated by a
CPU interrupt request and the Transmit Message Successful (TXMS) bit
being set), or the message has been aborted (Transmit Abort bit (TXAB)
in the MDLC Control Register (MCR) is toggled) before reloading the Tx
Buffer.
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The MDLC has three 11 byte buffer arrays. The transmit circuitry uses a single Tx Buffer,
that for certain periods of time may have either the CPU or the MDLC access "locked out".
The receiver has two Rx Buffers but only one can appear in the MCU memory map at a
time. The CPU will have access to whichever Rx Buffer was filled the earliest. While the
CPU is reading data from one Rx Buffer, the MDLC may place incoming data into the other
Rx Buffer. When the CPU writes to the MRSR register, the Rx Buffer which the CPU had
access to is "given back" to the MDLC making it available for another incoming message.
The MDLC Tx Buffer is writable by the CPU at all times but it is not readable. A read of the
Tx buffer will result in an unknown value. The Rx Buffers can be read by the CPU at
anytime. However, writes to the Rx Buffer will not have an effect on the buffer’s content.
NOTE: The contents of the Tx Buffer are not guaranteed to remain intact following
a transmission so the Tx Buffer should be completely reloaded for each
new message to be sent.
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Indicates active path
MRSR
Rx Buffer
Array
#1
11 bytes
MDLC
Rx Logic
To
CPU
MUX
MUX
MRSR
Rx Buffer
Array
#2
Write to MRSR
"gives back" buffer
to MDLC for Rx.
MDLC automatically
toggles multiplexer (MUX)
11 bytes
when one buffer is full.
MTCR
Tx Buffer
Array
MDLC
Tx Logic
From
CPU
Write to MTCR
"gives back" buffer
to MDLC for Tx.
11 bytes
Figure 15-7: MDLC Rx/Tx Buffers Outline
15.3.2
RX BUFFERS
The Rx Buffers consist of two 11-byte arrays, with 8 bits per byte. Only one message may
occupy each Rx Buffer array at any time. Each Rx Buffer array has an internal register (the
’Rx Buffer pointer’) associated with it in which the length of the message body is recorded.
Following a reset, the MDLC has "possession" of the two empty Rx Buffers and their
associated Rx Buffer pointers are both reset to zero. Neither Rx Buffer appears in the CPU
memory map at this time, attempts to read them will return undefined data.
As each data byte of an incoming message is received by the MDLC, it is placed into the
next available entry of one of the Rx Buffers and the Rx Buffer pointer is incremented. This
continues until the end of the message is detected or an error occurs.
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If the received message is verified as error-free then the CRC is discarded, the filled Rx
Buffer and the final value of the Rx Buffer pointer are placed into the CPU memory map,
the Received Message Successfully (RXMS) bit in the MDLC Status Register (MSR) is set,
a CPU interrupt request is made (if interrupts are enabled) and the other Rx Buffer and its
pointer are readied for reception of the next message by the MDLC.
The CPU may now randomly read the Rx Buffer. The first data byte received will be located
in the lowest address entry of the Rx Buffer. The rest of the message is located in
contiguous ascending address entries up to the last data byte received, which will be
located in the nth entry, where ’n’ is the final value of the Rx Buffer pointer which now
appears in the MDLC Rx Status Register (MRSR).
As long as the CPU has possession of this Rx Buffer, the MDLC will have possession of
the other Rx Buffer and can concurrently receive a second message without conflict with,
or intervention by, the CPU. Once the CPU has finished with the contents of the Rx Buffer,
it may be "given back" to the MDLC by writing any value to the MRSR register.
The above sequence is then repeated as long as normal data reception takes place.
If the CPU is unable to return an Rx Buffer and the second Rx Buffer becomes filled and a
further new message arrives from the J1850 bus then the new message will be ignored by
the MDLC until an Rx Buffer becomes available to receive new data.
If any type of reception error is detected by the MDLC as a message is being received from
the J1850 bus, the internal Rx Buffer pointer will be reset to zero, effectively flushing the
data received so far, and the MDLC will ignore the rest of the message. When this occurs
the MDLC will not generate a CPU interrupt request and will silently wait for the next valid
SOF symbol.
This will also happen if a message received from the J1850 bus is longer than 12 bytes
(including CRC byte), and the Receive Block mode (RXBM) bit is not set. In both cases,
when the internal Rx Buffer pointer is reset to zero, the associated Rx Buffer array bytes
will not be cleared or changed.
If a message received from the J1850 bus is longer than 12 bytes (including CRC byte),
and the Receive Block mode (RXBM) bit is set then reception of the message will be
continued into the next available Rx Buffer. This will repeat until the end of the message is
detected, at which time the residual data bytes will remain in the last Rx Buffer to be filled.
15.3.3
TX BUFFER
The Tx Buffer consists of one 11-byte array, with 8 bits per byte. Only one message may
occupy the Tx Buffer at any time. The Tx Buffer array has an internal register (the ’Tx Buffer
pointer’) associated with it in which the length of the message body is stored.
Following a reset, the CPU has "possession" of the empty Tx Buffer and its associated Tx
Buffer pointer is reset to zero. The Tx Buffer appears in the CPU memory map at this time,
where the CPU may randomly access it. The first data byte of the message to be sent must
be placed in the lowest address entry of the Tx Buffer. The rest of the message must be
placed in contiguous ascending address entries up to the last data byte to be sent, which
is located in the nth entry, where ’n’ is the length of the message body to be sent.
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As long as the CPU has possession of the Tx Buffer, the MDLC cannot transmit. Once the
CPU has finished with the contents of the Tx Buffer, it may be "given back" to the MDLC by
writing the message body length ’n’ to the MDLC Tx Control Register (MTCR).
Starting from the first entry of the Tx Buffer, the MDLC fetches each data byte from a filled
entry of the Tx Buffer, the Tx Buffer pointer is incremented and the MDLC attempts to
transmit the data byte onto the J1850 bus. This continues until the last byte of the message
body has been fetched, arbitration is lost or an error occurs. If the transmitted message is
sent error-free then a CRC is appended, the filled Tx Buffer is given back to the CPU, the
Transmitted Message Successfully (TXMS) bit in the MDLC Status Register (MSR) is set,
and a CPU interrupt request is made (if interrupts are enabled). This sequence is then
repeated as long as normal data transmission takes place.
If any type of transmission error is detected by the MDLC as a message is being transmitted
onto the J1850 bus, the internal Tx Buffer pointer will be reset to zero, effectively flushing
the data to be sent, and the MDLC will automatically abort transmission. When this occurs
the MDLC will not generate a CPU interrupt request and will silently wait for the next write
to the MTCR register.
If a loss of arbitration occurs while the MDLC is attempting to transmit a message, the
MDLC will immediately halt transmission and become a receiver. As soon as an idle bus
condition is detected, the MDLC will again attempt to transmit the message onto the
multiplex bus. This automatic retry will continue until the message is transmitted
successfully, an error is detected during transmission, or the TXAB bit is set by the CPU.
Since the Tx Buffer is 11 bytes long, any value greater than or equal to $0C written to the
MTCR register will create a Tx Buffer overflow error and cause the MDLC to not transmit
that message. Attempts to send a zero byte message body length (value of $00 written to
MTCR) will also cause the MDLC to not transmit that message.
At the end of a transmission, successful, unsuccessful or aborted, the MTCR register is
automatically cleared. If interrupts are enabled, the programmer should not poll the MTCR
register to detect this action since each access will clear the TXMS bit in the MSR register!
Instead, since the MDLC receives every message that it sends, the programmer should
check that each message that is attempted to be sent is received back within some
acceptable amount of time before attempting to send another message. Failure to receive
back a message that has been sent in a timely fashion might indicate that some network
fault exists.
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15.4 MDLC PROTOCOL HANDLER
The Protocol Handler is responsible for framing, collision detection, arbitration, CRC
generation/checking, and error detection. The Protocol Handler conforms to SAE J1850 -
Class B Data Communications Network Interface.
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
15.4.1
OUTLINE
The Protocol Handler contains three main blocks: the State Machine, Rx Shift Register and
Tx Shift Register, as shown below. Each block will now be described in more detail.
To MUX Interface
State Machine
Rx Shift Register
Tx Shift Register
8
8
To CPU Interface & Rx/Tx Buffers
Figure 15-8: MDLC Protocol Handler Outline
15.4.2
Rx & Tx SHIFT REGISTERS
The Rx Shift Register gathers received serial data bits from the J1850 bus and makes them
available in parallel form to the Rx Buffer. The Tx Shift Register takes data, in parallel form,
from the Tx Buffer and presents it serially to the State Machine so that it can be transmitted
onto the J1850 bus.
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15.4.3
STATE MACHINE
All of the functions associated with performing the protocol are executed or controlled by
the State Machine. The State Machine is responsible for framing, collision detection,
arbitration, CRC generation/checking, and error detection. The following sections describe
the MDLC’s actions in a variety of situations.
15.4.3.1
In-Frame Response
The MDLC does not support the In-Frame Response (IFR) feature of J1850. If the MDLC
receives an IFR, it will ignore the response (not placing it in an Rx Buffer) and wait for the
End of Frame (EOF) symbol.
15.4.3.2
4x Speed Mode
The MDLC can exist on the same J1850 bus as modules which use a special 4x mode of
J1850 VPW operation. The MDLC treats 4x mode messages as noise and ignores them.
The MDLC will wait for a valid SOF or BREAK at 10.4 kbps to resume normal operation.
15.4.3.3
Block Mode
While the MDLC can only transmit a maximum of 12 bytes (including CRC byte) in a given
message, it has the ability to receive a message of unlimited length. Like 4x mode, the
programmer will have to determine from a received message that Block mode is to be
enabled. The programmer then sets the “Receive Block Message” (RXBM) bit in the MDLC
Control Register (MCR) to indicate to the MDLC that the following message will be longer
than 12 bytes and not to treat it as a message over length error.
15.4.3.4
Arbitration
Arbitration is performed by the MDLC simply by comparing the data being received from
the J1850 bus with the data being transmitted. This is done by latching the data being
transmitted into a comparator, where it is compared with the data being received from the
J1850 bus. If a valid data bit is received which has a higher priority over what was
transmitted (0 over 1), arbitration is then lost, and the transmitter stops transmitting until a
valid EOF symbol is received from the J1850 bus. See 15.5.5 MESSAGE ARBITRATION
for more information.
If an invalid bit or a symbol in a non-byte boundary is detected, the transmitter will also stop
transmitting.
In VPW, an active signal will always dominate a passive one, and a shorter passive symbol
will dominate a longer passive symbol. This ensures that a logic zero will dominate a logic
one, and the message with the highest priority (lowest value) will win arbitration. See 15.5.5
MESSAGE ARBITRATION for more details.
15.4.3.5
J1850 Bus Errors
The MDLC detects several types of transmit and receive errors which can occur during the
transmission of a message onto the J1850 bus.
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If the MDLC is transmitting a message and the message received contains invalid bits, or
framing symbols on non-byte boundaries, this constitutes a transmission error. When a
transmission error is detected, the MDLC will immediately cease transmitting.
If the MDLC is receiving a message and it detects an error during the message, the
message is discarded. No message with an error contained in it is passed to the CPU and
no error status information is available.
15.4.3.5.1
CRC Error
A CRC error is detected when the data bytes and CRC byte of a received message are
processed, and the CRC calculation result is not equal to $C4. The CRC code should
detect any single and 2 bit errors, as well as all 8 bit burst errors, and almost all other types
of errors.
15.4.3.5.2
Bit Format Error
A Bit Format error is detected when an abnormal (invalid) bit is detected in a message
being received from the J1850 bus. However, if the MDLC is transmitting when this
happens, it will be treated as a loss of arbitration rather than a transmitter error and the
automatic retry mechanism will apply.
15.4.3.5.3
Message Format Error
A Message Format error is detected if an EOD or EOF symbol is detected on a non-byte
boundary from the J1850 bus.
15.4.3.5.4
Bus Fault
If a bus fault occurs, the response of the MDLC will depend upon the type of bus fault.
If the bus is shorted to V , the MDLC will wait for the bus to fall to a passive state before
batt
it will attempt to transmit a message. As long as the short remains, the MDLC will never
attempt to transmit a message onto the J1850 bus.
If the bus is shorted to ground, the MDLC will see an idle bus, begin to transmit the
message, and then detect a transmission error, since the short to ground would not allow
the bus to be driven to the dominant state. The MDLC will abort that transmission and wait
for the next CPU command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the MDLC will
resume normal operation. If the bus fault is permanent, it may result in permanent loss of
communication on the J1850 bus.
15.4.3.5.5
Message Under Length Error
Any message received by the MDLC must be at least two bytes long. Since the MDLC does
not have message filtering, these two bytes could just be one data byte and a CRC byte.
Any messages received with less than the minimum number of bytes will be discarded by
the MDLC.
15.4.3.5.6
Message Over Length Error
A Message Over Length error is detected when a message being received exceeds the
maximum length allowed for a message on the J1850 bus. If the Receive Block mode
(RXBM) bit is not set, the maximum received length from SOF to the EOD is 12 bytes
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including the CRC byte. Any messages received with more than the maximum number of
bytes will be discarded by the MDLC.
15.4.3.5.7
Invalid Active Level
If the MDLC transmits an active symbol but senses that the bus remains active longer than
163 us, then the MDLC will stop transmitting. The MDLC will treat this invalid active level
just like a received Break symbol. The MDLC will try to transmit the message again after
an idle bus is detected.
15.4.3.5.8
BREAK - Break
Any MDLC transmitting at the time a BREAK is detected will treat the BREAK as if a loss
of arbitration had occurred, and halt transmission. The MDLC will then retry to transmit the
message.
If while receiving a message the MDLC detects a BREAK symbol, it will treat the BREAK
as a reception error and clear the current Rx Buffer pointer.
Table 15-3: MDLC J1850 Bus Error Summary
Error Condition
Bus short to V
MDLC Function
.
The MDLC will not transmit until the bus is idle.
BATT
Bus short to Gnd.
The MDLC will try only once to send the message.
No interrupt will be generated.
MDLC transmits
but The MDLC will abort transmission immediately. No
receives invalid bits (noise). interrupt will be generated.
MDLC receives invalid bit. The MDLC will reset the Rx Buffer pointer and wait
for the next valid SOF. No interrupt will be generated.
MDLC receives message The MDLC will reset the Rx Buffer pointer and wait
framing error. for the next valid SOF. No interrupt will be generated.
MDLC receives under length The MDLC will reset the Rx Buffer pointer and wait
or over length message. for the next valid SOF. No interrupt will be generated.
MDLC receives invalid CRC The MDLC will reset the Rx Buffer pointer and wait
for the next valid SOF. No interrupt will be generated.
MDLC receives BREAK The MDLC will reset the Rx Buffer pointer and wait
symbol
for the next valid SOF. No interrupt will be generated.
MDLC sends an EOD but The MDLC will reset the Rx Buffer pointer and try to
receives an active symbol. resend that message after an idle bus.
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15.5 MDLC MUX INTERFACE
The MUX Interface is responsible for bit encoding/decoding and digital noise filtering
between the Protocol Handler and the Physical Interface.
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
15.5.1
Rx DIGITAL FILTER
The Receiver section of the MDLC includes a digital low pass filter to remove narrow noise
pulses from the incoming message. An outline of the digital filter is shown below.
Input
Sync
Data
Latch
4-Bit Up/Down Counter
Filtered
Rx Data
from
Physical
Interface
(RxP)
Rx Data Out
d
q
up/down
= 15
= 0
s
r
q
MUX Interface Clock
Figure 15-9: MDLC Rx Digital Filter Block
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15.5.1.1
Operation
The clock for the digital filter is provided by the MUX Interface clock. At each positive edge
of the clock signal, the current state of the Receiver Physical Interface (RxP) signal is
sampled. The RxP signal state is used to determine whether the counter should increment
or decrement at the next negative edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample
is low. The counter will thus progress up towards ’15’ if, on average, the RxP signal remains
high or progress down towards ’0’ if, on average, the RxP signal remains low.
When the counter eventually reaches the value ’15’, the digital filter decides that the
condition of the RxP signal is at a stable logic level one and the Data Latch is set, causing
the Filtered Rx Data signal to become a logic level one. Furthermore, the counter is
prevented from overflowing and can only be decremented from this state.
Alternatively, should the counter eventually reach the value ’0’, the digital filter decides that
the condition of the RxP signal is at a stable logic level zero and the Data Latch is reset,
causing the Filtered Rx Data signal to become a logic level zero. Furthermore, the counter
is prevented from underflowing and can only be incremented from this state.
The Data Latch will retain its value until the counter next reaches the opposite end point,
signifying a definite transition of the RxP signal.
15.5.1.2
Performance
The performance of the digital filter is best described in the time domain rather than the
frequency domain.
If the level of the RxP signal transitions, then there will be a delay before that transition
appears at the Filtered Rx Data output signal. This delay will be between 15 and 16 clock
periods, depending on where the transition occurs with respect to the sampling points. This
’filter delay’ must be taken into account when performing message arbitration.
For example, if the frequency of the MUX Interface clock (fMDLC) is 1.0486MHz, then the
period (tMDLC) is 954ns and the maximum filter delay in the absence of noise will be
15.259us.
The effect of random noise on the RxP signal depends on the characteristics of the noise
itself. Narrow noise pulses on the RxP signal will be completely ignored if they are shorter
than the filter delay. This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition may be delayed
by an amount equal to the length of the noise burst. This is just a reflection of the
uncertainty of where the transition is truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable
symbol length will be detected by the next stage of the MDLC’s receiver as an invalid
symbol.
Noise pulses that are longer than the shortest allowable symbol length will normally be
detected as an invalid symbol or as invalid data when the frame’s CRC is checked.
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15.5.2 J1850 FRAME FORMAT
All messages transmitted on the J1850 bus are structured using the format:
Optional
E
I
F
S
O
Data
Data
Idle SOF
Data
CRC
IFR
EOF
Idle
0
1
n
D
Figure 15-10: J1850 Bus Message Format (VPW)
Each message has a maximum length of 12 bytes (excluding SOF, EOD, NB and EOF).
15.5.2.1 SOF - Start of Frame Symbol
All messages transmitted onto the J1850 bus must begin with an SOF symbol. This
indicates to any listeners on the J1850 bus the start of a new message transmission. The
SOF symbol is not used in the CRC calculation.
15.5.2.2
Data - In Message Data Bytes
The data bytes contained in the message include the message header bytes and any actual
data being transmitted to the receiving node. The MDLC can be used to transmit messages
using any of the three header formats outlined in the SAE J1850 document. However, the
MDLC does not utilize the IFR, Header type or functional/physical addressing bits defined
in the 1st byte of the 3-byte consolidated header message format. See SAE J1850 - Class
B Data Communications Network Interface, for more information about 1- and 3-byte
headers.
Messages transmitted by the MDLC onto the J1850 bus must contain at least one data
byte, and therefore can be as short as one data byte and one CRC byte. Each data byte in
the message is 8 bits in length, transmitted MSB to LSB.
15.5.2.3
CRC - Cyclical Redundancy Check Byte
This byte is used by the receiver(s) of each message to determine if any errors have
occurred during the transmission of the message. The MDLC calculates the CRC byte and
appends it onto any messages transmitted onto the J1850 bus, and also performs CRC
detection on any messages it receives from the J1850 bus.
8
4
3
2
CRC generation uses the divisor polynomial X +X +X +X +1. The remainder polynomial
is initially set to all ones, and then each byte in the message after the SOF symbol is serially
processed through the CRC generation circuitry. The one’s complement of the remainder
then becomes the 8-bit CRC byte, which is appended to the message after the data bytes,
in MSB to LSB order.
When receiving a message, the MDLC uses the same divisor polynomial. All data bytes,
excluding the SOF and EOD symbols, but including the CRC byte, are used to check the
7
6
2
CRC. If the message is error free, the remainder polynomial will equal X +X +X ($C4),
regardless of the data contained in the message. If the calculated CRC does not equal $C4,
the MDLC will recognize this as a CRC error, and will discard the message, not informing
the CPU of the failure.
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15.5.2.4
EOD - End of Data Symbol
The EOD symbol is a short passive period on the J1850 bus used to signify to any
recipients of a message that the transmission by the originator has completed.
15.5.2.5
IFR - In Frame Response Bytes
The IFR section of the J1850 message format is optional. The MDLC does not support this
option. The MDLC will not transmit an IFR under any circumstances. If an IFR is received
from another node, the MDLC will ignore this part of the message and wait for the EOF
symbol before resuming normal operation.
15.5.2.6
EOF - End of Frame Symbol
This symbol is a passive period on the J1850 bus, longer than an EOD symbol, which
signifies the end of a message. Since an EOF symbol is longer than an EOD symbol, if no
response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed.
15.5.2.7
IFS - Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus that allows proper synchronization
between nodes during continuous message transmission. The IFS symbol is transmitted
by a node following the completion of the EOF period.
When the last byte of a message has been transmitted onto the J1850 bus, and the EOF
symbol time has expired, all nodes must then wait for the IFS symbol time to expire before
transmitting an SOF, marking the beginning of another message.
However, if the MDLC is waiting for the IFS period to expire before beginning a
transmission and a rising edge is detected before the IFS time has expired, it must
internally synchronize to that edge. If a write to the MTCR register (initiate transmission)
occurred on or before 104· tMDLC from the received rising edge, then the MDLC will transmit
and arbitrate for the bus. If a CPU write to the MTCR register occurred after 104· t
from
mdlc
the detection of the rising edge, then the MDLC will not transmit, but will wait for the next
IFS period to expire before attempting to transmit the message.
A rising edge may occur during the IFS period because of varying clock tolerances and
loading of the J1850 bus, causing different nodes to observe the completion of the IFS
period at different times. Receivers must synchronize to any SOF occurring during an IFS
period to allow for individual clock tolerances.
15.5.2.8
BREAK - Break
Any MDLC transmitting at the time a BREAK is detected will treat the BREAK as if a loss
of arbitration had occurred, and halt transmission. The MDLC cannot transmit a BREAK
symbol. If while receiving a message the MDLC detects a BREAK symbol, it will treat the
BREAK as a reception error and clear any partially received message from the Rx buffer.
15.5.2.9
Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS
period. Any node sensing an idle bus condition can begin transmission immediately.
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15.5.3 J1850 VPW SYMBOLS
Variable Pulse Width Modulation (VPW) is an encoding technique in which each bit is
defined by the time between successive transitions, and by the level of the bus between
transitions, active or passive. Active and passive bits are used alternately.
Each logic one or logic zero contains a single transition, and can be at either the active or
passive level and one of two lengths, either 64 µs or 128 µs (T
at 10.4 kbps baud rate),
NOM
depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS symbols
will always be encoded at an assigned level and length. See Figure 15-11: J1850 VPW
Symbols
Active
128 µs
64 µs
64 µs
OR
OR
Passive
Logic "0"
(a)
Active
128 µs
Passive
Logic "1"
(b)
Active
200 µs
200 µs
Passive
Start of Frame
End of Data
(c)
(d)
Active
280 µs
≥ 280 µs
Passive
End of Frame
Break
(e)
(f)
Figure 15-11 : J1850 VPW Symbols
Each message will begin with an SOF symbol, an active symbol, and therefore each data
byte (including the CRC byte) will begin with a passive bit, regardless of whether it is a logic
one or a logic zero.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit
rate.
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15.5.3.1
Logic "0"
A logic zero is defined as either an active to passive transition followed by a passive period
64 µs in length, or a passive to active transition followed by an active period 128 µs in length
(Figure 15-11(a)).
15.5.3.2
Logic "1"
A logic one is defined as either an active to passive transition followed by a passive period
128 µs in length, or a passive to active transition followed by an active period 64 µs in length
(Figure 15-11(b)).
15.5.3.3
SOF - Start of Frame Symbol
The SOF symbol is defined as a passive to active transition followed by an active period
200 µs in length (Figure 15-11(c)). This allows the data bytes that follow the SOF symbol
to begin with a passive bit, regardless of whether it is a logic one or a logic zero.
15.5.3.4
EOD - End of Data Symbol
The EOD symbol is defined as an active to passive transition followed by a passive period
200 µs in length (Figure 15-11(d)).
15.5.3.5
EOF - End of Frame Symbol
The EOF symbol is defined as an active to passive transition followed by a passive period
of at least 280 µs in length (Figure 15-11(e)). If there is no IFR byte transmitted after an
EOD symbol is transmitted, after another 80 µs the EOD becomes an EOF, indicating the
completion of the message.
15.5.3.6
IFS - Inter-Frame Separation Symbol
The IFS symbol is defined as a passive period 300 µs in length. The IFS symbol contains
no transition, since when used it always follows an EOF symbol.
15.5.3.7
BREAK - Break Signal
The BREAK signal is defined as a passive to active transition followed by an active period
of at least 280 µs (Figure 15-11(f)).
15.5.4
J1850 VPW VALID/INVALID BITS & SYMBOLS
The timing tolerances for receiving data bits and symbols from the J1850 bus have been
defined to allow for variations in oscillator frequencies. In many cases the maximum time
allowed to define a data bit or symbol is equal to the minimum time allowed to define
another data bit or symbol.
Since the minimum resolution of the MDLC for determining what symbol is being received
is equal to a single period of the MUX Interface clock (tMDLC), an apparent separation in
these maximum time/minimum time concurrences equal to one cycle of tMDLC occurs.
This one clock resolution allows the MDLC to properly differentiate between the different
bits and symbols, without reducing the valid window for receiving bits and symbols from
transmitters onto the J1850 bus having varying oscillator frequencies.
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In VPW bit encoding, the tolerances for the both passive and active data bits and symbols
are defined with no gaps between definitions. For example, the maximum length of a
passive logic zero is equal to the minimum length of a passive logic one, and the maximum
length of an active logic zero is equal to the minimum length of a valid SOF symbol
200 µs
128 µs
64 µs
Active
(1) Invalid Passive
Bit
Passive
a
Active
(2) Valid Passive
Logic Zero
Passive
a
b
b
Active
(3) Valid Passive
Logic One
Passive
Active
c
c
(4) Valid EOD
Symbol
Passive
d
Figure 15-12 : J1850 VPW Passive Symbols
15.5.4.1
Invalid Passive Bit
If the passive to active transition beginning the next data bit or symbol occurs between the
active to passive transition beginning the current data bit or symbol and a, the current bit
would be invalid. See Figure 15-12(1).
15.5.4.2
Valid Passive Logic Zero
If the passive to active transition beginning the next data bit or symbol occurs between a
and b, the current bit would be considered a logic zero. See Figure 15-12(2).
15.5.4.3
Valid Passive Logic One
If the passive to active transition beginning the next data bit or symbol occurs between b
and c, the current bit would be considered a logic one. See Figure 15-12(3).
15.5.4.4
Valid EOD Symbol
If the passive to active transition beginning the next data bit or symbol occurs between c
and d, the current symbol would be considered a valid EOD symbol. See Figure 15-12(4).
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580 µs
280 µs
Active
(1) Valid EOF
Symbol
Passive
Active
a
b
(2) Valid EOF+
IFS Symbol
Passive
c
d
Figure 15-13 : J1850 VPW EOF and IFS Symbols
15.5.4.5
Valid EOF & IFS Symbol
If the passive to active transition beginning the SOF symbol of the next message occurs
between a and b, the current symbol will be considered a valid EOF symbol. If the passive
to active transition beginning the SOF symbol of the next message occurs between c and
d, the current symbol will be considered a valid EOF symbol followed by a valid IFS symbol.
All nodes must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus loading, some nodes
may recognize a valid IFS symbol before others, and immediately begin transmitting.
Therefore, anytime a node waiting to transmit detects a passive to active transition once a
valid EOF has been detected, it should immediately begin transmission, initiating the
arbitration process. See Figure 15-13(1&2).
15.5.4.6
Idle Bus
If the passive to active transition beginning the SOF symbol of the next message does not
occur before d, the bus is considered to be idle, and any node wishing to transmit a
message may do so immediately.
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280 µs
200 µs
128 µs
64 µs
(1) Invalid Active
Bit
a
a
(2) Valid Active
Logic One
b
b
(3) Valid Active
Logic Zero
c
c
(4) Valid SOF
Symbol
d
d
(5) Valid BREAK
Symbol
e
Figure 15-14 : J1850 VPW Active Symbols
Invalid Active Bit
15.5.4.7
If the active to passive transition beginning the next data bit or symbol occurs between the
passive to active transition beginning the current data bit or symbol and a, the current bit
would be invalid. See Figure 15-14(1).
15.5.4.8
Valid Active Logic One
If the active to passive transition beginning the next data bit or symbol occurs between a
and b, the current bit would be considered a logic one. See Figure 15-14(2).
15.5.4.9
Valid Active Logic Zero
If the active to passive transition beginning the next data bit or symbol occurs between b
and c, the current bit would be considered a logic zero. See Figure 15-14(3).
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15.5.4.10
Valid SOF Symbol
If the active to passive transition beginning the next data bit or symbol occurs between c
and d, the current symbol would be considered a valid SOF symbol. See Figure 15-14(4).
15.5.4.11
Valid BREAK Symbol
If the next active to passive transition does not occur until after d, the current symbol will
be considered a valid BREAK symbol. Following the BREAK symbol, an IFS period must
be observed, after which normal communication can resume on the J1805 bus. See Figure
15-14(5).
15.5.5
MESSAGE ARBITRATION
Message arbitration on the J1850 bus is accomplished in a non-destructive manner,
allowing the message with the highest priority to be transmitted, while any transmitters
which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting
again.
If the MDLC wishes to transmit onto the J1850 bus, but detects that another message is in
progress, it must wait until the bus is idle. However, if multiple nodes begin to transmit in
the same synchronization window, message arbitration will occur beginning with the first bit
after the SOF symbol and continue with each bit thereafter.
The VPW symbols and J1850 bus electrical characteristics are carefully chosen so that a
logic zero (active or passive type) will always dominate over a logic one (active or passive
type) simultaneously transmitted. Hence logic zeroes are said to be ’dominant’ and logic
ones are said to be ’recessive’. Whenever a node detects a dominant bit when it transmits
a recessive bit, it loses arbitration, and immediately stops transmitting. This is known as
’bitwise arbitration’.
"0"
"0"
"0"
"1"
"1"
"1"
"1"
"1"
"1"
"1"
Transmitter A detects
an active state on
the bus, and stops
transmitting
Active
Transmitter A
Passive
"0"
"0"
"0"
Active
Transmitter B
Transmitter B wins
arbitration and
continues
Passive
"0"
transmitting
Active
J1850 Bus
Passive
Data
Bit 2
Data
Bit 3
Data
Bit 4
Data
Bit 5
Data
Bit 1
SOF
Figure 15-15: J1850 VPW Bitwise Arbitration
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During arbitration, or even throughout the message being transmitted, when an opposite
bit is detected, transmission is immediately stopped unless it occurs on the 8th bit of a byte.
In this case the MDLC will automatically append up to two extra 1 bits and then stop
transmitting. These two extra bits will be arbitrated normally and thus will not interfere with
another message. The second 1 bit will not be sent if the first loses arbitration. If the MDLC
has lost arbitration to another valid message then the two extra ones will not corrupt the
current message. However, if the MDLC has lost arbitration due to noise on the bus, then
the two extra ones will ensure that the current message will be detected and ignored as a
noise-corrupted message.
Since a "0" dominates a "1", the message with the lowest value will have the highest
priority, and will always win arbitration, i.e. a message with priority 000 will win arbitration
over a message with priority 001. This method of arbitration will work no matter how many
bits of priority encoding are contained in the message.
If the MDLC loses arbitration during the transmission of a message, it will attempt to
retransmit as soon as a valid EOF is detected on the J1850 bus. The MDLC will attempt to
retransmit the message indefinitely, as long as messages with higher priorities continue to
win arbitration.
The only way to stop transmission retry due to loss of arbitration is to abort the transmission
by setting the Tx Abort (TXAB) bit in the MDLC Control register. This will reset the internal
Tx Buffer pointer and halt transmission.
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15.6 MDLC PHYSICAL INTERFACE
All analog functions involved in transmitting and receiving from the J1850 bus are
performed by the Physical Interface. The Physical Interface serves to buffer the incoming
messages, wave-shape the messages being transmitted, and protect the MDLC from
transients occurring on the J1850 bus.
To J1850 Bus
Physical Interface
MUX Interface
Protocol Handler
Rx/Tx
Buffers
CPU Interface
MDLC
To CPU
15.6.1
OUTLINE
The receiver analog comparator and transmitter drivers are included in the MDLC Physical
Interface and together are referred to as the "transceiver".
The transceiver provides a waveshaped 7V bus waveform in response to a timed logic
signal from the MUX Interface. The transceiver actively drives the bus high, and passively
lets an RC network pull the bus low. In order to achieve the 7V level necessary for the bus
signal, the transceiver uses a battery supply (V
) which is nominally 12V. The
BATT
transceiver also receives bus waveforms and provides the MUX Interface with unfiltered
input data
A low power mode of operation is automatically entered if the CPU executes a STOP or
WAIT instruction.
In the event that ground is lost, the transceiver senses this condition and releases the bus
by switching the LOAD pin to a high impedance instead of a low impedance to ground.The
transceiver also protects the MDLC by not passing on any standard disruptive or non-
disruptive signals seen on the bus to the rest of the MDLC.
The Physical Interface contains its own power-on reset circuit that is used to reset its
control circuitry whenever a power-on condition is detected.
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See Figure 15-16: MDLC Physical Interface Outline for an example mechanization for
interfacing the MDLC module to the J1850 multiplex bus physical layer. Although this example
mechanization is designed to provide some transient protection beyond what the MDLC
module can withstand directly, the user should ensure that their circuit design meets the
transient protection requirements of their application.
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MDLC Use
R1
C1
L1
TDK NL322522T-470J-3 (surface)
TDK SP0203-470K-7 (leaded)
1st node in system
1.5kΩ±±1%
3300pF/2700pF*
TDK NL322522T-470J-3 (surface)
TDK SP0203-470K-7 (leaded)
All other nodes
10.7kΩ±±1%
470pF/220pF*
PHYSICAL INTERFACE
Sleep/Wake
* Values account for load contributions by protection
devices
Sleep & Wake
Control
To V
Prst
DD
31.6 kΩ 1%
REXT1
REXT2
J1850 BUS
24.9 kΩ 1%
Txp
Rxp
V
CCA
Locate close to
connector
Waveshaper
Driver
L1
BUS
47µH
Both
Rx Comparator
+
-
TSMA16A(surface)
P4KA16A(leaded)
C1
R1
Keep lead lengths
to a minimum on
leaded devices
LOAD
Vref
Example
transient/ESD
protection
+12V
V
BATT
0.1µF
+5V
1N5822
P6KE30A
Voltage References &
Control
V
DD
P6KE15A
0V
0.1µF
V
SSD
Example V
transient protection
Notes:
BATT
All circuit board grounds ( ) should be tied to a single point on the circuit board.
The chassis ground ( ) should be tied to a single point on the chassis as close to the Bus connector as
possible.
The L1,C1 filter should be located as close to the Bus connector as possible.
R1, REXT1, REXT2 and decoupling capacitors should be located as close as possible to the MDLC
Transient protection circuits are optional and are only examples of how a protection scheme might be
implemented, these devices may not be sufficient for all applications and under all circumstances.
Figure 15-16 : MDLC Physical Interface Outline
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15.6.2 MUX INTERFACE SIGNALS
There are five signals which pass between the Physical Interface and the MUX Interface
section of the MDLC as shown in Figure 15-16: MDLC Physical Interface Outline.
These signals are now described.
15.6.2.1
Sleep/Wake
This input signal is used to control the power consumption of the Physical Interface
transmitter.
When driven high by the MUX interface, the transmitter will enter a low power consumption
Sleep mode. This will happen whenever the CPU executes a STOP or WAIT instruction.
The transmitter is not capable of transmitting while it is in the Sleep mode.
When driven low by the MUX interface, the transmitter will ’wake-up’ and become capable
of transmitting messages. This will happen when the MDLC enters the Run mode.
15.6.2.2
Wake
This input signal is used to exit the low power consumption mode of the Physical Interface
transmitter.
The MUX interface will drive this signal high and then low to notify the transmitter to wake
up from Sleep mode.
This will happen whenever the transmitter is in the Sleep mode and a passive to active
transition occurs on the J1850 bus, causing the RxP signal to transition from low to high.
15.6.2.3
Prst
This is the reset signal input to the Physical Interface.
This signal is normally low and the MUX Interface will drive this signal high to reset the
Physical Interface control circuits.
15.6.2.4
Txp
This input signal represents the digital serial transmit data from the MUX Interface to the
Physical Interface.
When sending a passive phase, this signal will be driven low.
When sending an active phase, this signal will be driven high.
15.6.2.5
Rxp
This output signal represents the digital serial receive data from the Physical Interface to
the MUX Interface.
When receiving an active phase, this signal will be driven high.
When receiving a passive phase this signal will be driven low.
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15.6.3
PINS
There are seven pins associated with the MDLC module. Figure 15-16: MDLC Physical
Interface Outline gives an example mechanization. A brief description of each pin follows.
15.6.3.1
REXT1, REXT2
These are external biasing resistor tie points for transmitter waveshaping and they must be
referenced to the V pin through lines which are as low impedance and low noise as
DD
possible to ensure consistent operation.
15.6.3.2 BUS
This is the half-duplex data line for J1850 communications.
15.6.3.3 LOAD
This is the switched ground connection for the J1850 bus, via an RC load.
15.6.3.4
V
BATT
This is the source for battery voltage for the MDLC. This power supply pin must be
protected against transient and fault conditions.
To protect against loss of battery, a low voltage protect circuit within the transceiver
disables drive from the BUS pin to prevent erroneous messages from being transmitted.
Nominal trip points are V
Volts on V
and V
Volts on V
.
TIVB
BATT
RIVD
CCA
15.6.3.5
V
CCA
This is the MDLC analog transceiver power supply input and is nominally 5V. This supply
must be kept as low impedance and low noise as possible. It may be supplied from a
different voltage regulator source than V
DD.
Whenever the voltage on this pin rises from zero to its nominal operating value, the
Physical Interface detects this power-on condition and resets its control circuits. Also,
whenever the voltage on this pin falls below its minimum operating value, the MDLC analog
circuitry will return to its reset state.
15.6.3.6
V
SSA2
This is the Physical Interface power supply ground. This supply must be kept as low
impedance and low noise as possible. It must be connected directly to the same grounding
point that the main MCU V uses.
ss
15.6.3.7
Decoupling
Good supply decoupling, as close as possible to the supply pins, is absolutely essential to
guarantee correct operation, minimize RFI and maximize analog performance. MDLC and
non-MDLC supply lines should be kept separate to minimize interaction. Emphasis should
be placed on keeping supply and ground line impedances as low as possible, with
preference given to ground lines if some compromise is necessitated. Ground planes and
wide, short, PCB traces can help significantly here. Decoupling capacitors should be of low
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impedance construction, with regard to high frequencies, and placed as close as is
physically possible to the supply pins of the MDLC. See Motorola application note
Designing for EMC with HCMOS Microcontrollers (AN1050) for more help on this matter.
15.7 MDLC APPLICATION NOTES
15.7.1
INITIALIZATION
The MCU will first write to the MDLC Control Register (MCR). This byte should configure
the rate select bits to configure the MUX Interface clock to its nominal value, and set the
Interrupt Enable bit if desired.
15.7.2
TRANSMITTING A MESSAGE
The MDLC is ready for loading of a new message for transmission when the TXMS bit in
the MDLC Status Register (MSR) is set to a 1, or had been set but was cleared by a
subsequent access of the MDLC Transmit Control Register (MTCR). The MCU will first load
bytes for transmission into the Tx Buffer. Once the data bytes have been loaded, the MCU
will then write the transmit count to the MTCR register. This will command the MDLC to
begin transmission on the J1850 bus at the next idle bus period. The MDLC will
automatically calculate and append a CRC to the last byte of the transmitted message.
If the IE bit was set in the MCR register an interrupt request will be generated for the receipt
of this message from the J1850 bus. The MCU should clear the interrupt by an access (read
or write) to the MTCR register. The TXMS and RXMS bits in the MSR register will be set
by the MDLC upon reception of this message. The TXMS bit is cleared by any access (read
or write) of the MTCR register. The RXMS bit is cleared by any access (read or write) of the
MDLC Receive Status Register (MRSR). The MDLC is now available to transmit another
message.
A transmitting node should verify the correct transmission of its message by waiting for the
Transmit Message Successful (TXMS) bit to be set in the MSR register. The only way to
check for incorrect transmission of a message is for the MCU to provide a time-out if the
TXMS bit is not set in a certain length of time. This is the only way to detect the
unsuccessful transmission of a message, because any received message with errors is
neither stored nor indicated as received in error by the MDLC.
15.7.3
RECEIVING A MESSAGE
When a complete message is received by the MDLC error-free from the SAE J1850 bus,
the RXMS bit in the MSR will be set. In addition, if the IE bit in the MCR is set, a CPU
interrupt request will be generated. The RXMS bit and the CPU interrupt are cleared by an
access (read or write) of the MRSR register, unless a second message has also been
received from the SAE J1850 bus and is waiting to be retrieved.
The MCU may extract received message bytes from the MDLC by reading successive Rx
Buffer locations beginning at the lowest address location of the Rx Buffer. The received
message bytes can be accessed any number of times, in any order, by the CPU. The CPU
can determine the number of bytes to read by the Receive Count indicated in the MRSR
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register. If in Block mode (RXBM bit set by MCU in MCR register) the MCU should treat the
received bytes as part of an in-progress message until the MDLC clears the RXBM bit.
Once the received data bytes of interest to the CPU have been analyzed, the MCU must
write any quantity to the MRSR register to free it for the next received message.
15.7.4
RECEIVING A MESSAGE IN BLOCK MODE
Although not a part of the SAE J1850 protocol, the MDLC does allow for a special ’Block
mode’ of operation for the receiver only. The MDLC cannot transmit Block mode messages.
As far as the MDLC is concerned, a Block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All of the other features of the frame remain
the same, including the SOF, CRC and EOD symbols.
Another node wishing to send a Block mode transmission must first inform all other nodes
on the network that this is about to happen. This is usually accomplished by sending a
special predefined message. MDLC nodes wishing to receive the message should set the
Receive Block Mode (RXBM) bits in the MDLC Control Register (MCR).
Since the MDLC only has a finite amount of received data buffering available, the
programmer must ensure that received data is moved from the Rx Buffers to the application
memory throughout the duration of the Block mode message. The MDLC aids the user by
utilizing both Rx Buffers to buffer the arriving data bytes in Block mode. As soon as one Rx
Buffer fills, the incoming data ’spills over’ into the second Rx Buffer, the Received Message
Successfully (RXMS) bit in the MDLC Status Register (MSR) will be set and a CPU interrupt
request is generated, signalling to the user that an Rx Buffer must be emptied and "given
back" in the same manner as explained for receiving normal messages. This alternate
filling of Rx Buffers gives plenty of time for one Rx Buffer to be emptied by the user, while
the other one is being filled by the MDLC.
The Rx Buffers will continue to be alternately filled and emptied until an EOD symbol, or
error, is detected. Throughout the reception of the Block mode message, the MDLC will
calculate a running CRC. When an EOD symbol is finally detected, the CRC will be
checked and, if correct, the Received Message Successfully (RXMS) bit in the MDLC
Status Register (MSR) will be set, the RXBM bit will be cleared and a CPU interrupt request
will be generated.
Should the second Rx Buffer ever fill, then it will attempt to spill over into the first Rx Buffer
which (hopefully) has been emptied in time. If not, an overflow condition is detected, both
Rx Buffer pointers are reset (discarding the data currently held in the Rx Buffers), the
RXBM bit will be cleared, and the MDLC will silently wait for the next normal J1850
message to be received. Any other errors detected during the reception of a Block mode
message (for example, invalid symbols) will result in these same actions.
MDLC nodes not wishing to receive a Block mode message can leave the RXBM bit clear,
causing all Block mode messages to be completely ignored. The next normal J1850
message to appear on the bus will be automatically received as long as it contains no
errors.
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15.7.5 MDLC STOP MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set. This is the lowest power mode that the MDLC can
enter.
A subsequent passive to active transition on the J1850 bus will cause the MDLC to ’wake
up’ and generate a non-maskable CPU interrupt request. The MDLC is not guaranteed to
correctly receive the message which woke it up since it may take some time for the MDLC
internal operating clocks to restart and stabilize.
When MDLC Stop mode is entered, the analog circuitry within the transmitter will be put
into a power conserving ’sleep’ mode. In MDLC Stop mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important that the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop mode.
If this mode is entered while the MDLC is receiving a message, the first subsequent
received edge will cause the MDLC to immediately wake up, generate a CPU interrupt
request, and wait for the MDLC internal operating clocks to restart and stabilize before
normal communication can resume. Therefore, the MDLC is not guaranteed to correctly
receive that message.
15.7.6
MDLC WAIT MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and the WCM bit in the MCR register is previously clear.
A subsequent successfully received message, including one that is in progress at the time
that this mode is entered, will cause the MDLC to ’wake up’ and generate a CPU interrupt
request if the Interrupt Enable (IE) bit in the MCR register is previously set. This results in
less of a power saving, but the MDLC is guaranteed to correctly receive the message which
woke it up since the MDLC internal operating clocks are kept running.
When MDLC Wait mode is entered, the analog circuitry within the transmitter will be put into
a power conserving ’sleep’ mode. In MDLC Wait mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop or MDLC
Wait mode.
15.7.7
CONTROLLING EXTERNAL VOLTAGE REGULATORS
If the application node contains other, off-chip, supply voltage regulators that need to be
controlled by J1850 network activity then an output port pin of the MCU must be reserved
by the programmer for use as a Power Sense (PSEN) signal. This pin will provide a logical
indication of when the MDLC is active through software.
Whenever the MCU is in the normal (Run) mode of operation, the programmer should
assert the PSEN output on the chosen port pin. The programmer should negate the PSEN
output just prior to placing the microcontroller in the Stop or Wait mode.
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When the MDLC is in the MDLC Stop or MDLC Wait mode of operation, and network
activity is sensed, a CPU interrupt request will be generated. As part of the service routine
for this interrupt, the programmer should once again assert the PSEN output. Note that
both V
and V for the MDLC must be maintained in the MDLC Stop and MDLC Wait
CCA
DD
modes of operation in order for this to work properly.
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SECTION 16
INSTRUCTION SET
The MCU has a set of 62 basic instructions. They can be divided into five different types:
register/memory, read-modify-write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. For more information on the instruction set, refer to
the M6805 Family User’s Manual (M6805UM/AD3) or the associated MC68HC05 Data
Sheet.
16.1 REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the
index register. The other operand is obtained from memory using one of the addressing
modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the following instruction list.
Function
Load A from Memory
Mnemonic
LDA
Load X from Memory
LDX
Store A in Memory
STA
Store X in Memory
STX
Add Memory to A
ADD
ADC
SUB
SBC
AND
ORA
EOR
CMP
CPX
BIT
Add Memory and Carry to A
Subtract Memory
Subtract Memory from A with Borrow
AND Memory to A
OR Memory with A
Exclusive OR Memory with A
Arithmetic Compare A with Memory
Arithmetic Compare X with Memory
Bit Test Memory with A (Logical Compare)
Jump Unconditional
JMP
JSR
Jump to Subroutine
Multiply
MUL
16.2 READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and
write the modified value back to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read-modify-write sequence since it does not modify
the value. Do not use these read-modify-write instructions on write-only locations. Refer to
the following list of instructions.
SECTION 16: INSTRUCTION SET
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Function
Mnemonic
INC
Increment
Decrement
DEC
CLR
Clear
Complement
COM
NEG
ROL
Negate (Two’s Complement)
Rotate Left Thru Carry
Rotate Right Thru Carry
Logical Shift Left
Logical Shift Right
Arithmetic Shift Right
Test for Negative or Zero
ROR
LSL
LSR
ASR
TST
16.3 BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is
performed. Branch instructions are 2-byte instructions. Refer to the following list for branch
instructions.
Function
Mnemonic
BRA
BRN
BHI
Branch Always
Branch Never
Branch if Higher
Branch if Lower or Same
Branch if Carry Clear
Branch if Higher or Same
Branch if Carry Set
BLS
BCC
BHS
BCS
BLO
BNE
BEQ
BHCC
BHCS
BPL
Branch if Lower
Branch if Not Equal
Branch if Equal
Branch if Half Carry Clear
Branch if Half Carry Set
Branch if Plus
Branch if Minus
BMI
Branch if Interrupt Mask Bit is Clear
Branch if Interrupt Mask Bit is Set
Branch if Interrupt Line is Low
Branch if Interrupt Line is High
Branch to Subroutine
BMC
BMS
BIL
BIH
BSR
16.4 BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any read/write bit that resides in the first 256
bytes of the memory space where all port registers, port DDRs, timer, timer control, and on-
chip RAM reside. An additional feature allows the software to test and branch on the state
of any bit within these 256 locations. The bit set, bit clear, and bit test and branch functions
are each implemented with a single instruction. For test and branch instructions, the value
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of the bit tested is also placed in the carry bit of the condition code register. The bit set and
bit clear instructions are also read-modify-write instructions and should not be used to
manipulate write-only locations. Refer to the following list for bit manipulation instructions.
Function
Mnemonic
Set Bit n
BSET n (n = 0. . .7)
BCLR n (n = 0. . .7)
BRSET n (n = 0. . .7)
BRCLR n (n = 0. . .7)
Clear Bit n
Branch if Bit n is Set
Branch if bit n is Clear
16.5 CONTROL INSTRUCTIONS
These instructions are register reference instructions and are used to control processor
operation during program execution. Refer to the following list for control instructions.
Function
Mnemonic
TAX
Transfer A to X
Transfer X to A
Set Carry Bit
TXA
SEC
CLC
Clear Carry Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
Software Interrupt
Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Stop
Wait
16.6 ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an
opportunity to optimize the code for all situations. The various indexed addressing modes
make it possible to locate data tables, code conversion tables, and scaling tables anywhere
in the memory space. Short indexed accesses are single byte instructions; the longest
instructions (3 bytes) permit accessing tables throughout memory. Short and long absolute
addressing is also included. One- or 2-byte direct addressing instructions access all data
bytes in most applications. Extended addressing permits jump instructions to reach all
memory.
The term “effective address” (EA) is used in describing the various addressing modes.
Effective address is defined as the address from which the argument for an instruction is
fetched or stored.
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16.6.1 IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately
following the opcode. The immediate addressing mode is used to access constants that do
not change during program execution (for example, a constant used to initialize a loop
counter).
16.6.2
DIRECT
In the direct addressing mode, the effective address of the argument is contained in a single
byte following the opcode byte. Direct addressing allows the user to directly address the
lowest 256 bytes in memory with single 2-byte instructions.
16.6.3
EXTENDED
In the extended addressing mode, the effective address of the argument is contained in the
2 bytes following the opcode byte. Instructions with extended addressing mode are capable
of referencing arguments anywhere in memory with a single 3-byte instruction. When using
the Motorola assembler, the user need not specify whether an instruction uses direct or
extended addressing. The assembler automatically selects the shortest form of the
instruction.
16.6.4
RELATIVE
The relative addressing mode is only used in branch instructions. In relative addressing,
the contents of the 8-bit signed offset byte (which is the last byte of the instruction) is added
to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from -128 to +127 from the address of
the next opcode. The programmer need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks to see that it is within the span
of the branch.
16.6.5
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective address of the argument is
contained in the 8-bit index register. This addressing mode can access the first 256
memory locations. These instructions are only 1 byte long. This mode is often used to move
a pointer through a table or to hold the address of a frequently referenced RAM or I/O
location.
16.6.6
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the unsigned byte following the opcode.
The addressing mode is useful for selecting the Kth element in an element table. With this
2-byte instruction, K would typically be in X with the address of the beginning of the table
in the instruction. As such, tables may begin anywhere within the first 256 addressable
locations and could extend as far as location 510. $1FE is the highest location that can be
accessed in this way.
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16.6.7
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the
opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except
that this 3-byte instruction allows tables to be anywhere in memory. As with direct and
extended addressing, the Motorola assembler determines the shortest form of indexed
addressing.
16.6.8
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and
the byte following the opcode specifies the direct address of the byte in which the specified
bit is to be set or cleared. Any read/write register bit in the first 256 locations of memory,
including I/O, can be selectively set or cleared with a single 2-byte instruction.
16.6.9
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit that is to be tested and its condition (set or clear), is included in the
opcode. The address of the byte to be tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third byte is added to the PC if the
specified bit is set or cleared in the specified memory location. This single 3-byte instruction
allows the program to branch based on the condition of any readable bit in the first 256
locations of memory. The span of branching is from -128 to +127 from the address of the
next opcode. The state of the tested bit is also transferred to the carry bit of the condition
code register.
16.6.10 INHERENT
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register and/or accumulator
as well as the control instructions with no other arguments are included in this mode. These
instructions are 1 byte long.
SECTION 16: INSTRUCTION SET
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SECTION 17
ELECTRICAL SPECIFICATIONS
17.1 MAXIMUM RATINGS
(Voltages referenced to V
)
SS
Rating
Symbol
Value
Unit
V
Supply Voltage
Input Voltage
V
-0.5 to +42.0
BATT
V
V
-0.3 to V +0.3
V
IN
SS
DD
Current Drain Per Pin Excluding V and V
I
25
mA
DD
SS
o
C
T
Operating Temperature Range
MC68HC05V7XX (Standard)
MC68HC05V7CXX (Extended)
T to T
A
L
H
0 to +70
-40 to +85
XX=B for SDIP, XX=FN for PLCC, XX=FU for QFP
o
Storage Temperature Range
T
-65 to +150
C
STG
Write/Erase Cycles (@ 10 ms write time & -40°C, +25°C, +85°C)
Data Retention EEPROM
10,000
10
cycles
years
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation, it is recommended that V and V
be constrained to the
IN
OUT
range V ≤ (V or V
) ≤ V . Reliability of operation is enhanced if unused inputs are
DD
SS
IN
OUT
connected to an appropriate logic voltage level (for example, either V or V ).
SS
DD
17.2 THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
Unit
Thermal Resistance
o
SDIP (56 pin)
PLCC (68 pin)
QFP (64 pin)
θ JA
θ JA
θ JA
60
50
85
C/W
C/W
C/W
o
o
SECTION 17: ELECTRICAL SPECIFICATIONS
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17.3 DC ELECTRICAL CHARACTERISTICS
(V = 5.0 Vdc ±10%, V = 0 Vdc, T = -40°C to +85°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
Output voltage
I
= 10.0 µA
V
—
—
—
0.1
—
V
Load
OL
V
V
V
-0.1
OH
DD
Output High Voltage
(I = -0.8 mA) PA0-7, PB0-7, PC0-7, PF0-3, PWM
V
-0.8
—
—
V
Load
Output Low Voltage
(I = 1.6 mA) PA0-7, PB0-7, PC0-7, PF0-3,PWM
OH
DD
V
---
—
—
0.4
V
V
Load
OL
Input High Voltage
Ports A, B, C
V
0.8×V
0.8×V
V
V
DD
DD
IH
V
BATT
IGN
BATT
Input High Voltage
V
—
—
V
V
IH
0.7×V
V
Ports D, E, F, IRQ, RESET, OSC1
DD
DD
Input Low Voltage
Ports A, B, C
V
V
0.4×V
0.4×V
V
SS
SS
DD
BATT
IL
V
IGN
Input Low Voltage
V
V
0.3×V
Ports D, E, F, IRQ, RESET, OSC1
V
—
SS
SS
V
DD
IL
0.3×V
BATT
V
Supply Current (see Notes)
DD
Run
I
---
---
---
5
3
---
mA
mA
mA
DD
Wait SPI, TIMER, A/D, PWM, COP, and LVR enabled
I
---
---
DD
Wait above modules off
Stop (Regulator disabled, LVR enabled)
I
1.2
DD
25°C
I
---
---
200
---
µA
µA
DD
0°C to +70°C (Standard)
-40°C to +85°C (Extended)
25°C (LVR disabled)
I
TBD
TBD
DD
I
---
---
TBD
100
TBD
---
µA
µA
DD
I
DD
V
Supply Current at 12V
BATT
I
---
---
---
25
TBD
TBD
TBD
µA
µA
µA
BATT
Stop Regulator disabled
I
800
250
Run Regulator disabled (Transceiver current)
BATT
I
Stop Regulator enabled (includes STOP I
, LVR disabled)
BATT
DD
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-7, PC0-7, PF0-3
±1
±1
µA
µA
I
—
—
—
—
IL
Input Current
RESET, IRQ, OSC1, TCAP, PD0-7,PE0-7, SS
I
IN
*
Capacitance
Ports (as Input or Output)
C
—
—
—
—
12
8
pF
pF
OUT
RESET, IRQ, OSC1, OSC2, TCAP, PD0-7,PE0-7, SS
C
IN
Low Voltage Reset Inhibit
V
3.5
3.6
0.1
—
—
4.2
4.5
0.3
V
V
V
LVRI
Low Voltage Reset Recover
V
LVRR
Low Voltage Reset Inhibit/Recover Hysteresis
H
0.2
LVR
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V
V
slew rate rising *
slew rate falling*
S
—
—
—
—
—
—
0.1
0.05
100
V/µs
V/µs
mV
DD
VDDR
S
DD
VDDF
POR Reset Voltage *
V
POR
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) I , Wait I : Measured using external square wave clock source to OSC1 (f = 4.2 MHz), all inputs
DD
DD
OSC
0.2 VDC from rail; no DC loads, less than 50 pF on all outputs, C = 20 pF on OSC2.
L
4. Wait, Stop I : All ports configured as inputs, V = 0.2 Vdc, V = V -0.2 Vdc.
DD
IL
IH
DD
5. Stop I measured with OSC1 = V
.
SS
DD
6. Wait I is affected linearly by the OSC2 capacitance.
DD
7. Total
* Not Tested.
17.4 REGULATOR ELECTRICAL CHARACTERISTICS
(V
= 12 Vdc ±10%, V = 0 Vdc, T = -40°C to +85°C, unless otherwise noted)
BATT
SS
A
Characteristic
Symbol
Min
Max
Units
V
1
Input Voltage
V
BATT
8
26.5
--
16
40
2,4
Maximum Input Voltage transient amplitude
V
V
V
BATTMAX
BATTDUR
2,4
Maximum Input Voltage transient duration
Output Voltage
mS
V
200
5.25
20
V
DD
4.75
-
3
Output Current
I
mA
O
Input Bias Current
IBIAS
uA
uVrms
dB
TBD
TBD
TBD
65
2
Output Noise Voltage
V
N
-
-
2
Ripple Rejection Ratio
RR
5
Input - Output Differential Voltage V
to V with V < min.
BATT
VDIFF
ISHORT
V
mA
BATT
DD
1.5*
75
-
2.5
Short Circuit Current Limit
95
2
Temperature Coefficient
T
mV/°C
mV
c
TBD
Line regulation
VLINEREG
VLOADREG
-
-
50
50
Load regulation at 20mA
mV
Notes: (All values shown reflect average measurements.)
1. Maximum voltage of 26.5V for 5 minutes only. If VBATT exceeds VBATTMAX, V
may deviate from min/max limits.
DD
2. Guaranteed by design. Not tested in productions tests.
3. This is the available current out of the V pin for off chip usage.
DD
4. This transient may be disruptive but will not be destructive.
5. Total regulator load of 20mA. Lighter load currents result in lower V
.
DIFF
* max I of 20mA at V =3.5V.
DD
DD
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17.5 CONTROL TIMING
(V = 5.0 Vdc ±10%, V = 0 Vdc, T = -40°C to +85°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Max
Units
Frequency of Operation
Crystal Oscillator Option
External Clock Source
f
f
0.1
DC
4.2
4.2
MHz
MHz
OSC
OSC
Internal Operating Frequency
Crystal Oscillator (f ÷ 2)
f
f
---
DC
2.1
2.1
MHz
MHz
OSC
OP
OP
External Clock (f
÷ 2)
OSC
Cycle Time (1 ÷ f
)
t
nS
OP
CYC
476
---
---
TBD
TBD
---
Crystal Oscillator Startup Time (Crystal Oscillator option)
Stop Recovery Startup Time (Crystal Oscillator option)
RESET Pulse Width Low (See Figure 8-1)
IRQ Interrupt Pulse width low (Edge-Triggered)
IRQ Interrupt Pulse Period (See Figure 8-1)
PA0-7, PC0-7 Interrupt Pulse Width High (Edge-Triggered)
PA0-7, PC0-7 Interrupt Pulse Period
t
t
t
OXON
CYC
t
ILCH
CYC
---
t
ns
RL
120
120
note 3
120
note 3
90
t
ILHI
nS
---
t
t
t
ILIL
IHIL
IHIH
osc1
CYC
---
t
nS
---
t
CYC
---
OSC1 Pulse Width
t
nS
---
EEPROM Programming Time per Byte
t
mS
mS
mS
mS
µS
µS
EEPGM
10
---
EEPROM Erase Time per Byte
t
EBYT
10
10
10
---
---
EEPROM Erase Time per Block
EEPROM Bulk Erase Time
t
EBLOCK
t
EBULK
---
EEPROM Programming Voltage Discharge Period
RC Oscillator Stabilization Time
t
FPV
10
5.0
t
--
RCON
16-Bit Timer
Resolution (note 2)
Input Capture Pulse Width (See Figure 11-4)
Input Capture Period
t
4.0
125
note 4
--
--
--
t
t
RESL
t
CYC
nS
t
TH, TL
t
TLTL
CYC
NOTES:
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T
H
DD
SS
A
L
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. The minimum period t
or t
should not be less than the number of cycles it takes to execute the interrupt service routine
ILIL
IHIH
plus 19 t
.
CYC
4. The minimum period t
should not be less than the number of cycles it takes to execute the capture interrupt service routine
TLTL
plus 24 t
.
CYC
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17.6 A/D CONVERTER CHARACTERISTICS
(V
= 5.0 Vdc ±10%, V
SSA1
= 0 Vdc, T = -40°C to +85°C, unless otherwise noted)
CCA
A
Characteristic
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute Accuracy
(V = 0 V, V
1
= V
)
—
LSB
Including quantization
±1 /2
REFL
REFH
DD
Conversion Range
V
V
V
V
V
V
A/D accuracy may decrease
REFL
REFH
proportionately as V
is
V
V
REFH
REFH
REFL
-0.1
DD
V
V
reduced below 4.0
REFL
REFH
100
µs
Power-up Time
—
Input Leakage
±1
±1
PD0-PD7, PE0-PE7
,V
—
—
µA
µA
V
REFL REFH
Conversion Time
(Includes Sampling Time)
32
32
T
*
AD
Monotonicity
Inherent (Within Total Error)
Hex
Zero Input Reading
Full-scale Reading
Sample Time
00
FE
12
—
01
FF
12
8
V
= 0V
IN
Hex
V
= V
IN
REFH
T
*
AD
pF
Not Tested
Input Capacitance
Analog Input Voltage
V
V
V
REFL
REFH
100
A/D On Current Stabilization Time (t
RC Oscillator Stabilization Time (t
)
µs
µs
ADON
)
5
RCON
*T
AD
= t
if clock source equals MCU.
CYC
SECTION 17: ELECTRICAL SPECIFICATIONS
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17.7 DC ELECTRICAL CHARACTERISTICS
9
(V =3.5-4.5 Vdc ±10% , V =0 Vdc, T =-40°C to +85°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
Output voltage
I
= 10.0 µA
V
—
—
—
0.1
—
V
V
Load
OL
V
V
V
-0.1
OH
DD
Output High Voltage
(I = -0.2 mA) PA0-7, PB0-7,PC0-7,PF0-3,PWM
V
-0.3
—
—
—
—
—
—
—
V
V
V
V
V
V
Load
Output Low Voltage
(I = 0.4 mA) PA0-7, PB0-7,PC0-7,PF0-3,PWM
OH
DD
V
—
0.3
Load
OL
Input High Voltage
Ports A, B, C
0.8×V
V
V
DD
IH
DD
Input High Voltage
V
Ports D, E,F, IRQ, RESET, OSC1
V
0.7XV
DD
DD
IH
Input Low Voltage
Ports A, B, C
V
SS
V
0.4XV
IL
DD
Input Low Voltage
0.3×V
Ports D, E,F, IRQ, RESET, OSC1
V
V
DD
IL
SS
V
Supply Current (see Notes)
DD
Run
I
TBD
TBD
TBD
TBD
TBD
TBD
---
---
---
mA
mA
mA
DD
Wait SPI, TIMER, A/D, PWM, COP and LVR enabled
I
DD
Wait above modules off
Stop (Regulator disabled, LVR enabled)
I
DD
25°C
I
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
---
µA
µA
µA
µA
DD
0°C to +70°C (Standard)
-40°C to +85°C (Extended)
25°C (LVR disabled)
I
TBD
TBD
---
DD
I
DD
I
DD
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-7, PC0-7, PF0-3
±±1
µA
I
—
—
OZ
Input Current
±±1
±±1
µA
µA
RESET, IRQ, OSC1, TCAP,SS
PD0-PD7,PE0-7
I
—
—
—
—
IN
I
IN
*
Capacitance
Ports (as Input or Output)
C
—
—
—
—
12
8
pF
pF
OUT
RESET, IRQ, OSC1,OSC2,TCAP,SS
C
IN
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Wait I : Only timer system active.
DD
4. Run (Operating) I , Wait I : Measured using external square wave clock source (f
DD DD osc
=4.2 MHz), all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, C =20 pF on OSC2.
L
5. Wait, Stop I : All ports configured as inputs, V =0.2 V, V =V -0.2 V.
DD
IL
IH DD
6. Stop I
7. Wait I
measured with OSC1=V
.
DD
SS
is affected linearly by the OSC2 capacitance.
DD
8. The MDLC will not operate below 4.65 volts.
* Not Tested.
MOTOROLA
Page 144
SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
17.8 CONTROL TIMING
(V =3.5-4.5 Vdc ±10%, V = 0 Vdc, T = -40°C to +85°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Max
Units
Frequency of Operation
Crystal Oscillator Option
External Clock Source
f
f
0.1
DC
4.2
4.2
MHz
MHz
OSC
OSC
Internal Operating Frequency
Crystal Oscillator (f ÷ 2)
f
f
---
DC
2.1
2.1
MHz
MHz
OSC
OP
OP
External Clock (f
÷ 2)
OSC
Cycle Time (1 ÷ f
)
t
nS
OP
CYC
476
---
---
TBD
TBD
---
Crystal Oscillator Startup Time (Crystal Oscillator option)
Stop Recovery Startup Time (Crystal Oscillator option)
RESET Pulse Width Low
t
t
t
t
OXON
CYC
CYC
t
ILCH
---
t
RL
CYC
1.5
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
t
nS
ILIH
120
note 3
120
note 3
90
---
t
t
t
ILIL
IHIL
IHIH
osc1
CYC
---
PA0-7, PC0-7 Interrupt Pulse Width High (Edge-Triggered)
PA0-7, PC0-7 Interrupt Pulse Period
OSC1 Pulse Width
t
nS
---
t
CYC
---
t
nS
---
EEPROM Programming Time per Byte
EEPROM Erase Time per Byte
t
mS
mS
mS
mS
µS
µs
EEPGM
15
---
t
EBYT
15
---
EEPROM Erase Time per Block
t
EBLOCK
15
---
EEPROM Bulk Erase Time
t
EBULK
15
---
EEPROM Programming Voltage Discharge Period
RC Oscillator Stabilization Time
t
FPV
10
5.0
t
--
RCON
16-Bit Timer
Resolution (note 2)
Input Capture Pulse Width (See Figure 11-4)
Input Capture Period
t
4.0
250
note 4
--
--
--
t
t
RESL
t
CYC
nS
t
TH, TL
t
TLTL
CYC
NOTES:
1. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
2. The minimum period t
or t
should not be less than the number of cycles it takes to execute the interrupt service routine
ILIL
IHIH
plus 19 t
.
CYC
3. The minimum period t
should not be less than the number of cycles it takes to execute the capture interrupt service routine
TLTL
plus 24 t
.
CYC
SECTION 17: ELECTRICAL SPECIFICATIONS
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
17.9 LVR TIMING DIAGRAM
t
t
VDDF = V /S
VDDR= V /S
DD VDDR
DD VDDF
V
V
LVRI
LVRR
V
DD
Internal LVR
Reset Pin
MOTOROLA
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SECTION 17: ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
MC68HC05V7 Specification Rev. 1.0
17.10 SPI TIMING
SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
SERIAL PERIPHERAL INTERFACE (SPI) TIMING
(V = 5.0 Vdc ±10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
4.2
fOP
MHz
1
2
3
4
5
6
7
8
9
Cycle Time
Master
Slave
tCYC(M)
tCYC(S)
2.0
240
—
—
tCYC
ns
Enable Lead Time
Master
Slave
tLEAD(M)
*
—
—
ns
ns
t
lead(s)
240
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
*
—
—
ns
ns
240
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
ns
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
ns
Access Time (Time to Data Active from High-
Impedance State)
Slave
tA
0
120
ns
Disable Time (Hold Time to High-Impedance State)
Slave
tDIS
tV(S)
tHO
—
—
240
240
ns
ns
10
11
12
Data Valid (After Enable Edge)**
Data Hold Time (Output) (After Enable Edge)
0
—
ns
Rise Time (20% V to 70% V , C =200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
DD
DD
L
tRM
tRS
—
—
100
2.0
ns
us
13
Fall Time (70% V to 20% V , C =200 pF)
DD DD L
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
us
* Signal production depends on software.
** Assumes 200 pF load on all SPI pins.
MOTOROLA
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SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
SS
(INPUT)
SS is Held High on Master
12
13
13
12
5
SCK (CPOL=0)
(OUTPUT)
SEE
NOTE
4
5
1
SCK (CPOL=1)
(OUTPUT)
SEE
NOTE
4
7
6
MISO
MSB IN
BIT 6 --- 1
11
LSB IN
(INPUT)
11 (ref)
12
10
MASTER LSB OUT
10 (ref)
MOSI
(OUTPUT)
BIT 6 --- 1
MASTER MSB OUT
13
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.
Figure 17-1: SPI MASTER TIMING (CPHA = 0)
SS
(INPUT)
SS is Held High on Master
13
12
SCK (CPOL=0)
(OUTPUT)
5
SEE
NOTE
4
1
5
SCK (CPOL=1)
(OUTPUT)
SEE
NOTE
13
4
12
7
6
MISO
MSB IN
BIT 6 --- 1
11
LSB IN
10
MASTER LSB OUT
(INPUT)
11 (ref)
10 (ref)
MOSI
(OUTPUT)
BIT 6 --- 1
MASTER MSB OUT
13
12
NOTE: This last clock edge is generated internally but is not seen at the SCK pin.
Figure 17-2: SPI MASTER TIMING (CPHA = 1)
SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
SS
(INPUT)
13
12
13
2
5
SCK (CPOL=0)
(INPUT)
4
1
5
SCK (CPOL=1)
(INPUT)
2
4
12
8
9
SEE
NOTE
MISO
(OUTPUT)
BIT 6 --- 1
11
SLAVE
6
MSB OUT
7
SLAVE LSB OUT
11
10
MOSI
(INPUT)
MSB IN
LSB IN
BIT 6 --- 1
NOTE: Not defined but normally LSB of character previously transmitted.
Figure 17-3: SPI SLAVE TIMING (CPHA = 0)
SS
(INPUT)
12
13
13
5
4
SCK (CPOL=0)
(INPUT)
4
5
1
SCK (CPOL=1)
(INPUT)
3
12
2
10
8
9
SEE
NOTE
BIT 6 --- 1
SLAVE LSB OUT
LSB IN
MISO
SLAVE MSB OUT
(OUTPUT)
11
10
7
6
MOSI
(INPUT)
MSB IN
BIT 6 --- 1
NOTE: Not defined but normally LSB of character previously transmitted.
Figure 17-4: SPI SLAVE TIMING (CPHA = 1)
MOTOROLA
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SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
17.11 MDLC ELECTRICAL SPECIFICATIONS
17.11.1 ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to V
unless otherwise indicated.)
SSA2
Rating
Symbol
Min.
Typ.
Max.
Unit
Battery Voltage (V
)
V
-0.3
12.0
16.0
V
BATT
BATT
Reference Supply Voltage (V
Bus Voltage (BUS)
)
V
-0.3
-2.0
-2.0
--
5.0
0 to 7.0
—
7.0
18.0
+24.0
10.0
V
V
V
V
CCA
CCA
BUS
V
Transient Voltage (V
, BUS, TBD max. time)
V
TRAN
BATT
Bus Voltage with respect to V
V
--
BATT
BUS
17.11.2 OPERATING CONDITIONS
(Voltages referenced to V
)
SSA2
Rating
) for proper MDLC operation
Symbol
Min.
Typ.
Max.
Unit
Battery Voltage (V
V
9.0
12.0
16.0
V
BATT
BATT
BATT
BATT
Battery Supply Current (Run)
Battery Supply Current (Stop)
I
I
—
—
5
5
50
50
mA
µA
V
Reference Supply Voltage (V
)
V
4.75
—
5.00
0.5
40
5.25
2
CCA
CCA
CCA
CCA
Reference Supply Current (Run)
Reference Supply Current (Stop)
I
I
mA
µA
—
50
17.11.3 TRANSMITTER D.C. ELECTRICAL CHARACTERISTICS
(Total network Bus to V
resistance = 245Ω to 15kΩ,
ssa2
V
= 9 to 16V, V
= 5.0V ±5%, V
= 0V, T = -40°C to +8°C, unless otherwise noted)
SSA2 A
BATT
CCA
Characteristic
Symbol
Min.
Max.
Unit
Output High Voltage (BUS)
Output Low Voltage (BUS)
V
6.25
8.0
V
V
OH
V
0
1.5
OL
Output Current (BUS, Loss of V
8V)
or V
, VOUT = 0V, VIN = 0 to
I
—
±1
mA
BATT
SSA2
OUT
Output Current (BUS, Tx = passive, VIN = 12V)
Output Current (BUS, Tx = active, VIN = 0V)
I
I
—
—
-200
200
7.5
mA
mA
V
OUT
OUT
Low voltage inhibit of transmitter for V
Low voltage inhibit of transmitter for V
V
6.0
4.5
BATT
DD
TIVB
RIVD
V
4.75
V
SECTION 17: ELECTRICAL SPECIFICATIONS
MOTOROLA
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MC68HC05V7 Specification Rev. 1.0
17.11.4 TRANSMITTER A.C. ELECTRICAL CHARACTERISTICS
(V
= 9 to 16V, V
= 5.0V ±5%, V
= 0V, T = -40°C to +85∞∞°C, unless otherwise noted)
SSA A
BATT
CCA
Characteristic
Number
Symbol
Min.
Typ.
Max.
Unit
Transmitter Rise Time (REXT1 = 31.6kΩ, REXT2 = 24.9kΩ)
Transmitter Fall Time (REXT1 = 31.6kΩ, REXT2 = 24.9kΩ)
1
t
13.0
14.5
16.0
µs
R
2
t
13.0
14.5
16.0
µs
F
1
2
VOH
6.25 V
BUS
2 V
VOL
0 V
Figure 17-5: Transmitter A.C. Electrical Characteristics
17.11.5 RECEIVER D.C. ELECTRICAL CHARACTERISTICS
(V
= 9 to 16V, V
= 5.0V ±5%, V
= 0 V, T = -40°C to +85°C, unless otherwise noted)
SSA2 A
BATT
CCA
Characteristic
Symbol
Min.
Max.
Unit
Input High Voltage (BUS)
Input Low Voltage (BUS)
V
4.25
—
V
IH
V
—
—
3.5
V
IL
Input Current (BUS, Normal operation, Tx = passive, VIN = 0 to 8V)
I
±10
µA
IN
17.11.6 TRANSMITTER VPW SYMBOL TIMINGS
(f
= 1.048576 MHz, V
= 12V, V
= 5.0V, V
= 0V, T = 25°C, unless otherwise noted)
BATT
CCA
SSA2 A
MDLC
Characteristic
Number
Symbol
Min.
Typ.
Max.
Unit
Passive logic 0
Passive logic 1
Active logic 0
10
T
62.0
64.0
66.0
µs
µs
µs
µs
µs
tvp1
11
12
13
14
T
126.0
126.0
62.0
128.0
128.0
64.0
130.0
130.0
66.0
tvp2
T
tva1
Active logic 1
T
tva2
Start of Frame (SOF)
T
198.0
200.0
202.0
tva3
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SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
Characteristic
End of Data (EOD)
Number
Symbol
Min.
Typ.
Max.
Unit
15
T
198.0
200.0
202.0
µs
tvp3
End of Frame
16
17
T
278.0
298.0
280.0
300.0
282.0
302.0
µs
µs
tv4
Inter-Frame Separator (IFS)
T
tv6
17.11.7 RECEIVER VPW SYMBOL TIMINGS
(f
= 1.048576 MHz, V
=12V, V
= 5.0V, V
= 0 V, T = 25°C, unless otherwise noted)
BATT
CCA
SSA2 A
MDLC
Characteristic
Number
Symbol
Min.
Typ.
Max.
Unit
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start of Frame (SOF)
End of Data (EOD)
End of Frame
Break
10
T
T
T
T
T
T
34.0
64.0
96.0
µs
rvp1
11
12
13
14
15
16
18
96.0
96.0
128.0
128.0
64.0
163.0
163.0
96.0
µs
µs
µs
µs
µs
µs
µs
rvp2
rva1
rva2
rva3
rvp3
34.0
163.0
163.0
239.0
239.0
200.0
200.0
280.0
800.0
239.0
239.0
320.0
—
T
rv4
rv7
T
Note: The receiver symbol timing boundaries are subject to an uncertainty of ± 1 TMDLC µs due to sampling considerations.
SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
14
10
12
SOF
"0"
"0"
13
11
15
"1"
"1"
"0"
EOD
16
17
IFS
EOF
18
BRK
Figure 17-6: Variable Pulse Width Modulation (VPW) Symbol Timings
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SECTION 17: ELECTRICAL SPECIFICATIONS
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MC68HC05V7 Specification Rev. 1.0
SECTION 18
05V7 BEHAVIOR DURING EMULATION
This section covers the functions of the MCU that behave differently during emulation using
either the 705V8/05V7 EVS or MMDS emulation systems. Since the 705V8/05V7 device
itself is used in the emulator system and operates in TEST mode, some extra software
operations must be performed to make the device behave as it will in the users application
(USER mode). The circuits which require special treatment are described in the sections
that follow.
18.1 COP
A value of $04 should be written to location $003F to enable the COP circuitry. The COP
circuit is defaulted off to allow ease of factory testing. It should be noted that enabling the
COP with this bit will enable the COP regardless of the state of the COPEN mask option.
18.2 MDLC
The MDLC requires bit 2 and 3 to be set in the MDLC Control Register ($0E) to allow normal
operation of the MDLC. If these two bits are not set during emulation the MDLC will not
transmit or receive.
18.3 REGULATOR
The voltage regulator should not be enabled in the device used in the top board of the
emulator system. This may result in a supply voltage contention and may overheat and
damage the emulator system.
SECTION 18: 05V7 BEHAVIOR DURING EMULATION
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MC68HC05V7 Specification Rev. 1.0
MOTOROLA
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SECTION 18: 05V7 BEHAVIOR DURING EMULATION
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MOTOROLA
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