MC68HSC05C4ACFN [NXP]
8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44;
| 型号： | MC68HSC05C4ACFN |
| 厂家： | 
NXP |
| 描述： | 8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44 时钟 外围集成电路 |
| 文件： | 总156页 (文件大小：711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
HC05C4AGRS/D
REV. 4.0
MC68HC05C4A
MC68HCL05C4A
MC68HSC05C4A
Ge ne ra l Re le a se Sp e c ific a tion
Aug ust 5, 1997
CSIC Syste m De sig n Gro up
Austin, Te xa s
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Ge ne ra l Re le a se Sp e c ific a tion
© Motorola, Inc. 1997
2
MC68HC05C4A — Rev. 4.0
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
List of Se c tions
Section 1. General Description . . . . . . . . . . . . . .15
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . .25
Section 3. Central Processor Unit (CPU) . . . . . .31
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . .35
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . .41
Section 6. Low-Power Modes . . . . . . . . . . . . . . .45
Section 7. Input/Output (I/O) Ports . . . . . . . . . . .49
Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 9. Serial Communications
Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . .63
Section 10. Serial Peripheral Interface (SPI) . . .81
Section 11. Operating Modes. . . . . . . . . . . . . . . .91
Section 12. Instruction Set. . . . . . . . . . . . . . . . . .95
Section 13. Electrical Specifications. . . . . . . . .113
Section 14. Mechanical Specifications . . . . . . .131
Section 15. Ordering Information . . . . . . . . . . .135
Appendix A. MC68HCL05C4A . . . . . . . . . . . . . .141
Appendix B. MC68HSC05C4A . . . . . . . . . . . . . .145
Appendix C. M68HC05Cx Family
Feature Comparisons . . . . . . . . . . . . . . .153
MC68HC05C4A — Rev. 4.0
General Release Specification
List of Sections
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List of Se c tions
General Release Specification
4
MC68HC05C4A — Rev. 4.0
List of Sections
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Ta b le of Conte nts
Section 1. General Description
1.1
1.2
1.3
1.4
Contents ...................................................................................15
Introduction...............................................................................15
Features....................................................................................16
Mask Options............................................................................18
Functional Pin Description........................................................18
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
V
and V ........................................................................22
DD SS
IRQ......................................................................................22
OSC1 and OSC2.................................................................22
RESET ................................................................................22
TCAP...................................................................................22
TCMP ..................................................................................22
Port A (PA0–PA7) ...............................................................23
Port B (PB0–PB7) ...............................................................23
Port C (PC0–PC7)...............................................................23
Port D (PD0–PD5 and PD7)................................................23
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents ...................................................................................25
Introduction...............................................................................25
Read-Only Memory (ROM).......................................................25
ROM Security Feature..............................................................26
Random-Access Memory (RAM)..............................................26
Section 3. Central Processor Unit (CPU)
3.1
3.2
3.3
3.3.1
3.3.2
Contents ...................................................................................31
Introduction...............................................................................31
CPU Registers..........................................................................31
Accumulator ........................................................................32
Index Register .....................................................................32
MC68HC05C4A — Rev. 4.0
General Release Specification
Table of Contents
5
Ta b le of Conte nts
3.3.3
3.3.4
3.3.5
Program Counter................................................................ 33
Stack Pointer ...................................................................... 33
Condition Code Register .................................................... 33
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Contents................................................................................... 35
Introduction .............................................................................. 35
Hardware Controlled Interrupt Sequence ................................ 37
Software Interrupt (SWI) .......................................................... 37
External Interrupt (IRQ)............................................................ 39
Timer Interrupt ......................................................................... 39
Serial Communications Interrupt (SCI) .................................... 39
Serial Peripheral Interrupt (SPI)............................................... 40
Section 5. Resets
5.1
5.2
5.3
5.4
Contents................................................................................... 41
Introduction .............................................................................. 41
Power-On Reset (POR) ........................................................... 42
RESET Pin............................................................................... 42
Computer Operating Properly (COP) Reset ............................ 42
Resetting the COP.............................................................. 42
COP During Wait Mode...................................................... 43
COP During Stop Mode...................................................... 43
COP During Self-Check Mode............................................ 43
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Section 6. Low-Power Modes
6.1
6.2
6.3
6.4
6.5
Contents................................................................................... 45
Introduction .............................................................................. 45
Stop Mode................................................................................ 46
Stop Recovery ......................................................................... 47
Wait Mode................................................................................ 47
Section 7. Input/Output (I/O) Ports
7.1
7.2
7.3
7.4
Contents................................................................................... 49
Introduction .............................................................................. 49
Port A....................................................................................... 49
Port B....................................................................................... 50
General Release Specification
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MC68HC05C4A — Rev. 4.0
Table of Contents
Table of Contents
7.5
7.6
7.7
Port C........................................................................................50
Port D........................................................................................51
Input/Output Programming .......................................................51
Section 8. Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Contents ...................................................................................53
Introduction...............................................................................53
Counter.....................................................................................55
Output Compare Register.........................................................56
Input Capture Register..............................................................57
Timer Control Register..............................................................58
Timer Status Register...............................................................60
Timer During Wait Mode...........................................................61
Timer During Stop Mode...........................................................61
Section 9. Serial Communications Interface (SCI)
Contents ...................................................................................63
Introduction...............................................................................63
Features....................................................................................64
SCI Data Format.......................................................................64
SCI Operation...........................................................................65
Transmitter ..........................................................................65
Receiver ..............................................................................68
SCI I/O Registers......................................................................71
SCI Data Register ...............................................................71
SCI Control Register 1 ........................................................72
SCI Control Register 2 ........................................................74
SCI Status Register.............................................................76
Baud Rate Register.............................................................78
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
Section 10. Serial Peripheral Interface (SPI)
10.1 Contents ...................................................................................81
10.2 Introduction...............................................................................81
10.3 Features....................................................................................82
10.4 SPI Signal Description..............................................................82
10.4.1
10.4.2
Master In Slave Out (MISO)................................................82
Master Out Slave In (MOSI)................................................82
MC68HC05C4A — Rev. 4.0
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Ta b le of Conte nts
10.4.3
10.4.4
Serial Clock (SCK).............................................................. 83
Slave Select (SS) ............................................................... 84
10.5 Functional Description ............................................................. 84
10.6 SPI Registers........................................................................... 86
10.6.1
10.6.2
10.6.3
Serial Peripheral Control Register...................................... 87
Serial Peripheral Status Register ....................................... 88
Serial Peripheral Data I/O Register .................................... 90
Section 11. Operating Modes
11.1 Contents................................................................................... 91
11.2 Introduction .............................................................................. 91
11.3 User Mode ............................................................................... 91
11.4 Self-Check Mode ..................................................................... 92
11.4.1
11.4.2
Self-Check Tests ................................................................ 92
Self-Check Results............................................................. 93
Section 12. Instruction Set
12.1 Contents................................................................................... 95
12.2 Introduction .............................................................................. 96
12.3 Addressing Modes ................................................................... 96
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
Inherent .............................................................................. 97
Immediate........................................................................... 97
Direct .................................................................................. 97
Extended ............................................................................ 97
Indexed, No Offset.............................................................. 98
Indexed, 8-Bit Offset........................................................... 98
Indexed,16-Bit Offset.......................................................... 98
Relative............................................................................... 99
12.4 Instruction Types...................................................................... 99
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
Register/Memory Instructions........................................... 100
Read-Modify-Write Instructions ........................................ 101
Jump/Branch Instructions................................................. 102
Bit Manipulation Instructions............................................. 104
Control Instructions........................................................... 105
12.5 Instruction Set Summary........................................................ 106
12.6 Opcode Map .......................................................................... 111
General Release Specification
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MC68HC05C4A — Rev. 4.0
Table of Contents
Table of Contents
Section 13. Electrical Specifications
13.1 Contents .................................................................................113
13.2 Introduction.............................................................................113
13.3 Maximum Ratings...................................................................114
13.4 Operating Temperature Range...............................................115
13.5 Thermal Characteristics..........................................................115
13.6 Power Considerations.............................................................116
13.7 5.0 V DC Electrical Characteristics.........................................118
13.8 3.3 V DC Electrical Characteristics.........................................119
13.9 5.0 V Control Timing...............................................................122
13.10 3.3 V Control Timing...............................................................123
13.11 5.0 V Serial Peripheral Interface Timing.................................126
13.12 3.3 V Serial Peripheral Interface Timing.................................127
Section 14. Mechanical Specifications
14.1 Contents .................................................................................131
14.2 Introduction.............................................................................131
14.3 40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03)....................................................................132
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP)
Package (Case 858-01).....................................................132
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02)....................................................................133
14.6 44-Lead Quad Flat Pack (QFP)
(Case 824A-01) .................................................................134
Section 15. Ordering Information
15.1 Contents .................................................................................135
15.2 Introduction.............................................................................135
15.3 MCU Ordering Forms .............................................................135
15.4 Application Program Media.....................................................136
15.5 ROM Program Verification......................................................137
15.6 ROM Verification Units (RVUs)...............................................138
15.7 MC Order Numbers ................................................................139
MC68HC05C4A — Rev. 4.0
General Release Specification
Table of Contents
9
Ta b le of Conte nts
Appendix A. MC68HCL05C4A
A.1 Contents................................................................................. 141
A.2 Introduction ............................................................................ 141
A.3 Low-Power Operating Temperature Range........................... 141
A.4 2.5–3.6 V DC Electrical Characteristics................................. 142
A.5 1.8–2.4 V DC Electrical Characteristics................................. 142
A.6 Low-Power Supply Current.................................................... 143
Appendix B. MC68HSC05C4A
B.1 Contents................................................................................. 145
B.2 Introduction ............................................................................ 145
B.3 High-Speed Operating Temperature Range.......................... 146
B.4 4.5 –5.5 V High-Speed Supply Currents................................ 147
B.5 4.5–5.5 V High-Speed Control Timing ................................... 148
B.6 2.4–3.6 V High-Speed Control Timing ................................... 148
B.7 4.5–5.5 V High-Speed SPI Timing......................................... 150
B.8 2.4–3.6 V High-Speed SPI Timing......................................... 151
Appendix C. M68HC05Cx Family
Feature Comparisons
C.1 Contents................................................................................. 153
C.2 Introduction ............................................................................ 153
Table C-1. M68HC05Cx Feature Comparison ...................... 154
General Release Specification
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MC68HC05C4A — Rev. 4.0
Table of Contents
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
List of Fig ure s
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
40-Pin Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . .19
42-Pin Plastic Shrink Dual In-Line Package. . . . . . . . . . . . .20
44-Lead Plastic Leaded Chip Carrier . . . . . . . . . . . . . . . . . .21
44-Lead Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6-1
6-2
Stop/Wait Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .47
7-1
7-2
Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8-1
8-2
8-3
8-4
8-5
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
Input Capture Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .58
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .60
9-1
9-2
9-3
SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
SCI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
MC68HC05C4A — Rev. 4.0
General Release Specification
List of Figures
11
List of Fig ure s
Figure
Title
Page
9-4
9-5
9-6
9-7
9-8
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . .71
SCI Control Register (SCCR1). . . . . . . . . . . . . . . . . . . . . . .72
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . .74
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . .76
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . .78
10-1
10-2
10-3
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .83
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . .85
Serial Peripheral Interface
Master-Slave Interconnection . . . . . . . . . . . . . . . . . . . . .86
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . .87
SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . .88
10-4
10-5
11-1
11-2
User Mode Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Self-Check Circuit Schematic. . . . . . . . . . . . . . . . . . . . . . . .94
13-1
13-2
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Maximum Supply Current Versus Internal
Clock Frequency, V = 5.5 V . . . . . . . . . . . . . . . . . . .120
DD
13-3
Maximum Supply Current Versus Internal
Clock Frequency, V = 3.6 V . . . . . . . . . . . . . . . . . . .121
DD
13-4
13-5
13-6
13-7
13-8
13-9
13-10
TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . .123
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .124
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
STOP Recovery Timing Diagram. . . . . . . . . . . . . . . . . . . .125
Power-On Reset Timing Diagram . . . . . . . . . . . . . . . . . . .125
SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .128
SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .129
General Release Specification
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MC68HC05C4A — Rev. 4.0
List of Figures
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
List of Ta b le s
Table
4-1
Title
Page
Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . .36
I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7-1
9-1
9-2
9-3
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . .79
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . . . .80
10-1 Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . . . .88
11-1 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11-2 Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . . . . . .93
12-1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .100
12-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .101
12-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .103
12-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104
12-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
12-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
C-1 M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . .154
MC68HC05C4A — Rev. 4.0
General Release Specification
List of Tables
13
List of Ta b le s
General Release Specification
14
MC68HC05C4A — Rev. 4.0
List of Tables
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
Introduction...............................................................................15
Features....................................................................................16
Mask Options............................................................................18
Functional Pin Description........................................................18
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
V
and V ........................................................................22
DD SS
IRQ......................................................................................22
OSC1 and OSC2.................................................................22
RESET ................................................................................22
TCAP...................................................................................22
TCMP ..................................................................................22
Port A (PA0–PA7) ...............................................................23
Port B (PB0–PB7) ...............................................................23
Port C (PC0–PC7)...............................................................23
Port D (PD0–PD5 and PD7)................................................23
1.2 Introd uc tion
The MC68HC05C4A is an enhanced version of the MC68HC05C4. It
includes keyboard scanning logic, a high-current pin, a COP watchdog
timer, and read-only memory (ROM) security.
MC68HC05C4A — Rev. 4.0
General Release Specification
General Description
15
Ge ne ra l De sc rip tion
1.3 Fe a ture s
• M68HC05 Core
• Single 3.0- to 5.5-Volt Supply
• Available Packages:
– 40-Pin Dual In-Line (DIP)
– 42-Pin Plastic Shrink Dual In-Line (SDIP)
– 44-Lead Plastic Leaded Chip Carrier (PLCC)
– 44-Lead Quad Flat Pack (QFP)
• On-Chip Oscillator for Crystal/Ceramic Resonator
• Fully Static Operation
• 4160 Bytes of User ROM
• ROM Security Feature
• 176 Bytes of On-Chip Random-Access Memory (RAM)
• Asynchronous Serial Communications Interface (SCI) System
• Synchronous Serial Peripheral Interface (SPI) System
• 16-Bit Capture/Compare Timer System
• Computer Operating Properly (COP) Watchdog Timer
• 24 Bidirectional Input/Output (I/O) Lines
• Seven Input-Only Lines
• User Mode
• Self-Check Mode
• Power-Saving Stop and Wait Modes
• High Current Sink and Source on One Port Pin (PC7)
• Mask Selectable External Interrupt Sensitivity
• Mask Programmable Keyscan Logic
General Release Specification
16
MC68HC05C4A — Rev. 4.0
General Description
General Description
Features
PA0
PA1
PA2
PA3
PA4
USER ROM AND USER VECTORS — 4160 BYTES
P
SELF-CHECK ROM — 240 BYTES
SRAM — 176 BYTES
PA5
PA6
PA7
D
PB0*
PB1*
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
IRQ
RESET
CPU
ALU
CONTROL
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7✝
INDEX REGISTER
0
0
0
0
0
0
1
1
STACK POINTER
PROGRAM COUNTER
0
0
1
1
I
Z
N
C
1
H
CONDITION CODE REGISTER
OSC2
OSC1
÷ 2
OSCILLATOR
PD7
PORT D
SCI
RDI(PD0)
TDO(PD1)
MISO(PD2)
MOSI(PD3)
SCK(PD4)
SS(PD5)
COP
SYSTEM
BAUD RATE
GENERATOR
V
DD
SPI
POWER
V
SS
BAUD RATE
GENERATOR
TCMP
TCAP
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
* Port B pins also function as external interrupts.
✝ PC7 has a high current sink and source capability.
Figure 1-1. Block Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
17
General Description
Ge ne ra l De sc rip tion
1.4 Ma sk Op tions
Eight mask options are available to select the pullup/interrupts on port B
on a pin-by-pin basis.
There are also four mask options for:
1. IRQ, edge-sensitive only or edge- and level-sensitive
2. CLOCK, crystal or RC
3. COP, enable or disable
4. STOP, enable or disable
1.5 Func tiona l Pin De sc rip tion
The MC68HC05C4A is available in a 40-pin DIP (see Figure 1-2), 42-pin
SDIP (see Figure 1-3), 44-pin PLCC (see Figure 1-2), and 44-pin QFP
(see Figure 1-5). The following paragraphs describe the general function
of each pin.
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, resistance, capacitance, time, or frequency specified in the
following paragraphs will refer to the nominal values. The exact values
and their tolerance or limits are specified in Section 13. Electrical
Specifications.
General Release Specification
18
MC68HC05C4A — Rev. 4.0
General Description
General Description
Functional Pin Description
1
40
39
38
37
36
35
34
V
DD
RESET
IRQ
2
OSC1
OSC2
TCAP
3
NC*
PA7
4
5
PD7
PA6
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PA5
7
PA4
8
33
32
PA3
9
PA2
PA1
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC1
PC2
PC3
PC4
17
18
PC5
PC6
19
20
PB7
V
21
PC7
SS
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD
.
Figure 1-2. 40-Pin Dual In-Line Package
MC68HC05C4A — Rev. 4.0
General Release Specification
19
General Description
Ge ne ra l De sc rip tion
RESET
IRQ
NC*
PA7
1
2
3
4
5
6
7
8
9
42 VDD
41 OSC1
40 OSC2
39 TCAP
38 PD7
PA6
PA5
37 TCMP
36 PD5/SS
35 PD4/SCK
34 PD3/MOSI
33 PD2/MISO
32 PD1/TDO
31 PD0/RDI
30 PC0
PA4
PA3
PA2
PA1 10
PA0 11
PB0 12
PB1 13
PB2 14
PB3 15
NC 16
29 PC1
28 PC2
27 NC
PB4 17
PB5 18
PB6 19
26 PC3
25 PC4
24 PC5
20
23 PC6
PB7
VSS 21
22 PC7
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD
.
Figure 1-3. 42-Pin Plastic Shrink Dual In-Line Package
General Release Specification
20
MC68HC05C4A — Rev. 4.0
General Description
General Description
Functional Pin Description
T
6
7
D
A
A
C
C
R
R
V
O
O
T
C
6
5
4
3
1
2
1
4
3
2
0
39
PD7
PA5
PA4
PA3
7
8
9
38 TCMP
PD5/SS
37
PD4/SCK
36
PA2 10
PD3/MOSI
35
11
12
13
14
PA1
PA0
PB0
PB1
PD2/MISO
PD1/TDO
34
33
32 PD0/RDI
31 PC0
PB2 15
16
17
PB3
PB4
PC1
30
29 PC2
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD
.
Figure 1-4. 44-Lead Plastic Leaded Chip Carrier
33 32 31 30 29 28 27 26 25 24 23
PD7
TCAP
OSC2
OSC1
VDD
34
35
36
37
38
39
40
41
42
43
22 NC
21 PC4
20 PC5
19 PC6
18 PC7
17 VSS
16 NC
15 PB7
14 PB6
13 PB5
12 PB4
NC
NC
RESET
IRQ
NC*
44
PA7
1
2
3
4
5
6
7
8
9 10 11
* If MC68HC705C4A OTPs are to be used in the same application,
this pin should be tied to VDD
.
Figure 1-5. 44-Lead Quad Flat Pack
MC68HC05C4A — Rev. 4.0
General Release Specification
21
General Description
Ge ne ra l De sc rip tion
1.5.1 V a nd V
DD
SS
Power is supplied to the microcontroller using these two pins. V is the
DD
positive supply and V is ground.
SS
1.5.2 IRQ
This pin has a mask selectable option that provides two different choices
of interrupt triggering sensitivity. The IRQ pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. Refer to
Section 4. Interrupts for more detail.
1.5.3 OSC1 a nd OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal, a ceramic resonator, a resistor/capacitor combination, or an
external signal connects to these pins, providing a system clock. The
internal bus rate is one-half the external oscillator frequency.
1.5.4 RESET
1.5.5 TCAP
1.5.6 TCMP
This active low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity.
This pin controls the input capture feature for the on-chip programmable
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity.
The TCMP pin provides an output for the output compare feature of the
on-chip timer subsystem.
General Release Specification
22
MC68HC05C4A — Rev. 4.0
General Description
General Description
Functional Pin Description
1.5.7 Port A (PA0–PA7)
These eight input/output (I/O) lines comprise port A. The state of any pin
is software programmable and all port A lines are configured as input
during power-on or reset. For detailed information on I/O programming,
see 7.7 Input/Output Programming.
1.5.8 Port B (PB0–PB7)
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as input during power-
on or reset. Port B has mask option enabled pullup devices and interrupt
capability by pin. The interrupts and pullups are enabled together. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.9 Port C (PC0–PC7)
These eight I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as input during power-
on or reset. PC7 has high current sink and source capability. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.10 Port D (PD0–PD5 a nd PD7)
These seven port lines comprise port D. PD7 and PD5–PD0 are input
only. PD0 and PD1 are shared with the SCI subsystem and PD2–PD5
are shared with the SPI subsystem. For a detailed description on I/O
programming, refer to 7.7 Input/Output Programming.
MC68HC05C4A — Rev. 4.0
General Release Specification
General Description
23
Ge ne ra l De sc rip tion
General Release Specification
24
MC68HC05C4A — Rev. 4.0
General Description
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
2.5
Introduction...............................................................................25
Read-Only Memory (ROM).......................................................25
ROM Security Feature..............................................................26
Random-Access Memory (RAM)..............................................26
2.2 Introd uc tion
The MC68HC05C4A has an 8-Kbyte memory map, consisting of user
read-only memory (ROM), user random-access memory (RAM), self-
check ROM, and input/output (I/O) registers. See Figure 2-1 and
Figure 2-2.
2.3 Re a d -Only Me m ory (ROM)
The user ROM consists of 48 bytes of page zero ROM from $0020 to
$004F, 4096 bytes of ROM from $0100 to $10FF, and 16 bytes of user
vectors from $1FF0 to $1FFF. The self-check ROM and vectors are
located from $1F00 to $1FEF. See Figure 2-1.
Twelve of the user vectors, $1FF4 through $1FFF, are dedicated to
user-defined reset and interrupt vectors. The remaining four bytes from
$1FF0-$1FF3 are not used.
MC68HC05C4A — Rev. 4.0
General Release Specification
Memory
25
Me m ory
2.4 ROM Se c urity Fe a ture
1
A security feature has been incorporated into the MC68HC05C4A to
help prevent externally reading of code in the ROM. This feature aids in
keeping customer-developed software proprietary.
2.5 Ra nd om -Ac c e ss Me m ory (RAM)
The user RAM consists of 176 bytes and is used both for general-
purpose RAM and stack area. The stack begins at address $00FF. The
stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.
See Figure 2-1.
NOTE: Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make
reading or copying the ROM difficult for unauthorized users.
General Release Specification
26
MC68HC05C4A — Rev. 4.0
Memory
Memory
Random-Access Memory (RAM)
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
I/O REGISTERS
32 BYTES
$001F
$0020
USER ROM
48 BYTES
$004F
$0050
UNUSED
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
RAM
176 BYTES
$00BF
$00C0
STACK
64 BYTES
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
$00FF
$0100
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
USER ROM
4096 BYTES
$10FF
$1100
UNUSED
UNUSED
UNUSED
UNUSED
3548 BYTES
COP REGISTER
$1FF0
$1FF1
$1FF2
$1EFF
$1F00
NOT USED (3 BYTES)
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SCI VECTOR (HIGH)
SELF-CHECK
ROM
AND VECTORS
240 BYTES
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
$1FEF
$1FF0
USER ROM VECTORS
16 BYTES
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$1FFF
Figure 2-1. Memory Map
MC68HC05C4A — Rev. 4.0
General Release Specification
27
Memory
Me m ory
Addr.
Register
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Port A Data
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTA
Port B Data
PORTB
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
PB7
PC7
PD7
PB6
PC6
PB5
PC5
PD5
PB4
PC4
PD4
PB3
PC3
PD3
PB2
PC2
PD2
PB1
PC1
PD1
PB0
PC0
PD0
Port C Data
PORTD
Port D Data
PORTD
Port A Data Direction
DDRA
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Port B Data Direction
DDRB
Port C Data Direction
DDRC
Unimplemented
Unimplemented
Unimplemented
SPI Control Register
SPCR
SPIE
SPIF
SPD7
SPE
WCOL
SPD6
MSTR
MODF
SPD4
CPOL
0
CPHA
0
SPR1
0
SPR0
0
0
SPI Status Register
SPSR
SPI Data Register
SPDR
SPD5
SPD3
SPD2
SPD1
SPD0
= Unimplemented
Figure 2-2. Input/Output Registers
General Release Specification
28
MC68HC05C4A — Rev. 4.0
Memory
Memory
Random-Access Memory (RAM)
Addr.
Register
Bit 7
6
5
SCP1
0
4
3
2
SCR2
0
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
SCI Baud Rate Register
BAUD
$000D
SCP0
R8
SCI Control 1
SCCR1
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
T8
TCIE
TC
M
WAKE
TE
SCI Control 2
SCCR2
TIE
RIE
ILIE
IDLE
RE
NF
RMW
FE
SBK
0
SCI Status Register
SCSR
TDRE
SCD7
RDRF
SCD5
OR
SCI Data Register
SCDAT
SCD6
SCD4
0
SCD3
0
SCD2
0
SCD1
SCD0
Timer Control Register
TCR
ICIE
ICF
OCIE
OCF
TOIE
TOF
IEDGE
0
OLVL
0
0
0
0
Timer Status Register
TSR
Read: Bit 15
Write:
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Input Capture Register
ICR (High)
Read: Bit 7
Write:
Input Capture Register
ICR (Low)
Read:
Bit 15
Write:
Output Compare Register
OCR (High)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Bit 7
Output Compare Register
OCR (Low)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Write:
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Timer Counter Register
TCNT (High)
Read: Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer Counter Register
TCNT (Low)
= Unimplemented
Figure 2-2. Input/Output Registers (Continued)
MC68HC05C4A — Rev. 4.0
General Release Specification
29
Memory
Me m ory
Addr.
Register
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Alternate Counter Register
ALTCNT (High)
$001A
$001B
$001C
$001D
$001E
Read: Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Alternate Counter Register
ALTCNT (Low)
Read:
Unimplemented
Unimplemented
Unimplemented
Reserved
Write:
Read:
Write:
Read:
Write:
Read:
R
Write:
$001F
R
R
R
R
R
R
R
↑
↑
↓
Read:
User ROM Data
$1FF0
COP Reset
Write:
COPC
= Unimplemented
R
= Reserved
Figure 2-2. Input/Output Registers (Continued)
General Release Specification
30
MC68HC05C4A — Rev. 4.0
Memory
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 3. Ce ntra l Proc e ssor Unit (CPU)
3.1 Conte nts
3.2
Introduction...............................................................................31
3.3
CPU Registers..........................................................................31
Accumulator ........................................................................32
Index Register .....................................................................32
Program Counter.................................................................33
Stack Pointer.......................................................................33
Condition Code Register .....................................................33
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.2 Introd uc tion
3.3 CPU Re g iste rs
This section describes the CPU registers.
The five CPU registers are shown in Figure 3-1 and the interrupt
stacking order is shown in Figure 3-2.
MC68HC05C4A — Rev. 4.0
General Release Specification
31
Central Processor Unit (CPU)
Ce ntra l Proc e ssor Unit (CPU)
7
7
A
X
0
0
ACCUMULATOR
INDEX REGISTER
12
12
0
0
PC
1
PROGRAM COUNTER
STACK POINTER
7
1
0
0
0
0
0
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
0
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
STACK
1
1
1
I
N
T
E
R
R
U
P
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
DECREASING
MEMORY
ADDRESSES
T
PCL
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
3.3.1 Ac c um ula tor
The accumulator (A) shown in Figure 3-1 is a general-purpose 8-bit
register used to hold operands and results of arithmetic calculations or
data manipulations.
3.3.2 Ind e x Re g iste r
The index register (X) is an 8-bit register used by the indexed addressing
value to create an effective address. The index register also may be
used as a temporary storage area.
General Release Specification
32
MC68HC05C4A — Rev. 4.0
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
3.3.3 Prog ra m Counte r
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched.
3.3.4 Sta c k Pointe r
The stack pointer (SP) contains the address of the next free location on
the stack. During an MCU reset or the reset stack pointer (RSP)
instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented
as data is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These eight bits are appended to the six
least significant register bits (LSB) to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64
(decimal) locations. If 64 locations are exceeded, the stack pointer
wraps around and loses the previously stored information. A subroutine
call occupies two locations on the stack; an interrupt uses five locations.
3.3.5 Cond ition Cod e Re g iste r
The condition code register (CCR) is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed, and the fifth
bit indicates whether interrupts are masked. These bits can be tested
individually by a program, and specific actions can be taken as a result
of their state. Each bit is explained in the following paragraphs.
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
I — Interrupt
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
MC68HC05C4A — Rev. 4.0
General Release Specification
Central Processor Unit (CPU)
33
Ce ntra l Proc e ssor Unit (CPU)
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
C — Carry/Borrow
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
General Release Specification
34
MC68HC05C4A — Rev. 4.0
Central Processor Unit (CPU)
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 4. Inte rrup ts
4.1 Conte nts
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Introduction...............................................................................35
Hardware Controlled Interrupt Sequence .................................37
Software Interrupt (SWI)...........................................................37
External Interrupt (IRQ) ............................................................39
Timer Interrupt ..........................................................................39
Serial Communications Interrupt (SCI).....................................39
Serial Peripheral Interrupt (SPI)................................................40
4.2 Introd uc tion
The MCU can be interrupted five different ways:
• Four maskable hardware interrupts, IRQ (interrupt request), SPI
(serial peripheral interface), SCI (serial communications
interface), and timer
• Non-maskable software interrupt instruction (SWI)
Port B interrupts, if enabled, are combined with the IRQ to form a single
interrupt source.
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI (return to interrupt) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
MC68HC05C4A — Rev. 4.0
General Release Specification
Interrupts
35
Inte rrup ts
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but they are considered pending until the current
instruction is complete.
NOTE: The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-
bit state.
Vector addresses for all interrupts, including reset, are listed in
Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
Flag
CPU
Vector
Register
Interrupts
Reset
Name
Interrupt
Address
N/A
N/A
N/A
TSR
N/A
N/A
N/A
ICF
RESET
SWI
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
Software
External Interrupt
Timer Input Capture
IRQ
TIMER
Timer Output
Compare
TSR
TSR
OCF
TOF
TIMER
TIMER
SCI
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
Timer Overflow
Transmit Buffer
Empty
SCSR
TDRE
SCSR
SCSR
SCSR
SCSR
SPSR
SPSR
TC
RDRF
IDLE
OR
Transmit Complete
Receiver Buffer Full
Idle Line Detect
Overrun
SCI
SCI
SCI
SCI
SPI
SPI
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF4–$1FF5
$1FF4–$1FF5
SPIF
MODF
Transfer Complete
Mode Fault
General Release Specification
36
MC68HC05C4A — Rev. 4.0
Interrupts
Interrupts
Hardware Controlled Interrupt Sequence
4.3 Ha rd wa re Controlle d Inte rrup t Se q ue nc e
Three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts
for hardware interrupts are shown in Figure 4-1.
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address, which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset, as previously described in
Section 5. Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ),
serial periferal interface, serial communications interface, or timer
interrupt. These individual interrupts have no special wait vectors.
4.4 Softwa re Inte rrup t (SWI)
The software interrupt (SWI) is an executable instruction and a non-
maskable interrupt. It is executed regardless of the state of the I bit in the
CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts
which were pending when the SWI was fetched but before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $1FFC and
$1FFD.
MC68HC05C4A — Rev. 4.0
General Release Specification
Interrupts
37
Inte rrup ts
FROM
RESET
I BIT
IN CCR SET?
Y
N
IRQ
EXTERNAL
INTERRUPT
?
Y
CLEAR IRQ
REQUEST LATCH
N
Y
Y
Y
INTERNAL
TIMER
INTERRUPT
?
N
INTERNAL
SCI
INTERRUPT
?
N
INTERNAL
SPI
INTERRUPT
?
N
STACK
PC, X, A, CCR
FETCH NEXT
INSTRUCTION
SET I BIT IN
CC REGISTER
LOAD PC FROM:
SWI: $1FFC-$1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
SCI: $1FF6-$1FF7
SWI
INSTRUCTION
?
Y
N
RTI
Y
INSTRUCTION
?
N
RESTORE REGISTERS
FROM STACK:
EXECUTE
INSTRUCTION
CCR, A, X, PC
Figure 4-1. Interrupt Flowchart
General Release Specification
38
MC68HC05C4A — Rev. 4.0
Interrupts
Interrupts
External Interrupt (IRQ)
4.5 Exte rna l Inte rrup t (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an
additional external interrupt source which is coupled to the IRQ pin logic.
It follows the same edge/edge-level selection that the IRQ pin has. See
Figure 7-1. Port B Pullup Option.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-
only trigger operation is selectable by mask option.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Tim e r Inte rrup t
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.7 Se ria l Com m unic a tions Inte rrup t (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF6 and $1FF7.
MC68HC05C4A — Rev. 4.0
General Release Specification
Interrupts
39
Inte rrup ts
4.8 Se ria l Pe rip he ra l Inte rrup t (SPI)
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF4 and $1FF5.
General Release Specification
40
MC68HC05C4A — Rev. 4.0
Interrupts
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 5. Re se ts
5.1 Conte nts
5.2
5.3
5.4
Introduction...............................................................................41
Power-On Reset (POR)............................................................42
RESET Pin................................................................................42
5.5
Computer Operating Properly (COP) Reset .............................42
Resetting the COP ..............................................................42
COP During Wait Mode.......................................................43
COP During Stop Mode.......................................................43
COP During Self-Check Mode ............................................43
5.5.1
5.5.2
5.5.3
5.5.4
5.2 Introd uc tion
The MCU can be reset three ways:
1. Initial power-on reset function
2. Active low input to the RESET pin
3. Computer operating properly (COP) reset
MC68HC05C4A — Rev. 4.0
General Release Specification
41
Resets
Re se ts
5.3 Powe r-On Re se t (POR)
An internal reset is generated on power-up to allow the internal clock
generator to stabilize. The power-on reset is strictly for power turn-on
conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (t ) oscillator
cyc
stabilization delay after the oscillator becomes active. If the RESET pin
is low after the end of this 4064-cycle delay, the MCU will remain in the
reset condition until RESET goes high.
For additional information, refer to Figure 13-8. Power-On Reset Timing
Diagram.
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL).
5.5 Com p ute r Op e ra ting Prop e rly (COP) Re se t
This device includes a watchdog COP feature as a mask option. The
COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP
should time out, a system reset will occur and the device will be
re-initialized in the same fashion as a POR or external reset.
5.5.1 Re se tting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This
action will reset the counter and begin the timeout period again. The
COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result
in the user defined ROM data at that location.
General Release Specification
42
MC68HC05C4A — Rev. 4.0
Resets
Resets
Computer Operating Properly (COP) Reset
5.5.2 COP During Wa it Mod e
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPC bit to prevent a COP reset.
5.5.3 COP During Stop Mod e
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an interrupt is
used to exit stop mode, the COP counter will not be reset after the
4064-cycle delay and will have that many cycles already counted when
control is returned to the program.
5.5.4 COP During Se lf-Che c k Mod e
The COP is disabled by hardware during self-check mode.
MC68HC05C4A — Rev. 4.0
General Release Specification
43
Resets
Re se ts
General Release Specification
44
MC68HC05C4A — Rev. 4.0
Resets
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 6. Low-Powe r Mod e s
6.1 Conte nts
6.2
6.3
6.4
6.5
Introduction...............................................................................45
Stop Mode ................................................................................46
Stop Recovery ..........................................................................47
Wait Mode.................................................................................47
6.2 Introd uc tion
This section describes the two low-power modes — stop and wait.
Figure 6-1 shows the sequence of events caused by the STOP and
WAIT instructions.
MC68HC05C4A — Rev. 4.0
General Release Specification
Low-Power Modes
45
Low-Powe r Mod e s
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS
OSCILLATOR ACTIVE
TIMER CLOCK ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT
CLEAR I BIT
N
N
RESET
Y
RESET
EXTERNAL
INTERRUPT
EXTERNAL
INTERRUPT
(IRQ)
Y
N
(IRQ)
N
TIMER
INTERRUPT
Y
Y
Y
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
N
RESTART
PROCESSOR CLOCK
SCI
INTERRUPT
Y
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
N
B. SET I BIT
C. VECTOR TO
INTERRUPT
B. SET I BIT
C. VECTOR TO
INTERRUPT
SPI
INTERRUPT
N
ROUTINE
ROUTINE
Figure 6-1. Stop/Wait Mode Flowchart
6.3 Stop Mod e
The STOP instruction places the MCU in its lowest-power consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer
interrupt request and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the condition code register is cleared to
enable external interrupts. All other registers and memory remain
General Release Specification
46
MC68HC05C4A — Rev. 4.0
Low-Power Modes
Low-Power Modes
Stop Recovery
unaltered. All input/output lines remain unchanged. The processor can
be brought out of stop mode only by an external interrupt or reset.
6.4 Stop Re c ove ry
6.5 Wa it Mod e
The processor can be brought out of stop mode only by an external
interrupt or reset. See Figure 6-2.
The WAIT instruction places the MCU in a low-power consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, SCI, SPI, and the oscillator
remain active. Any interrupt or reset will cause the MCU to exit wait
mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
1
OSC1
t
RL
RESET
t
ILIH
2
IRQ
t
4064 t
3
ILCH
cyc
IRQ
INTERNAL CLOCK
INTERNAL ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFF
NOTES:
RESET ($1FFE, $1FFF) OR
INTERRUPT ($1FFA, $1FFB)
VECTOR FETCH
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge sensitive option
Figure 6-2. Stop Recovery Timing Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
47
Low-Power Modes
Low-Powe r Mod e s
General Release Specification
48
MC68HC05C4A — Rev. 4.0
Low-Power Modes
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 7. Inp ut/ Outp ut (I/ O) Ports
7.1 Conte nts
7.2
7.3
7.4
7.5
7.6
7.7
Introduction...............................................................................49
Port A........................................................................................49
Port B........................................................................................50
Port C........................................................................................50
Port D........................................................................................51
Input/Output Programming .......................................................51
7.2 Introd uc tion
The MC68HC05C4A has three 8-bit input/output (I/O) ports.These 24
port pins are programmable as either inputs or outputs under software
control of the data direction registers. Port D does not have a data
direction register, and its seven pins are input only with the exception of
certain SCI/SPI functions.
NOTE: To avoid a glitch on the output pins, write data to the I/O port data
register before writing a 1 to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the
ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit
to output mode.
MC68HC05C4A — Rev. 4.0
General Release Specification
49
Input/Output (I/O) Ports
Inp ut/ Outp ut (I/ O) Ports
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001,
and the data direction register (DDR) is at $0005. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode. Each of the port B pins has a
mask programmable interrupt capability. This interrupt option also
enables a pullup device when the pin is configured as an input (see
Figure 7-1). The edge or edge and level sensitivity of the IRQ pin also
will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an
output to an input, the data should be preconditioned to a 1 to prevent
an interrupt from occurring.
V
V
DD
DD
MASK OPTION
DDR BIT
SCHMITT
TRIGGER
IRQ
PB0
NORMAL PORT CIRCUITRY
AS SHOWN IN
FIGURE 7-2.
TO
INTERRUPT
LOGIC
FROM ALL OTHER PORT B PINS
Figure 7-1. Port B Pullup Option
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. PC7 has a high current sink and
source capability.
General Release Specification
50
MC68HC05C4A — Rev. 4.0
Input/Output (I/O) Ports
Input/Output (I/O) Ports
Port D
7.6 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI
subsystem, and two more are shared with the SCI subsystem. Reset
does not affect the data registers. During reset, all seven bits become
valid input ports because all special function output drivers associated
with the SCI, timer, and SPI subsystems are disabled.
7.7 Inp ut/ Outp ut Prog ra m m ing
I/O port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all I/O pins
as inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin. For further information, refer to Table 7-1 and Figure 7-2.
Table 7-1. I/O Pin Functions
R/W*
DDR
I/O Pin Function
The I/O pin is in input mode. Data is written into the
output data latch.
0
0
Data is written into the output data latch and output to
the I/O pin.
0
1
1
1
0
1
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is
read.
*R/W is an internal signal.
MC68HC05C4A — Rev. 4.0
General Release Specification
Input/Output (I/O) Ports
51
Inp ut/ Outp ut (I/ O) Ports
READ DDRx
WRITE DDRx
DATA DIRECTION
REGISTER x BIT
U
RESET
A
T
A
PORT x DATA
REGISTER BIT
(LATCHED OUTPUT)
WRITE PORTx
READ PORTx
I/O
PIN
[1]
NI T ER N A L D
[3]
[2]
[1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode).
[2] This input buffer is enabled when DDR bit is 0 (input mode).
[3] This input buffer is enabled when DDR bit is 1 (output mode).
Figure 7-2. I/O Circuitry
General Release Specification
52
MC68HC05C4A — Rev. 4.0
Input/Output (I/O) Ports
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 8. Tim e r
8.1 Conte nts
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Introduction...............................................................................53
Counter.....................................................................................55
Output Compare Register.........................................................56
Input Capture Register..............................................................57
Timer Control Register..............................................................58
Timer Status Register...............................................................60
Timer During Wait Mode...........................................................61
Timer During Stop Mode...........................................................61
8.2 Introd uc tion
The timer consists of a 16-bit, software-programmable counter driven by
a fixed divide-by-four prescaler. This timer can be used for many
purposes, including input waveform measurements while
simultaneously generating an output waveform. Pulse widths can vary
from several microseconds to many seconds. Refer to Figure 8-1 for a
timer block diagram.
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
NOTE: The I bit in the condition code register should be set while manipulating
both the high and low byte register of a specific timer function to ensure
that an interrupt does not occur.
MC68HC05C4A — Rev. 4.0
General Release Specification
53
Timer
Tim e r
INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
HIGH
BYTE
LOW
BYTE
8-BIT
BUFFER
÷ 4
HIGH LOW
BYTE BYTE
OUTPUT
COMPARE
REGISTER
$16
$17
HIGH
BYTE
LOW
BYTE
INPUT
CAPTURE
REGISTER
16-BIT FREE
RUNNING
COUNTER
$14
$15
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
EDGE
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
D
Q
CLK
OUTPUT
LEVEL
$13
TIMER
STATUS
ICF OCF TOF
C
REGISTER
REGISTER
TIMER
CONTROL
RESET
ICIE OCIE TOIE IEDG OLVL
REGISTER
$12
OUTPUT
LEVEL
(TCMP)
EDGE
INPUT
(TCAP)
INTERRUPT
CIRCUIT
Figure 8-1. Timer Block Diagram
General Release Specification
54
MC68HC05C4A — Rev. 4.0
Timer
Timer
Counter
8.3 Counte r
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $18, $19 (counter register) or $1A, $1B (counter alternate
register). A read from only the least significant byte (LSB) of the free-
running counter ($19, $1B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB also must be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is
always a read-only register. During a power-on reset, the counter also is
preset to $FFFC and begins running after the oscillator startup delay.
Because the free-running counter is 16 bits preceded by a fixed divide-
by-four prescaler, the value in the free-running counter repeats every
262,144 internal bus clock cycles. When the counter rolls over from
$FFFF to $0000, the TOF bit is set. An interrupt also can be enabled
whenever counter rollover occurs by setting its interrupt enable bit
(TOIE).
MC68HC05C4A — Rev. 4.0
General Release Specification
Timer
55
Tim e r
8.4 Outp ut Com p a re Re g iste r
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
The output compare register contents are compared with the contents of
the free-running counter continually, and if a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt also can accompany a successful output
compare, provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is written also. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear. Figure 8-2 shows the logic of the output compare
function.
General Release Specification
56
MC68HC05C4A — Rev. 4.0
Timer
Timer
Input Capture Register
15
15
0
COUNTER HIGH BYTE
COUNTER LOW BYTE
PIN
CONTROL
16-BIT COMPARATOR
TCMP
LOGIC
8
7
0
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
TIMER
INTERRUPT
REQUEST
F
O
C
O
C
C
O
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-2. Output Compare Operation
8.5 Inp ut Ca p ture Re g iste r
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register except when exiting stop
mode.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
MC68HC05C4A — Rev. 4.0
General Release Specification
Timer
57
Tim e r
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-
running counter transfer, since they occur on opposite edges of the
internal bus clock. Figure 8-3 shows the logic of the input capture
function.
$0018
$0019
15
8
7
0
TIMER REGISTER HIGH
TIMER REGISTER LOW
15
8
7
0
EDGE
SELECT/DETECT
LOGIC
LATCH
TCMP
INPUT CAPTURE REGISTER HIGH INPUT CAPTURE REGISTER LOW
$0014
$0015
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-3. Input Capture Operation
8.6 Tim e r Control Re g iste r
The TCR is a read/write register containing five control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
Address:
$12
Bit 7
6
OCIE
0
5
TOIE
0
4
0
0
3
0
0
2
0
0
1
IEDG
U
Bit 0
OLVL
0
Read:
Write:
Reset:
ICIE
0
U = Unaffected
Figure 8-4. Timer Control Register (TCR)
General Release Specification
58
MC68HC05C4A — Rev. 4.0
Timer
Timer
Timer Control Register
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
MC68HC05C4A — Rev. 4.0
General Release Specification
Timer
59
Tim e r
8.7 Tim e r Sta tus Re g iste r
The TSR is a read-only register containing three status flag bits.
Address:
$13
Bit 7
6
OCF
U
5
TOF
U
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0
Read:
Write:
Reset:
ICF
0
0
U
U = Unaffected
Figure 8-5. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-
running counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
General Release Specification
60
MC68HC05C4A — Rev. 4.0
Timer
Timer
Timer During Wait Mode
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose
of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
8.8 Tim e r During Wa it Mod e
The CPU clock halts during wait mode, the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
the wait mode.
8.9 Tim e r During Stop Mod e
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If reset is used, the counter is forced to
$FFFC. During stop, if at least one valid input capture edge occurs at the
TCAP pin, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU. But if the MCU exits stop due to an
external interrupt, there is an active input capture flag and data from the
first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid
input capture edge occurred.
MC68HC05C4A — Rev. 4.0
General Release Specification
Timer
61
Tim e r
General Release Specification
62
MC68HC05C4A — Rev. 4.0
Timer
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 9. Se ria l Com m unic a tions Inte rfa c e (SCI)
9.1 Conte nts
9.2
9.3
9.4
Introduction...............................................................................63
Features....................................................................................64
SCI Data Format.......................................................................64
9.5
9.5.1
SCI Operation...........................................................................65
Transmitter ..........................................................................65
Character Length .............................................................65
Character Transmission...................................................65
Break Characters .............................................................67
Idle Characters.................................................................67
Transmitter Interrupts.......................................................67
Receiver ..............................................................................68
Character Length .............................................................69
Character Reception ........................................................69
Receiver Wakeup.............................................................69
Receiver Noise Immunity .................................................70
Framing Errors .................................................................70
Receiver Interrupts...........................................................70
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.1.5
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.2.4
9.5.2.5
9.5.2.6
9.6
SCI I/O Registers......................................................................71
SCI Data Register ...............................................................71
SCI Control Register 1 ........................................................72
SCI Control Register 2 ........................................................74
SCI Status Register.............................................................76
Baud Rate Register.............................................................78
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.2 Introd uc tion
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other MCUs.
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Communications Interface (SCI)
63
Se ria l Com munic a tions Inte rfa c e (SCI)
9.3 Fe a ture s
Features of the SCI module include:
• Standard Mark/Space Non-Return-to-Zero Format
• Full-Duplex Operation
• 32 Programmable Baud Rates
• Programmable 8-Bit or 9-Bit Character Length
• Separately Enabled Transmitter and Receiver
• Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
• Interrupt-Driven Operation Capability with Five Interrupt Flags:
– Transmitter Data Register Empty
– Transmission Complete
– Receiver Data Register Full
– Receiver Overrun
– Idle Receiver Input
• Receiver Framing Error Detection
• 1/16 Bit-Time Noise Detection
9.4 SCI Da ta Form a t
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 9-1.
8-BIT DATA FORMAT
BIT M IN SCCR1 CLEAR
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCCR1 SET
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 9-1. SCI Data Format
General Release Specification
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI Operation
9.5 SCI Op e ra tion
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. The following
paragraphs describe the operation of the SCI transmitter and receiver.
9.5.1 Tra nsm itte r
Figure 9-2 shows the structure of the SCI transmitter.
9.5.1.1 Cha ra c te r Le ng th
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCCR1) determines character length.
When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit (bit 8).
9.5.1.2 Cha ra c te r Tra nsm issio n
During transmission, the transmit shift register shifts a character out to
the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then
writing data to the SCDR begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Communications Interface (SCI)
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Se ria l Com munic a tions Inte rfa c e (SCI)
When the shift register is not transmitting a character, the PD1/TDO pin
goes to the idle condition, logic 1. If software clears the TE bit during the
idle condition, and while TDRE is set, the transmitter relinquishes control
of the PD1/TDO pin.
INTERNAL DATA BUS
SCDR ($0011)
TRANSMIT SHIFT REGISTER
1X
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
PD1/
TDO
H 8
7
6 5 4 3 2 1 0 L
M
T8
SBK
TRANSMITTER
CONTROL LOGIC
TE
TDRE
TIE
TC
TCIE
SCI
INTERRUPT
REQUEST
SCI
RECEIVE
REQUESTS
BIT 7
0
6
0
4
3
0
2
1
BIT 0
5
BAUD RATE REGISTER (BAUD)
SCP1 SCP0
SCR2 SCR1 SCR0 $000D
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
T8
TCIE
TC
0
RIE
M
ILIE
WAKE
TE
OR
0
RE
NF
BIT 2
0
0
$000E
SBK $000F
$0010
BIT 0 $0011
RWU
FE
BIT 1
RDRF IDLR
BIT 5 BIT 4
0
BIT 6
BIT 3
Figure 9-2. SCI Transmitter
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI Operation
9.5.1.3 Bre a k Cha ra c te rs
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
break character. A break character contains all logic 0s and has no start
and stop bits. Break character length depends on the M bit in SCCR1.
As long as SBK is at logic 1, transmitter logic continuously loads break
characters into the shift register. After software clears the SBK bit, the
shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break
character is to guarantee the recognition of the start bit of the next
character.
9.5.1.4 Id le Cha ra c te rs
An idle character contains all logic 1s and has no start or stop bits. Idle
character length depends on the M bit in SCCR1. The preamble is a
synchronizing idle character that begins every transmission.
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin
after the last character to be transmitted is shifted out. The last character
may already be in the shift register, or waiting in the SCDR, or in a break
character generated by writing to the SBK bit. Toggling TE from logic 0
to logic 1 while the last character is in transmission generates an idle
character (a preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
9.5.1.5 Tra nsm itte r Inte rrup ts
Two sources can generate SCI transmitter interrupt requests:
1. Transmit Data Register Empty (TDRE) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to the
transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TDRE interrupts.
2. Transmission Complete (TC) — The TC bit in the SCSR indicates
that both the transmit shift register and the SCDR are empty and
that no break or idle character has been generated. TC is a source
of SCI interrupt requests. The transmission complete interrupt
enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.
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General Release Specification
Serial Communications Interface (SCI)
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.5.2 Re c e ive r
Figure 9-3 shows the structure of the SCI receiver.
INTERNAL DATA BUS
SCDR ($0011)
RECEIVE SHIFT REGISTER
16X
BAUD RATE
CLOCK
÷16
T
P
A
T
T
PD0/
RDI
PIN BUFFER
AND CONTROL
DATA
RECOVERY
8
7 6 5 4 3 2 1 0
NF
FE
R8
RE
M
RDRF
RIE
SCI
INTERRUPT
REQUEST
OR
RIE
SCI
TRANSMIT
REQUESTS
IDLE
ILIE
WAKEUP
LOGIC
RWU
BIT 0
BIT 7
0
6
0
5
4
3
0
2
1
BAUD RATE REGISTER (BAUD)
SCP1 SCP0
SCR2 SCR1 SCR0 $000D
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
T8
TCIE
TC
0
RIE
M
ILIE
WAKE
TE
OR
0
RE
NF
BIT 2
0
0
$000E
SBK $000F
$0010
BIT 0 $0011
RWU
FE
BIT 1
RDRF IDLR
BIT 5 BIT 4
0
BIT 6
BIT 3
Figure 9-3. SCI Receiver
General Release Specification
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI Operation
9.5.2.1 Cha ra c te r Le ng th
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCCR1) determines character length.
When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit
(bit 8).
9.5.2.2 Cha ra c te r Re c e p tio n
During reception, the receive shift register shifts characters in from the
PD0/RDI pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character is transferred to the SCDR, setting the receive
data register full (RDRF) flag. The RDRF flag can be used to generate
an interrupt.
9.5.2.3 Re c e ive r Wa ke up
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup enable (RWU) bit in SCI
control register 2 (SCCR2) puts the receiver into a standby state during
which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of
the standby state:
1. Idle input line condition — If the PD0/RDI pin is at logic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift register,
receiver interrupts are again enabled.
2. Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
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Serial Communications Interface (SCI)
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Se ria l Com munic a tions Inte rfa c e (SCI)
9.5.2.4 Re c e ive r No ise Im m unity
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
9.5.2.5 Fra m ing Erro rs
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.5.2.6 Re c e ive r Inte rrup ts
Three sources can generate SCI receiver interrupt requests:
1. Receive Data Register Full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character
to the SCDR.
2. Receiver Overrun (OR) — The OR bit in the SCSR indicates that
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
3. Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
11 consecutive logic 1s shifted in from the PD0/RDI pin.
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
9.6 SCI I/ O Re g iste rs
These I/O registers control and monitor SCI operation:
• SCI data register (SCDR)
• SCI control register 1 (SCCR1)
• SCI control register 2 (SCCR2)
• SCI status register (SCSR)
9.6.1 SCI Da ta Re g iste r
The SCI data register is the buffer for characters received and for
characters transmitted.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unaffected by Reset
Figure 9-4. SCI Data Register (SCDR)
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General Release Specification
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Serial Communications Interface (SCI)
Se ria l Com munic a tions Inte rfa c e (SCI)
9.6.2 SCI Control Re g iste r 1
SCI control register 1 has these functions:
• Stores ninth SCI data bit received and ninth SCI data bit
transmitted
• Controls SCI character length
• Controls SCI wakeup method
Address: $000E
Bit 7
R8
6
5
0
4
3
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
T8
M
WAKE
Unaffected by Reset
= Unimplemented
Figure 9-5. SCI Control Register (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit from the receive shift
register at the same time that the SCDR receives the other eight bits.
Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T8 bit.
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
M — Character Length
This read/write bit determines whether SCI characters are 8 bits long
or 9 bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the MSB position of a received character or
an idle condition of the PD0/RDI pin. Reset has no effect on the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Communications Interface (SCI)
73
Se ria l Com munic a tions Inte rfa c e (SCI)
9.6.3 SCI Control Re g iste r 2
SCI control register 2 has these functions:
• Enables the SCI receiver and SCI receiver interrupts
• Enables the SCI transmitter and SCI transmitter interrupts
• Enables SCI receiver idle interrupts
• Enables SCI transmission complete interrupts
• Enables SCI wakeup
• Transmits SCI break characters
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Unaffected by Reset
Figure 9-6. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable
This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable
This read/write bit enables SCI interrupt requests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
General Release Specification
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
ILIE — Idle Line Interrupt Enable
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Communications Interface (SCI)
75
Se ria l Com munic a tions Inte rfa c e (SCI)
9.6.4 SCI Sta tus Re g iste r
The SCI status register contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing Error
Address: $0010
Bit 7
Read: TDRE
Write:
6
5
4
3
2
1
Bit 0
TC
RDRF
IDLE
OR
NF
FE
0
Reset:
Unaffected by Reset
= Unimplemented
Figure 9-7. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
General Release Specification
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
bit by reading the SCSR with TC set, and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set, and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
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General Release Specification
Serial Communications Interface (SCI)
77
Se ria l Com munic a tions Inte rfa c e (SCI)
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR, and then reading the SCDR. Reset clears
the FE bit.
1 = Framing error
0 = No framing error
9.6.5 Ba ud Ra te Re g iste r
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address: $000D
Bit 7
6
0
0
5
SCP1
0
4
SCP0
0
3
0
0
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
Read:
Write:
Reset:
0
0
U = Unaffected
Figure 9-8. Baud Rate Register (BAUD)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Resets clear both SCP1 and SCP0.
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Serial Communications Interface (SCI)
SCI I/O Registers
Table 9-1. Baud Rate Generator Clock Prescaling
Baud Rate Generator Clock
Internal Clock Divided by 1
Internal Clock Divided by 3
Internal Clock Divided by 4
Internal Clock Divided by 13
SCP0–SCP1
00
01
10
11
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 9-2. Reset has no effect on the SCR2–SCR0 bits.
Table 9-2. Baud Rate Selection
SCI Baud Rate (Baud)
Prescaled Clock Divided by 1
Prescaled Clock Divided by 2
Prescaled Clock Divided by 4
Prescaled Clock Divided by 8
Prescaled Clock Divided by 16
Prescaled Clock Divided by 32
Prescaled Clock Divided by 64
Prescaled Clock Divided by 128
SCR2–SCR0
000
001
010
011
100
101
110
111
Table 9-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
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Serial Communications Interface (SCI)
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Se ria l Com munic a tions Inte rfa c e (SCI)
Table 9-3. Baud Rate Selection Examples
SCI Baud Rate
fOSC = 4 MHz
SCP1–SCP0
SCR2–SCR0
fOSC = 2 MHz
fOSC = 4.194304 MHz
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
62.50 kBaud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
20.83 kBaud
10.42 kBaud
5208 Baud
2604 Baud
1302 Baud
651.0 Baud
325.5 Baud
162.8 Baud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
244.1 Baud
122.1 Baud
4808 Baud
2404 Baud
1202 Baud
601.0 Baud
300.5 Baud
150.2 Baud
75.12 Baud
37.56 Baud
125 kBaud
62.50 kBaud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
41.67 kBaud
20.83 kBaud
10.42 kBaud
5208 Baud
2604 Baud
1302 Baud
651.0 Baud
325.5 Baud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
244.1 Baud
9615 Baud
4808 Baud
2404 Baud
1202 Baud
601.0 Baud
300.5 Baud
150.2 Baud
75.12 Baud
131.1 kBaud
65.54 kBaud
32.77 kBaud
16.38 kBaud
8192 Baud
4096 Baud
2048 Baud
1024 Baud
43.69 kBaud
21.85 kBaud
10.92 kBaud
5461 Baud
2731 Baud
1365 Baud
682.7 Baud
341.3 Baud
32.77 kBaud
16.38 kBaud
8192 Baud
4906 Baud
2048 Baud
1024 Baud
512.0 Baud
256.0 Baud
10.08 kBaud
5041 Baud
2521 Baud
1260 Baud
630.2 Baud
315.1 Baud
157.5 Baud
78.77 Baud
General Release Specification
80
MC68HC05C4A — Rev. 4.0
Serial Communications Interface (SCI)
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 10. Se ria l Pe rip he ra l Inte rfa c e (SPI)
10.1 Conte nts
10.2 Introduction...............................................................................81
10.3 Features....................................................................................82
10.4 SPI Signal Description..............................................................82
10.4.1
10.4.2
10.4.3
10.4.4
Master In Slave Out (MISO)................................................82
Master Out Slave In (MOSI)................................................82
Serial Clock (SCK) ..............................................................83
Slave Select (SS) ................................................................84
10.5 Functional Description ..............................................................84
10.6 SPI Registers............................................................................86
10.6.1
10.6.2
10.6.3
Serial Peripheral Control Register.......................................87
Serial Peripheral Status Register ........................................88
Serial Peripheral Data I/O Register.....................................90
10.2 Introd uc tion
The serial peripheral interface (SPI) is an interface built into the
MC68HC05 MCU which allows several MC68HC05 MCUs or
MC68HC05 MCU plus peripheral devices to be interconnected within a
single printed circuit board. In an SPI, separate wires are required for
data and clock. In the SPI format, the clock is not included in the data
stream and must be furnished as a separate signal. An SPI system may
be configured in a system containing one master MCU and several slave
MCUs or in a system in which an MCU is capable of being a master or a
slave.
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Peripheral Interface (SPI)
81
Se ria l Pe rip he ra l Inte rfa c e (SPI)
10.3 Fe a ture s
• Full-Duplex, 4-Wire Synchronous Transfers
• Master or Slave Operation
• Bus Frequency Divided by 2 (Maximum) Master Bit Frequency
• Bus Frequency (Maximum) Slave Bit Frequency
• Four Programmable Master Bit Rates
• Programmable Clock Polarity and Phase
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Master-Master Mode Fault Protection Capability
10.4 SPI Sig na l De sc rip tion
The four basic signals (MOSI, MISO, SCK, and SS) are described in the
following paragraphs. Each signal function is described for both the
master mode and slave mode.
10.4.1 Ma ste r In Sla ve Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Ma ste r Out Sla ve In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit (MSB) sent first.
General Release Specification
82
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPI Signal Description
10.4.3 Se ria l Cloc k (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line one-half cycle before the clock edge (SCK), so the slave
device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI
operation.
SS
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
83
Serial Peripheral Interface (SPI)
Se ria l Pe rip he ra l Inte rfa c e (SPI)
10.4.4 Sla ve Se le c t (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.
The SS line on the master must be tied high. If it goes low, a mode fault
error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to V as long as CPHA = 1 clock modes are used.
SS
10.5 Func tiona l De sc rip tion
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full-duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
The SPI data register (SPDR) is double buffered on read, but not on
write. If a write is performed during data transfer, the transfer occurs
uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After
a data byte is shifted, the SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
General Release Specification
84
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
Functional Description
S
M
MISO
PD2
INTERNAL
MCU CLOCK
MSB
LSB
M
S
MOSI
PD3
8-BIT SHIFT REG
READ DATA BUFF
DIVIDER
÷2
÷4 ÷16 ÷32
CLOCK
SPI CLOCK
(MASTER)
S
SELECT
CLOCK
SCK
P
LOGIC
PD4
M
SS
PD5
MSTR
SPE
SPI CONTROL
SPI STATUS REGISTER
SPI CONTROL REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
85
Serial Peripheral Interface (SPI)
Se ria l Pe rip he ra l Inte rfa c e (SPI)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5
SS
I/O PORT
SPDR ($000C)
SLAVE MCU
SPDR ($000C)
PD4/SCK
MASTER MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.6 SPI Re g iste rs
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
General Release Specification
86
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPI Registers
10.6.1 Se ria l Pe rip he ra l Control Re g iste r
Address: $000A
Bit 7
SPID
0
6
SPD
0
5
0
4
MSTR
0
3
CPOL
0
2
CPHA
0
1
SPR1
U
Bit 0
SPR0
0
Read:
Write:
Reset:
U = Unaffected
= Unimplemented
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Peripheral Interface (SPI)
87
Se ria l Pe rip he ra l Inte rfa c e (SPI)
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Selects
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
See Table 10-1.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
0
0
1
1
0
1
0
1
2
4
16
32
10.6.2 Se ria l Pe rip he ra l Sta tus Re g iste r
Address: $000B
Bit 7
6
5
0
4
3
0
2
0
1
0
Bit 0
0
Read:
SPIF
0
WCOL
0
MODF
0
Write:
Reset:
0
0
0
U
0
U = Unaffected
= Unimplemented
Figure 10-5. SPI Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
General Release Specification
88
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPI Registers
WCOL — Write Collision
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is 0, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is 1, a transfer is said to begin the first time SCK
becomes active while SS is low. The transfer ends when the SPIF flag
gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
Bit 5 — Not implemented
This bit always reads 0.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low.
Setting the MODF bit affects the internal serial peripheral interface
system in the following ways:
• An SPI interrupt is generated if SPIE = 1.
• The SPE bit is cleared. This disables the SPI.
• The MSTR bit is cleared, thus forcing the device into the slave
mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always read 0.
MC68HC05C4A — Rev. 4.0
General Release Specification
Serial Peripheral Interface (SPI)
89
Se ria l Pe rip he ra l Inte rfa c e (SPI)
10.6.3 Se ria l Pe rip he ra l Da ta I/ O Re g iste r
The serial peripheral data I/O register is used to transmit and receive
data on the serial bus. Only a write to this register will initiate
transmission/reception of another byte, and this will occur only in the
master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
General Release Specification
90
MC68HC05C4A — Rev. 4.0
Serial Peripheral Interface (SPI)
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 11. Op e ra ting Mod e s
11.1 Conte nts
11.2 Introduction...............................................................................91
11.3 User Mode ................................................................................91
11.4 Self-Check Mode ......................................................................92
11.4.1
11.4.2
Self-Check Tests.................................................................92
Self-Check Results..............................................................93
11.2 Introd uc tion
The MCU has two modes of operation: user mode and self-check mode.
Table 11-1 shows the conditions required to enter into each mode,
where V
= 2 x V .
TST
DD
Table 11-1. Operating Mode Conditions
RESET
IRQ
to V
TCAP
to V
Mode
User
V
V
SS
DD
SS
DD
V
V
Self-Check
TST
DD
11.3 Use r Mod e
In user mode, the address and data buses are not available externally,
but there are three 8-bit input/output (I/O) ports and one 7-bit input-only
port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU. User
mode is entered on the rising edge of RESET if the IRQ pin is within
normal operating range.
MC68HC05C4A — Rev. 4.0
General Release Specification
Operating Modes
91
Op e ra ting Mod e s
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
1
RESET
IRQ
NC
2
OSC1
OSC2
TCAP
3
4
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
5
PD7
6
PD6/TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
PC2
PC3
PC4
PC5
PC6
V
PC7
SS
Figure 11-1. User Mode Pinout
11.4 Se lf-Che c k Mod e
Self-check mode is entered upon the rising edge of RESET if the IRQ pin
is at V and the TCAP pin is at logic 1.
TST
11.4.1 Se lf-Che c k Te sts
The self-check ROM at mask ROM location $1F00–$1FEF determines
if the MCU is functioning properly. These five tests are performed:
1. I/O — Functional test of ports A, B, and C
2. RAM — Counter test for each RAM byte
3. Timer — Test of counter register and OCF bit
4. SCI — Transmission test checks for RDRF, TDRE, TC, and FE
flags
General Release Specification
92
MC68HC05C4A — Rev. 4.0
Operating Modes
Operating Modes
Self-Check Mode
5. ROM — Exclusive OR with odd ones parity result
6. SPI — Transmission test checks for SPIF and WCOL flags
The self-check circuit is shown in Figure 11-2.
11.4.2 Se lf-Che c k Re sults
Table 11-2 shows the LED codes that indicate self-check test results.
Table 11-2. Self-Check Circuit LED Codes
PC3
Off
Off
Off
Off
Off
Off
PC2
On
On
On
Off
Off
Off
PC1
On
Off
Off
On
On
Off
PC0
Off
On
Off
On
Off
On
Remarks
I/O Failure
RAM Failure
Timer Failure
SCI Failure
ROM Failure
SPI Failure
No Failure
Flashing
All Others
Device Failure
Perform these three steps to activate the self-check tests:
1. Apply 10 V (2 x V ) to the IRQ pin.
DD
2. Apply a logic 1 to the TCAP pin.
3. Apply a logic 0 to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR) or
for a time, t , for any other reset. (For the t value, see 13.9 5.0 V
RL
RL
Control Timing.)
MC68HC05C4A — Rev. 4.0
General Release Specification
93
Operating Modes
Op e ra ting Mod e s
V
V
DD
DD
10 V
V
DD
MC34064
MC68H05C4A
4.7 kΩ
RESET
V
DD
1
40
39
38
37
36
IRQ
NC
OSC1
OSC2
TCAP
PD7
2
4 MHZ
3
PA7
PA6
4
V
DD
5
10 MΩ
20 pF
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
TCMP
6
35
34
33
32
31
30
29
28
27
26
10 kΩ
20 pF
PD5/SS
7
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
8
9
1 MΩ
10
11
12
13
PC1
14
15
CMOS
BUFFER
PC2
(MC74HC125)
PB4
PB5
PB6
PB7
PC3
PC4
PC5
PC6
PC7
16
17
18
19
20
25
24
23
22
21
V
SS
V
DD
NOTES:
1. VDD = 5.0 V
2. TCMP = NC
Figure 11-2. Self-Check Circuit Schematic
General Release Specification
94
MC68HC05C4A — Rev. 4.0
Operating Modes
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 12. Instruc tion Se t
12.1 Conte nts
12.2 Introduction...............................................................................96
12.3 Addressing Modes....................................................................96
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
Inherent ...............................................................................97
Immediate............................................................................97
Direct...................................................................................97
Extended .............................................................................97
Indexed, No Offset ..............................................................98
Indexed, 8-Bit Offset............................................................98
Indexed,16-Bit Offset...........................................................98
Relative ...............................................................................99
12.4 Instruction Types ......................................................................99
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
Register/Memory Instructions............................................100
Read-Modify-Write Instructions.........................................101
Jump/Branch Instructions..................................................102
Bit Manipulation Instructions .............................................104
Control Instructions ...........................................................105
12.5 Instruction Set Summary ........................................................106
12.6 Opcode Map ...........................................................................111
MC68HC05C4A — Rev. 4.0
General Release Specification
Instruction Set
95
Instruc tion Se t
12.2 Introd uc tion
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
12.3 Ad d re ssing Mod e s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
General Release Specification
96
MC68HC05C4A — Rev. 4.0
Instruction Set
Instruction Set
Addressing Modes
12.3.1 Inhe re nt
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
12.3.2 Im m e d ia te
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Dire c t
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Exte nd e d
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
MC68HC05C4A — Rev. 4.0
General Release Specification
Instruction Set
97
Instruc tion Se t
12.3.5 Ind e xe d , No Offse t
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Ind e xe d , 8-Bit Offse t
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Ind e xe d ,16-Bit Offse t
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler
determines the shortest form of indexed addressing.
General Release Specification
98
MC68HC05C4A — Rev. 4.0
Instruction Set
Instruction Set
Instruction Types
12.3.8 Re la tive
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
12.4 Instruc tion Typ e s
The MCU instructions fall into the following five categories:
• Register/Memory instructions
• Read-Modify-Write instructions
• Jump/Branch instructions
• Bit manipulation instructions
• Control instructions
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Instruction Set
Instruc tion Se t
12.4.1 Re g iste r/ Me m ory Instruc tions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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MC68HC05C4A — Rev. 4.0
Instruction Set
Instruction Set
Instruction Types
12.4.2 Re a d -Mod ify-Write Instruc tions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence be-
cause it does not write a replacement value.
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Instruction Set
Instruc tion Se t
12.4.3 Jum p / Bra nc h Instruc tions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Instruction Set
Instruction Types
Table 12-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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Instruction Set
Instruc tion Se t
12.4.4 Bit Ma nip ula tion Instruc tions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
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Instruction Set
Instruction Set
Instruction Types
12.4.5 Control Instruc tions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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General Release Specification
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Instruction Set
Instruc tion Se t
12.5 Instruc tion Se t Sum m a ry
Table 12-6. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
M oed
C
H I N Z C
O
A
O
ii
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
dd
hh ll
ee ff
ff
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
Add without Carry
Logical AND
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
A ← (A) + (M)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕ INH
C
0
IX1
IX
ff
b7
b7
b0
b0
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕ INH
IX1
IX
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
3
3
3
3
BEQ rel
BHCC rel
BHCS rel
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
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Instruction Set
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M
C
H I N Z C
O
A
O
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
22 rr
24 rr
3
3
3
3
BHS rel
BIH rel
BIL rel
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
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Instruction Set
Instruc tion Se t
Table 12-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
C
H I N Z C
O
A
O
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— — ↕ ↕ ↕
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— — ↕ ↕
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
— — ↕ ↕ ↕
— — ↕ ↕ —
— — ↕ ↕ —
— — ↕ ↕ —
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
General Release Specification
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Instruction Set
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M
C
H I N Z C
O
A
O
dd
hh ll
ee ff
ff
JMP opr
DIR
EXT CC
IX2
IX1
IX
BC
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Unconditional Jump
PC ← Jump Address
— — — — —
DC
EC
FC
dd
hh ll
ee ff
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
— — — — —
DD
ED
FD
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
X ← (M)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0 ↕ ↕ INH
b7
b0
IX1
IX
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
0 — — — 0
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ↕ ↕ ↕ INH
IX1
IX
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
A ← (A) (M)
— — ↕ ↕ —
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General Release Specification
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Instruction Set
Instruc tion Se t
Table 12-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
C
H I N Z C
O
A
O
dd
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39
49
59
69
79
5
3
3
6
5
C
Rotate Byte Left through Carry Bit
Rotate Byte Right through Carry Bit
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
dd
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
36
46
56
66
76
5
3
3
6
5
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— — ↕ ↕ —
— 0 — — —
— — ↕ ↕ —
STOP
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— — ↕ ↕ ↕
General Release Specification
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MC68HC05C4A — Rev. 4.0
Instruction Set
Instruction Set
Opcode Map
Table 12-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M
C
H I N Z C
O
A
O
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
— 1 — — —
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAX
Transfer Accumulator to Index Register
Test Memory Byte for Negative or Zero
X ← (A)
(M) – $00
A ← (X)
— — — — —
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
— — ↕ ↕ —
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr Operand (one or two bytes)
PC Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
SP Stack pointer
ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
X
Z
#
Index register
Zero flag
Immediate value
Logical AND
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode
Logical EXCLUSIVE OR
Contents of
( )
IX
IX1
IX2
M
N
n
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
–( ) Negation (two’s complement)
←
?
Loaded with
If
:
↕
—
Concatenated with
Set or cleared
Not affected
12.6 Op c od e Ma p
See Table 12-7.
MC68HC05C4A — Rev. 4.0
General Release Specification
111
Instruction Set
Table 12-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
BRCLR0
DIR 2
5
BRSET1
DIR 2
5
BRCLR1
DIR 2
5
BRSET2
DIR 2
5
BRCLR2
DIR 2
5
BRSET3
DIR 2
5
BRCLR3
DIR 2
5
BRSET4
DIR 2
5
BRCLR4
DIR 2
5
BRSET5
DIR 2
5
BRCLR5
DIR 2
5
BRSET6
DIR 2
5
BRCLR6
DIR 2
5
BRSET7
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
RTS
INH
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
CMP
IX2 2
IX1 1
4
CMP
IX1 1
IX
3
BCLR0
BRN
CMP
CMP
CMP
1
2
3
3
DIR 2
5
REL
3
1
IMM 2
2
DIR 3
3
EXT 3
4
IX
3
11
5
4
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
3
DIR 2
5
BCLR2 BCS/BLO
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BIT
BIT
BIT
5
5
3
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
LDA
DIR 3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
6
6
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
4
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
8
8
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
9
9
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR5
BMI
SEI
ADD
ADD
ADD
3
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
3
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR 2
5
DIR 2
5
BCLR7
DIR 2
REL
3
BIH
REL 2
1
INH
2
WAIT
INH 1
2
2
IMM 2
DIR 3
4
EXT 3
5
STX
EXT 3
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
TXA
INH
STX
3
DIR 2
IX1 1
IX 1
2
DIR 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB of Opcode in Hexadecimal
Number of Cycles
0
LSB
5
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 13. Ele c tric a l Sp e c ific a tions
13.1 Conte nts
13.2 Introduction.............................................................................113
13.3 Maximum Ratings...................................................................114
13.4 Operating Temperature Range...............................................115
13.5 Thermal Characteristics..........................................................115
13.6 Power Considerations.............................................................116
13.7 5.0 V DC Electrical Characteristics.........................................118
13.8 3.3 V DC Electrical Characteristics.........................................119
13.9 5.0 V Control Timing...............................................................122
13.10 3.3 V Control Timing...............................................................123
13.11 5.0 V Serial Peripheral Interface Timing.................................126
13.12 3.3 V Serial Peripheral Interface Timing.................................127
13.2 Introd uc tion
This section contains electrical and timing specifications.
MC68HC05C4A — Rev. 4.0
General Release Specification
Electrical Specifications
113
Ele c tric a l Sp e c ific a tions
13.3 Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Supply Voltage
Symbol
Value
Unit
V
–0.3 to +7.0
V
DD
Current Drain Per Pin, Excluding
I
25
mA
V
and V
DD
SS
V
– 0.3
SS
IRQ Pin Only
V
to 2 × V + 0.3
DD
Storage Temperature Range
TSTG
–65 to +150
°C
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0 V DC Electrical Characteristics and
13.8 3.3 V DC Electrical Characteristics for guaranteed operating
conditions.
General Release Specification
114
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
Operating Temperature Range
13.4 Op e ra ting Te m p e ra ture Ra ng e
Unit
Characteristic
Symbol
Value
T to T
0 to +70
–40 to +85
Operating Temperature Range
MC68HC05C4AP, FN, B, FB
MC68HC05C4ACP, CFN, CB, CFB
L
H
°C
T
A
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. C = Extended temperature range (–40°C to +85°C)
4. B = Shrink dual in-line-package (SDIP)
5. FB = Quad flat pack (QFP)
13.5 The rm a l Cha ra c te ristic s
Characteristic
Thermal Resistance
Symbol
Value
Unit
Plastic Dual In-Line Package (PDIP)
Plastic Leaded Chip Carrier (PLCC)
Quad Flat Pack (QFP)
60
70
95
60
θJA
°C/W
Plastic Shrink Dual In-Line Package (SDIP)
MC68HC05C4A — Rev. 4.0
General Release Specification
115
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.6 Powe r Consid e ra tions
The average chip-junction temperature, T , in °C, can be obtained from:
J
T = T + (P × θJA)
(1)
J
A
D
Where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction to ambient, °C/W.
JA
P = P
+ P
D
INT
I/O
P
P
= I
× V
DD
watts (chip internal power)
INT
I/O
DD
= Power dissipation on input and output pins (user-determined)
For most applications, P « P
and can be neglected.
I/O
INT
Following is an approximate relationship between P and T
D
J
neglecting P :
I/O
P = K ÷ (T + 273 °C)
(2)
(3)
D
J
Solving equations (1) and (2) for K gives:
K = P × (T + 273 °C) + θJA × (P ) )
2
D
A
D
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring P (at equilibrium) for a
D
known T . Using this value of K, the values of P and T can be obtained
A
D
J
by solving equations (1) and (2) iteratively for any value of T .
A
General Release Specification
116
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
Power Considerations
VDD = 4.5 V
Pins
V
DD
R1
R2
C
PA7–PA0
PB7–PB0
3.26 Ω
2.38 Ω
50 pF
R2
SEE TABLE
TEST
POINT
PC7–PC0
PD5–PD0, PD7
C
R1
SEE TABLE
SEE TABLE
VDD = 3.0 V
Pins
R1
R2
C
PA7–PA0
10.91 Ω
6.32 Ω
50 pF
PB7–PB0
PC7–PC0
PD5–PD0, PD7
Figure 13-1. Test Load
MC68HC05C4A — Rev. 4.0
General Release Specification
117
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.7 5.0 V DC Ele c tric a l Cha ra c te ristic s
Characteristic (Note 2)
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
Load = 10.0 µA
Load = –10.0 µA
VOL
VOH
—
DD–0.1
—
—
0.1
—
V
V
Output High Voltage
(ILoad = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –1.6 mA) PD4–PD1
(ILoad = –5.0 mA) PC7
VDD–0.8
—
—
—
—
—
—
VOH
V
V
V
V
DD–0.8
DD–0.8
Output Low Voltage
(ILoad = 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
VOL
—
—
—
—
0.4
0.4
(ILoad = 10 mA) PC7
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
—
VDD
V
V
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
0.2 × VDD
Supply Current (4.5–5.5 Vdc @ FBus= 2.1 MHz)
Run (Note 3)
Wait (Note 4)
—
—
3.50
1.00
5.25
3.25
mA
mA
Stop (Note 5)
IDD
25 °C
—
—
—
1
—
—
20
40
50
µA
µA
µA
0 °C to 70 °C (Standard)
–40 °C to +85 °C (Standard)
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
Ioz
—
—
±10
µA
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
IIn
IIn
—
—
±1
µA
µA
Input Pullup Current (Note 6)
PB7–PB0 (With Pullup)
60
140
300
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
COut
CIn
—
—
—
—
12
8
pF
NOTES:
1.
VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
4. Wait IDDmeasured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs
V
IL = 0.2 V, VIH = VDD–0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
General Release Specification
MC68HC05C4A — Rev. 4.0
118
Electrical Specifications
Electrical Specifications
3.3 V DC Electrical Characteristics
13.8 3.3 V DC Ele c tric a l Cha ra c te ristic s
Characteristic (Note 2)
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
= 10.0 µA
= –10.0 µA
V
—
—
—
0.1
—
V
Load
Load
OL
V
V
–0.1
OH
DD
Output High Voltage
(I
(I
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –0.4 mA) PD4–PD1
= –1.5 mA) PC7
V
V
V
–0.3
–0.3
–0.3
—
—
—
—
—
—
Load
Load
Load
DD
DD
DD
V
V
V
OH
Output Low Voltage
(I
= 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
= 6 mA) PC7
Load
V
—
—
—
—
0.3
0.3
OL
(I
Load
Input High Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
V
V
0.7 × V
—
—
V
DD
IH
DD
Input Low Voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
V
0.2 × V
DD
IL
SS
Supply Current (3.0–3.6 Vdc @ f
Run (Note 3)
Wait (Note 4)
= 1.0 MHz)
Bus
—
—
1.00
500
1.60
900
mA
µA
Stop (Note 5)
I
DD
25 °C
—
—
—
1
—
—
8
16
20
µA
µA
µA
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Standard)
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7–PB0 (Without Pullup)
PC7–PC0, PD7, PD5–PD0
I
—
—
±10
µA
OZ
Input Current
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
I
I
—
—
±1
µA
µA
In
In
Input Pullup Current (Note 6)
PB7–PB0 (With Pullup)
25
65
140
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
C
C
Out
—
—
—
—
12
8
pF
In
NOTES:
1.
VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs,
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs
V
IL = 0.2 V, VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
MC68HC05C4A — Rev. 4.0
General Release Specification
119
Electrical Specifications
Ele c tric a l Sp e c ific a tions
5.00 mA
VDD = 5.5 V
T = –40 °C TO 85°C
4.00 mA
3.00 mA
2.00 mA
1.00 mA
)
D
S PU P L Y UC R R EN T I(
50 µA
STOP IDD
MHZ
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-2. Maximum Supply Current
Versus Internal Clock Frequency, V = 5.5 V
DD
General Release Specification
120
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
3.3 V DC Electrical Characteristics
1.50 mA
1.00 mA
500 mA
V
DD = 3.6 V
T = –40 °C to 85 °C
)
D
S
STOP IDD
1.0 MHz
0.5 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-3. Maximum Supply Current
Versus Internal Clock Frequency, V = 3.6 V
DD
MC68HC05C4A — Rev. 4.0
General Release Specification
121
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.9 5.0 V Control Tim ing
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
f
—
dc
4.2
4.2
MHz
osc
Cycle Time
Crystal
External Clock
f
—
dc
2.1
2.1
MHz
op
Internal Clock Cycle Time
t
480
—
100
100
—
ns
ms
ms
cyc
Crystal Oscillator Startup Time
Stop Recovery Startup Time (Crystal Oscillator)
RESET Pulse Width
t
oxov
t
ilch
t
1.5
t
rl
cyc
Timer
Resolution (Note 2)
Input Capture Pulse Width
Input Capture Pulse Period
t
4.0
125
Note 3
—
—
—
t
ns
t
resl
, t
cyc
t
TH TL
t
TLTL
cyc
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
t
t
125
Note 4
90
—
—
—
ns
ILIL
t
ILIL
cyc
t
, t
ns
OH OL
NOTES:
1. VDD = 5.0 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc
4. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc
.
.
General Release Specification
122
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
3.3 V Control Timing
13.10 3.3 V Control Tim ing
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
f
—
dc
2.0
2.0
MHz
osc
Internal Operating Frequency
Crystal
External Clock
f
—
dc
1.0
1.0
MHz
op
Internal Clock Cycle Time
t
1000
—
100
100
—
ns
ms
ms
cyc
Crystal Oscillator Startup Time
Stop Recovery Startup Time (Crystal Oscillator)
RESET Pulse Width
t
oxov
t
ilch
t
1.5
t
rl
cyc
Timer
Resolution (Note 2)
Input Capture Pulse Width
Input Capture Pulse Period
t
4.0
250
Note 3
—
—
—
t
ns
t
resl
, t
cyc
t
TH TL
t
TLTL
cyc
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
t
250
Note 4
200
—
—
—
ns
ILIH
t
t
cyc
ILIL
t
, t
ns
OH OL
NOTES:
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it tkes to execute the capture interrupt
service routine plus 24 tcyc.
4. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc
.
tTH*
tTL*
tTLTL*
TCAP PIN
*Refer to timer resolution data in Section 8. Timer.
Figure 13-4. TCAP Timing Relationships
MC68HC05C4A — Rev. 4.0
General Release Specification
123
Electrical Specifications
Ele c tric a l Sp e c ific a tions
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tcyc cycles it takes to
execute the interrupt service routine plus 19 tcyc cycles.
tILIH
IRQ1
.
.
.
NORMALLY
USED WITH
WIRED-OR
IRQn
IRQ
INTERNAL
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt
is recognized.
Figure 13-5. External Interrupt Timing
INTERNAL
1
CLOCK
INTERNAL
1FFE
1FFE
1FFE
1FFE
1FFF
NEW PC
ADDRESS BUS1
INTERNAL
DATA BUS1
NEW
PCH
NEW
PCL
OP
CODE
RESET2
tRL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 13-6. External Reset Timing
General Release Specification
124
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
3.3 V Control Timing
OSC1
RESET
IRQ2
tRL
tILIH
4064 tcyc
IRQ3
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF4
NOTES:
RESET OR INTERRUPT
VECTOR FETCH
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
Figure 13-7. STOP Recovery Timing Diagram
(NOTE 1)
V
DD
2
OSC1 PIN
4064 tcyc
INTERNAL
3
CLOCK
INTERNAL
ADDRESS BUS3
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF
INTERNAL
DATA BUS3
NEW
PCH
NEW
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 13-8. Power-On Reset Timing Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
125
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.11 5.0 V Se ria l Pe rip he ra l Inte rfa c e Tim ing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
t
t
2.0
480
—
—
t
cyc
ns
cyc(M)
cyc(S)
Enable Lead Time
Master
Slave
t
†
240
—
—
ns
Lead(M)
t
Lead(S)
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
720
—
—
ns
ns
ns
ns
ns
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
Slave Access Time
(Time to Data Active from High-Impedance State)
8
9
tA
0
120
240
ns
ns
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
Data Valid
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
240
t
cyc(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise Time (20% V to 70% V , CL = 200 pF)
DD
DD
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall Time (70% V to 20% V , CL = 200 pF)
DD
DD
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
* VDD = 5.0 Vdc 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Section 8. Timer for timing diagrams.
† Signal production depends on software.
‡ Assumes 200 pF load on all SPI pins
General Release Specification
MC68HC05C4A — Rev. 4.0
126
Electrical Specifications
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
13.12 3.3 V Se ria l Pe rip he ra l Inte rfa c e Tim ing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
1.0
fOP
MHz
Cycle Time
Master
Slave
1
2
3
4
5
6
7
t
t
2.0
1.0
—
—
t
cyc
µs
cyc(M)
cyc(S)
Enable Lead Time
Master
Slave
t
†
500
—
—
ns
Lead(M)
t
Lead(S)
Enable Lag Time
Master
Slave
tLAG(M)
tLAG(S)
†
1.5
—
—
ns
µs
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
ns
ns
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
200
200
—
—
Slave Access Time
(Time to Data Active from High-Impedance State)
8
9
t
0
250
500
ns
ns
A
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
Data Valid
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
tV(M)
tV(S)
0.25
—
—
500
t
t
cyc(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
cyc(M)
ns
Rise Time (20% V to 70% V , CL = 200 pF)
DD
DD
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
200
2.0
ns
µs
Fall Time (70% V to 20% V , CL = 200 pF)
DD
DD
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
200
2.0
ns
µs
* VDD = 3.3 Vdc 0.3 Vdc;VSS = 0 Vdc, TA = TL to TH. Refer to Section 8. Timer for timing diagrams.
† Signal production depends on software.
‡ Assumes 200 pF load on all SPI pins
MC68HC05C4A — Rev. 4.0
Electrical Specifications
General Release Specification
127
Ele c tric a l Sp e c ific a tions
SS
(INPUT)
SS PIN OF MASTER HELD HIGH
1
12
13
12
13
5
4
SCK (CPOL = 0)
(OUTPUT)
NOTE
NOTE
4
5
12
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10 (ref)
11
MASTER MSB OUT
10
11 (ref)
MOSI
(OUTPUT)
MASTER LSB OUT
12
13
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS PIN OF MASTER HELD HIGH
1
13
12
12
SCK (CPOL = 0)
(OUTPUT)
5
NOTE
NOTE
4
13
SCK (CPOL = 1)
(OUTPUT)
5
4
6
7
MISO
MSB IN
11
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10 (ref)
10
11
MASTER LSB OUT
12
MOSI
(OUTPUT)
MASTER MSB OUT
13
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-9. SPI Master Timing Diagram
General Release Specification
128
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
SS
(INPUT)
1
13
12
3
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
SCK (CPOL = 1)
(INPUT)
8
12
11
13
SLAVE LSB OUT
11
9
MISO
(INPUT)
SLAVE MSB OUT
BITS 6–1
BITS 6–1
NOTE
10
6
7
MOSI
(OUTPUT)
MSB IN
LSB IN
NOTE: Not defined, but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
13
12
13
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
3
SCK (CPOL = 1)
(INPUT)
10
SLAVE MSB OUT
12
9
8
MISO
(OUTPUT)
NOTE
BITS 6–1
BITS 6–1
SLAVE LSB OUT
10
6
7
11
MOSI
(INPUT)
MSB IN
LSB IN
NOTE: Not defined, but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1)
Figure 13-10. SPI Slave Timing Diagram
MC68HC05C4A — Rev. 4.0
General Release Specification
129
Electrical Specifications
Ele c tric a l Sp e c ific a tions
General Release Specification
130
MC68HC05C4A — Rev. 4.0
Electrical Specifications
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 14. Me c ha nic a l Sp e c ific a tions
14.1 Conte nts
14.2 Introduction.............................................................................131
14.3 40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03)....................................................................132
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package
(Case 858-01)....................................................................132
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02)....................................................................133
14.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01)....................134
14.2 Introd uc tion
This section describes the dimensions of the dual in-line package (DIP),
plastic shrink dual in-line package (SDIP), plastic leaded chip carrier
(PLCC), and quad flat pack (QFP) MCU packages. Package dimensions
available at the time of this publication are provided in this section. To
make sure that you have the latest case outline specifications, contact
one of the following:
• Local Freescale Sales Office
.
MC68HC05C4A — Rev. 4.0
General Release Specification
Mechanical Specifications
131
Me c ha nic a l Sp e c ific a tions
14.3 40-Pin Pla stic Dua l In-Line (DIP) Pa c ka g e (Ca se 711-03)
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
40
21
20
B
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
B
C
D
F
51.69
13.72
3.94
0.36
1.02
52.45
14.22
5.08
0.56
1.52
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
L
A
C
N
2.54 BSC
0.100 BSC
G
H
J
K
L
J
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
K
SEATING
PLANE
M
H
G
F
D
15.24 BSC
0.600 BSC
0°
1°
0°
1°
M
N
0.51
1.02
0.020
0.040
14.4 42-Pin Pla stic Shrink Dua l In-Line (SDIP) Pa c ka g e (Ca se 858-01)
-A-
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
42
1
22
21
3. DIMENSION
FORMED PARALLEL.
4. DIMENSIONS AND
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
L
TO CENTER OF LEAD WHEN
-B-
A
B
DO NOT INCLUDE
MOLD
INCHES MILLIMETERS
MIN MAX MIN MAX
L
DIM
A
B
C
D
F
1.435 1.465 36.45 37.21
0.540 0.560 13.72 14.22
H
C
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
0.300 BSC
0.008 0.015
0.115 0.135
0.600 BSC
3.94
0.36
0.81
5.08
0.56
1.17
G
H
J
1.778 BSC
7.62 BSC
0.20
2.92
-T-
SEATING
PLANE
0.38
3.43
K
L
N
G
15.24 BSC
M
F
M
N
0° 15°
0.020 0.040
0°
0.51
15°
1.02
K
J 42 PL
0.25 (0.010M)
D 42 PL
S
B
0.25 (0.010M)
S
T A
T
General Release Specification
132
MC68HC05C4A — Rev. 4.0
Mechanical Specifications
Mechanical Specifications
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
14.5 44-Le a d Pla stic Le a d e d Chip Ca rrie r (PLCC) (Ca se 777-02)
M
S
S
N
0.007(0.180)
T
L-M
B
D
-N-
YBRK
-M-
M
S
S
0.007(0.180)
T
L-M
N
U
Z
-L-
V
X
G1
W
D
44
1
S
S
S
N
0.010 (0.25)
T
L-M
VIEW D-D
M
M
S
S
S
S
A
R
0.007(0.180)
0.007(0.180)
T
T
L-M
L-M
N
N
M
S
S
N
0.007(0.180)
T
L-M
H
Z
J
K1
E
0.004 (0.10)
G
K
C
SEATING
PLANE
-T-
G1
F
VIEW S
S
S
N
S
M
S
S
0.010 (0.25)
T
L-M
0.007(0.180)
T
L-M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1.DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETER-
DIM MIN
MAX
0.695
0.695
0.180
0.110
0.019
MIN
17.40
17.40
4.20
MAX
17.65
17.65
4.57
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
0.685
0.685
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.650
0.650
0.042
0.042
0.042
0.032
0.66
0.51
0.81
0.64
0.656
0.656
0.048
0.048
0.056
0.020
10°
16.51
16.51
1.07
1.07
1.07
16.66
16.66
1.21
1.21
1.42
0.50
10°
MINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940134). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
2°
2°
15.50
1.02
G1
K1
0.610
0.040
0.630
16.00
MC68HC05C4A — Rev. 4.0
General Release Specification
133
Mechanical Specifications
Me c ha nic a l Sp e c ific a tions
14.6 44-Le a d Qua d Fla t Pa c k (QFP) (Ca se 824A-01)
L
33
23
34
22
S
S
B
B
D
D
-A,B,D-
A
A
-A-
-B-
C
H
L
B
V
M
M
A
DETAIL A
DETAIL A
44
12
1
11
F
-D-
0.20 (0.008)
A
C
BASE METAL
M
S
A-B
S
D
0.05 (0.002A) -B
S
J
N
M
S
A-B
S
D
0.20 (0.008)
H
D
M
S
A-B
S
D
0.20 (0.008)
C
M
DETAIL C
SECTION B–B
E
C
DATUM
PLANE
-H-
-C-
SEATING
PLANE
0.01 (0.004)
H
G
M
MILLIMETERS
MIN MAX
INCHES
MIN MAX
NOTES:
DIM
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
D
9.90 10.10
9.90 10.10
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
M
B
C
2.10
0.30
2.45
0.45
2.10
0.40
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
E
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
2.00
0.30
T
F
0.80 BSC
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINGED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS AND
SEATING PLANE ĆCĆ.
6. DIMENSIONS AND
H
Ċ
0.25
0.23
0.95
Ċ
0.010
DATUM
-H-
S
V
B
TO BE DETERMINED AT
PLANE
J
0.13
0.65
0.005 0.009
0.026 0.037
0.315 REF
R
K
A
DO NOT INCLUDE MOLD
8.00 REF
L
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS B
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
M
5°
0.13
10°
0.17
7°
5°
0.005 0.007
0°
7°
10°
A
AND
DO
N
Q
0°
0.13
K
R
0.30
0.005 0.012
0.510 0.530
Q
D
W
S
12.95 13.45
T
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE
0.13
Ċ
Ċ
0.005
0°
Ċ
Ċ
X
D
U
0°
DIMENSION AT MAXIMUM MATERIAL CONDITION.
V
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
12.95 13.45
0.40
Ċ
1.6 REF
0.510 0.530
0.016
Ċ
0.063 REF
W
DETAIL C
X
General Release Specification
134
MC68HC05C4A — Rev. 4.0
Mechanical Specifications
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Se c tion 15. Ord e ring Inform a tion
15.1 Conte nts
15.2 Introduction.............................................................................135
15.3 MCU Ordering Forms .............................................................135
15.4 Application Program Media.....................................................136
15.5 ROM Program Verification......................................................137
15.6 ROM Verification Units (RVUs)...............................................138
15.7 MC Order Numbers ................................................................139
15.2 Introd uc tion
This section contains instructions for ordering custom-masked ROM
MCUs.
15.3 MCU Ord e ring Form s
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Freescale representative. Submit the
following items when ordering MCUs:
• A current MCU ordering form that is completely filled out
(Contact your Freescale sales office for assistance.)
• A copy of the customer specification, if the customer specification
deviates from the Freescale specification for the MCU.
• Customer’s application program on one of the media listed in 15.4
Application Program Media
MC68HC05C4A — Rev. 4.0
General Release Specification
Ordering Information
135
Ord e ring Inform a tion
The current MCU ordering form is also available through the Freescale
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lowercase letters.
Then press the return key to start the BBS software.
15.4 Ap p lic a tion Prog ra m Me d ia
Please deliver the application program to Freescale in one of the following
media:
®1
• Macintosh 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
®2
• MS-DOS or PC-DOSTM3 3 1/2-inch diskette (double-sided 720
K or double-sided high-density 1.44 M)
®
• MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
136
MC68HC05C4A — Rev. 4.0
Ordering Information
Ordering Information
ROM Program Verification
NOTE: Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. Refer to the current
MCU ordering form for additional requirements.Freescalemay request
pattern re-submission if non-user areas contain any non-zero code.
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Freescale keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
15.5 ROM Prog ra m Ve rific a tion
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Freescale inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Freescale sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Freescale will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
MC68HC05C4A — Rev. 4.0
General Release Specification
Ordering Information
137
Ord e ring Inform a tion
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the it to Freescale. The signed listing verify form
constitutes the contractual agreement for the creation of the custom
mask.
15.6 ROM Ve rific a tion Units (RVUs)
After receiving the signed listing verify form,Freescale manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Freescale then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Freescale Quality Assurance.
General Release Specification
138
MC68HC05C4A — Rev. 4.0
Ordering Information
Ordering Information
MC Order Numbers
15.7 MC Ord e r Num b e rs
Table 15-1 shows the MC order numbers for the available package
types.
Table 15-1. MC Order Numbers
Operating
Temperature
Range
Package Type
MC Order Number
40-Pin Plastic Dual In-Line Package
(DIP)
0 °C to 70 °C
0 °C to 70 °C
MC68HC05C4AP
MC68HC05C4AB
42-Pin Plastic Shrink Dual In-Line
Package (SDIP)
44-Lead Plastic Leaded Chip Carrier
(PLCC)
0 °C to 70 °C
0 °C to 70 °C
MC68HC05C4AFN
MC68HC05C4AFB
44-Lead Quad Flat Pack (QFP)
Extended Temperature Range
40-Pin Plastic Dual In-Line Package
(DIP)
–40 °C to +85 °C
–40 °C to +85 °C
MC68HC05C4ACP
MC68HC05C4ACB
42-Pin Plastic Shrink Dual In-Line
Package (SDIP)
44-Lead Plastic Leaded Chip Carrier
(PLCC)
–40 °C to +85 °C MC68HC05C4ACFN
–40 °C to +85 °C MC68HC05C4ACFB
44-Lead Quad Flat Pack (QFP)
MC68HC05C4A — Rev. 4.0
General Release Specification
139
Ordering Information
Ord e ring Inform a tion
General Release Specification
140
MC68HC05C4A — Rev. 4.0
Ordering Information
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Ap p e nd ix A. MC68HCL05C4A
A.1 Conte nts
A.2 Introduction.............................................................................141
A.3 Low-Power Operating Temperature Range............................141
A.4 2.5–3.6 V DC Electrical Characteristics..................................142
A.5 1.8–2.4 V DC Electrical Characteristics..................................142
A.6 Low-Power Supply Current.....................................................143
A.2 Introd uc tion
Appendix A introduces the MC68HCL05C4A, a low-power version of the
MC68HC05C4A. The technical data applying to the MC68HC05C4A
applies to the MC68HCL05C4A with the exceptions given in this
appendix.
A.3 Low-Powe r Op e ra ting Te m p e ra ture Ra ng e
The data here should replace the corresponding data found in 13.4
Operating Temperature Range.
Rating
Symbol
Value
T to T
Unit
Operating Temperature Range
MC68HCL05C4AP, FN, B, and FB
L
H
T
°C
A
0 to +70
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. B = Shrink dual in-line-package (SDIP)
4. FB = Quad flat pack (QFP)
MC68HC05C4A — Rev. 4.0
General Release Specification
141
MC68HCL05C4A
MC68HCL05C4A
A.4 2.5–3.6 V DC Ele c tric a l Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(I
(I
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –0.4 mA) PD4–PD1
= –1.5 mA) PC7
V
V
V
– 0.3
– 0.3
– 0.3
—
—
—
—
—
—
Load
Load
Load
DD
DD
DD
V
V
OH
Output Low Voltage
(I
= 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
= 5.0 mA) PC7
Load
V
I
—
—
—
—
0.3
0.3
V
OL
(I
Load
Input Pullup Current
PB7–PB0 with Pullup
10
55
120
µA
In
A.5 1.8–2.4 V DC Ele c tric a l Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(I
(I
(I
= –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –0.2 mA) PD4–PD1
= –0.75 mA) PC7
V
V
V
– 0.3
– 0.3
– 0.3
—
—
—
—
—
—
Load
Load
Load
DD
DD
DD
V
V
OH
Output Low Voltage
(I
= 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
= 2.0 mA) PC7
Load
V
I
—
—
—
—
0.3
0.3
V
OL
(I
Load
Input Pullup Current
PB7–PB0 with Pullup
3
45
75
µA
In
General Release Specification
142
MC68HC05C4A — Rev. 4.0
MC68HCL05C4A
MC68HCL05C4A
A.6 Low-Powe r Sup p ly Curre nt
Characteristic (Note 1)
Symbol
Min
Typ
Max
Unit
Supply Current (4.5–5.5 Vdc @ f
Run
Wait
Stop
= 2.1 MHz)
= 1.0 MHz)
= 500 kHz)
= 500 kHz)
Bus
Bus
Bus
Bus
—
—
3.50
1.6
4.25
2.25
mA
mA
I
I
I
I
DD
DD
DD
DD
25 °C
—
—
1
—
15
25
µA
µA
0 °C to +70 °C (Standard)
Supply Current (2.4–3.6 Vdc @ f
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
—
—
1.00
0.7
1.4
1.0
mA
mA
—
—
1
—
5
10
µA
µA
0 °C to +70 ° C (Standard)
Supply Current (2.5–3.6 Vdc @ f
Run
Wait
Stop
—
—
500
300
750
500
µA
µA
25 °C
—
—
1
—
5
10
µA
µA
0 °C to +70 °C (Standard)
Supply Current (1.8–2.4 Vdc @ f
Run
Wait
Stop
—
—
300
250
600
400
µA
µA
25 °C
—
—
1
—
2
5
µA
µA
0 °C to +70 °C (Standard)
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs;
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on
OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs; port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs; port B = VDD, all other inputs VIL = 0.2 V,
V
IL = VDD–0.2 V
MC68HC05C4A — Rev. 4.0
General Release Specification
143
MC68HCL05C4A
MC68HCL05C4A
General Release Specification
144
MC68HC05C4A — Rev. 4.0
MC68HCL05C4A
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Ap p e nd ix B. MC68HSC05C4A
B.1 Conte nts
B.2 Introduction.............................................................................145
B.3 High-Speed Operating Temperature Range...........................146
B.4 4.5 –5.5 V High-Speed Supply Currents.................................147
B.5 4.5–5.5 V High-Speed Control Timing....................................148
B.6 2.4–3.6 V High-Speed Control Timing....................................149
B.7 4.5 –5.5 V High-Speed SPI Timing.........................................150
B.8 2.4–3.6 V High-Speed SPI Timing..........................................151
B.2 Introd uc tion
Appendix B introduces the MC68HSC05C4A, a high-speed version of
the MC68HC05C4A. The technical data applying to the MC68HC05C4A
applies to the MC68HSC05C4A with the exceptions given in this
appendix.
MC68HC05C4A — Rev. 4.0
General Release Specification
MC68HSC05C4A
145
MC68HSC05C4A
B.3 Hig h-Sp e e d Op e ra ting Te m p e ra ture Ra ng e
The data here replaces the corresponding data in 13.4 Operating
Temperature Range.
Rating
Symbol
Value
Unit
Operating Temperature Range
MC68HSC05C4AP, FN, B, FB
MC68HSC05C4ACP, CFN, CB, CFB
TL to TH
0 to +70
–40 to +85
T
°C
A
NOTES:
1. P = Plastic dual in-line package (PDIP)
2. FN = Plastic-leaded chip carrier (PLCC)
3. C = Extended temperature range (–40° to +85°)
4. B = Shrink dual in-line-package (SDIP)
5. FB = Quad flat pack (QFP)
General Release Specification
146
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MC68HSC05C4A
B.4 4.5 –5.5 V Hig h-Sp e e d Sup p ly Curre nts
The data in 13.7 5.0 V DC Electrical Characteristics applies to the
MC68HSC05C4A with the exceptions given in this table.
Characteristic (Note 1)
Supply Current (4.5–5.5 Vdc @ f = 4.0 MHz)
Symbol
Min
Typ
Max
Unit
Bus
Run (Note 2)
Wait (Note 3)
—
—
7.00
2.00
11.0
6.50
mA
mA
Stop (Note 4)
25 °C
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
I
I
DD
—
—
—
1
—
—
20
40
50
µA
µA
µA
Supply Current (2.4–3.6 Vdc @ f
Run (Note 2)
Wait (Note 3)
= 2.0 MHz)
Bus
—
—
2.50
1.00
4.00
2.00
mA
mA
Stop (Note 4)
DD
25 °C
—
—
—
1
—
—
8
16
20
µA
µA
µA
0 °C to 70 °C (Standard)
–40 °C to 85 °C (Standard)
Input Pullup Current (V = 4.5–5.5 V)
PB7–PB0 with Pullup
DD
I
I
60
10
140
55
300
140
µA
µA
DD
DD
Input Pullup Current (V = 2.4–3.6 V)
DD
PB7–PB0 with Pullup
NOTES:
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs;
port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF
on OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other
inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is
affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs; port B = VDD, all other inputs VIL = 0.2 V,
V
IH = VDD–0.2 V
MC68HC05C4A — Rev. 4.0
General Release Specification
147
MC68HSC05C4A
MC68HSC05C4A
B.5 4.5–5.5 V Hig h-Sp e e d Control Tim ing
The data in 13.9 5.0 V Control Timing applies to the MC68HSC05C4A
with the exceptions in this table.
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
—
dc
8.2
8.2
MHz
f
osc
Internal Operating Frequency (f ÷ 2)
Crystal
External Clock
osc
—
dc
4.1
4.1
MHz
fOP
Cycle Time
t
244
—
100
100
—
ns
ms
ms
cyc
Crystal Oscillator Startup Time
Stop Recovery Startup Time
RESET Pulse Width
tOXOV
tILCH
tRL
1.5
t
cyc
Timer
Resolution (Note 1)
Input Capture Pulse Width
Input Capture Pulse Width
t
4.0
64
Note 2
—
—
—
t
ns
t
resl
cyc
tTH or tTL
tTHTL
cyc
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
tILIH
tILIL
64
Note 3
50
—
—
—
ns
t
cyc
tOH or tOL
ns
NOTES:
1. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc
3. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc
.
.
General Release Specification
148
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MC68HSC05C4A
B.6 2.4–3.6 V Hig h-Sp e e d Control Tim ing
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
—
dc
4.2
4.2
MHz
f
osc
Internal Operating Frequency (f ÷ 2)
Crystal
External Clock
osc
—
dc
2.1
2.1
MHz
fOP
Cycle Time
t
480
—
100
100
—
ns
ms
ms
cyc
Crystal Oscillator Startup Time
Stop Recovery Startup Time
RESET Pulse Width
tOXOV
tILCH
tRL
1.5
t
cyc
Timer
Resolution (Note 1)
Input Capture Pulse Width
Input Capture Pulse Width
t
4.0
125
Note 2
—
—
—
t
ns
t
resl
cyc
tTH or tTL
tTHTL
cyc
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
tILIH
tILIL
125
Note 3
90
—
—
—
ns
t
cyc
tOH or tOL
ns
NOTES:
1. Because a 2-bit prescaler in the timer must count four internal cycles (tcyc), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc
3. The minimum, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tcyc
.
.
MC68HC05C4A — Rev. 4.0
General Release Specification
149
MC68HSC05C4A
MC68HSC05C4A
B.7 4.5 –5.5 V Hig h-Sp e e d SPI Tim ing
The data in 13.11 5.0 V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given in the following table.
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
f
dc
dc
0.5
4.1
fOP
MHz
op(M)
op(S)
Cycle Time
Master
Slave
1
2
3
4
5
6
7
t
t
2.0
244
—
—
t
cyc
ns
cyc(M)
cyc(S)
Enable Lead Time
Master
Slave
t
†
122
—
—
ns
ns
Lead(M)
tLEAD(S)
Enable Lag Time
Master
Slave
t
†
366
—
—
ns
ns
Lag(M)
t
Lag(S)
Clock (SCK) High Time
Master
Slave
t
t
166
93
—
—
ns
ns
W(SCKH)M
W(SCKH)S
Clock (SCK) Low Time
Master
Slave
t
t
166
93
—
—
ns
ns
W(SCKL)M
W(SCKL)S
Data Setup Time (Inputs)
Master
Slave
t
t
49
49
—
—
ns
ns
SU(M)
SU(S)
Data Hold Time (Inputs)
Master
Slave
t
49
49
—
—
ns
ns
H(M)
t
H(S)
Slave Access Time
(Time to Data Active from High-Impedance State)
8
9
t
0
61
ns
ns
A
Slave Disable Time
(Hold Time to High-Impedance State)
t
—
122
DIS
Data Valid
10
11
12
13
Master (Before Capture Edge)
Slave (After Enable Edge)‡
t
t
0.25
—
—
122
t
t
V(M)
cyc(M)
ns
V(S)
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
t
0.25
0
—
—
HO(M)
cyc(M)
ns
t
HO(S)
Rise Time (20% V to 70% V , C = 200 pF)
DD
DD
L
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
—
—
50
1.0
ns
µs
RM
t
RS
Fall Time (70% V to 20% V , C = 200 pF)
DD
DD
L
tFM
tFS
—
—
50
1.0
ns
µs
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
†
‡
Signal production depends on software.
Assumes 200 pF load on all SPI pins.
General Release Specification
150
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
MC68HSC05C4A
B.8 2.4–3.6 V Hig h-Sp e e d SPI Tim ing
The data in 13.12 3.3 V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given in the following table.
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Slave
Cycle Time
Master
1
2
3
4
5
6
7
t
t
2.0
480
—
—
t
cyc
ns
cyc(M)
Slave
cyc(S)
Enable Lead Time
Master
tLead(M)
tLead(S)
†
240
—
—
ns
ns
Slave
Enable Lag Time
Master
tLag(M)
tLag(S)
†
720
—
—
ns
ns
Slave
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
ns
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
ns
Slave Access Time
(Time to Data Active from High-Impedance State)
tA
0
120
ns
8
9
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
240
ns
Data
Master (Before Capture Edge)
Slave (After Enable Edge)‡
10
11
12
13
tV(M)
tV(S)
0.25
—
—
240
t
t
cyc(M)
ns
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
cyc(M)
ns
Rise Time (20% V to 70% V , C = 200 pF)
DD
DD
L
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall Time (70% V to 20% V , C = 200 pF)
DD
DD
L
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
†
‡
Signal production depends on software.
Assumes 200 pF load on all SPI pins
MC68HC05C4A — Rev. 4.0
General Release Specification
151
MC68HSC05C4A
MC68HSC05C4A
General Release Specification
152
MC68HC05C4A — Rev. 4.0
MC68HSC05C4A
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05C4A
Ap p e nd ix C. M68HC05Cx Fa m ily Fe a ture Com p a risons
C.1 Conte nts
C.2 Introduction.............................................................................153
Table C-1. M68HC05Cx Feature Comparison .......................154
C.2 Introd uc tion
Refer to Table C-1 for a comparison of the features for all the
M68HC05C Family members.
MC68HC05C4A — Rev. 4.0
General Release Specification
153
Table C-1. M68HC05Cx Feature Comparison
C4
4160
—
C4A
4160
—
705C4A
—
C8
7744
—
C8A
7744
—
705C8
—
705C8A
—
C12
12,096
—
C12A
12,096
—
C9
C9A
705C9
705C9A
USER ROM
15,760-15,936 15,760-15,936
—
—
USER EPROM
4160
7596-7740
7596-7740
—
NO
—
15,760-15,936 12,096-15,936
CODE
SECURITY
NO
YES
176
YES
176
NO
YES
176
YES
YES
NO
YES
176
YES
NO
YES
RAM
176
176
176-304
176-304
176
176-352
176-352
176-352
176-352
OPTION
REGISTER
(IRQ/RAM/
SEC)
$1FDF
(IRQ/RAM/
SEC)
$1FDF
(IRQ/SEC)
$1FDF
(IRQ/RAM/SEC)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
MASK
OPTION
REGISTER(S)
$1FF0-1
NO
NO
$1FF0-1
NO
NO
NO
$3FF0-1
PORTB
KEYSCAN
(PULLUP/
YES
MOR
SELECT-
ABLE
YES
MASK
OPTION
YES
MASK
OPTION
YES
MOR
SELECTABLE
YES
MASK
OPTION
YES
MASK
OPTION
YES
MASK
OPTION
YES
MOR
SELECTABLE
NO
NO
NO
INTERRUPT)
HIGH
HIGH
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
PC7 DRIVE STANDARD
PD7, 5-0
STANDARD
STANDARD
PD7, 5-0
STANDARD
STANDARD
CURRENT CURRENT
PD7, 5-0
PD7, 5-0
INPUT
PD7, 5-0
INPUT
ONLY
PD7, 5-0
BIDIREC-
TIONAL
PD7, 5-0
BIDIREC-
TIONAL
PD7, 5-0
BIDIREC-
TIONAL
PD7, 5-0
BIDIREC-
TIONAL
PD7, 5-0
INPUT ONLY INPUT ONLY
PD7, 5-0
INPUT ONLY
PD7, 5-0
INPUT ONLY INPUT ONLY
PD7, 5-0
PORT D
INPUT
ONLY
INPUT ONLY
ONLY
COP
NO
—
YES
YES
NO
—
YES
YES
TWO TYPES
YES
YES
YES
YES
YES
TWO TYPES
MASK
OPTION
MASK
OPTION
SOFTWARE+
MOR
MASK
OPTION
MASK
OPTION
SOFTWARE+
MOR
COP ENABLE
MOR
SOFTWARE
SOFTWARE
SOFTWARE
SOFTWARE
64 ms
(@4 MHz
osc)
64 ms
(@4 MHz
osc)
SOFTWARE+
MOR
SELECTABLE
SOFTWARE+
MOR
SELECTABLE
COP
TIMEOUT
64 ms
SOFTWARE
64 ms
64 ms
SOFTWARE
SOFTWARE
SOFTWARE
—
—
(@4 MHz osc) SELECTABLE
(@4 MHz osc) (@4MHz osc) SELECTABLE SELECTABLE SELECTABLE
WRITE $55/$AA
TO $001D
OR
WRITE $55/$AA
TO $001D
OR
WRITE
$55/$AA
TO $001D
WRITE
$55/$AA
TO $001D
WRITE
$55/$AA
TO $001D
WRITE
$55/$AA
TO $001D
COP CLEAR
—
CLR $1FF0 CLR $1FF0
—
CLR $1FF0
NO
CLR $3FF0
NO
CLR $3FF0
NO
CLR $1FF0
CLR $3FF0
CLOCK
MONITOR
YES
(C9A MODE)
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
PROGRAM-
MABLE
COP/CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/C9A COP/
CLOCK
MONITOR
ACTIVE
RESET
COP/CLOCK
MONITOR
NO
NO
NO
MOR
SELECTABLE
(C12A MODE)
STOP
DISABLE
MASK
OPTION
MASK
OPTION
MASK
OPTION
MASK
OPTION
NO
NO
NO
NO
NO
NO
NO
NO
NOTES:
1. The expanded RAM map (from $30–$4F and $100–$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A.
2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
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© Motorola, Inc., 1997
HC05C4AGRS/D
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