MC8640VU1067NE_技术文档

Document Number: MPC8640D

Rev. 4, 05/2014

Freescale Semiconductor

Technical Data

MPC8640 and MPC8640D

Integrated Host Processor

Hardware Specifications

Contents

1 Overview

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management 26

The MPC8640 processor family integrates either one or two

Power Architecture™ e600 processor cores with system

logic required for networking, storage, wireless

infrastructure, and general-purpose embedded applications.

The MPC8640 integrates one e600 core while the

MPC8640D integrates two cores.

9. Ethernet Management Interface Electrical

This section provides a high-level overview of the MPC8640

and MPC8640D features. When referring to the MPC8640

throughout the document, the functionality described applies

to both the MPC8640 and the MPC8640D. Any differences

specific to the MPC8640D are noted.

Characteristics 40

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 57

14. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

15. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

16. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

17. Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

18. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

20. System Design Information . . . . . . . . . . . . . . . . . . 116

21. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 126

22. Document Revision History . . . . . . . . . . . . . . . . . . 128

Figure 1 shows the major functional units within the

MPC8640 and MPC8640D. The major difference between

the MPC8640 and MPC8640D is that there are two cores on

the MPC8640D.

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

Overview

e600 Core Block

e600 Core

1-Mbyte

L2 Cache

1-Mbyte

L2 Cache

32-Kbyte

L1 Instruction Cache

32-Kbyte

L1 Instruction Cache

L1 Data Cache

MPX Bus

MPX Coherency Module (MCM)

Platform Bus

Platform

SDRAM

DDR SDRAM Controller

ROM,

GPIO

Local Bus Controller

(LBC)

Multiprocessor

Programmable Interrupt

Controller

IRQs

(MPIC)

Dual Universal

Asynchronous

Receiver/Transmitter

(DUART)

Serial

I²C

I²C Controller

Serial RapidIO

Interface

or

Enhanced TSEC

Controller

PCI Express

Interface

OCeaN

Switch

Fabric

RMII, GMII,

MII, RGMII,

TBI, RTBI

[ x1/x2/x4/x8 PCI Exp (4 GB/s)

AND 1x/4x SRIO (2.5 GB/s) ]

10/100/1Gb

OR [2-x1/x2/x4/x8 PCI Express

(8 GB/S) ]

Enhanced TSEC

Controller

RMII, GMII,

MII, RGMII,

TBI, RTBI

PCI Express

Interface

10/100/1Gb

Enhanced TSEC

Controller

RMII, GMII,

MII, RGMII,

TBI, RTBI

Four-Channel

DMA Controller

External

Control

10/100/1Gb

Enhanced TSEC

Controller

RMII, GMII,

MII, RGMII,

TBI, RTBI

10/100/1Gb

Figure 1. MPC8640 and MPC8640D

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

2

Overview

1.1

Key Features

The following lists the MPC8640 key feature set:

•

Major features of the e600 core are as follows:

— High-performance, 32-bit superscalar microprocessor that implements the PowerPC

instruction set architecture (ISA)

— Eleven independent execution units and three register files

– Branch processing unit (BPU)

– Four integer units (IUs) that share 32 GPRs for integer operands

– 64-bit floating-point unit (FPU)

– Four vector units and a 32-entry vector register file (VRs)

– Three-stage load/store unit (LSU)

— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle.

— Rename buffers

— Dispatch unit

— Completion unit

— Two separate 32-Kbyte instruction and data level 1 (L1) caches

— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache

with ECC

— 36-bit real addressing

— Separate memory management units (MMUs) for instructions and data

— Multiprocessing support features

— Power and thermal management

— Performance monitor

— In-system testability and debugging features

— Reliability and serviceability

•

MPX coherency module (MCM)

— Ten local address windows plus two default windows

— Optional low memory offset mode for core 1 to allow for address disambiguation

Address translation and mapping units (ATMUs)

— Eight local access windows define mapping within local 36-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

— Three inbound windows plus a configuration window on PCI Express® interface unit

— Four inbound windows plus a default window on serial RapidIO interface unit

— Four outbound windows plus default translation for PCI Express interface unit

— Eight outbound windows plus default translation for serial RapidIO® interface unit with

segmentation and subsegmentation support

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

3

Overview

•

DDR memory controllers

— Dual 64-bit memory controllers (72-bit with ECC)

— Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM

— Support for DDR, DDR2 SDRAM

— Up to 16 Gbytes per memory controller

— Cache line and page interleaving between memory controllers.

Serial RapidIO interface unit

•

— Supports RapidIO Interconnect Specification, Revision 1.2

— Both 1× and 4× LP-Serial link interfaces

— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per

lane

— Message unit compliant with RapidIO specifications

— RapidIO atomic transactions to the memory controller

PCI Express interface

•

— PCI Express 1.0a compatible

— Supports ×1, ×2, ×4, and ×8 link widths

— 2.5 Gbaud, 2.0 Gbps lane

Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four controllers that comply with IEEE Std. 802.3®, 802.3u®, 802.3x®, 802.3z®, 802.3ac®,

802.3ab® standards

— Support for the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI

— Support for a full-duplex FIFO mode for high-efficiency ASIC connectivity

— TCP/IP off-load

— Header parsing

— Quality of service support

— VLAN insertion and deletion

— MAC address recognition

— Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III

programming models

— RMON statistics support

— MII management interface for control and status

•

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts and 48 internal interrupts

— Eight global high resolution timers/counters that can generate interrupts

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

4

Freescale Semiconductor

Overview

— Allows processors to interrupt each other with 32b messages

— Support for PCI-Express message-shared interrupts (MSIs)

Local bus controller (LBC)

•

— Multiplexed 32-bit address and data operating at up to 125 MHz

— Eight chip selects support eight external slaves

Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and the remote masters

— Supports transfers to or from any local memory or I/O port

— Ability to start and flow control each DMA channel from external 3-pin interface

Device performance monitor

•

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

2

•

Dual I C controllers

— Two-wire interface

— Multiple master support

2

— Master or slave I C mode support

— On-chip digital filtering rejects spikes on the bus

Boot sequencer

2

— Optionally loads configuration data from serial ROM at reset via the I C interface

— Can be used to initialize configuration registers and/or memory

2

— Supports extended I C addressing mode

— Data integrity checked with preamble signature and CRC

DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

IEEE 1149.1™-compliant, JTAG boundary scan

•

Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

5

Electrical Characteristics

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8640. The MPC8640 is currently targeted to these specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

1

Table 1. Absolute Maximum Ratings

Absolute Maximum

Value

Parameter

Symbol

Unit Notes

Cores supply voltages

Cores PLL supply

V_DD_Core0,

V_DD_Core1

–0.3 to 1.21 V

V

2

AV_DD_Core0,

AV_DD_Core1

–0.3 to 1.21 V

—

SerDes Transceiver Supply (Ports 1 and 2)

SerDes Serial I/O Supply Port 1

SV_DD

–0.3 to 1.21 V

–0.3 to 1.21V

V

—

XV_{DD_}SRDS1

XV_{DD_}SRDS2

SerDes Serial I/O Supply Port 2

SerDes DLL and PLL supply voltage for Port 1 and Port 2

AV_DD_SRDS1,

AV_DD_SRDS2

Platform Supply voltage

V

_DD_PLAT

–0.3 to 1.21V

V

—

Local Bus and Platform PLL supply voltage

AV_DD_LB,

AV_DD_PLAT

DDR and DDR2 SDRAM I/O supply voltages

eTSEC 1 and 2 I/O supply voltage

D1_GV_DD,

D2_GV_DD

–0.3 to 2.75 V

–0.3 to 1.98 V

–0.3 to 3.63 V

–0.3 to 2.75 V

–0.3 to 3.63 V

–0.3 to 2.75 V

–0.3 to 3.63V

V

3

LV_DD

TV_DD

OV_DD

4

eTSEC 3 and 4 I/O supply voltage

4

Local Bus, DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management, I²C,

JTAG and Miscellaneous I/O voltage

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

6

Electrical Characteristics

1

Table 1. Absolute Maximum Ratings (continued)

Absolute Maximum

Parameter

Symbol

Unit Notes

Value

Input voltage

DDR and DDR2 SDRAM signals

DDR and DDR2 SDRAM reference

Dn_MV_IN

–0.3 to (Dn_GV_DD+ 0.3)

V

5

Dn_MV_REF

–0.3 to (Dn_GV_DD÷ 2 +

—

0.3)

Three-speed Ethernet signals

LV_IN

TV_IN

GND to (LV_DD+ 0.3)

GND to (TV_DD+ 0.3)

V

5

DUART, Local Bus, DMA,

OV_IN

GND to (OV_DD+ 0.3)

Multiprocessor Interrupts, System

Control and Clocking, Debug, Test,

Power management, I²C, JTAG

and Miscellaneous I/O voltage

Storage temperature range

T_STG

–55 to 150

^oC

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Core 1 characteristics apply only to MPC8640D. If two separate power supplies are used for V_DD_Core0 and V_DD_Core1,

they must be kept within 100 mV of each other during normal run time.

3. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.

4. The 3.63 V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75 V

maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on

the recommended operating conditions per protocol.

5. During run time (M,L,T,O)V_INand Dn_MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown

in Figure 2.

2.1.2

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8640. Note that the values in Table 2

are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed. For details on order information and specific operating conditions for parts, see

Section 21, “Ordering Information.”

Table 2. Recommended Operating Conditions

Recommended

Parameter

Symbol

Unit

Notes

Value

Cores supply voltages

Cores PLL supply

V_DD_Core0,

V_DD_Core1

1.05 50 mV

0.95 50 mV

1.05 50 mV

0.95 50 mV

1.05 50 mV

V

1, 2

1, 2, 10

11

AV_DD_Core0,

AV_DD_Core1

V

10, 11

9

SerDes Transceiver Supply (Ports 1 and 2)

SerDes Serial I/O Supply Port 1

SV_DD

V

XV_{DD_}SRDS1

XV_{DD_}SRDS2

—

SerDes Serial I/O Supply Port 2

—

SerDes DLL and PLL supply voltage for Port 1 and Port 2

AV_DD_SRDS1,

AV_DD_SRDS2

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

7

Electrical Characteristics

Table 2. Recommended Operating Conditions (continued)

Recommended

Parameter

Symbol

Unit

Notes

Value

Platform supply voltage

V_DD_PLAT

1.05 50 mV

V

—

Local Bus and Platform PLL supply voltage

AV_DD_LB,

AV_DD_PLAT

DDR and DDR2 SDRAM I/O supply voltages

D1_GV_DD,

D2_GV_DD

2.5 V 125 mV

1.8 V 90 mV

3.3 V 165 mV

2.5 V 125 mV

3.3 V 165 mV

2.5 V 125 mV

3.3 V 165 mV

V

7

8

5

eTSEC 1 and 2 I/O supply voltage

eTSEC 3 and 4 I/O supply voltage

LV_DD

TV_DD

OV_DD

V

Local Bus, DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management, I²C,

JTAG and Miscellaneous I/O voltage

Input voltage

DDR and DDR2 SDRAM signals

DDR and DDR2 SDRAM reference

Three-speed Ethernet signals

Dn_MV_IN

GND to Dn_GV_DD

Dn_GV_DD/2 1%

V

3, 6

—

Dn_MV_REF

LV_IN

TV_IN

GND to LV_DD

GND to TV_DD

4, 6

DUART, Local Bus, DMA,

OV_IN

GND to OV_DD

V

5,6

Multiprocessor Interrupts, System

Control & Clocking, Debug, Test,

Power management, I²C, JTAG

and Miscellaneous I/O voltage

Junction temperature range

T_J

0 to 105

^oC

—

–40 to 105

12

Notes:

1. Core 1 characteristics apply only to MPC8640D

2. If two separate power supplies are used for V_DD_Core0 and V_DD_Core1, they must be at the same nominal voltage and the

individual power supplies must be tracked and kept within 100 mV of each other during normal run time.

3. Caution: Dn_MV_INmust meet the overshoot/undershoot requirements for Dn_GV_DDas shown in Figure 2.

4. Caution: L/TV_INmust meet the overshoot/undershoot requirements for L/TV_DDas shown in Figure 2 during regular run time.

5. Caution: OV_INmust meet the overshoot/undershoot requirements for OV_DDas shown in Figure 2 during regular run time.

6. Timing limitations for M,L,T,O)V_INand Dn_MV_REFduring regular run time is provided in Figure 2

7. The 2.5 V 125 mV range is for DDR and 1.8 V 90 mV range is for DDR2.

8. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended

operating conditions per protocol.

9. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to

Section 14.4.3, “Differential Receiver (Rx) Input Specifications.”

10. Applies to Part Number MC8640wxx1067Nz only. V_DD_Coren = 0.95 V and V_DD_PLAT = 1.05 V devices. Refer to Table 74

Part Numbering Nomenclature to determine if the device has been marked for V_DD_Coren = 0.95 V.

11. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing,” and not necessarily

the voltage at the AV_DD_Coren pin, which may be reduced from V_DD_Coren by the filter.

12. Applies to part number MC8640DTxxyyyyaz. Refer to Table 74 Part Numbering Nomenclature to determine if the device

has been marked for extended operating temperature range.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

8

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640.

L/T/Dn_G/O/X/SV_DD+ 20%

L/T/Dn_G/O/X/SV_DD+ 5%

L/T/Dn_G/O/X/SV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_CLK

Note:

1. t_CLKreferences clocks for various functional blocks as follows:

DDRn = 10% of Dn_MCK period

eTSECn = 10% of ECn_GTX_CLK125 period

Local Bus = 10% of LCLK[0:2] period

I2C = 10% of SYSCLK

JTAG = 10% of SYSCLK

Figure 2. Overshoot/Undershoot Voltage for Dn_M/O/L/TV

IN

The MPC8640 core voltage must always be provided at nominal V _Coren (See Table 2 for actual

DD

recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of

supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with

respect to the associated I/O supply voltage. OV and L/TV based receivers are simple CMOS I/O

DD

circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended differential receiver referenced to each externally supplied Dn_MV signal (nominally set

REF

to Dn_GV /2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.

DD

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

9

Electrical Characteristics

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 3. Output Drive Capability

Programmable

Supply

Driver Type

Output Impedance

Notes

Voltage

(Ω)

DDR1 signal

18

Dn_GV_DD= 2.5 V

4, 9

1, 5, 9

2, 6

36 (half strength mode)

DDR2 signal

18

Dn_GV_DD= 1.8 V

36 (half strength mode)

Local Bus signals

eTSEC/10/100 signals

45

25

OV_DD= 3.3 V

45

30

45

T/LV_DD= 3.3 V

T/LV_DD= 2.5 V

OV_DD= 3.3 V

6

DUART, DMA, Multiprocessor Interrupts, System Control &

Clocking, Debug, Test, Power management, JTAG and

Miscellaneous I/O voltage

I²C

150

100

OV_DD= 3.3 V

7

SRIO, PCI Express

SV_DD= 1.1/1.05 V

3, 8

Notes:

1. See the DDR Control Driver registers in the MPC8641D reference manual for more information.

2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE,

LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive

strength of 45 Ω. See the POR Impedance Control register in the MPC8641D reference manual for more information about

local bus signals and their drive strength programmability.

3. See Section 17, “Signal Listings,” for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and

SDn_IMP_CAL_RX transmit and receive signals.

4. Stub Series Terminated Logic (SSTL-25) type pins.

5. Stub Series Terminated Logic (SSTL-18) type pins.

6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.

7. Open Drain type pins.

8. Low Voltage Differential Signaling (LVDS) type pins.

9. The drive strength of the DDR interface in half strength mode is at T_j= 105C and at Dn_GV_DD(min).

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

Electrical Characteristics

2.2

Power-Up/Down Sequence

The MPC8640 requires its power rails to be applied in a specific sequence to ensure proper device

operation.

NOTE

The recommended maximum ramp up time for power supplies is 20

milliseconds.

The chronological order of power up is:

1. All power rails other than DDR I/O (Dn_GV , and Dn_MV ).

DD

REF

NOTE

There is no required order sequence between the individual rails for this

item (# 1). However, V _PLAT, AV _PLAT rails must reach 90% of

DD

their recommended value before the rail for Dn_GV , and Dn_MV

(in

DD

REF

next step) reaches 10% of their recommended value. AV type supplies

DD

must be delayed with respect to their source supplies by the RC time

constant of the PLL filter circuit described in Section 20.2.1, “PLL Power

Supply Filtering.”

2. Dn_GV , Dn_MV

DD

REF

NOTE

It is possible to leave the related power supply (Dn_GV , Dn_MV

)

REF

DD

turned off at reset for a DDR port that will not be used. Note that these power

supplies can only be powered up again at reset for functionality to occur on

the DDR port.

3. 3. SYSCLK

The recommended order of power down is as follows:

1. Dn_GV , Dn_MV

DD

REF

2. All power rails other than DDR I/O (Dn_GV , Dn_MV ).

DD

REF

NOTE

SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in

the power down sequence. Beyond this, the power supplies may power

down simultaneously if the preservation of DDRn memory is not a concern.

See Figure 3 for more details on the power and reset sequencing details.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

11

Electrical Characteristics

Figure 3 illustrates the power up sequence as described above.

3.3 V

L/T/OV_DD

If

L/TV =2.5 V

1

DD

2.5 V

Dn_GV_DD, = 1.8/2.5 V

Dn_MV_REF

1.8 V

1.2 V

V_DD_PLAT, AV_DD_PLAT

AV_DD_LB, SV_DD, XV_DD_SRDSn

AV_DD_SRDSn

V_DD_Coren, AV_DD_Coren

100 µs Platform PLL

7

Relock Time ³

0

Power Supply Ramp Up ²

Time

SYSCLK ⁸

(not drawn to scale)

9

HRESET (& TRST)

Asserted for

5

e600

PLL

100 μs after

SYSCLK is functional ⁴

Reset

Configuration Pins

Cycles Setup and hold Time ⁶

Notes:

1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2.

2. The recommended maximum ramp up time for power supplies is 20 milliseconds.

3. Refer to Section 5, “RESET Initialization,” for additional information on PLL relock and reset signal

assertion timing requirements.

4. Refer to Table 11 for additional information on reset configuration pin setup timing requirements. In

addition see Figure 68 regarding HRESET and JTAG connection details including TRST.

5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.

6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration

inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles

after HRESET has negated (hold requirement). See Section 5, “RESET Initialization,” for more

information on setup and hold time of reset configuration signals.

7. V_DD_PLAT, AV_DD_PLAT must strictly reach 90% of their recommended voltage before the rail for

Dn_GV_DD, and Dn_MV_REFreaches 10% of their recommended voltage.

8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.

9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)

must be valid BEFORE HRESET is asserted.

Figure 3. MPC8640 Power-Up and Reset Sequence

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

Power Characteristics

3 Power Characteristics

The power dissipation for the dual core MPC8640D device is shown in Table 4.

Table 4. MPC8640D Power Dissipation (Dual Core)

V_DD_Coren,

Core Frequency

(MHz)

Platform

Frequency (MHz)

Junction

Temperature

Power

(Watts)

Power Mode

V_DD_PLAT

Notes

(Volts)

Typical

65 ^oC

21.7

27.3

31

1, 2

1, 3

Thermal

Maximum

Typical

1250 MHz

1000 MHz

1067 MHz

500 MHz

533 MHz

1.05 V

105 ^oC

65 ^oC

1, 4

18.9

23.8

27

1, 2

Thermal

Maximum

Typical

1, 3

105 ^oC

65 ^oC

1, 4

15.7

19.5

22

1, 2, 5

1, 3, 5

1, 4, 5

Thermal

Maximum

Notes:

0.95/1.05 V

105 ^oC

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (V_DD_Coren) and 65 °C junction

temperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with one core

at 100% efficiency and the second core at 65% efficiency.

3. Thermal power is the average power measured at nominal core voltage (V_DD_Coren) and maximum operating junction

temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on both cores

and a typical workload on platform interfaces.

4. Maximum power is the maximum power measured at nominal core voltage (V_DD_Coren) and maximum operating junction

temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions

which keep all the execution units maximally busy on both cores.

5. These power numbers are for Part Number MC8640Dwxx1067Nz and MC8640wxx1067Nz only. V_DD_Coren = 0.95 V and

V_DD_PLAT = 1.05 V.

The power dissipation for individual power supplies of the MPC8640D is shown in Table 5.

1

Table 5. MPC8640D Individual Supply Maximum Power Dissipation

Supply Voltage

(Volts)

Power

(Watts)

Component Description

Notes

Per Core voltage Supply

Per Core PLL voltage supply

Per Core voltage Supply

V_DD_Core0/V_DD_Core1 = 1.05 V at 1250 MHz

AV_DD_Core0/AV_DD_Core1 = 1.05 V at 1250 MHz

17.00

0.0125

15.00

0.0125

11.50

0.0125

0.80

—

5

V

_DD_Core0/V_DD_Core1 = 1.05 V at 1000 MHz

Per Core PLL voltage supply

Per Core voltage Supply

AV_DD_Core0/AV_DD_Core1 = 1.05 V at 1000 MHz

V_DD_Core0/V_DD_Core1 = 0.95 V at 1067 MHz

AV_DD_Core0/AV_DD_Core1 = 0.95 V at 1067 MHz

Dn_GV_DD= 2.5 V at 400 MHz

Per Core PLL voltage supply

DDR Controller I/O voltage supply

5

2, 6

Dn_GV_DD= 1.8 V at 533 MHz

0.68

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

13

Power Characteristics

1

Table 5. MPC8640D Individual Supply Maximum Power Dissipation (continued)

Supply Voltage

(Volts)

Power

(Watts)

Component Description

Notes

16-bit FIFO @ 200 MHz

L/TV_DD= 3.3 V

0.11

2, 3, 6

eTsec 1&2/3&4 Voltage Supply

non-FIFO eTsecn Voltage Supply

x8 SerDes transceiver Supply

x8 SerDes I/O Supply

L/TV_DD= 3.3 V

SV_DD= 1.05 V

0.08

0.70

0.66

0.10

0.45

3.5

2, 6

4, 6

—

XV_DD_SRDSn = 1.05 V

SerDes PLL voltage supply Port 1 or 2

Platform I/O Supply

AV_DD_SRDS1/AV_DD_SRDS2 = 1.05 V

OV_DD= 3.3 V

Platform source Supply

V_DD_PLAT = 1.05 V at 533 MHz

V_DD_PLAT = 1.05 Vn at 500 MHz

AV_DD_PLAT, AV_DD_LB = 1.1 V

Platform source Supply

3.5

5

Platform, Local Bus PLL voltage Supply

0.0125

—

Notes:

1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are

based on 100% bus utilization for each component. The components listed are not expected to have 100% bus usage

simultaneously for all components. Actual numbers may vary based on activity.

2. Number is based on a per port/interface value.

3. This is based on one eTSEC port used. Since 16-bit FIFO mode involves two ports, the number will need to be multiplied by

two for the total. The other eTSEC protocols dissipate less than this number per port. Note that the power needs to be

multiplied by the number of ports used for the protocol for the total eTSEC port power dissipation.

4.Platform I/O includes local bus, DUART, I²C, DMA, multiprocessor interrupts, system control and clocking, debug, test, power

management, JTAG and miscellaneous I/O voltage.

5. Power numbers with V_DD_Coren = 0.95 V and V_DD_PLAT = 1.05 V are for Part Number MC8640xxx1067Nz only.

6. The maximum power supply number for the I/Os are estimates.

The power dissipation for the MPC8640 single core device is shown in Table 6.

Table 6. MPC8640 Power Dissipation (Single Core)

V_DD_Coren,

V_DD_PLAT

(Volts)

Core Frequency

(MHz)

Platform

Frequency (MHz)

Junction

Temperature

Power

(Watts)

Power Mode

Notes

Typical

65 ^oC

13.3

16.5

19

1, 2

1, 3

1, 4

1, 2

1, 3

1, 4

Thermal

Maximum

Typical

1250 MHz

1000 MHz

500 MHz

1.05 V

105 ^oC

65 ^oC

11.9

14.8

17

Thermal

Maximum

105 ^oC

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

14

Input Clocks

Notes

Table 6. MPC8640 Power Dissipation (Single Core) (continued)

V_DD_Coren,

Core Frequency

(MHz)

Platform

Junction

Power

Power Mode

V_DD_PLAT

(Volts)

Frequency (MHz)

Temperature

(Watts)

Typical

65 ^oC

10.1

12.3

14

1, 2, 5

1, 3, 5

1, 4, 5

Thermal

Maximum

Notes:

1067 MHz

533 MHz

0.95 V,

1.05 V

105 ^oC

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (V_DD_Coren) and 65 °C junction

temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Thermal power is the average power measured at nominal core voltage (V_DD_Coren) and maximum operating junction

temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz and a typical

workload on platform interfaces.

4. Maximum power is the maximum power measured at nominal core voltage (V_DD_Coren) and maximum operating junction

temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of

instructions which keep all the execution units maximally busy.

5. These power numbers are for Part Number MC8640Dwxx1067Nz and MC8640wxx1067Nz only. V_DD_Coren = 0.95 V and

V_DD_PLAT = 1.05 V.

4 Input Clocks

Table provides the system clock (SYSCLK) DC specifications for the MPC8640.

Table 7. SYSCLK DC Electrical Characteristics (OV = 3.3 V 165 mV)

DD

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

–0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= V_DD)

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

4.1

System Clock Timing

Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8640.

Table 8. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV_DD= 3.3 V 165 mV.

Parameter

SYSCLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_SYSCLK

t_SYSCLK

t_KH, t_KL

66

6

—

166.66

—

MHz

ns

1

—

2

SYSCLK cycle time

SYSCLK rise and fall time

0.6

1.0

1.2

ns

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

15

Input Clocks

Table 8. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions (see Table 2) with OV_DD= 3.3 V 165 mV.

Parameter

SYSCLK duty cycle

Symbol

Min

Typical

Max

Unit

Notes

t_KHK/t_SYSCLK

—

40

—

60

%

3

SYSCLK jitter

150

ps

4, 5

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL

Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the short term jitter only and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation

for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on

design.

4.1.1

SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 8 considers

short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the

MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns,

and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in Table 9 are

observed.

Table 9. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Table 2.

Parameter

Min

Max

Unit

Notes

Frequency modulation

Frequency spread

—

50

kHz

%

1

1.0

1, 2

Notes:

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Table 8.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated e600 core frequency should avoid violating the stated limits by using

down-spreading only.

SDn_REF_CLK and SDn_REF_CLK were designed to work with a spread spectrum clock (+0 to 0.5%

spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

use a source without significant unintended modulation.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

16

Freescale Semiconductor

Input Clocks

4.2

Real Time Clock Timing

The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then

used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of

the RTC signal should be greater than 2× the period of the MPX clock. That is, minimum clock high time

is 2 × t

, and minimum clock low time is 2 × t

. There is no minimum RTC frequency; RTC may be

MPX

grounded if not needed.

4.3

eTSEC Gigabit Reference Clock Timing

Table 10 provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC

timing specifications for the MPC8640.

Table 10. ECn_GTX_CLK125 AC Timing Specifications

Parameter

Symbol

Min

Typical

Max

Unit

Notes

ECn_GTX_CLK125 frequency

f_G125

—

125 100

ppm

—

MHz

3

ECn_GTX_CLK125 cycle time

ECn_GTX_CLK125 peak-to-peak jitter

ECn_GTX_CLK125 duty cycle

t_G125

t_G125J

—

8

—

ns

ps

%

—

1

—

250

t_G125H/t_G125

1, 2

GMII, TBI

1000Base-T for RGMII, RTBI

45

47

55

53

Notes:

1. Timing is guaranteed by design and characterization.

2. ECn_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. ECn_GTX_CLK125

duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T

reference clock.

3. 100 ppm tolerance on ECn_GTX_CLK125 frequency.

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

4.4

Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI

Express and Serial RapidIO interfaces as described below.

For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_plat_freq)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

17

RESET Initialization

Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,

when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with

cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.

For proper Serial RapidIO operation, the MPX clock frequency must be greater than or equal to:

2 × (0.8512) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

64

4.5

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8640. Table 11 provides the RESET initialization AC timing specifications.

Table 11. RESET Initialization Timing Specifications

Parameter

Required assertion time of HRESET

Min

Max

Unit

Notes

100

3

—

μs

SYSCLKs

μs

—

1

Minimum assertion time for SRESET_0 & SRESET_1

Platform PLL input setup time with stable SYSCLK before HRESET

negation

100

2

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

4

2

—

5

SYSCLKs

1

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET

—

Notes:

1. SYSCLK is the primary clock input for the MPC8640.

2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See

the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.

Table 12 provides the PLL lock times.

Table 12. PLL Lock Times

Parameter

Min

Max

Unit

Notes

(Platform and E600) PLL lock times

Local bus PLL

—

100

50

μs

1

—

Notes:

1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

18

DDR and DDR2 SDRAM

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8640. Note that DDR SDRAM is Dn_GV (typ) = 2.5 V and DDR2 SDRAM is

DD

Dn_GV (typ) = 1.8 V.

DD

6.1

DDR SDRAM DC Electrical Characteristics

Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8640 when Dn_GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM DC Electrical Characteristics for Dn_GV (typ) = 1.8 V

DD

Parameter

I/O supply voltage

Symbol

Min

Max

Unit

Notes

Dn_GV_DD

Dn_MV_REF

V_TT

1.71

0.49 × Dn_GV_DD

Dn_MV_REF– 0.04

Dn_MV_REF+ 0.125

–0.3

1.89

0.51 × Dn_GV_DD

Dn_MV_REF+ 0.04

Dn_GV_DD+ 0.3

Dn_MV_REF– 0.125

50

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.420 V)

Output low current (V_OUT= 0.280 V)

Notes:

I_OZ

–50

μA

mA

I_OH

–13.4

—

I_OL

13.4

—

1. Dn_GV_DDis expected to be within 50 mV of the DRAM Dn_GV_DDat all times.

2. Dn_MV_REFis expected to be equal to 0.5 × Dn_GV_DD, and to track Dn_GV_DDDC variations as measured at the receiver.

Peak-to-peak noise on Dn_MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MV_REF. This rail should track variations in the DC level of Dn_MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ Dn_GV_DD

.

Table 14 provides the DDR2 capacitance when Dn_GV

= 1.8 V.

DD(typ)

Table 14. DDR2 SDRAM Capacitance for Dn_GV (typ)=1.8 V

DD

Parameter

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. Dn_GV_DD= 1.8 V 0.090 V, f = 1 MHz, T_A= 25°C, V_OUT= Dn_GV_DD÷ 2,

_{OUT(peak-to-peak)}= 0.2 V.

V

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

19

DDR and DDR2 SDRAM

Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) when

Dn_GV (typ) = 2.5 V.

DD

Table 15. DDR SDRAM DC Electrical Characteristics for Dn_GV (typ) = 2.5 V

DD

Parameter

I/O supply voltage

Symbol

Min

Max

Unit

Notes

Dn_GV_DD

Dn_MV_REF

V_TT

2.375

2.625

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

0.49 × Dn_GV_DD

0.51 × Dn_GV_DD

Dn_MV_REF– 0.04 Dn_MV_REF+ 0.04

V

3

V_IH

Dn_MV_REF+ 0.15

Dn_GV_DD+ 0.3

V

—

4

Input low voltage

V_IL

–0.3

–50

Dn_MV_REF– 0.15

V

Output leakage current

Output high current (V_OUT= 1.95 V)

Output low current (V_OUT= 0.35 V)

Notes:

I_OZ

50

—

μA

mA

I_OH

–16.2

16.2

—

I_OL

1. Dn_GV_DDis expected to be within 50 mV of the DRAM Dn_GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × Dn_GV_DD, and to track Dn_GV_DDDC variations as measured at the receiver.

Peak-to-peak noise on Dn_MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MV_REF. This rail should track variations in the DC level of Dn_MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ Dn_GV_DD

.

Table 16 provides the DDR capacitance when Dn_GV_DD(typ) = 2.5 V.

Table 16. DDR SDRAM Capacitance for Dn_GV (typ) = 2.5 V

DD

Parameter

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. Dn_GV_DD= 2.5 V 0.125 V, f = 1 MHz, T_A= 25°C, V_OUT= Dn_GVDD/2,

V_OUT(peak-to-peak) = 0.2 V.

Table 17 provides the current draw characteristics for MV

.

REF

Table 17. Current Draw Characteristics for MV

REF

Parameter

Current draw for MV_REF

Symbol

Min

Max

500

Unit

μA

Note

I_MVREF

—

1

1. The voltage regulator for MV_REFmust be able to supply up to 500 μA current.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

20

DDR and DDR2 SDRAM

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 18 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GV

= 1.8 V.

DD(typ)

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions (see Table 2)

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

Dn_MV_REF– 0.25

V

—

V_IH

Dn_MV_REF+ 0.25

—

Table 19 provides the input AC timing specifications for the DDR SDRAM when Dn_GV

= 2.5 V.

DD(typ)

Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions (see Table 2)

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

Dn_MV_REF– 0.31

V

—

V_IH

Dn_MV_REF+ 0.31

—

Table 20 provides the input AC timing specifications for the DDR SDRAM interface.

Table 20. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions (see Table 2)

Parameter

Controller Skew for

Symbol

Min

Max

Unit

Notes

t_CISKEW

—

ps

1, 2

MDQS—MDQ/MECC

533 MHz

—

–300

–365

300

365

—

3

400 MHz

—

Note:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW.This can be

determined by the following equation: t_DISKEW= (T ³ 4 – abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the

absolute value of t_CISKEW

.

3. Maximum DDR1 frequency is 400 MHz.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

21

DDR and DDR2 SDRAM

Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 4. DDR Input Timing Diagram for tDISKEW

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 21. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions (see Table 2).

Parameter

Symbol ¹

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

MCK duty cycle

t_MCK

3

10

ns

%

2

t_MCKH/t_MCK

533 MHz

400 MHz

47

53

8

ADDR/CMD output setup with respect to MCK

t_DDKHAS

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

7

533 MHz

400 MHz

1.48

1.95

—

ADDR/CMD output hold with respect to MCK

3

7

533 MHz

400 MHz

1.48

1.95

—

MCS[n] output setup with respect to MCK

3

7

533 MHz

400 MHz

1.48

1.95

—

MCS[n] output hold with respect to MCK

MCK to MDQS Skew

3

7

533 MHz

400 MHz

1.48

1.95

–0.6

—

0.6

4

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

22

DDR and DDR2 SDRAM

Table 21. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol ¹

Min

Max

Unit

Notes

MDQ/MECC/MDM output setup with respect to

MDQS

t_DDKHDS,

t_DDKLDS

ps

5

533 MHz

400 MHz

590

700

—

7

MDQ/MECC/MDM output hold with respect to

MDQS

t_DDKHDX,

t_DDKLDX

ps

5

7

533 MHz

590

700

—

400 MHz

MDQS preamble start

—

–0.5 × t_MCK+0.6

0.6

t_DDKHMP

t_DDKHME

–0.5 × t_MCK– 0.6

–0.6

ns

6

MDQS epilogue end

Note:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until

outputs (A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock

reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the

same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2

parameters have been set to the same adjustment value. See the MPC8641 Integrated Processor Reference Manual for a

description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in note 1.

7. Maximum DDR1 frequency is 400 MHz

8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.

NOTE

For the ADDR/CMD setup and hold specifications in Table 21, it is

assumed that the Clock Control register is set to adjust the memory clocks

by 1/2 applied cycle.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

23

DDR and DDR2 SDRAM

Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t

).

DDKHMH

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

MDQS

Figure 5. Timing Diagram for tDDKHMH

Figure 6 shows the DDR SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS,t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 6. DDR SDRAM Output Timing Diagram

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

24

DUART

Figure 7 provides the AC test load for the DDR bus.

Dn_GV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 7. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8640.

7.1

DUART DC Electrical Characteristics

Table 22 provides the DC electrical characteristics for the DUART interface.

Table 22. DUART DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

Low-level input voltage

–0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= V_DD)

High-level output voltage

(OV_DD= min, I_OH= –100 μA)

V_OH

OV_DD– 0.2

—

V

Low-level output voltage

V_OL

0.2

(OV_DD= min, I_OL= 100 μA)

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

7.2

DUART AC Electrical Specifications

Table 23 provides the AC timing parameters for the DUART interface.

Table 23. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

MPX clock/1,048,576

MPX clock/16

16

baud

—

1,2

1,3

1,4

Notes:

1. Guaranteed by design.

2. MPX clock refers to the platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

4. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16^thsample.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

25

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management

This section provides the AC and DC electrical characteristics for enhanced three-speed and MII

management.

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI

interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether

the GMII or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard.

The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII)

Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII

Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in

Section 9, “Ethernet Management Interface Electrical Characteristics.”

8.1.1

eTSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric

attributes specified in Table 24 and Table 25. The potential applied to the input of a GMII, MII, TBI,

RGMII, RMII or RTBI receiver may exceed the potential of the receiver’s power supply (that is, a GMII

driver powered from a 3.6-V supply driving V into a GMII receiver powered from a 2.5-V supply).

OH

Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The

RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

Table 24. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics

Parameter

Supply voltage 3.3 V

Symbol

Min

Max

Unit

Notes

LV_DD

TV_DD

3.135

3.465

V

1, 2

Output high voltage

(LV_DD/TV_DD= Min, I_OH= –4.0 mA)

V_OH

2.40

—

V

—

Output low voltage

V_OL

0.50

(LV_DD/TV_DD= Min, I_OL= 4.0 mA)

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

2.0

—

0.90

40

V

—

μA

1, 2, 3

(V_IN= LV_DD, V_IN= TV_DD

)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Table 24. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics (continued)

Parameter

Input low current

Symbol

Min

Max

Unit

Notes

3

I_IL

–600

—

μA

(V_IN= GND)

Notes:

1. LV_DDsupports eTSECs 1 and 2

2. TV_DDsupports eTSECs 3 and 4

3. The symbol V_IN, in this case, represents the LV_INand TV_INsymbols referenced in Table 1 and Table 2

Table 25. GMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics

Parameter

Supply voltage 2.5 V

Symbol

LV_DD/TV_DD

V_OH

Min

2.375

2.00

Max

2.625

—

Unit

V

Notes

1, 2

Output high voltage

V

—

(LV_DD/TV_DD= Min, I_OH= –1.0 mA)

Output low voltage

(LV_DD/TV_DD= Min, I_OL= 1.0 mA)

V_OL

—

0.40

V

—

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

1.70

—

0.90

10

V

—

1, 2, 3

—

μA

(V_IN= LV_DD, V_IN= TV_DD

)

3

Input low current

(V_IN= GND)

I_IL

–15

—

μA

Note:

1

LV_DDsupports eTSECs 1 and 2.

TV_DDsupports eTSECs 3 and 4.

Note that the symbol V_IN, in this case, represents the LV_INand TV_INsymbols referenced in Table 1 and Table 2.

2

3

8.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

8.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications because they have similar performance and are described in a source-synchronous fashion

like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is

relationship between the maximum FIFO speed and the platform speed. For more information, see

Section 18.4.2, “Platform to FIFO Restrictions.”

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

A summary of the FIFO AC specifications appears in Table 26 and Table 27.

Table 26. FIFO Mode Transmit AC Timing Specification

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol

Min

Typ

Max

Unit

TX_CLK, GTX_CLK clock period (GMII mode)

TX_CLK, GTX_CLK clock period (Encoded mode)

TX_CLK, GTX_CLK duty cycle

t_FIT

t_{FITH/ FIT}

8.4

6.4

45

—

8.0

50

—

100

55

ns

%

t

TX_CLK, GTX_CLK peak-to-peak jitter

Rise time TX_CLK (20%–80%)

t_FITJ

t_FITR

t_FITF

250

0.75

—

ps

ns

—

Fall time TX_CLK (80%–20%)

—

FIFO data TXD[7:0], TX_ER, TX_EN setup time to

t_FITDV

2.0

—

GTX_CLK

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold

t_FITDX

0.5

—

3.0

ns

time

Table 27. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol

Min

Typ

Max

Unit

1

RX_CLK clock period (GMII mode)

RX_CLK clock period (Encoded mode)

RX_CLK duty cycle

t_FIR

8.4

6.4

45

—

8.0

50

—

100

55

ns

%

1

t_FIR

t_FIRH/t_FIR

t_FIRJ

RX_CLK peak-to-peak jitter

250

0.75

—

ps

ns

Rise time RX_CLK (20%–80%)

t_FIRR

—

Fall time RX_CLK (80%–20%)

t_FIRF

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

t_FIRDV

t_FIRDX

1.5

0.5

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

1

100 ppm tolerance on RX_CLK frequency

Timing diagrams for FIFO appear in Figure 8 and Figure 9.

.

t_FITF

t_FITR

t_FIT

GTX_CLK

t_FITH

t_FITDV

t_FITDX

TXD[7:0]

TX_EN

TX_ER

Figure 8. FIFO Transmit AC Timing Diagram

t_FIRR

t_FIR

RX_CLK

t_FIRH

t_FIRF

RXD[7:0]

RX_DV

RX_ER

valid data

t_FIRDV

Figure 9. FIFO Receive AC Timing Diagram

t_FIRDX

8.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1

GMII Transmit AC Timing Specifications

Table 28 provides the GMII transmit AC timing specifications.

Table 28. GMII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

GMII data TXD[7:0], TX_ER, TX_EN setup time

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK data clock rise time (20%–80%)

t_GTKHDV

t_GTKHDX

2.5

0.5

—

ns

5.0

1.0

2

t_GTXR

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Table 28. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

2

GTX_CLK data clock fall time (80%–20%)

t_GTXF

—

1.0

ns

Notes:

1. The symbols used for timing specifications herein follow the pattern t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GTKHDVsymbolizes GMII

transmit timing (GT) with respect to the t_GTXclock reference (K) going to the high state (H) relative to the time date input

signals (D) reaching the valid state (V) to state or setup time. Also, t_GTKHDXsymbolizes GMII transmit timing (GT) with respect

to the t_GTXclock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t_GTXrepresents the GMII(G) transmit (TX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 10 shows the GMII transmit AC timing diagram.

t_GTX

t_GTXR

GTX_CLK

t_GTXF

t_GTXH

TXD[7:0]

TX_EN

TX_ER

t_GTKHDX

t_GTKHDV

Figure 10. GMII Transmit AC Timing Diagram

8.2.2.2

GMII Receive AC Timing Specifications

Table 29 provides the GMII receive AC timing specifications.

Table 29. GMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol¹

Min

Typ

Max

Unit

3

RX_CLK clock period

RX_CLK duty cycle

t_GRX

—

40

2.0

0.5

—

8.0

—

60

—

ns

t

_GRXH/t_GRX

t_GRDVKH

t_GRDXKH

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise time (20%–80%)

—

2

t_GRXR

1.0

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Table 29. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol¹

Min

Typ

Max

Unit

2

RX_CLK clock fall time (80%-20%)

t_GRXF

—

1.0

ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GRDVKHsymbolizes GMII

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_RXclock

reference (K) going to the high state (H) or setup time. Also, t_GRDXKLsymbolizes GMII receive timing (GR) with respect to

the time data input signals (D) went invalid (X) relative to the t_GRXclock reference (K) going to the low (L) state or hold time.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of t_GRXrepresents the GMII (G) receive (RX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

3. 100 ppm tolerance on RX_CLK frequency

Figure 11 provides the AC test load for eTSEC.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 11. eTSEC AC Test Load

Figure 12 shows the GMII receive AC timing diagram.

t_GRX

t_GRXR

RX_CLK

t_GRXF

t_GRXH

RXD[7:0]

RX_DV

RX_ER

t_GRDXKH

t_GRDVKH

Figure 12. GMII Receive AC Timing Diagram

8.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.3.1

MII Transmit AC Timing Specifications

Table 30 provides the MII transmit AC timing specifications.

Table 30. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

2

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t_MTX

—

400

40

—

5

—

ns

%

t_MTX

t_{MTXH/ MTX}

t

35

1

65

15

4.0

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise time (20%–80%)

TX_CLK data clock fall time (80%–20%)

Note:

t_MTKHDX

ns

2

t_MTXR

1.0

—

2

t_MTXF

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII

transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 13 shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 13. MII Transmit AC Timing Diagram

8.2.3.2

MII Receive AC Timing Specifications

Table 31 provides the MII receive AC timing specifications.

Table 31. MII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

2,3

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t_MRX

—

35

400

40

—

65

ns

%

3

t_MRX

t_MRXH/t_MRX

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Table 31. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise time (20%–80%)

RX_CLK clock fall time (80%–20%)

Note:

t_MRDVKH

t_MRDXKH

10.0

1.0

—

ns

2

t_MRXR

4.0

2

t_MRXF

1.0

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K)

going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

3. 100 ppm tolerance on RX_CLK frequency

Figure 14 provides the AC test load for eTSEC.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 14. eTSEC AC Test Load

Figure 15 shows the MII receive AC timing diagram.

t_MRX

t_MRXR

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKL

Figure 15. MII Receive AC Timing Diagram

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2.4.1

TBI Transmit AC Timing Specifications

Table 32 provides the TBI transmit AC timing specifications.

Table 32. TBI Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

TCG[9:0] setup time GTX_CLK going high

TCG[9:0] hold time from GTX_CLK going high

GTX_CLK rise time (20%–80%)

GTX_CLK fall time (80%–20%)

Notes:

t_TTKHDV

t_TTKHDX

2.0

1.0

—

ns

2

t_TTXR

1.0

2

t_TTXF

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state )(reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TTKHDVsymbolizes the TBI

transmit timing (TT) with respect to the time from t_TTX(K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, t_TTKHDXsymbolizes the TBI transmit timing (TT) with respect to the time from t_TTX(K) going high

(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript

of t_TTXrepresents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. Guaranteed by design.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

34

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 16 shows the TBI transmit AC timing diagram.

t_TTXR

t_TTX

GTX_CLK

TCG[9:0]

t_TTXH

t_TTXF

t_TTKHDV

t_TTXR

t_TTKHDX

Figure 16. TBI Transmit AC Timing Diagram

8.2.4.2

TBI Receive AC Timing Specifications

Table 33 provides the TBI receive AC timing specifications.

Table 33. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

PMA_RX_CLK[0:1] clock period

Symbol ¹

Min

Typ

Max

Unit

3

t_TRX

—

16.0

—

8.5

60

—

ns

%

PMA_RX_CLK[0:1] skew

t_SKTRX

t_TRXH/t_TRX

t_TRDVKH

t_TRDXKH

7.5

40

PMA_RX_CLK[0:1] duty cycle

—

RCG[9:0] setup time to rising PMA_RX_CLK

RCG[9:0] hold time to rising PMA_RX_CLK

PMA_RX_CLK[0:1] clock rise time (20%–80%)

PMA_RX_CLK[0:1] clock fall time (80%–20%)

Note:

2.5

1.5

0.7

—

ns

—

2

t_TRXR

—

2.4

2

t_TRXF

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TRDVKHsymbolizes TBI

receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_TRXclock reference

(K) going to the high (H) state or setup time. Also, t_TRDXKHsymbolizes TBI receive timing (TR) with respect to the time data

input signals (D) went invalid (X) relative to the t_TRXclock reference (K) going to the high (H) state. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,

the subscript of t_TRXrepresents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that

is being skewed (TRX).

2. Guaranteed by design.

3. 100 ppm tolerance on PMA_RX_CLK[0:1] frequency

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

35

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 17 shows the TBI receive AC timing diagram.

t_TRXR

t_TRX

PMA_RX_CLK1

t_TRXH

t_TRXF

Valid Data

RCG[9:0]

Valid Data

t_TRDVKH

t_SKTRX

t_TRDXKH

PMA_RX_CLK0

t_TRDXKH

t_TRXH

t_TRDVKH

Figure 17. TBI Receive AC Timing Diagram

8.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock

is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas

for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the

TSEC_GTX_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 34.

Table 34. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with L/TV_DDof 3.3 V 5% and 2.5 V 5%.

Parameter

Symbol

Min

Typ

Max

Unit

1

RX_CLK clock period

RX_CLK duty cycle

t_TRR

7.5

40

—

8.0

50

—

8.5

60

ns

%

t_{TRRH/ TRR}

t_TRRJ

t_TRRR

t

RX_CLK peak-to-peak jitter

250

1.0

—

ps

ns

Rise time RX_CLK (20%–80%)

—

Fall time RX_CLK (80%–20%)

t_TRRF

—

RCG[9:0] setup time to RX_CLK rising edge

RCG[9:0] hold time to RX_CLK rising edge

t_TRRDVKH

t_TRRDXKH

2.0

1.0

—

1

100 ppm tolerance on RX_CLK frequency

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

36

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

A timing diagram for TBI receive appears in Figure 18.

t_TRRR

t_TRR

RX_CLK

RCG[9:0]

t_TRRH

t_TRRF

valid data

t_TRRDVKH

t_TRRDXKH

Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6

RGMII and RTBI AC Timing Specifications

Table 35 presents the RGMII and RTBI AC timing specifications.

Table 35. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with L/TV_DDof 2.5 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

5

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver) ²

Clock period duration ³

t_SKRGT

–500

1.0

7.2

40

0

500

2.8

ps

ns

%

t_SKRGT

—

8.0

50

—

5,6

t_RGT

8.8

Duty cycle for 10BASE-T and 100BASE-TX ^{3, 4}

Rise time (20%–80%)

t_RGTH/t_RGT

60

5

t_RGTR

—

0.75

ns

5

Fall time (80%–20%)

t_RGTF

—

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of t_RGTrepresents the TBI (T) receive (RX) clock. Note also that the

notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,

the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between.

5. Guaranteed by characterization

6. 100 ppm tolerance on RX_CLK frequency.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

37

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At Transmitter)

t_SKRGT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t_SKRGT

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t_SKRGT

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t_SKRGT

RX_CLK

(At PHY)

Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.2.7

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.7.1

RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 36.

Table 36. RMII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

REF_CLK clock period

Symbol ¹

t_RMT

Min

—

Typ

20.0

50

Max

—

Unit

ns

REF_CLK duty cycle

t_RMTH/t_RMT

35

65

%

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

t_RMTJ

—

250

2.0

ps

t_RMTR

1.0

—

ns

t_RMTF

—

ns

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

38

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Table 36. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

REF_CLK to RMII data TXD[1:0], TX_EN delay

Note:

Symbol ¹

Min

Typ

Max

Unit

t_RMTDX

1.0

—

10.0

ns

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII

transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

Figure 20 shows the RMII transmit AC timing diagram.

t_RMTR

t_RMT

REF_CLK

t_RMTF

t_RMTH

TXD[1:0]

TX_EN

TX_ER

t_RMTDX

Figure 20. RMII Transmit AC Timing Diagram

8.2.7.2

RMII Receive AC Timing Specifications

Table 37 shows the RMII receive AC timing specifications.

Table 37. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

REF_CLK clock period

Symbol¹

t_RMR

Min

15.0

35

Typ

20.0

50

Max

25.0

65

Unit

ns

%

t

_RMRH/t_RMR

t_RMRJ

REF_CLK duty cycle

REF_CLK peak-to-peak jitter

—

250

2.0

—

ps

ns

t_RMRR

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

1.0

4.0

—

t_RMRF

—

t_RMRDV

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

39

Ethernet Management Interface Electrical Characteristics

Table 37. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typ

Max

Unit

t_RMRDX

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge

2.0

—

ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII

receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference

(K) going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Figure 21 provides the AC test load for eTSEC.

LV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 21. eTSEC AC Test Load

Figure 22 shows the RMII receive AC timing diagram.

t_RMRR

t_RMR

REF_CLK

t_RMRF

Valid Data

t_RMRH

RXD[1:0]

CRS_DV

RX_ER

t_RMRDV

t_RMRDX

Figure 22. RMII Receive AC Timing Diagram

9 Ethernet Management Interface Electrical

Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

GMII, RGMII, RMII, TBI and RTBI are specified in “Section 8, “Ethernet: Enhanced Three-Speed

Ethernet (eTSEC), MII Management.”

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

40

Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

9.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics

for MDIO and MDC are provided in Table 38.

Table 38. MII Management DC Electrical Characteristics

Parameter

Supply voltage (3.3 V)

Symbol

Min

Max

Unit

OV_DD

V_OH

3.135

2.10

3.465

—

V

Output high voltage

(OV_DD= Min, I_OH= –1.0 mA)

Output low voltage

V_OL

—

0.50

V

(OV_DD= Min, I_OL= 1.0 mA)

Input high voltage

Input low voltage

V_IH

V_IL

I_IH

1.70

—

0.90

40

V

Input high current

—

μA

(OV_DD= Max, V_IN¹= 2.1 V)

Input low current

I_IL

–600

—

μA

(OV_DD= Max, V_IN= 0.5 V)

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

9.2

MII Management AC Electrical Specifications

Table 39 provides the MII management AC timing specifications.

Table 39. MII Management AC Timing Specifications

At recommended operating conditions with OV_DDis 3.3 V 5%.

Parameter

MDC frequency

Symbol ¹

Min

Typ

Max

Unit

Notes

f_MDC

t_MDC

2.5

—

9.3

MHz

ns

2, 4

—

5

MDC period

80

400

MDC clock pulse width high

MDC to MDIO valid

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t_MDCH

32

—

ns

t_MDKHDV

t_MDKHDX

t_MDDVKH

t_MDDXKH

t_MDCR

16 × t_MPXCLK

—

ns

10

5

16 × t_MPXCLK

ns

3, 5

—

4

—

10

ns

0

ns

—

ns

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

41

Ethernet Management Interface Electrical Characteristics

Table 39. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OV_DDis 3.3 V 5%.

Parameter

Symbol ¹

Min

Typ

Max

Unit

Notes

MDC fall time

t_MDHF

—

10

ns

4

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes

management data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency

divided by 64.)

3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is

8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and

the minimum frequency is 1.7 MHz.)

4. Guaranteed by design.

5. t_MPXCLKis the platform (MPX) clock

Figure 23 provides the AC test load for eTSEC.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 23. eTSEC AC Test Load

NOTE

Output will see a 50 Ω load since what it sees is the transmission line.

Figure 24 shows the MII management AC timing diagram.

t_MDCR

t_MDC

MDC

t_MDCF

t_MDCH

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 24. MII Management Interface Timing Diagram

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

42

Local Bus

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8640.

10.1 Local Bus DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the local bus interface operating at OV = 3.3 V

DD

DC.

Table 40. Local Bus DC Electrical Characteristics (3.3 V DC)

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

–0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= OV_DD

)

High-level output voltage

(OV_DD= min, I_OH= –2 mA)

V_OH

OV_DD– 0.2

—

V

Low-level output voltage

(OV_DD= min, I_OL= 2 mA)

V_OL

0.2

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

10.2 Local Bus AC Timing Specifications

Table 41 describes the timing parameters of the local bus interface at OV = 3.3 V with PLL enabled.

DD

For information about the frequency range of local bus see Section 18.1, “Clock Ranges.”

Table 41. Local Bus Timing Specifications (OV = 3.3 V)—PLL Enabled

DD

Parameter

Symbol ¹

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

t_LBK

7.5

45

—

55

ns

%

2

—

t_LBKH/t_LBK

t_LBKSKEW

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

t_LBIXKH2

LCLK[n] skew to LCLK[m] or LSYNC_OUT

150

—

ps

ns

7, 8

3, 4

6

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

1.8

1.7

1.0

1.5

—

LALE output transition to LAD/LDP output transition (LATCH hold time) t_LBOTOT

—

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

Local bus clock to LALE assertion

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOV4

2.0

2.2

2.3

—

3

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

43

Local Bus

Table 41. Local Bus Timing Specifications (OV = 3.3 V)—PLL Enabled (continued)

DD

Parameter

Symbol ¹

Min

Max

Unit

Notes

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

t_LBKHOX1

t_LBKHOX2

0.7

—

ns

—

3

Local bus clock to output high Impedance (except LAD/LDP and LALE) t_LBKHOZ1

2.5

5

Local bus clock to output high impedance for LAD/LDP

t_LBKHOZ2

—

5

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for

clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from OV_DD÷ 2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 × OV_DDof the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. t_LBOTOTis a measurement of the minimum time between the negation of LALE and any change in LAD. t_LBOTOTis

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV_DD÷ 2.

8. Guaranteed by design.

Figure 25 provides the AC test load for the local bus.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 25. Local Bus AC Test Load

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

44

Local Bus

Figure 26 shows the local bus signals with PLL enabled.

LSYNC_IN

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH2

t_LBIVKH2

Input Signal:

LGTA

LUPWAIT

t_LBKHOZ1

t_LBKHOX1

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t_LBKHOZ2

t_LBKHOX2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ2

t_LBKHOX2

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

t_LBKHOV4

LALE

Figure 26. Local Bus Signals (PLL Enabled)

NOTE

PLL bypass mode is recommended when LBIU frequency is at or below

83 MHz. When LBIU operates above 83 MHz, LBIU PLL is recommended

to be enabled.

Table 42 describes the general timing parameters of the local bus interface at OV = 3.3 V with PLL

DD

bypassed.

Table 42. Local Bus Timing Parameters—PLL Bypassed

Parameter

Symbol¹

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

t_LBK

12

45

—

55

3.9

—

ns

%

2

t_{LBKH/ LBK}

t

—

Internal launch/capture clock to LCLK delay

t_LBKHKT

t_LBIVKH1

t_LBIVKL2

t_LBIXKH1

2.3

5.7

5.6

–1.8

ns

8

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

Input hold from local bus clock (except LGTA/LUPWAIT)

4, 5

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

45

Local Bus

Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)

Parameter

Symbol¹

Min

Max

Unit

Notes

LGTA/LUPWAIT input hold from local bus clock

t_LBIXKL2

t_LBOTOT

–1.3

1.5

—

ns

4, 5

6

LALE output transition to LAD/LDP output transition (LATCH hold

time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

t_LBKLOV1

t_LBKLOV2

t_LBKLOV3

t_LBKLOV4

t_LBKLOX1

t_LBKLOX2

—

–0.3

–0.1

0

ns

4

7

Local bus clock to address valid for LAD

—

Local bus clock to LALE assertion

—

0

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

–3.2

—

Local bus clock to output high Impedance (except LAD/LDP and t_LBKLOZ1

LALE)

0.2

Local bus clock to output high impedance for LAD/LDP

t_LBKLOZ2

—

0.2

ns

7

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case

for clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect

to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus

clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK

by t_LBKHKT

.

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV_DD÷ 2.

4. All signals are measured from BV_DD÷ 2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BV_DDof the signal

in question for 3.3-V signaling levels.

5. Input timings are measured at the pin.

6. The value of t_LBOTOTis the measurement of the minimum time between the negation of LALE and any change in LAD

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

8. Guaranteed by characterization.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

46

Freescale Semiconductor

Local Bus

Figure 27 shows the local bus signals in PLL bypass mode.

Internal launch/capture clock

t_LBKHKT

LCLK[n]

t_LBIVKH1

t_LBIXKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIVKL2

Input Signal:

LGTA

t_LBIXKL2

LUPWAIT

t_LBKLOV1

t_LBKLOZ1

t_LBKLOX1

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t_LBKLOZ2

t_LBKLOV2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKLOX2

t_LBKLOV3

Output (Address) Signal:

LAD[0:31]

t_LBKLOV4

t_LBOTOT

LALE

Figure 27. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of t_LBKHKT.In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock,

with the exception of the LGTA/LUPWAIT signal, which is captured at the

rising edge of the internal clock.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

47

Local Bus

Figure 28–Figure 31 show the local bus signals and GPCM/UPM signals for LCRR[CLKDIV] at clock

ratios of 4, 8, and 16 with PLL enabled or bypassed.

LSYNC_IN

T1

T3

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t_LBIVKH2

t_LBIXKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH1

t_LBKHOV1

t_LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Enabled)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

48

Local Bus

Internal launch/capture clock

T1

T3

LCLK

t_LBKLOX1

t_LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t_LBKLOZ1

GPCM Mode Input Signal:

LGTA

t_LBIVKL2

t_LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4)

(PLL Bypass Mode)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

49

Local Bus

LSYNC_IN

T1

T2

T3

T4

t_LBKHOV1

t_LBKHOZ1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t_LBIVKH2

t_LBIXKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH1

t_LBKHOV1

t_LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

(PLL Enabled)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

50

Freescale Semiconductor

Local Bus

Internal launch/capture clock

T1

T2

T3

T4

LCLK

t_LBKLOX1

t_LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t_LBKLOZ1

GPCM Mode Input Signal:

LGTA

t_LBIVKL2

t_LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

(PLL Bypass Mode)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

51

JTAG

11 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of

the MPC8640/D.

11.1 JTAG DC Electrical Characteristics

Table 43 provides the DC electrical characteristics for the JTAG interface.

Table 43. JTAG DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

Low-level input voltage

–0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= V_DD)

High-level output voltage

(OV_DD= min, I_OH= –100 μA)

V_OH

OV_DD– 0.2

—

V

Low-level output voltage

V_OL

0.2

(OV_DD= min, I_OL= 100 μA)

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

11.2 JTAG AC Electrical Specifications

Table 44 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35.

1

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (see Table 3).

Parameter

Symbol²

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

33.3

—

2

MHz

ns

—

6

30

15

0

t_JTKHKL

t_JTGR& t_JTGF

t_TRST

ns

25

—

ns

3

Input setup times:

ns

Boundary-scan data

t_JTDVKH

t_JTIVKH

4

0

—

4

5

TMS, TDI

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

20

25

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

4

20

25

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

52

JTAG

1

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)

At recommended operating conditions (see Table 3).

Parameter

Symbol²

Min

Max

Unit

Notes

Output hold times:

ns

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

30

—

5, 6

JTAG external clock to output high impedance:

Boundary-scan data

TDO

ns

t_JTKLDZ

t_JTKLOZ

3

19

9

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 32).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock

reference (K) going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time

data input signals (D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise

and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

.

6. Guaranteed by design.

Figure 32 provides the AC test load for TDO and the boundary-scan outputs.

Z₀= 50 Ω

Output

OV_DD/2

R_L= 50 Ω

Figure 32. AC Test Load for the JTAG Interface

Figure 33 provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTG

t_JTGF

VM = Midpoint Voltage (OV /2)

DD

Figure 33. JTAG Clock Input Timing Diagram

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

53

I²C

Figure 34 provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 34. TRST Timing Diagram

Figure 35 provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Output Data Valid

Boundary

Data Outputs

VM = Midpoint Voltage (OV /2)

DD

Figure 35. Boundary-Scan Timing Diagram

12 I²C

2

This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8640.

2

12.1 I C DC Electrical Characteristics

Table 45 provides the DC electrical characteristics for the I C interfaces.

2

Table 45. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

Input low voltage level

Low level output voltage

V_IH

V_IL

0.7 × OV_DD

OV_DD+ 0.3

0.3 × OV_DD

0.2 × OV_DD

50

V

—

1

–0.3

0

V_OL

V

Pulse width of spikes which must be suppressed by the input

filter

t_I2KHKL

0

ns

2

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

54

I²C

2

Table 45. I C DC Electrical Characteristics (continued)

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input current each I/O pin (input voltage is between

I_I

–10

10

μA

3

0.1 × OV_DDand 0.9 × OV_DD(max)

Capacitance for each I/O pin

C_I

—

10

pF

—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OV_DDis switched off.

2

12.2 I C AC Electrical Specifications

2

Table 46 provides the AC timing parameters for the I C interfaces.

2

Table 46. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 45).

Parameter

Symbol¹

Min

Max

Unit

SCL clock frequency

f_I2C

0

400

—

kHz

μs

4

Low period of the SCL clock

t_I2CL

1.3

0.6

4

High period of the SCL clock

t_I2CH

—

μs

4

Setup time for a repeated START condition

t_I2SVKH

—

μs

4

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

t_I2SXKL

—

μs

4

Data setup time

t_I2DVKH

100

—

ns

Data input hold time:

CBUS compatible masters

I²C bus devices

t_I2DXKL

—

0 ²

μs

ns

μs

V

5

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Data output delay time

t_I2CR

20 + 0.1 C_B

300

0.9 ³

—

t

20 + 0.1 C_b

I2CF

t_I2OVKL

—

Set-up time for STOP condition

t

0.6

1.3

I2PVKH

Bus free time between a STOP and START condition

t_I2KHDX

—

Noise margin at the LOW level for each connected device (including

hysteresis)

V_NL

0.1 × OV_DD

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

55

I²C

2

Table 46. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 45).

Parameter

Symbol¹

Min

Max

Unit

Noise margin at the HIGH level for each connected device (including

hysteresis)

V_NH

0.2 × OV_DD

—

V

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock reference (K) going to the

high (H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When MPC8640 acts as the I²C bus master while transmitting, MPC8640 drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start or Stop condition. Therefore, the 300

ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for

MPC8640 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the

desired I²C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I²C SCL clock frequency

is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal

16):

I²C Source Clock Frequency

FDR Bit Setting

Actual FDR Divider Selected

Actual I²C SCL Frequency Generated 371 KHz

333 MHz 266 MHz

200 MHz

0x26

512

133 MHz

0x00

384

0x2A

896

0x05

704

378 KHz

390 KHz

346 KHz

For the detail of I²C frequency calculation, refer to the application note AN2919 “Determining the I²C Frequency Divider Ratio

for SCL.” Note that the I²C Source Clock Frequency is half of the MPX clock frequency for MPC8640.

3. The maximum t_I2DXKLhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

4. Guaranteed by design.

5. C_B= capacitance of one bus line in pF.

2

Figure 32 provides the AC test load for the I C.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 36. I C AC Test Load

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

56

High-Speed Serial Interfaces (HSSI)

2

Figure 37 shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

P

S

2

Figure 37. I C Bus AC Timing Diagram

13 High-Speed Serial Interfaces (HSSI)

The MPC8640D features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial

interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2

can be used for PCI Express and/or serial RapidIO data transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference

circuits are also shown.

13.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

57

High-Speed Serial Interfaces (HSSI)

Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a

receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.

SDn_TX or

SDn_RX

A Volts

V_cm= (A + B) ÷ 2

SDn_TX or

SDn_RX

B Volts

Differential Swing, VID or VOD = A – B

Differential Peak Voltage, VDIFFp = |A - B|

Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)

Figure 38. Differential Voltage Definitions for Transmitter or Receiver

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

Single-Ended Swing

The transmitter output signals and the receiver input signals SDn_TX, SDn_TX,

SDn_RX and SDn_RX each have a peak-to-peak swing of A – B volts. This is also

referred as each signal wire’s single-ended swing.

Differential Output Voltage, V (or Differential Output Swing):

OD

The differential output voltage (or swing) of the transmitter, V , is defined as the

OD

difference of the two complimentary output voltages: V

– V

The

SDn_TX

SDn_TX.

V

value can be either positive or negative.

OD

Differential Input Voltage, V (or Differential Input Swing):

ID

The differential input voltage (or swing) of the receiver, V , is defined as the

ID

difference of the two complimentary input voltages: V

– V

. The

SDn_RX

V value can be either positive or negative.

ID

Differential Peak Voltage, V

DIFFp

The peak value of the differential transmitter output signal or the differential

receiver input signal is defined as differential peak voltage, V = |A – B| volts.

DIFFp

Differential Peak-to-Peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input

signal of the receiver each range from A – B to –(A – B) volts, the peak-to-peak

value of the differential transmitter output signal or the differential receiver input

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

58

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

signal is defined as differential peak-to-peak voltage,

= 2 × V = 2 × |(A – B)| volts, which is twice of differential swing in

V

DIFFp-p

DIFFp

amplitude, or twice of the differential peak. For example, the output differential

peak-peak voltage can also be calculated as V = 2 × |V |.

TX-DIFFp-p

OD

Differential Waveform

The differential waveform is constructed by subtracting the inverting signal

(SDn_TX, for example) from the non-inverting signal (SDn_TX, for example)

within a differential pair. There is only one signal trace curve in a differential

waveform. The voltage represented in the differential waveform is not referenced

to ground. Refer to Figure 47 as an example for differential waveform.

Common Mode Voltage, V

cm

The common mode voltage is equal to one half of the sum of the voltages between

each conductor of a balanced interchange circuit and ground. In this example, for

SerDes output, V

= (V

+ V

) ÷ 2 = (A + B) ÷ 2, which is the

cm_out

SDn_TX

arithmetic mean of the two complimentary output voltages within a differential

pair. In a system, the common mode voltage may often differ from one

component’s output to the other’s input. Sometimes, it may be even different

between the receiver input and driver output circuits within the same component.

It is also referred as the DC offset in some occasion.

To illustrate these definitions using real values, consider the case of a current mode logic (CML)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

OD

between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other

OD

phase. The peak differential voltage (V

is 1000 mV p-p.

) is 500 mV. The peak-to-peak differential voltage (V

)

DIFFp

DIFFp-p

13.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and

SDn_REF_CLK for PCI Express and Serial RapidIO.

The following sections describe the SerDes reference clock requirements and some application

information.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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59

High-Speed Serial Interfaces (HSSI)

13.2.1 SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XV

SRDSn are specified in Table 1 and Table 2.

DD_

SerDes Reference Clock Receiver Reference Circuit Structure

— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as

shown in Figure 39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a

50-Ω termination to SGND followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For

example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven

by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential

input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to

SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled

off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

50 W

SDn_REF_CLK

Input

Amp

SDn_REF_CLK

50 W

Figure 39. Receiver of SerDes Reference Clocks

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

60

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

13.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8640D SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV

differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,

each signal wire of the differential pair must have a single-ended swing less than 800 mV and

greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in section 13.2.1, the maximum average

current requirements sets the requirement for average voltage (common mode voltage) to be

between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement

for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND. Each signal wire of the differential inputs is allowed to swing below and above the

command mode voltage (SGND). Figure 41 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-ended Mode

— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV peak-peak (from V to V

)

min

max

with SDn_REF_CLK either left unconnected or tied to ground.

— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as

the clock input (SDn_REF_CLK) in use.

200mV < Input Amplitude or Differential Peak < 800mV

SDn_REF_CLK

Vmax < 800mV

100mV < Vcm < 400mV

Vmin > 0V

SDn_REF_CLK

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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61

High-Speed Serial Interfaces (HSSI)

200mV < Input Amplitude or Differential Peak < 800mV

SDn_REF_CLK

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm – 400 mV

SDn_REF_CLK

Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SDn_REF_CLK Input Amplitude < 800 mV

SDn_REF_CLK

0 V

SDn_REF_CLK

Figure 42. Single-Ended Reference Clock Input DC Requirements

13.2.3 Interfacing With Other Differential Signaling Levels

The following list explains characteristics of interfacing with other differential signaling levels.

•

With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed

current steering logic) compatible DC-coupled.

•

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can

be used but may need to be AC-coupled due to the limited common mode input range allowed (100

to 400 mV) for DC-coupled connection.

•

LVPECL outputs can produce signal with too large amplitude. It may need to be DC-biased at

clock driver output first and followed with series attenuation resistor to reduce the amplitude, in

addition to AC-coupling.

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High-Speed Serial Interfaces (HSSI)

Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8640D SerDes reference clock

input’s DC requirement.

NOTE

Figure 43–Figure 46 are for conceptual reference only. Due to the

differences in the clock driver chip’s internal structure, output impedance,

and termination requirements among various clock driver chip

manufacturers, the clock circuit reference designs provided by clock driver

chip vendor may be different from what is shown above. They may also vary

from one vendor to the other. Therefore, Freescale Semiconductor can

neither provide the optimal clock driver reference circuits, nor guarantee the

correctness of the following clock driver connection reference circuits. The

system designer is recommended to contact the selected clock driver chip

vendor for the optimal reference circuits with the MPC8640D SerDes

reference clock receiver requirement provided in this document.

MPC8640D

HCSL CLK Driver Chip

50 Ω

SDn_REF_CLK

CLK_Out

33 Ω

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

CLK_Out

SDn_REF_CLK

50 Ω

Clock driver vendor dependent

source termination resistor

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8640D SerDes reference clock

input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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63

High-Speed Serial Interfaces (HSSI)

LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

MPC8640D

LVDS CLK Driver Chip

50 Ω

SDn_REF_CLK

10 nF

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

SDn_REF_CLK

CLK_Out

10 nF

50 Ω

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8640D SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45

assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8640D SerDes

reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential

peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference

clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω.

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Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Please consult with the clock driver chip manufacturer to verify whether this connection scheme is

compatible with a particular clock driver chip.

LVPECL CLK

Driver Chip

MPC8640D

50 Ω

SDn_REF_CLK

CLK_Out

10nF

R2

SerDes Refer.

CLK Receiver

R1

100 Ω differential PWB trace

10nF

Clock Driver

R2

CLK_Out

50 Ω

Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock

input’s DC requirement.

Single-Ended

CLK Driver Chip

MPC8640D

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SDn_REF_CLK

33 Ω

Clock Driver

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

SDn_REF_CLK

50 Ω

Figure 46. Single-Ended Connection (Reference Only)

13.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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65

High-Speed Serial Interfaces (HSSI)

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

Table 47 describes some AC parameters common to PCI Express and Serial RapidIO protocols.

Table 47. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XV_{DD_}SRDS1 or XV_{DD_}SRDS2 = 1.1 V 5% and 1.05 V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Rising Edge Rate

Falling Edge Rate

Rise Edge Rate

1.0

+200

—

4.0

—

V/ns

mV

%

2, 3

2

Fall Edge Rate

Differential Input High Voltage

Differential Input Low Voltage

V_IH

V_IL

–200

20

2

Rising edge rate (SDn_REF_CLK) to falling edge rate

(SDn_REF_CLK) matching

Rise-Fall

Matching

—

1, 4

Notes:

1. Measurement taken from single-ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered

on the differential zero crossing. See Figure 47.

4. Matching applies to the rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median

cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rising edge

rate of SDn_REF_CLK should be compared to the falling edge rate of SDn_REF_CLK, and the maximum allowed difference

should not exceed 20% of the slowest edge rate. See Figure 48.

Rise Edge Rate

Fall Edge Rate

V_IH= +200 mV

0.0 V

V_IL= –200 mV

SD_REF_CLKn –

SD_REF_CLKn

Figure 47. Differential Measurement Points for Rise and Fall Time

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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High-Speed Serial Interfaces (HSSI)

SDn_REF_CLK

Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol

based on application usage. Refer to the following sections for detailed information:

•

Section 14.2, “AC Requirements for PCI Express SerDes Clocks”

Section 15.2, “AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK”

13.3 SerDes Transmitter and Receiver Reference Circuits

Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver.

SD1_RXn or

SD2_RXn

SD1_TXn or

SD2_TXn

50 Ω

Receiver

Transmitter

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

Figure 49. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express or Serial Rapid IO) in this document based on the application usage:

•

Section 14, “PCI Express”

Section 15, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above two serial transmission protocols with

the capacitor value defined in specification of each protocol section.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640.

14.1 DC Requirements for PCI Express SDn_REF_CLK and

SDn_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

14.2 AC Requirements for PCI Express SerDes Clocks

Table 48 lists AC requirements.

Table 48. SDn_REF_CLK and SDn_REF_CLK AC Requirements

Parameter

Symbol Min Typical

Max

Units

Notes

REFCLK cycle time

t_REF

—

10

—

ns

ps

—

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

t_REFCJ

100

Phase jitter. Deviation in edge location with respect to mean edge

location

t_REFPJ

–50

—

50

ps

—

14.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ± 300 ppm tolerance.

14.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer please use the PCI Express

Base Specification, Rev. 1.0a document.

14.4.1 Differential Transmitter (Tx) Output

Table 49 defines the specifications for the differential output at all transmitters. The parameters are

specified at the component pins.

Table 49. Differential Transmitter Output Specifications

Parameter

Symbol

Min

Nom Max Units

Notes

Unit Interval

UI

399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for

spread spectrum clock dictated variations. See Note 1.

Differential

V_TX-DIFFp-p

0.8

—

1.2

V

V_TX-DIFFp-p= 2 × |V_TX-D+– V_TX-D-| See Note 2.

Peak-to-Peak

Output Voltage

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PCI Express

Table 49. Differential Transmitter Output Specifications (continued)

Parameter

Symbol

Min

Nom Max Units

Notes

De- Emphasized

Differential

Output Voltage

(Ratio)

V_TX-DE-RATIO

–3.0

–3.5

–4.0

dB Ratio of the V_TX-DIFFp-pof the second and following bits

after a transition divided by the V_TX-DIFFp-pof the first

bit after a transition. See Note 2.

Minimum TX Eye

Width

T_TX-EYE

0.70

—

UI The maximum Transmitter jitter can be derived as

T_{TX-MAX-JITTER}= 1 – T_TX-EYE= 0.3 UI.

See Notes 2 and 3.

Maximum time

between the jitter

median and

maximum

deviation from

the median.

T_{TX-EYE-MEDIAN-to-}

0.15

UI Jitter is defined as the measurement variation of the

crossing points (V_TX-DIFFp-p= 0 V) in relation to a

recovered Tx UI. A recovered Tx UI is calculated over

3500 consecutive unit intervals of sample data. Jitter is

measured using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating the Tx UI.

See Notes 2 and 3.

MAX-JITTER

D+/D– Tx Output T_TX-RISE, T_TX-FALL0.125

Rise/Fall Time

—

UI See Notes 2 and 5

RMS AC Peak

Common Mode

Output Voltage

V_TX-CM-ACp

—

20

mV V_TX-CM-ACp= RMS(|V_TXD++ V_TXD-|/2 – V_TX-CM-DC

V_TX-CM-DC= DC_(avg)of |V_TX-D++ V_TX-D–|/2

See Note 2

)

AbsoluteDeltaof V_{TX-CM-DC-ACTIVE-}

0

—

100

25

mV |V_{TX-CM-DC (during L0)}– V_{TX-CM-Idle-DC (During Electrical}

_Idle)| ≤ 100 mV

DC Common

Mode Voltage

During L0 and

Electrical Idle

IDLE-DELTA

V_TX-CM-DC= DC_(avg)of |V_TX-D++ V_TX-D-|/2 [L0]

V_{TX-CM-Idle-DC}= DC_(avg)of |V_TX-D++ V_TX-D–|/2

[Electrical Idle]

See Note 2.

AbsoluteDeltaof V_{TX-CM-DC-LINE-DELTA}

DC Common

0

—

mV |V_TX-CM-DC-D+– V_TX-CM-DC-D-| ≤ 25 mV

V_TX-CM-DC-D+= DC_(avg)of |V_TX-D+

|

Mode between

D+ and D–

V_{TX-CM-DC-D–}= DC_(avg)of |V_TX-D–

See Note 2.

|

Electrical Idle

differential Peak

Output Voltage

V_{TX-IDLE-DIFFp}

0

—

20

mV V_{TX-IDLE-DIFFp}= |V_TX-IDLE-D+-V_TX-IDLE-D–| ≤ 20 mV

See Note 2.

The amount of

voltage change

allowed during

Receiver

V_{TX-RCV-DETECT}

—

600

mV The total amount of voltage change that a transmitter

can apply to sense whether a low impedance receiver

is present. See Note 6.

Detection

The Tx DC

Common Mode

Voltage

V_TX-DC-CM

0

—

3.6

90

V

The allowed DC common mode voltage under any

conditions. See Note 6.

Tx Short Circuit

Current Limit

I_TX-SHORT

—

mA The total current the transmitter can provide when

shorted to its ground

Minimum time

spent in

electrical idle

T_TX-IDLE-MIN

50

UI Minimum time a transmitter must be in electrical idle.

Utilized by the receiver to start looking for an electrical

idle exit after successfully receiving an electrical idle

ordered set.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

Parameter

Table 49. Differential Transmitter Output Specifications (continued)

Symbol

Min

Nom Max Units

Notes

Maximum time to T_{TX-IDLE-SET-TO-IDLE}

transition to a

valid electrical

idle after sending

an electrical idle

—

20

UI After sending an electrical idle ordered set, the

transmitter must meet all electrical idle specifications

within this time. This is considered a debounce time for

the transmitter to meet electrical idle after transitioning

from L0.

ordered set

Maximum time to T_{TX-IDLE-TO-DIFF-DATA}

transition to valid

Tx specifications

—

20

UI Maximum time to meet all Tx specifications when

transitioning from electrical idle to sending differential

data. This is considered a debounce time for the Tx to

meet all Tx specifications after leaving electrical idle

after leaving an

electrical idle

condition

Differential

Return Loss

RL_TX-DIFF

RL_TX-CM

Z_TX-DIFF-DC

Z_TX-DC

12

6

—

dB Measured over 50 MHz to 1.25 GHz. See Note 4

Common Mode

Return Loss

DC Differential

TX Impedance

80

40

—

75

100

—

120

—

Ω

TX DC differential mode low impedance

Transmitter DC

Impedance

Required TX D+ as well as D– DC impedance during

all states

Lane-to-Lane

Output Skew

L_TX-SKEW

—

500 +

2 UI

ps Static skew between any two transmitter lanes within a

single link

AC Coupling

Capacitor

C_TX

—

200

nF All transmitters shall be AC coupled. The AC coupling

is required either within the media or within the

transmitting component itself. See Note 8.

Crosslink

Random

Timeout

T_crosslink

0

—

1

ms This random timeout helps resolve conflicts in crosslink

configuration by eventually resulting in only one

downstream and one upstream port. See Note 7.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over

any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50)

3. A T_TX-EYE= 0.70 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.30 UI for the

transmitter collected over any 250 consecutive Tx UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}median is less than half of the total

TX jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and

D– line (that is, as measured by a Vector Network Analyzer with 50 Ω probes—see Figure 52). Note that the series capacitors

C_TXis optional for the return loss measurement.

5. Measured between 20–80% at transmitter package pins into a test load as shown in Figure 52 for both V_TX-D+and V_TX-D–

6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a

.

7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a

8. MPC8640D SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

14.4.2 Transmitter Compliance Eye Diagrams

The Tx eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express interconnect + Rx component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in

time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ

in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level

of the de-emphasized bit will always be relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered Tx UI is calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

V_RX-DIFF= 0 mV

V_TX-DIFF= 0 mV

(D+ D– Crossing Point)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

[De-Emphasized Bit]

566 mV (3 dB ) >= V_{TX-DIFFp-p-MIN}>= 505 mV (4 dB )

0.07 UI = UI – 0.3 UI (J_TX-TOTAL-MAX

)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

14.4.3 Differential Receiver (Rx) Input Specifications

Table 50 defines the specifications for the differential input at all receivers. The parameters are specified

at the component pins.

Table 50. Differential Receiver Input Specifications

Parameter

Symbol

Min

Nom

Max

Units

Comments

Unit Interval

UI

399.88

400

400.12

ps

Each UI is 400 ps 300 ppm. UI does not

account for spread spectrum clock dictated

variations. See Note 1.

Differential

Peak-to-Peak

Output Voltage

V_RX-DIFFp-p

0.175

0.4

—

1.200

—

V

V_RX-DIFFp-p= 2 × |V_RX-D+– V_RX-D–|

See Note 2.

Minimum

Receiver Eye

Width

T_RX-EYE

UI

The maximum interconnect media and

transmitter jitter that can be tolerated by the

receiver can be derived as T_{RX-MAX-JITTER}

1 – T_RX-EYE= 0.6 UI.

=

See Notes 2 and 3.

Maximum time

between the jitter

median and

maximum

deviation from

the median.

T_{RX-EYE-MEDIAN-to-MAX}

—

0.3

UI

Jitter is defined as the measurement variation

of the crossing points (V_RX-DIFFp-p= 0 V) in

relation to a recovered Tx UI. A recovered Tx

UI is calculated over 3500 consecutive unit

intervals of sample data. Jitter is measured

using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating

the Tx UI. See Notes 2, 3 and 7.

-JITTER

AC Peak

Common Mode

Input Voltage

V_RX-CM-ACp

—

150

—

mV

dB

V_RX-CM-ACp= |V_RXD+– V_RXD-|/2 – V_RX-CM-DC

V_RX-CM-DC= DC_(avg)of |V_RX-D+– V_RX-D–|/2

See Note 2

Differential

Return Loss

RL_RX-DIFF

15

Measured over 50 MHz to 1.25 GHz with the

D+ and D– lines biased at +300 mV and

–300 mV, respectively.

See Note 4

Common Mode RL_RX-CM

Return Loss

6

—

100

50

—

120

60

dB

Ω

Measured over 50 MHz to 1.25 GHz with the

D+ and D– lines biased at 0 V. See Note 4

DC Differential

Z_RX-DIFF-DC

80

Rx DC Differential mode impedance. See

Note 5

Input Impedance

DC Input

Z_RX-DC

40

Ω

Required Rx D+ as well as D– DC impedance

(50 20% tolerance). See Notes 2 and 5.

Impedance

Powered Down Z_{RX-HIGH-IMP-DC}

DC Input

Impedance

200

—

kΩ

Required Rx D+ as well as D– DC impedance

when the receiver terminations do not have

power. See Note 6.

Electrical Idle

V_{RX-IDLE-DET-DIFFp-p}

65

—

175

mV

V_{RX-IDLE-DET-DIFFp-p}= 2 × |V_RX-D+–V_RX-D–

|

Detect Threshold

Measured at the package pins of the receiver

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

Table 50. Differential Receiver Input Specifications (continued)

Parameter

Symbol

Min

Nom

Max

Units

Comments

An unexpected electrical Idle (V_RX-DIFFp-p<

V_{RX-IDLE-DET-DIFFp-p}) must be recognized no

longer than T_{RX-IDLE-DET-DIFF-ENTERING}to

signal an unexpected idle condition.

Unexpected

Electrical Idle

Enter Detect

Threshold

T_{RX-IDLE-DET-DIFF-}

—

10

ms

ENTERTIME

Integration Time

Total Skew

L_TX-SKEW

—

20

ns

Skew across all lanes on a link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five symbols) at

the Rx as well as any delay differences arising

from the interconnect itself.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 52 should be used

as the Rx device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 51). If the

clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The T_{RX-EYE-MEDIAN-to-MAX-JITTER}specification ensures a jitter distribution in

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The

reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by

a vector network analyzer with 50-Ω probes, see Figure 52). Note that the series capacitors C_TXis optional for the return loss

measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the Rx ground.

7. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

14.5 Receiver Compliance Eye Diagrams

The Rx eye diagram in Figure 51 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express Rx component.

Note that in general, the minimum receiver eye diagram measured with the compliance/test measurement

load (see Figure 52) is larger than the minimum receiver eye diagram measured over a range of systems at

the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is

due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI

Express component to vary in impedance from the compliance/test measurement load. The input receiver

eye diagram is implementation specific and is not specified. A Rx component designer should provide

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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PCI Express

additional margin to adequately compensate for the degraded minimum Rx eye diagram (shown in

Figure 51) expected at the input receiver based on some adequate combination of system simulations and

the return loss measured looking into the Rx package and silicon. The Rx eye diagram must be aligned in

time using the jitter median to locate the center of the eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50Ω to ground for

both the D+ and D– line (that is, as measured by a vector network analyzer

with 50-Ω probes—see Figure 52). Note that the series capacitors, C , are

TX

optional for the return loss measurement.

V_RX-DIFF= 0 mV

(D+ D– Crossing Point)

V_{RX-DIFFp-p-MIN}> 175 mV

0.4 UI = T_RX-EYE-MIN

Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification

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Serial RapidIO

14.5.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2

inches of the package pins, into a test/measurement load shown in Figure 52.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

D+ Package

C = C_TX

TX

Silicon

+ Package

C = C_TX

D– Package

R = 50 Ω

Figure 52. Compliance Test/Measurement Load

15 Serial RapidIO

This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8640,

for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links.

Two transmitter types (short run and long run) on a single receiver are specified for each of three baud

rates, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving two connectors across a backplane. A single receiver specification is given that will accept signals

from both the short run and long run transmitter specifications.

The short run transmitter specifications should be used mainly for chip-to-chip connections on either the

same printed circuit board or across a single connector. This covers the case where connections are made

to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall

power used by the transceivers.

The long run transmitter specifications use larger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications

allow a distance of at least 50 cm at all baud rates.

All unit intervals are specified with a tolerance of ± 100 ppm. The worst case frequency difference between

any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and technologies, AC

coupling at the receiver input must be used.

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Serial RapidIO

15.1 DC Requirements for Serial RapidIO SDn_REF_CLK and

SDn_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

15.2 AC Requirements for Serial RapidIO SDn_REF_CLK and

SDn_REF_CLK

Table 51 lists AC requirements.

Table 51. SDn_REF_CLK and SDn_REF_CLK AC Requirements

Symbol

Parameter Description

REFCLK cycle time

Min Typical Max Units

Comments

t_REF

—

10(8)

—

80

40

ns

ps

8 ns applies only to serial RapidIO

with 125-MHz reference clock

t_REFCJREFCLK cycle-to-cycle jitter. Difference in the

period of any two adjacent REFCLK cycles

—

t_REFPJPhase jitter. Deviation in edge location with

respect to mean edge location

–40

—

15.3 Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and

specification of differential signals. Figure 53 shows how the signals are defined. The figures show

waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal

swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows:

1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a

peak-to-peak swing of A – B volts

2. The differential output signal of the transmitter, V , is defined as V – V

TD

OD

TD

3. The differential input signal of the receiver, V , is defined as V – V

RD

ID

RD

4. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) volts

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5. The peak value of the differential transmitter output signal and the differential receiver input

signal is A – B volts

6. The peak-to-peak value of the differential transmitter output signal and the differential receiver

input signal is 2 × (A – B) volts

TD or RD

A Volts

TD or RD

B Volts

Differential Peak-Peak = 2 * (A-B)

Figure 53. Differential Peak-Peak Voltage of Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a current mode logic (CML)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD

and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak

differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

15.4 Equalization

With the use of high speed serial links, the interconnect media causes degradation of the signal at the

receiver. Effects such as inter-symbol interference (ISI) or data-dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techniques

that can be used are:

•

A passive high pass filter network placed at the receiver, often referred to as passive equalization.

The use of active circuits in the receiver, often referred to as adaptive equalization.

15.5 Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at

three baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to the serial RapidIO interface. The goal of this standard is that

electrical designs for the serial RapidIO interface can reuse electrical designs for XAUI, suitably modified

for applications at the baud intervals and reaches described herein.

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Serial RapidIO

15.6 Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and Table 52 through

Table 57.

The differential return loss, S11, of the transmitter in each case shall be better than

•

–10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz

–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency

The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential

return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components

related to the driver. The output impedance requirement applies to all valid output levels.

It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.

Table 52. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage

V_O

Volts

Voltage relative to COMMON of

either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

500

800

1000

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

ps

—

Multiple output skew

S_MO

1000

Skew at the transmitter output

between lanes of a multilane link

Unit Interval

UI

800

ps

100 ppm

Table 53. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage

V_O

Volts

Voltage relative to COMMON of

either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

500

1000

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

—

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Serial RapidIO

Table 53. Short Run Transmitter AC Timing Specifications—2.5 GBaud (continued)

Range

Parameter

Symbol

Unit

Notes

Min

Max

1000

Multiple Output skew

Unit Interval

S_MO

UI

—

ps

Skew at the transmitter output

between lanes of a multilane link

400

100 ppm

Table 54. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V_O

Volts

Voltage relative to COMMON of

either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

500

320

1000

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

ps

—

Multiple output skew

S_MO

1000

Skew at the transmitter output

between lanes of a multilane link

Unit Interval

UI

320

ps

100 ppm

Table 55. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V_O

Volts

Voltage relative to COMMON of

either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

800

1600

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

ps

—

Multiple output skew

S_MO

1000

Skew at the transmitter output

between lanes of a multilane link

Unit Interval

UI

800

ps

100 ppm

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Serial RapidIO

Table 56. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V_O

Volts

Voltage relative to COMMON of

either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

800

400

1600

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

ps

—

Multiple output skew

S_MO

1000

Skew at the transmitter output

between lanes of a multilane link

Unit Interval

UI

400

ps

100 ppm

Table 57. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V_O

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

Differential Output Voltage

Deterministic Jitter

V_DIFFPP

J_D

800

1600

0.17

mV p-p

UI p-p

—

Total Jitter

J_T

0.35

UI p-p

ps

—

Multiple output skew

S_MO

1000

Skew at the transmitter output

between lanes of a multilane

link

Unit Interval

UI

320

ps

100 ppm

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown

in Figure 54. This figure should be used with the parameters specified in Table 58 when measured at the

output pins of the device and the device is driving a 100-Ω ± 5% differential resistive load.The output eye

pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce

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inter-symbol interference) need only comply with the transmitter output compliance mask when

pre-emphasis is disabled or minimized.

V

max

min

DIFF

V

DIFF

0

–V

min

DIFF

–V

max

DIFF

0

A

B

1-B

1-A

1

Time in UI

Figure 54. Transmitter Output Compliance Mask

Table 58 specifies the parameters for the transmitter differential output eye diagram.

Table 58. Transmitter Differential Output Eye Diagram Parameters

Transmitter Type

1.25 GBaud short range

V_DIFFmin (mV)

V_DIFFmax (mV)

A (UI)

B (UI)

250

400

250

400

250

400

500

800

500

800

500

800

0.175

0.39

1.25 GBaud long range

2.5 GBaud short range

2.5 GBaud long range

3.125 GBaud short range

3.125 GBaud long range

15.7 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and Table 59 through Table 61.

Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode

return loss better than 6 dB from 100 MHz to (0.8) × (Baud Frequency). This includes contributions from

on-chip circuitry, the chip package and any off-chip components related to the receiver. AC-coupling

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Serial RapidIO

components are included in this requirement. The reference impedance for return loss measurements is

100-Ω resistive for differential return loss and 25-Ω resistive for common mode.

Table 59. Receiver AC Timing Specifications—1.25 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

Max

1600

Differential Input Voltage

V_IN

J_D

200

mV p-p

Measured at receiver

Deterministic Jitter Tolerance

0.37

0.55

—

UI p-p

Measured at receiver

Combined Deterministic and Random J_DR

Jitter Tolerance

Total Jitter Tolerance¹

J_T

0.65

—

UI p-p

ns

Measured at receiver

Multiple Input Skew

S_MI

—

24

Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate

Unit Interval

Note:

BER

UI

10^–12

800

—

ps

—

800

+/– 100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Table 60. Receiver AC Timing Specifications—2.5 GBaud

Range

Parameter

Symbol

Unit

Notes

Min

Max

Differential Input Voltage

V_IN

J_D

200

0.37

0.55

1600

—

mV p-p Measured at receiver

UI p-p Measured at receiver

Deterministic Jitter Tolerance

Combined Deterministic and Random

Jitter Tolerance

J_DR

—

Total Jitter Tolerance¹

J_T

0.65

—

UI p-p Measured at receiver

Multiple Input Skew

S_MI

24

ns

Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate

Unit Interval

Note:

BER

UI

—

10^–12

400

—

ps

—

400

100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

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Table 61. Receiver AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential Input Voltage

V_IN

J_D

200

0.37

0.55

1600

—

mV p-p Measured at receiver

UI p-p Measured at receiver

Deterministic Jitter Tolerance

Combined Deterministic and Random

Jitter Tolerance

J_DR

—

Total Jitter Tolerance¹

J_T

0.65

—

UI p-p Measured at receiver

Multiple Input Skew

S_MI

22

ns

Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate

Unit Interval

Note:

BER

UI

—

10^-12

320

—

ps

—

320

100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

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Serial RapidIO

Figure 55 shows the single frequency sinusoidal jitter limits.

8.5 UI p-p

Sinusoidal

Jitter

Amplitude

0.10 UI p-p

22.1 kHz

1.875 MHz

20 MHz

Frequency

Figure 55. Single Frequency Sinusoidal Jitter Limits

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Serial RapidIO

15.8 Receiver Eye Diagrams

For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the

corresponding bit error rate specification (Table 59 through Table 61) when the eye pattern of the receiver

test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the shown in

Figure 56 with the parameters specified in Table 62. The eye pattern of the receiver test signal is measured

at the input pins of the receiving device with the device replaced with a 100 Ω ± 5% differential resistive

load.

V

max

DIFF

V

min

DIFF

0

–V

min

DIFF

max

0

1

A

B

1-B

1-A

Time (UI)

Figure 56. Receiver Input Compliance Mask

Table 62 shows the parameters for the receiver input compliance mask exclusive of sinusoidal jitter.

Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver Type

V_DIFFmin (mV)

V_DIFFmax (mV)

A (UI)

B (UI)

1.25 GBaud

2.5 GBaud

100

800

0.275

0.400

3.125 GBaud

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Serial RapidIO

15.9 Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in clause

47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by

clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE802.3ae-2002 is specified as

the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE802.3ae-2002 is

recommended as a reference for additional information on jitter test methods.

15.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (Baud Frequency) ÷ 1667 is applied to the jitter. The data pattern for template measurements is the

continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial

link shall be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The

-12

amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V

.

differential. The left and right edges of the template shall be aligned with the mean zero crossing points of

the measured data eye. The load for this test shall be 100-Ω resistive ± 5% differential to 2.5 GHz.

15.9.2 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud

Frequency) ÷ 1667 is applied to the jitter. The data pattern for jitter measurements is the continuous jitter

test pattern (CJPAT) pattern defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall

be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter

tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described

in Annex 48B of IEEE802.3ae.

15.9.3 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100-Ω resistive ± 5%

differential to 2.5 GHz.

15.9.4 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in Section 15.7, “Receiver Specifications,”

and then adjusting the signal amplitude until the data eye contacts the six points of the minimum eye

opening of the receive template shown in Figure 56 and Table 62.Note that for this to occur, the test signal

must have vertical waveform symmetry about the average value and have horizontal symmetry (including

jitter) about the mean zero crossing. Eye template measurement requirements are as defined above.

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Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20

dB/decade roll-off below this. The required sinusoidal jitter specified in Section 15.7, “Receiver

Specifications,” is then added to the signal and the test load is replaced by the receiver being tested.

16 Package

This section details package parameters and dimensions.

16.1 Package Parameters for the MPC8640

The package parameters are as provided in the following list. The package type is 33 mm × 33 mm, 1023

pins. There are two package options: high-lead flip chip-ceramic ball grid array (FC-CBGA) and lead-free

(FC-CBGA).

For all package types:

Die size

12.1 mm × 14.7 mm

33 mm × 33 mm

1023

Package outline

Interconnects

Pitch

1 mm

Total Capacitor count

43 caps; 100 nF each

1

For high-lead FC-CBGA (package option: HCTE HX)

Maximum module height

Minimum module height

Solder Balls

2.97 mm

2.47 mm

89.5% Pb 10.5% Sn

0.60 mm

2

Ball diameter (typical )

1

For RoHS lead-free FC-CBGA (package option: HCTE VU)and lead-free FC-CBGA (package option:

1

HCTE VJ)

Maximum module height

Minimum module height

Solder Balls

2.77 mm

2.27 mm

95.5% Sn 4.0% Ag 0.5% Cu

0.60 mm

2

Ball diameter (typical )

1

High-coefficient of thermal expansion

2

Typical ball diameter is before reflow

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Package

16.2 Mechanical Dimensions of the MPC8640 FC-CBGA

The mechanical dimensions and bottom surface nomenclature of the MPC8640D (dual core) and

MPC8640 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA

(package option: HCTE VU) are shown respectfully in Figure 57 and Figure 58.

Figure 57. MPC8640D High-Lead FC-CBGA Dimensions

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Package

NOTES for Figure 57

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5. Capacitors may not be present on all devices.

6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top.

7. All dimensions symmetrical about centerlines unless otherwise specified.

8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package:

VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17,

Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).

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Package

Figure 58. MPC8640D Lead-Free FC-CBGA Dimensions

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Signal Listings

NOTES for Figure 58

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5. Capacitors may not be present on all devices.

6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top.

7. All dimensions symmetrical about centerlines unless otherwise specified.

8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package:

VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17,

Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).

17 Signal Listings

Table 63 provides the pin assignments for the signals. Notes for the signal changes on the single core

device (MPC8640) are italicized and prefixed by S.

Table 63. MPC8640 Signal Reference by Functional Block

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

DDR Memory Interface 1 Signals^2,3

D1_MDQ[0:63]

D15, A14, B12, D12, A15, B15, B13, C13,

C11, D11, D9, A8, A12, A11, A9, B9, F11,

G12, K11, K12, E10, E9, J11, J10, G8, H10,

L9, L7, F10, G9, K9, K8, AC6, AC7, AG8,

AH9, AB6, AB8, AE9, AF9, AL8, AM8,

AM10, AK11, AH8, AK8, AJ10, AK10, AL12,

AJ12, AL14, AM14, AL11, AM11, AM13,

AK14, AM15, AJ16, AK18, AL18, AJ15,

AL15, AL17, AM17

I/O

D1_GV_DD

—

D1_MECC[0:7]

D1_MDM[0:8]

M8, M7, R8, T10, L11, L10, P9, R10

I/O

O

D1_GV_DD

—

C14, A10, G11, H9, AD7, AJ9, AM12, AK16,

N10

D1_MDQS[0:8]

A13, C10, H12, J7, AE8, AM9, AK13, AK17,

N9

I/O

D1_GV_DD

—

D14, B10, H13, J8, AD8, AL9, AJ13, AM16,

P10

D1_MBA[0:2]

D1_MA[0:15]

AA8, AA10, T9

O

D1_GV_DD

—

Y10, W8, W9, V7, V8, U6, V10, U9, U7, U10,

Y9, T6, T8, AE12, R7, P6

D1_MWE

D1_MRAS

AB11

O

D1_GV_DD

—

23

—

AB12

D1_MCAS

AC10

D1_MCS[0:3]

D1_MCKE[0:3]

D1_MCK[0:5]

AB9, AD10, AC12, AD11

P7, M10, N8, M11

W6, E13, AH11, Y7, F14, AG10

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

91

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

D1_MCK[0:5]

D1_MODT[0:3]

D1_MDIC[0:1]

D1_MV_REF

Y6, E12, AH12, AA7, F13, AG11

AC9, AF12, AE11, AF10

E15, G14

O

D1_GV_DD

D1_GV_DD/2

—

27

3

IO

AM18

DDR Port 1

reference

voltage

DDR Memory Interface 2 Signals^2,3

D2_MDQ[0:63]

A7, B7, C5, D5, C8, D8, D6, A5, C4, A3, D3,

D2, A4, B4, C2, C1, E3, E1, H4, G1, D1, E4,

G3, G2, J4, J2, L1, L3, H3, H1, K1, L4, AA4,

AA2, AD1, AD2, Y1, AA1, AC1, AC3, AD5,

AE1, AG1, AG2, AC4, AD4, AF3, AF4, AH3,

AJ1, AM1, AM3, AH1, AH2, AL2, AL3, AK5,

AL5, AK7, AM7, AK4, AM4, AM6, AJ7

I/O

D2_GV_DD

—

D2_MECC[0:7]

D2_MDM[0:8]

D2_MDQS[0:8]

D2_MBA[0:2]

D2_MA[0:15]

H6, J5, M5, M4, G6, H7, M2, M1

C7, B3, F4, J1, AB1, AE2, AK1, AM5, K6

B6, B1, F1, K2, AB3, AF1, AL1, AL6, L6

A6, A2, F2, K3, AB2, AE3, AK2, AJ6, K5

W5, V5, P3

I/O

O

D2_GV_DD

—

I/O

O

W1, U4, U3, T1, T2, T3, T5, R2, R1, R5, V4,

R4, P1, AH5, P4, N1

O

D2_MWE

D2_MRAS

Y4

O

IO

D2_GV_DD

D2_GV_DD/2

—

23

—

27

3

W3

D2_MCAS

AB5

D2_MCS[0:3]

D2_MCKE[0:3]

D2_MCK[0:5]

D2_MODT[0:3]

D2_MDIC[0:1]

D2_MV_REF

Y3, AF6, AA5, AF7

N6, N5, N2, N3

U1, F5, AJ3, V2, E7, AG4

V1, G5, AJ4, W2, E6, AG5

AE6, AG7, AE5, AH6

F8, F7

A18

DDR Port 2

reference

voltage

High Speed I/O Interface 1 (SERDES 1)⁴

SD1_TX[0:7]

SD1_RX[0:7]

L26, M24, N26, P24, R26, T24, U26, V24

O

I

SV_DD

—

L27, M25, N27, P25, R27, T25, U27, V25

J32, K30, L32, M30, T30, U32, V30, W32

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

92

Signal Listings

Notes

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

SD1_RX[0:7]

SD1_REF_CLK

SD1_IMP_CAL_TX

SD1_IMP_CAL_RX

SD1_PLL_TPD

SD1_PLL_TPA

SD1_DLL_TPD

SD1_DLL_TPA

J31, K29, L31, M29, T29, U31, V29, W31

I

SV_DD

—

N32

N31

Y26

J28

I

—

Analog

O

19

30

U28

T28

N28

P31

13, 17

13, 18

13, 17

13, 18

Analog

O

Analog

High Speed I/O Interface 2 (SERDES 2)⁴

SD2_TX[0:3]

SD2_TX[4:7]

Y24, AA27, AB25, AC27

O

SV_DD

—

34

AE27, AG27, AJ27, AL27

O

SD2_TX[0:3]

Y25, AA28, AB26, AC28

O

—

SD2_TX[4:7]

AE28, AG28, AJ28, AL28

O

34

SD2_RX[0:3]

Y30, AA32, AB30, AC32

I

32

SD2_RX[4:7]

AH30, AJ32, AK30, AL32

I

32, 35

—

SD2_RX[0:3]

Y29, AA31, AB29, AC31

I

SD2_RX[4:7]

AH29, AJ31, AK29, AL31

I

35

SD2_REF_CLK

SD2_IMP_CAL_TX

SD2_IMP_CAL_RX

SD2_PLL_TPD

SD2_PLL_TPA

SD2_DLL_TPD

SD2_DLL_TPA

AE32

AE31

AM29

AA26

AF29

AF31

AD29

AD30

I

—

I

—

Analog

O

19

30

13, 17

13, 18

13, 17

13, 18

Analog

O

Analog

Special Connection Requirement pins

No Connects

K24, K25, P28, P29, W26, W27, AD25,

—

13

AD26

Reserved

H30, R32, V28, AG32

H29, R31, W28, AG31

AD24, AG26

—

14

15

16

Ethernet Miscellaneous Signals⁵

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

93

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

EC1_GTX_CLK125

EC2_GTX_CLK125

EC_MDC

AL23

AM23

G31

I

LV_DD

TV_DD

OV_DD

39

—

O

I/O

EC_MDIO

G32

eTSEC Port 1 Signals⁵

TSEC1_TXD[0:7]/

GPOUT[0:7]

AF25, AC23,AG24, AG23, AE24, AE23,

AE22, AD22

O

LV_DD

6, 10

TSEC1_TX_EN

TSEC1_TX_ER

TSEC1_TX_CLK

TSEC1_GTX_CLK

TSEC1_CRS

AB22

AH26

AC22

AH25

AM24

AM25

O

I

LV_DD

36

—

40

41

37

—

10

O

I/O

I

TSEC1_COL

TSEC1_RXD[0:7]/

GPIN[0:7]

AL25, AL24, AK26, AK25, AM26, AF26,

AH24, AG25

I

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_RX_CLK

AJ24

AJ25

AK24

I

LV_DD

—

40

eTSEC Port 2 Signals⁵

TSEC2_TXD[0:3]/

GPOUT[8:15]

AB20, AJ23, AJ22, AD19

O

LV_DD

6, 10

6,10, 38

6, 10

TSEC2_TXD[4]/

GPOUT[12]

AH23

TSEC2_TXD[5:7]/

GPOUT[13:15]

AH21, AG22, AG21

TSEC2_TX_EN

TSEC2_TX_ER

TSEC2_TX_CLK

TSEC2_GTX_CLK

TSEC2_CRS

AB21

AB19

AC21

AD20

AE20

AE21

O

I

LV_DD

36

6, 38

40

O

I/O

I

41

37

TSEC2_COL

—

TSEC2_RXD[0:7]/

GPIN[8:15]

AL22, AK22, AM21, AH20, AG20, AF20,

AF23, AF22

I

10

TSEC2_RX_DV

TSEC2_RX_ER

AC19

AD21

I

LV_DD

—

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

94

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

TSEC2_RX_CLK

AM22

I

LV_DD

40

eTSEC Port 3 Signals⁵

TSEC3_TXD[0:3]

TSEC3_TXD[4]/

TSEC3_TXD[5:7]

TSEC3_TX_EN

TSEC3_TX_ER

TSEC3_TX_CLK

TSEC3_GTX_CLK

TSEC3_CRS

AL21, AJ21, AM20, AJ20

O

I

TV_DD

6

AM19

—

6

AK21, AL20, AL19

AH19

36

—

40

41

37

—

AH17

AH18

AG19

O

I/O

I

AE15

TSEC3_COL

AF15

TSEC3_RXD[0:7]

AJ17, AE16, AH16, AH14, AJ19, AH15,

AG16, AE19

I

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_RX_CLK

AG15

AF16

AJ18

I

TV_DD

—

40

eTSEC Port 4 Signals⁵

TSEC4_TXD[0:3]

TSEC4_TXD[4]

TSEC4_TXD[5:7]

TSEC4_TX_EN

TSEC4_TX_ER

TSEC4_TX_CLK

TSEC4_GTX_CLK

TSEC4_CRS

AC18, AC16, AD18, AD17

O

I

TV_DD

6

AD16

25

6

AB18, AB17, AB16

AF17

36

—

40

41

37

—

AF19

AF18

AG17

O

I/O

I

AB14

TSEC4_COL

AC13

TSEC4_RXD[0:7]

AG14, AD13, AF13, AD14, AE14, AB15,

AC14, AE17

I

TSEC4_RX_DV

TSEC4_RX_ER

TSEC4_RX_CLK

AC15

AF14

AG13

I

TV_DD

—

40

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

95

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Local Bus Signals⁵

Pin Type

Power Supply

Notes

LAD[0:31]

A30, E29, C29, D28, D29, H25, B29, A29,

C28, L22, M22, A28, C27, H26, G26, B27,

B26, A27, E27, G25, D26, E26, G24, F27,

A26, A25, C25, H23, K22, D25, F25, H22

I/O

OV_DD

6

LDP[0:3]

LA[27:31]

LCS[0:4]

A24, E24, C24, B24

I/O

O

OV_DD

6, 22

7

J21, K21, G22, F24, G21

A22, C22, D23, E22, A23

O

LCS[5]/DMA_DREQ[2] B23

LCS[6]/DMA_DACK[2] E23

LCS[7]/DMA_DDONE[2] F23

O

OV_DD

7, 9, 10

7, 10

6

LWE[0:3]/

LSDDQM[0:3]/

LBS[0:3]

E21, F21, D22, E20

LBCTL

LALE

D21

E19

F20

H20

J20

O

OV_DD

—

25

—

LGPL0/LSDA10

LGPL1/LSDWE

LGPL2/LOE/

LSDRAS

LGPL3/LSDCAS

K20

L21

O

OV_DD

6

LGPL4/LGTA/

I/O

42

LUPWAIT/LPBSE

LGPL5

LCKE

J19

O

I

OV_DD

6

H19

—

LCLK[0:2]

LSYNC_IN

LSYNC_OUT

G19, L19, M20

M19

D20

O

DMA Signals⁵

DMA_DREQ[0:1]

E31, E32

I

OV_DD

—

9, 10

10

DMA_DREQ[2]/LCS[5] B23

DMA_DREQ[3]/IRQ[9] B30

I

DMA_DACK[0:1]

D32, F30

O

—

DMA_DACK[2]/LCS[6] E23

DMA_DACK[3]/IRQ[10] C30

10

9, 10

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

96

Signal Listings

Notes

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

DMA_DDONE[0:1]

F31, F32

O

OV_DD

—

10

DMA_DDONE[2]/LCS[7] F23

DMA_DDONE[3]/IRQ[11] D30

9, 10

Programmable Interrupt Controller Signals⁵

MCP_0

MCP _1

IRQ[0:8]

F17

H17

I

OV_DD

—

12, S4

—

G28, G29, H27, J23, M23, J27, F28, J24,

L23

I

IRQ[9]/DMA_DREQ[3] B30

IRQ[10]/DMA_DACK[3] C30

IRQ[11]/DMA_DDONE[3] D30

I

OV_DD

10

9, 10

IRQ_OUT

J26

O

OV_DD

7, 11

DUART Signals⁵

UART_SIN[0:1]

UART_SOUT[0:1]

UART_CTS[0:1]

UART_RTS[0:1]

B32, C32

D31, A32

A31, B31

C31, E30

I

OV_DD

—

O

I

O

I²C Signals

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

A16

B17

A21

B21

I/O

OV_DD

7, 11

System Control Signals⁵

HRESET

HRESET_REQ

SMI_0

B18

K18

L15

L16

C20

C21

L18

L17

J13

I

O

I

OV_DD

—

SMI_1

I

12, S4

—

SRESET_0

SRESET_1

CKSTP_IN

I

12, S4

—

I

CKSTP_OUT

READY/TRIG_OUT

O

7, 11

10, 25

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

97

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Debug Signals⁵

Pin Type

Power Supply

Notes

TRIG_IN

J14

J13

I

OV_DD

—

TRIG_OUT/READY

O

10, 25

6, 10

D1_MSRCID[0:1]/LB_SR F15, K15

CID[0:1]

D1_MSRCID[2]/LB_SRCI K14

D[2]

O

OV_DD

10, 25

10

D1_MSRCID[3:4]/LB_SR H15, G15

CID[3:4]

D2_MSRCID[0:4]

D1_MDVAL/LB_DVAL

D2_MDVAL

E16, C17, F16, H16, K16

O

OV_DD

—

10

—

J16

D19

Power Management Signals⁵

System Clocking Signals⁵

ASLEEP

C19

O

OV_DD

—

SYSCLK

RTC

G16

K17

B16

I

OV_DD

—

32

23

CLK_OUT

O

Test Signals⁵

JTAG Signals⁵

LSSD_MODE

C18

I

OV_DD

26

TEST_MODE[0:3]

C16, E17, D18, D16

TCK

TDI

H18

J18

G18

F18

A17

I

OV_DD

—

24

23

24

TDO

TMS

TRST

O

I

Miscellaneous⁵

Spare

J17

—

O

—

13

GPOUT[0:7]/

TSEC1_TXD[0:7]

AF25, AC23, AG24, AG23, AE24, AE23,

AE22, AD22

OV_DD

6, 10

GPIN[0:7]/

TSEC1_RXD[0:7]

AL25, AL24, AK26, AK25, AM26, AF26,

AH24, AG25

I

OV_DD

10

GPOUT[8:15]/

TSEC2_TXD[0:7]

AB20, AJ23, AJ22, AD19, AH23, AH21,

AG22, AG21

O

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

98

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

GPIN[8:15]/

TSEC2_RXD[0:7]

AL22, AK22, AM21, AH20, AG20, AF20,

AF23, AF22

I

OV_DD

10

Additional Analog Signals

TEMP_ANODE

AA11

Y11

Thermal

—

TEMP_CATHODE

Sense, Power and GND Signals

SENSEV_DD_Core0

SENSEV_DD_Core1

SENSEV_SS_Core0

SENSEV_SS_Core1

SENSEV_DD_PLAT

SENSEV_SS_PLAT

D1_GV_DD

M14

U20

P14

V20

N18

P18

V_DD_Core0

sensing pin

—

31

12,31, S1

31

V_DD_Core1

sensing pin

Core0 GND

sensing pin

Core1 GND

sensing pin

12, 31, S3

28

V_DD_PLAT

sensing pin

Platform GND

sensing pin

29

B11, B14, D10, D13, F9, F12, H8, H11, H14, SDRAM 1 I/O

D1_GV_DD

• 2.5 DDR

• 1.8 DDR2

—

K10, K13, L8, P8, R6, U8, V6, W10, Y8,

AA6, AB10, AC8, AD12, AE10, AF8, AG12,

AH10, AJ8, AJ14, AK12, AL10, AL16

supply

D2_GV_DD

B2, B5, B8, D4, D7, E2, F6, G4, H2, J6, K4, SDRAM 2 I/O

D2_GV_DD

• 2.5 V DDR

• 1.8 V DDR2

—

L2, M6, N4, P2, T4, U2, W4, Y2, AB4, AC2,

AD6, AE4, AF2, AG6, AH4, AJ2, AK6, AL4,

AM2

supply

OV_DD

B22, B25, B28, D17, D24, D27, F19, F22,

DUART, Local

F26, F29, G17, H21, H24, K19, K23, M21, Bus, DMA,

AM30

Multiprocessor

Interrupts,

System Control

& Clocking,

Debug, Test,

JTAG, Power

management,

I²C, JTAG and

Miscellaneous

I/O voltage

OV_DD

3.3 V

LV_DD

TV_DD

AC20, AD23, AH22

AC17, AG18, AK20

TSEC1 and

TSEC2 I/O

voltage

LV_DD

2.5/3.3 V

—

TSEC3 and

TSEC4 I/O

voltage

TV_DD

2.5/3.3 V

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

99

Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

SV_DD

H31, J29, K28, K32, L30, M28, M31, N29,

R30, T31, U29, V32, W30, Y31, AA29,

AB32, AC30, AD31, AE29, AG30, AH31,

AJ29, AK32, AL30, AM31

Transceiver

Power Supply

SerDes

—

SV_DD

1.05/1.1 V

XV_{DD_}SRDS1

XV_{DD_}SRDS2

V_DD_Core0

V_DD_Core1

K26, L24, M27, N25, P26, R24, R28, T27,

U25, V26

Serial I/O

Power Supply

for SerDes

Port 1

XV_{DD_}SRDS1

1.05/1.1 V

AA25, AB28, AC26, AD27, AE25, AF28,

AH27, AK28, AM27, W24, Y27

Serial I/O

Power Supply

for SerDes

Port 2

XV_{DD_}SRDS2

1.05/1.1 V

—

L12, L13, L14, M13, M15, N12, N14, P11,

P13, P15, R12, R14, T11, T13, T15, U12,

U14, V11, V13, V15, W12, W14, Y12, Y13,

Y15, AA12, AA14, AB13

Core 0 voltage

supply

V_DD_Core0

0.95/1.05/1.1

V

R16, R18, R20, T17, T19, T21, T23, U16,

U18, U22, V17, V19, V21, V23, W16, W18,

W20, W22, Y17, Y19, Y21, Y23, AA16,

AA18, AA20, AA22, AB23, AC24

Core 1 voltage

supply

V_DD_Core1

12, S1

0.95/1.05/1.1

V

V_DD_PLAT

M16, M17, M18, N16, N20, N22, P17, P19, Platformsupply

V_DD_PLAT

1.05/1.1 V

—

P21, P23, R22

voltage

AV_DD_Core0

B20

Core 0 PLL

Supply

AV_DD_Core0

0.95/1.05/

1.1 V

AV_DD_Core1

A19

Core 1 PLL

Supply

AV_DD_Core1

0.95/1.05/

1.1 V

12, S2

AV_DD_PLAT

AV_DD_LB

B19

A20

P32

Platform PLL

supply voltage

AV_DD_PLAT

1.05/1.1 V

—

Local Bus PLL

supply voltage

AV_DD_LB

1.05/1.1 V

AV_DD_SRDS1

SerDes Port 1 AV_DD_SRDS1

PLL & DLL

Power Supply

1.05/1.1 V

AV_DD_SRDS2

AF32

SerDes Port 2 AV_DD_SRDS2

PLL & DLL

—

Power Supply

1.05/1.1 V

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

GND

C3, C6, C9, C12, C15, C23, C26, E5, E8,

E11, E14, E18, E25, E28, F3, G7, G10, G13,

G20, G23, G27, G30, H5, J3, J9, J12, J15,

J22, J25, K7, L5, L20, M3, M9, M12, N7,

N11, N13, N15, N17, N19, N21, N23, P5,

P12, P16, P20, P22, R3, R9, R11, R13, R15,

R17, R19, R21, R23, T7, T12, T14, T16,

T18, T20, T22, U5, U11,U13, U15, U17,

U19, U21, U23, V3, V9, V12, V14, V16, V18,

V22, W7, W11, W13, W15, W17, W19, W21,

W23,Y5, Y14, Y16, Y18, Y20, Y22, AA3,

AA9, AA13, AA15, AA17, AA19, AA21,

AA23, AB7, AB24, AC5, AC11, AD3, AD9,

AD15, AE7, AE13, AE18, AF5, AF11, AF21,

AF24, AG3, AG9, AH7, AH13, AJ5, AJ11,

AK3, AK9, AK15, AK19, AK23, AL7, AL13

GND

—

AGND_SRDS1

AGND_SRDS2

SGND

P30

SerDes Port 1

Ground pin for

AV_DD_SRDS1

—

AF30

SerDes Port 2

Ground pin for

AV_DD_SRDS2

H28, H32, J30, K31, L28, L29, M32, N30,

R29, T32, U30, V31, W29,Y32 AA30, AB31,

AC29, AD32, AE30, AG29, AH32, AJ30,

AK31, AL29, AM32

Ground pins for

SV_DD

XGND

K27, L25, M26, N24, P27, R25, T26, U24,

Ground pins for

—

V27, W25, Y28, AA24, AB27, AC25, AD28, XV_DD_SRDSn

AE26, AF27, AH28, AJ26, AK27, AL26,

AM28

Reset Configuration Signals²⁰

TSEC1_TXD[0] /

cfg_alt_boot_vec

AF25

—

LV_DD

—

21

—

38

TSEC1_TXD[1]/

cfg_platform_freq

AC23

TSEC1_TXD[2:4]/

cfg_device_id[5:7]

AG24, AG23, AE24

AE23

TSEC1_TXD[5]/

cfg_tsec1_reduce

TSEC1_TXD[6:7]/

cfg_tsec1_prtcl[0:1]

AE22, AD22

AB20, AJ23, AJ22, AD19

TSEC2_TXD[0:3]/

cfg_rom_loc[0:3]

TSEC2_TXD[4],

TSEC2_TX_ER/

cfg_dram_type[0:1]

AH23,

AB19

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Signal Listings

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Name¹

Package Pin Number

Pin Type

Power Supply

Notes

TSEC2_TXD[5]/

AH21

—

LV_DD

—

cfg_tsec2_reduce

TSEC2_TXD[6:7]/

cfg_tsec2_prtcl[0:1]

AG22, AG21

AL21, AJ21

AM20

—

O

LV_DD

TV_DD

LV_DD

OV_DD

—

33

—

TSEC3_TXD[0:1]/

cfg_spare[0:1]

TSEC3_TXD[2]/

cfg_core1_enable

O

TSEC3_TXD[3]/

cfg_core1_lm_offset

AJ20

—

TSEC3_TXD[5]/

cfg_tsec3_reduce

AK21

TSEC3_TXD[6:7]/

cfg_tsec3_prtcl[0:1]

AL20, AL19

AC18, AC16, AD18, AD17

AB18

TSEC4_TXD[0:3]/

cfg_io_ports[0:3]

TSEC4_TXD[5]/

cfg_tsec4_reduce

TSEC4_TXD[6:7]/

cfg_tsec4_prtcl[0:1]

AB17, AB16

LAD[0:31]/

cfg_gpporcr[0:31]

A30, E29, C29, D28, D29, H25, B29, A29,

C28, L22, M22, A28, C27, H26, G26, B27,

B26, A27, E27, G25, D26, E26, G24, F27,

A26, A25, C25, H23, K22, D25, F25, H22

LWE[0]/

cfg_cpu_boot

E21

—

OV_DD

—

22

—

LWE[1]/

cfg_rio_sys_size

F21

LWE[2:3]/

cfg_host_agt[0:1]

D22, E20

LDP[0:3], LA[27] /

cfg_core_pll[0:4]

A24, E24, C24, B24,

J21

LA[28:31]/

cfg_sys_pll[0:3]

K21, G22, F24, G21

LGPL[3],

LGPL[5]/

K20,

J19

cfg_boot_seq[0:1]

D1_MSRCID[0]/

cfg_mem_debug

F15

K15

—

OV_DD

—

D1_MSRCID[1]/

cfg_ddr_debug

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Signal Listings

Notes

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Package Pin Number Pin Type Power Supply

Name¹

Note:

1. Multi-pin signals such as D1_MDQ[0:63] and D2_MDQ[0:63] have their physical package pin numbers listed in order

corresponding to the signal names.

2. Stub Series Terminated Logic (SSTL-18 and SSTL-25) type pins.

3. If a DDR port is not used, it is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset. Note

that these power supplies can only be powered up again at reset for functionality to occur on the DDR port.

4. Low Voltage Differential Signaling (LVDS) type pins.

5. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.

6. This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset

Configuration Signals section of this table for config name and connection details.

7. Recommend a weak pull-up resistor (1–10 kΩ) be placed from this pin to its power supply.

8. Recommend a weak pull-down resistor (2–10 kΩ) be placed from this pin to ground.

9. This multiplexed pin has input status in one mode and output in another

10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table.

11. This pin is open drain signal.

12. Functional only on the MPC8640D.

13. These pins should be left floating.

14. These pins should be connected to SV_DD

.

15. These pins should be pulled to ground with a strong resistor (270-Ω to 330-Ω).

16. These pins should be connected to OVDD.

17.This is a SerDes PLL/DLL digital test signal and is only for factory use.

18. This is a SerDes PLL/DLL analog test signal and is only for factory use.

19. This pin should be pulled to ground with a 100-Ω resistor.

20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when

the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down

resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down

the value of the net at reset, then a pullup or active driver is needed.

21. Should be pulled down at reset if platform frequency is at 400 MHz.

22. These pins require 4.7-kΩ pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration

ratios at reset.

23. This output is actively driven during reset rather than being released to high impedance during reset.

24 These JTAG pins have weak internal pull-up P-FETs that are always enabled.

25. This pin should NOT be pulled down (or driven low) during reset.

26.These are test signals for factory use only and must be pulled up (100-Ω to 1- kΩ.) to OVDD for normal machine operation.

27. Dn_MDIC[0] should be connected to ground with an 18-Ω resistor 1-Ω and Dn_MDIC[1] should be cLonnected Dn_GVDD

with an 18-Ω resistor 1-Ω. These pins are used for automatic calibration of the DDR IOs.

28. Pin N18 is recommended as a reference point for determining the voltage of V_DD_PLAT and is hence considered as the

V_DD_PLAT sensing voltage and is called SENSEVDD_PLAT.

29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT.

30.This pin should be pulled to ground with a 200-Ω resistor.

31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve

tracking and regulation.

32. Must be tied low if unused

33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull-up/down

option to allow flexibility of future designs.

34. Used as serial data output for serial RapidIO 1×/4× link.

35. Used as serial data input for serial RapidIO 1×/4× link.

36.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively

driven.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Clocking

Table 63. MPC8640 Signal Reference by Functional Block (continued)

Package Pin Number Pin Type Power Supply

37.This pin is only an output in FIFO mode when used as Rx Flow Control.

Name¹

Notes

38.This pin functions as cfg_dram_type[0 or 1] at reset. Note: This pin must be valid before HRESET assertion in device sleep

mode.

39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).

40. See Section 18.4.2, “Platform to FIFO Restrictions” for clock speed limitations for this pin when used in FIFO mode.

41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps.

The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.

42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.

Special Notes for Single Core Device:

S1. Solder ball for this signal will not be populated in the single core package.

S2. The PLL filter from V_DD_Core1 to AV_DD_Core1 should be removed. AV_DD_Core1 should be pulled to ground with a weak

(2–10 kΩ) resistor. See Section 20.2.1, “PLL Power Supply Filtering” for more details.

S3. This pin should be pulled to GND for the single core device.

S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.

18 Clocking

This section describes the PLL configuration of the MPC8640. Note that the platform clock is identical to

the MPX clock.

18.1 Clock Ranges

Table 64 provides the clocking specifications for the processor cores, and Table 65 provides the clocking

specifications for the memory bus. Table 66 provides the clocking for the Platform/MPX bus, and Table 67

provides the clocking for the local bus.

Table 64. Processor Core Clocking Specifications

Maximum Processor Core Frequency

Parameter

1000 MHz

1067 MHz

1250MHz

Unit

Notes

Min

800

Max

Min

800

Max

Min

800

Max

e600 core processor frequency

1000

1067

1250

MHz

1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”

for ratio settings.

2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Clocking

Table 65. Memory Bus Clocking Specifications

Maximum Processor Core

Frequency

Parameter

Unit

Notes

1000, 1067, 1250 MHz

Min

Max

Memory bus clock frequency

Notes:

200

266

MHz

1, 2

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”

for ratio settings.

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.

Table 66. Platform/MPX bus Clocking Specifications

Maximum Processor Core

Frequency

Parameter

Unit

Notes

1000, 1067, 1250 MHz

Min

Max

Platform/MPX bus clock frequency

400

533

MHz

1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”

for ratio settings.

2. Platform/MPX frequencies between 400 and 500 MHz are not supported.

Table 67. Local Bus Clocking Specifications

Maximum Processor Core

Frequency

Parameter

Unit

Notes

1000, 1067, 1250 MHz

Min

Max

Local bus clock speed (for Local Bus Controller)

25

133

MHz

1

Notes:

1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in

LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.

18.2 MPX to SYSCLK PLL Ratio

The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency

of the MPX is set using the following reset signals, as shown in Table 68:

•

SYSCLK input signal

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Clocking

•

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that the DDR data rate is the determining factor in selecting the MPX bus frequency because the MPX

frequency must equal the DDR data rate.

Table 68. MPX:SYSCLK Ratio

Binary Value of

MPX:SYSCLK Ratio

LA[28:31] Signals

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

Reserved

2:1

3:1

4:1

5:1

6:1

Reserved

8:1

Reserved

18.3 e600 to MPX clock PLL Ratio

Table 69 describes the clock ratio between the platform and the e600 core clock. This ratio is determined

by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in

Table 69.

Table 69. e600 Core to MPX Clock Ratio

Binary Value of

e600 core: MPX Clock Ratio

LDP[0:3], LA[27] Signals

01000

01100

10000

11100

10100

01110

2:1

2.5:1

3:1

Reserved

18.4 Frequency Options

This section discusses the frequency options for the MPC8640.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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18.4.1 SYSCLK to Platform Frequency Options

Table 70 shows some SYSCLK frequencies and the expected MPX frequency values based on the MPX

clock to SYSCLK ratio. Note that frequencies between 400 MHz and 500 MHz are not supported on the

platform. See note regarding cfg_platform_freq in Section 17, “Signal Listings,” because it is a reset

configuration pin that is related to platform frequency.

Table 70. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed

MPX to

SYSCLK

Ratio

SYSCLK (MHz)

100

66

83

133

167

Platform/MPX Frequency (MHz)¹

2

3

4

5

6

8

400

500

400

500

533

400

533

500

1

SYSCLK frequency range is 66-167 MHz. Platform clock/MPX

frequency range is 400 MHz, 500-533 MHz.

18.4.2 Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed:

For FIFO GMII mode:

FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 4.2

For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no

more than 119 MHz.

For FIFO encoded mode:

FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2

For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no

more than 156 MHz.

19 Thermal

This section describes the thermal specifications of the MPC8640.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Thermal

19.1 Thermal Characteristics

Table 71 provides the package thermal characteristics for the MPC8640.

1

Table 71. Package Thermal Characteristics

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board

Junction-to-board thermal resistance

R

18

13

9

°C/W

1, 2

1, 3

4

JA

θ

R

JMA

θ

R

θ

R

5

JB

JC

θ

Junction-to-case thermal resistance

R

< 0.1

5

θ

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. This is the thermal resistance between die and case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 °C/W.

19.2 Thermal Management Information

This section provides thermal management information for the high coefficient of thermal expansion

(HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the

system-level design—the heat sink, airflow, and thermal interface material. The MPC8640 implements

several features designed to assist with thermal management, including the temperature diode. The

temperature diode allows an external device to monitor the die temperature in order to detect excessive

temperature conditions and alert the system; see Section 19.2.4, “Temperature Diode,” for more

information.

To reduce the die-junction temperature, heat sinks are required. Due to the potential large mass of the heat

sink, attachment through the printed-circuit board is suggested. In any implementation of a heat sink

solution, the force on the die should not exceed ten pounds force (45 newtons). Figure 59 shows a spring

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

108

Freescale Semiconductor

Thermal

clip through the board. Occasionally the spring clip is attached to soldered hooks or to a plastic backing

structure. Screw and spring arrangements are also frequently used.

HCTE FC-CBGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 59. FC-CBGA Package Exploded Cross-Sectional View with Several Heat Sink Options

There are several commercially-available heat sinks for the MPC8640 provided by the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

781-769-2800

408-749-7601

888-732-6100

Advanced Thermal Solutions

89 Access Road #27.

Norwood, MA02062

Internet: www.qats.com

Alpha Novatech

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alphanovatech.com

Calgreg Thermal Solutions

60 Alhambra Road, Suite 1

Warwick, RI 02886

Internet: www.calgreg.com

International Electronic Research Corporation (IERC)818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

109

Thermal

Millennium Electronics (MEI)

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

408-436-8770

800-522-6752

603-635-5102

Internet: www.mei-thermal.com

Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

19.2.1 Internal Package Conduction Resistance

For the exposed-die packaging technology described in Table 71, the intrinsic conduction thermal

resistance paths are as follows:

•

The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die)

The die junction-to-board thermal resistance

Figure 60 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance.)

Figure 60. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Thermal

Heat generated on the active side of the chip is conducted through the silicon, then the heat sink attach

material (or thermal interface material), and finally to the heat sink where it is removed by forced-air

convection.

Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected

for a first-order analysis. Thus the thermal interface material and the heat sink conduction/convective

thermal resistances are the dominant terms.

19.2.2 Thermal Interface Materials

A thermal interface material is recommended at the package-to-heat sink interface to minimize the thermal

contact resistance. Figure 61 shows the thermal performance of three thin-sheet thermal-interface

materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function

of contact pressure. As shown, the performance of these thermal interface materials improves with

increasing contact pressure. The use of thermal grease significantly reduces the interface thermal

resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the

thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board

(see Figure 59). Therefore, synthetic grease offers the best thermal performance, considering the low

interface pressure, and is recommended due to the high power dissipation of the MPC8640. Of course, the

selection of any thermal interface material depends on many factors—thermal performance requirements,

manufacturability, service temperature, dielectric properties, cost, and so on.

Silicone Sheet (0.006 in.)

Bare Joint

2

Fluoroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

10

20

30

Contact Pressure (psi)

Figure 61. Thermal Performance of Select Thermal Interface Material

40

50

60

70

80

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

111

Thermal

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration

requirements. There are several commercially available thermal interfaces and adhesive materials

provided by the following vendors:

The Bergquist Company

18930 West 78 St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

800-347-4572

781-935-4850

800-248-2481

th

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01801

Internet: www.chomerics.com

Dow-Corning Corporation

Corporate Center

PO Box 994

Midland, MI 48686-0994

Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

888-246-9050

Internet: www.microsi.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

The following section provides a heat sink selection example using one of the commercially available heat

sinks.

19.2.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (R + R

+ R ) × P

θsa d

j

i

r

θJC

θint

where:

T is the die-junction temperature

j

T is the inlet cabinet ambient temperature

i

T is the air temperature rise within the computer cabinet

r

R

is the junction-to-case thermal resistance

θJC

θint

θsa

is the adhesive or interface material thermal resistance

is the heat sink base-to-ambient thermal resistance

P is the power dissipated by the device

d

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

Thermal

During operation, the die-junction temperatures (T ) should be maintained less than the value specified in

j

Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature

and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )

i

may range from 30 to 40 °C. The air temperature rise within a cabinet (T ) may be in the range of

r

5 to 10 °C. The thermal resistance of the thermal interface material (R ) is typically about 0.2 °C/W. For

θint

example, assuming a T of 30 °C, a T of 5 °C, a package R

= 0.1, and a typical power consumption (P )

i

r

θJC

d

of 43.4 W, the following expression for T is obtained:

j

Die-junction temperature: T = 30 °C + 5 °C + (0.1 °C/W + 0.2 °C/W + θ ) × 43.4 W

j

sa

For this example, a R value of 1.32 °C/W or less is required to maintain the die junction temperature

θsa

below the maximum value of Table 2.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common

figure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat flow. The final die-junction

operating temperature is not only a function of the component-level thermal resistance, but the

system-level design and its operating conditions. In addition to the component's power consumption, a

number of factors affect the final operating die-junction temperature—airflow, board population (local

heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect

technology, system air temperature rise, altitude, and so on.

Due to the complexity and variety of system-level boundary conditions for today's microelectronic

equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)

may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as

well as system-level designs.

For system thermal modeling, the MPC8640 thermal model is shown in Figure 62. Four cuboids are used

to represent this device. The die is modeled as 12.4 × 15.3 mm at a thickness of 0.86 mm. See Section 3,

“Power Characteristics,” for power dissipation details. The substrate is modeled as a single block

33×33×1.2 mm with orthotropic conductivity: 13.5 W/(m • K) in the xy-plane and 5.3 W/(m • K) in the

z-direction. The die is centered on the substrate. The bump/underfill layer is modeled as a collapsed

thermal resistance between the die and substrate with a conductivity of 5.3 W/(m • K) in the thickness

dimension of 0.07 mm. Because the bump/underfill is modeled with zero physical dimension (collapsed

height), the die thickness was slightly enlarged to provide the correct height. The C5 solder layer is

modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal conductivity of 0.034 W/(m

• K) in the xy-plane and 9.6 W/(m • K) in the z-direction. An LGA solder layer would be modeled as a

collapsed thermal resistance with thermal conductivity of 9.6W/(m • K) and an effective height of 0.1 mm.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

113

Thermal

The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual

dimensions.

Conductivity

Value

Unit

Die

Die (12.4 × 15.3 × 0.86 mm)

Bump and Underfill

z

Silicon

Temperature

dependent

Substrate

C5 solder layer

Bump and Underfill (12.4 × 15.3 × 0.07 mm)

Collapsed Resistance

Side View of Model (Not to Scale)

k_z

5.3

W/(m • K)

x

Substrate (33 × 33 × 1.2 mm)

k_x

k_y

k_z

13.5

5.3

Substrate

Die

C5 Solder layer (33 × 33 × 0.4 mm)

k_x

0.034

9.6

W/(m • K)

k_y

k_z

y

Top View of Model (Not to Scale)

Figure 62. Recommended Thermal Model of MPC8640

19.2.4 Temperature Diode

The MPC8640 has a temperature diode on the microprocessor that can be used in conjunction with other

system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the

negative temperature coefficient of a diode operated at a constant current to determine the temperature of

the microprocessor and its environment. It is recommended that each device be individually calibrated.

The following are the specifications of the MPC8640 on-board temperature diode:

V > 0.40 V

f

V < 0.90 V

f

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

114

Thermal

An approximate value of the ideality may be obtained by calibrating the device near the expected operating

temperature.

Ideality factor is defined as the deviation from the ideal diode equation:

qV

___f

nKT

I_fw= I_se

– 1

Another useful equation is:

KT

I

__

_H_

V_H– V_L= n

ln

q

I

L

Where:

I

= Forward current

= Saturation current

fw

s

V = Voltage at diode

d

V = Voltage forward biased

f

V = Diode voltage while I is flowing

H

V = Diode voltage while I is flowing

L

I

= Larger diode bias current

= Smaller diode bias current

H

L

–19

q = Charge of electron (1.6 x 10

n = Ideality factor (normally 1.0)

C)

–23

K = Boltzman’s constant (1.38 x 10 Joules/K)

T = Temperature (Kelvins)

The ratio of I to I is usually selected to be 10:1. The above simplifies to the following:

H

L

V_H– V_L= 1.986 × 10^–4× nT

Solving for T, the equation becomes:

_{__}V_{__}_H_{__}–_{__}V_{_}_L_{_}

nT =

1.986 × 10^–4

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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115

System Design Information

20 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8640.

20.1 System Clocking

This device includes six PLLs, as follows:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio

configuration bits as described in Section 18.2, “MPX to SYSCLK PLL Ratio.”

•

The dual e600 Core PLLs generate the e600 clock from the externally supplied input.

The local bus PLL generates the clock for the local bus.

There are two internal PLLs for the SerDes block.

20.2 Power Supply Design and Sequencing

This section describes the power supply design and sequencing.

20.2.1 PLL Power Supply Filtering

Each of the PLLs listed in Section 20.1, “System Clocking,” is provided with power through independent

power supply pins.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits per PLL power supply as illustrated in Figure 64, one to each of the

AV type pins. By providing independent filters to each PLL the opportunity to cause noise injection

DD

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AV type pin being supplied to minimize

DD

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

type pin, which is on the periphery of the footprint, without the inductance of vias.

DD

Figure 63 and Figure 64 show the PLL power supply filter circuits for the platform and cores, respectively.

10 Ω

V_DD_PLAT

AV_DD_PLAT, AV_DD_LB;

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

116

Freescale Semiconductor

System Design Information

Filter Circuit (should not be used for Single core device)

10 Ω

V_DD_Core0/1

AV_DD_Core0/1

2.2 µF

Low ESL Surface Mount Capacitors

GND

Note: For single core device the filter circuit (in the dashed box) should

be removed and AV_DD_Core1 should be tied to ground with a weak

(2–10 kΩ) pull-down resistor.

Figure 64. MPC8640 PLL Power Supply Filter Circuit (for cores)

The AV _SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability

DD

of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AV _SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be

DD

near the AV _SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the two 2.2-µF

DD

capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from

AV _SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant

DD

frequency. All traces should be kept short, wide, and direct.

1.0 Ω

SV_DD

AV_DD_SRDSn

2.2 µF ¹

0.003 µF

GND

1. An 0805 sized capacitor is recommended for system initial bring-up.

Figure 65. SerDes PLL Power Supply Filter

Note the following:

•

AV _SRDSn should be a filtered version of SV

.

DD

Signals on the SerDes interface are fed from the SV power plan.

DD

20.2.2 PLL Power Supply Sequencing

For details on power sequencing for the AV type and supplies refer to Section 2.2, “Power-Up/Down

DD

Sequence.”

20.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8640 system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

117

System Design Information

designer place at least one decoupling capacitor at each OV , Dn_GV , LV , TV , V _Coren,

DD

and V _PLAT pin of the device. These decoupling capacitors should receive their power from separate

DD

OV , Dn_GV , LV , TV , V _Coren, and V _PLAT and GND power planes in the PCB,

DD

utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a

standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the OV , Dn_GV , LV , TV , V _Coren, and V _PLAT planes, to enable quick

DD

recharging of the smaller chip capacitors. They should also be connected to the power and ground planes

through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum

or Sanyo OSCON).

20.4 SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SV and XV _SRDSn) to ensure

DD

low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be

done for all SerDes supplies.

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

20.5 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. In general all unused active low inputs should be tied to OV , Dn_GV , LV , TV ,

DD

V

_Coren, and V _PLAT, XV _SRDSn, and SV as required and unused active high inputs should

DD

DD DD DD

be connected to GND. All NC (no-connect) signals must remain unconnected.

The following list explains the special cases:

•

DDR—If one of the DDR ports is not being used the power supply pins for that port can be

connected to ground so that there is no need to connect the individual unused inputs of that port to

ground. Note that these power supplies can only be powered up again at reset for functionality to

occur on the DDR port. Power supplies for other functional buses should remain powered.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

118

Freescale Semiconductor

System Design Information

•

Local Bus—If parity is not used, tie LDP[0:3] to ground via a 4.7-kΩ resistor, tie LPBSE to OV

via a 4.7-kΩ resistor (pull-up resistor). For systems which boot from Local Bus

(GPCM)-controlled flash, a pull-up on LGPL4 is required.

DD

SerDes—Receiver lanes configured for PCI Express are allowed to be disconnected (as would

occur when a PCI Express slot is connected but not populated). Directions for terminating the

SerDes signals is discussed in Section 20.5.1, “Guidelines for High-Speed Interface Termination.”

20.5.1 Guidelines for High-Speed Interface Termination

This section provides the guidelines for high-speed interface termination.

20.5.1.1 SerDes Interface

The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through the

DEVDISR register in software. If a SerDes port is disabled through the POR input the user cannot enable

it through the DEVDISR register in software. However, if a SerDes port is enabled through the POR input

the user can disable it through the DEVDISR register in software. Disabling a SerDes port through

software should be done on a temporary basis. Power is always required for the SerDes interface, even if

the port is disabled through either mechanism. Table 72 describes the possible enabled/disabled scenarios

for a SerDes port. The termination recommendations must be followed for each port.

Table 72. SerDes Port Enabled/Disabled Configurations

Disabled Through POR Input

Enabled Through POR Input

SerDes port is disabled (and cannot

be enabled through DEVDISR)

SerDes port is enabled

Enabled through DEVDISR

Disabled through DEVDISR

Partial termination may be required¹

(Reference Clock is required)

Complete termination required

(Reference Clock not required)

SerDes port is disabled (through

POR input)

SerDes port is disabled after software

disables port

Complete termination required

(Reference Clock not required)

Same termination requirements as when the

port is enabled through POR input²

(Reference Clock is required)

Note:

1

Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the SerDes

port mode. If the port is in ×8 PCI Express mode, no termination is required because all pins are being used. If the port

is in ×1/×2/×4 PCI Express mode, termination is required on the unused pins. If the port is in ×4 serial RapidIO mode,

termination is required on the unused pins.

If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are

required. Termination of the SerDes port should follow what is required when the port is enabled through both POR

input and DEVDISR. See Note 1 for more information.

2

If the high-speed SerDes port requires complete or partial termination, the unused pins should be

terminated as described in this section.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

119

System Design Information

The following pins must be left unconnected (floating):

•

SDn_TX[7:0]

The following pins must be connected to GND:

•

SDn_RX[7:0]

SDn_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDS1CR1[0:7]

register (offset = 0xE_0F08) and SRDS2CR1[0:7] register

(offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver

output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.

For other directions on reserved or no-connects pins see Section 17, “Signal Listings.”

20.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8640 requires weak pull-up resistors (2–10 kΩ is recommended) on all open drain type pins.

The following pins must not be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10,

LGPL1/LSDWE, TRIG_OUT/READY, and D1_MSRCID[2].

The following are factory test pins and require strong pull-up resistors (100Ω –1 kΩ) to OV

DD

LSSD_MODE, TEST_MODE[0:3].The following pins require weak pull-up resistors (2–10 kΩ) to their

specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2],

LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and

CKSTP_OUT.

The following pins should be pulled to ground with a 100-Ω resistor: SD1_IMP_CAL_TX,

SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200-Ω resistor:

SD1_IMP_CAL_RX, SD2_IMP_CAL_RX

TSECn_TX_EN signals require an external 4.7-kΩ pull down resistor to prevent PHY from seeing a valid

Transmit Enable before it is actively driven.

When the platform frequency is 400 MHz, TSEC1_TXD[1] must be pulled down at reset.

TSEC2_TXD[4] and TSEC2_TX_ER pins function as cfg_dram_type[0 or 1] at reset and MUST BE

VALID BEFORE HRESET ASSERTION when coming out of device sleep mode.

20.6.1 Special instructions for Single Core device

The mechanical drawing for the single core device does not have all the solder balls that exist on the single

core device. This includes all the balls for VDD_Core1 and SENSEV _Core1 which exist on the

DD

package for the dual core device, but not on the single core package. A solder ball is present for

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

120

Freescale Semiconductor

System Design Information

SENSEV _Core1 and needs to be connected to ground with a weak (2–10 kΩ) pull down resistor.

SS

Likewise, AV _Core1 needs to be pulled to ground as shown in Figure 64.

DD

The mechanical drawing for the single core device is located in Section 16.2, “Mechanical Dimensions of

the MPC8640 FC-CBGA.”

For other pin pull-up or pull-down recommendations of signals, please see Section 17, “Signal Listings.”

20.7 Output Buffer DC Impedance

The MPC8640 drivers are characterized over process, voltage, and temperature. For all buses, the driver

2

is a push-pull single-ended driver type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV

0

DD

or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 66). The

DD

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals

P

OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each

DD

P

N

other in value. Then, Z = (R + R ) ÷ 2.

0

P

N

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 66. Driver Impedance Measurement

Table 73 summarizes the signal impedance targets. The driver impedances are targeted at minimum V

,

DD

nominal OV , 105 °C.

DD

Table 73. Impedance Characteristics

DUART, Control,

PCI

Impedance

Configuration, Power

Management

DDR DRAM Symbol

Unit

Express

R

43 Target

25 Target

20 Target

Z₀

W

N

P

Note: Nominal supply voltages. See Table 1, T_j= 105 °C.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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121

System Design Information

20.8 Configuration Pin Muxing

The MPC8640 provides the user with power-on configuration options which can be set through the use of

external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration

pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input

receiver is disabled, the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio and e600 PLL ratio configuration pins are not equipped with these default pull-up

devices.

20.9 JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 68. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture

technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary

logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the

reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained

if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing

the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

port connects primarily through the JTAG interface of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 67 allows the COP port to independently assert HRESET or TRST,

while ensuring that the target can drive HRESET as well.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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System Design Information

The COP interface has a standard header, shown in Figure 67, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header shown in Figure 67; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 67 is common to all known emulators.

For a multi-processor non-daisy chain configuration, Figure 68, can be duplicated for each processor. The

recommended daisy chain configuration is shown in Figure 69. Please consult with your tool vendor to

determine which configuration is supported by their emulator.

20.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•

TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 68. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

•

Tie TCK to OV through a 10 kΩ resistor. This will prevent TCK from changing state and

DD

reading incorrect data into the device.

No connection is required for TDI, TMS, or TDO.

2

1

3

COP_TDO

COP_TDI

NC

4

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

NC

5

7

6

8

COP_TCK

COP_TMS

COP_SRESET

9

10

12

NC

11

KEY

13

15

COP_HRESET

No pin

GND

COP_CHKSTP_OUT

16

Figure 67. COP Connector Physical Pinout

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

123

System Design Information

OV_DD

10 kΩ

SRESET0

From Target

Board Sources

(if any)

SRESET1

HRESET¹

SRESET1

HRESET

COP_HRESET

13

11

10 kΩ

COP_SRESET

5

2

4

1

3

TRST¹

COP_TRST

4

COP_VDD_SENSE²

10 Ω

5

6

5

NC

7

8

COP_CHKSTP_OUT

9

10

12

CKSTP_OUT

15

10 kΩ

11

14 ³

10 kΩ

KEY

No pin

13

15

COP_CHKSTP_IN

COP_TMS

CKSTP_IN

TMS

8

9

1

3

16

COP_TDO

COP_TDI

COP_TCK

COP Connector

Physical Pinout

TDO

TDI

7

2

TCK

10 kΩ

NC

10

4

12

16

Notes:

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor

in order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

Figure 68. JTAG/COP Interface Connection for one MPC8640 device

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

124

Freescale Semiconductor

System Design Information

OV

DD

10kΩ

TDI

MPC8640

10kΩ

SRESET0

SRESET1

HRESET

SRESET0

From Target

Board Sources

(if any)

SRESET1

3

4

HRESET

OV

Ω

DD

10 k

4

TRST

10kΩ

5

3

10kΩ

CHKSTP_OUT

CHKSTP_IN

TMS

COP_TDI

11

13

COP_SRESET

COP_HRESET

COP_TRST

3

TCK

4

5

TDO

NC

15

8

COP_CHKSTP_OUT

COP_CHKSTP_IN

TDI

MPC8640

2

NC

SRESET0

SRESET1

HRESET

10

14

9

JTAG/COP

Header

2

4

COP_TMS

COP_TCK

4

7

TRST

12

16

CHKSTP_OUT

CHKSTP_IN

TMS

6

10

Ω

GND

1

TCK

6

COP_VDD_SENSE

TDO

COP_TDO

1

Notes:

1. Populate this with a 10-Ω resistor for short circuit/current-limiting protection.

2. KEY location; pin 14 is not physically present on the COP header.

3. Use a AND gate with sufficient drive strength to drive two inputs.

4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order

to fully control the processor as shown above.

5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

6. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

improved signal integrity.

Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

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125

Ordering Information

21 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 21.1, “Part Numbers Fully Addressed by This Document.”

21.1 Part Numbers Fully Addressed by This Document

Table 74 provides the Freescale part numbering nomenclature for the MPC8640. Note that the individual

part numbers correspond to a maximum processor core frequency. For available frequencies, contact your

local Freescale sales office. In addition to the processor frequency, the part numbering scheme also

includes an application modifier which may specify special application conditions. Each part number also

contains a revision code which refers to the die mask revision number.

Table 74. Part Numbering Nomenclature

uu

nnnn

D

w

xx

yyyy

a

z

Core

Processor

Frequency ²

(MHz)

Product

Code

Part

Identifier

Core

Count

DDR speed

(MHz)

Temp

Package¹

Product Revision Level

Revision C = 2.1

System Version Register

Value for Rev C:

Blank:

HX = High-lead

Blank =

Single Core

0°C to 105°C

HCTE FC-CBGA

0x8090_0021 MPC8640

0x8090_0121 MPC8640D

N = 533 MHz⁴

H = 500 MHz

1000, 1067,

1250

MC⁵

8640

T:

VU = RoHS lead-free

HCTE FC-CBGA⁶

D =

Dual Core

–40 °C to

105 °C

Revision E = 3.0

System Version Register

Value for Rev E:

0x8090_0030 MPC8640

0x8090_0130 MPC8640D

VJ = Lead-free HCTE

FC-CBGA⁷

Notes:

1. See Section 16, “Package,” for more information on available package types.

2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification

support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core

frequencies.

3. The P prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by Freescale SOP 3-13. These parts

have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization

from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product

changes may still occur while shipping pilot production prototypes.

4. Part Number MC8640xxx1067Nz is our low V_DD_Coren device. V_DD_Coren = 0.95 V and V_DD_PLAT = 1.05 V.

5. MC - Qualified production

6. VU part number is RoHS compliant with the permitted exception of the C4 die bumps.

7. VJ part number is entirely lead-free including the C4 die bumps.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

126

Freescale Semiconductor

Ordering Information

Table 75 shows the parts that are available for ordering and their operating conditions.

Table 75. Part Offerings and Operating Conditions

Part Offerings¹

Operating Conditions

Dual core

MC8640Dwxx1250Hz

Max CPU speed = 1250 MHz,

Max DDR = 500 MHz

Core Voltage = 1.05 volts

MC8640Dwxx1000Hz

MC8640Dwxx1067Nz

MC8640wxx1250Hz

MC8640wxx1000Hz

MC8640wxx1067Nz

Dual core

Max CPU speed = 1000 MHz,

Max DDR = 500 MHz

Core Voltage = 1.05 volts

Dual core

MAX CPU speed = 1067 MHz,

MAX DDR = 533 MHz

Core Voltage = 0.95 volts

Single core

Max CPU speed = 1250 MHz,

Max DDR = 500 MHz

Core Voltage = 1.05 volts

Single core

Max CPU speed = 1000 MHz,

Max DDR = 500 MHz

Core Voltage = 1.05 volts

Single core

Max CPU speed = 1067 MHz,

Max DDR = 533 MHz

Core Voltage = 0.95 volts

1

Note that the “w” represents the operating temperature range. The “xx”

in the part marking represents the package option. The “z” represents

the product revision level. For more information see Table 74.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

127

Document Revision History

21.2 Part Marking

Parts are marked as the example shown in Figure 70.

MC8640x

xxnnnnxx

TWLYYWW

MMMMMM

YWWLAZ

8641D

NOTE:

TWLYYWW is the test code

MMMMMM is the M00 (mask) number.

YWWLAZ is the assembly traceability code.

Figure 70. Part Marking for FC-CBGA Device

22 Document Revision History

Table 76 provides a revision history for the MPC8640D hardware specification.

Table 76. Document Revision History

Revision

Date

Substantive Change(s)

4

05/2014 • Updated Serial RapidIO equation in Section 4.4, “Platform Frequency Requirements for PCI-Express

and Serial RapidIO”

• In Table 41, “Local Bus Timing Specifications (OV_DD= 3.3 V)—PLL Enabled,” changed the value for

Local bus cycle time from 8 to 7.5 ns.

• Updated Section 19.2.4, “Temperature Diode,” by removing the ideality factor value.

• Updated Figure 70 such that the marking on the substrate is 8641D instead of 8640D.

• Added VJ package description and footnotes to Table 74., “Part Numbering Nomenclature” and

Section 16, “Package.”

3

2

07/2009 • Updated Table 74, “Part Numbering Nomenclature,” and Table 75, “Part Offerings and Operating

Conditions,” to include silicon revision 3.0 part markings.

06/2009 • Added Table 5, “MPC8640D Individual Supply Maximum Power Dissipation 1.”

• Added Note 8 to Table 49, “Differential Transmitter Output Specifications.”

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

128

Freescale Semiconductor

Document Revision History

Table 76. Document Revision History

Substantive Change(s)

Revision

Date

1

11/2008 • Removed voltage option of 1.10 V from Table 2 because it is not supported by MPC8640D or MPC8640

• Updated Table 4 and Table 6 with the new 1067/533 MHz device offering. This includes updated Power

Specifications.

• Added Section 4.4, “Platform Frequency Requirements for PCI-Express and Serial RapidIO”

• Updated Section 6, “DDR and DDR2 SDRAM” to include 533 MHz.

• Added core frequency of 1067 to Table 64, Table 65, Table 66 and Table 67

• Changed Max Memory clock frequency from 250 MHz to 266 MHz in Table 65

• Changed Max MPX/Platform clock Frequency from 500 MHz to 533 MHz in Table 66

• Changed Max Local Bus clock speed from 1 MHz to 133 MHz in Table 67

• Added MPX:Sysclk Ratio of 8:1 to Table 68

• Added Core:MPX Ratio of 3:1 to Table 69

• Updated Table 70 to include 533 MPX clock frequency

• Changed the Extended Temp range part numbering ‘w’ to be T instead of an H in Table 74

• Changed the DDR speed part numbering N to stand for 533 MHz instead of 500 MHz in Table 74

• Removed the statement “Note that core processor speed of 1500 MHz is only available for the

MPC8640D (dual core)” from Note 2 in Table 74 because MPC8640D is not offered at 1500 MHz core.

• Removed the part offering MC8640Dwxx1000NC which is replaced with MC8640Dwxx1067NC and

removed MC8640wxx1000NC replaced with MC8640wxx1067NC in Table 75

• Added Note 8 to Figure 57 and Figure 58.

0

07/2008 • Initial Release

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

129

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

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Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may vary

over time. All operating parameters, including “typicals,” must be validated for each

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license under its patent rights nor the rights of others. Freescale sells products pursuant

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freescale.com/SalesTermsandConditions.

Freescale, the Freescale logo, and PowerQUICC are trademarks of Freescale

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engineis a trademark of Freescale

Semiconductor, Inc. All other product or service names are the property of their

respective owners. The Power Architecture and Power.org word marks and the Power

and Power.org logos and related marks are trademarks and service marks licensed by

Power.org.

Document Number: MPC8640D

Rev. 4

05/2014


型号：	MC8640VU1067NE
厂家：	NXP
描述：	32-Bit Power Architecture SoC, 1067MHz, DDR1/2, AltiVec, GbE, PCI-e, SRIO, 0 to 105C, Rev 3 PC 双倍数据速率
文件：	总130页 (文件大小：1193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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