MC88915TFN100FN [NXP]
IC 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28, Clock Driver;
| 型号： | MC88915TFN100FN |
| 厂家： | 
NXP |
| 描述： | IC 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28, Clock Driver 驱动 输出元件 |
| 文件： | 总18页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MC88915T
Rev 6, 08/2004
MC88915TFN55
Low Skew CMOS PLL Clock Drivers,
MC88915TFN70
MC88915TFN100
MC88915TFN133
MC88915TFN160
3-State
55, 70, 100, 133, and 160 MHz Versions
The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to
lock its low skew outputs frequencies and phase onto an input reference clock.
It is designed to provide clock distribution for high performance PCs and
workstations. For a 3.3 V version, see the MC88LV915T data sheet.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple components
on a board. The PLL also allows the MC88915T to multiply a low frequency
input clock and distribute it locally at a higher (2X) system frequency. Multiple
88915s can lock onto a single reference clock, ideal for applications when a
central system clock must be distributed synchronously to multiple boards
(see Figure 9).
LOW SKEW CMOS
PLL CLOCK DRIVER
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between
their rising edges. The Q5 output is inverted (180° phase shift) from the “Q”
outputs. The 2X_Q output runs at twice the “Q” output frequency, while the
Q/2 runs at 1/2 the “Q” frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q fmax
specification. The wiring diagrams in Figure 7 detail the different feedback
configurations, creating specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide-by in the feed-
back path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
before its signal reaches the internal clock distribution section of the chip (see Figure 2. MC88915T Block Diagram (All Versions)). In
most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2)
allows the VCO to run in its optimal range (>20 MHz and >40 MHz for the TFN133 version).
In normal phase-locked operation the PLL_EN pi is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915
in a static “test mode.” In this mode, there is no frequency limitation on the input clock, necessary for a low frequency board test en-
vironment. The second SYNC input can be used as a test clock input to further simplify board-level testing (see APPLICATIONS IN-
FORMATION FOR ALL VERSIONS).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5, and Q/2 into a high impedance state (3-state). After the
OE/RST pin goes back high Q0–Q4, Q5, and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go
low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915 sees a
SYNC signal and full 5.0 V VCC
.
Features
•
•
Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD
specification, defining the part-to-part skew).
•
•
•
•
Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available
Input frequency range from 5 MHz – 2X_Q fmax specification (10 MHz – 2X_Q fmax for the TFN133 version)
Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL-level compatible. ±88 mA IOL/IOH specifications guarantee 50 Ω transmission line switching on the incident edge.
Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All
outputs can go into high impedance (3-state) for board test purposes.
•
•
Lock indicator (LOCK) accuracy indicates a phase-locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
26
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
OE/RST VCC Q5 GND Q4 VCC 2X_Q
28 27 26
4
3
2
1
25
24
23
22
21
20
19
Q/2
FEEDBACK
REF_SEL
SYNC[0]
5
GND
Q3
6
7
VCC
Q2
VCC(AN)
8
RC1
9
GND
LOCK
GND(AN)
SYNC[1]
10
11
12 13 14 15 16 17 18
FREQ_SEL GND Q0 VCC Q1 GND PLL_EN
Figure 1. Pinout: 28-Lead PLCC (Top View)
Table 1. Pin Summary
Pin Name
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Number
I/O
Function
1
1
Input
Input
Reference clock input
Reference clock input
1
Input
Chooses reference between SYNC[0] and SYNC[1]
Doubles VCO internal frequency (low)
Feedback input to phase detector
1
Input
1
Input
1
Input
Input for external RC network
Q(0–4)
5
Output
Output
Output
Output
Output
Input
Clock output (locked to SYNC)
Q5
1
Inverse of clock output
2x_Q
1
2 x clock output (Q) frequency (synchronous)
Clock output (Q) frequency ÷ 2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output enable/asynchronous reset (active low)
Disables phase-lock for low frequency testing
Q/2
1
LOCK
1
OE/RST
PLL_EN
VCC, GND
1
1
Input
11
Power and ground pins (note pins 8 and 10 are “analog” supply pins
for internal PLL only)
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
27
MC88915T
LOCK
FEEDBACK
SYNC (0)
VOLTAGE
CONTROLLED
OSCILLATOR
0
1
PHASE/FREQ
DETECTOR
CHARGE PUMP/LOOP
FILTER
M
U
X
SYNC (1)
REF_SEL
EXTERNAL REC NETWORK
(RC1 PIN)
0
1
2x_Q
Q0
PLL_EN
MUX
D
Q
Q
(÷1)
(÷2)
1
0
CP
M
U
X
R
R
R
R
DIVIDE
BY TWO
Q1
D
Q
Q
Q
CP
FREQ_SEL
OE/RST
D
Q2
Q3
CP
D
CP
D
Q4
Q5
Q/2
Q
Q
CP
R
R
D
CP
D
Q
CP
R
Figure 2. MC88915T Block Diagram (All Versions)
28
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
MC88915TFN55 AND MC88915TFN70
Table 2. SYNC Input Timing Requirements
Minimum
Symbol
Parameter
Maximum
Unit
TFN70
TFN55
tRISE/FALL, SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V
tCYCLE, SYNC Inputs Input Clock Period SYNC Inputs
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs
—
—
3.0
ns
ns
28.51
36.01
2002
50% ± 25%
1. These tCYCLE minimum values are valid when “Q” output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
Figure 7b.
2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
Table 3. DC Electrical Characteristics (Voltages Referenced to GND)
TA = –40°C to +85°C for 55 MHz Version; TA = 0°C to +70°C for 70 MHz Version; VCC = 5.0 V ± 5%
VCC
V
Target
Limit
Symbol
Parameter
Test Conditions
Unit
VIH
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
V
VOH
Vin = VIH or VIL
IOH = –36 mA1
4.75
5.25
4.01
4.51
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL
IOH = 36 mA1
4.75
5.25
0.44
0.44
V
Iin
Maximum Input Leakage Current
Maximum ICC/Input
VI = VCC or GND
5.25
5.25
5.25
5.25
5.25
5.25
± 1.0
2.0
µA
mA
mA
mA
mA
µA
ICCT
IOLD
IOHD
ICC
VI = VCC – 2.1 V
Minimum Dynamic Output Current
VOLD = 1.0 V Maximum
VOHD = 3.85 V Minimum
VI = VCC or GND
88
–88
1.0
Maximum Quiescent Supply Current (per Package)
Maximum 3-State Leakage Current
± 502
IOZ
VI = VIH or VIL; VO = VCC or GND
1. Maximum test duration is 2.0 ms, one output loaded at a time.
2. Specification value for IOZ is preliminary, will be finalized upon “MC” status.
Table 4. Capacitance and Power Specifications
Symbol
Parameter
Typical Values
Unit
Conditions
CIN
Input Capacitance
4.5
pF
pF
VCC = 5.0 V
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
1
Power Dissipation @ 50 MHz with 50 Ω Thevenin Termination
23 mW/Output
184 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD1
1
Power Dissipation @ 50 MHz with 50 Ω Parallel Termination to GND
57 mW/Output
456 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD2
1. PD1 nd PD2 mW/Output numbers are for a “Q” output.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
29
MC88915T
MC88915TFN55 AND MC88915TFN70 (Continued)
Table 5. Frequency Specifications (TA = –40°C to +85 °C, VCC = 5.0 V ± 5%)
Guaranteed Minimum
TFN70 TFN55
70 55
35 27.5
Symbol
Parameter
Unit
1
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
fmax
Maximum Operating Frequency (Q0–Q4, Q5 Output)
1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 Ω terminated to VCC/2.
Table 6. AC Characteristics (TA = –40°C to +85°C, VCC = 5.0 V ± 5%, Load = 50 Ω Terminated to VCC/2)
Symbol
tRISE/FALL
Parameter
Rise/Fall Time, All Outputs
(Between 0.2 VCC and 0.8 VCC
Min
Max
Unit
Condition
1.0
2.5
ns
Into a 50 Ω Load
Terminated to VCC/2
)
Outputs
1
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note2
0.5
1.6
ns
ns
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
tRISE/FALL
2X_Q Output
1
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
Into a 50 Ω Load
Terminated to VCC/2
(Q0–Q4, Q5, Q/2)
1
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
0.5 tCYCLE – 1.0 0.5 tCYCLE + 1.0
0.5 tCYCLE – 1.5 0.5 tCYCLE + 1.5
Output Pulse Width:
2X_Q @ 1.5 V
66 MHz
50 MHz
40 MHz
Must Use Termination
Specified in Note2
(2X_Q Output)
1
Output Pulse Width:
2X_Q @ VCC/2
50 – 65 MHz
40 – 49 MHz
ns
ns
Into a 50 Ω Load
Terminated to VCC/2
tPULSEWIDTH
0.5 tCYCLE – 1.02 0.5 tCYCLE + 1.02
0.5 tCYCLE – 1.5 0.5 tCYCLE + 1.5
0.5 tCYCLE – 0.5 0.5 tCYCLE + 0.5
(2X_Q Output)
66 – 70 MHz
1,3
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 MΩ from RC1 to An VCC
–1.05 –0.40
(With 1 MΩ from RC1 to An GND)
)
tPD
See Note4 and Figure 4 for
Detailed Explanation
SYNC Feedback
+1.25
—
+3.25
500
1,4
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
ps
ps
ps
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWr
(Rising)5
V
CC/2
1,4
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
—
—
500
750
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWf
(Falling)
V
CC/2
1,4
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWall
V
CC/2
5
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
3.0
3.0
10
14
14
ms
ns
ns
Also Time to LOCK
Indicator High
tLOCK
6
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPZL
6
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ
1. These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
2. tCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The tPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 µF, tLOCK minimum is with
C1 = 0.01 µF.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when “MC” status is
reached.
30
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
MC88915TFN100
Table 7. SYNC Input Timing Requirements
Symbol
Parameter
Minimum
Maximum
Unit
tRISE/FALL, SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V
tCYCLE, SYNC Inputs Input Clock Period SYNC Inputs
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs
—
3.0
ns
20.01
2002
ns
50% ± 25%
1. These tCYCLE minimum values are valid when “Q” output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
Figure 7b.
2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
Table 8. DC Electrical Characteristics (Voltages Referenced to GND) TA = –40°C to +85°C, VCC = 5.0 V ± 5%
VCC
V
Target
Limit
Symbol
Parameter
Test Conditions
Unit
VIH
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
V
VOH
Vin = VIH or VIL
IOH = –36 mA1
4.75
5.25
4.01
4.51
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL
IOH = 36 mA1
4.75
5.25
0.44
0.44
V
Iin
Maximum Input Leakage Current
Maximum ICC/Input
VI = VCC or GND
5.25
5.25
5.25
5.25
5.25
5.25
± 1.0
µA
mA
mA
mA
mA
µA
2.02
88
ICCT
IOLD
IOHD
ICC
VI = VCC –2.1 V
Minimum Dynamic Output Current3
VOLD = 1.0 V Maximum
VOHD = 3.85 V Minimum
VI = VCC or GND
–88
1.0
Maximum Quiescent Supply Current (per Package)
Maximum 3-State Leakage Current
± 504
IOZ
VI = VIH or VIL; VO = VCC or GND
1. IOL and IOH are 12 mA and –12 mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0 ms, one output loaded at a time.
4. Specification value for IOZ is preliminary, will be finalized upon “MC” status.
Table 9. Capacitance and Power Specifications
Symbol
Parameter
Typical Values
Unit
Conditions
CIN
Input Capacitance
4.5
pF
pF
VCC = 5.0 V
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
1
Power Dissipation @ 50 MHz with 50 Ω Thevenin Termination
23 mW/Output
184 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD1
1
Power Dissipation @ 50 MHz with 50 Ω Parallel Termination to GND
57 mW/Output
456 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD2
1. PD1 nd PD2 mW/Output numbers are for a “Q” output.
Table 10. Frequency Specifications (TA = –40°C to +85 °C, VCC = 5.0 V ± 5%)
Guaranteed Minimum
Symbol
Parameter
Unit
TFN100
100
1
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
fmax
50
Maximum Operating Frequency (Q0–Q4, Q5 Output)
1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 Ω terminated to VCC/2.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
31
MC88915T
MC88915TFN100 (Continued)
Table 11. AC Characteristics (TA = –40°C to +85°C, VCC = 5.0 V ± 5%, Load = 50 Ω Terminated to VCC/2)
Symbol
tRISE/FALL
Parameter
Rise/Fall Time, All Outputs
(Between 0.2 VCC and 0.8 VCC
Min
Max
Unit
Condition
1.0
2.5
ns
Into a 50 Ω Load
Terminated to VCC/2
)
Outputs
1
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note2
0.5
1.6
ns
ns
ns
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
tRISE/FALL
2X_Q Output
1
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
Into a 50 Ω Load
Terminated to VCC/2
(Q0–Q4, Q5, Q/2)
1
Output Pulse Width: 2X_Q @ 1.5 V
Must Use Termination
Specified in Note2
tPULSEWIDTH
(2X_Q Output)
1
tPULSEWIDTH
0.5 tCYCLE – 1.52 0.5 tCYCLE + 1.52
0.5 tCYCLE – 1.0 0.5 tCYCLE + 1.0
0.5 tCYCLE – 0.5 0.5 tCYCLE + 0.5
Output Pulse Width:
2X_Q @ VCC/2
40 – 49 MHz
50 – 65 MHz
Into a 50 Ω Load
Terminated to VCC/2
(2X_Q Output)
66 – 100 MHz
See Note4 and Figure 4 for
Detailed Explanation
1,3
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 MΩ from RC1 to An VCC
–1.05 –0.30
(With 1 MΩ from RC1 to An GND)
)
ns
tPD
SYNC Feedback
+1.25
—
+3.25
500
1,4
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
ps
ps
ps
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWr
(Rising)5
V
CC/2
1,4
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
—
—
500
750
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWf
(Falling)
V
CC/2
1,4
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWall
V
CC/2
5
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
3.0
3.0
10
14
14
ms
ns
ns
Also Time to LOCK
Indicator High
tLOCK
6
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPZL
6
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ
1. These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
2. tCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The tPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 µF, tLOCK minimum is with
C1 = 0.01 µF.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when “MC” status is
reached.
32
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
MC88915TFN133
Table 12. SYNC Input Timing Requirements
Symbol
Parameter
Minimum
Maximum
Unit
tRISE/FALL, SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V
tCYCLE, SYNC Inputs Input Clock Period SYNC Inputs
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs
—
3.0
ns
15.01
1002
ns
50% ± 25%
1. These tCYCLE minimum values are valid when “Q” output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
Figure 7b.
2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
Table 13. DC Electrical Characteristics (Voltages Referenced to GND) TA = –40°C to +85°C, VCC = 5.0 V ± 5%
VCC
V
Target
Limit
Symbol
Parameter
Test Conditions
Unit
VIH
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
V
VOH
Vin = VIH or VIL
IOH = –36 mA1
4.75
5.25
4.01
4.51
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL
IOH = 36 mA1
4.75
5.25
0.44
0.44
V
Iin
Maximum Input Leakage Current
Maximum ICC/Input
VI = VCC or GND
5.25
5.25
5.25
5.25
5.25
5.25
± 1.0
µA
mA
mA
mA
mA
µA
2.02
88
ICCT
IOLD
IOHD
ICC
VI = VCC –2.1 V
Minimum Dynamic Output Current3
VOLD = 1.0 V Maximum
VOHD = 3.85 V Minimum
VI = VCC or GND
–88
1.0
Maximum Quiescent Supply Current (per Package)
Maximum 3-State Leakage Current
± 504
IOZ
VI = VIH or VIL; VO = VCC or GND
1. IOL and IOH are 12 mA and –12 mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0 ms, one output loaded at a time.
4. Specification value for IOZ is preliminary, will be finalized upon “MC” status.
Table 14. Capacitance and Power Specifications
Symbol
Parameter
Typical Values
Unit
Conditions
CIN
Input Capacitance
4.5
pF
pF
VCC = 5.0 V
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
1
Power Dissipation @ 50 MHz with 50 Ω Thevenin Termination
23 mW/Output
184 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD1
1
Power Dissipation @ 50 MHz with 50 Ω Parallel Termination to GND
57 mW/Output
456 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD2
1. PD1 nd PD2 mW/Output numbers are for a “Q” output.
Table 15. Frequency Specifications (TA = –40°C to +85 °C, VCC = 5.0 V ± 5%)
Guaranteed Minimum
Symbol
Parameter
Unit
TFN133
133
1
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
fmax
66
Maximum Operating Frequency (Q0–Q4, Q5 Output)
1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 Ω terminated to VCC/2.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
33
MC88915T
MC88915TFN133 (Continued)
Table 16. AC Characteristics (TA = –40°C to +85°C, VCC = 5.0 V ± 5%, Load = 50 Ω Terminated to VCC/2)
Symbol
tRISE/FALL
Parameter
Rise/Fall Time, All Outputs
(Between 0.2 VCC and 0.8 VCC
Min
Max
Unit
Condition
1.0
2.5
ns
Into a 50 Ω Load
Terminated to VCC/2
)
Outputs
1
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note2
0.5
1.6
ns
ns
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
tRISE/FALL
2X_Q Output
1
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
Into a 50 Ω Load
Terminated to VCC/2
(Q0–Q4, Q5, Q/2)
1
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
0.5 tCYCLE – 0.9 0.5 tCYCLE + 0.9
Output Pulse Width:
2X_Q @ 1.5 V
66 – 133 MHz
40 – 65 MHz
Must Use Termination
Specified in Note2
(2X_Q Output)
1
Output Pulse Width:
2X_Q @ VCC/2
66 – 133 MHz
40 – 65 MHz
ns
ns
Into a 50 Ω Load
Terminated to VCC/2
tPULSEWIDTH
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
0.5 tCYCLE – 0.9 0.5 tCYCLE + 0.9
(2X_Q Output)
1,3
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 MΩ from RC1 to An VCC
–1.05 –0.25
(With 1 MΩ from RC1 to An GND)
)
tPD
See Note4 and Figure 4 for
Detailed Explanation
SYNC Feedback
+1.25
—
+3.25
500
1,4
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
ps
ps
ps
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWr
(Rising)5
V
CC/2
1,4
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
—
—
500
750
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWf
(Falling)
V
CC/2
1,4
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWall
V
CC/2
5
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
3.0
3.0
10
14
14
ms
ns
ns
Also Time to LOCK
Indicator High
tLOCK
6
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPZL
6
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ
1. These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
2. tCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The tPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 µF, tLOCK minimum is with
C1 = 0.01 µF.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when “MC” status is
reached.
34
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
MC88915TFN160
Table 17. SYNC Input Timing Requirements
Symbol
Parameter
Minimum
Maximum
Unit
tRISE/FALL, SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V
tCYCLE, SYNC Inputs Input Clock Period SYNC Inputs
Duty Cycle SYNC Inputs Input Duty Cycle SYNC Inputs
—
3.0
ns
12.51
1002
ns
50% ± 25%
1. These tCYCLE minimum values are valid when “Q” output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
Figure 7b.
2. Information in Table 22 and in Note 3 of the AC specification notes describe this specification with its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
Table 18. DC Electrical Characteristics (Voltages Referenced to GND) TA = 0°C to +70°C, VCC = 5.0 V ± 5%
VCC
V
Target
Limit
Symbol
Parameter
Test Conditions
Unit
VIH
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC –0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
V
VOH
Vin = VIH or VIL
IOH = –36 mA1
4.75
5.25
4.01
4.51
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL
IOH = 36 mA1
4.75
5.25
0.44
0.44
V
Iin
Maximum Input Leakage Current
Maximum ICC/Input
VI = VCC or GND
5.25
5.25
5.25
5.25
5.25
5.25
± 1.0
µA
mA
mA
mA
mA
µA
2.02
88
ICCT
IOLD
IOHD
ICC
VI = VCC –2.1 V
Minimum Dynamic Output Current3
VOLD = 1.0 V Maximum
VOHD = 3.85 V Minimum
VI = VCC or GND
–88
1.0
Maximum Quiescent Supply Current (per Package)
Maximum 3-State Leakage Current
± 504
IOZ
VI = VIH or VIL; VO = VCC or GND
1. IOL and IOH are 12 mA and –12 mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0 ms, one output loaded at a time.
4. Specification value for IOZ is preliminary, will be finalized upon “MC” status.
Table 19. Capacitance and Power Specifications
Symbol
Parameter
Typical Values
Unit
Conditions
CIN
Input Capacitance
4.5
pF
pF
VCC = 5.0 V
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
1
Power Dissipation @ 50 MHz with 50 Ω Thevenin Termination
15 mW/Output
120 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD1
1
Power Dissipation @ 50 MHz with 50 Ω Parallel Termination to GND
57 mW/Output
456 mW/Device
mW
VCC = 5.0 V
T = 25°C
PD2
1. PD1 nd PD2 mW/Output numbers are for a “Q” output.
Table 20. Frequency Specifications (TA = 0°C to +70°C, VCC = 5.0 V ± 5%)
Guaranteed Minimum
Symbol
Parameter
Unit
TFN160
160
1
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
fmax
80
Maximum Operating Frequency (Q0–Q4, Q5 Output)
1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 Ω terminated to VCC/2.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
35
MC88915T
MC88915TFN160 (Continued)
Table 21. AC Characteristics (TA = 0°C to +70°C, VCC = 5.0 V ± 5%, Load = 50 Ω Terminated to VCC/2)
Symbol
tRISE/FALL
Parameter
Rise/Fall Time, All Outputs
Min
Max
Unit
Condition
1.0
2.5
ns
Into a 50 Ω Load
(Between 0.2 VCC and 0.8 VCC
)
Terminated to VCC/2
Outputs
tRISE/FALL
Rise/Fall Time
0.5
1.6
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
2X_Q Output
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
tPULSEWIDTH
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
ns
ns
Into a 50 Ω Load
Terminated to VCC/2
(Q0–Q4, Q5, Q/2)
tPULSEWIDTH
Output Pulse Width:
2X_Q @ 1.5 V
80 MHz 0.5 tCYCLE – 0.7 0.5 tCYCLE + 0.7
100 MHz 0.5 tCYCLE – 0.5 0.5 tCYCLE + 0.5
133 MHz 0.5 tCYCLE – 0.5 0.5 tCYCLE + 0.5
(2X_Q Output)
160 MHz
TBD
TBD
See Note2 and Figure 4 for
Detailed Explanation
1
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
ns
tPD
(With 1 MΩ from RC1 to An VCC
)
SYNC Feedback
133 MHz
160 MHz
–1.05
–0.9
–0.25
–0.10
tCYCLE
Cycle-to-Cycle Variation
133 MHz tCYCLE – 300 ps tCYCLE + 300 ps
tCYCLE – 300 ps tCYCLE + 300 ps
(2x_Q Output)
160 MHz
3
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
—
—
—
500
500
750
ps
ps
ps
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWr
(Rising)4
V
CC/2
3
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWf
(Falling)
V
CC/2
3
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
All Outputs into a Matched
50 Ω Load Terminated to
tSKEWall
V
CC/2
4
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
3.0
3.0
10
14
14
ms
ns
ns
Also Time to LOCK
Indicator High
tLOCK
5
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPZL
5
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 µF, tLOCK minimum is with
C1 = 0.01 µF.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when “MC” status is
reached.
36
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
APPLICATIONS INFORMATION FOR ALL VERSIONS
2. These two specs (tRISE/FALL and tPULSE Width 2X_Q
General AC Specification Notes
output) guarantee the MC88915T meets the 40 MHz and
33 MHz MC68040 P-Clock input specification (at 80 MHz
and 66 MHz, respectively). For these two specs to be
guaranteed by Freescale Semiconductor, the termination
scheme shown below in Figure 3 must be used.
1. Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase-locked
operation. It is not possible to have the part in phase-lock
on automated test equipment (ATE). Statistical
characterization techniques were used to guarantee those
specifications which cannot be measured on the ATE.
MC88915TFN55, 70 and 100 units were fabricated with
key transistor properties intentionally varied to create a
14-cell designed experimental matrix. IC performance was
characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area, to set
performance limits of ATE testable specifications within
those to be guaranteed by statistical characterization. In
this way, all units passing the ATE test will meet or exceed
the non-tested specifications limits.
3. The wiring diagrams and explanations in Figure 7
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 22 below summarizes the allowable SYNC
frequency range for each possible configuration.
ZO (CLOCK TRACE)
RS
88915
68040
2X_Q OUTPUT
P-CLOCK INPUT
RS = ZO – 7 Ω
RP
RP = 1.5 ZO
Figure 3. MC68040 P-Clock Input Termination Scheme
Table 22. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHz)
Corresponding VCO
Frequency Range
HIGH
HIGH
HIGH
HIGH
Q/2
Any “Q” (Q0–Q4)
Q5
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
0°
0°
180°
0°
2X_Q
LOW
LOW
LOW
LOW
Q/2
Any “Q” (Q0–Q4)
Q5
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
0°
0°
180°
0°
2X_Q
4. A 1 MΩ resistor tied to either Analog VCC or Analog GND,
14 lots described in Note 1 while the part was in
phase-locked operation. The actual measurements were
made with a 10 MHz SYNC input (1.0 ns edge rate from
0.8 V – 2.0 V) with the Q/2 output fed back. The phase
measurements were made at 1.5 V. The Q/2 output was
terminated at the FEEDBACK input with 100 Ω to VCC and
depicted in Figure 4, is required to ensure no jitter is
present on the MC88915T outputs. This technique causes
a phase offset between the SYNC input and the output
connected to the FEEDBACK input, measured at the input
pins. The tPD spec describes how this offset varies with
100 Ω to ground.
process, temperature, and voltage. The specs were
determined by measuring the phase relationship for the
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
37
MC88915T
RC1
EXTERNAL LOOP FILTER
ANALOG VCC
1 MΩ
RC1
330 Ω
0.1 µF
R2
REFERENCE
RESISTOR
R2
330 Ω
C1
1 MΩ
REFERENCE
RESISTOR
0.1 µF
C1
ANALOG GND
ANALOG GND
With the 1.0 MΩ resistor tied in this fashion, the tPD
specification measured at the input pins is:
With the 1.0 MΩ resistor tied in this fashion, the tPD
specification measured at the input pins is:
tPD = 2.25 ns ± 1.0 ns
tPD = –0.775 ns ± 0.275 ns
3.0 V
3.0 V
SYNC INPUT
SYNC INPUT
–0.775 ns OFFSET
2.25 ns OFFSET
5.0 V
5.0 V
FEEDBACK OUTPUT
FEEDBACK OUTPUT
Figure 4. Depiction of the Fixed SYNC to Feedback Offset (tPD
)
Which is Present When a 1 mΩ Resistor is Tied to VCC or Ground
5. The tSKEWr specification guarantees the rising edges of
clock with equal delay of input signal to each part. This
skew value is valid at the 88915 output pins only (equally
loaded), it does not include PCB trace delays due to vary-
ing loads.
outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within
a 500 ps window within one part. However, if the relative
position of each output within this window is not specified,
the 500 ps window must be added to each side of the tPD
With a 1.0 MΩ resistor tied to analog VCC as shown in Note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05 ns and
–0.5 ns. To calculate the skew of any given output between
two or more parts, the absolute value of the distribution of
the output given in Table 23 must be subtracted and added
to the lower and upper tPD spec limits respectively. For out-
put Q2, [276 – (–44)] = 320 ps is the absolute value of the
distribution. Therefore, [–1.05 ns – 0.32 ns] = –1.37 ns is
the lower tPD limit, and [–0.5 ns + 0.32 ns] = –0.18 ns is the
upper limit. Therefore, the worst case skew of output Q2
between any number of parts is |(–1.37) – (–0.18)| =
1.19 ns. Q2 has the worst case skew distribution of any
output, so 1.2 ns is the absolute worst case output-to-out-
put skew between multiple parts.
specification limits to calculate the total part-to-part skew.
For this reason, the absolute distribution of these outputs
are provided in Table 23. When taking the skew data, Q0
was used as a reference, so all measurements are relative
to this output. The information in Table 23 is derived from
measurements taken from the 14 process lots described
in Note 1, over the temperature and voltage range.
Table 23. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q
Within the 500 ps tSKEWr Spec Window
Output
Q0
– (ps)
0
+ (ps)
0
Q1
–72
–44
–40
–274
–16
–633
40
7. Note 4 explains the tPD specification was measured and is
Q2
276
255
–34
250
–35
guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10 MHz. The fixed offset (tPD) as described
Q3
Q4
Q/2
2X_Q
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 5 demonstrate this dependence.
6. Calculation of Total Output-to-Skew Between Multiple
Parts (Part-to-Part Skew)
The data presented in Figure 5 is from devices represent-
ing process extremes, and the measurements were also
taken at the voltage extremes (VCC = 5.25 V and 4.75 V).
Therefore, the data in Figure 5 is a realistic representation
By combining the tPD specification and the information in
Note 5, the worst case output-to-output skew between mul-
tiple 88915s connected in parallel can be calculated. This
calculation assumes all parts have a common SYNC input
of the variation of tPD
.
38
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
–0.50
–0.75
–0.5
–1.0
–1.5
–1.00
–1.25
–1.50
–2.0
2.5
5.0
7.5
10.0
12.5
15.0 17.5
2.5
7.5
12.5
17.5
27.5
25.0
SYNC INPUT FREQUENCY (MHz)
5.0
10.0
15.0
20.0
22.5
SYNC INPUT FREQUENCY (MHz)
Figure 5a
t
PD versus Frequency Variation for Q/2 Output Fed
Figure 5b
Back, Including Process and Voltage Variation @ 25°C
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(with 1.0 MΩ Resistor Tied to Analog VCC
)
(with 1.0 MΩ Resistor Tied to Analog VCC
)
3.5
3.0
2.5
3.5
3.0
2.5
2.0
1.5
2.0
1.5
1.0
0.5
1.0
0.5
0
5
10
15
20
25
2.5
5.0
7.5
10.0
12.5
15.0 17.5
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
Figure 5c
Figure 5d
tPD versus Frequency Variation for Q/2 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(with 1.0 MΩ Resistor Tied to Analog GND)
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(with 1.0 MΩ Resistor Tied to Analog GND)
Figure 5. Graphs
8. The lock indicator pin (LOCK) will reliably indicate a
phase-locked condition at SYNC input frequencies down
to 10 MHz. At frequencies below 10 MHz, the frequency of
correction pulses going into the phase detector form the
SYNC and FEEDBACK pins may not be sufficient to allow
the lock indicator circuitry to accurately predict a
provide stable phase-locked operation down to the
appropriate minimum input frequency given in Table 22,
even though the LOCK pin may be LOW at frequencies
below 10 MHz. The exact minimum frequency where the
lock indicator functionality can be guaranteed will be
available when the MC88915T reaches “MC” status.
phase-locked condition. The MC88915T is guaranteed to
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
39
MC88915T
SYNC INPUT
(SYNC[1] OR
SYNC[0])
tCYCLE SYNC INPUT
tPD
FEEDBACK
INPUT
Q/2 OUTPUT
tSKEWr
tSKEWALL
tSKEWr
tSKEWf
tSKEWf
Q0–Q4
OUTPUTS
tCYCLE "Q" OUTPUTS
Q5 OUTPUT
2X_Q OUTPUT
Figure 6. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook-up configuration of Figure 7a)
TIMING NOTES:
1. The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
“windows,” not as a ± deviation around a center point.
3. If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency would match the
SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC
frequency.
40
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
100 MHz SIGNAL
25 MHz FEEDBACK SIGNAL
HIGH
1:2 Input to “Q” Output Frequency Relationship
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
RST
FEEDBACK
Q5
Q4 2X_Q
Q/2
LOW
25 MHz INPUT
REF_SEL
SYNC[0]
MC88915T
CRYSTAL
OSCILLATOR
Q3
50 MHz
“Q” CLOCK
OUTPUTS
ANALOG VCC
RC1
Allowable Input Frequency Range:
5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
EXTERNAL
LOOP
FILTER
Q2
ANALOG GND
FQ_SEL Q0
HIGH
Q1 PLL_EN
HIGH
NOTE: If the OE/RST input is active, a pullup or pull-down
resistor isn’t necessary at the FEEDBACK pin so it won’t
when the fed back output goes into 3-state.
Figure 7a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback
50 MHz FEEDBACK SIGNAL
HIGH
100 MHz SIGNAL
1:1 Input to “Q” Output Frequency Relationship
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
equal the SYNC frequency. The Q/2 output will
always rn at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
RST
Q5
Q4 2X_Q
25 MHz
SIGNAL
Q/2
FEEDBACK
LOW
50 MHz INPUT
REF_SEL
SYNC[0]
MC88915T
CRYSTAL
OSCILLATOR
Q3
ANALOG VCC
RC1
EXTERNAL
LOOP
FILTER
Allowable Input Frequency Range:
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
Q2
ANALOG GND
50 MHz
“Q” CLOCK
OUTPUTS
FQ_SEL Q0
HIGH
Q1 PLL_EN
HIGH
Figure 7b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback
100 MHz FEEDBACK SIGNAL
HIGH
2:1 Input to “Q” Output Frequency Relationship
In this application, the 2X_Q output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/3 the 2X_Q
frequency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
RST
FEEDBACK
Q5
Q4 2X_Q
Q/2
25 MHz
SIGNAL
LOW
100 MHz INPUT
REF_SEL
SYNC[0]
MC88915T
CRYSTAL
OSCILLATOR
Q3
Q2
50 MHz
“Q” CLOCK
OUTPUTS
ANALOG VCC
RC1
EXTERNAL
LOOP
FILTER
Allowable Input Frequency Range:
20 MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
ANALOG GND
FQ_SEL Q0
HIGH
Q1 PLL_EN
HIGH
Figure 7c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feedback
Figure 7. Wiring Diagrams
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
41
MC88915T
BOARD VCC
47 Ω
ANALOG VCC
ANALOG LOOP FILTER/VCO
8
9
1 MΩ
330 Ω
SECTION OF THE MC88915T
28-PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
RC1
0.1 µF HIGH
FREQUENCY
BYPASS
10 µF LOW
FREQUENCY
BYPASS
0.1 µF (LOOP
FILTER CAP)
ANALOG GND
10
47 Ω
NOTE: A separate analog power supply is not necessary and
should not be used. Following these prescribed guidelines
is all that is necessary to use the MC88915T in a normal
digital environment.
BOARD GND
Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 8 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter-free operation:
scheme shown in Figure 8 is to give the 88915T
additional protection from the power supply and
ground plane transients potentially occurring in a high
frequency, high speed digital system.
a. All loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces
can cause undesirable voltage transients at the RC1
pin.
c. There are no special requirements set forth for the
loop filter resistors (1.0 MΩ and 330 Ω). The loop filter
capacitor (0.1 µF) can be a ceramic chip capacitor,
the same as a standard bypass capacitor.
d. The 1.0 M reference resistor injects current into the
internal charge pump of the PLL, causing a fixed
offset between the outputs and the SYNC input. This
also prevents excessive jitter caused by inherent PLL
dead-band. If the VCO (2X_Q output) is running
above 40 MHz, the 1.0 MΩ resistor provides the
correct amount of current injection into the charge
pump
b. The 47 Ω resistors, the 10 µF low frequency bypass
capacitor, and the 0.1 µF high frequency bypass
capacitor form a wide bandwidth filter minimizing the
88915T’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This
filter will typically ensure a 100 mV step deviation on
the digital VCC supply, causing no more than a 100 ps
(2–3 µA). For the TFN55, 70 or 100, if the VCO is
running below 40 MHz, a 1.5 MΩ reference resistor
should be used (instead of 1 MΩ).
phase deviation o the 88915T outputs. A 250 mV step
deviation on VCC using the recommended filter
values should cause no more than 250 ps phase
deviation; if a 25 µF bypass capacitor is used (instead
of 10 µF) a 250 mV VCC step should cause no more
2. In addition to the bypass capacitors used in the analog
filter of Figure 8, there should be a 0.1 µF bypass
capacitor between each of the other (digital) four VCC pins
than a 100 ps phase deviation.
and the board ground plane. This will reduce output
switching noise caused by the 88915T outputs. In addition
to reducing potential for noise in the “analog” section of
the chip. These bypass capacitors should also be tied as
close to the 88915T package as possible.
If good bypass techniques are used on a board
design near components potentially causing digital
VCC and ground noise, the above described VCC step
deviations should not occur at the 88915T’s digital
VCC supply. The purpose of the bypass filtering
42
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915T
CPU
CARD
CMMU CMMU
CPU CMMU
CMMU CMMU
MC88915T
PLL
2f
CLOCK
@ f
SYSTEM
CLOCK
SOURCE
CPU
CARD
CMMU CMMU
CPU CMMU
CMMU CMMU
MC88915T
PLL
2f
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
AT POINT OF USE
MC88915T
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board-to-Board Skew
MC88915T System Level Testing Functionality
With the PLL_EN pin low the selected SNC signal is gated
directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly
driven by the SYNC input (per the block diagram). This mode
can also be used for low frequency board testing.
Three-state functionality was added to the 100 MHz version
of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the
high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain in the low state
after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output is the inverse of the SYNC signal in this mode. If the
3-state functionality is used, a pull-up or pull-down resistor must
be tied to the FEEDBACK input pin to prevent it from floating
when the fed back output goes into high impedance.
NOTE: If the outputs are put into 3-state during normal PLL
operation, the loop will be broken and phase-lock will
be lost. It will take a maximum of 10 ms (tLOCK spec)
to regain phase-lock after the OE/RST pin goes back
high.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
43
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