MC9328MX1VM15_技术文档

Document Number: MC9328MX1

Rev. 7, 12/2006

Freescale Semiconductor

Data Sheet: Technical Data

MC9328MX1

Package Information

Plastic Package

Case 1304B-01

MC9328MX1

(MAPBGA–225)

Ordering Information

See Table 1 on page 3

Contents

1 Introduction

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Signals and Connections . . . . . . . . . . . . . . . 4

3 Electrical Characteristics . . . . . . . . . . . . . . 22

The i.MX Family of applications processors provides a

leap in performance with an ARM9™ microprocessor

core and highly integrated system functions. The i.MX

family specifically addresses the requirements of the

personal, portable product market by providing

intelligent integrated peripherals, an advanced processor

core, and power management capabilities.

4 Functional Description and Application

Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Pin-Out and Package Information . . . . . . . . 96

6 Product Documentation . . . . . . . . . . . . . . . . 98

Contact Information . . . . . . . . . . . . . . . Last Page

The MC9328MX1 (i.MX1) processor features the

advanced and power-efficient ARM920T™ core that

operates at speeds up to 200 MHz. Integrated modules,

which include a USB device, an LCD controller, and an

MMC/SD host controller, support a suite of peripherals

to enhance portable products seeking to provide a rich

multimedia experience. It is packaged in a 256-contact

Mold Array Process-Ball Grid Array (MAPBGA).

Figure 1 shows the functional block diagram of the

i.MX1 processor.

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its

products.

Introduction

Standard

System I/O

System Control

Power

Control

CGM

(DPLLx2)

JTAG/ICE

Bootstrap

GPIO

PWM

Connectivity

MC9328MX1

CPU Complex

ARM9TDMI™

MMC/SD

Timer 1 & 2

RTC

Memory Stick®

Host Controller

SPI 1 and

SPI 2

Watchdog

UART 1

I Cache

D Cache

Multimedia

UART 2 & 3

Multimedia

Accelerator

2

Interrupt

Controller

SSI/I S 1 & 2

AIPI 1

AIPI 2

VMMU

DMAC

Video Port

2

I C

Bus

Control

USB Device

Human Interface

(11 Chnl)

Analog Signal

Processor

SmartCard I/F

EIM &

SDRAMC

eSRAM

(128K)

Bluetooth

Accelerator

LCD Controller

Figure 1. i.MX1 Functional Block Diagram

1.1

Features

To support a wide variety of applications, the processor offers a robust array of features, including the following:

•

ARM920T™ Microprocessor Core

AHB to IP Bus Interfaces (AIPIs)

External Interface Module (EIM)

SDRAM Controller (SDRAMC)

DPLL Clock and Power Control Module

Three Universal Asynchronous Receiver/Transmitters (UART 1, UART 2, and UART3)

Two Serial Peripheral Interfaces (SPI1 and SPI2)

Two General-Purpose 32-bit Counters/Timers

Watchdog Timer

Real-Time Clock/Sampling Timer (RTC)

LCD Controller (LCDC)

Pulse-Width Modulation (PWM) Module

Universal Serial Bus (USB) Device

Multimedia Card and Secure Digital (MMC/SD) Host Controller Module

Memory Stick® Host Controller (MSHC)

Direct Memory Access Controller (DMAC)

2

Two Synchronous Serial Interfaces and an Inter-IC Sound (SSI1 and SSI2/I S) Module

2

Inter-IC (I C) Bus Module

Video Port

MC9328MX1 Technical Data, Rev. 7

2

Freescale Semiconductor

Introduction

•

General-Purpose I/O (GPIO) Ports

Bootstrap Mode

Analog Signal Processing (ASP) Module

Bluetooth™ Accelerator (BTA)

Multimedia Accelerator (MMA)

Power Management Features

Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O

256-pin MAPBGA Package

1.2

Target Applications

The i.MX1 processor is targeted for advanced information appliances, smart phones, Web browsers, based

on the popular Palm OS platform, and messaging applications such as wireless cellular products, including the

Accompli^TM008 GSM/GPRS interactive communicator.

1.3

Ordering Information

Table 1 provides ordering information.

Table 1. Ordering Information

Package Type

Frequency

Temperature

Solderball Type

Order Number

256-lead MAPBGA

200 MHz

0°C to 70°C

-30°C to 70°C

0°C to 70°C

Pb-free

MC9328MX1VM20(R2)

MC9328MX1DVM20(R2)

MC9328MX1VM15(R2)

MC9328MX1DVM15(R2)

MC9328MX1CVM15(R2)

150 MHz

-30°C to 70°C

-40°C to 85°C

1.4

Conventions

This document uses the following conventions:

•

OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.

Logic level one is a voltage that corresponds to Boolean true (1) state.

Logic level zero is a voltage that corresponds to Boolean false (0) state.

To set a bit or bits means to establish logic level one.

To clear a bit or bits means to establish logic level zero.

A signal is an electronic construct whose state conveys or changes in state convey information.

A pin is an external physical connection. The same pin can be used to connect a number of signals.

Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

3

Signals and Connections

•

Negated means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level one to logic level zero.

•

LSB means least significant bit or bits, and MSB means most significant bit or bits. References to

low and high bytes or words are spelled out.

Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x

are hexadecimal.

2 Signals and Connections

Table 2 identifies and describes the i.MX1 processor signals that are assigned to package pins. The signals

are grouped by the internal module that they are connected to.

Table 2. i.MX1 Signal Descriptions

Signal Name

Function/Notes

External Bus/Chip-Select (EIM)

A[24:0]

Address bus signals

Data bus signals

D[31:0]

EB0

MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].

Byte Strobe—Active low external enable byte signal that controls D [23:16].

Byte Strobe—Active low external enable byte signal that controls D [15:8].

LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].

Memory Output Enable—Active low output enables external data bus.

EB1

EB2

EB3

OE

CS [5:0]

Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the

Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.

ECB

LBA

Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an

on-going burst sequence and initiate a new (long first access) burst sequence.

Active low signal sent by a flash device causing the external burst device to latch the starting burst

address.

BCLK (burst clock)

RW

Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input

signal by external DRAM.

DTACK

DTACK signal—The external input data acknowledge signal. When using the external DTACK signal

as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not

terminated by the external DTACK signal after 1022 clock counts have elapsed.

Bootstrap

BOOT [3:0]

SDBA [4:0]

System Boot Mode Select—The operational system boot mode of the i.MX1 processor upon system

reset is determined by the settings of these pins.

SDRAM Controller

SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals

are logically equivalent to core address p_addr [25:21] in SDRAM cycles.

MC9328MX1 Technical Data, Rev. 7

4

Freescale Semiconductor

Signals and Connections

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

Signal Name

SDIBA [3:0]

SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These

signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.

MA [11:10]

MA [9:0]

SDRAM address signals

SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on

SDRAM cycles.

DQM [3:0]

CSD0

SDRAM data enable

SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable

by programming the system control register.

CSD1

SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by

programming the system control register. By default, CSD1 is selected, so it can be used as boot

chip-select by properly configuring BOOT [3:0] input pins.

RAS

SDRAM Row Address Select signal

SDRAM Column Address Select signal

SDRAM Write Enable signal

SDRAM Clock Enable 0

SDRAM Clock Enable 1

SDRAM Clock

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

RESET_SF

Not Used

Clocks and Resets

EXTAL16M

Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut

down.

XTAL16M

EXTAL32K

XTAL32K

CLKO

Crystal output

32 kHz crystal input

32 kHz crystal output

Clock Out signal selected from internal clock signals.

RESET_IN

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

RESET_OUT

POR

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the

following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

TRST

TDO

TDI

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

Test Clock to synchronize test logic and control register access through the JTAG port.

TCK

TMS

Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of

TCK.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

5

Signals and Connections

Signal Name

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

DMA

DMA_REQ

DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.

BIG_ENDIAN

Big Endian—Input signal that determines the configuration of the external chip-select space. If it is

driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven

logic-low at reset, the external chip-select space will be configured to little endian. This input must not

change state after power-on reset negates or during chip operation.

ETM

ETMTRACESYNC

ETMTRACECLK

ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM

mode.

ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

CMOS Sensor Interface

CSI_D [7:0]

CSI_MCLK

CSI_VSYNC

CSI_HSYNC

CSI_PIXCLK

Sensor port data

Sensor port master clock

Sensor port vertical sync

Sensor port horizontal sync

Sensor port data latch clock

LCD Controller

LD [15:0]

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

FLM/VSYNC

Frame Sync or Vsync—This signal also serves as the clock signal output for the gate

driver (dedicated signal SPS for Sharp panel HR-TFT).

LP/HSYNC

LSCLK

Line pulse or H sync

Shift clock

ACD/OE

CONTRAST

SPL_SPR

PS

Alternate crystal direction/output enable.

This signal is used to control the LCD bias voltage as contrast control.

Program horizontal scan direction (Sharp panel dedicated signal).

Control signal output for source driver (Sharp panel dedicated signal).

CLS

Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated

signal).

REV

Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SIM

SIM_CLK

SIM_RST

SIM_RX

SIM Clock

SIM Reset

Receive Data

MC9328MX1 Technical Data, Rev. 7

6

Freescale Semiconductor

Signals and Connections

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

Signal Name

SIM_TX

Transmit Data

SIM_PD

Presence Detect Schmitt trigger input

SIM Vdd Enable

SIM_SVEN

SPI 1 and SPI 2

SPI1_MOSI

SPI1_MISO

SPI1_SS

Master Out/Slave In

Slave In/Master Out

Slave Select (Selectable polarity)

Serial Clock

SPI1_SCLK

SPI1_SPI_RDY

SPI2_TXD

Serial Data Ready

SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary or

alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in

the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin.

SPI2_RXD

SPI2_SS

SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or

alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in

the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin.

SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative

signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the

MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin.

SPI2_SCLK

SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative

signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the

MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin.

General Purpose Timers

TIN

Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers

simultaneously.

TMR2OUT

Timer 2 Output

USB Device

USBD_VMO

USBD_VPO

USBD_VM

USB Minus Output

USB Plus Output

USB Minus Input

USB Plus Input

USBD_VP

USBD_SUSPND

USBD_RCV

USBD_ROE

USBD_AFE

USB Suspend Output

USB Receive Data

USB OE

USB Analog Front End Enable

Secure Digital Interface

SD_CMD

SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up

enable register, a 4.7K–69K external pull up resistor must be added.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

7

Signals and Connections

Signal Name

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

SD_CLK

MMC Output Clock

SD_DAT [3:0]

Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable

register, a 50K–69K external pull up resistor must be added.

Memory Stick Interface

MS_BS

Memory Stick Bus State (Output)—Serial bus control signal

Memory Stick Serial Data (Input/Output)

MS_SDIO

MS_SCLKO

MS_SCLKI

Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider

Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test

purposes, not for use in application mode.

MS_PI0

MS_PI1

General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect

General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect

UARTs – IrDA/Auto-Bauding

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

UART2_DSR

UART2_RI

Receive Data

Transmit Data

Request to Send

Clear to Send

Receive Data

Transmit Data

Request to Send

Clear to Send

Data Set Ready

Ring Indicator

UART2_DCD

UART2_DTR

UART3_RXD

UART3_TXD

UART3_RTS

UART3_CTS

UART3_DSR

UART3_RI

Data Carrier Detect

Data Terminal Ready

Receive Data

Transmit Data

Request to Send

Clear to Send

Data Set Ready

Ring Indicator

UART3_DCD

UART3_DTR

Data Carrier Detect

Data Terminal Ready

Serial Audio Port – SSI (configurable to I²S protocol)

SSI_TXDAT

SSI_RXDAT

Transmit Data

Receive Data

MC9328MX1 Technical Data, Rev. 7

8

Freescale Semiconductor

Signals and Connections

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

Signal Name

SSI_TXCLK

Transmit Serial Clock

SSI_RXCLK

SSI_TXFS

Receive Serial Clock

Transmit Frame Sync

Receive Frame Sync

TxD

SSI_RXFS

SSI2_TXDAT

SSI2_RXDAT

SSI2_TXCLK

SSI2_RXCLK

SSI2_TXFS

SSI2_RXFS

RxD

Transmit Serial Clock

Receive Serial Clock

Transmit Frame Sync

Receive Frame Sync

I²C

I2C_SCL

I2C_SDA

I²C Clock

I²C Data

PWM

ASP

PWMO

PWM Output

UIN

Positive U analog input (for low voltage, temperature measurement)

Negative U analog input (for low voltage, temperature measurement)

Positive pen-X analog input

UIP

PX1

PY1

PX2

PY2

R1A

R1B

R2A

R2B

RVP

RVM

AVDD

AGND

Positive pen-Y analog input

Negative pen-X analog input

Negative pen-Y analog input

Positive resistance input (a)

Positive resistance input (b)

Negative resistance input (a)

Negative resistance input (b)

Positive reference for pen ADC

Negative reference for pen ADC

Analog power supply

Analog ground

BlueTooth

BT1

BT2

BT3

I/O clock signal

Output

Input

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

9

Signals and Connections

Signal Name

Table 2. i.MX1 Signal Descriptions (Continued)

Function/Notes

BT4

Input

BT5

Output

BT6

BT7

BT8

BT9

BT10

BT11

BT12

BT13

BTRF VDD

BTRF GND

Power supply from external BT RFIC

Ground from external BT RFIC

Test Function

TRISTATE

Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input

with a 1 k ohm resistor to ground. (TRI-STATE^®is a registered trademark of National Semiconductor.)

Digital Supply Pins

NVDD

NVSS

Digital Supply for the I/O pins

Digital Ground for the I/O pins

Supply Pins – Analog Modules

Supply for analog blocks

AVDD

Internal Power Supply

QVDD

QVSS

Power supply pins for silicon internal circuitry

Ground pins for silicon internal circuitry

2.1

I/O Pads Power Supply and Signal Multiplexing Scheme

This section describes detailed information about both the power supply for each I/O pin and its function

multiplexing scheme. The user can reference information provided in Table 6 on page 23 to configure the

power supply scheme for each device in the system (memory and external peripherals). The function

multiplexing information also shown in Table 6 allows the user to select the function of each pin by

configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.

MC9328MX1 Technical Data, Rev. 7

10

Freescale Semiconductor

Electrical Characteristics

3 Electrical Characteristics

This section contains the electrical specifications and timing diagrams for the i.MX1 processor.

3.1

Maximum Ratings

Table 4 provides information on maximum ratings which are those values beyond which damage to the

device may occur. Functional operation should be restricted to the limits listed in Recommended Operating

Range Table 5 on page 23 or the DC Characteristics table.

Table 4. Maximum Ratings

Symbol

NV_DD

Rating

Minimum

-0.3

Maximum

3.3

Unit

V

DC I/O Supply Voltage

QV_DD

DC Internal (core = 150 MHz) Supply Voltage

DC Internal (core = 200 MHz) Supply Voltage

DC Analog Supply Voltage

-0.3

1.9

V

QV_DD

-0.3

2.0

V

AV_DD

-0.3

3.3

V

BTRFV_DD

DC Bluetooth Supply Voltage

-0.3

3.3

V

VESD_HBM

VESD_MM

ILatchup

Test

ESD immunity with HBM (human body model)

ESD immunity with MM (machine model)

Latch-up immunity

–

2000

100

200

150

V

–

mA

°C

Storage temperature

-55

800¹

1300²

Pmax

Power Consumption

mW

A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM^®

core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.

1

2

A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the

ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS

application at MHz, and where the whole image is running out of SDRAM. QVDD at V, NVDD and AVDD at 3.3V, therefore,

180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle

GPIO consuming 4mA.

3.2

Recommended Operating Range

Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MX1

processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are

used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of

VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply

voltage levels in a system.

Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter

the AVDD pins from other VDD pins.

BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data

transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used

MC9328MX1 Technical Data, Rev. 7

22

Freescale Semiconductor

Electrical Characteristics

in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used

as other NVDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.

Table 5. Recommended Operating Range

Symbol

Rating

Minimum Maximum

Unit

T_A

Operating temperature range

0

70

°C

MC9328MX1VM20\MC9328MX1VM15

T_A

Operating temperature range

MC9328MX1DVM20\MC9328MX1DVM15

-30

-40

2.70

70

°C

V

Operating temperature range

MC9328MX1CVM15

85

NVDD

I/O supply voltage (if using MSHC, CSI, SPI, BTA, LCD, and USBd which

are only 3 V interfaces)

3.30

NVDD

QVDD

AVDD

I/O supply voltage (if not using the peripherals listed above)

Internal supply voltage (Core = 150 MHz)

Internal supply voltage (Core = 200 MHz)

Analog supply voltage

1.70

1.80

1.70

3.30

1.90

2.00

3.30

V

3.3

Power Sequence Requirements

For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of

application note AN2537 on the i.MX applications processor website.

3.4

DC Electrical Characteristics

Table 6 contains both maximum and minimum DC characteristics of the i.MX1 processor.

Table 6. Maximum and Minimum DC Characteristics

Number or

Symbol

Parameter

Min

Typical

Max

Unit

Iop

Full running operating current at 1.8V for QVDD, 3.3V for

NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4

decoding playback from external memory card to both

external SSI audio decoder and driving TFT display panel,

and OS with MMU enabled memory system is running on

external SDRAM).

–

QVDD at

–

mA

1.8V = 120mA;

NVDD+AVDD at

3.0V = 30mA

Sidd₁

Sidd₂

Sidd₃

Standby current

(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)

–

25

45

35

–

μA

Standby current

^{(Core = 150 MHz, QVDD = 1.8V, temp = 55}°C)

Standby current

(Core = 150 MHz, QVDD = 2.0V, temp = 25°C)

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

23

Electrical Characteristics

Table 6. Maximum and Minimum DC Characteristics (Continued)

Number or

Symbol

Parameter

Min

Typical

Max

Unit

Sidd₄

Standby current

–

60

–

μA

^{(Core = 150 MHz, QVDD = 2.0V, temp = 55}°C)

V

Input high voltage

0.7V

–

Vdd+0.2

0.4

V

IH

DD

V

Input low voltage

–

0.7V

–

IL

V

Output high voltage (I

= 2.0 mA)

Vdd

0.4

V

OH

DD

V

Output low voltage (I = -2.5 mA)

OL

V

OL

IL

I

Input low leakage current

–

1

μA

(V = GND, no pull-up or pull-down)

IN

I

Input high leakage current

–

1

–

μA

mA

μA

IH

(V = V , no pull-up or pull-down)

IN

DD

I

Output high current

(V = 0.8V_DD, V_DD= 1.8V)

4.0

-4.0

–

OH

I

Output low current

–

OL

OZ

(V = 0.4V, V_DD= 1.8V)

OL

I

Output leakage current

5

(V = V , output is high impedance)

out

DD

C

Input capacitance

Output capacitance

–

5

pF

i

C

o

3.5

AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All

signals are specified relative to an appropriate edge of other signals. All timing specifications are specified

at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an

operating supply voltage from V

timing is measured at 30 pF loading.

to V

under an operating temperature from T to T . All

L H

DD max

DD min

Table 7. Tristate Signal Timing

Parameter

Minimum

Maximum

Unit

TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z

Table 8. 32k/16M Oscillator Signal Timing

–

20.8

ns

Parameter

Minimum

RMS

Maximum

Unit

EXTAL32k input jitter (peak to peak)

EXTAL32k startup time

–

5

–

20

–

ns

800

ms

MC9328MX1 Technical Data, Rev. 7

24

Freescale Semiconductor

Functional Description and Application Information

Table 8. 32k/16M Oscillator Signal Timing (Continued)

Parameter

Minimum

RMS

Maximum

Unit

EXTAL16M input jitter (peak to peak) ¹

EXTAL16M startup time ¹

–

TBD

–

TBD

–

TBD

1

The 16 MHz oscillator is not recommended for use in new designs.

4 Functional Description and Application Information

This section provides the electrical information including and timing diagrams for the individual modules

of the i.MX1.

4.1

Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the

ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit

shift register comprised of the following:

•

32-bit data field

7-bit address field

A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address

field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit

data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.

The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used

in Figure 2.

2a

1

2b

3a

TRACECLK

3b

TRACECLK

(Half-Rate Clocking Mode)

Output Trace Port

Valid Data

4a

Figure 2. Trace Port Timing Diagram

4b

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

25

Functional Description and Application Information

Table 9. Trace Port Timing Diagram Parameter Table

1.8 ꢀ.1 V 3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

CLK frequency

0

1.3

3

85

–

0

2

–

2

3

100

–

MHz

ns

2a

2b

3a

3b

4a

4b

Clock high time

Clock low time

Clock rise time

Clock fall time

–

ns

–

4

3

ns

–

3

ns

Output hold time

Output setup time

2.28

3.42

–

ns

–

ns

4.2

DPLL Timing Specifications

Parameters of the DPLL are given in Table 10. In this table, T is a reference clock period after the

ref

Table 1ꢀ. DPLL Specifications

Test Conditions

pre-divider and T is the output double clock period.

dck

Parameter

Minimum Typical Maximum

Unit

DPLL input clock freq range

Vcc = 1.8V

5

–

100

30

MHz

Pre-divider output clock

freq range

MHz

DPLL output clock freq range

Pre-divider factor (PD)

Vcc = 1.8V

–

80

1

–

220

16

MHz

–

Total multiplication factor (MF) Includes both integer and fractional parts

5

15

MF integer part

–

5

15

–

MF numerator

Should be less than the denominator

0

1022

1023

312.5

–

MF denominator

Pre-multiplier lock-in time

–

1

–

μsec

Freq lock-in time after

full reset

FOL mode for non-integer MF

(does not include pre-multi lock-in time)

280

(56 μs)

T_ref

250

220

300

270

–

300

270

400

370

0.01

Freq lock-in time after

partial reset

FOL mode for non-integer MF (does not

include pre-multi lock-in time)

250

(50 μs)

Phase lock-in time after

full reset

FPL mode and integer MF (does not include

pre-multi lock-in time)

350

(70 μs)

T_ref

Phase lock-in time after

partial reset

FPL mode and integer MF (does not include

pre-multi lock-in time)

320

(64 μs)

T_ref

Freq jitter (p-p)

–

0.005

(0.01%)

2•T_dck

MC9328MX1 Technical Data, Rev. 7

26

Freescale Semiconductor

Functional Description and Application Information

Table 1ꢀ. DPLL Specifications (Continued)

Parameter

Phase jitter (p-p)

Test Conditions

Minimum Typical Maximum

Unit

Integer MF, FPL mode, Vcc=1.8V

1.0

–

1.7

–

1.5

2.5

4

ns

V

(10%)

Power supply voltage

Power dissipation

–

FOL mode, integer MF,

f_dck= MHz, Vcc = 1.8V

–

mW

4.3

Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and

Figure 4.

NOTE

Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up

to prevent forward biasing.

90% AVDD

1

10% AVDD

POR

2

RESET_POR

Exact 300ms

3

7 cycles @ CLK32

RESET_DRAM

4

14 cycles @ CLK32

HRESET

RESET_OUT

CLK32

HCLK

Figure 3. Timing Relationship with POR

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

27

Functional Description and Application Information

5

RESET_IN

14 cycles @ CLK32

HRESET

RESET_OUT

6

4

CLK32

HCLK

Figure 4. Timing Relationship with RESET_IN

Table 11. Reset Module Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref

No.

Parameter

Unit

Min

Max

–

Min

Max

–

note¹

300

note¹

300

1

2

Width of input POWER_ON_RESET

–

Width of internal POWER_ON_RESET

(9600 *CLK32 at 32 kHz)

300

ms

3

4

5

6

7K to 32K-cycle stretcher for SDRAM reset

7

14

4

7

14

–

7

14

4

7

14

–

Cycles of

CLK32

14K to 32K-cycle stretcher for internal system reset

HRESERT and output reset at pin RESET_OUT

Cycles of

CLK32

Width of external hard-reset RESET_IN

Cycles of

CLK32

4K to 32K-cycle qualifier

4

Cycles of

CLK32

1

POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal

tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals

for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals.

Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.

If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in

calculating timing for the start-up process.

4.4

External Interface Module

The External Interface Module (EIM) handles the interface to devices external to the i.MX1 processor,

including the generation of chip-selects for external peripherals and memory. The timing diagram for the

EIM is shown in Figure 5, and Table 12 defines the parameters of signals.

MC9328MX1 Technical Data, Rev. 7

28

Freescale Semiconductor

Functional Description and Application Information

(HCLK) Bus Clock

Address

1a

2a

3a

1b

2b

Chip-select

3b

Read (Write)

4a

5a

4b

OE (rising edge)

4c

5c

4d

OE (falling edge)

EB (rising edge)

EB (falling edge)

5b

5d

6a

6b

LBA (negated falling edge)

LBA (negated rising edge)

6c

7b

7a

BCLK (burst clock) - rising edge

7c

7d

BCLK (burst clock) - falling edge

Read Data

8b

9a

8a

9b

Write Data (negated falling)

9c

Write Data (negated rising)

DTACK_B

10a

Figure 5. EIM Bus Timing Diagram

Table 12. EIM Bus Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Min

Typical Max

Min

Typical Max

1a

1b

2a

2b

3a

3b

Clock fall to address valid

2.48

1.55

2.69

1.55

1.35

1.86

3.31

2.48

3.31

2.48

2.79

2.59

9.11

5.69

7.87

6.31

6.52

6.11

2.4

1.5

2.6

1.5

1.3

1.8

3.2

2.4

3.2

2.4

2.7

2.5

8.8

5.5

7.6

6.1

6.3

5.9

ns

Clock fall to address invalid

Clock fall to chip-select valid

Clock fall to chip-select invalid

Clock fall to Read (Write) Valid

Clock fall to Read (Write) Invalid

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

29

Functional Description and Application Information

Table 12. EIM Bus Timing Parameter Table (Continued)

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Min

Typical Max

Min

Typical Max

4a

4b

4c

4d

5a

5b

5c

5d

6a

6b

6c

7a

7b

7c

7d

8a

8b

9a

9b

9c

10a

Clock¹rise to Output Enable Valid

Clock¹rise to Output Enable Invalid

Clock¹fall to Output Enable Valid

Clock¹fall to Output Enable Invalid

Clock¹rise to Enable Bytes Valid

Clock¹rise to Enable Bytes Invalid

Clock¹fall to Enable Bytes Valid

Clock¹fall to Enable Bytes Invalid

Clock¹fall to Load Burst Address Valid

Clock¹fall to Load Burst Address Invalid

Clock¹rise to Load Burst Address Invalid

Clock¹rise to Burst Clock rise

Clock¹rise to Burst Clock fall

2.32

2.11

2.38

2.17

1.91

1.81

1.97

1.76

2.07

1.97

1.91

1.61

1.55

5.54

0

2.62

2.52

2.69

2.59

2.52

2.42

2.59

2.48

2.79

2.62

2.48

2.59

–

6.85

6.55

7.04

6.73

5.54

5.24

5.69

5.38

6.73

6.83

6.45

5.64

5.84

5.59

5.80

–

2.3

2.1

2.3

2.1

1.9

1.8

1.9

1.7

2.0

1.9

1.6

1.5

5.5

0

2.6

2.5

2.6

2.5

2.4

2.5

2.4

2.7

2.6

2.4

2.5

–

6.8

6.5

6.8

6.5

5.5

5.2

5.5

5.2

6.5

6.6

6.4

5.6

5.8

5.4

5.6

–

ns

Clock¹fall to Burst Clock rise

Clock¹fall to Burst Clock fall

Read Data setup time

Read Data hold time

–

Clock¹rise to Write Data Valid

Clock¹fall to Write Data Invalid

Clock¹rise to Write Data Invalid

DTACK setup time

1.81

1.45

1.63

2.52

2.72

2.48

–

6.85

5.69

–

1.8

1.4

1.62

2.5

2.7

2.4

–

6.8

5.5

–

1

Clock refers to the system clock signal, HCLK, generated from the System DPLL

4.4.1

DTACK Signal Description

The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal

as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not

terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group

supports DTACK signal function when the external DTACK signal is used for data acknowledgement.

4.4.2

DTACK Signal Timing

Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units

of measure for this figure are found in the associated tables.

MC9328MX1 Technical Data, Rev. 7

30

Freescale Semiconductor

Functional Description and Application Information

4.4.2.1

WAIT Read Cycle without DMA

3

Address

2

CS5

EB

8

1

9

programmable

min 0ns

5

OE

4

WAIT

7

6

DATABUS

10

11

X1)

Figure 6. WAIT Read Cycle without DMA

Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

1

OE and EB assertion time

CS5 pulse width

See note 2

–

ns

2

3T

56.81

–

3

OE negated to address inactive

Wait asserted after OE asserted

Wait asserted to OE negated

Data hold timing after OE negated

Data ready after wait asserted

OE negated to CS negated

OE negated after EB negated

Become low after CS5 asserted

Wait pulse width

–

4

1020T

3T+7.17

–

5

2T+2.2

T-1.86

0

6

7

T

8

9

1.5T+0.24

0.5

1.5T+0.85

1.5

10

0

1019T

1020T

11

1T

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

EBC bit in CS5L register is clear.

3. Address becomes valid and CS asserts at the start of read access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

31

Functional Description and Application Information

4.4.2.2

WAIT Read Cycle DMA Enabled

4

Address

2

9

CS5

EB

1

10

programmable

min 0ns

3

7

6

OE

RW

(logic high)

WAIT

5

8

11

DATABUS

12

nput to

MX1)

Figure 7. DTACK WAIT Read Cycle DMA Enabled

Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

1

2

OE and EB assertion time

See note 2

–

ns

CS pulse width

3T

–

1.5T+0.85

0.93

3

OE negated before CS5 is negated

Address inactived before CS negated

Wait asserted after CS5 asserted

Wait asserted to OE negated

Data hold timing after OE negated

Data ready after wait is asserted

CS deactive to next CS active

OE negate after EB negate

1.5T+0.24

4

–

5

–

2T+2.2

T-1.86

–

1020T

3T+7.17

–

6

7

8

T

9

T

–

10

11

0.5

1.5

Wait becomes low after CS5 asserted

0

1019T

MC9328MX1 Technical Data, Rev. 7

32

Freescale Semiconductor

Functional Description and Application Information

Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

12

Wait pulse width

1T

1020T

ns

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

EBC bit in CS5L register is clear.

3. Address becomes valid and CS asserts at the start of read access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.

4.4.2.3

WAIT Write Cycle without DMA

5

Address

3

1

programmable

min 0ns

CS5

EB

10

2

programmable

min 0ns

4

7

RW

(logic high)

WAIT

OE

6

11

9

8

12

DATABUS

(output from

i.MX1)

Figure 8. WAIT Write Cycle without DMA

Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

1

2

3

4

5

6

CS5 assertion time

See note 2

3T

–

ns

EB assertion time

–

CS5 pulse width

–

2.5T+0.68

–

RW negated before CS5 is negated

RW negated to Address inactive

Wait asserted after CS5 asserted

2.5T-0.29

67.28

–

1020T

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

33

Functional Description and Application Information

Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

7

8

Wait asserted to RW negated

Data hold timing after RW negated

Data ready after CS5 is asserted

EB negated after CS5 is negated

Wait becomes low after CS5 asserted

Wait pulse width

1T+2.15

2T+7.34

–

ns

2.5T-1.18

9

–

T

10

11

12

1.5T+0.74

1.5T+2.35

1019T

1020T

0

1T

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.

3. Address becomes valid and RW asserts at the start of write access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.

4.4.2.4

WAIT Write Cycle DMA Enabled

5

Address

1

3

10

programmable

min 0ns

CS5

2

11

programmable

min 0ns

EB

4

7

RW

OE (logic high)

WAIT

6

12

9

8

13

DATABUS

Figure 9. WAIT Write Cycle DMA Enabled

MC9328MX1 Technical Data, Rev. 7

34

Freescale Semiconductor

Functional Description and Application Information

Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.ꢀ ꢀ.3 V

Number

Characteristic

Unit

Minimum

Maximum

1

2

CS5 assertion time

See note 2

–

ns

EB assertion time

See note 2

–

3

CS5 pulse width

3T

4

RW negated before CS5 is negated

Address inactived after CS negated

Wait asserted after CS5 asserted

Wait asserted to RW negated

Data hold timing after RW negated

Data ready after CS5 is asserted

CS deactive to next CS active

EB negate after CS negate

Wait becomes low after CS5 asserted

Wait pulse width

2.5T-0.29

2.5T+0.68

0.93

5

–

6

–

1020T

2T+7.34

–

7

T+2.15

8

24.87

9

–

T

10

11

12

13

T

–

1.5T+0.74

1.5T+2.35

1019T

1020T

0

ns

1T

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.

3. Address becomes valid and RW asserts at the start of write access cycle.

4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.

4.4.3

EIM External Bus Timing

The External Interface Module (EIM) is the interface to devices external to the i.MX1, including

generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown

in Figure 5, and Table 12 defines the parameters of signals.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

35

Functional Description and Application Information

hclk

hsel_weim_cs[0]

htrans

hwrite

Seq/Nonseq

Read

haddr

hready

V1

weim_hrdata

weim_hready

Last Valid Data

V1

BCLK (burst clock)

ADDR

Last Valid Address

V1

CS2

R/W

Read

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

V1

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 1ꢀ. WSC = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

36

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[0]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data (V1)

Unknown

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR

Last Valid Address

V1

CS0

R/W

Write

LBA

OE

EB

DATA

Last Valid Data

Write Data (V1)

Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

37

Functional Description and Application Information

hclk

hsel_weim_cs[0]

htrans

hwrite

haddr

Nonseq

Read

V1

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS0

Read

R/W

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

1/2 Half Word

2/2 Half Word

DATA

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

38

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[0]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data (V1 Word)

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS0

R/W

LBA

Write

OE

EB

DATA

1/2 Half Word

2/2 Half Word

Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

39

Functional Description and Application Information

hclk

hsel_weim_cs[3]

Nonseq

htrans

hwrite

Read

V1

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS[3]

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Note 1: x = 0, 1, 2 or 3

1/2 Half Word

2/2 Half Word

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

40

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[3]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata Last Valid

Data

Write Data (V1 Word)

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS3

R/W

LBA

OE

Write

EB

DATA

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

41

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

Read

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

weim_data_in

1/2 Half Word

2/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

42

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

Write

LBA

OE

EB

DATA

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

43

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Note 1: x = 0, 1, 2 or 3

1/2 Half Word

2/2 Half Word

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

44

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Note 1: x = 0, 1, 2 or 3

1/2 Half Word

2/2 Half Word

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

45

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

Unknown

weim_hrdata

weim_hready

BCLK (burst clock)

ADDR Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

Write

LBA

OE

EB

DATA

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 2ꢀ. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

46

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Unknown

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS2

R/W

LBA

OE

Write

EB

DATA

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

47

Functional Description and Application Information

hclk

hsel_weim_cs[2]

Nonseq

Read

V1

Nonseq

Write

V8

htrans

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data

Read Data

weim_hrdata

weim_hready

Last Valid Data

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V8

CS2

R/W

LBA

Read

Write

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Read Data

Last Valid Data

Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

48

Freescale Semiconductor

Functional Description and Application Information

Read

Idle

Write

hclk

hsel_weim_cs[2]

htrans

Nonseq

Read

V1

Nonseq

Write

V8

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data

Read Data

weim_hrdata

weim_hready

Last Valid Data

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V8

Write

CS2

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Read Data

Last Valid Data

Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

49

Functional Description and Application Information

hclk

hsel_weim_cs[4]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (Word)

Last Valid Data

weim_hrdata

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V1 + 2

CS

R/W

Write

LBA

OE

EB

DATA

Last Valid Data

Write Data (1/2 Half Word)

Write Data (2/2 Half Word)

Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

50

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[4]

htrans

Nonseq

Read

V1

Nonseq

Write

V8

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

Last Valid Data

Write Data

Read Data

Last Valid Data

BCLK (burst clock)

ADDR Last Valid Addr

Address V1

Address V8

CS4

R/W

LBA

OE

Read

Write

EBx¹(EBC²=0)

EBx¹(EBC²=1)

Read Data

DATA

Last Valid Data

Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

51

Functional Description and Application Information

hclk

hsel_weim_cs[4]

htrans

hwrite

haddr

Nonseq

Read

V1

Idle

Seq

Read

V2

hready

weim_hrdata

weim_hready

Last Valid Data

Read Data (V1)

Read Data (V2)

BCLK (burst clock)

ADDR

Last Valid

Address V1

Address V2

CNC

CS4

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

Read Data

(V1)

Read Data

(V2)

DATA

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

52

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[4]

htrans

Nonseq

Read

V1

Idle Nonseq

hwrite

haddr

Write

V8

hready

hwdata

Last Valid Data

Write Data

Read Data

weim_hrdata

Last Valid Data

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V8

CNC

CS4

R/W

LBA

OE

Read

Write

EBx¹(EBC²=0)

EBx¹(EBC²=1)

DATA

Read Data

Last Valid Data

Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

53

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Idle

Nonseq

Nonse

Read

V5

hwrite

haddr

Read

V1

hready

weim_hrdata

weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

Address V1

Address V5

CS2

Read

R/W

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

ECB

DATA

V1 Word V2 Word

V5 Word V6 Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF

MC9328MX1 Technical Data, Rev. 7

54

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Idle

Nonseq

Read

V1

Seq

Read

V2

Seq

Read

V3

Seq

Read

V4

hwrite

haddr

hready

weim_hrdata

weim_hready

BCLK (burst clock)

ADDR

Last Valid Data

V1 Word

V2 Word

V3 Word

V4 Word

Last Valid Addr

Address V1

CS2

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

ECB

DATA

V1 Word

V2 Word

V3 Word

V4 Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 29. WSC = 2, SYNC = 1, DOL = [1/ꢀ], A.WORD/E.WORD

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

55

Functional Description and Application Information

hclk

hsel_weim_cs[2]

htrans

Idle

Seq

Nonseq

hwrite

haddr

Read

V1

Read

V2

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK (burst clock)

ADDR

CS2

Last Valid

Address V1

Address V2

Read

R/W

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

ECB

DATA

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 3ꢀ. WSC = 2, SYNC = 1, DOL = [1/ꢀ], A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

56

Freescale Semiconductor

Functional Description and Application Information

hclk

hsel_weim_cs[2]

Non

seq

Idle

htrans

hwrite

Seq

Read

V1

Read

V2

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK (burst clock)

Last

ADDR

CS2

Address V1

Read

R/W

LBA

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

ECB

DATA

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

57

Functional Description and Application Information

hclk

hsel_weim_cs[2]

Non

seq

htrans

hwrite

haddr

Idle

Seq

Read

V2

Read

V1

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK (burst clock)

ADDR

Last

Address V1

CS2

R/W

LBA

Read

OE

EBx¹(EBC²=0)

EBx¹(EBC²=1)

ECB

DATA

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF

MC9328MX1 Technical Data, Rev. 7

58

Freescale Semiconductor

Functional Description and Application Information

4.4.4

Non-TFT Panel Timing

T1

VSYN

T3

T4

T2

XMAX

HSYN

SCLK

Ts

LD[15:0]

Figure 33. Non-TFT Panel Timing

Table 17. Non TFT Panel Timing Diagram

Allowed Register

Symbol

Parameter

Actual Value

Unit

Minimum Value^{1, 2}

Tpix⁴

Tpix

–

T1

HSYN to VSYN delay³

0

HWAIT2+2

HWIDTH+1

T2

T3

HSYN pulse width

VSYN to SCLK

0

–

0 ≤ T3 ≤ Ts⁵

T4

SCLK to HSYN

0

HWAIT1+1

Tpix

1

Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.

Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.

2

3

VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all

these 3 signals are active high.

4

5

Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).

Ts is the shift clock period. Ts = Tpix * (panel data bus width).

4.5

Pen ADC Specifications

The specifications for the pen ADC are shown in Table 18 through Table 20.

Table 18. Pen ADC System Performance

Full Range Resolution¹

Non-Linearity Error¹

Accuracy ¹

13 bits

4 bits

9 bits

1

Tested under input = 0~1.8V at 25°C

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

59

Functional Description and Application Information

Table 19. Pen ADC Test Conditions

Vp max 1800 mV ip max +7 µA

Vp min

Vn

GND

ip min

in

1.5 µA

Sample frequency

Sample rate

12 MHz

1.2 KHz

100 Hz

Input frequency

Input range

0–1800 mV

Note: Ru1 = Ru2 = 200K

Table 2ꢀ. Pen ADC Absolute Rating

ip max

ip min

in max

in min

+9.5 µA

-2.5 µA

+9.5 µA

-2.5 µA

4.6

ASP Touch Panel Controller

The following sections contain the electrical specifications of the ASP touch panel controller. The value

of parameters and their corresponding measuring conditions are mentioned as well.

4.6.1

Electrical Specifications

Test conditions: Temperature = 25º C, QVDD = 1800mV.

Table 21. ASP Touch Panel Controller Electrical Spec

Parameter

Minimum

Typical

Maximum

Unit

Offset

–

32768

–

8199

–

Offset Error

Gain

mV^-1

–

13.65

Gain Error

DNL

–

9

33%

8

–

Bits

mV

Ohm

INL

–

0

–

Accuracy (without missing code)

Operating Voltage Range (Pen)

Operating Voltage Range (U)

On-resistance of switches SW[8:1]

8

9

–

QVDD

–

Negative QVDD

–

10

Note that QVDD should be 1800mV.

MC9328MX1 Technical Data, Rev. 7

60

Freescale Semiconductor

Functional Description and Application Information

4.6.2

Gain Calculations

The ideal mapping of input voltage to output digital sample is defined as follows:

Sample

65535

Smax

G0

C0

Vi

2400

-2400

1800

Figure 34. Gain Calculations

In general, the mapping function is:

S = G * V + C

Where V is input, S is output, G is the slope, and C is the y-intercept.

-1

Nominal Gain G = 65535 / 4800 = 13.65mV

0

Nominal Offset C = 65535 / 2 = 32767

0

4.6.3

Offset Calculations

The ideal mapping of input voltage to output digital sample is defined as:

Sample

65535

G0

Smax

C0

Vi

2400

-2400

1800

Figure 35. Offset Calculations

In general, the mapping function is:

S = G * V + C

Where V is input, S is output, G is the slope, and C is the y-intercept.

-1

Nominal Gain G = 65535 / 4800 = 13.65mV

0

Nominal Offset C = 65535 / 2 = 32767

0

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

61

Functional Description and Application Information

4.6.4

Gain Error Calculations

Gain error calculations are made using the information in this section.

Sample

Gmax

65535

Smax

G0

C0

Vi

2400

- 2400

1800

Figure 36. Gain Error Calculations

Assuming the offset remains unchanged, the mapping is rotated around y-intercept to determine the

maximum gain allowed. This occurs when the sample at 1800mV has just reached the ceiling of the 16-bit

range, 65535.

Maximum Offset G

max,

G

= (65535 - C / 1800

max

0)

= (65535 - 32767) / 1800

= 18.20

Gain Error G

r,

G

= (G

- G ) / G * 100%

max 0 0

r

= (18.20 - 13.65) / 13.65 * 100%

= 33%

4.7

Bluetooth Accelerator

CAUTION

On-chip accelerator hardware is not supported by software. An external

Bluetooth chip interfaced to a UART is recommended.

The Bluetooth Accelerator (BTA) radio interface supports the Wireless RF Transceiver, MC13180 using

an SPI interface. This section provides the data bus timing diagrams and SPI interface timing diagrams

shown in Figure 37 and Figure 38, and the associated parameters shown in Table 22 and Table 23.

MC9328MX1 Technical Data, Rev. 7

62

Freescale Semiconductor

Functional Description and Application Information

2

BT CLK (BT1)

7

Receive

FS (BT5)

1

PKT DATA (BT3)

3

4

RXTX_EN (BT9)

PKT DATA (BT2)

Transmit

8

5

6

Figure 37. MC1318ꢀ Data Bus Timing Diagram

Table 22. MC1318ꢀ Data Bus Timing Parameter Table

Ref No.

Parameter

Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

FrameSync setup time relative to BT CLK rising edge¹

FrameSync hold time relative to BT CLK rising edge¹

Receive Data setup time relative to BT CLK rising edge¹

Receive Data hold time relative to BT CLK rising edge¹

Transmit Data setup time relative to RXTX_EN rising edge²

TX DATA period

–

4

–

ns

µs

ns

%

–

12

–

6

–

13

–

172.5

–

192.5

1000 +/- 0.02

BT CLK duty cycle

40

4

–

60

10

Transmit Data hold time relative to RXTX_EN falling edge

µs

1

2

Please refer to 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation.

The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and

RF_Status (0x0021605C) registers.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

63

Functional Description and Application Information

5

1

4

6

SPI CLK (BT13)

9

SPI_EN (BT11)

8

SPI_DATA_OUT (BT12)

3

7

SPI_DATA_IN (BT4)

2

Figure 38. SPI Interface Timing Diagram Using MC1318ꢀ

Table 23. SPI Interface Timing Parameter Table Using MC1318ꢀ

Ref No.

Parameter

Minimum Maximum

Unit

1

2

3

4

5

6

7

8

9

SPI_EN setup time relative to rising edge of SPI_CLK

Transmit data delay time relative to rising edge of SPI_CLK

Transmit data hold time relative to rising edge of SPI_EN

SPI_CLK rise time

15

0

–

15

25

–

ns

0

ns

0

ns

SPI_CLK fall time

0

ns

SPI_EN hold time relative to falling edge of SPI_CLK

Receive data setup time relative to falling edge of SPI_CLK¹

Receive data hold time relative to falling edge of SPI_CLK¹

SPI_CLK frequency, 50% duty cycle required¹

15

–

ns

–

ns

–

ns

20

MHz

1

The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by programming

SPI_Control (0x00216138) register together with system clock.

4.8

SPI Timing Diagrams

To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a

master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY

signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period

Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or

SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register

(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input

signal, and is used to latch data into or load data out to the internal data shift registers, as well as to

increment the data FIFO. Figure 39 through Figure 43 show the timing relationship of the master SPI using

different triggering mechanisms.

MC9328MX1 Technical Data, Rev. 7

64

Freescale Semiconductor

Functional Description and Application Information

2

5

3

SS

1

4

SPIRDY

SCLK, MOSI, MISO

Figure 39. Master SPI Timing Diagram Using SPI_RDY Edge Trigger

SS

SPIRDY

SCLK, MOSI, MISO

Figure 4ꢀ. Master SPI Timing Diagram Using SPI_RDY Level Trigger

SS (output)

SCLK, MOSI, MISO

Figure 41. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger

SS (input)

SCLK, MOSI, MISO

Figure 42. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT

SS (input)

6

7

SCLK, MOSI, MISO

Figure 43. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

65

Functional Description and Application Information

Table 24. Timing Parameter Table for Figure 39 through Figure 43

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

2T¹

1

2

SPI_RDY to SS output low

–

ns

3 • Tsclk²

2 • Tsclk

0

SS output low to first SCLK edge

3

4

5

Last SCLK edge to SS output high

SS output high to SPI_RDY low

SS output pulse width

–

ns

Tsclk + WAIT ³

6

7

SS input low to first SCLK edge

SS input pulse width

T

–

ns

1

2

3

T = CSPI system clock period (PERCLK2).

Tsclk = Period of SCLK.

WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.

8

SCLK

9

Figure 44. SPI SCLK Timing Diagram

Table 25. Timing Parameter Table for SPI SCLK

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

8

9

SCLK frequency

SCLK pulse width

0

10

–

MHz

ns

100

4.9

LCD Controller

This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD

controller with various display configurations, refer to the LCD controller chapter of the MC9328MX1

Reference Manual.

LSCLK

1

LD[15:0]

Figure 45. SCLK to LD Timing Diagram

MC9328MX1 Technical Data, Rev. 7

66

Freescale Semiconductor

Functional Description and Application Information

Table 26. LCDC SCLK Timing Parameter Table

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Minimum

Maximum

Unit

1

SCLK to LD valid

–

2

ns

Non-display

Display region

T3

T1

T4

VSYN

T2

HSYN

OE

Line Y

Line 1

Line Y

LD[15:0]

T6

T7

T5

XMAX

HSYN

SCLK

OE

T8

(1,1)

(1,2)

LD[15:0]

VSYN

(1,X)

T9

T10

Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

Table 27. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

Symbol

Description

Minimum

Corresponding Register Value

Unit

T1

End of OE to beginning of VSYN

T5+T6

(VWAIT1·T2)+T5+T6+T7+T9

Ts

+T7+T9

T2

T3

T4

T5

T6

T7

HSYN period

XMAX+5

XMAX+T5+T6+T7+T9+T10

VWIDTH·(T2)

VWAIT2·(T2)

Ts

VSYN pulse width

T2

2

End of VSYN to beginning of OE

HSYN pulse width

1

HWIDTH+1

End of HSYN to beginning to T9

End of OE to beginning of HSYN

1

HWAIT2+1

1

HWAIT1+1

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

67

Functional Description and Application Information

Table 27. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)

Symbol

Description

SCLK to valid LD data

Minimum

Corresponding Register Value

Unit

T8

T9

-3

2

3

2

ns

Ts

End of HSYN idle2 to VSYN edge

(for non-display region)

T9

End of HSYN idle2 to VSYN edge

(for Display region)

1

Ts

T10

VSYN to OE active (Sharp = 0) when VWAIT2 = 0

VSYN to OE active (Sharp = 1) when VWAIT2 = 0

1

2

1

2

Ts

Note:

•

Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.

VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals

are active low.

•

The polarity of SCLK and LD[15:0] can also be programmed.

SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.

In Figure 46, SCLK is always active.

•

For T9 non-display region, VSYN is non-active. It is used as an reference.

XMAX is defined in pixels.

4.1ꢀ Multimedia Card/Secure Digital Host Controller

The DMA interface block controls all data routing between the external data bus (DMA access), internal

MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that

monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the

MMC/SD module (inner system) and the application (user programming).

3a

1

2

4b

3b

Bus Clock

4a

5b

5a

Valid Data

CMD_DAT Input

Valid Data

7

CMD_DAT Output

Valid Data

6a

Figure 47. Chip-Select Read Cycle Timing Diagram

6b

MC9328MX1 Technical Data, Rev. 7

68

Freescale Semiconductor

Functional Description and Application Information

Table 28. SDHC Bus Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

CLK frequency at Data transfer Mode

(PP)¹—10/30 cards

0

25/5

0

25/5

MHz

2

CLK frequency at Identification Mode²

Clock high time¹—10/30 cards

Clock low time¹—10/30 cards

Clock fall time¹—10/30 cards

0

6/33

15/75

–

400

–

0

400

–

kHz

ns

3a

3b

4a

10/50

–

ns

10/50

ns

(5.00)³

4b

Clock rise time¹—10/30 cards

–

14/67

(6.67)³

–

10/50

ns

5a

5b

6a

6b

7

Input hold time³—10/30 cards

Input setup time³—10/30 cards

Output hold time³—10/30 cards

Output setup time³—10/30 cards

Output delay time³

10.3/10.3

5.7/5.7

0

–

9/9

5/5

0

–

ns

–

16

14

1

2

3

C_L≤ 100 pF / 250 pF (10/30 cards)

C_L≤ 250 pF (21 cards)

C_L≤ 25 pF (1 card)

4.1ꢀ.1 Command Response Timing on MMC/SD Bus

The card identification and card operation conditions timing are processed in open-drain mode. The card

response to the host command starts after exactly N clock cycles. For the card address assignment,

ID

SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and

card response is NCR clock cycles as illustrated in Figure 48. The symbols for Figure 48 through

Figure 52 are defined in Table 29.

Table 29. State Signal Parameters for Figure 48 through Figure 52

Card Active

Definition

Host Active

Definition

Symbol

Z

D

High impedance state

Data bits

S

T

P

E

Start bit (0)

Transmitter bit (Host = 1, Card = 0)

One-cycle pull-up (1)

End bit (1)

*

Repetition

CRC

Cyclic redundancy check bits (7 bits)

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

69

Functional Description and Application Information

N

_IDcycles

Host Command

Content

CRC

CID/OCR

Content

CMD

******

ST

E Z

Z S T

Z Z Z

Identification Timing

N_CRcycles

Host Command

Content

CRC

CID/OCR

******

Content

SET_RCA Timing

ST

E Z

Z S T

Z Z Z

Figure 48. Timing Diagrams at Identification Mode

After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in

Figure 49, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a

period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the

responding card. The other two diagrams show the separating periods N and N

.

RC

CC

N_CRcycles

Host Command

Response

Content

CRC

E Z Z Z

CMD

Content

CRC

******

ST

E Z Z P

P S T

Command response timing (data transfer mode)

N_RCcycles

Response

Content

Host Command

Content

CRC

E Z Z Z

CMD

CRC

******

ST

E Z

Z S T

Timing response end to next CMD start (data transfer mode)

N_CCcycles

Host Command

Content

CRC

E Z Z Z

CMD

Content

CRC

E Z

******

ST

Z S T

Timing of command sequences (all modes)

Figure 49. Timing Diagrams at Data Transfer Mode

Figure 50 shows basic read operation timing. In a read operation, the sequence starts with a single block

read command (which specifies the start address in the argument field). The response is sent on the

SD_CMD lines as usual. Data transmission from the card starts after the access time delay N , beginning

AC

from the last bit of the read command. If the system is in multiple block read mode, the card sends a

continuous flow of data blocks with distance N until the card sees a stop transmission command. The

AC

data stops two clock cycles after the end bit of the stop command.

MC9328MX1 Technical Data, Rev. 7

70

Freescale Semiconductor

Functional Description and Application Information

N_CRcycles

Host Command

Response

CMD

DAT

Content

CRC

******

Content

CRC

E Z

ST

E Z Z P

P S T

Z****Z

*****

Z Z P

P S DDDD

Read Data

Timing of single block read

N_ACcycles

N_CRcycles

Host Command

Response

Content

CRC

E Z

CMD

DAT

Content

CRC

******

ST

E Z Z P

Z Z P

P S T

Z****Z

******

*****

Read Data

*****

Read Data

P S DDDD

P

P S DDDD

N_ACcycles

Timing of multiple block read

N_CRcycles

Host Command

Response

CMD

Content

CRC

******

Content

CRC

E Z

ST

E Z Z P

P S T

N_ST

DAT

*****

DDDD

DDDD E Z Z Z

Timing of stop command

(CMD12, data transfer mode)

Valid Read Data

Figure 5ꢀ. Timing Diagrams at Data Read

Figure 51 shows the basic write operation timing. As with the read operation, after the card response, the

data transfer starts after N cycles. The data is suffixed with CRC check bits to allow the card to check

WR

for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If

there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC

status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple

block mode, with the flow terminated by a stop transmission command.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

71

Functional Description and Application Information

Figure 51. Timing Diagrams at Data Write

The stop transmission command may occur when the card is in different states. Figure 52 shows the

different scenarios on the bus.

MC9328MX1 Technical Data, Rev. 7

72

Freescale Semiconductor

Functional Description and Application Information

Figure 52. Stop Transmission During Different Scenarios

Table 3ꢀ. Timing Values for Figure 48 through Figure 52

Parameter Symbol Minimum Maximum

MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)

Unit

Command response cycle

Identification response cycle

Access time delay cycle

NCR

NID

2

5

2

64

Clock cycles

5

NAC

TAAC + NSAC

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

73

Functional Description and Application Information

Table 3ꢀ. Timing Values for Figure 48 through Figure 52 (Continued)

Parameter

Command read cycle

Symbol

Minimum

Maximum

Unit

NRC

NCC

NWR

NST

8

2

–

2

Clock cycles

Command-command cycle

Command write cycle

Stop transmission cycle

TAAC: Data read access time -1 defined in CSD register bit[119:112]

NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]

4.1ꢀ.2 SDIO-IRQ and ReadWait Service Handling

In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the

interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data

in this mode. The memory controller generates an interrupt according to this low and the system interrupt

continues until the source is removed (SD_DAT[1] returns to its high level).

In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the “Interrupt

Period” during the data access, and the controller must sample SD_DAT[1] during this short period to

determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each

block (512 bytes).

CMD

Content

CRC

Response

******

S

ST

E Z Z P S

E Z Z Z

Z Z Z

DAT[1]

Interrupt Period

IRQ

Block Data

S

E

For 4-bit

L H

DAT[1]

Interrupt Period

For 1-bit

Figure 53. SDIO IRQ Timing Diagram

ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In

this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps

the clock running, and allows the user to submit commands as normal. After all commands are submitted,

the user can switch back to the data transfer operation and all counter and status values are resumed as

access continues.

MC9328MX1 Technical Data, Rev. 7

74

Freescale Semiconductor

Functional Description and Application Information

CMD

******

CMD52 CRC

******

P S T

E Z Z Z

DAT[1]

Block Data

S

E Z Z L H

S

E

For 4-bit

DAT[2]

Block Data

E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S

For 4-bit

Figure 54. SDIO ReadWait Timing Diagram

4.11 Memory Stick Host Controller

The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,

MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in

either four-state or two-state access mode.

The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according

to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet

transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,

BS2, and BS3 states are regarded as one packet length and one communication transfer is always

completed within one packet length (in four-state access mode).

The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When

an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0

and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

75

Functional Description and Application Information

2

3

5

1

4

MS_SCLKI

6

8

7

MS_SCLKO

MS_BS

9

10

11

12

11

12

MS_SDIO(output)

14

13

MS_SDIO (input)

(RED bit = 0)

15

16

MS_SDIO (input)

(RED bit = 1)

Figure 55. MSHC Signal Timing Diagram

Table 31. MSHC Signal Timing Parameter Table

Parameter

3.ꢀ ꢀ.3 V

Minimum Maximum

Ref

No.

Unit

1

2

MS_SCLKI frequency

–

20

–

25

–

MHz

ns

MS_SCLKI high pulse width

MS_SCLKI low pulse width

MS_SCLKI rise time

3

–

ns

4

3

ns

5

MS_SCLKI fall time

–

3

ns

6

MS_SCLKO frequency¹

MS_SCLKO high pulse width¹

MS_SCLKO low pulse width¹

MS_SCLKO rise time¹

MS_SCLKO fall time¹

–

25

–

MHz

ns

7

20

15

–

8

–

ns

9

5

ns

10

11

–

5

ns

MS_BS delay time¹

–

3

ns

MC9328MX1 Technical Data, Rev. 7

76

Freescale Semiconductor

Functional Description and Application Information

Table 31. MSHC Signal Timing Parameter Table (Continued)

3.ꢀ ꢀ.3 V

Ref

No.

Parameter

MS_SDIO output delay time^1,2

Unit

Minimum Maximum

12

13

14

15

16

–

18

0

3

–

ns

MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)³

MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)³

MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)⁴

MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)⁴

23

0

1

2

Loading capacitor condition is less than or equal to 30pF.

An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,

because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin

direction changes.

3

4

If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.

If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.

4.12 Pulse-Width Modulator

The PWM can be programmed to select one of two clock signals as its source frequency. The selected

clock signal is passed through a divider and a prescaler before being input to the counter. The output is

available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in

Figure 56 and the parameters are listed in Table 32.

1

2a

3b

System Clock

2b

4b

3a

4a

PWM Output

Figure 56. PWM Output Timing Diagram

Table 32. PWM Output Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

System CLK frequency¹

Clock high time¹

Clock low time¹

0

87

–

0

100

–

MHz

ns

2a

2b

3a

3.3

7.5

–

5/10

–

ns

Clock fall time¹

5

5/10

ns

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

77

Functional Description and Application Information

Table 32. PWM Output Timing Parameter Table (Continued)

1.8 ꢀ.1 V 3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

3b

4a

4b

Clock rise time¹

–

6.67

–

5

5/10

–

ns

Output delay time¹

Output setup time¹

5.7

–

1

C_Lof PWMO = 30 pF

4.13 SDRAM Controller

This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic

random access memory) Controller.

1

SDCLK

2

3S

3

CS

RAS

CAS

3H

3S

3H

3S

3H

4H

WE

ADDR

DQ

4S

ROW/BA

COL/BA

5

8

6

Data

7

3S

DQM

3H

Note: CKE is high during the read/write cycle.

Figure 57. SDRAM Read Cycle Timing Diagram

MC9328MX1 Technical Data, Rev. 7

78

Freescale Semiconductor

Functional Description and Application Information

Table 33. SDRAM Read Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

2.67

6

–

4

–

ns

11.4

3.42

2.28

3.42

2.28

–

10

3

–

3S CS, RAS, CAS, WE, DQM setup time

3H CS, RAS, CAS, WE, DQM hold time

4S Address setup time

–

2

–

3

–

4H Address hold time

–

2

–

5

6

7

8

SDRAM access time (CL = 3)

6.84

22

–

6

SDRAM access time (CL = 2)

–

6

SDRAM access time (CL = 1)

–

22

–

Data out hold time

2.85

–

2.5

–

Data out high-impedance time (CL = 3)

Data out high-impedance time (CL = 2)

Data out high-impedance time (CL = 1)

Active to read/write command period (RC = 1)

6.84

22

–

6

–

6

–

22

–

1

t_RCD1

t_RCD

1

t_RCD= SDRAM clock cycle time. This settings can be found in the MC9328MX1 reference manual.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

79

Functional Description and Application Information

SDCLK

1

3

2

CS

RAS

6

CAS

WE

ADDR

DQ

5

7

4

/ BA

ROW/BA

COL/BA

DATA

8

9

DQM

Figure 58. SDRAM Write Cycle Timing Diagram

Table 34. SDRAM Write Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

4

5

6

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

2.67

6

–

4

–

ns

11.4

3.42

2.28

10

3

Address hold time

Precharge cycle period¹

2

t_RP2

t_RP

7

Active to read/write command delay

t_RCD2

–

t_RCD2

–

ns

8

9

Data setup time

Data hold time

4.0

–

2

–

ns

2.28

1

Precharge cycle timing is included in the write timing diagram.

2

t_RPand t_RCD= SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual.

MC9328MX1 Technical Data, Rev. 7

80

Freescale Semiconductor

Functional Description and Application Information

SDCLK

CS

1

3

2

RAS

CAS

6

7

WE

ADDR

DQ

4

5

BA

ROW/BA

DQM

Figure 59. SDRAM Refresh Timing Diagram

Table 35. SDRAM Refresh Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

4

5

6

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

2.67

6

–

4

–

ns

11.4

3.42

2.28

10

3

Address hold time

2

1

Precharge cycle period

t_RP1

t_RP

7

Auto precharge command period

t_RC1

–

t_RC1

–

ns

1

t_RPand t_RC= SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

81

Functional Description and Application Information

SDCLK

CS

RAS

CAS

WE

ADDR

DQ

BA

DQM

CKE

Figure 6ꢀ. SDRAM Self-Refresh Cycle Timing Diagram

4.14 USB Device Port

Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous

transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is

identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section

covers the transfer modes and how they work from the ground up.

Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same

packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved

in the form of packets, however, because isochronous pipes are given a fixed portion of the USB

bandwidth at all times, there is no end-of-transfer.

MC9328MX1 Technical Data, Rev. 7

82

Freescale Semiconductor

Functional Description and Application Information

USBD_AFE

(Output)

t _{VMO_ROE}

4

t _{ROE_VPO}

1

USBD_ROE

(Output)

6

3

t_PERIOD

t_{VPO_ROE}

USBD_VPO

(Output)

USBD_VMO

(Output)

t_{ROE_VMO}

t_FEOPT

USBD_SUSPND

(Output)

2

5

USBD_RCV

(Input)

USBD_VP

(Input)

USBD_VM

(Input)

Figure 61. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)

Table 36. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)

3.ꢀ ꢀ.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

1

2

3

4

5

6

t

_{ROE_VPO}; USBD_ROE active to USBD_VPO low

83.14

81.55

83.54

248.90

160.00

11.97

83.47

81.98

83.80

249.13

175.00

12.03

ns

t_{ROE_VMO}; USBD_ROE active to USBD_VMO high

t_{VPO_ROE}; USBD_VPO high to USBD_ROE deactivated

t_{VMO_ROE}; USBD_VMO low to USBD_ROE deactivated (includes SE0)

t_FEOPT; SE0 interval of EOP

ns

t_PERIOD; Data transfer rate

Mb/s

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

83

Functional Description and Application Information

USBD_AFE

(Output)

USBD_ROE

(Output)

USBD_VPO

(Output)

USBD_VMO

(Output)

USBD_SUSPND

(Output)

USBD_RCV

(Input)

1

t_FEOPR

USBD_VP

(Input)

USBD_VM

(Input)

Figure 62. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)

Table 37. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

1

t_FEOPR; Receiver SE0 interval of EOP

82

–

ns

2

4.15 I C Module

2

The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data

Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

SDA

5

3

4

SCL

2

6

1

2

Figure 63. Definition of Bus Timing for I C

MC9328MX1 Technical Data, Rev. 7

84

Freescale Semiconductor

Functional Description and Application Information

2

Table 38. I C Bus Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

4

5

6

Hold time (repeated) START condition

Data hold time

182

0

–

171

–

160

0

–

150

–

ns

Data setup time

11.4

80

10

HIGH period of the SCL clock

LOW period of the SCL clock

Setup time for STOP condition

–

120

320

160

–

480

182.4

–

4.16 Synchronous Serial Interface

The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,

the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous

mode, the transmitter and receiver each have their own clock and frame synchronization signals.

Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated

clock mode, the clock functions only during transmission. The internal and external clock timing diagrams

are shown in Figure 65 through Figure 67.

Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of

I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is

typically used in star or ring-time division multiplex networks with other processors or codecs, allowing

interface to time division multiplexed networks without additional logic. Use of the gated clock is not

allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to

communicate with a wide variety of devices.

1

STCK Output

4

2

STFS (bl) Output

STFS (wl) Output

6

8

12

11

32

10

STXD Output

SRXD Input

31

Note: SRXD input in synchronous mode only.

Figure 64. SSI Transmitter Internal Clock Timing Diagram

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

85

Functional Description and Application Information

1

SRCK Output

3

5

SRFS (bl) Output

SRFS (wl) Output

7

9

13

14

SRXD Input

Figure 65. SSI Receiver Internal Clock Timing Diagram

15

16

17

STCK Input

18

20

STFS (bl) Input

STFS (wl) Input

24

22

28

27

34

26

STXD Output

SRXD Input

33

Note: SRXD Input in Synchronous mode only

Figure 66. SSI Transmitter External Clock Timing Diagram

MC9328MX1 Technical Data, Rev. 7

86

Freescale Semiconductor

Functional Description and Application Information

15

16

17

SRCK Input

19

21

SRFS (bl) Input

SRFS (wl) Input

25

23

30

29

SRXD Input

Figure 67. SSI Receiver External Clock Timing Diagram

Table 39. SSI (Port C Primary Function) Timing Parameter Table

1.8 ꢀ.1 V

3.ꢀ ꢀ.3 V

Ref No.

Parameter

Unit

Minimum Maximum Minimum Maximum

Internal Clock Operation¹(Port C Primary Function²)

1

2

STCK/SRCK clock period¹

95

1.5

–

4.5

83.3

1.3

-1.1

2.2

0.1

1.3

-1.1

2.2

0.1

12.5

0.8

0.5

11.3

18.5

0

–

ns

STCK high to STFS (bl) high³

SRCK high to SRFS (bl) high³

STCK high to STFS (bl) low³

SRCK high to SRFS (bl) low³

STCK high to STFS (wl) high³

SRCK high to SRFS (wl) high³

STCK high to STFS (wl) low³

SRCK high to SRFS (wl) low³

STCK high to STXD valid from high impedance

STCK high to STXD high

3.9

-1.5

3.8

-0.8

3.9

-1.5

3.8

-0.8

13.8

2.7

2.8

11.9

–

3

-1.2

2.5

-1.7

4.3

4

5

0.1

-0.8

4.45

-1.5

4.33

-0.8

15.73

3.08

3.19

13.57

–

6

1.48

-1.1

2.51

0.1

7

8

9

10

11a

11b

12

13

14

14.25

0.91

0.57

12.88

21.1

0

STCK high to STXD low

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hold time after SRCK low

–

External Clock Operation (Port C Primary Function²)

15

16

17

STCK/SRCK clock period¹

STCK/SRCK clock high period

STCK/SRCK clock low period

92.8

27.1

61.1

–

81.4

40.7

–

ns

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

87

Functional Description and Application Information

Table 39. SSI (Port C Primary Function) Timing Parameter Table (Continued)

1.8 ꢀ.1 V 3.ꢀ ꢀ.3 V

Minimum Maximum Minimum Maximum

Ref No.

Parameter

Unit

18

19

20

21

22

23

24

25

26

27a

27b

28

29

30

STCK high to STFS (bl) high³

SRCK high to SRFS (bl) high³

STCK high to STFS (bl) low³

SRCK high to SRFS (bl) low³

STCK high to STFS (wl) high³

SRCK high to SRFS (wl) high³

STCK high to STFS (wl) low³

SRCK high to SRFS (wl) low³

STCK high to STXD valid from high impedance

STCK high to STXD high

–

92.8

28.16

18.13

18.24

28.5

–

0

81.4

24.7

15.9

16.0

25.0

–

ns

–

0

–

0

–

0

–

0

–

0

–

0

18.01

8.98

9.12

18.47

1.14

0

15.8

7.0

8.0

16.2

1.0

0

STCK high to STXD low

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hole time after SRCK low

–

Synchronous Internal Clock Operation (Port C Primary Function²)

31

32

SRXD setup before STCK falling

SRXD hold after STCK falling

15.4

0

–

13.5

0

–

ns

Synchronous External Clock Operation (Port C Primary Function²)

33

34

SRXD setup before STCK falling

SRXD hold after STCK falling

1.14

0

–

1.0

0

–

ns

1

2

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B

alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary

function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on

status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary

function.

3

bl = bit length; wl = word length.

MC9328MX1 Technical Data, Rev. 7

88

Freescale Semiconductor

Functional Description and Application Information

Table 4ꢀ. SSI (Port B Alternate Function) Timing Parameter Table

1.8 ꢀ.1 V 3.ꢀ ꢀ.3 V

Minimum Maximum Minimum Maximum

Internal Clock Operation¹(Port B Alternate Function²)

Ref

No.

Parameter

Unit

1

2

3

4

5

6

7

8

9

STCK/SRCK clock period¹

95

1.7

–

83.3

1.5

-0.1

2.7

–

4.2

1.0

4.6

2.0

4.2

1.0

4.6

2.0

14.2

3.0

3.5

12.8

–

ns

STCK high to STFS (bl) high³

SRCK high to SRFS (bl) high³

STCK high to STFS (bl) low³

SRCK high to SRFS (bl) low³

STCK high to STFS (wl) high³

SRCK high to SRFS (wl) high³

STCK high to STFS (wl) low³

SRCK high to SRFS (wl) low³

4.8

-0.1

3.08

1.25

1.71

-0.1

3.08

1.25

14.93

1.25

2.51

12.43

20

1.0

5.24

2.28

4.79

1.0

1.1

1.5

-0.1

2.7

5.24

2.28

16.19

3.42

3.99

14.59

–

1.1

10 STCK high to STXD valid from high impedance

11a STCK high to STXD high

13.1

1.1

11b STCK high to STXD low

2.2

10.9

17.5

0

12 STCK high to STXD high impedance

13 SRXD setup time before SRCK low

14 SRXD hold time after SRCK low

0

–

External Clock Operation (Port B Alternate Function²)

15 STCK/SRCK clock period¹

16 STCK/SRCK clock high period

17 STCK/SRCK clock low period

18 STCK high to STFS (bl) high³

19 SRCK high to SRFS (bl) high³

20 STCK high to STFS (bl) low³

21 SRCK high to SRFS (bl) low³

22 STCK high to STFS (wl) high³

23 SRCK high to SRFS (wl) high³

24 STCK high to STFS (wl) low³

25 SRCK high to SRFS (wl) low³

26 STCK high to STXD valid from high impedance

27a STCK high to STXD high

92.8

27.1

61.1

–

81.4

40.7

0

–

ns

–

92.8

29.07

20.75

21.32

81.4

25.5

18.2

18.7

–

0

–

0

–

0

–

0

–

0

–

0

–

0

18.9

9.23

10.60

16.6

8.1

9.3

27b STCK high to STXD low

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

89

Functional Description and Application Information

Table 4ꢀ. SSI (Port B Alternate Function) Timing Parameter Table (Continued)

1.8 ꢀ.1 V 3.ꢀ ꢀ.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

28 STCK high to STXD high impedance

29 SRXD setup time before SRCK low

30 SRXD hold time after SRCK low

17.90

1.14

0

29.75

15.7

1.0

0

26.1

–

ns

–

Synchronous Internal Clock Operation (Port B Alternate Function²)

31 SRXD setup before STCK falling

32 SRXD hold after STCK falling

18.81

0

–

16.5

0

–

ns

Synchronous External Clock Operation (Port B Alternate Function²)

33 SRXD setup before STCK falling

34 SRXD hold after STCK falling

1.14

0

–

1.0

0

–

ns

1

2

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B

alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary

function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on

FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.

3

bl = bit length; wl = word length.

Table 41. SSI 2 (Port C Alternate Function) Timing Parameter Table

1.8V +/- ꢀ.1ꢀV

Minimum Maximum

Internal Clock Operation¹(Port C Alternate Function)²

3.ꢀV +/- ꢀ.3ꢀV

Ref

No.

Parameter

Unit

Minimum Maximum

1

2

STCK/SRCK clock period¹

95

1.7

–

83.3

1.5

–

ns

STCK high to STFS (bl) high³

SRCK high to SRFS (bl) high³

STCK high to STFS (bl) low³

SRCK high to SRFS (bl) low³

STCK high to STFS (wl) high³

SRCK high to SRFS (wl) high³

STCK high to STFS (wl) low³

SRCK high to SRFS (wl) low³

STCK high to STXD valid from high impedance

4.8

4.2

1.0

4.6

2.0

4.2

1.0

4.6

2.0

14.2

3.0

3

-0.1

3.08

1.25

1.71

-0.1

3.08

1.25

14.93

1.25

1.0

-0.1

2.7

4

5.24

2.28

4.79

1.0

5

1.1

6

1.5

7

-0.1

2.7

8

5.24

2.28

16.19

3.42

9

1.1

10

13.1

1.1

11a STCK high to STXD high

MC9328MX1 Technical Data, Rev. 7

90

Freescale Semiconductor

Functional Description and Application Information

Table 41. SSI 2 (Port C Alternate Function) Timing Parameter Table (Continued)

1.8V +/- ꢀ.1ꢀV 3.ꢀV +/- ꢀ.3ꢀV

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

11b STCK high to STXD low

2.51

12.43

20

3.99

14.59

–

2.2

10.9

17.5

0

3.5

12.8

–

ns

12

13

14

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hold time after SRCK low

0

–

External Clock Operation (Port C Alternate Function)²

15

16

17

18

19

20

21

22

23

24

25

26

STCK/SRCK clock period¹

92.8

27.1

61.1

–

81.4

40.7

0

–

ns

STCK/SRCK clock high period

STCK/SRCK clock low period

STCK high to STFS (bl) high³

SRCK high to SRFS (bl) high³

STCK high to STFS (bl) low³

SRCK high to SRFS (bl) low³

STCK high to STFS (wl) high³

SRCK high to SRFS (wl) high³

STCK high to STFS (wl) low³

SRCK high to SRFS (wl) low³

STCK high to STXD valid from high impedance

–

92.8

29.07

20.75

21.32

29.75

–

81.4

25.5

18.2

18.7

26.1

–

0

–

0

–

0

–

0

–

0

–

0

–

0

18.9

9.23

10.60

17.90

1.14

0

16.6

8.1

9.3

15.7

1.0

0

27a STCK high to STXD high

27b STCK high to STXD low

28

29

30

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hole time after SRCK low

–

Synchronous Internal Clock Operation (Port C Alternate Function)²

31

32

SRXD setup before STCK falling

SRXD hold after STCK falling

18.81

0

–

16.5

0

–

ns

Synchronous External Clock Operation (Port C Alternate Function)²

33

34

SRXD setup before STCK falling

SRXD hold after STCK falling

1.14

0

–

1.0

0

–

ns

1

All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted

frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid

by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

91

Functional Description and Application Information

2

There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 – PC24). When SSI signals

are configured as outputs, they can be viewed at Port C alternate function a. When SSI signals are configured as inputs, the

SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input is selected

from Port C alternate function.

3

bl = bit length; wl = word length

4.17 CMOS Sensor Interface

The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,

a control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive

FIFO, and a 16 × 32 statistic data FIFO.

4.17.1 Gated Clock Mode

Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge

and the CSI is programmed to received data on the positive edge. Figure 69 shows the timing diagram

when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received

data in negative edge. The parameters for the timing diagrams are listed in Table 42.

1

VSYNC

7

HSYNC

5

6

2

PIXCLK

Valid Data

DATA[7:0]

3

4

Figure 68. Sensor Output Data on Pixel Clock Falling Edge

CSI Latches Data on Pixel Clock Rising Edge

MC9328MX1 Technical Data, Rev. 7

92

Freescale Semiconductor

Functional Description and Application Information

1

VSYNC

HSYNC

7

6

5

2

PIXCLK

Valid Data

DATA[7:0]

3

4

Figure 69. Sensor Output Data on Pixel Clock Rising Edge

CSI Latches Data on Pixel Clock Falling Edge

Table 42. Gated Clock Mode Timing Parameters

Ref No.

Parameter

Min

Max

Unit

1

2

3

4

5

6

7

csi_vsync to csi_hsync

csi_hsync to csi_pixclk

csi_d setup time

180

–

ns

1

–

ns

csi_d hold time

1

–

ns

csi_pixclk high time

csi_pixclk low time

csi_pixclk frequency

10.42

0

–

ns

–

ns

48

MHz

The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold

time and setup time, according to:

Rising-edge latch data

max rise time allowed = (positive duty cycle - hold time)

max fall time allowed = (negative duty cycle - setup time)

In most of case, duty cycle is 50 / 50, therefore

max rise time = (period / 2 - hold time)

max fall time = (period / 2 - setup time)

For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.

positive duty cycle = 10 / 2 = 5ns

=> max rise time allowed = 5 - 1 = 4ns

negative duty cycle = 10 / 2 = 5ns

=> max fall time allowed = 5 - 1 = 4ns

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

93

Functional Description and Application Information

Falling-edge latch data

max fall time allowed = (negative duty cycle - hold time)

max rise time allowed = (positive duty cycle - setup time)

4.17.2 Non-Gated Clock Mode

Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge

and the CSI is programmed to received data on the positive edge. Figure 71 shows the timing diagram

when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received

data in negative edge. The parameters for the timing diagrams are listed in Table 43.

1

VSYNC

6

4

5

PIXCLK

Valid Data

DATA[7:0]

2

3

Figure 7ꢀ. Sensor Output Data on Pixel Clock Falling Edge

CSI Latches Data on Pixel Clock Rising Edge

1

VSYNC

6

4

5

PIXCLK

Valid Data

DATA[7:0]

2

3

Figure 71. Sensor Output Data on Pixel Clock Rising Edge

CSI Latches Data on Pixel Clock Falling Edge

Table 43. Non-Gated Clock Mode Parameters

Ref No.

Parameter

Min

Max

Unit

1

2

csi_vsync to csi_pixclk

csi_d setup time

180

1

–

ns

MC9328MX1 Technical Data, Rev. 7

94

Freescale Semiconductor

Functional Description and Application Information

Table 43. Non-Gated Clock Mode Parameters (Continued)

Ref No.

Parameter

csi_d hold time

Min

Max

Unit

3

4

5

6

1

–

ns

csi_pixclk high time

csi_pixclk low time

csi_pixclk frequency

10.42

0

–

ns

48

MHz

The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold

time and setup time, according to:

max rise time allowed = (positive duty cycle - hold time)

max fall time allowed = (negative duty cycle - setup time)

In most of case, duty cycle is 50 / 50, therefore:

max rise time = (period / 2 - hold time)

max fall time = (period / 2 - setup time)

For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.

positive duty cycle = 10 / 2 = 5ns

=> max rise time allowed = 5 - 1 = 4ns

negative duty cycle = 10 / 2 = 5ns

=> max fall time allowed = 5 - 1 = 4ns

Falling-edge latch data

max fall time allowed = (negative duty cycle - hold time)

max rise time allowed = (positive duty cycle - setup time)

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

95

Pin-Out and Package Information

5.1

MAPBGA 256 Package Dimensions

Figure 72 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, with an 0.8 mm pad pitch.

The device designator for the MAPBGA package is VH.

Case Outline 1367

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.

3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.

Figure 72. i.MXL 256 MAPBGA Mechanical Drawing

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

97

Product Documentation

6 Product Documentation

6.1

Revision History

Table 45 provides revision history for this release. This history includes technical content revisions only

and not stylistic or grammatical changes.

Table 45. i.MX1 Data Sheet Revision History Rev. 7

Location

Table 1 on page 3

Revision

• Added the DMA_REQ signal to table.

Signal Names and

Descriptions

• Corrected signal name from USBD_OE to USBD_ROE

• Corrected signal names

From: C10 BTRFGN, To: BTRFGND

From: G6 SIM_RST, To: SIM_RX

From: G7 UART2_TXD, To: SIM_CLK

Table 3 on page 11

Signal Multiplex Table i.MX1

Added Signal Multiplex table from Reference Manual with the following changes:

• Changed I/O Supply Voltage, PB31–14, from NVDD3 to NVDD4

• Corrected footnotes 1–5.

• Changed AVDD2 references to QVDD, except for C14. Added footnote regarding ESD.

• Changed occurrence of SD_SCLK to SD_CLK.

• Removed 69K pull-up resistor from EB1, EB2, and added to D9

Table 10 on page 26

Table 3 on page 11

Changed first and second parameters descriptions:

From: Reference Clock freq range, To: DPLL input clock freq range

From: Double clock freq range, To: DPLL output freq range

Added Signal Multiplex table.

6.2

Reference Documents

The following documents are required for a complete description of the MC9328MX1 and are necessary

to design properly with the device. Especially for those not familiar with the ARM920T processor or

previous i.MX processor products, the following documents are helpful when used in conjunction with this

document.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)

ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)

MC9328MX1 Product Brief (order number MC9328MX1P)

MC9328MX1 Reference Manual (order number MC9328MX1RM)

The Freescale manuals are available on the Freescale Semiconductors Web site at

http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web

site, or printed versions may be ordered. The ARM Ltd. documentation is available from

http://www.arm.com.

MC9328MX1 Technical Data, Rev. 7

98

Freescale Semiconductor

NOTES

MC9328MX1 Technical Data, Rev. 7

Freescale Semiconductor

99

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Document Number: MC9328MX1

Rev. 7

12/2006


型号：	MC9328MX1VM15
厂家：	NXP
描述：	32-BIT, 150MHz, RISC PROCESSOR, PBGA256, 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256 时钟外围集成电路
文件：	总100页 (文件大小：1119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC9328MX1VM15 [NXP]

相关型号：

MC9328MX1VM15R2

MC9328MX1VM20

MC9328MX1VM20

MC9328MX1VM20

MC9328MX1VM20R2

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MC9328MX21

MC9328MX21

MC9328MX21CJM

MC9328MX21CVG

MC9328MX21CVH

MC9328MX21CVK