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MC9328MXSVF10R2 [NXP]

32-BIT, 100MHz, MICROPROCESSOR, PBGA225, 13 X 13 MM, PLASTIC, BGA-225;
MC9328MXSVF10R2
型号： MC9328MXSVF10R2
厂家： NXP    NXP
描述：

32-BIT, 100MHz, MICROPROCESSOR, PBGA225, 13 X 13 MM, PLASTIC, BGA-225

时钟 外围集成电路
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MC9328MXS/D  
Rev. 0, 1/2005  
Freescale Semiconductor  
Advance Information  
MC9328MXS  
Package Information  
Plastic Package  
(PBGA–225)  
MC9328MXS  
Ordering Information  
See Table 2 on page 4  
Contents  
1 Introduction  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Signals and Connections . . . . . . . . . . . . . . . . . . . .5  
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Pin-Out and Package Information . . . . . . . . . . . .69  
Contact Information . . . . . . . . . . . . . . . . . Last Page  
The i.MX (Media Extensions) series provides a leap in  
performance with an ARM9™ microprocessor core and  
highly integrated system functions. The i.MX products  
specifically address the requirements of the personal,  
portable product market by providing intelligent integrated  
peripherals, an advanced processor core, and power  
management capabilities.  
The i.MX processor features the advanced and power-  
efficient ARM920T™ core that operates at speeds up to  
100 MHz. Integrated modules, which include a USB device  
and an LCD controller, support a suite of peripherals to  
enhance portable products. It is packaged in a 225-contact  
PBGA package. Figure 1 shows the functional block diagram  
of the i.MX processor.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  
This document contains information on a new product. Specifications and information herein are  
subject to change without notice.  
Introduction  
Figure 1. MC9328MXS Functional Block Diagram  
1.1 Conventions  
This document uses the following conventions:  
•
•
•
•
•
•
•
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.  
Logic level one is a voltage that corresponds to Boolean true (1) state.  
Logic level zero is a voltage that corresponds to Boolean false (0) state.  
To set a bit or bits means to establish logic level one.  
To clear a bit or bits means to establish logic level zero.  
A signal is an electronic construct whose state conveys or changes in state convey information.  
A pin is an external physical connection. The same pin can be used to connect a number of signals.  
Asserted means that a discrete signal is in active logic state.  
— Active low signals change from logic level one to logic level zero.  
— Active high signals change from logic level zero to logic level one.  
Negated means that an asserted discrete signal changes logic state.  
— Active low signals change from logic level zero to logic level one.  
— Active high signals change from logic level one to logic level zero.  
•
•
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and  
high bytes or words are spelled out.  
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are  
hexadecimal.  
MC9328MXS Advance Information, Rev. 0  
2
Freescale Semiconductor  
Introduction  
1.2 Features  
To support a wide variety of applications, the i.MX processor offers a robust array of features, including the  
following:  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM920T™ Microprocessor Core  
AHB to IP Bus Interfaces (AIPIs)  
External Interface Module (EIM)  
SDRAM Controller (SDRAMC)  
DPLL Clock and Power Control Module  
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)  
Serial Peripheral Interface (SPI)  
Two General-Purpose 32-bit Counters/Timers  
Watchdog Timer  
Real-Time Clock/Sampling Timer (RTC)  
LCD Controller (LCDC)  
Pulse-Width Modulation (PWM) Module  
Universal Serial Bus (USB) Device  
Direct Memory Access Controller (DMAC)  
•
Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module  
•
•
•
•
•
•
Inter-IC (I2C) Bus Module  
General-Purpose I/O (GPIO) Ports  
Bootstrap Mode  
Power Management Features  
Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O  
225-contact PBGA Package  
1.3 Target Applications  
The i.MX processor is targeted for advanced information appliances, smart phones, Web browsers, and messaging  
applications.  
1.4 Revision History  
Table 1 provides revision history for this release. This history includes technical content revisions only and not  
stylistic or grammatical changes.  
Table 1. MC9328MXS Data Sheet Revision History for Rev. 0  
Revision  
Initial Release  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
3
Introduction  
1.5 Reference Documents  
The following documents are required for a complete description of the MC9328MXS and are necessary to design  
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall  
products, the following documents are helpful when used in conjunction with this document.  
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)  
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)  
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)  
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)  
MC9328MXS Product Brief (order number MC9328MXSP/D)  
MC9328MXS Reference Manual (order number MC9328MXSRM/D)  
The Freescale manuals are available on the Freescale Semiconductors Web site at  
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or  
printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.  
1.6 Ordering Information  
Table 2 provides ordering information for the 225-contact PBGA package.  
Table 2. MC9328MXS Ordering Information  
Package Type  
Frequency  
Temperature  
Solderball Type  
Order Number  
-40OC to 85OC  
225-contact PBGA  
100 MHz  
Standard  
Pb-free  
MC9328MXSCVF10(R2)  
See Note1  
0OC to 70OC  
Standard  
Pb-free  
MC9328MXSVF10(R2)  
See Note1  
1. Contact your distribution center or Freescale sales office.  
MC9328MXS Advance Information, Rev. 0  
4
Freescale Semiconductor  
Signals and Connections  
2 Signals and Connections  
Table 3 identifies and describes the i.MX processor signals that are assigned to package pins. The signals are  
grouped by the internal module that they are connected to.  
Table 3. MC9328MXS Signal Descriptions  
Signal Name  
Function/Notes  
External Bus/Chip-Select (EIM)  
A[24:0]  
Address bus signals  
Data bus signals  
D[31:0]  
EB0  
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].  
Byte Strobe—Active low external enable byte signal that controls D [23:16].  
Byte Strobe—Active low external enable byte signal that controls D [15:8].  
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].  
Memory Output Enable—Active low output enables external data bus.  
EB1  
EB2  
EB3  
OE  
CS [5:0]  
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the  
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.  
ECB  
LBA  
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an  
on-going burst sequence and initiate a new (long first access) burst sequence.  
Active low signal sent by a flash device causing the external burst device to latch the starting burst  
address.  
BCLK (burst clock)  
RW  
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.  
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE  
input signal by external DRAM.  
DTACK  
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal  
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is  
not terminated by the external DTACK signal after 1022 clock counts have elapsed.  
Bootstrap  
BOOT [3:0]  
System Boot Mode Select—The operational system boot mode of the i.MX processor upon system  
reset is determined by the settings of these pins.  
SDRAM Controller  
SDBA [4:0]  
SDIBA [3:0]  
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These  
signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles.  
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These  
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.  
MA [11:10]  
MA [9:0]  
SDRAM address signals  
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected  
on SDRAM cycles.  
DQM [3:0]  
CSD0  
SDRAM data enable  
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are  
selectable by programming the system control register.  
CSD1  
RAS  
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by  
programming the system control register. By default, CSD1 is selected, so it can be used as boot  
chip-select by properly configuring BOOT [3:0] input pins.  
SDRAM Row Address Select signal  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
5
Signals and Connections  
Signal Name  
Table 3. MC9328MXS Signal Descriptions (Continued)  
Function/Notes  
CAS  
SDRAM Column Address Select signal  
SDRAM Write Enable signal  
SDRAM Clock Enable 0  
SDRAM Clock Enable 1  
SDRAM Clock  
SDWE  
SDCKE0  
SDCKE1  
SDCLK  
RESET_SF  
Not Used  
Clocks and Resets  
EXTAL16M  
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is  
shut down.  
XTAL16M  
EXTAL32K  
XTAL32K  
CLKO  
Crystal output  
32 kHz crystal input  
32 kHz crystal output  
Clock Out signal selected from internal clock signals.  
RESET_IN  
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all  
modules (except the reset module and the clock control module) are reset.  
RESET_OUT  
POR  
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from  
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.  
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally  
generated by an external RC circuit designed to detect a power-up event.  
JTAG  
TRST  
TDO  
TDI  
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.  
Serial Output for test instructions and data. Changes on the falling edge of TCK.  
Serial Input for test instructions and data. Sampled on the rising edge of TCK.  
Test Clock to synchronize test logic and control register access through the JTAG port.  
TCK  
TMS  
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge  
of TCK.  
DMA  
BIG_ENDIAN  
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is  
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is  
driven logic-low at reset, the external chip-select space will be configured to big endian.  
DMA_REQ  
External DMA request pin.  
ETM  
ETMTRACESYNC  
ETMTRACECLK  
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.  
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.  
ETMPIPESTAT [2:0]  
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM  
mode.  
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].  
ETMTRACEPKT [7:0] are selected in ETM mode.  
LCD Controller  
LD [15:0]  
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.  
MC9328MXS Advance Information, Rev. 0  
6
Freescale Semiconductor  
Signals and Connections  
Table 3. MC9328MXS Signal Descriptions (Continued)  
Function/Notes  
Signal Name  
FLM/VSYNC  
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate  
driver (dedicated signal SPS for Sharp panel HR-TFT).  
LP/HSYNC  
LSCLK  
Line pulse or H sync  
Shift clock  
ACD/OE  
CONTRAST  
SPL_SPR  
PS  
Alternate crystal direction/output enable.  
This signal is used to control the LCD bias voltage as contrast control.  
Program horizontal scan direction (Sharp panel dedicated signal).  
Control signal output for source driver (Sharp panel dedicated signal).  
CLS  
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated  
signal).  
REV  
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).  
SPI 1  
Master Out/Slave In  
SPI1_MOSI  
SPI1_MISO  
SPI1_SS  
Slave In/Master Out  
Slave Select (Selectable polarity)  
Serial Clock  
SPI1_SCLK  
SPI1_SPI_RDY  
Serial Data Ready  
General Purpose Timers  
TIN  
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers  
simultaneously.  
TMR2OUT  
Timer 2 Output  
USB Device  
USBD_VMO  
USBD_VPO  
USBD_VM  
USB Minus Output  
USB Plus Output  
USB Minus Input  
USB Plus Input  
USBD_VP  
USBD_SUSPND  
USBD_RCV  
USBD_OE  
USB Suspend Output  
USB Receive Data  
USB OE  
USBD_AFE  
USB Analog Front End Enable  
UARTs – IrDA/Auto-Bauding  
Receive Data  
UART1_RXD  
UART1_TXD  
UART1_RTS  
UART1_CTS  
UART2_RXD  
UART2_TXD  
UART2_RTS  
UART2_CTS  
UART2_DSR  
Transmit Data  
Request to Send  
Clear to Send  
Receive Data  
Transmit Data  
Request to Send  
Clear to Send  
Data Set Ready  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
7
Signals and Connections  
Signal Name  
Table 3. MC9328MXS Signal Descriptions (Continued)  
Function/Notes  
UART2_RI  
Ring Indicator  
Data Carrier Detect  
Data Terminal Ready  
Serial Audio Port – SSI (configurable to I2S protocol)  
UART2_DCD  
UART2_DTR  
SSI_TXDAT  
SSI_RXDAT  
SSI_TXCLK  
SSI_RXCLK  
SSI_TXFS  
Transmit Data  
Receive Data  
Transmit Serial Clock  
Receive Serial Clock  
Transmit Frame Sync  
Receive Frame Sync  
SSI_RXFS  
I2C  
I2C_SCL  
I2C_SDA  
I2C Clock  
I2C Data  
PWM  
PWMO  
PWM Output  
Test Function  
TRISTATE  
Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input  
with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National  
Semiconductor.)  
General Purpose Input/Output  
PA[14:3]  
PB[13:8]  
Dedicated GPIO  
Dedicated GPIO  
Digital Supply Pins  
NVDD  
NVSS  
Digital Supply for the I/O pins  
Digital Ground for the I/O pins  
Supply Pins – Analog Modules  
AVDD  
AVSS  
Supply for analog blocks  
Quiet ground for analog blocks  
Internal Power Supply  
QVDD  
QVSS  
Power supply pins for silicon internal circuitry  
Ground pins for silicon internal circuitry  
Substrate Supply Pins  
SVDD  
SGND  
Supply routed through substrate of package; not to be bonded  
Ground routed through substrate of package; not to be bonded  
MC9328MXS Advance Information, Rev. 0  
8
Freescale Semiconductor  
Specifications  
3 Specifications  
This section contains the electrical specifications and timing diagrams for the i.MX processor.  
3.1 Maximum Ratings  
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may  
occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on  
page 9 or the DC Characteristics table.  
Table 4. Maximum Ratings  
Symbol  
Rating  
Minimum  
Maximum  
Unit  
NVDD  
QVDD  
DC I/O Supply Voltage  
-0.3  
-0.3  
-0.3  
-0.3  
–
3.3  
1.9  
V
V
DC Internal (core = 100 MHz) Supply Voltage  
DC Analog Supply Voltage  
AVDD  
3.3  
V
BTRFVDD  
VESD_HBM  
VESD_MM  
ILatchup  
Test  
DC Bluetooth Supply Voltage  
ESD immunity with HBM (human body model)  
ESD immunity with MM (machine model)  
Latch-up immunity  
3.3  
V
2000  
100  
200  
150  
V
–
V
–
mA  
°C  
mW  
Storage temperature  
-55  
8001  
13002  
Pmax  
Power Consumption  
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches  
from the ARM® core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.  
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches  
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core  
running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at  
1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,  
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.  
3.2 Recommended Operating Range  
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MX processor  
has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal  
logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides  
power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.  
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the  
AVDD pins from other VDD pins.  
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5.  
Table 5. Recommended Operating Range  
Symbol  
Rating  
Minimum Maximum  
70  
Unit  
TA  
Operating temperature range  
MC9328MXSVF10  
0
°C  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
9
Specifications  
Table 5. Recommended Operating Range (Continued)  
Rating Minimum Maximum  
Symbol  
Unit  
TA  
Operating temperature range  
MC9328MXSCVF10  
-40  
85  
°C  
NVDD  
I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V  
interfaces)  
2.70  
3.30  
V
NVDD  
QVDD  
AVDD  
I/O supply voltage (if not using the peripherals listed above)  
Internal supply voltage (Core = 100 MHz)  
Analog supply voltage  
1.70  
1.70  
1.70  
3.30  
1.90  
3.30  
V
V
V
3.3 Power Sequence Requirements  
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of  
application note AN2537 on the i.MX application processor website.  
3.4 DC Electrical Characteristics  
Table 6 contains both maximum and minimum DC characteristics of the i.MX processor.  
Table 6. Maximum and Minimum DC Characteristics  
Number or  
Symbol  
Parameter  
Min  
Typical  
Max  
Unit  
Iop  
Full running operating current at 1.8V for QVDD, 3.3V for  
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving  
TFT display panel, and OS with MMU enabled memory  
system is running on external SDRAM).  
–
QVDD at  
–
mA  
1.8V = 120mA;  
NVDD+AVDD at  
3.0V = 30mA  
Sidd1  
Sidd2  
Sidd3  
Sidd4  
Standby current  
(Core = 100 MHz, QVDD = 1.8V, temp = 25°C)  
–
–
–
–
25  
45  
35  
60  
–
–
–
–
µA  
µA  
µA  
µA  
Standby current  
(Core = 100 MHz, QVDD = 1.8V, temp = 55°C)  
Standby current  
(Core = 100 MHz, QVDD = 1.9V, temp = 25°C)  
Standby current  
(Core = 100 MHz, QVDD = 1.9V, temp = 55°C)  
V
Input high voltage  
0.7V  
–
–
–
–
–
Vdd+0.2  
0.4  
V
V
IH  
DD  
V
Input low voltage  
–
0.7V  
–
IL  
V
Output high voltage (I  
= 2.0 mA)  
Vdd  
0.4  
V
OH  
OH  
DD  
V
Output low voltage (I = -2.5 mA)  
OL  
V
OL  
IL  
I
Input low leakage current  
–
1
µA  
(V = GND, no pull-up or pull-down)  
IN  
MC9328MXS Advance Information, Rev. 0  
10  
Freescale Semiconductor  
Specifications  
Table 6. Maximum and Minimum DC Characteristics (Continued)  
Number or  
Symbol  
Parameter  
Min  
Typical  
Max  
Unit  
I
Input high leakage current  
(V = V , no pull-up or pull-down)  
–
–
1
µA  
IH  
IN  
DD  
I
Output high current  
(V = 0.8VDD, VDD = 1.8V)  
–
-4.0  
–
–
–
–
4.0  
–
mA  
mA  
µA  
OH  
OH  
I
Output low current  
OL  
OZ  
(V = 0.4V, VDD = 1.8V)  
OL  
I
Output leakage current  
5
(V = V , output is high impedence)  
out  
DD  
C
Input capacitance  
Output capacitance  
–
–
–
–
5
5
pF  
pF  
i
C
o
3.5 AC Electrical Characteristics  
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are  
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system  
operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage  
from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading.  
Table 7. Tristate Signal Timing  
Pin  
Parameter  
Minimum  
Maximum  
Unit  
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z  
–
20.8  
ns  
Table 8. 32k/16M Oscillator Signal Timing  
Parameter  
Minimum  
RMS  
Maximum  
Unit  
EXTAL32k input jitter (peak to peak)  
EXTAL32k startup time  
–
800  
–
5
–
20  
–
ns  
ms  
–
EXTAL16M input jitter (peak to peak) 1  
EXTAL16M startup time 1  
TBD  
–
TBD  
–
TBD  
–
1. The 16 MHz oscillator is not recommended for use in new designs.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
11  
Specifications  
3.6 Embedded Trace Macrocell  
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the  
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift  
register comprised of the following:  
•
•
•
32-bit data field  
7-bit address field  
A read/write bit  
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,  
and a 1 into the read/write bit.  
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field  
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing  
diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2.  
2a  
1
2b  
3a  
TRACECLK  
3b  
TRACECLK  
(Half-Rate Clocking Mode)  
Output Trace Port  
Valid Data  
Valid Data  
4a  
Figure 2. Trace Port Timing Diagram  
Table 9. Trace Port Timing Diagram Parameter Table  
1.8 0.1 ꢀ 3.0 0.3 ꢀ  
4b  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
1
CLK frequency  
0
1.3  
3
85  
–
0
2
2
–
–
2
3
100  
–
MHz  
ns  
2a  
2b  
3a  
3b  
4a  
4b  
Clock high time  
Clock low time  
Clock rise time  
Clock fall time  
–
–
ns  
–
4
3
ns  
–
3
3
ns  
Output hold time  
Output setup time  
2.28  
3.42  
–
–
ns  
–
–
ns  
MC9328MXS Advance Information, Rev. 0  
12  
Freescale Semiconductor  
Specifications  
3.7 DPLL Timing Specifications  
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the pre-divider  
and Tdck is the output double clock period.  
Table 10. DPLL Specifications  
Parameter  
Test Conditions  
Minimum Typical Maximum  
Unit  
Reference clock freq range  
Vcc = 1.8V  
Vcc = 1.8V  
5
5
–
–
100  
30  
MHz  
MHz  
Pre-divider output clock  
freq range  
Double clock freq range  
Pre-divider factor (PD)  
Vcc = 1.8V  
–
80  
1
–
–
–
–
–
–
–
220  
16  
MHz  
–
Total multiplication factor (MF) Includes both integer and fractional parts  
5
15  
–
MF integer part  
–
5
15  
–
MF numerator  
Should be less than the denominator  
0
1022  
1023  
312.5  
300  
–
MF denominator  
Pre-multiplier lock-in time  
–
–
1
–
–
µsec  
Tref  
Freq lock-in time after  
full reset  
FOL mode for non-integer MF  
(does not include pre-multi lock-in time)  
250  
280  
(56 µs)  
Freq lock-in time after  
partial reset  
FOL mode for non-integer MF (does not  
include pre-multi lock-in time)  
220  
300  
270  
–
250  
(50 µs)  
270  
400  
370  
0.01  
1.5  
Tref  
Phase lock-in time after  
full reset  
FPL mode and integer MF (does not  
include pre-multi lock-in time)  
350  
(70 µs)  
Tref  
Phase lock-in time after  
partial reset  
FPL mode and integer MF (does not  
include pre-multi lock-in time)  
320  
(64 µs)  
Tref  
Freq jitter (p-p)  
–
0.005  
(0.01%)  
2•Tdck  
ns  
Phase jitter (p-p)  
Integer MF, FPL mode, Vcc=1.8V  
–
1.0  
(10%)  
Power supply voltage  
Power dissipation  
–
1.7  
–
–
–
2.5  
4
V
FOL mode, integer MF,  
mW  
f
dck = 100 MHz, Vcc = 1.8V  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
13  
Specifications  
3.8 Reset Module  
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.  
NOTE:  
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up  
to prevent forward biasing.  
90% AVDD  
1
10% AVDD  
POR  
2
RESET_POR  
Exact 300ms  
3
7 cycles @ CLK32  
RESET_DRAM  
4
14 cycles @ CLK32  
HRESET  
RESET_OUT  
CLK32  
HCLK  
Figure 3. Timing Relationship with POR  
MC9328MXS Advance Information, Rev. 0  
14  
Freescale Semiconductor  
Specifications  
5
RESET_IN  
14 cycles @ CLK32  
HRESET  
4
RESET_OUT  
6
CLK32  
HCLK  
Figure 4. Timing Relationship with RESET_IN  
Table 11. Reset Module Timing Parameter Table  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Min Max  
Ref  
No.  
Parameter  
Unit  
Min  
Max  
–
note1  
300  
note1  
300  
1
2
Width of input POWER_ON_RESET  
–
–
Width of internal POWER_ON_RESET  
(CLK32 at 32 kHz)  
300  
300  
ms  
3
4
5
6
7K to 32K-cycle stretcher for SDRAM reset  
7
14  
4
7
14  
–
7
14  
4
7
14  
–
Cycles of  
CLK32  
14K to 32K-cycle stretcher for internal system reset  
HRESERT and output reset at pin RESET_OUT  
Cycles of  
CLK32  
Width of external hard-reset RESET_IN  
Cycles of  
CLK32  
4K to 32K-cycle qualifier  
4
4
4
4
Cycles of  
CLK32  
1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for  
crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of  
supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of  
start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.  
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored  
in calculating timing for the start-up process.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
15  
Specifications  
3.9 External Interface Module  
The External Interface Module (EIM) handles the interface to devices external to the i.MX processor, including the  
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in  
Figure 5, and Table 12 on page 16 defines the parameters of signals.  
(HCLK) Bus Clock  
1a  
2a  
3a  
1b  
2b  
3b  
Address  
Chip-select  
Read (Write)  
4a  
5a  
4b  
5b  
OE (rising edge)  
4c  
5c  
4d  
OE (falling edge)  
EB (rising edge)  
EB (falling edge)  
5d  
6b  
6a  
6a  
LBA (negated falling edge)  
LBA (negated rising edge)  
6c  
7a  
7b  
BCLK (burst clock) - rising edge  
7c  
7d  
BCLK (burst clock) - falling edge  
Read Data  
8b  
9a  
9a  
8a  
9b  
Write Data (negated falling)  
9c  
Write Data (negated rising)  
DTACK_B  
10a  
10a  
Figure 5. EIM Bus Timing Diagram  
Table 12. EIM Bus Timing Parameter Table  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Ref No.  
Parameter  
Unit  
Min  
Typical Max  
Min  
Typical Max  
1a  
1b  
Clock fall to address valid  
Clock fall to address invalid  
2.48  
1.55  
3.31  
2.48  
9.11  
5.69  
2.4  
1.5  
3.2  
2.4  
8.8  
5.5  
ns  
ns  
MC9328MXS Advance Information, Rev. 0  
16  
Freescale Semiconductor  
Specifications  
Unit  
Table 12. EIM Bus Timing Parameter Table (Continued)  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Typical Max  
Ref No.  
Parameter  
Min  
Typical Max  
Min  
2a  
2b  
3a  
3b  
4a  
4b  
4c  
4d  
5a  
5b  
5c  
5d  
6a  
6b  
6c  
7a  
7b  
7c  
7d  
8a  
8b  
9a  
9b  
9c  
10a  
Clock fall to chip-select valid  
2.69  
1.55  
1.35  
1.86  
2.32  
2.11  
2.38  
2.17  
1.91  
1.81  
1.97  
1.76  
2.07  
1.97  
1.91  
1.61  
1.61  
1.55  
1.55  
5.54  
0
3.31  
2.48  
2.79  
2.59  
2.62  
2.52  
2.69  
2.59  
2.52  
2.42  
2.59  
2.48  
2.79  
2.79  
2.62  
2.62  
2.62  
2.48  
2.59  
–
7.87  
6.31  
6.52  
6.11  
6.85  
6.55  
7.04  
6.73  
5.54  
5.24  
5.69  
5.38  
6.73  
6.83  
6.45  
5.64  
5.84  
5.59  
5.80  
–
2.6  
1.5  
1.3  
1.8  
2.3  
2.1  
2.3  
2.1  
1.9  
1.8  
1.9  
1.7  
2.0  
1.9  
1.9  
1.6  
1.6  
1.5  
1.5  
5.5  
0
3.2  
2.4  
2.7  
2.5  
2.6  
2.5  
2.6  
2.5  
2.5  
2.4  
2.5  
2.4  
2.7  
2.7  
2.6  
2.6  
2.6  
2.4  
2.5  
–
7.6  
6.1  
6.3  
5.9  
6.8  
6.5  
6.8  
6.5  
5.5  
5.2  
5.5  
5.2  
6.5  
6.6  
6.4  
5.6  
5.8  
5.4  
5.6  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock fall to chip-select invalid  
Clock fall to Read (Write) Valid  
Clock fall to Read (Write) Invalid  
Clock1 rise to Output Enable Valid  
Clock1 rise to Output Enable Invalid  
Clock1 fall to Output Enable Valid  
Clock1 fall to Output Enable Invalid  
Clock1 rise to Enable Bytes Valid  
Clock1 rise to Enable Bytes Invalid  
Clock1 fall to Enable Bytes Valid  
Clock1 fall to Enable Bytes Invalid  
Clock1 fall to Load Burst Address Valid  
Clock1 fall to Load Burst Address Invalid  
Clock1 rise to Load Burst Address Invalid  
Clock1 rise to Burst Clock rise  
Clock1rise to Burst Clock fall  
Clock1 fall to Burst Clock rise  
Clock1 fall to Burst Clock fall  
Read Data setup time  
Read Data hold time  
–
–
–
–
Clock1 rise to Write Data Valid  
Clock1 fall to Write Data Invalid  
Clock1 rise to Write Data Invalid  
DTACK setup time  
1.81  
1.45  
1.63  
2.52  
2.72  
2.48  
–
6.85  
5.69  
–
1.8  
1.4  
1.62  
2.5  
2.7  
2.4  
–
6.8  
5.5  
–
–
–
–
–
1. Clock refers to the system clock signal, HCLK, generated from the System DPLL  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
17  
Specifications  
3.9.1 DTACK Signal Description  
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a  
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the  
external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal  
function when the external DTACK signal is used for data acknowledgement.  
3.9.2 DTACK Signal Timing  
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of  
measure for this figure are found in the associated tables.  
MC9328MXS Advance Information, Rev. 0  
18  
Freescale Semiconductor  
Specifications  
3.9.2.1 DTACK Read Cycle without DMA  
3
Address  
2
8
CS5  
1
9
programmable  
min 0ns  
EB  
OE  
5
4
DTACK  
10  
6
DATABUS  
(input to i.MX)  
7
Figure 6. DTACK Read Cycle without DMA  
Table 13. Read Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
OE and EB assertion time  
See note 3  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS5 pulse width  
3T  
–
–
3
OE negated to address inactive  
DTACK asserted after CS5 asserted  
DTACK asserted to OE negated  
Data hold timing after OE negated  
Data ready after DTACK asserted  
OE negated to CS negated  
OE negated after EB negated  
DTACK pulse width  
46.39  
4
–
1019T  
4T+6.6  
–
5
3T+1.83  
6
0
0
7
T
8
0.5T-0.68  
0.06  
1T  
0.5T-0.06  
0.18  
3T  
9
10  
Note:  
1. DTACK asserted means DTACK becomes low level.  
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when  
EBC bit in CS5L register is clear.  
4. Address becomes valid and CS asserts at the start of read access cycle.  
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
19  
Specifications  
3.9.2.2 DTACK Read Cycle DMA Enabled  
4
Address  
2
9
CS5  
1
10  
programmable  
min 0ns  
EB  
3
6
OE  
(logic high)  
DTACK  
RW  
5
7
11  
DATABUS  
(input to i.MX)  
8
Figure 7. DTACK Read Cycle DMA Enabled  
Table 14. Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
OE and EB assertion time  
See note 3  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS pulse width  
3T  
–
0.5T-0.06  
0.3  
3
OE negated before CS5 is negated  
Address inactive before CS negated  
DTACK asserted after CS5 asserted  
DTACK asserted to OE negated  
Data hold timing after OE negated  
Data ready after DTACK is asserted  
CS deactive to next CS active  
OE negate after EB negate  
DTACK pulse width  
0.5T-0.68  
4
–
5
–
1019T  
4T+6.6  
–
6
3T+1.83  
7
0
–
8
T
9
T
–
10  
11  
0.06  
1T  
0.18  
3T  
Note:  
1. DTACK asserted means DTACK becomes low level.  
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when  
EBC bit in CS5L register is clear.  
4. Address becomes valid and CS asserts at the start of read access cycle.  
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
20  
Freescale Semiconductor  
Specifications  
3.9.2.3 DTACK Write Cycle without DMA  
5
Address  
3
1
programmable  
min 0ns  
CS5  
2
10  
programmable  
min 0ns  
EB  
4
RW  
7
(logic high)  
DTACK  
OE  
6
8
11  
9
Databus  
(input to i.MX)  
Figure 8. DTACK Write Cycle without DMA  
Table 15. Write Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
CS5 assertion time  
See note 3  
See note 3  
3T  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
EB assertion time  
–
3
CS5 pulse width  
–
1.5T-0.8  
–
4
RW negated before CS5 is negated  
RW negated to address inactive  
DTACK asserted after CS5 asserted  
DTACK asserted to RW negated  
Data hold timing after RW negated  
Data ready after CS5 is asserted  
EB negated after CS5 is negated  
DTACK pulse width  
1.5T-2.44  
57.31  
–
5
6
1019T  
3T+6.6  
–
7
8
2T+2.37  
1.5T-3.99  
–
9
T
10  
0.5T  
0.5T+0.5  
3T  
11  
1T  
Note:  
1. DTACK asserted means DTACK becomes low level.  
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
3. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.  
4. Address becomes valid and RW asserts at the start of write access cycle.  
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
21  
Specifications  
3.9.2.4 DTACK Write Cycle DMA Enabled  
5
Address  
3
1
10  
programmable  
min 0ns  
CS5  
2
11  
programmable  
min 0ns  
EB  
4
7
RW  
(logic high)  
DTACK  
OE  
6
8
12  
9
DATABUS  
(output to i.MX)  
Figure 9. DTACK Write Cycle DMA Enabled  
Table 16. Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
CS5 assertion time  
See note 3  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
EB assertion time  
See note 3  
–
3
CS5 pulse width  
3T  
–
1.5T-0.8  
0.3  
4
RW negated before CS5 is negated  
Address inactive after CS negated  
DTACK asserted after CS5 asserted  
DTACK asserted to RW negated  
Data hold timing after RW negated  
Data ready after CS5 is asserted  
CS deactive to next CS active  
EB negate after CS negate  
DTACK pulse width  
1.5T-2.44  
5
–
6
–
2T+2.37  
1.5T-3.99  
–
1019T  
3T+6.6  
–
7
8
9
T
10  
11  
12  
T
–
0.5T  
1T  
0.5T+0.5  
3T  
Note:  
1. DTACK asserted means DTACK becomes low level.  
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
3. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.  
4. Address becomes valid and RW asserts at the start of write access cycle.  
5.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
22  
Freescale Semiconductor  
Specifications  
3.9.2.5 WAIT Read Cycle without DMA  
3
Address  
2
CS5  
8
1
9
programmable  
min 0ns  
EB  
5
OE  
4
WAIT  
7
6
DATABUS  
(input to i.MX)  
10  
11  
Figure 10. WAIT Read Cycle without DMA  
Table 17. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
OE and EB assertion time  
See note 2  
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS5 pulse width  
3T  
56.81  
–
3
OE negated to address inactive  
Wait asserted after OE asserted  
Wait asserted to OE negated  
Data hold timing after OE negated  
Data ready after wait asserted  
OE negated to CS negated  
OE negated after EB negated  
Become low after CS5 asserted  
Wait pulse width  
57.28  
1020T  
3T+7.33  
–
4
5
2T+1.57  
T-1.49  
0
6
7
T
8
1.5T-0.68  
0.06  
0
1.5T-0.06  
0.18  
9
10  
11  
1019T  
1020T  
1T  
Note:  
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when  
EBC bit in CS5L register is clear.  
3. Address becomes valid and CS asserts at the start of read access cycle.  
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
23  
Specifications  
3.9.2.6 WAIT Read Cycle DMA Enabled  
4
Address  
CS5  
2
9
1
10  
programmable  
min 0ns  
EB  
3
7
6
OE  
(logic high)  
WAIT  
RW  
5
11  
8
DATABUS  
12  
(input to i.MX)  
Figure 11. WAIT Read Cycle DMA Enabled  
Table 18. WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
OE and EB assertion time  
See note 2  
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS pulse width  
3T  
3
OE negated before CS5 is negated  
Address inactived before CS negated  
Wait asserted after CS5 asserted  
Wait asserted to OE negated  
Data hold timing after OE negated  
Data ready after wait is asserted  
CS deactive to next CS active  
OE negate after EB negate  
Wait becomes low after CS5 asserted  
Wait pulse width  
1.5T-0.68  
1.5T-0.06  
0.05  
1020T  
3T+7.33  
–
4
–
5
–
6
2T+1.57  
7
T-1.49  
8
–
T
T
9
10  
11  
12  
0.06  
0
0.18  
1019T  
1020T  
1T  
Note:  
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when  
EBC bit in CS5L register is clear.  
3. Address becomes valid and CS asserts at the start of read access cycle.  
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
24  
Freescale Semiconductor  
Specifications  
3.9.2.7 WAIT Write Cycle without DMA  
5
Address  
3
1
programmable  
min 0ns  
CS5  
2
10  
programmable  
min 0ns  
EB  
4
7
RW  
(logic high)  
WAIT  
OE  
6
11  
8
9
12  
DATABUS  
(output to i.MX)  
Figure 12. WAIT Write Cycle without DMA  
Table 19. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
CS5 assertion time  
See note 2  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
EB assertion time  
See note 2  
–
–
3
CS5 pulse width  
3T  
2.5T-3.63  
64.22  
–
4
RW negated before CS5 is negated  
RW negated to Address inactive  
Wait asserted after CS5 asserted  
Wait asserted to RW negated  
Data hold timing after RW negated  
Data ready after CS5 is asserted  
EB negated after CS5 is negated  
Wait becomes low after CS5 asserted  
Wait pulse width  
2.5T-1.16  
–
5
6
1020T  
2T+7.96  
–
7
T+2.66  
2T+0.03  
–
8
9
T
10  
11  
12  
0.5T  
0
0.5T+0.5  
1019T  
1020T  
1T  
Note:  
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programable by WEA bits in CS5L register.  
3. Address becomes valid and RW asserts at the start of write access cycle.  
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
25  
Specifications  
3.9.2.8 WAIT Write Cycle DMA Enabled  
5
Address  
1
3
10  
programmable  
min 0ns  
CS5  
2
11  
programmable  
min 0ns  
EB  
4
7
RW  
OE (logic high)  
WAIT  
6
12  
9
8
13  
DATABUS  
(output to i.MX)  
Figure 13. WAIT Write Cycle DMA Enabled  
Table 20. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz  
3.0 0.3 ꢀ  
Number  
Characteristic  
Unit  
Minimum  
Maximum  
1
2
CS5 assertion time  
See note 2  
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
EB assertion time  
See note 2  
3
CS5 pulse width  
3T  
–
4
RW negated before CS5 is negated  
Address inactived after CS negated  
Wait asserted after CS5 asserted  
Wait asserted to RW negated  
Data hold timing after RW negated  
Data ready after CS5 is asserted  
CS deactive to next CS active  
EB negate after CS negate  
Wait becomes low after CS5 asserted  
Wait pulse width  
2.5T-3.63  
2.5T-1.16  
0.09  
1020T  
2T+7.96  
–
5
–
6
–
7
T+2.66  
8
2T+0.03  
9
–
T
T
10  
11  
12  
13  
–
0.5T  
0
0.5T+0.5  
1019T  
1020T  
ns  
ns  
1T  
Note:  
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)  
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programable by WEA bits in CS5L register.  
3. Address becomes valid and RW asserts at the start of write access cycle.  
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.  
MC9328MXS Advance Information, Rev. 0  
26  
Freescale Semiconductor  
Specifications  
3.9.3 EIM External Bus Timing  
The following timing diagrams show the timing of accesses to memory or a peripheral.  
hclk  
hsel_weim_cs[0]  
htrans  
hwrite  
Seq/Nonseq  
Read  
haddr  
hready  
V1  
weim_hrdata  
weim_hready  
Last Valid Data  
V1  
BCLK (burst clock)  
ADDR  
Last Valid Address  
V1  
CS2  
R/W  
Read  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
V1  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 14. WSC = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
27  
Specifications  
hclk  
hsel_weim_cs[0]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid Data  
Write Data (V1)  
Unknown  
weim_hrdata  
Last Valid Data  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Address  
V1  
CS0  
R/W  
Write  
LBA  
OE  
EB  
DATA  
Last Valid Data  
Write Data (V1)  
Figure 15. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
28  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[0]  
htrans  
Nonseq  
Read  
V1  
hwrite  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS0  
Read  
R/W  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
1/2 Half Word  
2/2 Half Word  
DATA  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 16. WSC = 1, OEA = 1, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
29  
Specifications  
hclk  
hsel_weim_cs[0]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid Data  
Write Data (V1 Word)  
Last Valid Data  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS0  
R/W  
LBA  
Write  
OE  
EB  
DATA  
1/2 Half Word  
2/2 Half Word  
Figure 17. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
30  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[3]  
htrans  
Nonseq  
hwrite  
Read  
V1  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS[3]  
R/W  
BA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
Note 1: x = 0, 1, 2 or 3  
1/2 Half Word  
2/2 Half Word  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 18. WSC = 3, OEA = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
31  
Specifications  
hclk  
hsel_weim_cs[3]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata Last Valid  
Data  
Write Data (V1 Word)  
Last Valid Data  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS3  
R/W  
LBA  
OE  
Write  
EB  
DATA  
Last Valid Data  
1/2 Half Word  
2/2 Half Word  
Figure 19. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
32  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Read  
V1  
hwrite  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
Read  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
weim_data_in  
1/2 Half Word  
2/2 Half Word  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 20. WSC = 3, OEA = 4, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
33  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid  
Data  
Write Data (V1 Word)  
Last Valid Data  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
Write  
LBA  
OE  
EB  
DATA  
Last Valid Data  
1/2 Half Word  
2/2 Half Word  
Figure 21. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
34  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Read  
V1  
hwrite  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
Note 1: x = 0, 1, 2 or 3  
1/2 Half Word  
2/2 Half Word  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 22. WSC = 3, OEN = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
35  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Read  
V1  
hwrite  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
Note 1: x = 0, 1, 2 or 3  
1/2 Half Word  
2/2 Half Word  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 23. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
36  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid  
Data  
Write Data (V1 Word)  
Last Valid Data  
Unknown  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
Write  
LBA  
OE  
EB  
DATA  
Last Valid Data  
1/2 Half Word  
2/2 Half Word  
Figure 24. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
37  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid  
Data  
Write Data (V1 Word)  
Last Valid Data  
Unknown  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS2  
R/W  
LBA  
OE  
Write  
EB  
DATA  
Last Valid Data  
1/2 Half Word  
2/2 Half Word  
Figure 25. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
38  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Read  
V1  
Nonseq  
Write  
V8  
hwrite  
haddr  
hready  
hwdata  
Last Valid Data  
Write Data  
Read Data  
weim_hrdata  
weim_hready  
Last Valid Data  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V8  
CS2  
R/W  
LBA  
Read  
Write  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
DATA  
Read Data  
Last Valid Data  
Write Data  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 26. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
39  
Specifications  
Read  
Idle  
Write  
hclk  
hsel_weim_cs[2]  
htrans  
Nonseq  
Read  
V1  
Nonseq  
Write  
V8  
hwrite  
haddr  
hready  
hwdata  
Last Valid Data  
Write Data  
weim_hrdata  
weim_hready  
Last Valid Data  
Read Data  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V8  
Write  
CS2  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
DATA  
Read Data  
Last Valid Data  
Write Data  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 27. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
40  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[4]  
htrans  
Nonseq  
Write  
V1  
hwrite  
haddr  
hready  
hwdata  
Last Valid  
Data  
Write Data (Word)  
Last Valid Data  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V1 + 2  
CS  
R/W  
Write  
LBA  
OE  
EB  
DATA  
Last Valid Data  
Write Data (1/2 Half Word)  
Write Data (2/2 Half Word)  
Figure 28. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
41  
Specifications  
hclk  
hsel_weim_cs[4]  
htrans  
Nonseq  
Read  
V1  
Nonseq  
Write  
V8  
hwrite  
haddr  
hready  
hwdata  
weim_hrdata  
weim_hready  
Last Valid Data  
Write Data  
Read Data  
Last Valid Data  
BCLK (burst clock)  
ADDR Last Valid Addr  
Address V1  
Address V8  
CS4  
R/W  
LBA  
OE  
Read  
Write  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
Read Data  
DATA  
DATA  
Last Valid Data  
Write Data  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 29. WSC = 3, CSA = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
42  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[4]  
htrans  
Nonseq  
Read  
V1  
Idle  
Seq  
Read  
V2  
hwrite  
haddr  
hready  
weim_hrdata  
weim_hready  
Last Valid Data  
Read Data (V1)  
Read Data (V2)  
BCLK (burst clock)  
ADDR  
Last Valid  
Address V1  
Address V2  
CNC  
CS4  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
Read Data  
(V1)  
Read Data  
(V2)  
DATA  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 30. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
43  
Specifications  
hclk  
hsel_weim_cs[4]  
htrans  
Nonseq  
Read  
V1  
Idle Nonseq  
hwrite  
haddr  
Write  
V8  
hready  
hwdata  
Last Valid Data  
Write Data  
weim_hrdata  
Last Valid Data  
Read Data  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V8  
CNC  
CS4  
R/W  
LBA  
OE  
Read  
Write  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
DATA  
DATA  
Read Data  
Last Valid Data  
Write Data  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 31. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
44  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Idle  
Nonseq  
Read  
V1  
Nonse  
Read  
V5  
hwrite  
haddr  
hready  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Addr  
Address V1  
Address V5  
CS2  
Read  
R/W  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
ECB  
DATA  
V1 Word V2 Word  
V5 Word V6 Word  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 32. WSC = 3, SYNC = 1, A.HALF/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
45  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Idle  
Nonseq  
Read  
V1  
Seq  
Read  
V2  
Seq  
Read  
V3  
Seq  
Read  
V4  
hwrite  
haddr  
hready  
weim_hrdata  
weim_hready  
BCLK (burst clock)  
ADDR  
Last Valid Data  
V1 Word  
V2 Word  
V3 Word  
V4 Word  
Last Valid Addr  
Address V1  
CS2  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
ECB  
DATA  
V1 Word  
V2 Word  
V3 Word  
V4 Word  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 33. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD  
MC9328MXS Advance Information, Rev. 0  
46  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Idle  
Seq  
Nonseq  
hwrite  
Read  
V1  
Read  
V2  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
V2 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
CS2  
Last Valid  
Address V1  
Address V2  
Read  
R/W  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
ECB  
DATA  
V1 1/2  
V1 2/2  
V2 1/2  
V2 2/2  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 34. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
47  
Specifications  
hclk  
hsel_weim_cs[2]  
Non  
seq  
Idle  
htrans  
hwrite  
Seq  
Read  
V2  
Read  
V1  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
V2 Word  
weim_hready  
BCLK (burst clock)  
Last  
ADDR  
CS2  
Address V1  
Read  
R/W  
LBA  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
ECB  
DATA  
V1 1/2  
V1 2/2  
V2 1/2  
V2 2/2  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 35. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
48  
Freescale Semiconductor  
Specifications  
hclk  
hsel_weim_cs[2]  
htrans  
Non  
seq  
Idle  
Seq  
Read  
V2  
hwrite  
Read  
V1  
haddr  
hready  
weim_hrdata  
Last Valid Data  
V1 Word  
V2 Word  
weim_hready  
BCLK (burst clock)  
ADDR  
Last  
Address V1  
CS2  
R/W  
LBA  
Read  
OE  
EBx1 (EBC2=0)  
EBx1 (EBC2=1)  
ECB  
DATA  
V1 1/2  
V1 2/2  
V2 1/2  
V2 2/2  
Note 1: x = 0, 1, 2 or 3  
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register  
Figure 36. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
49  
Specifications  
3.9.4 Non-TFT Panel Timing  
T1  
T1  
VSYN  
T3  
T4  
T2  
T2  
XMAX  
HSYN  
SCLK  
Ts  
LD[15:0]  
Figure 37. Non-TFT Panel Timing  
Table 21. Non TFT Panel Timing Diagram  
Allowed Register Minimum  
Symbol  
Parameter  
Actual ꢀalue  
Unit  
ꢀalue  
T1  
T2  
T3  
T4  
HSYN to VSYN delay  
HSYN pulse width  
VSYN to SCLK  
0
0
–
0
HWAIT2+2  
HWIDTH+1  
0<= T3<=Ts  
HWAIT1+1  
Tpix  
Tpix  
–
SCLK to HSYN  
Tpix  
•
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all  
these 3 signals are active high.  
•
•
•
•
•
Ts is the shift clock period.  
Ts = Tpix * (panel data bus width).  
Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).  
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.  
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.  
MC9328MXS Advance Information, Rev. 0  
50  
Freescale Semiconductor  
Specifications  
3.10 SPI Timing Diagrams  
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two  
control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The  
SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When  
the SPI module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to  
match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data  
into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 38 through  
Figure 42 show the timing relationship of the master SPI using different triggering mechanisms.  
2
5
3
SS  
1
4
SPIRDY  
SCLK, MOSI, MISO  
Figure 38. Master SPI Timing Diagram Using SPI_RDY Edge Trigger  
SS  
SPIRDY  
SCLK, MOSI, MISO  
Figure 39. Master SPI Timing Diagram Using SPI_RDY Level Trigger  
SS (output)  
SCLK, MOSI, MISO  
Figure 40. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger  
SS (input)  
SCLK, MOSI, MISO  
Figure 41. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT  
MC9328MXS Advance Information, Rev. 0  
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51  
Specifications  
SS (input)  
6
7
SCLK, MOSI, MISO  
Figure 42. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge  
Table 22. Timing Parameter Table for Figure 38 through Figure 42  
3.0 0.3 ꢀ  
Ref No.  
Parameter  
Unit  
Minimum  
Maximum  
2T1  
1
2
SPI_RDY to SS output low  
–
–
ns  
ns  
3 • Tsclk2  
2 • Tsclk  
0
SS output low to first SCLK edge  
3
4
5
Last SCLK edge to SS output high  
SS output high to SPI_RDY low  
SS output pulse width  
–
–
–
ns  
ns  
ns  
Tsclk + WAIT 3  
6
7
SS input low to first SCLK edge  
SS input pulse width  
T
T
–
–
ns  
ns  
1. T = CSPI system clock period (PERCLK2).  
2. Tsclk = Period of SCLK.  
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.  
3.11 LCD Controller  
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller  
with various display configurations, refer to the LCD controller chapter of the i.MX Reference Manual.  
LSCLK  
1
LD[15:0]  
Figure 43. SCLK to LD Timing Diagram  
Table 23. LCDC SCLK Timing Parameter Table  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
SCLK to LD valid  
Minimum  
Maximum  
Unit  
1
–
2
ns  
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Freescale Semiconductor  
Specifications  
Non-display region  
T3  
Display region  
T1  
T4  
VSYN  
HSYN  
OE  
T2  
Line Y  
Line 1  
Line Y  
LD[15:0]  
T6  
T7  
T5  
XMAX  
HSYN  
SCLK  
OE  
T8  
(1,1)  
(1,2)  
LD[15:0]  
VSYN  
(1,X)  
T9  
T10  
Figure 44. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing  
Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing  
Symbol  
Description  
Minimum  
Corresponding Register ꢀalue  
Unit  
T1  
End of OE to beginning of VSYN  
T5+T6  
(VWAIT1·T2)+T5+T6+T7+T9  
Ts  
+T7+T9  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
HSYN period  
XMAX+5  
XMAX+T5+T6+T7+T9+T10  
Ts  
Ts  
Ts  
Ts  
Ts  
Ts  
ns  
Ts  
VSYN pulse width  
T2  
2
VWIDTH·(T2)  
VWAIT2·(T2)  
HWIDTH+1  
HWAIT2+1  
HWAIT1+1  
3
End of VSYN to beginning of OE  
HSYN pulse width  
1
End of HSYN to beginning to T9  
End of OE to beginning of HSYN  
SCLK to valid LD data  
1
1
-3  
2
End of HSYN idle2 to VSYN edge  
(for non-display region)  
2
T9  
End of HSYN idle2 to VSYN edge  
(for Display region)  
1
1
Ts  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
53  
Specifications  
Symbol  
Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)  
Description  
Minimum  
Corresponding Register ꢀalue  
Unit  
T10  
T10  
VSYN to OE active (Sharp = 0) when VWAIT2 = 0  
VSYN to OE active (Sharp = 1) when VWAIT2 = 0  
1
2
1
2
Ts  
Ts  
Note:  
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.  
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 44, all 3 signals are active low.  
The polarity of SCLK and LD[15:0] can also be programmed.  
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 44, SCLK is always  
active.  
•
•
For T9 non-display region, VSYN is non-active. It is used as an reference.  
XMAX is defined in pixels.  
MC9328MXS Advance Information, Rev. 0  
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Freescale Semiconductor  
Specifications  
3.12 Pulse-Width Modulator  
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal  
is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-  
width modulator output (PWMO) external pin. Its timing diagram is shown in Figure 45 and the parameters are  
listed in Table 25.  
1
2a  
3b  
System Clock  
2b  
4b  
3a  
4a  
PWM Output  
Figure 45. PWM Output Timing Diagram  
Table 25. PWM Output Timing Parameter Table  
1.8 0.1 V  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
1
System CLK frequency1  
Clock high time1  
Clock low time1  
0
87  
–
0
5/10  
5/10  
–
100  
–
MHz  
ns  
2a  
2b  
3a  
3b  
4a  
4b  
3.3  
7.5  
–
–
–
ns  
Clock fall time1  
5
5/10  
5/10  
–
ns  
Clock rise time1  
–
6.67  
–
–
ns  
Output delay time1  
Output setup time1  
5.7  
5.7  
5
ns  
–
5
–
ns  
1. CL of PWMO = 30 pF  
MC9328MXS Advance Information, Rev. 0  
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55  
Specifications  
3.13 SDRAM Controller  
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random  
access memory) Controller.  
1
SDCLK  
2
3S  
3
CS  
RAS  
CAS  
3H  
3S  
3S  
3H  
3S  
3H  
3H  
4H  
WE  
ADDR  
DQ  
4S  
ROW/BA  
COL/BA  
8
5
6
Data  
7
3S  
DQM  
3H  
Note: CKE is high during the read/write cycle.  
Figure 46. SDRAM Read Cycle Timing Diagram  
Table 26. SDRAM Read Timing Parameter Table  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum Maximum Minimum Maximum  
1
2
SDRAM clock high-level width  
SDRAM clock low-level width  
SDRAM clock cycle time  
2.67  
6
–
–
–
–
–
4
4
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
3
11.4  
3.42  
2.28  
10  
3
3S  
3H  
CS, RAS, CAS, WE, DQM setup time  
CS, RAS, CAS, WE, DQM hold time  
2
MC9328MXS Advance Information, Rev. 0  
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Freescale Semiconductor  
Specifications  
Table 26. SDRAM Read Timing Parameter Table (Continued)  
1.8 0.1 ꢀ 3.0 0.3 ꢀ  
Minimum Maximum Minimum Maximum  
Ref  
No.  
Parameter  
Unit  
4S  
4H  
5
Address setup time  
3.42  
2.28  
–
–
–
3
2
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address hold time  
SDRAM access time (CL = 3)  
SDRAM access time (CL = 2)  
SDRAM access time (CL = 1)  
Data out hold time  
6.84  
6.84  
22  
–
6
5
–
–
6
5
–
–
22  
–
6
2.85  
–
–
2.5  
–
7
Data out high-impedance time (CL = 3)  
Data out high-impedance time (CL = 2)  
Data out high-impedance time (CL = 1)  
Active to read/write command period (RC = 1)  
6.84  
6.84  
22  
6
7
–
–
6
7
–
–
22  
–
1
1
8
–
tRCD  
tRCD  
1. tRCD = SDRAM clock cycle time. This settings can be found in the i.MX reference manual.  
MC9328MXS Advance Information, Rev. 0  
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Specifications  
SDCLK  
1
3
2
CS  
RAS  
CAS  
6
WE  
ADDR  
DQ  
4
5
7
/ BA  
ROW/BA  
COL/BA  
DATA  
8
9
DQM  
Figure 47. SDRAM Write Cycle Timing Diagram  
Table 27. SDRAM Write Timing Parameter Table  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
1
2
3
4
5
6
SDRAM clock high-level width  
SDRAM clock low-level width  
SDRAM clock cycle time  
Address setup time  
2.67  
6
–
–
–
–
–
–
4
4
–
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
ns  
11.4  
3.42  
2.28  
10  
3
Address hold time  
2
Precharge cycle period1  
2
2
tRP  
tRP  
2
2
7
Active to read/write command delay  
–
–
ns  
tRCD  
tRCD  
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Freescale Semiconductor  
Specifications  
Table 27. SDRAM Write Timing Parameter Table (Continued)  
1.8 0.1 ꢀ 3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
8
9
Data setup time  
Data hold time  
4.0  
–
–
2
2
–
–
ns  
ns  
2.28  
1. Precharge cycle timing is included in the write timing diagram.  
2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX reference manual.  
SDCLK  
1
3
2
CS  
RAS  
CAS  
6
7
7
WE  
ADDR  
DQ  
4
5
BA  
ROW/BA  
DQM  
Figure 48. SDRAM Refresh Timing Diagram  
Table 28. SDRAM Refresh Timing Parameter Table  
1.8 0.1 ꢀ  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
1
2
SDRAM clock high-level width  
SDRAM clock low-level width  
2.67  
6
–
–
4
4
–
–
ns  
ns  
MC9328MXS Advance Information, Rev. 0  
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59  
Specifications  
Table 28. SDRAM Refresh Timing Parameter Table (Continued)  
1.8 0.1 ꢀ 3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
3
4
5
6
SDRAM clock cycle time  
Address setup time  
11.4  
3.42  
2.28  
–
–
–
–
10  
3
–
–
–
–
ns  
ns  
ns  
ns  
Address hold time  
2
1
1
Precharge cycle period  
tRP  
tRP  
1
1
7
Auto precharge command period  
–
–
ns  
tRC  
tRC  
1. tRP and tRC = SDRAM clock cycle time. These settings can be found in the i.MX reference manual.  
SDCLK  
CS  
RAS  
CAS  
WE  
ADDR  
DQ  
BA  
DQM  
CKE  
Figure 49. SDRAM Self-Refresh Cycle Timing Diagram  
MC9328MXS Advance Information, Rev. 0  
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Freescale Semiconductor  
Specifications  
3.14 USB Device Port  
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers,  
and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk  
data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and  
how they work from the ground up.  
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet  
transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of  
packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is  
no end-of-transfer.  
USBD_AFE  
(Output)  
t VMO_ROE  
4
t ROE_VPO  
1
USBD_ROE  
(Output)  
6
3
tPERIOD  
tVPO_ROE  
USBD_VPO  
(Output)  
USBD_VMO  
(Output)  
tROE_VMO  
tFEOPT  
USBD_SUSPND  
(Output)  
2
5
USBD_RCV  
(Input)  
USBD_VP  
(Input)  
USBD_VM  
(Input)  
Figure 50. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)  
Table 29. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
1
2
3
4
5
6
tROE_VPO; USBD_ROE active to USBD_VPO low  
tROE_VMO; USBD_ROE active to USBD_VMO high  
83.14  
81.55  
83.54  
248.90  
160.00  
11.97  
83.47  
81.98  
83.80  
249.13  
175.00  
12.03  
ns  
ns  
t
VPO_ROE; USBD_VPO high to USBD_ROE deactivated  
tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0)  
FEOPT; SE0 interval of EOP  
tPERIOD; Data transfer rate  
ns  
ns  
t
ns  
Mb/s  
MC9328MXS Advance Information, Rev. 0  
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61  
Specifications  
USBD_AFE  
(Output)  
USBD_ROE  
(Output)  
USBD_VPO  
(Output)  
USBD_VMO  
(Output)  
USBD_SUSPND  
(Output)  
USBD_RCV  
(Input)  
1
tFEOPR  
USBD_VP  
(Input)  
USBD_VM  
(Input)  
Figure 51. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)  
Table 30. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)  
3.0 0.3 ꢀ  
Ref No.  
Parameter  
Unit  
Minimum  
Maximum  
1
t
FEOPR; Receiver SE0 interval of EOP  
82  
–
ns  
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Freescale Semiconductor  
Specifications  
3.15 I2C Module  
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction,  
Slave Acknowledge, Data, Data Acknowledge, and STOP.  
SDA  
5
3
4
SCL  
2
6
1
2
Figure 52. Definition of Bus Timing for I C  
2
Table 31. I C Bus Timing Parameter Table  
1.8 0.1 V  
3.0 0.3 ꢀ  
Ref No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
1
2
3
4
5
6
Hold time (repeated) START condition  
Data hold time  
182  
0
–
171  
–
160  
0
–
150  
–
ns  
ns  
ns  
ns  
ns  
ns  
Data setup time  
11.4  
80  
10  
HIGH period of the SCL clock  
LOW period of the SCL clock  
Setup time for STOP condition  
–
120  
320  
160  
–
480  
182.4  
–
–
–
–
3.16 Synchronous Serial Interface  
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the  
transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the  
transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock  
mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions  
only during transmission. The internal and external clock timing diagrams are shown in Figure 54 through  
Figure 56 on page 65.  
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of  
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used  
in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division  
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These  
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.  
MC9328MXS Advance Information, Rev. 0  
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63  
Specifications  
1
STCK Output  
4
2
STFS (bl) Output  
STFS (wl) Output  
6
8
12  
10  
11  
32  
STXD Output  
SRXD Input  
31  
Note: SRXD input in synchronous mode only.  
Figure 53. SSI Transmitter Internal Clock Timing Diagram  
1
SRCK Output  
3
5
SRFS (bl) Output  
SRFS (wl) Output  
7
9
13  
14  
SRXD Input  
Figure 54. SSI Receiver Internal Clock Timing Diagram  
MC9328MXS Advance Information, Rev. 0  
64  
Freescale Semiconductor  
Specifications  
15  
16  
17  
STCK Input  
18  
20  
STFS (bl) Input  
STFS (wl) Input  
24  
22  
28  
27  
34  
26  
STXD Output  
SRXD Input  
33  
Note: SRXD Input in Synchronous mode only  
Figure 55. SSI Transmitter External Clock Timing Diagram  
15  
16  
17  
SRCK Input  
19  
21  
SRFS (bl) Input  
SRFS (wl) Input  
25  
23  
30  
29  
SRXD Input  
Figure 56. SSI Receiver External Clock Timing Diagram  
Table 32. SSI (Port C Primary Function) Timing Parameter Table  
1.8 0.1 V 3.0 0.3 ꢀ  
Minimum Maximum Minimum Maximum  
Internal Clock Operation1 (Port C Primary Function2)  
Ref No.  
Parameter  
Unit  
1
2
3
STCK/SRCK clock period1  
STCK high to STFS (bl) high3  
SRCK high to SRFS (bl) high3  
95  
1.5  
-1.2  
–
83.3  
1.3  
–
ns  
ns  
ns  
4.5  
-1.7  
3.9  
-1.5  
-1.1  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
65  
Specifications  
Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued)  
1.8 0.1 V 3.0 0.3 ꢀ  
Minimum Maximum Minimum Maximum  
Ref No.  
Parameter  
Unit  
4
5
STCK high to STFS (bl) low3  
SRCK high to SRFS (bl) low3  
STCK high to STFS (wl) high3  
SRCK high to SRFS (wl) high3  
STCK high to STFS (wl) low3  
SRCK high to SRFS (wl) low3  
STCK high to STXD valid from high impedance  
STCK high to STXD high  
2.5  
0.1  
4.3  
-0.8  
4.45  
-1.5  
4.33  
-0.8  
15.73  
3.08  
3.19  
13.57  
–
2.2  
0.1  
1.3  
-1.1  
2.2  
0.1  
12.5  
0.8  
0.5  
11.3  
18.5  
0
3.8  
-0.8  
3.9  
-1.5  
3.8  
-0.8  
13.8  
2.7  
2.8  
11.9  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
6
1.48  
-1.1  
2.51  
0.1  
7
8
9
10  
11a  
11b  
12  
13  
14  
14.25  
0.91  
0.57  
12.88  
21.1  
0
STCK high to STXD low  
STCK high to STXD high impedance  
SRXD setup time before SRCK low  
SRXD hold time after SRCK low  
–
–
External Clock Operation (Port C Primary Function2)  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27a  
27b  
28  
29  
30  
STCK/SRCK clock period1  
92.8  
27.1  
61.1  
–
–
–
81.4  
40.7  
40.7  
0
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
STCK/SRCK clock high period  
STCK/SRCK clock low period  
STCK high to STFS (bl) high3  
SRCK high to SRFS (bl) high3  
STCK high to STFS (bl) low3  
SRCK high to SRFS (bl) low3  
STCK high to STFS (wl) high3  
SRCK high to SRFS (wl) high3  
STCK high to STFS (wl) low3  
SRCK high to SRFS (wl) low3  
STCK high to STXD valid from high impedance  
STCK high to STXD high  
–
–
–
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
28.16  
18.13  
18.24  
28.5  
–
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
24.7  
15.9  
16.0  
25.0  
–
–
0
–
0
–
0
–
0
–
0
–
0
–
0
18.01  
8.98  
9.12  
18.47  
1.14  
0
15.8  
7.0  
8.0  
16.2  
1.0  
0
STCK high to STXD low  
STCK high to STXD high impedance  
SRXD setup time before SRCK low  
SRXD hole time after SRCK low  
–
–
Synchronous Internal Clock Operation (Port C Primary Function2)  
31  
32  
SRXD setup before STCK falling  
SRXD hold after STCK falling  
15.4  
0
–
–
13.5  
0
–
–
ns  
ns  
MC9328MXS Advance Information, Rev. 0  
66  
Freescale Semiconductor  
Specifications  
Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued)  
1.8 0.1 V 3.0 0.3 ꢀ  
Minimum Maximum Minimum Maximum  
Synchronous External Clock Operation (Port C Primary Function2)  
Ref No.  
Parameter  
Unit  
33  
34  
SRXD setup before STCK falling  
SRXD hold after STCK falling  
1.14  
0
–
–
1.0  
0
–
–
ns  
ns  
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted  
frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing  
remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and  
in the figures.  
2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and  
Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed  
both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI  
module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default,  
the input are selected from Port C primary function.  
3. bl = bit length; wl = word length.  
Table 33. SSI (Port B Alternate Function) Timing Parameter Table  
1.8 0.1 V  
Minimum Maximum  
Internal Clock Operation1 (Port B Alternate Function2)  
3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum Maximum  
1
2
STCK/SRCK clock period1  
95  
1.7  
–
83.3  
1.5  
-0.1  
2.7  
–
4.2  
1.0  
4.6  
2.0  
4.2  
1.0  
4.6  
2.0  
14.2  
3.0  
3.5  
12.8  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
STCK high to STFS (bl) high3  
SRCK high to SRFS (bl) high3  
STCK high to STFS (bl) low3  
SRCK high to SRFS (bl) low3  
STCK high to STFS (wl) high3  
SRCK high to SRFS (wl) high3  
STCK high to STFS (wl) low3  
SRCK high to SRFS (wl) low3  
STCK high to STXD valid from high impedance  
4.8  
3
-0.1  
3.08  
1.25  
1.71  
-0.1  
3.08  
1.25  
14.93  
1.25  
2.51  
12.43  
20  
1.0  
4
5.24  
2.28  
4.79  
1.0  
5
1.1  
6
1.5  
7
-0.1  
2.7  
8
5.24  
2.28  
16.19  
3.42  
3.99  
14.59  
–
9
1.1  
10  
13.1  
1.1  
11a STCK high to STXD high  
11b STCK high to STXD low  
2.2  
10.9  
17.5  
0
12  
13  
14  
STCK high to STXD high impedance  
SRXD setup time before SRCK low  
SRXD hold time after SRCK low  
0
–
–
External Clock Operation (Port B Alternate Function2)  
92.8  
15  
STCK/SRCK clock period1  
–
81.4  
–
ns  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
67  
Specifications  
Table 33. SSI (Port B Alternate Function) Timing Parameter Table (Continued)  
1.8 0.1 V 3.0 0.3 ꢀ  
Ref  
No.  
Parameter  
Unit  
Minimum  
Maximum  
Minimum  
Maximum  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
STCK/SRCK clock high period  
STCK/SRCK clock low period  
STCK high to STFS (bl) high3  
SRCK high to SRFS (bl) high3  
STCK high to STFS (bl) low3  
SRCK high to SRFS (bl) low3  
STCK high to STFS (wl) high3  
SRCK high to SRFS (wl) high3  
STCK high to STFS (wl) low3  
SRCK high to SRFS (wl) low3  
STCK high to STXD valid from high impedance  
27.1  
61.1  
–
–
40.7  
40.7  
0
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
–
–
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
92.8  
29.07  
20.75  
21.32  
29.75  
–
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
81.4  
25.5  
18.2  
18.7  
26.1  
–
–
0
–
0
–
0
–
0
–
0
–
0
–
0
18.9  
9.23  
10.60  
17.90  
1.14  
0
16.6  
8.1  
9.3  
15.7  
1.0  
0
27a STCK high to STXD high  
27b STCK high to STXD low  
28  
29  
30  
STCK high to STXD high impedance  
SRXD setup time before SRCK low  
SRXD hold time after SRCK low  
–
–
Synchronous Internal Clock Operation (Port B Alternate Function2)  
31  
32  
SRXD setup before STCK falling  
SRXD hold after STCK falling  
18.81  
0
–
–
16.5  
0
–
–
ns  
ns  
Synchronous External Clock Operation (Port B Alternate Function2)  
33  
34  
SRXD setup before STCK falling  
SRXD hold after STCK falling  
1.14  
0
–
–
1.0  
0
–
–
ns  
ns  
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted  
frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing  
remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and  
in the figures.  
2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and  
Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed  
both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI  
module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input  
are selected from Port C primary function.  
3. bl = bit length; wl = word length.  
MC9328MXS Advance Information, Rev. 0  
68  
Freescale Semiconductor  
4 Pin-Out and Package Information  
Table 34 illustrates the package pin assignments for the 225-contact PBGA package.  
Table 34. i.MX 225 PBGA Pin Assignments  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
A
B
C
D
E
F
PB13  
SSI1_  
RXCLK  
SSI1_  
TXCLK  
USBD_  
ROE  
USBD_  
SUSPND  
USBD_VM  
SSI0_  
RXFS  
SSI0_  
TXCLK  
SPI1_RDY  
SPI1_  
SCLK  
REV  
PS  
LD2  
LD4  
LD5  
PB11  
D31  
A23  
A21  
A20  
PB12  
PB8  
A24  
A22  
A19  
SSI1_  
RXDAT  
USBD_  
AFE  
USBD_  
RCV  
USBD_  
VMO  
SSI0_  
RXDAT  
UART1_  
TXD  
SPI1_SS  
LSCLK  
SPL_  
SPR  
LD0  
LD8  
LD3  
LD9  
LD6  
LD12  
TOUT2  
PA4  
LD7  
NVDD2  
LD13  
PA3  
SSI1_  
RXFS  
SSI1_  
TXFS  
PB10  
USBD_  
VPO  
UART2_  
RXD  
SSI0_  
TXFS  
UART1_  
RTS  
CONTRAST  
VSYNC  
HSYNC  
PB9  
D30  
D28  
SSI1_  
TXDAT  
NVDD1  
NVDD1  
NVDD1  
USBD_  
VP  
QVDD4 UART2_  
TXD  
NVDD3  
SPI1_  
MOSI  
LD1  
LD11  
TIN  
D29  
D27  
QVSS  
UART2_ UART1_  
RTS  
UART1_  
CTS  
SPI1_  
MISO  
OE_  
ACD  
LD10  
LD14  
RXD  
NVDD1  
UART2_  
CTS  
SSI0_  
RXCLK  
SSI0_  
TXDAT  
CLS  
QVDD3  
LD15  
PA6  
PA8  
G
H
J
A17  
A15  
A14  
A18  
A16  
A12  
D26  
D23  
D21  
D25  
D24  
D20  
NVDD1  
D22  
NVSS  
NVSS  
NVSS  
NVDD4  
NVSS  
NVSS  
NVSS  
NVSS  
NVSS  
NVSS  
NVSS  
QVSS  
NVDD2  
PA10  
PWMO  
PA5  
PA7  
PA12  
TCK  
PA11  
PA14  
TDO  
PA13  
I2C_DATA  
BOOT1  
PA9  
TMS  
NVDD1  
QVDD1  
I2C_  
CLK  
BOOT0  
K
A13  
A11  
CS2  
D19  
NVDD1  
NVSS  
QVSS  
NVDD1  
NVSS  
ECB  
D1  
BOOT2  
TDI  
BIG_  
ENDIAN  
RESET_  
OUT  
XTAL32K  
L
A10  
D16  
A9  
D17  
D13  
D18  
D10  
NVDD1  
EB3  
NVDD1  
NVDD1  
CS5  
CS4  
D2  
NVSS  
RW  
NVSS  
NVSS  
POR  
QVSS  
XTAL16M  
EXTAL32K  
EXTAL16M  
1
M
D15  
CS1  
BOOT3  
QVDD2  
RESET_IN  
BCLK  
N
P
A8  
A7  
A5  
D12  
A4  
EB0  
A3  
D9  
A2  
D8  
A1  
CS3  
D6  
CS0  
D5  
PA17  
MA10  
D0  
DQM2  
DQM1  
DQM0  
RAS  
SDCKE0  
SDCKE1  
TRISTATE  
CLKO  
TRST  
2
D14  
MA11  
RESETSF  
2
R
A6  
D11  
EB1  
EB2  
OE  
D7  
A0  
D4  
LBA  
D3  
DQM3  
CAS  
SDWE  
AVDD1  
SDCLK  
1. Burst Clock  
2. These signals are not used on the MC9328MXS and should be floated in an actual application.  
Pin-Out and Package Information  
4.1 PBGA 225 Package Dimensions  
Figure 57 illustrates the 225 PBGA 13 mm × 13 mm package.  
Case Outline 1304B  
TOP ꢀIEW  
BOTTOM ꢀIEW  
SIDE ꢀIEW  
NOTES:  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
2. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.  
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.  
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.  
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF  
PACKAGE.  
Figure 57. i.MX Processor’s 225 PBGA Mechanical Drawing  
MC9328MXS Advance Information, Rev. 0  
70  
Freescale Semiconductor  
NOTES  
MC9328MXS Advance Information, Rev. 0  
Freescale Semiconductor  
71  
Information in this document is provided solely to enable system and software implementers to use  
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© Freescale Semiconductor, Inc. 2005. All rights reserved.  
MC9328MXS/D  
Rev. 0  
1/2005  

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