MC9S08PA32A [NXP]
MC9S08PA60A and MC9S08PA32A are recommended for new design;
| 型号： | MC9S08PA32A |
| 厂家： | 
NXP |
| 描述： | MC9S08PA60A and MC9S08PA32A are recommended for new design |
| 文件： | 总41页 (文件大小：897K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MC9S08PA60
Rev. 4, 09/2019
NXP Semiconductors
Data Sheet: Technical Data
MC9S08PA60
MC9S08PA60 Series Data
MC9S08PA60A and MC9S08PA32A
are recommended for new design
Sheet
Supports: MC9S08PA60(A) and
MC9S08PA32(A)
Key features
• Development support
– Single-wire background debug interface
– Breakpoint capability to allow three breakpoints
setting during in-circuit debugging
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes
• 8-Bit S08 central processor unit (CPU)
– Up to 20 MHz bus at 2.7 V to 5.5 V across
temperature range of -40 °C to 105 °C
– Supporting up to 40 interrupt/reset sources
– Supporting up to four-level nested interrupt
– On-chip memory
• Peripherals
– Up to 60 KB flash read/program/erase over full
operating voltage and temperature
– Up to 256 byte EEPROM; 2-byte erase sector;
program and erase while executing flash
– Up to 4096 byte random-access memory (RAM)
– Flash and RAM access protection
– ACMP - one analog comparator with both positive
and negative inputs; separately selectable interrupt
on rising and falling comparator output; filtering
– ADC - 16-channel, 12-bit resolution; 2.5 µs
conversion time; data buffers with optional
watermark; automatic compare function; internal
bandgap reference channel; operation in stop mode;
optional hardware trigger
• Power-saving modes
– One low-power stop mode; reduced power wait
mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
– CRC - programmable cyclic redundancy check
module
– FTM - three flex timer modulators modules
including one 6-channel and two 2-channel ones;
16-bit counter; each channel can be configured for
input capture, output compare, edge- or center-
aligned PWM mode
– IIC - One inter-integrated circuit module; up to 400
kbps; multi-master operation; programmable slave
address; supporting broadcast mode and 10-bit
addressing; supporting SMBUS and PMBUS
– MTIM - Two modulo timers with 8-bit prescaler and
overflow interrupt
– RTC - 16-bit real timer counter (RTC)
– SCI - three serial communication interface (SCI/
UART) modules optional 13-bit break; full duplex
non-return to zero (NRZ); LIN extension support
– SPI - one 8-bit and one 16-bit serial peripheral
interface (SPI) modules; full-duplex or single-wire
bidirectional; master or slave mode
• Clocks
– Oscillator (XOSC) - loop-controlled Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz
– Internal clock source (ICS) - containing a frequency-
locked-loop (FLL) controlled by internal or external
reference; precision trimming of internal reference
allowing 1% deviation across temperature range of 0
°C to 70 °C and 2% deviation across the whole
operating temperature; up to 20 MHz
• System protection
– Watchdog with independent clock source
– Low-voltage detection with reset or interrupt;
selectable trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Input/Output
– Up to 57 GPIOs including one output-only pin
– Two 8-bit keyboard interrupt modules (KBI)
– Two true open-drain output pins
– Eight, ultra-high current sink pins supporting 20 mA source/sink current
• Package options
– 64-pin LQFP; 64-pin QFP
– 48-pin LQFP
– 44-pin LQFP
– 32-pin LQFP
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
2
NXP Semiconductors
Table of Contents
1
2
3
MCU block diagram...........................................................................4
6.2.2 Debug trace timing specifications................................19
6.2.3 FTM module timing.....................................................20
6.3 Thermal specifications...............................................................21
6.3.1 Thermal operating requirements..................................21
6.3.2 Thermal characteristics................................................ 21
Peripheral operating requirements and behaviors..............................22
7.1 External oscillator (XOSC) and ICS characteristics..................22
7.2 NVM specifications...................................................................24
7.3 Analog........................................................................................25
7.3.1 ADC characteristics..................................................... 25
7.3.2 Analog comparator (ACMP) electricals...................... 28
7.4 Communication interfaces.........................................................29
7.4.1 SPI switching specifications........................................ 29
Dimensions.........................................................................................32
8.1 Obtaining package dimensions..................................................32
Pinout................................................................................................. 33
9.1 Signal multiplexing and pin assignments.................................. 33
9.2 Device pin assignment...............................................................35
Orderable part numbers......................................................................6
Part identification...............................................................................7
3.1 Description.................................................................................7
3.2 Format........................................................................................7
3.3 Fields..........................................................................................7
3.4 Example..................................................................................... 7
Parameter Classification.....................................................................8
Ratings................................................................................................8
5.1 Thermal handling ratings...........................................................8
5.2 Moisture handling ratings..........................................................8
5.3 ESD handling ratings.................................................................9
5.4 Voltage and current operating ratings........................................9
General............................................................................................... 10
6.1 Nonswitching electrical specifications...................................... 10
6.1.1 DC characteristics........................................................ 10
6.1.2 Supply current characteristics......................................16
6.1.3 EMC performance........................................................17
6.2 Switching specifications............................................................ 18
6.2.1 Control timing..............................................................18
7
4
5
6
8
9
10 Revision history................................................................................. 39
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
3
MCU block diagram
1 MCU block diagram
The block diagram below shows the structure of the MCUs.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
4
NXP Semiconductors
MCU block diagram
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0
PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
1
PTA2/KBI0P2/RxD0/SDA
PTA3/KBI0P3/TxD0/SCL
PTA4/ACMPO/BKGD/MS
HCS08 CORE
1
KEYBOARD INTERRUPT
2
MODULE (KBI0)
PTA5/IRQ/TCLK0/RESET
PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
CPU
BDC
KBYBOARD INTERRUPT
MODULE (KBI1)
PTB0/KBI0P4/RxD0/ADP4
PTB1/KBI0P5/TxD0/ADP5
PTB2/KBI0P6/SPSCK0/ADP6
PTB3/KBI0P7/MOSI0/ADP7
SYSTEM INTEGRATION
8-BIT MODULO TIMER
MODULE (SIM)
(MTIM0)
3
PTB4/FTM2CH4/MISO0
3
WDOG
IRQ
LVD
PTB5/FTM2CH5/SS0
PTB6/SDA/XTAL
PTB7/SCL/EXTAL
8-BIT MODULO TIMER
(MTIM1)
1 kHz OSC
PTC0/FTM2CH0/ADP8
PTC1/FTM2CH1/ADP9/
PTC2/FTM2CH2/ADP10
PTC3/FTM2CH3/ADP11
PTC4/FTM1CH0/RTCO
PTC5/FTM1CH1
2-CH FLEX TIMER
INTERRUPT PRIORITY
MODULE (FTM0)
CONTROLLER(IPC)
2-CH FLEX TIMER
ON-CHIP ICE AND
DEBUG MODUE (DBG)
MODULE (FTM1)
PTC6/RxD1
PTC7/TxD1
6-CH FTM TIMER
3
USER FLASH
MC9S08PA60 = 60,864 bytes
MC9S08PA32 = 32,768 bytes
MODULE (FTM2)
PTD0/KBI1P0/FTM2CH2/SPSCK1
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD2/KBI1P2/MISO1
PTD3/KBI1P3/SS1
PTD4/KBI1P4
PTD5/KBI1P5
PTD6/KBI1P6/RxD2
PTD7/KBI1P7/TxD2
3
SERIAL COMMUNICATION
INTERFACE (SCI0)
USER EEPROM
MC9S08PA60 = 256 bytes
MC9S08PA32 = 256 bytes
SERIAL COMMUNICATION
INTERFACE (SCI1)
3
PTE0/SPSCK0/TCLK1
PTE1/MOSI0
PTE2/MISO0
PTE3/SS0
PTE4
SERIAL COMMUNICATION
USER RAM
MC9S08PA60 = 4,096 bytes
MC9S08PA32 = 4,096 bytes
3
INTERFACE (SCI2)
8-BIT SERIAL PERIPHERAL
INTERFACE MODULE(SPI0)
PTE5
20 MHz INTERNAL CLOCK
PTE6
PTE7/TCLK2
SOURCE (ICS)
16-BIT SERIAL PERIPHERAL
EXTAL
XTAL
INTERFACE MODULE(SPI1)
PTF0
PTF1
PTF2
PTF3
PTF4/ADP12
PTF5/ADP13
PTF6/ADP14
PTF7/ADP15
EXTERNAL OSCILLATOR
SOURCE (XOSC)
INTER-INTEGRATED
V
V
V
V
V
DD
SS
DD
SS
CIRCUIT(IIC)
5
5
POWER MANAGEMENT
CONTROLLER (PMC)
ANALOG COMPARATOR
5
(ACMP)
SS
V
V
V
V
REFH
DDA
REFL
SSA
PTG0
PTG1
PTG2
PTG3
REAL-TIME COUNTER
16-CH 12-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
(RTC)
3
PTH0/FTM2CH0
3
CYCLIC REDUNDANCY
CHECK (CRC)
PTH1/FTM2CH1
4
PTH2/BUSOUT
PTH6
PTH7
1. PTA2 and PTA3 operate as true open drain when working as output .
2. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin.
3. PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 and PTH1 can provide high sink/source current drive.
4. The frequency of the clock from BUSOUT must be equal or less than 10 MHz with 25 pF loading at PAD.
5. The secondary power pair of V and V (pin 41 and pin 40 in 64-pin packages) and the third V (pin 13 in 64-pin packages) are not bonded
DD
SS
SS
in 32-pin packages.
Figure 1. MCU block diagram
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
5
Orderable part numbers
2 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this
document.
Table 1. Ordering information
Feature
MC9S08PA60(A)
VLF
MC9S08PA32(A)
VLF
Part
VLH
VQH
VLD
VLC
VLH
VQH
VLD
VLC
Number
Max.
frequency
(MHz)
20
60
20
60
4
20
60
20
60
4
20
60
4
20
32
4
20
32
4
20
32
20
32
4
20
32
4
Flash
memory
(KB)
RAM (KB) 4
4
4
EEPROM 256
(B)
256
256
256
256
256
256
256
256
256
12-bit
ADC
16ch
16ch
12ch
12ch
12ch
16ch
16ch
12ch
12ch
12ch
16-bit
6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch
FlexTimer +2ch
+2ch
+2ch
+2ch
+2ch
+2ch
+2ch
+2ch
+2ch
+2ch
8-bit
2
2
2
2
2
2
2
2
2
2
Modulo
timer
ACMP
RTC
1
1
1
1
1
1
1
1
1
1
Yes
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
16-bit SPI 1
8-bit SPI
I2C
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI (LIN
Capable)
3
3
3
2
3
3
3
3
2
Watchdog Yes
Yes
Yes
8
Yes
Yes
6
Yes
Yes
6
Yes
Yes
4
Yes
Yes
8
Yes
Yes
8
Yes
Yes
6
Yes
Yes
6
Yes
Yes
4
CRC
Yes
8
20mA
high-drive
pins
KBI pins 16
GPIO 57
16
57
16
41
12
37
12
28
16
57
16
57
16
41
12
37
12
28
Package 64-LQFP 64-QFP
48-LQFP 44-LQFP 32-LQFP 64-LQFP 64-QFP
48-LQFP 44-LQFP 32-LQFP
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
6
NXP Semiconductors
Part identification
3 Part identification
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.2 Format
Part numbers for this device have the following format:
MC 9 S08 PA AA (V) B CC
3.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
• MC = fully qualified, general market flow
• 9 = flash based
MC
9
Qualification status
Memory
S08
PA
AA
Core
• S08 = 8-bit CPU
Device family
• PA
Approximate flash size in KB
• 60 = 60 KB
• 32 = 32 KB
(V)
Mask set version
• (blank) = Any version
• A = Rev. 2 or later version, this is
recommended for new design
B
Operating temperature range (°C)
Package designator
• V = –40 to 105
CC
• QH = 64-pin QFP
• LH = 64-pin LQFP
• LF = 48-pin LQFP
• LD = 44-pin LQFP
• LC = 32-pin LQFP
3.4 Example
This is an example part number:
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
7
Parameter Classification
MC9S08PA60VQH
4 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
5 Ratings
5.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
8
NXP Semiconductors
Ratings
5.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-6000
-500
Max.
+6000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105 °C
1
2
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
5.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in below table may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Symbol
VDD
Description
Min.
–0.3
—
Max.
6.0
Unit
V
Supply voltage
IDD
Maximum current into VDD
120
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, XTAL, or true
open drain pin PTA2 and PTA3)
–0.3
VDD + 0.3
Digital input voltage (true open drain pin PTA2 and PTA3)
Analog1, RESET, EXTAL, and XTAL input voltage
-0.3
–0.3
–25
6
VDD + 0.3
25
V
V
VAIO
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 is only
clamped to VSS
.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
9
General
6 General
6.1 Nonswitching electrical specifications
6.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 3. DC characteristics
Symbol
—
C
—
P
Descriptions
Operating voltage
Output high All I/O pins, standard- 5 V, Iload
Min
2.7
Typical1
Max
5.5
—
Unit
V
—
—
—
VOH
=
=
=
=
VDD - 0.8
V
voltage
drive strength
-5 mA
C
P
C
D
3 V, Iload
-2.5 mA
VDD - 0.8
VDD - 0.8
VDD - 0.8
—
—
—
—
—
—
V
V
High current drive
pins, high-drive
strength2
5 V, Iload
-20 mA
3 V, Iload
-10 mA
V
IOHT
Output high
current
Max total IOH for all
ports
5 V
3 V
—
—
—
—
—
—
-100
-50
mA
VOL
P
C
P
C
D
Output low All I/O pins, standard- 5 V, Iload = 5
0.8
V
V
voltage
drive strength
mA
3 V, Iload
2.5 mA
=
—
—
—
—
—
—
0.8
0.8
0.8
High current drive
pins, high-drive
strength2
5 V, Iload
=20 mA
V
3 V, Iload
10 mA
=
V
IOLT
VIH
VIL
Output low
current
Max total IOL for all
ports
5 V
—
—
—
—
—
—
—
—
—
100
mA
3 V
50
P
C
P
C
C
Input high
voltage
All digital inputs
All digital inputs
All digital inputs
VDD>4.5V
VDD>2.7V
VDD>4.5V
VDD>2.7V
—
0.70 × VDD
0.75 × VDD
—
—
—
V
V
Input low
voltage
0.30 × VDD
0.35 × VDD
—
—
Vhys
|IIn|
Input
0.06 × VDD
mV
µA
hysteresis
P
Input leakage
current
All input only pins
(per pin)
VIN = VDD or
VSS
—
0.1
1
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
10
NXP Semiconductors
Nonswitching electrical specifications
Table 3. DC characteristics (continued)
Symbol
|IOZ
C
Descriptions
Min
Typical1
Max
Unit
|
P
Hi-Z (off-
state) leakage
current
All input/output (per VIN = VDD or
—
0.1
1
µA
pin)
VSS
|IOZTOT
|
C
P
Total leakage All input only and I/O VIN = VDD or
—
—
—
—
2
µA
kΩ
combined for
all inputs and
Hi-Z pins
VSS
—
RPU
Pullup
resistors
All digital inputs,
when enabled (all I/O
pins other than PTA2
and PTA3)
30.0
50.0
60.0
3
RPU
P
D
Pullup
PTA2 and PTA3 pin
—
30.0
kΩ
resistors
IIC
DC injection
current4, 5, 6
Single pin limit
VIN < VSS
VIN > VDD
,
-0.2
-5
—
—
2
mA
Total MCU limit,
includes sum of all
stressed pins
25
CIn
C
C
Input capacitance, all pins
RAM retention voltage
—
—
—
—
—
7
pF
V
VRAM
2.0
—
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD
.
5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large one.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is
very low (which would reduce overall power consumption).
Table 4. LVD and POR Specification
Symbol
VPOR
C
D
C
Description
Min
1.5
4.2
Typ
1.75
4.3
Max
2.0
Unit
V
POR re-arm voltage1, 2
VLVDH
Falling low-voltage detect
threshold - high range (LVDV
= 1)3
4.4
V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
C
C
C
C
Falling low- Level 1 falling
4.3
4.5
4.6
4.7
4.4
4.5
4.6
4.7
4.5
4.6
4.7
4.8
V
V
V
V
voltage
warning
threshold -
high range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
Level 4 falling
(LVWV = 11)
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
11
Nonswitching electrical specifications
Table 4. LVD and POR Specification (continued)
Symbol
C
Description
Min
Typ
Max
Unit
VHYSH
C
High range low-voltage
—
100
—
mV
detect/warning hysteresis
VLVDL
C
Falling low-voltage detect
threshold - low range (LVDV =
0)
2.56
2.61
2.66
V
VLVDW1L
VLVDW2L
VLVDW3L
VLVDW4L
VHYSDL
VHYSWL
VBG
C
C
C
C
C
C
P
Falling low- Level 1 falling
2.62
2.72
2.82
2.92
—
2.7
2.8
2.9
3.0
40
2.78
2.88
2.98
3.08
—
V
V
voltage
warning
threshold -
low range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
V
Level 4 falling
(LVWV = 11)
V
Low range low-voltage detect
hysteresis
mV
mV
V
Low range low-voltage
warning hysteresis
Buffered bandgap output 4
—
80
—
1.14
1.16
1.18
1. Maximum is highest voltage that POR is guaranteed.
2. POR ramp time must be longer than 20us/V to get a stable startup.
3. Rising thresholds are falling threshold + hysteresis.
4. Voltage factory trimmed at VDD = 5.0 V, Temp = 25 °C
VDD-VOH(V)
IOH(mA)
Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
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NXP Semiconductors
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 3. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
VDD-VOH(V)
IOH(mA)
Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
13
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 5. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
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14
NXP Semiconductors
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 7. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
15
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 9. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)
6.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 5. Supply current characteristics
Num
C
C
C
Parameter
Symbol Bus Freq
VDD (V)
Typical1
12.6
7.2
Max
—
Unit
Temp
1
Run supply current FEI
mode, all modules on; run
from flash
RIDD
RIDD
RIDD
20 MHz
10 MHz
1 MHz
5
mA -40 to 105 °C
mA -40 to 105 °C
mA -40 to 105 °C
—
2.4
—
C
C
20 MHz
10 MHz
1 MHz
3
5
3
5
9.6
—
6.1
—
2.1
—
2
3
C
C
Run supply current FEI
mode, all modules off &
gated; run from flash
20 MHz
10 MHz
1 MHz
10.5
6.2
—
—
2.3
—
C
C
20 MHz
10 MHz
1 MHz
7.4
—
5.0
—
2.0
—
P
C
Run supply current FBE
mode, all modules on; run
from RAM
20 MHz
10 MHz
1 MHz
12.1
6.5
14.8
—
1.8
—
Table continues on the next page...
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16
NXP Semiconductors
Nonswitching electrical specifications
Table 5. Supply current characteristics (continued)
Num
C
P
Parameter
Symbol Bus Freq
20 MHz
VDD (V)
Typical1
Max
11.8
—
Unit
Temp
3
9.1
C
10 MHz
5.5
1 MHz
1.5
—
4
P
C
Run supply current FBE
mode, all modules off &
gated; run from RAM
RIDD
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
—
5
3
5
3
9.8
12.3
—
mA -40 to 105 °C
5.4
1.6
—
P
C
6.9
9.2
—
4.4
1.4
—
5
C
C
Wait mode current FEI
mode, all modules on
WIDD
7.8
—
mA -40 to 105 °C
4.5
—
1.3
—
C
5.1
—
3.5
—
1.2
—
6
7
C
C
Stop3 mode supply
current no clocks active
(except 1 kHz LPO
clock)2, 3
S3IDD
5
3
1.45
1.4
—
µA
µA
-40 to 105 °C
-40 to 105 °C
—
—
C
C
ADC adder to stop3
ADLPC = 1
—
—
5
3
44
40
—
—
-40 to 105 °C
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
LVD adder to stop34
8
C
C
—
—
5
3
130
125
—
—
µA
-40 to 105 °C
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.
3. ACMP adder cause <10 µA IDD increase typically.
4. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.
6.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should
consult NXP applications notes such as AN2321, AN1050, AN1263, AN2764, and
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
17
Switching specifications
6.1.3.1 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors for 64-pin SOIC package
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
12
10
4
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
5
VRE_IEC
N
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 5.0 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 20 MHz, fBUS = 20 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
6.2 Switching specifications
6.2.1 Control timing
Table 7. Control timing
Num
C
P
P
D
Rating
Bus frequency (tcyc = 1/fBus
Symbol
fBus
Min
DC
Typical1
Max
20
Unit
MHz
KHz
ns
1
2
3
)
—
1.0
—
Internal low power oscillator frequency
External reset pulse width2
fLPO
0.67
1.25
—
textrst
1.5 ×
tcyc
4
5
D
D
Reset low drive
trstdrv
34 × tcyc
500
—
—
—
—
ns
ns
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
6
7
D
D
BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes3
tMSH
tILIH
100
100
—
—
—
—
ns
ns
IRQ pulse width
Asynchronous
path2
D
D
Synchronous path4
tIHIL
tILIH
1.5 × tcyc
100
—
—
—
—
ns
ns
8
Keyboard interrupt pulse
width
Asynchronous
path2
D
Synchronous path
tIHIL
1.5 × tcyc
—
—
ns
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
18
NXP Semiconductors
Switching specifications
Table 7. Control timing (continued)
Num
C
C
C
Rating
Symbol
tRise
Min
—
Typical1
10.2
Max
—
Unit
ns
9
Port rise and fall time -
standard drive strength
(load = 50 pF)5
—
—
tFall
—
9.5
—
ns
C
C
Port rise and fall time -
high drive strength (load =
50 pF)5
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD
.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% VDD and 80% VDD levels in operating temperature range.
textrst
RESET PIN
Figure 10. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 11. IRQ/KBIPx timing
6.2.2 Debug trace timing specifications
Table 8. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
MHz
ns
tcyc
twl
twh
tr
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
—
—
3
ns
tf
3
ns
ts
—
—
ns
th
Data hold
2
ns
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
19
Switching specifications
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 12. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 13. Trace data specifications
6.2.3 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 9. FTM input timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock
frequency
fTCLK
0
fBus/4
Hz
2
3
4
5
D
D
D
D
External clock
period
tTCLK
tclkh
4
—
—
—
—
tcyc
tcyc
tcyc
tcyc
External clock
high time
1.5
1.5
1.5
External clock
low time
tclkl
Input capture
pulse width
tICPW
tTCLK
tclkh
TCLK
tclkl
Figure 14. Timer external clock
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NXP Semiconductors
Thermal specifications
tICPW
FTMCHn
FTMCHn
tICPW
Figure 15. Timer input capture pulse
6.3 Thermal specifications
6.3.1 Thermal operating requirements
Table 10. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
Unit
°C
Die junction temperature
Ambient temperature
125
105
TA
°C
NOTE
Maximum TA can be exceeded only if the user ensures that TJ
does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
6.3.2 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
21
Peripheral operating requirements and behaviors
Table 11. Thermal attributes
Board type
Symbo
l
Description
64
LQFP
64 QFP
48
LQFP
44
LQFP
32
LQFP
Unit
Notes
Single-layer (1S)
RθJA Thermal resistance,
junction to ambient (natural
71
53
59
46
61
81
57
68
50
75
53
62
47
86
57
72
51
°C/W
1, 2
convection)
Four-layer (2s2p)
RθJA Thermal resistance,
47
50
41
°C/W
°C/W
°C/W
1, 3
1, 3
1, 3
junction to ambient (natural
convection)
Single-layer (1S) RθJMA Thermal resistance,
junction to ambient (200 ft./
min. air speed)
Four-layer (2s2p) RθJMA Thermal resistance,
junction to ambient (200 ft./
min. air speed)
—
—
—
RθJB Thermal resistance,
junction to board
35
20
5
32
23
8
34
24
6
34
20
5
33
24
6
°C/W
°C/W
°C/W
4
5
6
RθJC Thermal resistance,
junction to case
ΨJT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
7 Peripheral operating requirements and behaviors
7.1 External oscillator (XOSC) and ICS characteristics
Table 12. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)
Num
C
C
C
Characteristic
Low range (RANGE = 0)
Symbol
Min
31.25
4
Typical1
32.768
—
Max
39.0625
20
Unit
kHz
1
Oscillator
crystal or
resonator
flo
fhi
High range (RANGE = 1)
FEE or FBE mode2
MHz
C
High range (RANGE = 1),
high gain (HGO = 1),
FBELP mode
fhi
4
—
20
MHz
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
22
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 12. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
C
High range (RANGE = 1),
low power (HGO = 0),
FBELP mode
fhi
4
—
20
MHz
2
3
D
D
Load capacitors
C1, C2
RF
See Note3
—
Feedback
resistor
Low Frequency, Low-Power
Mode4
—
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
MΩ
Low Frequency, High-Gain
Mode
10
1
High Frequency, Low-
Power Mode
High Frequency, High-Gain
Mode
1
4
5
D
D
Series resistor -
Low Frequency
Low-Power Mode 4
High-Gain Mode
Low-Power Mode4
RS
RS
—
—
—
—
200
—
—
—
—
kΩ
kΩ
kΩ
Series resistor -
High Frequency
D
D
D
Series resistor -
High
Frequency,
High-Gain Mode
4 MHz
8 MHz
16 MHz
—
—
—
0
0
0
—
—
—
kΩ
kΩ
kΩ
6
C
C
C
C
Crystal start-up
time Low range
= 32.768 kHz
crystal; High
Low range, low power
Low range, high power
High range, low power
High range, high power
tCSTL
—
—
—
—
1000
800
3
—
—
—
—
ms
ms
ms
ms
tCSTH
range = 20 MHz
1.5
crystal5, 6
7
8
T
D
D
Internal reference start-up time
tIRST
fextal
—
0.03125
0
20
—
—
50
5
µs
Square wave
FEE or FBE mode2
MHz
MHz
input clock
frequency
FBELP mode
20
9
P
Average internal reference frequency -
trimmed
fint_t
—
32.768
—
kHz
10
11
P
P
DCO output frequency range - trimmed
fdco_t
16
—
—
—
20
MHz
Total deviation
of DCO output
from trimmed
frequency5
Over full voltage and
temperature range
Δfdco_t
2.0
%fdco
C
Over fixed voltage and
temperature range of 0 to
70 °C
1.0
12
13
C
C
FLL acquisition time5, 7
tAcquire
CJitter
—
—
—
2
ms
Long term jitter of DCO output clock
(averaged over 2 ms interval)8
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3. See crystal or resonator manufacturer's recommendation.
4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
23
Peripheral operating requirements and behaviors
5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 16. Typical crystal or resonator circuit
7.2 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 13. Flash clock characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
Vprog/erase
2.7
—
5.5
V
across the operating temperature range
D
D
D
C
Supply voltage for read operation
NVM Bus frequency
VRead
fNVMBUS
fNVMOP
nFLPE
2.7
1
—
—
5.5
20
V
MHz
MHz
Cycles
NVM operating frequency
0.8
10 k
1.0
1.05
—
FLASH Program/erase endurance TL to
TH in the operating temperature range
100 k
C
C
EEPROM Program/erase endurance TL
to TH in the operating temperature
range
nFLPE
50 k
15
500 k
100
—
—
Cycles
years
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
24
NXP Semiconductors
Peripheral operating requirements and behaviors
All timing parameters are a function of the bus clock frequency, FNVMBUS. All program
and erase times are also a function of the NVM operating frequency, fNVMOP
.
Each command timing is given by:
tcommand=fNVMOP cycle × 1/fNVMOP + fNVMBUS cycle × 1/fNVMBUS
Table 14. Flash timing characteristics
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Characteristic
Erase Verify All Blocks
Erase Verify Flash Block
Erase Verify EEPROM Block
Erase Verify Flash Section
Erase Verify EEPROM Section
Read Once
Symbol
tVFYALL
tRD1BLK
tRD1BLK
tRD1SEC
tDRD1SEC
tRDONCE
tPGM2
fNVMOP cycle
fNVMBUS cycle
17338
16913
810
—
—
—
—
484
—
555
—
450
Program Flash (2 word)
Program Flash (4 word)
Program Once
68
1397
2128
2090
1371
2120
2869
3618
17743
17236
868
tPGM4
122
122
47
tPGMONCE
tDPGM1
tDPGM2
tDPGM3
tDPGM4
tERSALL
tERSBLK
tERSPG
Program EEPROM (1 Byte)
Program EEPROM (2 Byte)
Program EEPROM (3 Byte)
Program EEPROM (4 Byte)
Erase All Blocks
94
141
188
100066
100060
20015
5015
100066
—
Erase Flash Block
Erase Flash Sector
Erase EEPROM Sector
Unsecure Flash
tDERSPG
tUNSECU
tVFYKEY
tMLOADU
756
17730
464
Verify Backdoor Access Key
Set User Margin Level
—
407
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Memory section.
7.3 Analog
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
25
Peripheral operating requirements and behaviors
7.3.1 ADC characteristics
Table 15. 5 V 12-bit ADC operating conditions
Characteri
stic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply
voltage
Absolute
VDDA
ΔVDDA
ΔVSSA
2.7
—
0
5.5
V
—
Delta to VDD (VDD-VDDAD
)
-100
-100
+100
+100
mV
mV
2
Ground
voltage
Delta to VSS (VSS-VSSA
)
0
Input
voltage
VADIN
CADIN
RADIN
RAS
VREFL
—
—
4.5
3
VREFH
5.5
V
Input
capacitance
pF
kΩ
kΩ
Input
resistance
—
5
—
Analog
source
resistance
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
External to
MCU
—
—
—
—
2
5
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
—
—
5
•
•
10
10
8-bit mode
(all valid fADCK
)
ADC
conversion
clock
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
0.4
0.4
—
—
8.0
4.0
MHz
—
frequency
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
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26
NXP Semiconductors
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ZAS
leakage
due to
input
ADC SAR
ENGINE
R AS
R ADIN
protection
v ADIN
C AS
v AS
R ADIN
R ADIN
R ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C ADIN
Figure 17. ADC input impedance equivalency diagram
Table 16. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA
)
Characteristic
Supply current
ADLPC = 1
Conditions
C
Symb
Min
Typ1
Max
Unit
T
IDDA
—
133
—
µA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
T
T
T
IDDA
—
—
—
218
327
582
—
—
µA
µA
µA
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
IDDA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
IDDAD
990
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset, module
off
T
P
IDDA
—
2
0.011
3.3
1
5
µA
ADC asynchronous High speed (ADLPC
fADACK
MHz
clock source
= 0)
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
27
Peripheral operating requirements and behaviors
Table 16. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
Low power (ADLPC
= 1)
1.25
2
3.3
Conversion time
(including sample
time)
Short sample
(ADLSMP = 0)
T
tADC
—
—
—
—
20
40
—
—
—
—
ADCK
cycles
Long sample
(ADLSMP = 1)
Sample time
Short sample
(ADLSMP = 0)
T
tADS
3.5
23.5
ADCK
cycles
Long sample
(ADLSMP = 1)
Total unadjusted
Error2
12-bit mode
10-bit mode
8-bit mode
T
P
P
T
P
P
T
T
T
C
P
P
T
T
T
D
D
D
ETUE
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
1.5
—
LSB3
LSB3
LSB3
LSB3
LSB3
2.0
1.0
—
0.7
Differential Non-
Linearity
12-bit mode
10-bit mode4
8-bit mode4
1.0
0.25
0.15
1.0
0.5
0.25
—
Integral Non-Linearity 12-bit mode
10-bit mode
0.3
0.5
0.25
—
8-bit mode
0.15
2.0
Zero-scale error5
Full-scale error6
Quantization error
12-bit mode
10-bit mode
8-bit mode
EZS
0.25
0.65
2.5
1.0
1.0
—
12-bit mode
10-bit mode
8-bit mode
EFS
0.5
1.0
1.0
0.5
0.5
≤12 bit modes
EQ
EIL
m
—
LSB3
mV
Input leakage error7 all modes
IIn * RAS
3.266
3.638
1.396
Temp sensor slope
-40°C– 25°C
25°C– 125°C
—
—
—
—
—
—
mV/°C
Temp sensor voltage 25°C
D
VTEMP25
V
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization.
3. 1 LSB = (VREFH - VREFL)/2N
4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
5. VADIN = VSSA
6. VADIN = VDDA
7. IIn = leakage current (refer to DC characteristics)
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
28
NXP Semiconductors
Peripheral operating requirements and behaviors
7.3.2 Analog comparator (ACMP) electricals
Table 17. Comparator electrical specifications
C
D
T
Characteristic
Supply voltage
Symbol
VDDA
IDDA
VAIN
VAIO
VH
Min
2.7
Typical
—
Max
5.5
20
Unit
V
Supply current (Operation mode)
Analog input voltage
—
10
µA
V
D
P
C
C
T
VSS - 0.3
—
—
VDDA
40
Analog input offset voltage
Analog comparator hysteresis (HYST=0)
Analog comparator hysteresis (HYST=1)
Supply current (Off mode)
Propagation Delay
—
mV
mV
mV
nA
µs
—
15
20
VH
—
20
30
IDDAOFF
tD
—
60
—
C
—
0.4
1
7.4 Communication interfaces
7.4.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
high drive strength is enabled for SPI output pins.
Table 18. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
2 x tBus
2048 x tBus
ns
tSPSCK
tSPSCK
ns
tBus = 1/fBus
1/2
—
—
—
—
—
—
—
—
—
4
1/2
—
5
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
1024 x tBus
6
tSU
tHI
tv
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
15
0
—
—
ns
7
ns
8
—
0
25
ns
9
tHO
tRI
—
ns
10
—
tBus - 25
ns
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
29
Peripheral operating requirements and behaviors
Table 18. SPI master mode timing (continued)
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
tFI
Fall time input
Rise time output
Fall time output
11
tRO
tFO
—
25
ns
—
1
SS
(OUTPUT)
3
2
10
10
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
11
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI master mode timing (CPHA=1)
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
30
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 19. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in .
2
3
4
5
6
7
8
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
4 x tBus
—
—
ns
tBus
tBus
ns
tBus = 1/fBus
1
1
—
—
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
15
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
25
—
ns
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
12
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA = 0)
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
31
Dimensions
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 21. SPI slave mode timing (CPHA=1)
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
32-pin LQFP
Then use this document number
98ASH70029A
44-pin LQFP
98ASS23225W
48-pin LQFP
98ASH00962A
64-pin QFP
98ASB42844B
64-pin LQFP
98ASS23234W
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
32
NXP Semiconductors
Pinout
9 Pinout
9.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 20. Pin availability by package pin-count
Pin Number
Lowest Priority <-- --> Highest
64-LQFP
48-LQFP 44-LQFP 32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
64-QFP
1
1
2
1
2
1
2
PTD11
PTD01
PTH7
PTH6
PTE7
PTH2
—
KBI1P1
FTM2CH3
FTM2CH2
—
MOSI1
SPSCK1
—
—
—
2
KBI1P0
3
—
—
3
—
—
3
—
—
—
—
3
—
—
4
—
—
—
—
5
—
TCLK2
BUSOUT
—
—
—
6
4
4
—
—
—
7
5
5
—
—
VDD
VREFH
VREFL
VSS
EXTAL
XTAL
VSS
—
8
6
6
4
—
—
—
VDDA
VSSA
—
9
7
7
5
—
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8
8
6
—
—
—
9
9
7
PTB7
PTB6
—
—
—
SCL
—
10
11
—
—
12
13
14
15
16
17
18
19
20
21
22
—
10
11
—
—
—
—
12
13
14
15
16
17
18
19
20
—
8
SDA
—
—
—
—
—
—
9
—
—
—
PTH11
PTH01
PTE6
PTE5
PTB51
PTB41
PTC3
PTC2
PTD7
PTD6
PTD5
PTC1
PTC0
PTF7
—
FTM2CH1
FTM2CH0
—
—
—
—
—
—
—
—
—
—
—
—
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
KBI1P7
KBI1P6
KBI1P5
—
SS0
—
—
10
11
12
—
—
—
13
14
—
MISO0
—
—
—
ADP11
ADP10
—
—
—
—
TXD2
RXD2
—
—
—
—
—
—
FTM2CH1
FTM2CH0
—
ADP9
ADP8
ADP15
—
—
—
—
—
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
33
Pinout
Table 20. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
64-LQFP
64-QFP
28
48-LQFP 44-LQFP 32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
—
—
—
23
24
25
26
—
—
27
28
29
30
31
—
—
32
33
34
35
36
37
38
39
40
41
42
—
—
—
—
43
44
45
46
47
48
—
—
—
21
22
23
24
—
—
25
26
—
27
28
—
—
29
30
31
32
33
34
35
36
37
—
38
—
—
—
—
39
40
41
42
43
44
—
—
—
15
16
17
18
—
—
19
20
—
—
—
—
—
—
21
22
23
24
25
26
27
28
—
—
—
—
—
—
—
—
29
30
31
32
PTF6
PTF5
PTF4
PTB3
PTB2
PTB1
PTB0
PTF3
PTF2
PTA7
PTA6
PTE4
—
—
—
—
ADP14
ADP13
ADP12
ADP7
ADP6
ADP5
ADP4
—
—
—
29
—
30
—
—
—
31
KBI0P7
MOSI0
SPSCK0
TXD0
RXD0
—
—
32
KBI0P6
—
33
KBI0P5
—
34
KBI0P4
—
35
—
—
36
—
—
—
—
37
FTM2FAULT2
—
ADP3
ADP2
—
—
38
FTM2FAULT1
—
—
39
—
—
—
—
40
—
—
VSS
VDD
—
41
—
—
—
—
42
PTF1
PTF0
PTD4
PTD3
PTD2
PTA32
PTA22
PTA1
PTA0
PTC7
PTC6
PTE3
PTE2
PTG3
PTG2
PTG1
PTG0
PTE11
PTE01
PTC5
PTC4
PTA5
PTA4
—
—
—
43
—
—
—
—
44
KBI1P4
KBI1P3
KBI1P2
KBI0P3
KBI0P2
KBI0P1
KBI0P0
—
—
—
—
45
SS1
—
—
46
MISO1
TXD0
RXD0
FTM0CH1
FTM0CH0
TxD1
RxD1
SS0
—
—
47
SCL
SDA
ACMP1
ACMP0
—
—
48
—
49
ADP1
ADP0
—
50
51
52
—
—
—
53
—
—
—
54
—
MISO0
—
—
—
55
—
—
—
56
—
—
—
—
57
—
—
—
—
58
—
—
—
—
59
—
MOSI0
SPSCK0
FTM1CH1
FTM1CH0
TCLK0
ACMPO
—
—
60
—
TCLK1
—
—
61
—
—
62
—
RTCO
—
—
63
IRQ
—
RESET
MS
64
BKGD
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
34
NXP Semiconductors
Pinout
1. This is a high current drive pin when operated as output.
2. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. The table above
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
9.2 Device pin assignment
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
35
Pinout
2
1
1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTA2/KBI0P2/RxD0/SDA
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
2
PTA3/KBI0P3/TxD0/SCL
PTD2/KBI1P2/MISO1
PTD3/KBI1P3/SS1
PTD4/KBI1P4
PTF0
PTH7
PTH6
3
4
PTE7/TCLK2
PTH2/BUSOUT
5
6
V
7
PTF1
DD
8
V
DD
V
DDA /V
REFH
9
V
SS
V
SSA /V
REFL
V
10
11
12
13
14
15
16
PTE4
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
PTF2
V
SS
1
PTF3
PTH1/FTM2CH1
1
PTB0/KBI0P4/RxD0/ADP4
PTB1/KBI0P5/TxD0/ADP5
PTH0/FTM2CH0
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 22. MC9S08PA60 64-pin QFP and LQFP package
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
36
NXP Semiconductors
Pinout
1
1
2
1
2
36
35
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
PTA2/KBI0P2/RxD0/SDA
2
PTA3/KBI0P3/TxD0/SCL
3
PTE7/TCLK2
34 PTD2/KBI1P2/MISO1
33
PTD3/KBI1P3/SS1
32 PTD4/KBI1P4
4
PTH2/BUSOUT
5
V
DD
REFH
SSA /V
6
31
30
V
DD
V
SS
V
DDA /V
7
V
REFL
8
29 PTE4
28 PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
V
SS
9
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
10
11
12
27
V
SS
26 PTB0/KBI0P4/RxD0/ADP4
25 PTB1/KBI0P5/TxD0/ADP5
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 23. MC9S08PA60 48-pin LQFP package
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
37
Pinout
2
1
1
33
32
31
30
29
28
27
26
25
24
23
1
2
PTA2/KBI0P2/RxD0/SDA
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
PTA3/KBI0P3/TxD0/SCL2
PTD2/KBI1P2/MISO1
PTD3/KBI1P3/SS1
PTD4/KBI1P4
3
PTE7/TCLK2
4
PTH2/BUSOUT
5
V
DD
REFH
SSA /V
6
V
V
V
DDA /V
DD
7
V
SS
REFL
8
PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
PTB0/KBI0P4/RxD0/ADP4
PTB1/KBI0P5/TxD0/ADP5
V
SS
9
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
10
11
V
SS
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 24. MC9S08PA60 44-pin LQFP package
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
38
NXP Semiconductors
Revision history
1
1
2
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PTA2/KBI0P2/RxD0/SDA
PTA3/KBI0P3/TxD0/SCL2
PTD2/KBI1P2/MISO1
V
DD
PTD3/KBI1P3/SS1
V
DDA /V
REFH
PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
PTB0/KBI0P4/RxD0/ADP4
PTB1/KBI0P5/TxD0/ADP5
V
SSA /V
REFL
V
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
1. High source/sink current pins
2. True open drain pins
Figure 25. MC9S08PA60 32-pin LQFP package
10 Revision history
The following table provides a revision history for this document.
Table 21. Revision history
Rev. No.
Date
Substantial Changes
1
2
10/2012
09/2014
Initial public release
• Updated VOH and VOL in DC characteristics
• footnote on the S3IDD in Supply current characteristics
• Added EMC radiated emissions operating behaviors
• Updated the typical of fint_t to 31.25 kHz and updated footnote to
tAcquire in External oscillator (XOSC) and ICS characteristics
• Updated the assumption for all the timing values in SPI switching
specifications
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
NXP Semiconductors
39
Revision history
Rev. No.
Table 21. Revision history (continued)
Date
Substantial Changes
• Updated the rating descriptions for tRise and tFall in Control timing
• Updated the part number format to add new field for new part
numbers in Fields
3
4
06/2015
09/2019
• Corrected the Min. of the textrst in Control timing
• Added new section of Thermal operating requirements, Updated
Thermal characteristics to remove redundant information.
• Added MCU block diagram.
• Added new section of Orderable part numbers
• Updated flash characteristics in the NVM specifications
• Updated S3IDD values in the Supply current characteristics
MC9S08PA60 Series Data Sheet, Rev. 4, 09/2019
40
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Document Number MC9S08PA60
Revision 4, 09/2019
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