MC9S08SE4VTG [NXP]
暂无描述;
| 型号： | MC9S08SE4VTG |
| 厂家： | 
NXP |
| 描述： | 暂无描述 |
| 文件： | 总35页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08SE8
Rev. 4, 4/2015
MC9S08SE8
28-Pin SOIC
Case 751F
16-Pin TSSOP
Case 948F-01
28-Pin PDIP
Case 710-02
MC9S08SE8 Series
Covers: MC9S08SE8
MC9S08SE4
Features:
– SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended
break detection; wakeup on active edge
– ADC — 10-channel, 10-bit resolution; 2.5 μs
conversion time; automatic compare function;
1.7 mV/°C temperature sensor; internal bandgap
reference channel; runs in stop3
• 8-Bit HCS08 Central Processor Unit (CPU)
– 20 MHz HCS08 CPU (central processor unit)
– 10 MHz internal bus frequency
– HC08 instruction set with added BGND
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– TPMx — One 2-channel (TPM1) and one 1-channel
(TPM2) 16-bit timer/pulse-width modulator (TPM)
modules; selectable input capture, output compare, and
edge-aligned PWM capability on each channel; timer
module may be configured for buffered, centered PWM
(CPWM) on all channels
– Up to 8 KB of on-chip in-circuit programmable flash
memory with block protection and security options
– Up to 512 bytes of on-chip RAM
• Power-Saving Modes
– Wait plus two stops
• Clock Source Options
– KBI — 8-pin keyboard interrupt module
– RTC — Real-time counter with binary- or
decimal-based prescaler
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
• Input/Output
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage;
supports bus frequencies from 1 MHz to 10 MHz.
• System Protection
– Software selectable pullups on ports when used as inputs
– Software selectable slew rate control on ports when used
as outputs
– Software selectable drive strength on ports when used as
outputs
– Master reset pin and power-on reset (POR)
– Internal pullup on RESET, IRQ, and BKGD/MS pins to
reduce customer system cost
– Optional computer operating properly (COP) reset with
option to run from independent 1 kHz internal clock
source or the bus clock
– Low voltage detection
– Illegal opcode detection with reset
• Package Options
– 28-pin PDIP
– 28-pin SOIC
– 16-pin TSSOP
– Illegal address detection with reset
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2009, 2015. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.8 Internal Clock Source (ICS) Characteristics . . . . . . . . 20
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2 TPM/MTIM Module Timing. . . . . . . . . . . . . . . . 26
3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7
3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .8
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .19
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to: freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
2
10/8/2008
1/16/2009
Initial public released.
In Table 8, added the Max. of S2IDD and S3IDD in 0–105 °C; changed the Max. of S2IDD and
S3IDD in 0–85 °C; changed the typical of S2IDD and S3IDD; changed the S23IDDRTI to P.
3
4/7/2009
Added |IOZTOT| in the Table 7.
Changed VDDAD to VDDA, VSSAD to VSSA
.
Updated Table 9, Table 10, Table 11, and Table 12.
Updated Figure 13 and Figure 14.
4
4/10/2015
Updated Table 9.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08SE8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08SE8 series MCUs.
HCS08 CORE
BKGD/MS
DEBUG MODULE (DBG)
BDC
CPU
HCS08 SYSTEM CONTROL
REAL-TIME COUNTER (RTC)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTA7/TPM1CH1/ADP5
PTA6/TPM1CH0/ADP4
PTA5/IRQ/TCLK/RESET
PTA4/BKGD/MS
IRQ
COP
IRQ
LVD
KBIP7–KBIP0
KEYBOARD INTERRUPT
MODULE (KBI)
PTA3/KBIP3/ADP3
TCLK
USER FLASH
(MC9S08SE8 = 8192 BYTES)
(MC9S08SE4 = 4096 BYTES)
PTA2/KBIP2/ADP2
2-CHANNEL TIMER/PWM
MODULE (TPM1)
TPM1CH1–TPM1CH0
PTA1/KBIP1/TPM1CH1/ADP1
PTA0/KBIP0/TPM1CH0/ADP0
PTB7/EXTAL
USER RAM
RxD
TxD
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
(MC9S08SE8 = 512 BYTES)
PTB6/XTAL
(MC9S08SE4 = 256 BYTES)
PTB5
TCLK
PTB4/TPM2CH0
PTB3/KBIP7/ADP9
PTB2/KBIP6/ADP8
PTB1/KBIP5/TxD/ADP7
PTB0/KBIP4/RxD/ADP6
1-CHANNEL TIMER/PWM
MODULE (TPM2)
20 MHz INTERNAL CLOCK
SOURCE (ICS)
TPM2CH0
EXTAL
XTAL
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
VSS
VDD
VOLTAGE REGULATOR
VSSA
VSSA/VREFL
VDDA/VREFH
10-CHANNEL, 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ADP9–ADP0
V
DDA
VREFL
VREFH
pins not available on 16-pin package
Notes:
When PTA4 is configured as BKGD, pin is bi-directional.
For the 16-pin package: VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.
Figure 1. MC9S08SE8 Series Block Diagram
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
3
Pin Assignments
2
Pin Assignments
This chapter shows the pin assignments in the packages available for the MC9S08SE8 series.
Table 1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest Priority --> Highest
(Package)
28
16
(TSSOP)
Port Pin
PTC5
Alt 1
Alt 2
Alt 3
(SOIC/PDIP)
1
—
—
1
2
PTC4
PTA5
PTA4
3
IRQ
TCLK
RESET
4
2
BKGD
MS
5
3
VDD
6
—
—
4
VDDA
VSSA
VREFH
VREFL
VSS
7
8
9
5
PTB7
PTB6
PTB5
PTB4
PTC3
PTC2
PTC1
PTC0
PTB3
PTB2
PTB1
PTB0
PTA7
PTA6
PTA3
PTA2
PTA1
PTA0
PTC7
PTC6
EXTAL
XTAL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
6
7
8
TPM2CH0
—
—
—
—
9
KBIP7
KBIP6
KBIP5
KBIP4
ADP9
ADP8
ADP7
ADP6
10
11
12
—
—
13
14
15
16
—
—
TxD
RxD
TPM1CH11 ADP5
TPM1CH01 ADP4
ADP3
KBIP3
KBIP2
KBIP1
KBIP0
ADP2
TPM1CH11 ADP1
TPM1CH01 ADP0
1
TPM1 pins can be remapped to PTA7, PTA6 and PTA1,PTA0
MC9S08SE8 Series MCU Data Sheet, Rev. 4
4
Freescale Semiconductor
Pin Assignments
PTC6
PTC5
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PTC7
PTC4
2
3
PTA0/KBIP0/TPM1CH0/ADP0
PTA1/KBIP1/TPM1CH1/ADP1
PTA2/KBIP2/ADP2
PTA5/IRQ/TCLK/RESET
PTA4/BKGD/MS
4
5
VDD
VDDA/VREFH
VSSA/VREFL
VSS
6
PTA3/KBIP3/ADP3
7
PTA6/TPM1CH0/ADP4
8
PTA7/TPM1CH1/ADP5
PTB0/KBIP4/RxD/ADP6
PTB7/EXTAL
PTB6/XTAL
PTB5
9
10
11
12
13
14
PTB1/KBIP5/TxD/ADP7
PTB2/KBIP6/ADP8
PTB4/TPM2CH0
PTC3
PTB3/KBIP7/ADP9
PTC0
PTC2
PTC1
Pins in bold are lost in the next lower pin count package.
Figure 2. MC9S08SE8 Series in 28-Pin PDIP/SOIC Package
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA0/KBIP0/TPM1CH0/ADP0
PTA1/KBIP1/TPM1CH1/ADP1
PTA2/KBIP2/ADP2
PTA5/IRQ/TCLK/RESET
PTA4/BKGD/MS
VDD
VSS
PTA3/KBIP3/ADP3
PTB0/KBIP4/RxD/ADP6
PTB7/EXTAL
PTB6/XTAL
PTB5
PTB1/KBIP5/TxD/ADP7
PTB2/KBIP6/ADP8
PTB3/KBIP7/ADP9
PTB4/TPM2CH0
Figure 3. MC9S08SE8 in 16-Pin TSSOP Package
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
5
Electrical Characteristics
3
Electrical Characteristics
This chapter contains electrical and timing specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable
SS
DD
pull-up resistor associated with the pin is enabled.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
6
Freescale Semiconductor
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
–0.3 to 5.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
ID
25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take P into account in power calculations, determine the difference between actual pin
I/O
voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high
SS
DD
pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
Table 4. Thermal Characteristics
DD
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
TL to TH
–40 to 85
–40 to 105
–40 to 125
C
V
M
TA
°C
°C
Maximum junction temperature
TJM
135
70
28-pin SOIC
Thermal resistance
single-layer board
28-pin PDIP
16-pin TSSOP
28-pin SOIC
28-pin PDIP
16-pin TSSOP
68
°C/W
129
48
θJA
Thermal resistance four-layer
board
49
°C/W
85
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
7
Electrical Characteristics
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
Where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
int
I/O
DD DD
= Power dissipation on input and output pins — user-determined
For most applications, P << P and can be neglected. An approximate relationship between P and T
I/O
int
D
J
(if P is neglected) is:
I/O
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
2
K = P × (T + 273°C) + θ × (P )
Eqn. 3
D
A
JA
D
Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
3.4
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
R1
C
1500
100
3
Ω
pF
—
Ω
Human
body
Storage capacitance
Number of pulses per pin
Series resistance
—
R1
C
0
Machine Storage capacitance
Number of pulses per pin
200
3
pF
—
—
MC9S08SE8 Series MCU Data Sheet, Rev. 4
8
Freescale Semiconductor
Electrical Characteristics
Unit
Table 5. ESD and Latch-up Test Conditions (continued)
Model
Description
Symbol
Value
Minimum input voltage limit
Maximum input voltage limit
—
—
–2.5
7.5
V
V
Latch-up
Table 6. ESD and Latch-up Protection Characteristics
No.
Rating1
Symbol
Min
Max
Unit
1
2
3
4
Human body model (HBM)
Machine model (MM)
VHBM
VMM
VCDM
ILAT
2000
200
500
100
—
—
—
—
V
V
Charge device model (CDM)
Latch-up current at TA = 125 °C
V
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
3.5
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
1 — Operating voltage
Parameter
Symbol
Min
Typical1
Max
Unit
—
2.7
—
5.5
V
Output high voltage — Low drive (PTxDSn = 0)
5 V, ILoad = –2 mA
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
3 V, ILoad = –0.6 mA
5 V, ILoad = –0.4 mA
3 V, ILoad = –0.24 mA
VOH
V
Output high voltage — High drive (PTxDSn = 1)
5 V, ILoad = –10 mA
VDD – 1.5
—
—
—
—
—
—
—
—
2
P
3 V, ILoad = –3 mA
5 V, ILoad = –2 mA
3 V, ILoad = –0.4 mA
VDD – 1.5
VDD – 0.8
VDD – 0.8
Output low voltage — Low drive (PTxDSn = 0)
5 V, ILoad = 2 mA
1.5
1.5
0.8
0.8
—
—
—
—
—
—
—
—
3 V, ILoad = 0.6 mA
5 V, ILoad = 0.4 mA
3 V, ILoad = 0.24 mA
VOL
V
Output low voltage — High drive (PTxDSn = 1)
5 V, ILoad = 10 mA
1.5
1.5
0.8
0.8
—
—
—
—
—
—
—
—
3
4
P
P
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
3 V, ILoad = 0.4 mA
Output high current — Max total IOH for all ports
5 V IOHT
3 V
—
—
—
—
100
60
mA
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
9
Electrical Characteristics
Num C
Table 7. DC Characteristics (continued)
Parameter
Symbol
Min
Typical1
Max
Unit
Output low current — Max total IOL for all ports
5 V IOLT
3 V
5
P
—
—
—
—
100
60
mA
6
7
8
9
P Input high voltage; all digital inputs
P Input low voltage; all digital inputs
P Input hysteresis; all digital inputs
C Input leakage current; input only pins2
VIH
VIL
0.65 × VDD
—
—
—
V
—
0.35 × VDD
Vhys
|IIn|
0.06 × VDD
—
—
1
mV
μA
μA
—
—
0.1
0.1
10 P High impedance (off-state) leakage current2
|IOZ
|
1
Total leakage combined for all inputs and Hi-Z pins
11
C
|IOZTOT
|
—
—
2
μA
— All input only and I/O2
12 P Internal pullup resistors3
13 P Internal pulldown resistors4
RPU
RPD
20
20
45
45
65
65
kΩ
kΩ
DC injection current 5, 6, 7
VIN < VSS, VIN > VDD
Single pin limit
14
D
IIC
mA
–0.2
–5
—
—
0.2
5
Total MCU limit, includes sum of all stressed pins
15 C Input capacitance; all non-supply pins
16 C RAM retention voltage
17 P POR re-arm voltage8
CIn
—
0.6
0.9
10
—
1.0
1.4
—
8
pF
V
VRAM
VPOR
tPOR
—
2.0
—
V
18 D POR re-arm time
μs
Low-voltage detection threshold —
high range
19
20
21
22
23
24
P
P
C
P
P
C
VLVD1
VLVD0
VLVW3
VLVW2
VLVW1
VLVW0
V
V
V
V
V
V
VDD falling
VDD rising
3.9
4.0
4.0
4.1
4.1
4.2
Low-voltage detection threshold —
low range
VDD falling
VDD rising
2.48
2.54
2.56
2.62
2.64
2.70
Low-voltage warning threshold —
high range 1
VDD falling
VDD rising
4.5
4.6
4.6
4.7
4.7
4.8
Low-voltage warning threshold —
high range 0
VDD falling
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
Low-voltage warning threshold
low range 1
VDD falling
2.84
2.90
2.92
2.98
3.00
3.06
VDD rising
Low-voltage warning threshold —
low range 0
VDD falling
VDD rising
2.66
2.72
2.74
2.80
2.82
2.88
MC9S08SE8 Series MCU Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Parameter
Symbol
Min
Typical1
Max
Unit
Low-voltage inhibit reset/recover hysteresis
25
T
5 V Vhys
3 V
—
—
100
60
—
—
mV
V
26 P Bandgap voltage reference9
VBG
1.18
1.20
1.21
1
2
3
4
5
6
Typical values are measured at 25 °C. Characterized, not tested.
Measured with VIn = VDD or VSS
Measured with VIn = VSS
Measured with VIn = VDD
All functional non-supply pins are internally clamped to VSS and VDD
.
.
.
.
Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
7
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of
VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power
consumption).
8
9
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 5.0 V, Temp = 25 °C.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical Characteristics
VOL vs IOL at VDD = 5.0 V, High Drive
700
-40C
0C
600
500
400
300
200
100
0
25C
70C
95C
125C
135C
1
1.5
2
2.5
3
9
9.5
10
10.5 11
IOL/mA
Figure 4. Typical V vs. I for High Drive Enabled Pad (V = 5 V)
OL
OL
DD
VOL vs IOL at VDD = 3.0 V, High Drive
350
300
250
200
150
100
50
-40C
0C
25C
70C
95C
125C
135C
0
0.2 0.3 0.4 0.5 0.6
2
2.5
3
3.5
4
IOL/mA
Figure 5. Typical V vs. I for High Drive Enabled Pad (V = 3 V)
OL
OL
DD
MC9S08SE8 Series MCU Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
VOL vs IOL at VDD = 5.0 V, Low Drive
600
500
400
300
200
100
0
-40C
0C
25C
70C
95C
125C
135C
0.2
0.3
0.4
0.5
0.6
1
1.5
2
2.5
3
IOL/mA
Figure 6. Typical V vs. I for Low Drive Enabled Pad (V = 5 V)
OL
OL
DD
VOL vs IOL at VDD = 3.0 V, Low Drive
250
200
150
100
50
-40C
0C
25C
70C
95C
125C
135C
0
160
200
240 280
320 400
500
600 700
800
IOL/mA
Figure 7. Typical V vs. I for Low Drive Enabled Pad (V = 3 V)
OL
OL
DD
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical Characteristics
VOH vs IOH at VDD = 5.0 V, High Drive
5.1
-40C
0C
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
25C
70C
95C
125C
135C
-1
-1.5
-2
-2.5
-3
-9
-9.5
-10 -10.5 -11
IOH/mA
Figure 8. Typical V vs. I for High Drive Enabled Pad (V = 5 V)
OH
OH
DD
VOH vs IOL at VDD = 3.0 V, High Drive
3.05
3
-40C
0C
2.95
2.9
25C
70C
95C
125C
135C
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
-200 -300 -400 -500 -600
-2
-2.5
-3
-3.5
-4
IOH/mA
Figure 9. Typical V vs. I for High Drive Enabled Pad (V = 3 V)
OH
OH
DD
MC9S08SE8 Series MCU Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
VOH vs IOH at VDD = 5.0 V, Low Drive
5.2
5
-40C
0C
25C
70C
95C
125C
135C
4.8
4.6
4.4
4.2
4
3.8
-200 -300 -400 -500 -600
-1
-1.5
-2
-2.5
-3
IOH/mA
Figure 10. Typical V vs. I for Low Drive Enabled Pad (V = 5 V)
OH
OH
DD
VOH vs IOH at VDD = 3.0 V, Low Drive
3
2.95
2.9
-40C
0C
25C
70C
95C
125C
135C
2.85
2.8
2.75
2.7
2.65
2.6
2.55
-160 -200 -240 -280 -320 -400 -500 -600 -700 -800
IOH/mA
Figure 11. Typical V vs. I for Low Drive Enabled Pad (V = 3 V)
OH
OH
DD
3.6
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
Table 8. Supply Current Characteristics
VDD
Temp
(°C)
Num
C
C
P
P
Parameter
Symbol
Typical1
Max
Unit
mA
mA
mA
(V)
Run supply current2 measured at
(CPU clock = 4 MHz, fBus = 2 MHz)
5
3
5
3
5
3
2.4
2.18
6.35
5.79
1.4
2.72
2.26
7.29
6.42
1.56
1.53
1
2
3
RIDD
–40 to 125
–40 to 125
–40 to 125
Run supply current2 measured at
(CPU clock = 20 MHz, fBus = 10 MHz)
RIDD
Wait supply current2 measured at
fBus = 2 MHz
WIDD
1.36
19
28
45.8
–40 to 85
–40 to 105
–40 to 125
1.4
1.3
μA
μA
μA
μA
5
3
5
4
P
Stop2 mode supply current
Stop3 mode supply current
S2IDD
15
22
37.2
–40 to 85
–40 to 105
–40 to 125
23
43
76.1
–40 to 85
–40 to 105
–40 to 125
1.61
1.44
5
6
P
P
S3IDD
19
38
66.4
–40 to 85
–40 to 105
–40 to 125
3
5
3
500
500
–40 to 85
–40 to 125
300
300
nA
nA
RTC adder to stop2 or stop33
S23IDDRTI
500
500
–40 to 85
–40 to 125
5
3
122
110
180
160
μA
μA
–40 to 125
–40 to 125
7
8
C
C
LVD adder to stop3 (LVDE = LVDSE = 1)
S3IDDLVD
Adder to stop3 for oscillator enabled4
(OSCSTEN =1)
S3IDDOSC
5,3
5
8
μA
–40 to 125
1
Typical values are based on characterization data at 25 °C unless otherwise stated. See Figure 12 through Figure 13 for typical
curves across voltage/temperature.
2
3
All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 220 μA at 5 V with fBus = 1 MHz.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768 kHz crystal and low power mode
(HGO = 0).
4
MC9S08SE8 Series MCU Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
Run IDD at 10 MHz vs Temp
8
7
6
5
4
3
2
1
0
5.5V
5.0V
4.5V
3.3V
3.0V
2.7V
-40C
0C
25C
70C
95C
125C
135C
Temp (C)
Figure 12. Typical Run I Curves
DD
Stop2 IDD vs Temp
20
18
16
14
12
10
8
5.5V
5.0V
4.5V
3.3V
3.0V
2.7V
6
4
2
0
-40C
0C
25C
70C
95C
125C
135C
Temp (C)
Figure 13. Typical Stop2 I Curves
DD
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
Stop3 IDD vs Temp
35
30
25
20
15
10
5
5.5V
5.0V
4.5V
3.3V
3.0V
2.7V
0
-40C
0C
25C
70C
95C
125C
135C
Temp (C)
Figure 14. Typical Stop3 I Curves
DD
3.7
External Oscillator (XOSC) Characteristics
Table 9. Oscillator electrical specifications (Temperature Range = –40 to 125°C Ambient)
Num
C
Characteristic
Symbol
Min.
Typical1 Max. Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi-hgo
fhi-lp
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
High range (RANGE = 1), high gain (HGO = 1)2
1
2
C
High range (RANGE = 1), low power (HGO = 0)2
— Load capacitors
C1,C2
See crystal or resonator
manufacturer’s recommendation
Feedback resistor
—
3
Low range (32 kHz to 100 kHz)
RF
—
—
10
1
—
—
MΩ
kΩ
High range (1 MHz to 16 MHz)
Series resistor
—
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
—
—
—
0
100
0
—
—
—
RS
4
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
MC9S08SE8 Series MCU Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
Table 9. Oscillator electrical specifications (Temperature Range = –40 to 125°C Ambient)
Num
C
Characteristic
Symbol
Min.
Typical1 Max. Unit
Crystal start-up time3
t
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)4
High range, high gain (RANGE = 1, HGO = 1)4
—
—
—
—
200
400
5
—
—
—
—
CSTL-LP
t
t
5
T
CSTH-HGO
ms
t
CSTH-LP
15
CSTH-HGO
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE or FBE mode 2
fextal
6
T
0.03125
0
—
—
20
20
MHz
MHz
FBELP mode
1
2
3
Typical column was characterized at 5.0 V, 25 °C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized
by the crystal manufacturer.
4
4 MHz crystal.
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
3.8
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min.
Typical1
Max.
Unit
Average internal reference frequency — factory trimmed
at VDD = 5 V and temperature = 25 °C
fint_t
1
P
—
39.0625
—
kHz
Internal reference frequency — user trimmed
Internal reference start-up time
fint_ut
tIRST
2
3
P
T
31.25
—
—
39.06
100
kHz
60
μs
DCO output frequency range —
trimmed2
Low range
(DRS = 00)
fdco_t
4
5
6
7
D
D
C
C
16
—
—
—
—
59.77
0.1
20
MHz
MHz
DCO output frequency2
Reference = 32768 Hz and DMX32 = 1
fdco_DMX32
Δfdco_res_t
Δfdco_res_t
—
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
%fdco
%fdco
0.2
0.4
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
0.2
Total deviation of DCO output from trimmed frequency3
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70 °C
Δfdco_t
%fdco
8
C
—
–1.0 to 0.5
0.5
2
1
FLL acquisition time4
tAcquire
CJitter
10
11
C
C
—
—
—
1
ms
Long term jitter of DCO output clock (averaged over 2-ms
interval)5
%fdco
0.02
0.2
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This parameter is characterized and not tested on each device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
-60
-40
-20
0
20
40
60
80
100
120
Temperature
Figure 17. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.9
ADC Characteristics
Table 11. 10-Bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Absolute
Delta to VDD (VDD – VDDA
VDDA
ΔVDDA
ΔVSSA
VADIN
CADIN
RADIN
2.7
–100
–100
VREFL
—
—
0
5.5
100
100
VREFH
5.5
V
Supply voltage
2
)
mV
mV
V
2
Ground voltage
Input voltage
Delta to VSS (VSS – VSSA
)
0
—
4.5
3
Input capacitance
Input resistance
pF
kΩ
—
5
10-bit mode
ADCK > 4MHz
f
—
—
—
—
5
10
Analog source
resistance
External to
MCU
RAS
kΩ
fADCK < 4MHz
8-bit mode (all valid fADCK
High speed (ADLPC = 0)
Low power (ADLPC = 1)
)
—
—
—
—
10
8.0
4.0
0.4
0.4
ADC conversion
clock frequency
fADCK
MHz
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
1
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
ADC SAR
ENGINE
input
protection
RAS
RADIN
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 18. ADC Input Impedance Equivalency Diagram
Table 12. 10-Bit ADC Characteristics (V
= V
, V
= V
)
SSA
REFH
DDA
REFL
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
Comment
Supply Current
ADLPC = 1
ADLSMP = 1
ADCO = 1
T
IDDA
—
—
—
133
—
—
—
μA
μA
μA
Supply Current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
T
IDDA
218
327
Supply Current
ADLPC = 0
ADLSMP = 1
ADCO = 1
IDDA
Supply Current
ADLPC = 0
ADLSMP = 0
ADCO = 1
D
D
IDDA
—
—
0.582
0.011
1
1
mA
Supply Current Stop, Reset, Module Off
IDDA
μA
MC9S08SE8 Series MCU Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
) (continued)
Table 12. 10-Bit ADC Characteristics (V
= V
, V
= V
SSA
REFH
DDA
REFL
Typ1
3.3
Characteristic
Conditions
C
Symb
Min
Max
Unit
Comment
ADC
Asynchronous
Clock Source
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
2
5
tADACK
1/fADACK
=
D
fADACK
MHz
1.25
2
3.3
Short Sample (ADLSMP =
0)
Conversion
Time(Including
sample time)
—
—
—
20
40
—
—
—
ADCK
cycles
D
D
tADC
See SE8
reference
manual for
conversion
time variances
Long Sample (ADLSMP = 1)
Short Sample (ADLSMP =
0)
3.5
23.5
ADCK
cycles
Sample Time
tADS
Long Sample (ADLSMP = 1)
–40°C– 25°C
—
—
—
—
—
—
3.266
3.638
Temp Sensor
Slope
D
D
m
mV/°C
25°C– 125°C
Temp Sensor
Voltage
25°C
VTEMP25
—
1.396
—
mV
Characteristics for 28-pin packages only
Total
Unadjusted
Error
10-bit mode
8-bit mode
P
P
—
—
1
2.5
1.0
Includes
quantization
ETUE
LSB3
0.5
10-bit mode2
8-bit mode3
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
P
P
T
T
P
P
T
T
—
—
—
—
—
—
—
—
—
—
—
—
0.5
0.3
0.5
0.3
0.5
0.5
0.5
0.5
—
1.0
0.5
1.0
0.5
1.5
0.5
1
Differential
Non-Linearity
DNL
INL
EZS
EFS
EQ
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
Integral
Non-Linearity
Zero-Scale
Error
VADIN = VSSA
Full-Scale
Error
VADIN = VDDA
0.5
0.5
0.5
2.5
1
Quantization
Error
D
D
—
0.2
0.1
Input Leakage
Error
Padleakage4 *
RAS
EIL
Characteristics for 16-pin package only
Total
Unadjusted
Error
10-bit mode
8-bit mode
P
P
—
—
1.5
0.7
3.5
1.5
Includes
quantization
ETUE
LSB3
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
Table 12. 10-Bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSA
REFH
DDA
REFL
Typ1
Characteristic
Conditions
10-bit mode3
C
Symb
Min
Max
1.0
Unit
Comment
P
P
T
T
P
P
T
T
—
—
—
—
—
—
—
—
—
—
—
—
0.5
0.3
0.5
0.3
1.5
0.5
1
Differential
Non-Linearity
DNL
INL
EZS
EFS
EQ
LSB3
8-bit mode3
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
0.5
1.0
0.5
2.1
0.7
1.5
0.5
0.5
0.5
2.5
1
Integral
Non-Linearity
LSB3
LSB3
LSB3
LSB3
LSB3
Zero-Scale
Error
VADIN = VSSA
Full-Scale
Error
VADIN = VDDA
0.5
—
Quantization
Error
D
D
—
0.2
0.1
Input Leakage
Error
Padleakage4 *
RAS
EIL
1
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
4
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
1 LSB =(VREFH – VREFL)/2N
Based on input pad leakage current. Refer to pad electricals.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 13. Control Timing
Num
C
Rating
Symbol
Min
Typical1
Max
Unit
1
2
3
4
D
D
D
D
Bus frequency (tcyc = 1/fBus
)
Internal low power oscillator period
External reset pulse width2
Reset low drive3
fBus
tLPO
textrst
trstdrv
DC
700
—
—
—
—
10
1300
—
MHz
μs
100
ns
34 × tcyc
—
ns
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
5
6
D
D
tMSSU
tMSH
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes4
μs
IRQ pulse width
7
8
D
Asynchronous path2
Synchronous path5
100
1.5 × tcyc
—
—
—
—
t
ILIH, tIHIL
ns
ns
ns
Pin interrupt pulse width
Asynchronous path2
Synchronous path5
D
100
1.5 × tcyc
tILIH, IHIL
t
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
—
—
—
—
40
75
C
9
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
11
35
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3
4
When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of tcyc
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
.
5
6
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 125 °C.
textrst
RESET PIN
Figure 19. Reset Timing
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
tIHIL
IRQ/Pin Interrupts
IRQ/Pin Interrupts
tILIH
Figure 20. IRQ/Pin Interrupt Timing
3.10.2 TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TPM Input Timing
Num
C
Rating
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
DC
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 21. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 22. Timer Input Capture Pulse
MC9S08SE8 Series MCU Data Sheet, Rev. 4
26
Freescale Semiconductor
Ordering Information
3.11 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory section in the reference
manual.
Table 15. Flash Characteristics
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
1
2
3
4
5
6
7
8
D
D
D
D
P
P
P
P
Supply voltage for program/erase
Supply voltage for read operation
Internal FCLK frequency1
Vprog/erase
VRead
fFCLK
tFcyc
2.7
2.7
150
5
—
—
5.5
5.5
V
V
—
200
6.67
kHz
μs
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
tBurst
4
tPage
4000
20,000
Mass erase time2
tMass
Program/erase endurance3
TL to TH = –40 °C to 125 °C
T = 25 °C
nFLPE
9
C
10,000
15
—
100,000
—
—
cycles
years
10
C
Data retention4
tD_ret
100
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
4
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile
Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
4
Ordering Information
This chapter contains ordering information for the device numbering system.
Example of the device numbering system:
9
SE 8
XX E
C
MC S08
RoHS compliance indicator (E = yes)
Package designator (see Table 16)
Status
(MC = Fully Qualified)
Memory
Temperature range
(C = –40 °C to 85 °C)
(V = –40 °C to 105 °C)
(M = –40 °C to 125 °C)
(9 = Flash-based)
Core
Family
Memory Size (in KB)
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
27
Ordering Information
4.1
Package Information
Table 16. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
28
28
16
Plastic Dual In-line Pin
PDIP
SOIC
RL
WL
TG
710
98ASB42390B
98ASB42345B
98ASH70247A
Small Outline Integrated Circuit
Thin Shrink Small Outline Package
751F
948F
TSSOP
4.2
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 16.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
28
Freescale Semiconductor
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
29
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
30
Freescale Semiconductor
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
31
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
32
Freescale Semiconductor
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
33
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4
34
Freescale Semiconductor
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Semiconductor was negligent regarding the design or manufacture of the part.
Japan:
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners.
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
© Freescale Semiconductor, Inc. 2008-2009, 2015. All rights reserved.
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
Document Number: MC9S08SE8
Rev. 4
4/2015
相关型号：
©2020 ICPDF网 联系我们和版权申明