MC9S12C64CPB25 [NXP]
16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP52, LQFP-52;
| 型号： | MC9S12C64CPB25 |
| 厂家： | 
NXP |
| 描述： | 16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP52, LQFP-52 时钟 外围集成电路 |
| 文件： | 总136页 (文件大小：2223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DOCUMENT NUMBER
9S12C128DGV1/D
Freescale Semiconductor, Inc.
MC9S12C Family
Device User Guide
V01.04
Covers also
MC9S12GC Family
Original Release Date: 25 JAN 2003
Revised: 27 JANUARY 2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Revision History
Version Revision Effective
Author
Description of Changes
Number
Date
Date
00.01
25.JAN.03 25.JAN.03
Original Version. Based on C32 user guide version 01.12
Enhanced PortK description
Part number table revision in preface
00.02
07.FEB.03 07.FEB.03
QFP112 Emulation pinout correction
00.03
25.FEB.03 25.FEB.03
15.APR.03 15.APR03
Enhanced part number explanation in preface
Reduced pseudo STOP current spec. for C64,C96,C128
Enhanced PortAD signal description
Corrected VDDR description in 2.4.2
Revised pin leakage in electrical parameters
00.04
00.05
SPI timing parameter table correction
Output drive high value reduced in 3V range
PE[4:2] Pull-Up spec out of reset changed
05.MAY.03 05.MAY.03
3V Expansion bus timing parameters not tested in production
Minimum bus frequency specification increased to 0.25MHz.
Parameter classification added to Appendix Table C-2.
IOH changed to 4mA for 3V range.
00.06
01.00
21.MAY.03 21.MAY.03
15.JUL.03 15.JUL03
LVR level defined.for C32. Run IDD changed for C32.
Block guide reference table updated
Added PCB layout guide for Pierce oscillator configuration
IOL parameter updated in 3.3V range
01.01
01.02
12.AUG.03 12.AUG.03
20.NOV.03 20.NOV.03
Updated PARTID listing due to C128 ECO revision
Changed DOC number and CPU DOC reference number
Included separate C32 LVI levels
Changed PortM pull up reset state to enabled.
Added References to the CAN-less GC-Family
No major revision number increment, since silicon functionality is
not changed.
Added VDDX connection in PCB layout figures 8-1.to 8-6
Added Part ID for 2L45J mask set to Part ID table
01.03
01.04
27.NOV.03 27.NOV.03
27.JAN.04 27.JAN.04
Table A-4 VDD/VDDPLL min when supplied externally now 2.35V
Reference S12FTS128K1 in Preface (was S12FTS128K)
Reference to CPU Guide corrected to Version2
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Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pin Initialization for 48 & 52 Pin LQFP bond-out versions . . . . . . . . . . . . . . . . . . 56
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
TEST / VPP — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . 58
PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 58
PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 58
PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2
2.2.1
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output. . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB). . . . . . . . . . . . . . 60
2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . 61
2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin . . . . . . . . . . . . 61
2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . 62
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Device User Guide — 9S12C128DGV1/D V01.04
2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.21 PM5 / SCK — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.22 PM4 / MOSI — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.23 PM3 / SS — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.24 PM2 / MISO — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.25 PM1 / TXCAN — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.26 PM0 / RXCAN — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.27 PS[3:2] — Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.28 PS1 / TXD — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.29 PS0 / RXD — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0] . . . . . . . . . . . . . . . . . . . . . . . 63
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 63
VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
2.4.1
2.4.2
63
2.4.3
2.4.4
2.4.5
2.4.6
VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins . . . . . . . . . . . . . . . . . . 63
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 64
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 64
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 64
Section 3 System Clock Description
Section 4 Modes of Operation
4.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Section 5 Resets and Interrupts
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Device User Guide — 9S12C128DGV1/D V01.04
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2
5.2.1
5.3
5.3.1
5.3.2
Section 6 HCS12 Core Block Description
6.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PPAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
BDM alternate clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Extended Address Range Emulation Implications . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.1
6.1.2
6.1.3
Section 7 Voltage Regulator (VREG) Block Description
7.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.1.1
7.1.2
Section 8 Recommended Printed Circuit Board Layout
Section 9 Clock Reset Generator (CRG) Block Description
9.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.1.1
Section 10 Oscillator (OSC) Block Description
Section 11 Timer (TIM) Block Description
Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 13 Serial Communications Interface (SCI) Block Description
Section 14 Serial Peripheral Interface (SPI) Block Description
Section 15 Flash Block Description
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Device User Guide — 9S12C128DGV1/D V01.04
Section 16 RAM Block Description
Section 17 Pulse Width Modulator (PWM) Block Description
Section 18 MSCAN Block Description
Section 19 Port Integration Module (PIM) Block Description
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix B Electrical Specifications
B.1 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
B.2 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.3.1
B.3.2
Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.4 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.4.1
B.4.2
B.4.3
B.4.4
B.4.5
ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ATD accuracy (5V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ATD accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.5 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B.5.1
B.5.2
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Device User Guide — 9S12C128DGV1/D V01.04
B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
B.6.1
B.6.2
B.6.3
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
B.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
B.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Appendix C Electrical Specifications
C.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
C.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
C.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
C.3.1
General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Appendix D Package Information
D.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
D.2 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
D.3 52-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
D.4 48-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Appendix E Emulation Information
E.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
E.1.1
PK[2:0] / XADDR[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
E.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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List of Figures
Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 1-1 MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map . . . . . . 29
Figure 1-3 MC9S12C96 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map. . . . . . . . 31
Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map. . . . . . . . 32
Figure 1-6 MC9S12GC16 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 33
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 52
Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 53
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . 54
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 8-1 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 8-2 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 8-3 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 77
Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 78
Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 79
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 96
Figure B-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure B-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure B-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure B-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure C-1 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure C-2 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure C-3 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure C-4 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure C-5 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 128
Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 129
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Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130
Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Di-
mensions (case no. 841B)133
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List of Tables
Table 0-2 MC9S12C-Family Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . . 15
Table 0-3 MC9S12C-Family Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 0-4 MC9S12GC-Family Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 0-5 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) 34
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) 34
$0018 - $0018 Miscellaneous Peripherals (Device User Guide) 35
$0019 - $0019 VREG3V3 (Voltage Regulator) 35
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) 35
$0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) 35
$001A - $001B Miscellaneous Peripherals (Device User Guide) 35
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, 36
Device User Guide) 36
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) 36
$001F - $001F INT map 2 of 2 (HCS12 Interrupt) 36
$0020 - $002F
DBG (including BKP) map 1 of 1 (HCS12 Debug) 36
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) 37
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) 37
$0034 - $003F CRG (Clock and Reset Generator) 37
$0040 - $006F TIM (Timer 16 Bit 8 Channels) 38
$0070 - $007F Reserved 40
$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 40
$00A0 - $00C7 Reserved 41
$00D0 - $00D7 Reserved 42
$00C8 - $00CF SCI (Asynchronous Serial Interface) 42
$00D8 - $00DF SPI (Serial Peripheral Interface) 42
$00E0 - $00FF PWM (Pulse Width Modulator) 43
$0100 - $010F Flash Control Register 44
$0110 - $013F Reserved 45
$0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 45
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 46
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$0180 - $023F Reserved 47
$0240 - $027F PIM (Port Interface Module) 47
$0280 - $03FF Reserved space 50
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-2 MC9S12C-Family Power and Ground Connection Summary . . . . . . . . . . . . . 64
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 6-1 Device Specific Flash PAGE Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table A-7 3.3V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-8 Supply Current Characteristics for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 94
Table B-1 Voltage Regulator Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table B-11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table C-1 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table C-4 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 124
Table C-5 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . . 125
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Preface
The Device User Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family
devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the
customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and
all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all
module specific information is located only in the respective Block User Guide. If applicable, special
implementation details of the module are given in the block description sections of this document.
The C-Family and the GC-Family offer an extensive range of package, temperature and speed options.
The members of the GC-Family do not feature a CAN module.
Table 0-1 shows a feature overview of the MC9S12C and MC9S12GC Family members.
Table 0-2 summarizes the package option and size configuration.
Table 0-3 lists the part number coding based on the package, speed and temperature and preliminary die
options for the C-Family.
Table 0-4 lists the part number coding based on the package, speed and temperature and preliminary die
options for the GC-Family.
Table 0-1 List of MC9S12C and MC9S12GC Family members
Flash
128K
96K
RAM
Device
CAN
1
SCI
1
SPI
1
A/D
8ch
8ch
8ch
8ch
8ch
8ch
8ch
8ch
PWM Timer
MC9S12C128
MC9S12GC128
MC9S12C96
MC9S12C64
MC9S12GC64
MC9S12C32
MC9S12GC32
MC9S12GC32
6ch
6ch
6ch
6ch
6ch
6ch
6ch
6ch
8ch
8ch
8ch
8ch
8ch
8ch
8ch
8ch
4K
—
1
1
1
4K
1
1
1
1
1
64K
4K
—
1
1
1
1
1
32K
16K
2K
1K
—
1
1
1
1
1
Table 0-2 MC9S12C-Family Package Option Summary
1
2
Mask
set
Temp.
3 4
Package
Device
Part Number
Flash
RAM
I/O ,
Options
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
48LQFP
52LQFP
80QFP
MC9S12C128
MC9S12C128
MC9S12C128
MC9S12C96
MC9S12C96
MC9S12C96
MC9S12C128 0L09S
MC9S12C128 0L09S
MC9S12C128 0L09S
31
35
60
31
35
60
128K
4K
4K
48LQFP
52LQFP
80QFP
MC9S12C96
MC9S12C96
MC9S12C96
TBD
TBD
TBD
96K
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Device User Guide — 9S12C128DGV1/D V01.04
1
2
Mask
set
Temp.
3 4
Package
Device
Part Number
Flash
RAM
I/O ,
Options
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
M, V, C
48LQFP
52LQFP
80QFP
MC9S12C64
MC9S12C64
MC9S12C64
MC9S12C32
MC9S12C32
MC9S12C32
MC9S12C64
MC9S12C64
MC9S12C64
TBD
TBD
TBD
31
35
60
31
35
60
31
35
60
31
35
60
31
35
60
31
35
60
64K
4K
48LQFP
52LQFP
80QFP
MC9S12C32 1L45J
MC9S12C32 1L45J
MC9S12C32 1L45J
MC9S12GC128 0L09S
MC9S12GC128 0L09S
MC9S12GC128 0L09S
32K
128K
64K
32K
16K
2K
4K
4K
2K
2K
48LQFP MC9S12GC128
52LQFP MC9S12GC128
80QFP MC9S12GC128
48LQFP MC9S12GC128
52LQFP MC9S12GC128
80QFP MC9S12GC128
MC9S12GC64
MC9S12GC64
MC9S12GC64
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12GC32
MC9S12GC32
MC9S12GC32
MC9S12GC16
MC9S12GC16
MC9S12GC16
MC9S12GC32 1L45J
MC9S12GC32 1L45J
MC9S12GC32 1L45J
MC9S12GC16 1L45J
MC9S12GC16 1L45J
MC9S12GC16 1L45J
48LQFP
52LQFP
80QFP
NOTES:
1. Maskset dependent errata can be accessed at
http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp
2. C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
3. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8
channel timer. The GC-Family members do not have the CAN module
4. I/O is the sum of ports capable to act as digital input or output.
Temperature Options
MC9S12 C32 (P)C FU
25
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80QFP
Speed Option
Package Option
Temperature Option
PB = 52LQFP
FA = 48LQFP
Preliminary Option
Speed Options
25 = 25MHz bus
16 = 16MHz bus
Device Title
Controller Family
Figure 0-1 Order Part number Coding
Table 0-3 MC9S12C-Family Part Number Coding
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12C128CFA16
TBD
-40˚C, 85˚C
48LQFP
16MHz
C128 die
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Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12C128CPB16
MC9S12C128CFU16
MC9S12C128VFA16
MC9S12C128VPB16
MC9S12C128VFU16
MC9S12C128MFA16
MC9S12C128MPB16
MC9S12C128MFU16
MC9S12C128CFA25
MC9S12C128CPB25
MC9S12C128CFU25
MC9S12C128VFA25
MC9S12C128VPB25
MC9S12C128VFU25
MC9S12C128MFA25
MC9S12C128MPB25
MC9S12C128MFU25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
52LQFP
80QFP
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
C128 die
C128 die
48LQFP
52LQFP
80QFP
C128 die
C128 die
C128 die
48LQFP
52LQFP
80QFP
C128 die
C128 die
C128 die
48LQFP
52LQFP
80QFP
C128 die
C128 die
C128 die
48LQFP
52LQFP
80QFP
C128 die
C128 die
C128 die
48LQFP
52LQFP
80QFP
C128 die
C128 die
C128 die
MC9S12C96PCFA16 0L09S
MC9S12C96PCPB16 0L09S
MC9S12C96PCFU16 0L09S
48LQFP
52LQFP
80QFP
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Final C96 using C96 die
Final C96 using C96 die
Final C96 using C96 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Final C96 using C96 die
Final C96 using C96die
Final C96 using C96 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Final C96 using C96 die
Final C96 using C96 die
Final C96 using C96 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Final C96 using C96 die
Final C96 using C96 die
Final C96 using C96 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
MC9S12C96CFA16
MC9S12C96CPB16
MC9S12C96CFU16
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12C96PVFA16 0L09S -40˚C, 105˚C
MC9S12C96PVPB16 0L09S -40˚C, 105˚C
MC9S12C96PVFU16 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12C96VFA16
MC9S12C96VPB16
MC9S12C96VFU16
TBD
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12C96PMFA16 0L09S -40˚C, 125˚C
MC9S12C96PMPB16 0L09S -40˚C, 125˚C
MC9S12C96PMFU16 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
MC9S12C96MFA16
MC9S12C96MPB16
MC9S12C96MFU16
TBD
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
MC9S12C96PCFA25 0L09S
MC9S12C96PCPB25 0L09S
MC9S12C96PCFU25 0L09S
48LQFP
52LQFP
80QFP
MC9S12C96CFA25
MC9S12C96CPB25
MC9S12C96CFU25
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12C96PVFA25 0L09S -40˚C, 105˚C
MC9S12C96PVPB25 0L09S -40˚C, 105˚C
MC9S12C96PVFU25 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12C96VFA25
MC9S12C96VPB25
MC9S12C96VFU25
TBD
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Final C96 using C96 die
Final C96 using C96 die
Final C96 using C96 die
MC9S12C96PMFA25 0L09S -40˚C, 125˚C
MC9S12C96PMPB25 0L09S -40˚C, 125˚C
MC9S12C96PMFU25 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Preliminary C96 using C128 die
Final C96 using C96 die
MC9S12C96MFA25
MC9S12C96MPB25
MC9S12C96MFU25
TBD
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
Final C96 using C96 die
Final C96 using C96 die
MC9S12C64PCFA16 0L09S
MC9S12C64PCPB16 0L09S
MC9S12C64PCFU16 0L09S
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Final C64 using C64 die
MC9S12C64CFA16
MC9S12C64CPB16
MC9S12C64CFU16
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
Final C64 using C64 die
Final C64 using C64 die
MC9S12C64PVFA16 0L09S -40˚C, 105˚C
MC9S12C64PVPB16 0L09S -40˚C, 105˚C
MC9S12C64PVFU16 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Final C64 using C64 die
MC9S12C64VFA16
MC9S12C64VPB16
MC9S12C64VFU16
TBD
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
Final C64 using C64 die
Final C64 using C64 die
MC9S12C64PMFA16 0L09S -40˚C, 125˚C
MC9S12C64PMPB16 0L09S -40˚C, 125˚C
MC9S12C64PMFU16 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Final C64 using C64 die
MC9S12C64MFA16
MC9S12C64MPB16
MC9S12C64MFU16
TBD
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
Final C64 using C64 die
Final C64 using C64 die
MC9S12C64PCFA25 0L09S
MC9S12C64PCPB25 0L09S
MC9S12C64PCFU25 0L09S
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
PreliminaryC64 using C128 die
Final C64 using C64 die
MC9S12C64CFA25
MC9S12C64CPB25
MC9S12C64CFU25
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
Final C64 using C64 die
Final C64 using C64 die
MC9S12C64PVFA25 0L09S -40˚C, 105˚C
MC9S12C64PVPB25 0L09S -40˚C, 105˚C
MC9S12C64PVFU25 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Final C64 using C64 die
MC9S12C64VFA25
MC9S12C64VPB25
MC9S12C64VFU25
TBD
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
Final C64 using C64 die
Final C64 using C64 die
MC9S12C64PMFA25 0L09S -40˚C, 125˚C
MC9S12C64PMPB25 0L09S -40˚C, 125˚C
MC9S12C64PMFU25 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Preliminary C64 using C128 die
Final C64 using C64 die
MC9S12C64MFA25
MC9S12C64MPB25
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
48LQFP
52LQFP
Final C64 using C64 die
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12C64MFU25
TBD
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
80QFP
48LQFP
52LQFP
80QFP
25MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Final C64 using C64 die
C32 die
MC9S12C32CFA16 1L45J
MC9S12C32CPB16 1L45J
MC9S12C32CFU16 1L45J
C32 die
C32 die
MC9S12C32VFA16 1L45J -40˚C,105˚C
MC9S12C32VPB16 1L45J -40˚C,105˚C
MC9S12C32VFU16 1L45J -40˚C, 105˚C
MC9S12C32MFA16 1L45J -40˚C,125˚C
MC9S12C32MPB16 1L45J -40˚C,125˚C
MC9S12C32MFU16 1L45J -40˚C, 125˚C
48LQFP
52LQFP
80QFP
C32 die
C32 die
C32 die
48LQFP
52LQFP
80QFP
C32 die
C32 die
C32 die
MC9S12C32CFA25 1L45J
MC9S12C32CPB25 1L45J
MC9S12C32CFU25 1L45J
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
C32 die
C32 die
C32 die
MC9S12C32VFA25 1L45J -40˚C,105˚C
MC9S12C32VPB25 1L45J -40˚C,105˚C
MC9S12C32VFU25 1L45J -40˚C, 105˚C
MC9S12C32MFA25 1L45J -40˚C,125˚C
MC9S12C32MPB25 1L45J -40˚C,125˚C
MC9S12C32MFU25 1L45J -40˚C, 125˚C
48LQFP
52LQFP
80QFP
C32 die
C32 die
C32 die
48LQFP
52LQFP
80QFP
C32 die
C32 die
C32 die
Table 0-4 MC9S12GC-Family Part Number Coding
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12GC128PCFA25 0L09S
MC9S12GC128PCPB25 0L09S
MC9S12GC128PCFU25 0L09S
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Preliminary GC128 using C128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Final GC128 using GC128 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
MC9S12GC128CFA25
MC9S12GC128CPB25
MC9S12GC128CFU25
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12GC128PVFA25 0L09S -40˚C, 105˚C
MC9S12GC128PVPB25 0L09S -40˚C, 105˚C
MC9S12GC128PVFU25 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC128VFA25
MC9S12GC128VPB25
MC9S12GC128VFU25
TBD
TBD
TBD
-40˚C, 105˚C
-40˚C, 105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC128PMFA25 0L09S -40˚C, 125˚C
MC9S12GC128PMPB25 0L09S -40˚C, 125˚C
MC9S12GC128PMFU25 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
MC9S12GC128MFA25
MC9S12GC128MPB25
MC9S12GC128MFU25
TBD
TBD
TBD
-40˚C, 125˚C
-40˚C, 125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
MC9S12GC64PCFA25 0L09S
MC9S12GC64PCPB25 0L09S
MC9S12GC64PCFU25 0L09S
48LQFP
52LQFP
80QFP
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12GC64CFA25
MC9S12GC64CPB25
MC9S12GC64CFU25
TBD
TBD
TBD
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Final GC64 using GC64 die
Final GC64 using GC64 die
Final GC64 using GC64 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
Final GC64 using GC64 die
Final GC64 using GC64 die
Final GC64 using GC64 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
Preliminary GC64 using C128 die
Final GC64 using GC64 die
Final GC64 using GC64 die
Final GC64 using GC64 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Preliminary GC32 using C32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Final GC32 using GC32 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Final GC16 using GC16 die
Final GC16 using GC16 die
Final GC16 using GC16 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Final GC16 using GC16 die
Final GC16 using GC16 die
MC9S12GC64PVFA25 0L09S -40˚C, 105˚C
MC9S12GC64PVPB25 0L09S -40˚C, 105˚C
MC9S12GC64PVFU25 0L09S -40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC64VFA25
MC9S12GC64VPB25
MC9S12GC64VFU25
TBD
TBD
TBD
-40˚C, 105˚C
-40˚C, 105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC64PMFA25 0L09S -40˚C, 125˚C
MC9S12GC64PMPB25 0L09S -40˚C, 125˚C
MC9S12GC64PMFU25 0L09S -40˚C, 125˚C
48LQFP
52LQFP
80QFP
MC9S12GC64MFA25
MC9S12GC64MPB25
MC9S12GC64MFU25
TBD
TBD
TBD
-40˚C, 125˚C
-40˚C, 125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
MC9S12GC32PCFA25 1L45J
MC9S12GC32PCPB25 1L45J
MC9S12GC32PCFU25 1L45J
48LQFP
52LQFP
80QFP
MC9S12GC32CFA25
MC9S12GC32CPB25
MC9S12GC32CFU25
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12GC32PVFA25 1L45J -40˚C,105˚C
MC9S12GC32PVPB25 1L45J -40˚C,105˚C
MC9S12GC32PVFU25 1L45J -40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC32VFA25
MC9S12GC32VPB25
MC9S12GC32VFU25
TBD
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
-40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC32PMFA25 1L45J -40˚C,125˚C
MC9S12GC32PMPB25 1L45J -40˚C,125˚C
MC9S12GC32PMFU25 1L45J -40˚C, 125˚C
48LQFP
52LQFP
80QFP
MC9S12GC32MFA25
MC9S12GC32MPB25
MC9S12GC32MFU25
TBD
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
-40˚C, 85˚C
48LQFP
52LQFP
80QFP
MC9S12GC16PCFA25 1L45J
MC9S12GC16PCPB25 1L45J
MC9S12GC16PCFU25 1L45J
48LQFP
52LQFP
80QFP
MC9S12GC16CFA25
MC9S12GC16CPB25
MC9S12GC16CFU25
TBD
TBD
TBD
48LQFP
52LQFP
80QFP
MC9S12GC16PVFA25 1L45J -40˚C,105˚C
MC9S12GC16PVPB25 1L45J -40˚C,105˚C
MC9S12GC16PVFU25 1L45J -40˚C, 105˚C
48LQFP
52LQFP
80QFP
MC9S12GC16VFA25
MC9S12GC16VPB25
TBD
TBD
-40˚C,105˚C
-40˚C,105˚C
48LQFP
52LQFP
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Mask
set
Part Number
Temp.
Package
Speed
Description
MC9S12GC16VFU25
TBD
-40˚C, 105˚C
80QFP
48LQFP
52LQFP
80QFP
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Final GC16 using GC16 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Preliminary GC16 using C32 die
Final GC16 using GC16 die
Final GC16 using GC16 die
Final GC16 using GC16 die
MC9S12GC16PMFA25 1L45J -40˚C,125˚C
MC9S12GC16PMPB25 1L45J -40˚C,125˚C
MC9S12GC16PMFU25 1L45J -40˚C, 125˚C
MC9S12GC16MFA25
MC9S12GC16MPB25
MC9S12GC16MFU25
TBD
TBD
TBD
-40˚C,125˚C
-40˚C,125˚C
-40˚C, 125˚C
48LQFP
52LQFP
80QFP
Table 0-5 Document References
1
Version Document Order Number
User Guide
CPU12 Reference Manual
V02
V01
V04
V04
V03
V01
V02
V04
V02
V03
V02
V01
V01
V02
V02
V01
V01
V01
V01
S12CPUV2/D
S12DBGV1/D
HCS12 Debug (DBG) Block Guide
HCS12 Background Debug (BDM) Block Guide
S12BDMV4/D
HCS12 Module Mapping Control (MMC) Block Guide
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide
HCS12 Interrupt (INT) Block Guide
S12MMCV4/D
S12MEBIV3/D
S12INTV1/D
Analog To Digital Converter: 10 Bit 8 Channel (ATD_10B8C) Block Guide
Clock and Reset Generator (CRG) Block Guide
S12ATD10B8CV2/D
S12CRGV4/D
Serial Communications Interface (SCI) Block Guide
Serial Peripheral Interface (SPI) Block Guide
S12SCIV2/D
S12SPIV3/D
Motorola Scalable CAN (MSCAN) Block Guide 2
Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide
Timer: 16 bit, 8 channel (TIM_16B8C) Block Guide
Voltage Regulator (VREG) Block Guide
S12MSCANV2/D
S12PWM8B6V1/D
S12TIM16B8CV1/D
S12VREG3V3V2/D
S12OSCV2/D
Oscillator (OSC) Block Guide
Port Integration Module (PIM_9C32) Block Guide
32Kbyte Flash EEPROM (FTS32K) Block Guide
64Kbyte Flash EEPROM (FTS64K) Block Guide
128Kbyte Flash EEPROM (FTS128K1) Block Guide
S12C32PIMV1/D
S12FTS32KV1/D
S12FTS64KV1/D
S12FTS128K1V1/D
NOTES:
1. For the GC16 refer to the 16K flash, for the C32 and GC32 refer to the 32K flash, for the C64 and GC64 the 64K flash, for
the C96 the 96K flash and C128 the 128K flash document.
2. Not available on the GC-Family members
Terminology
Acronyms and Abbreviations
New or invented terms, symbols, and notations
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
Section 1 Introduction
1.1 Overview
The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive
network control MCU family. Members of the MC9S12C-Family and the MC9S12GC-Family deliver the
power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive,
general purpose Industrial and Automotive network applications. All MC9S12C-Family and
MC9S12GC-Family members are comprised of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous
serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer
module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital
converter (ADC). The MC9S12C-Family members also feature a CAN 2.0 A, B software compatible
module (MSCAN12). The MC9S12C-Family as well as the MC9S12GC-Family has full 16-bit data paths
throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O
port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and
the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version
pin compatible to the HCS12 A, B and D- Family derivatives.
1.2 Features
•
16-bit HCS12 CORE
– HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv. Enhanced indexed addressing
– MMC (memory map and interface)
– INT (interrupt control)
– BDM (background debug mode)
– DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)
– MEBI: Multiplexed Expansion Bus Interface (available only in 80 pin package version)
Wake-up interrupt inputs
•
•
– Up to 12-port bits available for wake up interrupt function with digital filtering
Memory options
– 16K, 32K, 64K, 96K or 128KByte Flash EEPROM (erasable in 512-byte sectors)
– 1K, 2K or 4K Byte RAM
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Device User Guide — 9S12C128DGV1/D V01.04
•
Analog-to-Digital Converters
– One 8-channel module with 10-bit resolution.
– External conversion trigger capability
•
Available on MC9S12C-Family:
One 1M bit per second, CAN 2.0 A, B software compatible module
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
Timer Module (TIM)
•
– 8-Channel Timer
– Each Channel Configurable as either Input Capture or Output Compare
– Simple PWM Mode
– Modulo Reset of Timer Counter
– 16-Bit Pulse Accumulator
– External Event Counting
– Gated Time Accumulation
•
6 PWM channels
– Programmable period and duty cycle
– 8-bit 6-channel or 16-bit 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
•
•
Serial interfaces
– One asynchronous serial communications interface (SCI)
– One synchronous serial peripheral interface (SPI)
CRG (Clock Reset Generator Module)
– Windowed COP watchdog,
– Real time interrupt,
– Clock monitor,
– Pierce or low current Colpitts oscillator
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– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Low power 0.5 to 16 MHz crystal oscillator reference clock
Operating frequency
•
•
– 32MHz equivalent to 16MHz Bus Speed for single chip
– 32MHz equivalent to 16MHz Bus Speed in expanded bus modes
– Option of 9S12C-Family: 50MHz equivalent to 25MHz Bus Speed
– All 9S12GC-Family Members allow a 50MHz operting frequency.
Internal 2.5V Regulator
– Supports an input voltage range from 2.97V to 5.5V
– Low power mode capability
– Includes low voltage reset (LVR) circuitry
– Includes low voltage interrupt (LVI) circuitry
48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package
– Up to 58 I/O lines with 5V input and drive capability (80 pin package)
– Up to 2 dedicated 5V input only lines (IRQ, XIRQ)
– 5V 8 A/D converter inputs and 5V I/O
•
•
Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
– Enhanced DBG12 debug features
1.3 Modes of Operation
User modes (Expanded modes are only available in the 80 pin package version).
•
Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
– Special Single-Chip Mode with active Background Debug Mode
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Device User Guide — 9S12C128DGV1/D V01.04
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
•
– Stop Mode
– Pseudo Stop Mode
– Wait Mode
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Device User Guide — 9S12C128DGV1/D V01.04
1.4 Block Diagram
Figure 1-1 MC9S12C-Family Block Diagram
VSSR
VDDR
VDDX
VSSX
VDDA
VDDA
VSSA
VRH
ATD
VSSA
VRH
VRL
Voltage Regulator
VRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
16K, 32K, 64K, 96K, 128K Byte Flash
VDD2
VSS2
VDD1
VSS1
P
D
1K, 2K, 4K Byte RAM
Background
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
MODC
PT0
PT1
PT2
PT3
PT4
PT5
BKGD
HCS12
CPU
Debug12 Module
MUX
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
Timer
Module
Clock and
Reset
Generation
Module
PLL
COP Watchdog
Clock Monitor
Periodic Interrupt
PT6
PT7
RESET
PW0
PW1
PW2
PW3
PW4
PW5
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1
NOACC/XCLKS
PP0
PP1
PP2
PP3
PP4
PP5
System
PWM
Module
Integration
Module
(SIM)
PP6
PP7
TEST/VPP
PJ6
PJ7
Multiplexed Address/Data Bus
RXD
TXD
PS0
PS1
PS2
PS3
SCI
MSCAN is not available on the
9S12GC Family Members
DDRA
PTA
DDRB
PTB
RXCAN
TXCAN
MISO
SS
MOSI
SCK
PM0
PM1
PM2
PM3
PM4
PM5
MSCAN
2
1
SPI
A
PA
1
ADR9
9
Multiplexed
Wide Bus
0
A
T
T
A
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
D
DA
Internal Logic 2.5V
I/O Driver 5V
VDD1,2
VSS1,2
VDDX
VSSX
PLL 2.5V
A/D Converter 5V
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
VDDPLL
VSSPLL
VDDA
VSSA
Voltage Regulator 5V & I/O
VDDR
VSSR
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Device User Guide — 9S12C128DGV1/D V01.04
1.5 Device Memory Map
Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures
(Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash
and RAM.
Table 1-1 Device Register Map Overview
Address
$000 - $017
$018
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Size
24
1
$019
Voltage Regulator (VREG)
Device ID register
1
$01A - $01B
$01C - $01F
$020 - $02F
$030 - $033
$034 - $03F
$040 - $06F
$070 - $07F
$080 - $09F
$0A0 - $0C7
$0C8 - $0CF
$0D0 - $0D7
$0D8 - $0DF
$0E0 - $0FF
$100 - $10F
$110 - $13F
$140 - $17F
$180 - $23F
$240 - $27F
$280 - $3FF
2
CORE (MEMSIZ, IRQ, HPRIO)
CORE (DBG)
4
16
4
CORE (PPAGE1)
Clock and Reset Generator (CRG)
Standard Timer Module16-bit 8-channels (TIM)
Reserved
12
48
16
32
40
8
Analog to Digital Convert (ATD)
Reserved
Serial Communications Interface (SCI)
Reserved
8
Serial Peripheral Interface (SPI)
Pulse Width Modulator 8-bit 6 channels (PWM)
Flash Control Register
8
32
16
48
64
192
64
384
Reserved
Motorola Scalable CAN (MSCAN)2
Reserved
Port Integration Module (PIM)
Reserved
NOTES:
1. External memory paging is not supported on this device (6.1.1 PPAGE).
2. Not available on MC9S12GC-Family Devices
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Device User Guide — 9S12C128DGV1/D V01.04
$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
16K Fixed Flash EEPROM
4K Bytes RAM
$3FFF
$3000
$3000
$4000
$3FFF
$4000
Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
8 * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
Flash Erase Sector Size is 1024 Bytes
Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map
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$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
16K Fixed Flash EEPROM
4K Bytes RAM
$3FFF
$3000
$3000
$4000
$3FFF
$4000
Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
6 * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
Flash Erase Sector Size is 1024 Bytes
Figure 1-3 MC9S12C96 User Configurable Memory Map
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$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
16K Fixed Flash EEPROM
4K Bytes RAM
$3FFF
$3000
$3000
$4000
$3FFF
$4000
Mappable to any 4K Boundary
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
4 * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
Flash Erase Sector Size is 512 Bytes
Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$3800
$3FFF
2K Bytes RAM
$3800
$4000
Mappable to any 2K Boundary
$8000
$8000
16K Page Window
2 * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
Flash Erase Sector Size is 512 Bytes
Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$3800
$3FFF
2K Bytes RAM
$3800
$4000
Mappable to any 2K Boundary
$8000
EXT
$C000
16K Fixed Flash EEPROM
$C000
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
Flash Erase Sector Size is 512 Bytes
Figure 1-6 MC9S12GC16 User Configurable Memory Map
1.6 Detailed Register Map
The detailed register map of the MC9S12C Family is listed in address order below.
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$0000 - $000F
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0000
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PORTA
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PORTB
DDRA
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
DDRB
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 1
0
Bit 0
0
Bit 7
Bit 7
6
5
5
4
4
3
3
2
6
0
Bit 2
0
0
PEAR
NOACCE
MODC
PUPKE
PIPOE
NECLK
0
LSTRE
RDWE
0
MODE
MODB
0
MODA
0
IVIS
0
EMK
EME
PUPAE
RDPA
0
0
0
0
PUCR
PUPEE
PUPBE
0
0
0
0
0
0
0
0
0
RDRIV
RDPK
0
RDPE
0
RDPB
0
EBICTL
Reserved
ESTR
0
0
0
0
$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Address
$0010
Name
Bit 7
RAM15
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
RAMHAL
0
Read:
Write:
Read:
Write:
INITRM
RAM14
RAM13
RAM12
RAM11
0
0
$0011
INITRG
Name
REG14
Bit 6
REG13
Bit 5
REG12
Bit 4
REG11
Bit 3
Address
Bit 7
Bit 2
Bit 1
Bit 0
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$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Address
$0012
Name
Bit 7
EE15
0
Bit 6
EE14
0
Bit 5
EE13
0
Bit 4
EE12
0
Bit 3
Bit 2
0
Bit 1
0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
INITEE
EE11
EEON
$0013
$0014
MISC
EXSTR1 EXSTR0 ROMHM ROMON
0
0
0
0
0
0
0
0
Reserved
$0015 - $0016
INT map 1 of 2 (HCS12 Interrupt)
Address
$0015
Name
ITCR
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
WRINT
ADR3
ADR2
ADR1
ADR0
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0017
MMC map 2 of 4 (HCS12 Module Mapping Control)
Address
$0017
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Reserved
$0018 - $0018
Miscellaneous Peripherals (Device User Guide)
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0018
Reserved
$0019 - $0019
VREG3V3 (Voltage Regulator)
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
LVDS
Bit 1
LVIE
Bit 0
LVIF
Read:
Write:
$0019
VREGCTRL
$001A - $001B
Miscellaneous Peripherals (Device User Guide)
Address
$001A
Name
Bit 7
ID15
Bit 6
ID14
Bit 5
ID13
Bit 4
ID12
Bit 3
ID11
Bit 2
ID10
Bit 1
ID9
Bit 0
ID8
Read:
Write:
Read:
Write:
PARTIDH
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
$001B
PARTIDL
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$001C - $001D
MMC map 3 of 4 (HCS12 Module Mapping Control,
Device User Guide)
Address
$001C
Name
Bit 7
Read: reg_sw0
Write:
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
eep_sw1 eep_sw0
ram_sw2 ram_sw1 ram_sw0
MEMSIZ0
Read: rom_sw1 rom_sw0
Write:
0
0
0
0
pag_sw1 pag_sw0
$001D
MEMSIZ1
$001E - $001E
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$001E
Name
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
INTCR
IRQE
IRQEN
$001F - $001F
INT map 2 of 2 (HCS12 Interrupt)
Address
$001F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
HPRIO
$0020 - $002F
DBG (including BKP) map 1 of 1 (HCS12 Debug)
Address
Name
DBGC1
Bit 7
DBGEN
AF
Bit 6
ARM
BF
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
Bit 0
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
TRGSEL BEGIN DBGBRK
CAPMOD
$0020
-
CF
0
DBGSC
TRG
$0021
-
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
$0022
$0023
$0024
$0025
$0026
$0027
$0028
-
DBGTBL
Bit 7
TBF
Bit 6
0
-
DBGCNT
CNT
-
DBGCCX
-
DBGCCH
PAGSEL
EXTCMP
Bit 15
Bit 7
14
6
13
5
12
4
11
10
2
9
1
Bit 8
Bit 0
RWC
DBGCCL
-
3
DBGC2
BKPCT0
DBGC3
BKPCT1
DBGCAX
BKP0X
DBGCAH
BKP0H
BKABEN
FULL
BDM
TAGAB BKCEN
TAGC
RWCEN
RWBEN
BKAMBH BKAMBL BKBMBH BKBMBL RWAEN
PAGSEL
Bit 15 14
RWA
10
RWB
$0029
$002A
$002B
EXTCMP
13
12
11
9
Bit 8
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$0020 - $002F
DBG (including BKP) map 1 of 1 (HCS12 Debug)
Address
$002C
Name
DBGCAL
BKP0L
DBGCBX
BKP1X
DBGCBH
BKP1H
DBGCBL
BKP1L
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
read
write
read
write
read
write
read
write
$002D
$002E
$002F
PAGSEL
EXTCMP
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0030 - $0031
MMC map 4 of 4 (HCS12 Module Mapping Control)
Address
$0030
Name
Bit 7
0
Bit 6
0
Bit 5
PIX5
0
Bit 4
PIX4
0
Bit 3
PIX3
0
Bit 2
PIX2
0
Bit 1
PIX1
0
Bit 0
PIX0
0
Read:
Write:
Read:
Write:
PPAGE
0
0
$0031
Reserved
$0032 - $0033
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0032
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
1
PORTK
(1)
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
NOTES:
1. Only applicable in special emulation-only bond outs, for emulation of extended memory map.
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$0034
Name
SYNR
Bit 7
0
Bit 6
0
Bit 5
SYN5
0
Bit 4
SYN4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
SYN3
SYN2
SYN1
SYN0
0
0
$0035
$0036
$0037
$0038
$0039
$003A
REFDV
REFDV3 REFDV2 REFDV1 REFDV0
Read: TOUT7
Write:
TOUT6
TOUT5
TOUT4
TOUT3
LOCK
0
TOUT2
TRACK
0
TOUT1
TOUT0
SCM
0
CTFLG
TEST ONLY
Read:
Write:
Read:
Write:
Read:
Write:
0
0
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTIF
PROF
0
LOCKIF
LOCKIE
SCMIF
SCMIE
RTIWAI
PCE
RTIE
PLLSEL
PSTP
SYSWAI ROAWAI
AUTO ACQ
PLLWAI
0
CWAI
PRE
COPWAI
SCME
Read:
CME
PLLON
Write:
For More Information On This Product,
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Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$003B
Name
Bit 7
0
Bit 6
Bit 5
RTR5
0
Bit 4
RTR4
0
Bit 3
RTR3
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
RTICTL
RTR6
RTR2
RTR1
RTR0
$003C
$003D
$003E
$003F
COPCTL
WCOP
RSBCK
CR2
0
CR1
CR0
0
0
0
FORBYP
TEST ONLY
RTIBYP COPBYP
PLLBYP
TCTL4
FCM
Read: TCTL7
Write:
TCTL6
TCTL5
TCLT3
TCTL2
TCTL1
TCTL0
CTCTL
TEST ONLY
Read:
Write:
0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
ARMCOP
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0040
TIOS
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
0
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
$004F
CFORC
OC7M
OC7D
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D7
Bit 15
OC7D6
14
OC7D5
13
OC7D4
12
OC7D3
11
OC7D2
10
OC7D1
9
OC7D0
Bit 8
TCNT (hi)
TCNT (lo)
TSCR1
TTOV
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
TEN
TOV7
OM7
OM3
EDG7B
EDG3B
C7I
TSWAI
TOV6
OL7
TSFRZ
TOV5
TFFCA
TOV4
OL6
TOV3
OM5
TOV2
OL5
TOV1
OM4
TOV0
OL4
TCTL1
TCTL2
TCTL3
TCTL4
TIE
OM6
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7A
EDG3A
EDG6B
EDG2B
EDG6A
EDG2A
EDG5B
EDG1B
C3I
EDG5A
EDG1A
C2I
EDG4B
EDG0B
C1I
EDG4A
EDG0A
C0I
C6I
0
C5I
0
C4I
0
TSCR2
TFLG1
TFLG2
TOI
TCRE
PR2
PR1
PR0
C7F
C6F
0
C5F
0
C4F
0
C3F
0
C2F
0
C1F
0
C0F
0
TOF
For More Information On This Product,
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Device User Guide — 9S12C128DGV1/D V01.04
Address
$0050
Name
Bit 7
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit 8
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 15
TC0 (hi)
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PAI
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
TC0 (lo)
TC1 (hi)
TC1 (lo)
TC2 (hi)
TC2 (lo)
TC3 (hi)
TC3 (lo)
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Bit 7
0
PAEN
0
PAMOD
0
PEDGE
0
CLK1
0
CLK0
0
PAOVI
PAOVF
9
0
PAFLG
PAIF
Bit 8
Bit 15
14
13
12
11
10
PACNT (hi)
PACNT (lo)
Reserved
Reserved
Reserved
Reserved
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
For More Information On This Product,
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Address
$0068
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$0069
$006A
$006B
$006C
$006D
$006E
$006F
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
$0070 - $007F
Reserved
Read:
Write:
0
0
0
0
0
0
0
0
$0070
- $007F
Reserved
$0080 - $009F
ATD (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0080
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATDCTL0
0
0
0
0
0
0
0
0
$0081
$0082
$0083
$0084
$0085
$0086
$0087
$0088
$0089
$008A
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
ATDSTAT0
Reserved
ATDTEST0
ATDTEST1
Reserved
ASCIF
ADPU
0
AFFC
S8C
AWAI
S4C
ETRIGLE ETRIGP
ETRIG
FIFO
ASCIE
FRZ1
PRS1
S2C
PRS4
MULT
S1C
FRZ0
PRS0
SRES8
DJM
SMP1
SMP0
SCAN
PRS3
0
PRS2
DSGN
0
CC
CB
CA
0
0
0
0
0
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SC
0
For More Information On This Product,
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Device User Guide — 9S12C128DGV1/D V01.04
$0080 - $009F
ATD (Analog to Digital Converter 10 Bit 8 Channel)
Address
$008B
Name
Bit 7
CCF7
Bit 6
CCF6
Bit 5
CCF5
Bit 4
CCF4
Bit 3
CCF3
Bit 2
CCF2
Bit 1
CCF1
Bit 0
CCF0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATDSTAT1
0
0
0
0
0
0
0
0
$008C
$008D
$008E
$008F
$0090
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
$0099
$009A
$009B
$009C
$009D
$009E
$009F
Reserved
ATDDIEN
Reserved
PORTAD0
ATDDR0H
ATDDR0L
ATDDR1H
ATDDR1L
ATDDR2H
ATDDR2L
ATDDR3H
ATDDR3L
ATDDR4H
ATDDR4L
ATDDR5H
ATDDR5L
ATDDR6H
ATDDR6L
ATDDR7H
ATDDR7L
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Bit7
Bit15
Bit7
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
BIT 0
Bit8
0
14
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
14
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
Bit6
$00A0 - $00C7
Reserved
Read:
Write:
0
0
0
0
0
0
0
0
$00A0
Reserved
- $00C7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12C128DGV1/D V01.04
$00C8 - $00CF
SCI (Asynchronous Serial Interface)
Address
$00C8
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SBR12
SBR11
SBR10
SBR9
SBR8
SCIBDH
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
SCIBDL
SCICR1
SCICR2
SCISR1
SCISR2
SCIDRH
SCIDRL
SBR7
SBR6
SBR5
RSRC
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
TDRE
RDRF
IDLE
OR
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D0 - $00D7
Reserved
Read:
Write:
0
0
0
0
0
0
0
0
$00D0
Reserved
- $00D7
$00D8 - $00DF
SPI (Serial Peripheral Interface)
Address
$00D8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPICR1
MSTR
CPOL
SSOE
LSBFE
$00D9
$00DA
$00DB
$00DC
$00DD
$00DE
$00DF
SPICR2
SPIBR
MODFEN BIDIROE
SPISWAI
SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPISR
0
0
0
0
0
Reserved
SPIDR
Bit7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit0
0
Reserved
Reserved
0
0
0
0
0
0
0
0
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$00E0 - $00FF
PWM (Pulse Width Modulator)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
$00E0
PWME
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
0
0
0
0
0
0
0
0
0
$00E1
$00E2
$00E3
$00E4
$00E5
$00E6
$00E7
$00E8
$00E9
$00EA
$00EB
$00EC
$00ED
$00EE
$00EF
$00F0
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
PWMPOL
PWMCLK
PWMPRCLK
PWMCAE
PWMCTL
PPOL5
PCLK5
PCKB1
CAE5
PPOL4
PCLK4
PCKB0
CAE4
PPOL3
PPOL2
PCLK2
PCKA2
CAE2
PPOL1
PCLK1
PCKA1
PPOL0
PCLK0
PCKA0
PCLK3
0
PCKB2
0
CAE3
CAE1
0
CAE0
0
CON45
0
CON23
0
CON01
0
PSWAI
0
PFRZ
0
0
0
0
0
PWMTST
Test Only
0
6
0
5
0
4
0
3
0
2
PWMPRSC
PWMSCLA
PWMSCLB
PWMSCNTA
PWMSCNTB
PWMCNT0
PWMCNT1
PWMCNT2
PWMCNT3
PWMCNT4
PWMCNT5
PWMPER0
PWMPER1
PWMPER2
PWMPER3
PWMPER4
Bit 7
1
Bit 0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
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Device User Guide — 9S12C128DGV1/D V01.04
Address
$00F7
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWMPER5
$00F8
$00F9
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
Reserved
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
Reserved
$0100 - $010F
Flash Control Register
Address
$0100
Name
Bit 7
Read: FDIVLD
Write:
Bit 6
Bit 5
FDIV5
NV5
Bit 4
FDIV4
NV4
Bit 3
FDIV3
NV3
Bit 2
FDIV2
NV2
Bit 1
FDIV1
SEC1
Bit 0
FDIV0
SEC0
FCLKDIV
PRDIV8
Read: KEYEN1 KEYEN0
$0101
$0102
$0103
$0104
$0105
$0106
$0107
$0108
$0109
$010A
$010B
FSEC
FTSTMOD
FCNFG
FPROT
FSTAT
Write:
Read:
0
0
0
0
0
0
0
0
WRALL
0
0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CBEIE
FPOPEN
CCIE
KEYACC
FPHDIS
PVIOL
BKSEL1 BKSEL0
NV6
FPHS1
FPHS0
0
FPLDIS
BLANK
FPLS1
0
FPLS0
0
CCIF
CBEIF
0
ACCERR
0
0
0
0
0
0
0
0
0
0
0
0
0
FCMD
CMDB6
0
CMDB5
0
CMDB2
0
CMDB0
0
0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
Reserved for
Factory Test
Reserved for
Factory Test
Reserved for
Factory Test
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$0100 - $010F
Flash Control Register
Address
$010C
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$010D
$010E
$010F
Reserved
Reserved
Reserved
$0110 - $013F
Reserved
Read:
Write:
0
0
0
0
0
0
0
0
$0110
- $003F
Reserved
1
$0140 - $017F
CAN (Motorola Scalable CAN - MSCAN)
Address
$0140
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
RXFRM
CSWAI
WUPE
SLPRQ
SLPAK
INITRQ
INITAK
CANCTL0
CANE
SJW1
SAMP
WUPIF
CLKSRC
SJW0
LOOPB
BRP5
LISTEN
BRP4
WUPM
BRP2
$0141
$0142
$0143
$0144
$0145
$0146
$0147
$0148
$0149
$014A
$014B
$014C
$014D
CANCTL1
CANBTR0
CANBTR1
CANRFLG
CANRIER
CANTFLG
CANTIER
CANTARQ
CANTAAK
CANTBSEL
CANIDAC
Reserved
Reserved
BRP3
BRP1
BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1
RSTAT0
TSTAT1
TSTAT0
CSCIF
OVRIF
OVRIE
TXE1
RXF
RXFIE
TXE0
WUPIE
0
CSCIE
0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
ABTRQ2
ABTAK2
ABTRQ1
ABTAK1
ABTRQ0
ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
0
0
0
0
0
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1
$0140 - $017F
CAN (Motorola Scalable CAN - MSCAN)
Address
$014E
Name
Bit 7
RXERR7
Bit 6
RXERR6
Bit 5
RXERR5
Bit 4
RXERR4
Bit 3
RXERR3
Bit 2
RXERR2
Bit 1
RXERR1
Bit 0
RXERR0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CANRXERR
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
$014F
CANTXERR
$0150 -
$0153
CANIDAR0 -
CANIDAR3
AC7
AM7
AC7
AM7
AC6
AM6
AC6
AM6
AC5
AM5
AC5
AM5
AC4
AM4
AC4
AM4
AC3
AM3
AC3
AM3
AC2
AM2
AC2
AM2
AC1
AM1
AC1
AM1
AC0
AM0
AC0
AM0
$0154 -
$0157
CANIDMR0 -
CANIDMR3
$0158 -
$015B
CANIDAR4 -
CANIDAR7
$015C - CANIDMR4 -
$015F
CANIDMR7
FOREGROUND RECEIVE BUFFER see Table 1-2
$0160 -
$016F
CANRXFG
$0170 -
$017F
CANTXFG
FOREGROUND TRANSMIT BUFFER see Table 1-2
NOTES:
1. Not available on the MC9S12GC-Family members. Those memory locations should not be accessed.
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
Extended ID Read:
Standard ID Read:
CANxRIDR0 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR1 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR2 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR3 Write:
$xxx0
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID9
ID16
ID8
ID15
ID7
$xxx1
$xxx2
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID1
ID0
RTR
$xxx3
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$xxx4- CANxRDSR0 -
$xxxB
CANxRDSR7
DLC3
DLC2
DLC1
DLC0
$xxxC
CANRxDLR
$xxxD
$xxxE
$xxxF
Reserved
TSR14
TSR6
TSR13
TSR5
TSR12
TSR4
TSR11
TSR3
TSR10
TSR2
TSR9
TSR1
TSR8
TSR0
CANxRTSRH
CANxRTSRL
Extended ID Read:
CANxTIDR0 Write:
Standard ID Read:
Write:
ID28
ID10
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
$xx10
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Address
$xx11
Name
Bit 7
ID20
Bit 6
ID19
Bit 5
ID18
Bit 4
Bit 3
Bit 2
ID17
Bit 1
ID16
Bit 0
ID15
Extended ID Read:
CANxTIDR1 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR2 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR3 Write:
Standard ID Read:
Write:
SRR=1
IDE=1
ID2
ID1
ID0
RTR
ID11
IDE=0
ID10
ID14
ID13
ID12
ID9
ID1
ID8
ID0
ID7
$xx12
ID6
DB7
ID5
ID4
ID3
ID2
RTR
$xx13
Read:
Write:
Read:
Write:
Read:
Write:
$xx14- CANxTDSR0 -
$xx1B
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CANxTDSR7
$xx1C
CANxTDLR
DLC3
DLC2
DLC1
DLC0
$xx1D
$xx1E
$xx1F
CONxTTBPR
CANxTTSRH
CANxTTSRL
PRIO7
PRIO6
TSR14
PRIO5
TSR13
PRIO4
TSR12
PRIO3
TSR11
PRIO2
TSR10
PRIO1
TSR9
PRIO0
TSR8
Read: TSR15
Write:
Read: TSR7
Write:
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$0180 - $023F
Reserved
Read:
Write:
0
0
0
0
0
0
0
0
$0180
- $023F
Reserved
$0240 - $027F
PIM (Port Interface Module)
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0240
$0241
$0242
$0243
$0244
$0245
$0246
$0247
$0248
PTT
PTIT
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT
RDRT
PERT
PPST
DDRT7
RDRT7
PERT7
DDRT7
RDRT6
PERT6
DDRT5
RDRT5
PERT5
DDRT4
RDRT4
PERT4
DDRT3
RDRT3
PERT3
DDRT2
RDRT2
PERT2
DDRT1
RDRT1
PERT1
DDRT0
RDRT0
PERT0
PPST7
0
PPST6
0
PPST5
0
PPST4
0
PPST3
0
PPST2
0
PPST1
0
PPST0
0
Reserved
MODRR
PTS
0
0
0
0
0
0
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
0
PTS3
PTS2
PTS1
PTS0
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Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: PTIP7
Write:
Read:
DDRP7
Write:
Read:
RDRP7
Write:
Read:
PERP7
Write:
Read:
PPSP7
Write:
Read:
PIEP7
Write:
Read:
PIFP7
Write:
Read:
Write:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTIS3
PTIS2
PTIS1
PTIS0
$0249
$024A
$024B
$024C
$024D
$024E
$024F
$0250
$0251
$0252
$0253
$0254
$0255
$0256
$0257
$0258
$0259
$025A
$025B
$025C
$025D
$025E
$025F
$0260
PTIS
DDRS
RDRS
PERS
PPSS
WOMS
Reserved
PTM
DDRS3
RDRS3
PERS3
PPSS3
DDRS2
RDRS2
PERS2
PPSS2
DDRS1
RDRS1
PERS1
PPSS1
DDRS0
RDRS0
PERS0
PPSS0
WOMS3
0
WOMS2
0
WOMS1
0
WOMS0
0
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
PTIM
DDRM
RDRM
PERM
PPSM
WOMM
Reserved
PTP
DDRM5
RDRM5
PERM5
PPSM5
DDRM4
RDRM4
PERM4
PPSM4
DDRM3
RDRM3
PERM3
PPSM3
DDRM2
RDRM2
PERM2
PPSM2
DDRM1
RDRM1
PERM1
PPSM1
DDRM0
RDRM0
PERM0
PPSM0
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
0
0
0
0
0
0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
PTIP
DDRP
RDRP
PERP
PPSP
PIEP
DDRP7
RDRP6
PERP6
PPSP6
PIEP6
DDRP5
RDRP5
PERP5
PPSP5
PIEP5
DDRP4
RDRP4
PERP4
PPSP4
PIEP4
DDRP3
RDRP3
PERP3
PPSP3
PIEP3
DDRP2
RDRP2
PERP2
PPSP2
PIEP2
DDRP1
RDRP1
PERP1
PPSP1
PIEP1
DDRP0
RDRP0
PERP0
PPSS0
PIEP0
PIFP
PIFP6
0
PIFP5
0
PIFP4
0
PIFP3
0
PIFP2
0
PIFP1
0
PIFP0
0
0
Reserved
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Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$0261
$0262
$0263
$0264
$0265
$0266
$0267
$0268
$0269
$026A
$026B
$026C
$026D
$026E
$026F
$0270
$0271
$0272
$0273
$0274
$0275
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PTJ
PTJ7
PTJ6
PTIJ7
PTIJ6
PTIJ
DDRJ
DDRJ7
RDRJ7
PERJ7
PPSJ7
PIEJ7
DDRJ7
RDRJ6
PERJ6
PPSJ6
PIEJ6
RDRJ
PERJ
PPSJ
PIEJ
PIFJ
PIFJ7
PIFJ6
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PTIJ7
PTAD
PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1
PTIAD
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0
PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0
DDRAD
RDRAD
PERAD
PPSAD
Reserved
0
0
0
0
0
0
0
0
$0276-
$027F
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$0280 - $03FF
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
$0280
- $2FF
Reserved
0
0
0
0
0
0
0
0
$0300 -
$03FF
Unimplemented
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned
part ID numbers.
Table 1-3 Assigned Part ID Numbers
1
Device
Mask Set Number
0L45J
1L45J
2L45J
TBD
Part ID
$3300
$3300
$3302
TBD
MC9S12C32
MC9S12C32
MC9S12C32
MC9S12C64
MC9S12C96
MC9S12C128
MC9S12C128
MC9S12GC16
MC9S12GC32
MC9S12GC64
MC9S12GC128
TBD
TBD
0L09S
1L09S
TBD
$3100
$3101
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to Module Mapping
and Control (MMC) Block Guide for further details.
Table 1-4 Memory size registers
Device
Register name
MEMSIZ0
Value
$00
MC9S12GC16
MEMSIZ1
$80
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Table 1-4 Memory size registers
Device
Register name
Value
$00
$80
$01
$C0
$01
$C0
$01
$C0
MEMSIZ0
MC9S12C32, MC9S12GC32
MC9S12C64, MC9S12GC64
MC9S12C96
MEMSIZ1
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
MC9S12C128, MC9S12GC128
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Section 2 Signal Description
2.1 Device Pinout
O
S
W
P
P
V
V
M
M
M
P
M
P
J
J
P
S
S
P
P
V
V
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PW3/KWP3/PP3
PW2/KWP2/PP2
PW1/KWP1/PP1
PW0/KWP0/PP0
PW0/IOC0/PT0
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
1
2
3
4
5
6
7
8
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
9
VSS1
PW4/IOC4/PT4
IOC5/PT5
10
11
12
13
14
15
16
17
18
19
20
MC9S12C-Family
MC9S12GC-Family
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family
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S
W
P
V
V
M
M
M
P
M
P
P
P
V
5
5
5
4
8
7
6
5
4
3
2
1
0
VRH
39
PW3/KWP3/PP3
1
PW0/IOC0/PT0
VDDA
38
37
36
35
34
33
32
31
30
29
28
27
2
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
PAD07/AN07
PAD06/AN06
PAD05/AN05
3
4
5
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
PA2
6
MC9S12C-Family
MC9S12GC-Family
VSS1
7
PW4/IOC4/PT4
IOC5/PT5
8
9
10
11
12
13
IOC6/PT6
IOC7/PT7
PA1
MODC/BKGD
PB4
PA0
* Signals shown in Bold italic are not available on the 48 Pin Package
Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family
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S
P
V
V
M
M
M
P
M
P
P
P
V
4
4
4
5
4
3
2
1
0
9
8
7
PW0/IOC0/PT0
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
VRH
1
36
35
34
33
32
31
30
29
28
27
26
25
2
VDDA
3
PAD07/AN07
PAD06/AN06
PAD05/AN05
4
5
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
PA0
VSS1
6
MC9S12C-Family
MC9S12GC-Family
PW4/IOC4/PT4
IOC5/PT5
7
8
9
IOC6/PT6
10
11
12
IOC7/PT7
MODC/BKGD
PB4
XIRQ/PE0
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family
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2.2 Signal Properties Summary
Table 2-1 Signal Properties
Internal Pull
Resistor
Pin Name Pin Name Pin Name Power
Function 1 Function 2 Function 3 Domain
Description
Reset
CTRL
State
EXTAL
XTAL
RESET
XFC
—
—
—
—
VDDPLL
VDDPLL
VDDX
NA
NA
NA
Oscillator pins
NA
—
—
None
NA
None
NA
External reset pin
PLL loop filter pin
Test pin only
—
—
VDDPLL
VSSX
TEST
BKGD
PE7
VPP
MODC
NOACC
—
NA
NA
TAGHI
XCLKS
VDDX
Up
Up
Background debug, mode pin, tag signal high
Port E I/O pin, access, clock select
VDDX
PUCR
Up
While RESET
pin is low: Down
PE6
PE5
PE4
IPIPE1
IPIPE0
ECLK
MODB
MODA
—
VDDX
VDDX
VDDX
Port E I/O pin and pipe status
Port E I/O pin and pipe status
Port E I/O pin, bus clock output
While RESET
pin is low: Down
Mode
PUCR
Dep1
Mode
PUCR
PE3
PE2
LSTRB
R/W
TAGLO
—
VDDX
VDDX
Port E I/O pin, low strobe, tag signal low
Port E I/O pin, R/W in expanded modes
Dep(1)
Mode
PUCR
Dep(1)
PE1
PE0
IRQ
—
—
VDDX
VDDX
PUCR
PUCR
Up
Up
Port E input, external interrupt pin
XIRQ
Port E input, non-maskable interrupt pin
ADDR[15:1/
DATA[15:1]
PA[7:3]
PA[2:1]
PA[0]
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDA
VDDX
VDDX
VDDX
VDDX
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
Disabled Port A I/O pin & multiplexed address/data
Disabled Port A I/O pin & multiplexed address/data
Disabled Port A I/O pin & multiplexed address/data
Disabled Port B I/O pin & multiplexed address/data
Disabled Port B I/O pin & multiplexed address/data
Disabled Port B I/O pin & multiplexed address/data
Disabled Port AD I/O pins and ATD inputs
ADDR[10:9/
DATA[10:9]
—
—
ADDR[8]/
DATA[8]
ADDR[7:5]/
DATA[7:5]
PB[7:5]
PB[4]
—
ADDR[4]/
DATA[4]
—
ADDR[3:0]/
DATA[3:0]
PB[3:0]
PAD[7:0]
PP[7]
—
PERAD/P
PSAD
AN[7:0]
KWP[7]
KWP[6]
KWP[5]
—
PERP/
PPSP
—
Disabled Port P I/O Pins and keypad wake-up
PERP/
PPSP
Port P I/O Pins, keypad wake-up and ROMON
PP[6]
ROMCTL
PW5
PW[4:3]
Disabled
enable.
PERP/
PPSP
PP[5]
Disabled Port P I/O Pin, keypad wake-up, PW5 output
PERP/
PPSP
PP[4:3]
KWP[4:3]
Disabled Port P I/O Pin, keypad wake-up, PWM output
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Internal Pull
Resistor
Pin Name Pin Name Pin Name Power
Function 1 Function 2 Function 3 Domain
Description
Reset
State
CTRL
PERP/
PPSP
PP[2:0]
PJ[7:6]
PM5
KWP[2:0]
KWJ[7:6]
SCK
PW[2:0]
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Disabled Port P I/O Pins, keypad wake-up, PWM outputs
Disabled Port J I/O Pins and keypad wake-up
PERJ/
PPSJ
—
—
PERM/
PPSM
Up
Up
Up
Up
Up
Up
Up
Up
Up
Port M I/O Pin and SPI SCK signal
Port M I/O Pin and SPI MOSI signal
Port M I/O Pin and SPI SS signal
Port M I/O Pin and SPI MISO signal
PERM/
PPSM
PM4
MOSI
—
PERM/
PPSM
PM3
SS
—
PERM/
PPSM
PM2
MISO
—
PERM/
PPSM
Port M I/O Pin and CAN transmit signal2
Port M I/O Pin and CAN receive signal2
Port S I/O Pins
PM1
TXCAN
RXCAN
—
—
PERM/
PPSM
PM0
—
PERS/
PPSS
PS[3:2]
PS1
—
PERS/
PPSS
TXD
—
Port S I/O Pin and SCI transmit signal
Port S I/O Pin and SCI receive signal
PERS/
PPSS
PS0
RXD
—
PERT/
PPST
PT[7:5]
IOC[7:5]
IOC[4:0]
—
Disabled Port T I/O Pins shared with timer (TIM)
Disabled Port T I/O Pins shared with timer and PWM
PERT/
PPST
PT[4:0]
PW[4:0]
NOTES:
1. The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. E.g. in
special test mode RDWE=LSTRE=1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to S12_MEBI
user guide for PEAR register details.
2. CAN functionality is not available on the MC9S12GC-Family members
2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions
Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the
registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the
following pins:
(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6],
PortS[3:2]
(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6],
PortS[3:2]
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2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing.
2.3.3 TEST / VPP — Test Pin
This pin is reserved for test and must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop
filter. Please ask your Motorola representative for the interactive application note to compute PLL loop
filter elements. Any current leakage on this pin must be avoided.
XFC
R
0
C
P
MCU
C
S
VDDPLL
VDDPLL
Figure 2-4 PLL Loop Filter Connections
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2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when
the state of this pin is latched to the MODC bit.
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins,. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48 package
version. PA[7:3] are not available in the 52 pin package version.
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PB[7:5] and PB[3:0] pins are not available in the
48 nor 52 pin package version.
2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.The XCLKS is an input signal which controls whether a
crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce
oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If
the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If
input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts
oscillator circuit on EXTAL and XTAL.
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EXTAL
C
*
DC
C
MCU
Crystal or
1
ceramic resonator
XTAL
C
2
VSSPLL
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
.Please contact the crystal manufacturer for crystal DC
Figure 2-5 Colpitts Oscillator Connections (PE7=1)
EXTAL
C
1
MCU
R
Crystal or
B
ceramic resonator
*
R
S
XTAL
C
2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 2-6 Pierce Oscillator Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATO
(VDDPLL-Level)
R
MCU
XTAL
not connected
Figure 2-7 External Clock Connections (PE7=0)
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2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1}. This pin is an input with a pull-down device which is only
active when RESET is low. PE[6] is not available in the 48 / 52 pin package versions.
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0}. This pin is an input with a pull-down device which is only
active when RESET is low. This pin is not available in the 48 / 52 pin package versions.
2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output
ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in
expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency
out of reset. The ECLK pin is initially configured as ECLK output with stretch in all expanded modes. The
E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in
the MODE register and the ESTR bit in the EBICTL register. All clocks, including the E clock, are halted
when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses. Reference the MISC register (EXSTR[1:0] bits) for
more information. In normal expanded narrow mode, the E clock is available for use in external select
decode logic or as a constant speed clock for use in the external application system. Alternatively PE4 can
be used as a general purpose input or output pin.
2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)
In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of
reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register.
This signal is used in write operations. Therefore external low byte writes will not be possible until this
function is enabled. This pin is also used as TAGLO in Special Expanded modes and is multiplexed with
the LSTRB function. This pin is not available in the 48 / 52 pin package versions.
2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write
In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of
reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until enabled. This pin is not available in the 48 / 52 pin
package versions.
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2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling
edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is
always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing
IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code
register. This pin is always an input and can always be read. There is an active pull-up on this pin while in
reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin
The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During
reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software
enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR
network. This pin is always an input and can always be read. There is an active pull-up on this pin while
in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR
register.
2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]
PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In
order to use a PAD pin as a standard I/O, the corresponding ATDDIEN register bit must be set. These bits
are cleared out of reset to configure the PAD pins for A/D operation.
When the A/D converter is active in multi-channel mode, port inputs are scanned and converted
irrespective of PortAD configuration. Thus PortAD pins that are configured as digital inputs or digital
outputs are also converted in the A/D conversion sequence.
2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]
PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions.
2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]
PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used
to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
PP6=1 in emulation modes equates to ROMON =0 (ROM space externally mapped)
PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)
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2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0]
PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When
configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode.
PP[5:0] are also shared with the PWM output signals, PW[5:0]. Pins PP[2:0] are only available in the 80
pin package version. Pins PP[4:3] are not available in the 48 pin package version.
2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6]
PJ[7:6] are general purpose input or output pins, shared with the keypad interrupt function. When
configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. These
pins are not available in the 48 pin package version nor in the 52 pin package version.
2.3.21 PM5 / SCK — Port M I/O Pin 5
PM5 is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral
Interface (SPI).
2.3.22 PM4 / MOSI — Port M I/O Pin 4
PM4 is a general purpose input or output pin and also the master output (during master mode) or slave
input (during slave mode) pin for the Serial Peripheral Interface (SPI).
2.3.23 PM3 / SS — Port M I/O Pin 3
PM3 is a general purpose input or output pin and also the slave select pin SS for the Serial Peripheral
Interface (SPI).
2.3.24 PM2 / MISO — Port M I/O Pin 2
PM2 is a general purpose input or output pin and also the master input (during master mode) or slave
output (during slave mode) pin for the Serial Peripheral Interface (SPI).
2.3.25 PM1 / TXCAN — Port M I/O Pin 1
PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module if
available.
2.3.26 PM0 / RXCAN — Port M I/O Pin 0
PM0 is a general purpose input or output pin and the receive pin, RXCAN, of the CAN module if available.
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2.3.27 PS[3:2] — Port S I/O Pins [3:2]
PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin
package versions.
2.3.28 PS1 / TXD — Port S I/O Pin 1
PS1 is a general purpose input or output pin and the transmit pin, TXD, of Serial Communication Interface
(SCI).
2.3.29 PS0 / RXD — Port S I/O Pin 0
PS0 is a general purpose input or output pin and the receive pin, RXD, of Serial Communication Interface
(SCI).
2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5]
PT7-PT5 are general purpose input or output pins. They can also be configured as the timer system input
capture or output compare pins IOC7-IOC5.
2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]
PT4-PT0 are general purpose input or output pins. They can also be configured as the timer system input
capture or output compare pins IOC4-IOC0 or as the PWM outputs PW[4:0].
2.4 Power Supply Pins
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins
are loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator
External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the
internal voltage regulator.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal
voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned
off, if VDDR is tied to ground.
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2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the
analog to digital converter.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
Table 2-2 MC9S12C-Family Power and Ground Connection Summary
Nominal
Voltage
Mnemonic
Description
VDD1
VDD2
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and bypass
the internal voltage regulator.
2.5 V
VSS1
VSS2
0V
In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.
VDDR
VSSR
VDDX
VSSX
VDDA
5.0 V
0 V
External power and ground, supply to internal voltage regulator.
External power and ground, supply to pin drivers.
5.0 V
0 V
5.0 V
Operating voltage and ground for the analog-to-digital converters and the
reference for the internal voltage regulator, allows the supply voltage to the
A/D to be bypassed independently.
VSSA
0 V
VRH
VRL
5.0 V
0 V
Reference voltage low for the ATD converter.
In the 48 and 52 LQFP packages VRL is bonded to VSSA.
VDDPLL
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop. This
allows the supply voltage to the PLL to be bypassed independently.
Internal power and ground generated by internal regulator.
VSSPLL
0 V
NOTE:All VSS pins must be connected together in the application. Because fast signal transitions
place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on MCU pin load.
Section 3 System Clock Description
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The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User
Guide for details on clock generation.
S12_CORE
core clock
Flash
RAM
TIM
ATD
PIM
EXTAL
SCI
SPI
bus clock
CRG
MSCAN
Not on 9S12GC
oscillator clock
XTAL
VREG
TPM
Figure 3-1 Clock Connections
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12C Family. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
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latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PP6 =
ROMCTL
ROMON
Bit
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
0
0
0
X
1
0
1
X
0
1
X
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
1
1
1
1
0
1
X
1
0
1
0
1
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the S12_MEBI block guide.
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
Description
1
0
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
Protection of the contents of FLASH,
Operation in single-chip mode,
Operation from external memory with internal FLASH disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
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of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH, the part can be secured by programming the security bits
located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part
and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be
blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an
external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via
the Backdoor Key Access. Refer to Flash Block Guide for details.
Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a
program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase
and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but
the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to
an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).
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4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption reduction the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
External Reset, Power On Reset or Low
$FFFE, $FFFF
Voltage Reset (see CRG Flags Register None
to determine reset source)
None
–
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
Clock Monitor fail reset
COP failure reset
None
None
None
COPCTL (CME, FCME)
COP rate select
None
–
–
–
Unimplemented instruction trap
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$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
SWI
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
None
None
–
XIRQ
–
IRQ
INTCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
Real Time Interrupt
Standard Timer channel 0
Standard Timer channel 1
Standard Timer channel 2
Standard Timer channel 3
Standard Timer channel 4
Standard Timer channel 5
Standard Timer channel 6
Standard Timer channel 7
Standard Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
SCI
I-Bit
$D6
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
$FFCA, $FFCB
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFBA to $FFC3
$FFB8, $FFB9
$FFB6, $FFB7
Reserved
ATD
I-Bit
ATDCTL2 (ASCIE)
PIEP (PIEP7-6)
$D2
$CE
Reserved
I-Bit
Port J
Reserved
Reserved
Reserved
I-Bit
CRG PLL lock
PLLCR (LOCKIE)
PLLCR (SCMIE)
$C6
$C4
CRG Self Clock Mode
I-Bit
Reserved
I-Bit
FLASH
FCNFG (CCIE, CBEIE)
CANRIER (WUPIE)
$B8
$B6
$B4
$B2
$B0
CAN wake-up1
CAN errors1
CAN receive1
CAN transmit1
I-Bit
$FFB4, $FFB5
$FFB2, $FFB3
I-Bit
I-Bit
I-Bit
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
$FFB0, $FFB1
$FF90 to $FFAF
$FF8E, $FF8F
$FF8C, $FF8D
$FF8A, $FF8B
$FF80 to $FF89
CANTIER (TXEIE[2:0])
Reserved
I-Bit
Port P
PWM Emergency Shutdown
VREG LVI
PIEP (PIEP7-0)
PWMSDN(PWMIE)
CTRL0 (LVIE)
$8E
$8C
$8A
I-Bit
I-Bit
Reserved
NOTES:
1. Not available on MC9S12GC-Family members
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are
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changed to known start-up states. Refer to the respective module Block User Guides for register reset
states.
5.3.1 Reset Summary Table
Table 5-2 Reset Summary
Reset
Priority
Source
Vector
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Power-on Reset
1
1
1
2
3
CRG Module
RESET pin
External Reset
Low Voltage Reset
Clock Monitor Reset
COP Watchdog Reset
VREG Module
CRG Module
CRG Module
5.3.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External
Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to Figure 1-2 to Figure 1-5 footnotes for locations of the memories depending on the operating
mode after reset.
The RAM array is not automatically initialized out of reset.
NOTE: For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins
should be configured as outputs after reset in order to avoid current drawn from
floating inputs. Refer to Table 2-1 for affected pins.
Section 6 HCS12 Core Block Description
Consult the individual block guides for information about the HCS12 core modules, i.e. central processing
unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus
interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM).
Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods.
6.1 Device-specific information
6.1.1 PPAGE
External paging is not supported on these devices. In order to access the 16K flash blocks in the address
range $8000-$BFFF the PPAGE register must be loaded with the corresponding value for this range. Refer
to Table 6-1 for device specific page mapping.
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For all devices Flash Page 3F is visible in the $C000-$FFFF range if ROMON is set. For all devices (ecept
9S12GC16) Page 3E is also visible in the $4000-$7FFF range if ROMHM is cleared and ROMON is set.
For all devices apart from MC9S12C32 Flash Page 3D is visible in the $0000-$3FFF range if ROMON is
set...
Table 6-1 Device Specific Flash PAGE Mapping
Device
PAGE
PAGE visible with PPAGE contents
$00,$01,$02,$03,$04,$05,$06,$07,$08,$09......$36DS,$37,$38,$39,$3A,$3B,$3C,$3D,$3E,$3
F
MC9S12GC16
3F
3E
3F
3C
3D
3E
3F
3A
3B
3C
3D
3E
3F
38
39
3A
3B
3C
3D
3E
3F
$00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E
$01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$3F
$00,$04,$08,$0C,$10,$14,$18,$1C,$20,$24,$28,$2C,$30,$34,$38,$3C
$01,$05,$09,$0D,$11,$15,$19,$1D,$21,$25,$29,$2D,$31,$35,$39,$3D
$02,$06,$0A,$0E,$12,$16,$1A,$1E,$22,$26,$2A,$2E,$32,$36,$3A,$3E
$03,$07,$0B,$0F,$13,$17,$1B,$1F,$23,$27,$2B,$2F,$33,$37,$3B,$3F
$00,$02,$08,$0A,$10,$12,$18,$1A,$20,$22,$28,$2A,$30,$32,$38,$3A
$01,$03,$09,$0B,$11,$13,$19,$1B,$21,$23,$29,$2B,$31,$33,$39,$3B
$04,$0C,$14,$1C,$24,$2C,$34,$3C
MC9S12C32
MC9S12GC32
MC9S12C64
MC9S12GC64
MC9S12C96
$05,$0D,$15,$1D,$25,$2D,$35,$3D
$06,$0E,$16,$1E,$26,$2E,$36,$3E
$07,$0F,$17,$1F,$27,$2F,$37,$3F
$00,$08,$10,$18,$20,$28,$30,$38
$01,$09,$11,$19,$21,$29,$31,$39
$02,$0A,$12,$1A,$22,$2A,$32,$3A
$03,$0B,$13,$1B,$23,$2B,$33,$3B
MC9S12C128
MC9S12GC128
$04,$0C,$14,$1C,$24,$2C,$34,$3C
$05,$0D,$15,$1D,$25,$2D,$35,$3D
$06,$0E,$16,$1E,$26,$2E,$36,$3E
$07,$0F,$17,$1F,$27,$2F,$37,$3F
6.1.2 BDM alternate clock
The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock.
6.1.3 Extended Address Range Emulation Implications
In order to emulate the MC9S12GC or MC9S12C-Family devices, external addressing of a 128K memory
map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra
external address bus signals via PortK[2:0]. This package version is for emulation only and not provided
as a general production package.
The reset state of DDRK is $00, configuring the pins as inputs.
The reset state of PUPKE in the PUCR register is “1” enabling the internal PortK pullups.
In this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing
unnecessary current flow at the input stage.
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To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE
should not be changed by software.
Section 7 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
7.1 Device-specific information
The VREG is part of the IPBus domain.
7.1.1 VREGEN
VREGEN is connected internally to VDDR.
7.1.2 VDD1, VDD2, VSS1, VSS2
In the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected
together internally. VSS1 and VSS2 are connected together internally.
The extra pin pair enables systems using the 80 pin package to employ better supply routing and further
decoupling.
Section 8 Recommended Printed Circuit Board Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
•
•
•
•
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
VSSPLL must be directly connected to VSSR.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
•
•
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
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Table 8-1 Recommended External Component Values
Component
Purpose
Type
Value
220nF, 470nF1
220nF
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
VDD1 filter capapcitor
VDD2 filter capacitor (80 QFP only)
VDDA filter capacitor
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
100nF
VDDR filter capacitor
>=100nF
100nF
VDDPLL filter capacitor
VDDX filter capacitor
>=100nF
OSC load capacitor
See PLL specification chapter
OSC load capacitor
PLL loop filter capacitor
PLL loop filter capacitor
See PLL specification chapter
Colpitts mode only, if recommended by
quartz manufacturer
C11
DC cutoff capacitor
R1
PLL loop filter resistor
PLL loop filter resistor
PLL loop filter resistor
Quartz
See PLL Specification chapter
R2 / RB
Pierce mode only
R3 / RS
Q1
NOTES:
1. In 48LQFP and 52LQFP package versions, VDD2 is not available. Thus 470nF must be connected
to VDD1.
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V DDX
C
VSSA
C3
VSSX
VDDA
VDD1
VSS1
C1
VSSR
VDDR
Q1
Note:
VSSPLL
VDDPLL
Oscillator in
Colpitts mode.
R1
Figure 8-1 Recommended PCB Layout (48 LQFP)
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)
NOTE: Oscillator in Colpitts mode.
V
C6
VSSA
VSSX
C3
VDDA
VDD1
VSS1
C1
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
Figure 8-2 Recommended PCB Layout (52 LQFP)
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)
NOTE: Oscillator in Colpitts mode.
V DDX
C
VSSA
VSSX
C3
VDDA
VDD1
VSS1
VSS2
VDD2
C2
C1
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
Figure 8-3 Recommended PCB Layout (80 QFP)
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V
C6
VSSA
C3
VSSX
VDDA
VDD1
VSS1
C1
VSSR
R3
R2
VDDR
Q1
VDDPLL
R1
Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
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V
C6
VSSA
VSSX
C3
VDDA
VDD1
VSS1
C1
VSSR
R3
R2
VDDR
Q1
VDDPLL
R1
Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
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VDDX
C
C3
VSSA
VSSX
VDDA
VDD1
C1
VSS2
C2
VSS1
VDD2
VSSPLL
VSSR
R3
VDDR
R2
Q1
VDDPLL
R1
Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
Section 9 Clock Reset Generator (CRG) Block Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
9.1 Device-specific information
The CRG is part of the IPBus domain.
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The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block User Guide for voltage level specifications.
9.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 10 Oscillator (OSC) Block Description
Consult the OSC Block User Guide for information about the Oscillator module.
Section 11 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module.
Section 12 Analog to Digital Converter (ATD) Block
Description
12.1 Device-specific information
12.1.1 VRL (voltage reference low)
In the 48 and 52 pin package versions, the VRL pad is bonded internally to the VSSA pin.
Consult the ATD_10B8C Block User Guide for further information about the A/D Converter module.
Section 13 Serial Communications Interface (SCI) Block
Description
Consult the SCI Block User Guide for information about the Asynchronous Serial Communications
Interface module.
Section 14 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
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Consult the SPI Block User Guide for information about the Synchronous Serial Communications
Interface module.
Section 15 Flash Block Description
Consult the FTS16K Block User Guide for information about the Flash module for the MC9S12GC16.
Consult the FTS32K Block User Guide for information about the Flash module for the MC9S12C32 or
MC9S12GC32.
Consult the FTS64K Block User Guide for information about the Flash module for the MC9S12C64 or
MC9S12GC64.
Consult the FTS96K Block User Guide for information about the Flash module for the MC9S12C96.
Consult the FTS128K Block User Guide for information about the Flash module for the MC9S12C128or
MC9S12GC128.
Section 16 RAM Block Description
This module supports single-cycle misaligned word accesses without wait states.
The MC912GC16 features a single 1K byte RAM module.
The MC9S12C32 and MC9S12GC32 feature a 2K byte RAM module.
The MC9S12C64, MC9S12GC64, MC9S12C96, MC9S12C128 and MC9S12GC128 versions feature a
4K byte RAM module.
Section 17 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator Module.
Section 18 MSCAN Block Description
Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.
This module is not available on the MC9GC-Family Members.
Section 19 Port Integration Module (PIM) Block Description
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Consult the PIM_9C32 Block User Guide for information about the Port Integration Module for all
versions of the MC9DS12GC and MC9S12C-Family.
The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of
PortP pins for the low pin count packages. For the 80QFP package option it is recommended not to use
MODRR since this is intended to support PWM channel availability in low pin count packages. Note that
when mapping PWM channels to PortT in an 80QFP option, the associated PWM channels are then
mapped to both PortP and PortT.
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
NOTE:
The parts are specified and tested over the 5V and 3.3V ranges. For the
intermediate range, generally the electrical specifications for the 3.3V range
apply, but the parts are not tested in production test in the intermediate range.
This supplement contains the most accurate electrical information for the MC9S12C-Family
microcontrollers available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification will be added at a later release of the specification
P: Those parameters are guaranteed during production testing on each individual device.
C: Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T: Those parameters are achieved by design characterization on a small sample size from typical devices.
All values shown in the typical column are within this category.
D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12C-Family and MC9S12GC-Family members utilize several pins to supply power to the I/O
ports, A/D converter, oscillator and PLL as well as the internal logic.
The VDDA, VSSA pair supplies the A/D converter.
The VDDX, VSSX pair supplies the I/O pins
The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.
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VSS1 and VSS2 are internally connected by metal.
VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some
of the functionality may be disabled. E.g. pull-up and pull-down resistors may be disabled permanently.
A.1.3.2 Analog Reference
This class is made up by the two VRH and VRL pins. In 48 and 52 pin package versions the VRL pad is
bonded to the VSSA pin.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
or V range during instantaneous and
DD
DD5
operating maximum current conditions. If positive injection current (V > V
) is greater than I
, the
in
DD5
DD5
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
or V
).
SS5
DD5
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
6.5
3.0
3.0
0.3
0.3
6.5
6.5
3.0
10.0
Unit
V
VDD5
1
2
3
4
5
6
7
8
9
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage1
VDD
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage difference VDDX to VDDR and VDDA
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
V
VDDX
∆
V
VSSX
VIN
VRH, VRL
VILV
V
Analog Reference
V
XFC, EXTAL, XTAL inputs
TEST input
V
VTEST
V
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 2
ID
10
11
12
-25
-25
+25
+25
0
mA
mA
mA
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL3
IDL
Instantaneous Maximum Current
Single pin limit for TEST4
IDT
TA
-0.25
13
14
Operating Temperature Range (packaged)
Operating Temperature Range (junction)
Storage Temperature Range
– 40
– 40
– 65
125
140
155
°C
°C
°C
TJ
Tstg
15
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA
.
3. These pins are internally clamped to VSSPLL and VDDPLL
4. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ohm
pF
Series Resistance
R1
C
Storage Capacitance
Human Body
Number of Pulse per pin
positive
negative
-
3
3
-
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
negative
-
3
3
-
Minimum input voltage limit
Maximum input voltage limit
-2.5
7.5
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
C
Rating
Symbol
VHBM
Min
2000
200
Max
Unit
V
1
2
3
C
C
C
Human Body Model (HBM)
Machine Model (MM)
-
-
-
VMM
V
VCDM
Charge Device Model (CDM)
500
V
Latch-up Current at 125°C
positive
negative
ILAT
4
5
C
C
+100
-100
-
-
mA
mA
Latch-up Current at 27°C
positive
negative
ILAT
+200
-200
A.1.7 Operating Conditions
This chapter describes the operating conditions of the devices. Unless otherwise noted those conditions
apply to all the following data.
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NOTE: Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
to Section A.1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
2.97
2.35
2.35
-0.1
-0.1
0.5
Typ
5
Max
5.5
Unit
V
VDD5
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage1
VDD
2.5
2.5
0
2.75
2.75
0.1
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage Difference VDDX to VDDA
Voltage Difference VSSX to VSSR and VSSA
Oscillator
V
VDDX
∆
0
0.1
V
VSSX
fosc
-
16
MHz
2
Bus Frequency
0.25
-40
-
-
25
MHz
fbus
TJ
Operating Junction Temperature Range
140
°C
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper oper-
ation.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T ) in °C can be
J
obtained from:
T = T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
P
= Ambient Temperature, [°C]
A
D
= Total Chip Power Dissipation, [W]
Θ
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
= P
P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
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Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P
= I
V
+ I
V
+ I
V
INT
DD DD DDPLL DDPLL DDA DDA
2
P
=
R
I
∑
IO
DSON IO
i
i
Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
For R is valid:
DSON
V
OL
R
= ----------- ;for outputs driven low
DSON
I
OL
respectively
V
– V
DD5
OH
R
= ----------------------------------- ;for outputs driven high
DSON
I
OH
2. Internal voltage regulator enabled
= I
P
V
+ I
V
INT
DDR DDR DDA DDA
I
is the current shown in Table A-8 and not the overall current flowing into VDDR, which
DDR
additionally contains the current flowing into the external loads with output high.
2
P
=
R
I
∑
IO
DSON IO
i
i
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Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
1
Table A-5 Thermal Package Characteristics
Num
C
Rating
Symbol
Min
Typ
Max
Unit
Thermal Resistance LQFP48, single layer PCB2
oC/W
θJA
1
T
-
-
69
Thermal Resistance LQFP48, double sided PCB with
2 internal planes3
oC/W
θJA
2
T
-
-
53
oC/W
oC/W
oC/W
oC/W
θJB
θJC
ΨJT
θJA
3
4
5
6
T
T
T
T
Junction to Board LQFP48
30
20
4
Junction to Case LQFP48
Junction to Package Top LQFP48
Thermal Resistance LQFP52, single sided PCB
-
-
-
-
65
Thermal Resistance LQFP52, double sided PCB with
2 internal planes
oC/W
θJA
7
T
49
oC/W
oC/W
oC/W
oC/W
θJB
θJC
ΨJT
θJA
8
9
T
T
T
T
Junction to Board LQFP52
31
17
3
Junction to Case LQFP52
10
11
Junction to Package Top LQFP52
Thermal Resistance QFP 80, single sided PCB
-
-
-
-
52
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
oC/W
θJA
12
T
42
oC/W
oC/W
oC/W
θJB
θJC
ΨJT
13
14
T
T
T
Junction to Board QFP80
Junction to Case QFP80
28
18
4
15
Junction to Package Top QFP80
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not
all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, unless otherwise noted
Num
C
P
T
Rating
Symbol
Min
Typ
Max
-
Unit
V
VIH
0.65*VDD5
1
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Input Hysteresis
-
VIH
VIL
-
-
VDD5 + 0.3
0.35*VDD5
V
2
P
T
-
-
-
V
VIL
VSS5 - 0.3
-
V
VHYS
3
4
C
250
mV
Input Leakage Current (pins in high ohmic input
mode)1
Vin = VDD5 or VSS5
Iin
P
C
–1
-
-
1
-
µA
Output High Voltage (pins in output mode)
VOH
VDD5 – 0.8
5
V
Partial Drive I
OH
= –2mA
Output High Voltage (pins in output mode)
Full Drive IOH = –10mA
VOH
VOL
VOL
VDD5 – 0.8
6
7
P
C
-
-
-
V
V
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
-
-
0.8
Output Low Voltage (pins in output mode)
8
9
P
P
C
P
-
-
-
-
0.8
-130
-
V
Full Drive I
= +10mA
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
-
-10
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
10
11
Internal Pull Down Device Current,
tested at VIH Min.
130
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
12
13
C
D
10
-
-
-
µA
Input Capacitance
7
pF
Injection current2
Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
14
T
-2.5
-25
-
2.5
25
mA
Port P, J Interrupt Input Pulse filtered3
Port P, J Interrupt Input Pulse passed3
tPIGN
tPVAL
15
P
P
3
µs
µs
16
10
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 3.3V I/O Characteristics
Conditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, unless otherwise noted
Num
C
P
T
Rating
Symbol
Min
Typ
Max
-
Unit
V
VIH
0.65*VDD5
1
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Input Hysteresis
-
VIH
VIL
-
-
VDD5 + 0.3
0.35*VDD5
V
2
P
T
-
-
-
V
VIL
VSS5 - 0.3
-
V
VHYS
3
4
C
250
mV
Input Leakage Current (pins in high ohmic input
mode)1
Iin
P
–1
-
1
µA
Vin = VDD5 or VSS5
Output High Voltage (pins in output mode)
VOH
VOH
VOL
VOL
IPUL
IPUH
IPDH
VDD5 – 0.4
5
6
C
P
C
P
P
C
P
-
-
-
-
-
-
-
-
V
V
Partial Drive I
OH
= –0.75mA
Output High Voltage (pins in output mode)
Full Drive I = –4mA
VDD5 – 0.4
-
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +0.9mA
7
-
-
0.4
0.4
–60
-
V
OL
Output Low Voltage (pins in output mode)
Full Drive I = +4.75mA
8
V
OL
Internal Pull Up Device Current,
tested at VIL Max.
9
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
10
11
-6
-
Internal Pull Down Device Current,
tested at VIH Min.
60
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
12
11
C
D
6
-
-
-
µA
Input Capacitance
7
pF
Injection current2
Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
12
T
-2.5
-25
-
2.5
25
mA
Port P, J Interrupt Input Pulse filtered3
Port P, J Interrupt Input Pulse passed3
tPIGN
tPVAL
13
P
P
3
µs
µs
14
10
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
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Table A-8 Supply Current Characteristics for MC9S12C32
Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted
Num
C
Rating
Run Supply Current Single Chip
Wait Supply current
Symbol
Min
Typ
Max
Unit
IDD5
1
P
35
mA
All modules enabled
VDDR<4.9V, only RTI enabled(2)
VDDR>4.9V, only RTI enabled
P
P
C
30
8
IDDW
2
mA
3.5
2.5
Pseudo Stop Current (RTI and COP disabled)(2)(3)
C
P
C
P
C
P
C
P
340
360
500
550
590
720
780
1100
-40°C
27°C
85°C
450
1
3
1450
1900
4500
µA
IDDPS
"C" Temp Option 100˚C
105°C
"V" Temp Option 120˚C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP enabled)2 3
C
C
C
C
C
540
700
750
880
1300
-40°C
27°C
85°C
105°C
125°C
1
4
µA
IDDPS
Stop Current (3)
C
P
C
P
C
P
C
P
10
20
-40°C
27°C
85°C
80
100
140
170
300
350
520
(1)
5
1000
1400
4000
µA
IDDS
"C" Temp Option 100˚C
105°C
"V" Temp Option 120˚C
125°C
"M" Temp Option 140°C
NOTES:
1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is
carried out at 100˚C although the Temperature specification is 85˚C. Similarly for "v" and "M" options the temperature
used in test lies 15˚C above the temperature option specification.
2. PLL off
3. At those low power dissipation levels TJ = TA can be assumed
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Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128
Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted
Num
C
Rating
Run Supply Current Single Chip,
Wait Supply current
Symbol
Min
Typ
Max
Unit
IDD5
1
P
45
mA
All modules enabled
VDDR<4.9V, only RTI enabled(2)
VDDR>4.9V, only RTI enabled
P
P
C
33
8
IDDW
2
6
mA
2.5
3.5
Pseudo Stop Current (RTI and COP disabled)(2)(3)
C
P
C
P
C
P
C
P
190
200
300
400
450
600
650
1000
-40°C
27°C
85°C
250
1
IDDPS
1400
1900
4800
µA
"C" Temp Option 100˚C
105°C
"V" Temp Option 120˚C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP enabled)2 3
C
C
C
C
C
370
500
590
780
1200
-40°C
27°C
85°C
105°C
125°C
1
4
µA
IDDPS
Stop Current (3)
C
P
C
P
C
P
C
P
12
25
-40°C
27°C
85°C
100
130
160
200
350
400
600
(1)
5
1200
1700
4500
µA
IDDS
"C" Temp Option 100˚C
105°C
"V" Temp Option 120˚C
125°C
"M" Temp Option 140°C
NOTES:
1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is
carried out at 100˚C although the Temperature specification is 85˚C. Similarly for "v" and "M" options the temperature
used in test lies 15˚C above the temperature option specification.
2. PLL off
3. At those low power dissipation levels TJ = TA can be assumed
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Appendix B Electrical Specifications
B.1 Voltage Regulator Operating Conditions
Table B-1 Voltage Regulator Electrical Parameters
Nu
m
C
Characteristic
Symbol
Min
Typical
Max
Unit
VVDDR, A
1
P
Input Voltages
2.97
—
5.5
V
Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
2
3
C
P
—
—
20
12
50
40
µA
µA
Output Voltage Core
Full Performance Mode
VDD
2.35
2.5
2.75
V
Low Voltage Interrupt1
Assert Level C32, GC32
Assert Level C64, C96,C128
GC64, GC128
Deassert Level C32, GC32
Deassert Level C64, C96, C128
GC64, GC128
VLVIA
VLVIA
VLVID
VLVID
4.30
4.10
4.42
4.25
4.53
4.37
4.65
4.52
4.77
4.66
4.89
4.77
V
V
V
V
4
P
P
Low Voltage Reset2
Assert Level C32, GC32
Assert Level C64, C96, C128
GC64, GC128
5
6
2.25
2.25
2.3
2.35
VLVRA
—
V
V
Low Voltage Reset(2)
Deassert Level
P
C
—
—
VLVRD
2.55
Power-on Reset3
Assert Level
Deassert Level
VPORA
VPORD
7
0.97
—
—
—
—
2.05
V
V
NOTES:
1. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply
voltage.
2. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure B-1)
3. Monitors VDD. Active in all modes.
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values in this section cannot be guaranteed by Motorola and
are subject to change without notice.
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B.2 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1.
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
V
VDDA
VLVID
VLVIA
VDD
VLVRD
VLVRA
VPORD
t
LVI
LVI enabled
LVI disabled due to LVR
POR
LVR
B.3 Output Loads
B.3.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.
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B.3.2 Capacitive Loads
The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required.
Table B-2 Voltage Regulator - Capacitive Loads
Num
Characteristic
VDD external capacitive load
VDDPLL external capacitive load
Symbol
CDDext
Min
400
90
Typical
440
Max
12000
5000
Unit
nF
1
2
CDDPLLext
220
nF
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B.4 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is
bonded to the VSSA pin.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the
ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.4.1 ATD Operating Characteristics In 5V Range
The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-3 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
Num
C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1
D
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA/2
VDDA
V
V
Differential Reference Voltage1
ATD Clock Frequency
2
3
C
D
VRH-VRL
4.75
0.5
5.0
5.25
2.0
V
f
MHz
ATDCLK
ATD 10-Bit Conversion Period
Clock Cycles2
4
5
D
D
N
T
14
7
28
14
Cycles
µs
CONV10
CONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles2
N
T
12
6
26
13
Cycles
µs
CONV10
CONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK
Recovery Time (VDDA=5.0 Volts)
Reference Supply current
5
D
P
t
20
µs
REC
6
I
0.375
mA
REF
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
B.4.2 ATD Operating Characteristics In 3.3V Range
The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
≤ V ≤ V ≤ V ≤ V
. This constraint exists since the sample buffer amplifier can not drive
SSA
RL
IN
RH
DDA
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beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped
Table B-4 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Rating
Symbol
Min
Typ
Max
/2
Unit
Reference Potential
1
D
Low
High
V
V
V
V
V
RL
SSA
DDA
V
V
/2
V
RH
DDA
DDA
2
3
C Differential Reference Voltage
D ATD Clock Frequency
V
-V
3.0
3.3
3.6
2.0
V
RH RL
f
0.5
MHz
ATDCLK
ATD 10-Bit Conversion Period
D
Clock Cycles1
4
5
N
T
14
7
28
14
Cycles
µs
CONV10
CONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles(1)
D
N
T
12
6
26
13
Cycles
µs
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
Recovery Time (VDDA=3.3 Volts)
6
7
D
P
t
20
µs
REC
Reference Supply current
I
0.250
mA
REF
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
B.4.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influenceon the
accuracy of the ATD.
B.4.3.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
S
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowable.
B.4.3.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C ≥ 1024 * (C - C ).
f
INS
INN
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B.4.3.3 Current injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
= K * R *
ERR
S
I
, with I being the sum of the currents injected into the two pins adjacent to the converted
INJ
INJ
channel.
Table B-5 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
RS
1
C
Max input Source Resistance
-
-
1
KΩ
Total Input Capacitance
Non Sampling
Sampling
CINN
CINS
2
T
10
15
pF
INA
Kp
Kn
3
4
5
C
C
C
Disruptive Analog Input Current
-2.5
2.5
10-4
10-2
mA
A/A
A/A
Coupling Ratio positive current injection
Coupling Ratio negative current injection
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B.4.4 ATD accuracy (5V Range)
Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table B-6 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
f
= 2.0MHz
ATDCLK
Num
C
Rating
Symbol
LSB
DNL
INL
Min
Typ
Max
Unit
mV
1
P
P
P
P
P
P
P
P
10-Bit Resolution
5
2
10-Bit Differential Nonlinearity
10-Bit Integral Nonlinearity
–1
–2
1
2
Counts
Counts
Counts
mV
3
10-Bit Absolute Error1
8-Bit Resolution
4
AE
-2.5
2.5
5
LSB
DNL
INL
20
6
8-Bit Differential Nonlinearity
8-Bit Integral Nonlinearity
–0.5
–1.0
-1.5
0.5
1.0
1.5
Counts
Counts
Counts
7
±0.5
±1
8-Bit Absolute Error(1)
8
AE
NOTES:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.
B.4.5 ATD accuracy (3.3V Range)
Table B-6 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table B-7 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
f
= 2.0MHz
ATDCLK
Num
C
Rating
Symbol
LSB
DNL
INL
Min
Typ
Max
Unit
mV
1
P
P
P
P
P
P
P
P
10-Bit Resolution
3.25
2
10-Bit Differential Nonlinearity
10-Bit Integral Nonlinearity
–1.5
–3.5
-5
1.5
3.5
5
Counts
Counts
Counts
mV
3
±1.5
±2.5
13
10-Bit Absolute Error1
8-Bit Resolution
4
AE
5
LSB
DNL
INL
6
8-Bit Differential Nonlinearity
8-Bit Integral Nonlinearity
–0.5
–1.5
-2.0
0.5
1.5
2.0
Counts
Counts
Counts
7
±1
8-Bit Absolute Error(1)
8
AE
±1.5
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
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For the following definitions see also Figure B-2.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
n
0
-------------------
1LSB
INL(n) =
DNL(i) =
– n
∑
i = 1
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DNL
10-Bit Absolute Error Boundary
LSB
V
V
i
i-1
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
3.25 6.5 9.75 13 16.25 19.5 22.75 26 29.25
3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Vin
mV
Figure B-2 ATD Accuracy Definitions
NOTE: Figure B-2 shows only definitions, for specification values refer to Table B-6.
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B.5 NVM, Flash and EEPROM
B.5.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f is required for performing program or erase operations. The NVM modules
NVMOSC
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash program and erase operations are timed using a clock derived from the oscillator using the
FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits
specified as f
.
NVMOP
The minimum program and erase times shown in Table B-8 are calculated for maximum f
and
NVMOP
maximum f . The maximum times are calculated for minimum f
and a f of 2MHz.
bus
NVMOP
bus
B.5.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f¨ and can be calculated according to the following formula.
NVMOP
1
1
t
= 9
+ 25
---------------------
----------
swpgm
f
f
NVMOP
bus
B.5.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t
= 4
+ 9
---------------------
----------
bwpgm
f
f
NVMOP
bus
The time to program a whole row is:
t
= t
+ 31 t
brpgm
swpgm
bwpgm
Burst programming is more than 2 times faster than single word programming.
B.5.1.3 Sector Erase
Erasing a 512 byte Flash sector takes:
1
t
≈ 4000
---------------------
era
f
NVMOP
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The setup times can be ignored for this operation.
B.5.1.4 Mass Erase
Erasing a NVM block takes:
1
t
≈ 20000
---------------------
mass
The setup times can be ignored for this operation.
f
NVMOP
Table B-8 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
D
D
D
P
D
D
P
P
D
Rating
Symbol
fNVMOSC
fNVMBUS
fNVMOP
tswpgm
Min
0.5
1
Typ
Max
Unit
MHz
MHz
kHz
µs
501
1
External Oscillator Clock
2
Bus frequency for Programming or Erase Operations
Operating Frequency
3
150
200
74.53
313
462
20.42
678.42
204
4
Single Word Programming Time
Flash Burst Programming consecutive word
Flash Burst Programming Time for 32 Words
Sector Erase Time
tbwpgm
tbrpgm
tera
5
µs
1035.53
26.73
1333
6
µs
7
ms
1004
115
tmass
t check
8
Mass Erase Time
ms
327786
tcyc
9
Blank Check Time Flash per block
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequen-
cy fbus
.
3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus
. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP
5. Minimum time, if first word in the array is not blank
.
6. Maximum time to complete check on an erased block.
B.5.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime
at the operating conditions noted.
A program/erase cycle is specified as two transitions of the cell value from erased → programmed →
erased, 1 → 0 → 1.
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NOTE: All values shown in Table B-9 are target values and subject to further extensive
characterization.
Table B-9 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
C
C
Rating
Symbol
tNVMRET
nFLPE
Min
15
Typ Max Unit
Years
Data Retention at an average junction temperature of
1
2
TJavg = 85°C
Flash number of Program/Erase cycles
10,000
Cycles
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B.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
B.6.1 Startup
Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table B-10 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
T
Rating
Symbol
VPORR
VPORA
PWRSTL
nRST
Min
Typ
Max
Unit
V
1
2
3
4
POR release level
POR assert level
2.07
T
0.97
2
V
tosc
nosc
D
D
Reset input pulse width, minimum input time
Startup from Reset
192
196
14
Interrupt pulse width, IRQ edge-sensitive
mode
PWIRQ
tWRS
5
6
D
D
20
ns
tcyc
Wait recovery startup time
B.6.1.1 POR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
DD
PORR
PORA
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
B.6.1.2 LVR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
LVRR
LVRA DD
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
B.6.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
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B.6.1.4 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
B.6.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
B.6.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts
wrs
fetching the interrupt vector.
B.6.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
specifies the maximum time before switching to the internal self clock mode in
CQOUT
case no proper oscillation is detected. The quality monitor also determines the minimum oscillator start-up
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time t
. The device features a clock monitor. A time-out is asserted if the frequency of the incoming
UPOSC
clock signal is below the Clock Monitor FailureAssert Frequency f
CMFA.
Table B-11 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1a
1b
2
C
C
C
P
C
D
P
P
D
D
D
D
D
Rating
Symbol
Min
0.5
Typ
Max
16
Unit
MHz
MHz
µA
fOSC
Crystal oscillator range (Colpitts)
Crystal oscillator range (Pierce) 1(4)
Startup Current
fOSC
iOSC
0.5
40
100
82
1003
2.5
tUPOSC
tCQOUT
fCMFA
fEXT
3
Oscillator start-up time (Colpitts)
Clock Quality check time-out
Clock Monitor Failure Assert Frequency
ms
s
4
0.45
50
5
100
200
50
KHz
MHz
ns
External square wave input frequency 4
External square wave pulse width low
External square wave pulse width high
External square wave rise time
6
0.5
9.5
9.5
tEXTL
tEXTH
tEXTR
tEXTF
CIN
7
8
ns
9
1
1
ns
10
11
External square wave fall time
ns
Input Capacitance (EXTAL, XTAL pins)
7
pF
DC Operating Bias in Colpitts Configuration
on EXTAL Pin
VDCBIAS
12
C
1.1
V
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset
B.6.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
B.6.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
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C
p
VDDPLL
R
C
XFC Pin
s
Phase
VCO
f
f
vco
f
1
ref
osc
∆
K
K
Φ
V
refdv+1
Detector
f
cmp
Loop Divider
1
1
2
synr+1
Figure B-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table B-12.
1
1
ch
The grey boxes show the calculation for f
= 50MHz and f = 1MHz. E.g., these frequencies are used
ref
VCO
for f
= 4MHz and a 25MHz bus clock.
OSC
The VCO Gain at the desired VCO frequency is approximated by:
(f1 – fvco
-----------------------
K1 1V
)
(60 – 50)
-----------------------
–100
K = K e
= -90.48MHz/V
= –100 e
V
1
The phase detector relationship is given by:
K = – i
K
= 316.7Hz/Ω
Φ
ch
V
i is the current in tracking mode.
ch
The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ζ f
f
ref
1
ref
f < ------------------------------------------
→ f < ------------- ;(ζ = 0.9)
------
10
C
C
4 10
fC < 25kHz
2
π ζ + 1 + ζ
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And finally the frequency relationship is defined as
f
VCO
n = ------------- = 2 (synr + 1)
= 50
f
ref
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f =10kHz:
C
2 π n f
C
= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
R = ----------------------------
K
Φ
The capacitance C can now be calculated as:
s
2
0.516
≈ --------------;(ζ = 0.9)
2 ζ
= 5.19nF =~ 4.7nF
C =
---------------------
π f
s
f
R
R
C
C
The capacitance C should be chosen in the range of:
p
C ⁄ 20 ≤ C ≤ C ⁄ 10
Cp = 470pF
s
p
s
B.6.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.
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1
2
3
N-1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure B-4 Jitter Definitions
is at its maximum for one clock period, and decreases towards zero for larger
The relative deviation of t
nom
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
max
min
J(N) = max 1 –
, 1 –
--------------------
---------------------
N t
N t
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J(N) =
+ j
-------
2
N
J(N)
1
5
10
20
N
Figure B-5 Maximum bus clock jitter approximation
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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table B-12 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fSCM
Min
1
Typ
Max
5.5
Unit
MHz
MHz
1
2
P Self Clock Mode frequency
D VCO locking range
fVCO
8
50
Lock Detector transition from Acquisition to Tracking
mode
1
|∆trk
|∆Lock
|∆unl
|∆unt
|
3
D
3
4
%
(1)
|
4
5
D Lock Detection
0
1.5
2.5
%
(1)
|
D Un-Lock Detection
0.5
%
Lock Detector transition from Tracking to Acquisition
mode
(1)
|
6
D
6
8
%
PLLON Total Stabilization delay (Auto Mode) 2
C
tstab
tacq
tal
7
8
9
0.5
0.3
ms
ms
PLLON Acquisition mode stabilization delay (2)
D
PLLON Tracking mode stabilization delay (2)
D
0.2
ms
K1
f1
10 D Fitting parameter VCO loop gain
11 D Fitting parameter VCO loop frequency
12 D Charge pump current acquisition mode
13 D Charge pump current tracking mode
-100
60
MHz/V
MHz
µA
| ich
| ich
j1
|
38.5
3.5
|
µA
Jitter fit parameter 1(2)
Jitter fit parameter 2(2)
14
15
C
C
1.1
%
j2
0.13
%
NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.
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B.7 MSCAN
Table B-13 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
tWUP
Min
Typ
Max
1
2
P MSCAN Wake-up dominant pulse filtered
P MSCAN Wake-up dominant pulse pass
2
tWUP
5
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B.8 SPI
Appendix C Electrical Specifications
This section provides electrical parametrics and ratings for the SPI.
In Table C-1 the measurement conditions are listed.
Table C-1 Measurement Conditions
Description
Value
Unit
Drive mode
full drive mode
—
Load capacitance CLOAD,
on all outputs
50
pF
V
Thresholds for delay
measurement points
(20% / 80%) VDDX
C.1 Master Mode
In Figure C-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.
1
SS
(OUTPUT)
2
1
12
12
13
13
3
SCK
0)
4
(CPOL
=
(OUTPUT)
4
SCK
= 1)
(CPOL
(OUTPUT)
5
6
MISO
(INPUT)
2
BIT 6 . . . 1
MSB IN
LSB IN
10
9
11
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure C-1 SPI Master Timing (CPHA=0)
In Figure C-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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1
SS
(OUTPUT)
1
12
12
13
13
3
2
SCK
(CPOL
= 0)
(OUTPUT)
4
4
SCK
= 1)
(CPOL
(OUTPUT)
5
6
MISO
2
MSB IN
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
(INPUT)
9
MOSI
(OUTPUT)
2
PORT DATA
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure C-2 SPI Master Timing (CPHA=1)
In Table C-2 the timing characteristics for master mode are listed.
Table C-2 SPI Master Mode Timing Characteristics
Num
C
Characteristic
Symbol
Unit
Min
1/2048
2
Typ
—
Max
fsck
tsck
tlead
tlag
twsck
tsu
fbus
tbus
tsck
tsck
tsck
ns
1
1
P
P
D
D
D
D
D
D
D
D
D
D
SCK Frequency
1/2
2048
—
SCK Period
—
2
Enable Lead Time
—
1/2
1/2
1/2
—
3
Enable Lag Time
—
—
4
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
—
5
8
—
thi
6
8
—
—
ns
tvsck
tvss
tho
9
—
—
30
15
—
ns
10
11
12
13
—
—
ns
20
—
—
ns
trfi
—
8
ns
trfo
—
—
8
ns
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C.2 Slave Mode
In Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
1
12
12
13
13
3
SCK
0)
(CPOL
=
(INPUT)
4
4
2
SCK
(CPOL
= 1)
10
7
(INPUT)
8
9
11
11
MISO
(OUTPUT)
see
note
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
6
NOTE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure C-3 SPI Slave Timing (CPHA=0)
In Figure C-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
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SS
(INPUT)
3
1
12
13
13
2
SCK
(CPOL
= 0)
(INPUT)
4
4
12
11
SCK
= 1)
(INPUT)
(CPOL
8
9
MISO
see
BIT 6 . . . 1
SLAVE
5
MSB OUT
6
SLAVE LSB OUT
LSB IN
note
(OUTPUT)
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
Figure C-4 SPI Slave Timing (CPHA=1)
In Table C-3 the timing characteristics for slave mode are listed.
Table C-3 SPI Slave Mode Timing Characteristics
Num
C
Characteristic
Symbol
Unit
Min
DC
4
Typ
—
Max
1/4
∞
fsck
tsck
tlead
tlag
fbus
tbus
tbus
tbus
tbus
ns
1
1
2
3
4
5
6
D
P
D
D
D
D
D
SCK Frequency
SCK Period
—
Enable Lead Time
4
—
—
Enable Lag Time
4
—
—
twsck
tsu
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
4
—
—
8
—
—
thi
8
—
—
ns
Slave Access Time (time to data
active)
ta
7
D
—
—
20
22
ns
tdis
8
9
D
D
Slave MISO Disable Time
Data Valid after SCK Edge
—
—
—
—
ns
ns
1
1
tvsck
30 + tbus
tvss
tho
trfi
10
11
D
D
D
D
Data Valid after SS fall
—
20
—
—
—
—
—
—
ns
ns
ns
ns
30 + tbus
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
8
12
trfo
13
8
NOTES:
1. tbus added due to internal synchronization delay
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C.3 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with the actual timing
values shown on table Table C-4. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
C.3.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
Figure C-5 General External Bus Timing
1, 2
3
4
ECLK
PE4
5
6
16
10
9
15
11
Addr/Data
(read)
PA, PB
data
data
data
addr
7
8
12
14
data
13
Addr/Data
(write)
PA, PB
addr
17
20
19
22
25
18
21
R/W
PE2
LSTRB
PE3
24
27
23
26
NOACC
PE7
28
29
PIPO0
PIPO1, PE6,5
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Table C-4 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
D
D
Rating
Frequency of operation (E-clock)
Cycle time
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
25.0
tcyc
2
40
19
19
PWEL
3
Pulse width, E low
ns
Pulse width, E high1
PWEH
tAD
4
ns
5
Address delay time
8
ns
Address valid time to E rise (PWEL–tAD
)
tAV
6
11
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
7
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
ns
8
7
ns
9
2
ns
10
11
12
13
13
0
ns
ns
7
ns
2
12
19
6
ns
Write data setup time(1) (PWEH–tDDW
Address access time(1) (tcyc–tAD–tDSR
)
14
15
D
D
ns
ns
tACCA
)
E high access time(1) (PWEH–tDSR
Read/write delay time
)
tACCE
tRWD
tRWV
tRWH
tLSD
tLSV
16
17
18
19
20
21
22
23
24
25
26
27
28
D
D
D
D
D
D
D
D
D
D
D
D
D
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
Read/write valid time to E rise (PWEL–tRWD
Read/write hold time
)
14
2
Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
)
14
2
tLSH
tNOD
tNOV
tNOH
tP0D
tP0V
Low strobe hold time
NOACC strobe delay time
NOACC valid time to E rise (PWEL–tLSD
NOACC hold time
)
14
2
IPIPO[1:0] delay time
2
7
IPIPO[1:0] valid time to E rise (PWEL–tP0D
)
11
2
IPIPO[1:0] delay time(1) (PWEH-tP1V
)
tP1D
tP1V
25
29
IPIPO[1:0] valid time to E fall
11
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Table C-5 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF
Num
1
C
D
D
D
D
D
D
D
D
D
D
D
D
D
Rating
Frequency of operation (E-clock)
Cycle time
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
16.0
tcyc
2
62.5
30
PWEL
3
Pulse width, E low
ns
Pulse width, E high1
PWEH
tAD
4
30
ns
5
Address delay time
16
ns
Address valid time to E rise (PWEL–tAD
)
tAV
6
16
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
7
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
ns
8
7
ns
9
2
ns
10
11
12
13
15
0
ns
ns
15
ns
2
ns
Write data setup time(1) (PWEH–tDDW
Address access time(1)
)
14
15
16
D
D
15
29
15
ns
ns
tACCA
E high access time(1) (PWEH–tDSR
Read/write delay time
)
tACCE
tRWD
tRWV
tRWH
tLSD
tLSV
D
D
D
D
D
D
D
D
D
D
D
D
D
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
18
14
14
14
Read/write valid time to E rise (PWEL–tRWD
)
16
2
19
Read/write hold time
20
Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
Low strobe hold time
)
21
16
2
tLSH
tNOD
tNOV
tNOH
tP0D
tP0V
22
23
NOACC strobe delay time
NOACC valid time to E rise (PWEL–tLSD
)
24
16
2
25
NOACC hold time
26
IPIPO[1:0] delay time
2
14
25
IPIPO[1:0] valid time to E rise (PWEL–tP0D
)
27
16
2
IPIPO[1:0] delay time(1)
tP1D
tP1V
28
29
IPIPO[1:0] valid time to E fall
11
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix D Package Information
D.1 General
This section provides the physical dimensions of the MC9S12C Family and MC9S12GC Family packages
48LQFP, 52LQFP, 80QFP.
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D.2 80-pin QFP package
L
60
61
41
40
S
S
B
B
D
D
P
-A-
L
-B-
A
A
V
B
D
M
M
-A-,-B-,-D-
0
0
0
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
S
M
S
S
S
0.20
H
A-B
A-B
D
D
0.05 A-B
J
N
M
S
0.20
C
D
M
E
DETAIL C
M
S
S
0.20
C
A-B
D
SECTION B-B
VIEW ROTATED 90
C
DATUM
PLANE
-H-
°
-C-
0.10
H
SEATING
PLANE
M
G
NOTES:
MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
DIM
A
B
C
D
E
MIN
13.90
13.90
2.15
MAX
14.10
14.10
2.45
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
U
0.22
0.38
2.00
2.40
T
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
F
0.22
0.33
G
H
J
K
L
M
N
P
Q
R
S
0.65 BSC
DATUM
PLANE
---
0.13
0.65
0.25
0.23
0.95
-H-
R
12.35 REF
5
0.13
10
0.17
°
°
0.325 BSC
K
0
7
Q
°
°
W
0.13
16.95
0.13
0.30
17.45
---
X
T
DETAIL C
U
V
W
X
0
---
17.45
0.45
°
16.95
0.35
1.6 REF
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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D.3 52-pin LQFP package
4X
4X 13 TIPS
0.20 (0.008) T L-M N
0.20 (0.008)
H
L-M
N
-X-
X=L, M, N
52
40
C
1
39
L
AB
AB
G
3X VIEW Y
-L-
-M-
B1
B
V
VIEW Y
F
BASE METAL
PLATING
V1
13
27
J
U
14
26
-N-
D
A1
S1
M
S
S
0.13 (0.005)
T
L-M
N
SECTION AB-AB
A
ROTATED 90 ° CLOCKWISE
S
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: MILLIMETER
DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEADANDISCOINCIDENTWITHTHELEADWHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4X θ2
4X θ3
C
4.
5.
6.
DATUMS -L-, -M- AND -N- TO BE DETERMINED AT
DATUM PLANE -H-.
DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-
0.10 (0.004)
T
-H-
-T-
SEATING
PLANE
VIEW AA
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018).
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
S
0.05 (0.002)
MILLIMETERS
MIN MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
INCHES
MIN MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
W
2X R R1
DIM
A
A1
B
B1
C
C1
C2
D
θ1
0.25 (0.010)
C2
θ
---
0.05
1.30
0.20
0.45
0.22
1.70
---
0.067
GAGE PLANE
0.20
1.50
0.40
0.75
0.35
0.002 0.008
0.051
0.008
0.018
0.009
0.059
0.016
0.030
0.014
K
E
E
F
C1
G
0.65 BSC
0.026 BSC
J
K
0.07
0.50 REF
0.20
0.003
0.020 REF
0.008
VIEW AA
Z
R1
S
S1
U
0.08
0.20
0.003
0.008
12.00 BSC
6.00 BSC
0.09 0.16
0.472 BSC
0.236 BSC
0.004 0.006
V
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
V1
W
Z
θ
0
0
12
12
7
---
REF
REF
0
0
12
12
7
---
REF
REF
°
°
°
°
°
°
θ
θ
θ
1
2
3
°
°
°
°
Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)
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D.4 48-pin LQFP package
4X
NOTES:
0.200 AB T-U Z
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
1. CONTROLLING DIMENSION: MILLIMETER.
2. DATUM PLANE AB IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
DETAIL Y
9
A
P
A1
48
37
3. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE AC.
1
36
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
AANDBDOINCLUDEMOLDMISMATCHAND
ARE DETERMINED AT DATUM PLANE AB.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
7. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076.
8. EXACT SHAPE OF EACH CORNER IS
OPTIONAL.
T
U
B
V
AE
AE
B1
V1
12
25
MILLIMETERS
13
24
DIM MIN MAX
Z
A
A1
B
7.000 BSC
3.500 BSC
7.000 BSC
S1
T, U, Z
B1
C
D
E
F
G
H
J
K
L
M
N
P
3.500 BSC
1.400 1.600
0.170 0.270
1.350 1.450
0.170 0.230
0.500 BSC
0.050 0.150
0.090 0.200
0.500 0.700
S
DETAIL Y
4X
0.200 AC T-U Z
0
7
°
°
0.080 AC
12 REF
°
G
AB
AC
0.090 0.160
0.250 BSC
0.150 0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
R
S
S1
V
V1
W
AA
AD
°
M
BASE METAL
TOP & BOTTOM
R
N
J
E
C
H
F
D
M
0.080
AC T-U Z
SECTION AE-AE
W
°
L
K
DETAIL AD
AA
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)
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Appendix E Emulation Information
E.1 General
In order to emulate the MC9S12C and 9S12GC-Family devices, external addressing of a 128K memory
map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra
external address bus signals via PortK. This package version is for emulation only and not provided as a
general production package.
O M NE
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PW3/KWP3/PP3
PW2/KWP2/PP2
PW1/KWP1/PP1
/PW0/KWP0/PP0
NC
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
NC
PAD07/AN07
NC
PAD06/AN06
NC
PAD05/AN05
NC
PAD04/AN04
NC
PAD03/AN03
NC
PAD02/AN02
NC
PAD01/AN01
NC
PAD00/AN00
VSS2
9
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12C Family
MC9S12GC Family
IOC6/PT6
IOC7/PT7
NC
NC
NC
NC
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are available only in the 112 Pin Package. Pins marked "NC" are not connected
Figure 19-1 Pin Assignments in 112-pin LQFP
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E.1.1 PK[2:0] / XADDR[16:14]
PK2-PK0 provide the expanded address XADDR[16:14] for the external bus.
Refer to the S12 Core user guide for detailed information about external address page access.
Internal Pull
Resistor
Pin Name
Function 1
Pin Name
Power
Description
Function 2 Domain
Reset
CTRL
State
PK[2:0]
XADDR[16:14]
VDDX
PUPKE
Up
Port K I/O Pins
The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs.
The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal pullup
resistors at PortK[2:0].
In this reset state the pull-up resistors provide a defined state and prevent a floating input, thereby
preventing unneccesary current consumption at the input stage.
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E.2 112-pin LQFP package
4X
0.20
T L-M N
4X 28 TIPS
0.20
T L-M N
4X
P
J1
J1
PIN 1
112
85
IDENT
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T
L-M
N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
S
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
C2
VIEW AB
θ2
C
0.050
112X
0.10
T
SEATING
PLANE
MILLIMETERS
DIM
A
MIN
MAX
θ3
20.000 BSC
A1
B
B1
C
C1
C2
D
10.000 BSC
20.000 BSC
10.000 BSC
T
---
0.050
1.350
0.270
0.450
0.270
1.600
0.150
1.450
0.370
0.750
0.330
θ
E
F
G
0.650 BSC
J
K
P
0.090
0.500 REF
0.325 BSC
0.170
R R2
R1
R2
S
0.100
0.100
22.000 BSC
0.200
0.200
0.25
R R1
S1
V
V1
Y
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
GAGE PLANE
(K)
Z
C1
θ1
AA
θ
0.090
0.160
E
8
°
°
°
°
0
°
°
°
°
θ
θ
θ
1
2
3
3
7
(Y)
(Z)
13
13
11
11
VIEW AB
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical
Dimensions (case no. 841B)
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Device User Guide End Sheet
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