MCIMX31LCVKN5DR2 [NXP]
i.MX31 32-bit MPU, ARM1136JF-S core, 532MHz, MAPBGA 457;
| 型号： | MCIMX31LCVKN5DR2 |
| 厂家： | 
NXP |
| 描述： | i.MX31 32-bit MPU, ARM1136JF-S core, 532MHz, MAPBGA 457 |
| 文件： | 总118页 (文件大小：1416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MCIMX31_5
Rev. 4.3, 12/2009
Freescale Semiconductor
Data Sheet: Technical Data
MCIMX31 and
MCIMX31L
Package Information
Plastic Package
Case 1581 14 x 14 mm, 0.5 mm Pitch
Case 1931 19 x 19 mm, 0.8 mm Pitch
MCIMX31 and
MCIMX31L
Ordering Information
Multimedia Applications
Processors
See Table 1 on page 3 for ordering information.
Contents
1 Introduction
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering Information . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4
The MCIMX31 and MCIMX31L multimedia
applications processors represent the next step in
low-power, high-performance application processors.
Unless otherwise specified, the material in this data sheet
is applicable to both the MCIMX31 and MCIMX31L
processors and referred to singularly throughout this
document as MCIMX31. The MCIMX31L does not
include a graphics processing unit (GPU).
Functional Description and Application
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARM11 Microprocessor Core . . . . . . . . . . . . . . 4
Module Inventory. . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics . . . . . . . . . . . . . . . . 10
Chip-Level Conditions . . . . . . . . . . . . . . . . . . 10
Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . 18
Module-Level Electrical Specifications . . . . . . 20
Based on an ARM11™ microprocessor core, the
MCIMX31 provides the performance with low power
consumption required by modern digital devices.
Package Information and Pinout . . . . . . . . . 103
MAPBGA Production Package—457 14 x 14 mm,
0.5 mm Pitch . . . . . . . . . . . . . . . . . . . . . 103
MAPBGA Production Package—473 19 x 19 mm,
0.8 mm Pitch . . . . . . . . . . . . . . . . . . . . . 109
Ball Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
The MCIMX31 takes advantage of the
ARM1136JF-S™ core running at up to 532 MHz, and is
optimized for minimal power consumption using the
most advanced techniques for power saving (DPTC,
DVFS, power gating, clock gating). With 90 nm
technology and dual-Vt transistors (two threshold
voltages), the MCIMX31 provides the optimal
performance versus leakage current balance.
Product Documentation . . . . . . . . . . . . . . . . 117
Revision History . . . . . . . . . . . . . . . . . . . . . . . 117
The performance of the MCIMX31 is boosted by a
multi-level cache system, and features peripheral devices
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005–2008. All rights reserved.
Introduction
such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector
Floating Point (VFP11) co-processor, and a RISC-based SDMA controller.
The MCIMX31 supports connections to various types of external memories, such as DDR, NAND Flash,
NOR Flash, SDRAM, and SRAM. The MCIMX31 can be connected to a variety of external devices using
technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and compact flash.
1.1
Features
The MCIMX31 is designed for the high-tier, mid-tier smartphone markets, and portable media players.
They provide low-power solutions for high-performance demanding multimedia and graphics
applications.
The MCIMX31 is built around the ARM11 MCU core and implemented in the 90 nm technology.
The systems include the following features:
•
Multimedia and floating-point hardware acceleration supporting:
— MPEG-4 real-time encode of up to VGA at 30 fps
— MPEG-4 real-time video post-processing of up to VGA at 30 fps
— Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps
— Video streaming (playback) of up to VGA-30 fps, 384 kbps
®
— 3D graphics and other applications acceleration with the ARM tightly-coupled Vector
Floating Point co-processor
— On-the-fly video processing that reduces system memory load (for example, the
power-efficient viewfinder application with no involvement of either the memory system or the
ARM CPU)
•
Advanced power management
— Dynamic voltage and frequency scaling
— Multiple clock and power domains
— Independent gating of power domains
•
•
Multiple communication and expansion ports including a fast parallel interface to an external
graphic accelerator (supporting major graphic accelerator vendors)
Security
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
2
Freescale Semiconductor
Introduction
1.2
Ordering Information
Table 1 provides the ordering information for the MCIMX31.
1
Table 1. Ordering Information
Operating Temperature
2, 3, 4,5
6
Part Number
Silicon Revision
Device Mask
Package
Range (°C)
MCIMX31DVKN5D!
MCIMX31LDVKN5D!
MCIMX31CVKN5D!
MCIMX31LCVKN5D!
MCIMX31DVMN5D!
MCIMX31LDVMN5D!
2.0.1
2.0.1
2.0.1
2.0.1
2.0.1
2.0.1
M91E
M91E
M91E
M91E
M91E
M91E
–20 to 70
–20 to 70
–40 to 85
–40 to 85
–20 to 70
–20 to 70
14 x 14 mm,
0.5 mm pitch,
MAPBGA-457,
Case 1581
19 x 19 mm,
0.8 mm pitch,
Case 1931
MCIMX31CJKN5D
MCIMX31LCJKN5D
2.0.1
2.0.1
M91E
M91E
–40 to 85
–40 to 85
14 x 14 mm,
0.5 mm pitch,
MAPBGA-457,
Case 1581
1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010:
Indicated by the Icon (!)
2
3
4
Information on reading the silicon revision register can be found in the IC Identification (IIM) chapter of the Reference Manual,
see Section 6, “Product Documentation.”
Errata and fix information of the various mask sets can be found in the standard MCIMX31 Chip Errata, see Section 6, “Product
Documentation.”
Changes in output buffer characteristics can be found in the I/O Setting Exceptions and Special Pad Descriptions table in the
Reference Manual, see Section 6, “Product Documentation.”
5
6
JTAG functionality is not tested nor guaranteed at -40°C.
Case 1581 and 1931 are RoHS compliant, lead-free, MSL = 3.
1.2.1
Feature Differences Between Mask Sets
There are no silicon differences between revisions 2.0 and 2.0.1. The main difference is an updated iROM
code which supports USB-HS, SD/MMC boot modes and corrects some boot mode related erratas.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
3
Functional Description and Application Information
1.3
Block Diagram
Figure 1 shows the MCIMX31 simplified interface block diagram.
SDRAM
DDR
SRAM, PSRAM,
NOR Flash
NAND Flash,
SmartMedia
Parallel
Display (2)
Serial
LCD
Camera
Sensor (2)
Tamper
Detection
Mouse
Keyboard
AP Peripherals
AUDMUX
SSI (2)
External Memory
Interface (EMI)
MPEG-4
Video Encoder
Image Processing Unit (IPU)
Inversion and Rotation
Camera Interface
Power
Management
UART (5)
I2C (3)
FIR
Blending
IC
SDMA
Display/TV Ctl
Pre and Post Processing
CSPI (3)
PWM
Internal
Memory
Expansion
SDHC (2)
PCMCIA/CF
Mem Stick (2)
SIM
Timers
RTC
USB Host (2)
WDOG
GPT
USB-OTG
KPP
8 x 8
Keypad
ARM11TM Platform
ARM1136JF-STM
EPIT (2)
GPIO
CCM
ATA
I-Cache
Serial
EPROM
1-WIRE
®
Security
SCC
D-Cache
IIM
Debug
ECT
L2-Cache
RTIC
GPU
*
MAX
ROMPATCH
VFP
RNGA
SJC
GPS
ETM
* GPU unavailable for i.MX31L
ATA
Hard Drive
Fast
IrDA
USB
Host/Device
PC
Card
PC
Card
SD
Card
Bluetooth
Baseband
WLAN
Figure 1. MCIMX31 Simplified Interface Block Diagram
2 Functional Description and Application Information
2.1
ARM11 Microprocessor Core
The CPU of the MCIMX31 is the ARM1136JF-S core based on the ARM v6 architecture. It supports the
®
®
ARM Thumb instruction sets, features Jazelle technology (which enables direct execution of Java byte
codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The ARM1136JF-S processor core features:
™
•
•
•
•
Integer unit with integral EmbeddedICE logic
Eight-stage pipeline
Branch prediction with return stack
Low-interrupt latency
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
4
Freescale Semiconductor
Functional Description and Application Information
•
Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
•
•
•
•
•
•
Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss
Virtually indexed/physically addressed L1 caches
64-bit interface to both L1 caches
Write buffer (bypassable)
™
High-speed Advanced Micro Bus Architecture (AMBA) L2 interface
Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications
hardware acceleration
™
•
ETM and JTAG-based debug support
2.1.1
Memory System
The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the
MCIMX31 L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write (bi-directional),
and 64-bit data write interfaces.
The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for
the low-power audio playback, for security, or for other applications. There is also a 32-KB ROM for
bootstrap code and other frequently-used code and data.
A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot
by overriding the boot reset sequence by a jump to a configurable address.
Table 2 shows information about the MCIMX31 core in tabular form.
Table 2. MCIMX31 Core
Core
Acronym
Core
Name
Integrated Memory
Includes
Brief Description
ARM11 or ARM1136 The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM
• 16 Kbyte Instruction
Cache
• 16 Kbyte Data
Cache
ARM1136 Platform
real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and
a Vector Floating Processor (VFP).
The MCIMX31 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and • 128 Kbyte L2 Cache
other subsystems address the needs of the personal, wireless, and portable • 32 Kbyte ROM
product market with integrated peripherals, advanced processor core, and
power management capabilities.
• 16 Kbyte RAM
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
5
Functional Description and Application Information
2.2
Module Inventory
Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. For
extended descriptions of the modules, see the reference manual. A cross-reference is provided to the
electrical specifications and timing information for each module with external signal connections.
Table 3. Digital and Analog Modules
Block
Mnemonic
Functional
Grouping
Section/
Page
Block Name
Brief Description
1-Wire® 1-Wire Interface Connectivity The 1-Wire module provides bi-directional communication between
Peripheral the ARM11 core and external 1-Wire devices.
4.3.4/24
4.3.5/25
ATA
Advanced
Connectivity The ATA block is an AT attachment host interface. It is designed to
Technology (AT) Peripheral
Attachment
interface with IDE hard disc drives and ATAPI optical disc drives.
AUDMUX Digital Audio
Multiplexer
Multimedia
Peripheral
The AUDMUX interconnections allow multiple, simultaneous
audio/voice/data flows between the ports in point-to-point or
point-to-multipoint configurations.
4.3.6/34
CAMP
CCM
Clock Amplifier Clock
Module
The CAMP converts a square wave/sinusoidal input into a rail-to-rail
square wave. The output of CAMP feeds the predivider.
4.3.3/23
—
Clock Control
Module
Clock
The CCM provides clock, reset, and power management control for
the MCIMX31.
CSPI
Configurable
Connectivity The CSPI is equipped with data FIFOs and is a master/slave
4.3.7/34
SerialPeripheral Peripheral
Interface (x 3)
configurable serial peripheral interface module, capable of
interfacing to both SPI master and slave devices.
DPLL
ECT
EMI
Digital Phase
Lock Loop
Clock
The DPLLs produce high-frequency on-chip clocks with low
frequency and phase jitters.
Note: External clock sources provide the reference frequencies.
4.3.8/35
—
Embedded
Cross Trigger
Debug
The ECT is composed of three CTIs (Cross Trigger Interface) and
one CTM (Cross Trigger Matrix—key in the multi-core and
multi-peripheral debug strategy.
External
Memory
Interface
Memory
Interface
(EMI)
The EMI includes
• Multi-Master Memory Interface (M3IF)
• Enhanced SDRAM Controller (ESDCTL)
• NAND Flash Controller (NFC)
—
4.3.9.3/44,
4.3.9.1/36,
4.3.9.2/39
• Wireless External Interface Module (WEIM)
EPIT
Enhanced
Periodic
Interrupt Timer
Timer
Peripheral
The EPIT is a 32-bit “set and forget” timer which starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
—
ETM
FIR
Embedded
Trace Macrocell
Debug/Trace The ETM (from ARM, Ltd.) supports real-time instruction and data
tracing by way of ETM auxiliary I/O port.
4.3.10/52
Fast InfraRed
Interface
Connectivity This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 4.3.11/53
Peripheral
Mbit/s half duplex link via a LED and IR detector. It supports 0.576
Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol
and 4Mbit/s fast infrared (FIR) physical layer protocol defined by
IrDA, Rev. 1.4.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
6
Freescale Semiconductor
Functional Description and Application Information
Table 3. Digital and Analog Modules (continued)
Block
Mnemonic
Functional
Grouping
Section/
Page
Block Name
Brief Description
Fusebox Fusebox
ROM
The Fusebox is a ROM that is factory configured by Freescale.
4.3.12/53
See also
Table 11
GPIO
General
Purpose I/O
Module
Pins
The GPIO provides several groups of 32-bit bidirectional, general
purpose I/O. This peripheral provides dedicated general-purpose
signals that can be configured as either inputs or outputs.
—
GPT
GPU
General
Purpose Timer Peripheral
Timer
The GPT is a multipurpose module used to measure intervals or
generate periodic output.
—
—
Graphics Multimedia
The GPU provides hardware acceleration for 2D and 3D graphics
algorithms.
Processing Unit Peripheral
Inter IC
2
2
I C
Connectivity The I C provides serial interface for controlling the Sensor Interface 4.3.13/54
Communication Peripheral
and other external devices. Data rates of up to 100 Kbits/s are
supported.
IIM
IPU
KPP
IC Identification ID
Module
The IIM provides an interface for reading device identification.
—
Image
Multimedia
The IPU processes video and graphics functions in the MCIMX31
and interfaces to video, still image sensors, and displays.
4.3.14/55,
4.3.15/57
Processing Unit Peripheral
Keypad Port
Connectivity The KPP is used for keypad matrix scanning or as a general purpose
—
Peripheral
I/O. This peripheral simplifies the software task of scanning a keypad
matrix.
MPEG-4 MPEG-4 Video Multimedia
The MPEG-4 encoder accelerates video compression, following the
—
Encoder
Peripherals MPEG-4 standard
MSHC
PADIO
Memory Stick
Host Controller Peripheral
Connectivity The MSHC is placed in between the AIPS and the customer memory 4.3.16/82
stick to support data transfer from the MCIMX31 to the customer
memory stick.
Pads I/O
Buffers and The PADIO serves as the interface between the internal modules and
Drivers the device's external connections.
4.3.1/20
4.3.17/84
4.3.18/86
—
PCMCIA PCM
Connectivity The PCMCIA Host Adapter provides the control logic for PCMCIA
Peripheral
socket interfaces.
PWM
Pulse-Width
Modulator
Timer
Peripheral
The PWM has a 16-bit counter and is optimized to generate sound
from stored sample audio images. It can also generate tones.
RNGA
Random
Number
Generator
Accelerator
Security
The RNGA module is a digital integrated circuit capable of generating
32-bit random numbers. It is designed to comply with FIPS-140
standards for randomness and non-determinism.
RTC
Real Time Clock Timer
Peripheral
The RTC module provides a current stamp of seconds, minutes,
hours, and days. Alarm and timer functions are also available for
programming. The RTC supports dates from the year 1980 to 2050.
—
—
RTIC
Run-Time
Integrity
Security
The RTIC ensures the integrity of the peripheral memory contents
and assists with boot authentication.
Checkers
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
7
Functional Description and Application Information
Table 3. Digital and Analog Modules (continued)
Block
Mnemonic
Functional
Grouping
Section/
Page
Block Name
Brief Description
SCC
SDHC
SDMA
SIM
Security
Controller
Module
Security
The SCC is a hardware component composed of two blocks—the
Secure RAM module, and the Security Monitor. The Secure RAM
provides a way of securely storing sensitive information.
—
Secured Digital Connectivity The SDHC controls the MMC (MultiMediaCard), SD (Secure Digital) 4.3.19/87
Host Controller Peripheral
memory, and I/O cards by sending commands to cards and
performing data accesses to and from the cards.
Smart Direct
Memory Access Control
Peripheral
System
The SDMA controller maximizes the system’s performance by
relieving the ARM core of the task of bulk data transfer from memory
to memory or between memory and on-chip peripherals.
—
Subscriber
Identification
Module
Connectivity The SIM interfaces to an external Subscriber Identification Card. It is 4.3.20/88
Peripheral
an asynchronous serial interface adapted for Smart Card
communication for e-commerce applications.
SJC
Secure JTAG
Controller
Debug
The SJC provides debug and test control with maximum security and 4.3.21/92
provides a flexible architecture for future derivatives or future
multi-cores architecture.
SSI
Synchronous
Serial Interface Peripheral
Multimedia
The SSI is a full-duplex, serial port that allows the device to
communicate with a variety of serial devices, such as standard
codecs, Digital Signal Processors (DSPs), microprocessors,
peripherals, and popular industry audio codecs that implement the
inter-IC sound bus standard (I2S) and Intel AC97 standard.
4.3.22/94
UART
USB
Universal
Connectivity The UART provides serial communication capability with external
—
Asynchronous
Receiver/Trans
mitter
Peripheral
devices through an RS-232 cable or through use of external circuitry
that converts infrared signals to electrical signals (for reception) or
transforms electrical signals to signals that drive an infrared LED (for
transmission) to provide low speed IrDA compatibility.
Universal Serial Connectivity • USB Host 1 is designed to support transceiverless connection to 4.3.23/102
Bus—
2 Host
Controllers and
1 OTG
(On-The-Go)
Peripherals
the on-board peripherals in Low Speed and Full Speed mode, and
connection to the ULPI (UTMI+ Low-Pin Count) and Legacy Full
Speed transceivers.
• USB Host 2 is designed to support transceiverless connection to
the Cellular Modem Baseband Processor.
• The USB-OTG controller offers HS/FS/LS capabilities in Host
mode and HS/FS in device mode. In Host mode, the controller
supports direct connection of a FS/LS device (without external
hub). In device (bypass) mode, the OTG port functions as gateway
between the Host 1 Port and the OTG transceiver.
WDOG
Watchdog Timer Timer
Module Peripheral
The WDOG module protects against system failures by providing a
method for the system to recover from unexpected events or
programming errors.
—
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
8
Freescale Semiconductor
Signal Descriptions
3 Signal Descriptions
Signal descriptions are in the reference manual. Special signal considerations are listed following this
paragraph. The BGA ball assignment is in Section 5, “Package Information and Pinout.”
Special Signal Considerations:
•
Tamper detect (GPIO1_6)
Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect
input is asserted.
The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable
it until the next reset. The GPR[16] bit functions as the tamper detect enable bit.
GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the
tamper detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO
capabilities, such as sampling through PSR or generating interrupts.)
•
•
Power ready (GPIO1_5)
The power ready input, GPIO1_5, should be connected to an external power management IC power
ready output signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b)
a no connect, internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated
input and cannot be used as a general-purpose input/output.
SJC_MOD
SJC_MOD must be externally connected to GND for normal operation. Termination to GND
through an external pull-down resistor (such as 1 kΩ) is allowed, but the value should be much
smaller than the on-chip 100 kΩ pull-up.
•
CE_CONTROL
CE_CONTROL is a reserved input and must be externally tied to GND through a 1 kΩ resistor.
•
TTM_PAD
This is for Freescale factory use only. Control bits indicate that the pull-up/down is disabled.
However, the TTM_PAD is actually connected to an on-chip pull-down device. Users must either
float this signal or tie it to GND.
•
•
M_REQUEST and M_GRANT
These two signals are not utilized internally. The user should make no connection to these signals.
Clock Source Select (CLKSS)
The CLKSS is the input that selects the default reference clock source providing input to the DPLL.
To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization,
the reference clock source can be changed (initial setting is overwritten) by programming the
PRCS bits in the CCMR.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
9
Electrical Characteristics
4 Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the MCIMX31.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference
to the individual tables and sections.
Table 4. MCIMX31 Chip-Level Conditions
For these characteristics, …
Table 5, “Absolute Maximum Ratings”
Topic appears …
on page 10
on page 11
on page 13
on page 14
on page 14
on page 16
on page 18
Table 7, “Thermal Resistance Data—19 × 19 mm Package”
Table 8, “Operating Ranges”
Table 9, “Specific Operating Ranges for Silicon Revision 2.0.1”
Table 10, “Interface Frequency”
Section 4.1.1, “Supply Current Specifications”
Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions”
CAUTION
Stresses beyond those listed under Table 5 may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device
at these or any other conditions beyond those indicated under Table 8,
"Operating Ranges," on page 13 is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device
reliability.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Supply Voltage (Core)
Supply Voltage (I/O)
Input Voltage Range
Storage Temperature
ESD Damage Immunity:
QVCC
NVCC
–0.5
–0.5
–0.5
–40
1.65
3.3
V
V
V
max
max
V
NVCC +0.3
125
Imax
o
T
C
storage
Human Body Model (HBM)
—
—
—
—
1500
200
500
15
V
V
esd
Machine Model (MM)
Charge Device Model (CDM)
1
Offset voltage allowed in run mode between core supplies.
V
mV
core_offset
1
The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
10
Freescale Semiconductor
Electrical Characteristics
Table 6 provides the thermal resistance data for the 14 × 14 mm, 0.5 mm pitch package.
Table 6. Thermal Resistance Data—14 × 14 mm Package
Rating
Board
Symbol
Value
Unit
Notes
Junction to Ambient (natural convection)
Junction to Ambient (natural convection)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board
Single layer board (1s)
R
R
56
30
46
26
17
10
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2, 3
1, 3
θJA
Four layer board (2s2p)
θJA
Single layer board (1s)
R
R
1, 2, 3
1, 3
θJMA
θJMA
Four layer board (2s2p)
—
—
—
R
1, 4
θJB
Junction to Case
R
1, 5
θJC
Junction to Package Top (natural convection)
Ψ
1, 6
JT
NOTES
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of
other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9
specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top
and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the
thermal characterization parameter is written as Psi-JT.
Table 7 provides the thermal resistance data for the 19 × 19 mm, 0.8 mm pitch package.
Table 7. Thermal Resistance Data—19 × 19 mm Package
Rating
Board
Symbol
Value
Unit
Notes
Junction to Ambient (natural convection)
Junction to Ambient (natural convection)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board
Single layer board (1s)
R
R
46
29
38
25
19
10
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 3
θJA
θJA
Four layer board (2s2p)
Single layer board (1s)
R
R
θJMA
θJMA
Four layer board (2s2p)
—
—
—
R
θJB
Junction to Case (Top)
R
1, 4
θJCtop
Junction to Package Top (natural convection)
Ψ
1, 5
JT
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
11
Electrical Characteristics
NOTES
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of
other components on the board, and board thermal resistance.
2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6.
Thermal test board meets JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board
meets JEDEC specification for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The
cold plate temperature is used for the case temperature. Reported value includes the thermal
resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package
top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the
thermal characterization parameter is written as Psi-JT.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
12
Freescale Semiconductor
Electrical Characteristics
Table 8 provides the operating ranges.
NOTE
The term NVCC in this section refers to the associated supply rail of an
input or output. The association is shown in the Signal Multiplexing chapter
of the reference manual.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Table 8. Operating Ranges
Symbol
Parameter
Min
Max
Units
1,2,3
QVCC,
QVCC1,
QVCC4
Core Operating Voltage
0 ≤ f
0 ≤ f
0 ≤ f
≤ 400 MHz, non-overdrive
≤ 532 MHz, non-overdrive
≤ 532 MHz, overdrive
1.22
1.38
1.52
1.47
1.52
1.65
ARM
ARM
V
4
ARM
5
State Retention Voltage
0.95
—
6
NVCC1,
NVCC3–10 overdrive
I/O Supply Voltage, except DDR non-overdrive
1.75
>3.1
3.1
3.3
V
V
7
NVCC2,
NVCC21,
NVCC22
I/O Supply Voltage, DDR only
1.75
1.95
8
FVCC, MVCC, PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage
V
SVCC, UVCC
non-overdrive
1.3
>1.47
1.47
1.6
4
overdrive
IOQVDD
On-device Level Shifter Supply Voltage
1.6
1.65
3.0
1.9
1.95
3.3
70
V
V
V
9, 10
Fusebox read Supply Voltage
FUSE_VDD
11
Fusebox write (program) Supply Voltage
12
o
T
Operating Ambient Temperature Range
–20
C
A
1
2
Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively).
The core voltage must be higher than 1.38V to avoid corrupted data during transfers from the USB HS. Please refer to Errata
file ENGcm02610 ID.
3
4
If the Core voltage is supplied by the MC13738, it will be 1.6 ± 0.05 V during the power-up sequence and this is allowed. After
power-up the voltage should be reduced to avoid operation in overdrive mode.
Supply voltage is considered “overdrive” for voltages above 1.52 V. Operation time in overdrive—whether switching or
not—must be limited to a cumulative duration of 1.25 years (10,950 hours) or less to sustain the maximum operating voltage
without significant device degradation—for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated
equipment. To tolerate the maximum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or
less in overdrive (for example 3 out of 24 hours per day). Below 1.52 V, duty cycle restrictions may apply for equipment rated
above 5 years.
5
6
The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC)
is operational in State Retention (SR) mode.
Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the
duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
13
Electrical Characteristics
7
Supply voltage is considered “overdrive” for voltages above 3.1 V. Operation time in overdrive—whether switching or
not—must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without
significant device degradation—for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated
equipment. Operation at 3.3 V that exceeds a cumulative 3,504 hours may cause non-operation whenever supply voltage is
reduced to 1.8 V; degradation may render the device too slow or inoperable. Below 3.1 V, duty cycle restrictions may apply for
equipment rated above 5 years.
8
For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL ≥ Core – 100 mV. In other
words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. This restriction is no longer necessary on mask
set M91E. PLL supplies may be set independently of core supply. PLL voltage must not be altered after power up, otherwise
the PLL will be unstable and lose lock. To minimize inducing noise on the PLL supply line, source the voltage from a low-noise,
dedicated supply. PLL parameters in Table 30, "DPLL Specifications," on page 35, are guaranteed over the entire specified
voltage range.
9
Fusebox read supply voltage applies to silicon Revisions 1.2 and previous.
10
In read mode, FUSE_VDD can be floated or grounded for mask set M91E (silicon Revision 2.0.1).
11
Fuses might be inadvertently blown if written to while the voltage is below this minimum.
12
The temperature range given is for the consumer version. Please refer to Table 1 for extended temperature range offerings
and the associated part numbers.
Table 9. Specific Operating Ranges for Silicon Revision 2.0.1
Symbol
Parameter
Min
Max
Units
1
Fusebox read Supply Voltage
Fusebox write (program) Supply Voltage
—
—
V
V
FUSE_VDD
2
3.0
3.3
1
2
In read mode, FUSE_VDD should be floated or grounded.
Fuses might be inadvertently blown if written to while the voltage is below the minimum.
Table 10 provides information for interface frequency limits. For more details about clocks characteristics,
see Section 4.3.8, “DPLL Electrical Specifications,” and Section 4.3.3, “Clock Amplifier Module
(CAMP) Electrical Characteristics.”
Table 10. Interface Frequency
ID
Parameter
JTAG TCK Frequency
Symbol
Min
Typ
Max
Units
1
2
3
f
DC
32
15
5
32.768
26
10
38.4
75
MHz
kHz
JTAG
1
CKIL Frequency
f
CKIL
2
CKIH Frequency
f
MHz
CKIH
1
2
CKIL must be driven by an external clock source to ensure proper start-up and operation of the device. CKIL is needed to clock
the internal reset synchronizer, the watchdog, and the real-time clock.
DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication,
standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency
requires an update to the OS. For more details, refer to the particular OS user's guide documentation.
Table 11 shows the fusebox supply current parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
14
Freescale Semiconductor
Electrical Characteristics
Table 11. Fusebox Supply Current Parameters
Ref. Num
Description
Symbol Minimum Typical Maximum Units
1
1
eFuse Program Current.
I
—
35
60
mA
program
Current to program one eFuse bit: efuse_pgm = 3.0 V
2
2
eFuse Read Current
I
read
—
5
8
mA
Current to read an 8-bit eFuse word
vdd_fusebox = 1.875 V
1
2
The current I
The current I
is during program time (t
).
program
program
is present for approximately 50 ns of the read access to the 8-bit word, and only applies to Silicon Rev. 1.2
read
and previous.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
15
Electrical Characteristics
4.1.1
Supply Current Specifications
Table 12 shows the core current consumption for –40°C to 85°C for Silicon Revision 2.0.1 for the
MCIMX31.
1
1, 2
Table 12. Current Consumption for –40°C to 85°C
for Silicon Revision 2.0.1
FVCC + MVCC
QVCC
(Peripheral)
QVCC1
(ARM)
QVCC4
(L2)
+ SVCC + UVCC
(PLL)
Mode
Conditions
Unit
Typ Max Typ
0.16 5.50
Max
Typ Max
Typ
Max
Deep
Sleep
• QVCC = 0.95 V
—
—
—
—
0.02
0.10
mA
• ARM and L2 caches are power gated
(QVCC1 = QVCC4 = 0 V)
• All PLLs are off, VCC = 1.4 V
• ARM is in well bias
• FPM is off
• 32 kHz input is on
• CKIH input is off
• CAMP is off
• TCK input is off
• All modules are off
• No external resistive loads
• RNGA oscillator is off
State
• QVCC and QVCC1 = 0.95 V
0.16 5.50 0.07 2.20
—
—
0.02
0.10
mA
Retention • L2 caches are power gated (QVCC4 = 0 V)
• All PLLs are off, VCC = 1.4 V
• ARM is in well bias
• FPM is off
• 32 kHz input is on
• CKIH input is off
• CAMP is off
• TCK input is off
• All modules are off
• No external resistive loads
• RNGA oscillator is off
Wait
• QVCC,QVCC1, and QVCC4 = 1.22 V
• ARM is in wait for interrupt mode
• MAX is active
6.00 15.00 2.20 25.00 0.03 0.29
3.60
4.40
mA
• L2 cache is stopped but powered
• MCU PLL is on (532 MHz), VCC = 1.4 V
• USB PLL and SPLL are off, VCC = 1.4 V
• FPM is on
• CKIH input is on
• CAMP is on
• 32 kHz input is on
• All clocks are gated off
• All modules are off
(by programming CGR[2:0] registers)
• RNGA oscillator is off
• No external resistive loads
1
2
Typical column: TA = 25°C
Maximum column: TA = 85°C
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
16
Freescale Semiconductor
Electrical Characteristics
Table 13 shows the core current consumption for –20°C to 70°C for Silicon Revision 2.0.1 for the
MCIMX31.
1, 2
Table 13. Current Consumption for –20°C to 70°C
for Silicon Revision 2.0.1
FVCC, +MVCC,
QVCC
(Peripheral)
QVCC1
(ARM)
QVCC4
(L2)
+SVCC, +UVCC
(PLL)
Mode
Conditions
Unit
Typ
Max Typ Max Typ Max
Typ
Max
Deep
Sleep
• QVCC = 0.95 V
0.16
—
—
—
—
—
0.02
—
mA
• ARM and L2 caches are power gated
(QVCC1 2= QVCC4 = 0 V)
• All PLLs are off, VCC = 1.4 V
• ARM is in well bias
• FPM is off
• 32 kHz input is on
• CKIH input is off
• CAMP is off
• TCK input is off
• All modules are off
• No external resistive loads
• RNGA oscillator is off
State
• QVCC and QVCC1 = 0.95 V
0.16
—
0.07
—
—
—
0.02
—
mA
Retention • L2 caches are power gated (QVCC4 = 0 V)
• All PLLs are off, VCC = 1.4 V
• ARM is in well bias
• FPM is off
• 32 kHz input is on
• CKIH input is off
• CAMP is off
• TCK input is off
• All modules are off
• No external resistive loads
• RNGA oscillator is off
Wait
• QVCC,QVCC1, and QVCC4 = 1.22 V
• ARM is in wait for interrupt mode
• MAX is active
6.00
—
2.20
—
0.03
—
3.60
—
mA
• L2 cache is stopped but powered
• MCU PLL is on (532 MHz), VCC = 1.4 V
• USB PLL and SPLL are off, VCC = 1.4 V
• FPM is on
• CKIH input is on
• CAMP is on
• 32 kHz input is on
• All clocks are gated off
• All modules are off
(by programming CGR[2:0] registers)
• RNGA oscillator is off
• No external resistive loads
1
2
Typical column: TA = 25°C
Maximum column: TA = 70°C
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
17
Electrical Characteristics
4.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any MCIMX31 board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
may result in any or all of the following situations:
•
•
•
Cause excessive current during power up phase
Prevent the device from booting
Cause irreversible damage to the MCIMX31 (worst-case scenario)
4.2.1
Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up
logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of
POR. Figure 2 and Figure 3 show the power-up sequence for silicon Revision 2.0.1.
NOTE
Stages need to be performed in the order shown; however, within each stage,
supplies can be powered up in any order. For example, supplies IOQVDD,
NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the
order shown.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
18
Freescale Semiconductor
Electrical Characteristics
4.2.1.1
Power-Up Sequence for Silicon Revision 2.0.1
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
Hold POR Asserted
2
3
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
QVCC, QVCC1, QVCC41
The parallel paths in the flow indicate that supply group
NVCC2, NVCC21, and NVCC22, and supply group
FVCC, MVCC, SVCC, and UVCC ramp-ups are
independent.
4
5
1, 2
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0.1. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
IOQVDD, NVCC1, NVCC3–10
Raising IOQVDD before NVCC21 produces a slight
increase in current drain on IOQVDD of approximately
3–5 mA. The current increase will not damage the IC.
Refer to Errata ID TLSbo91750 for details.
NVCC2, NVCC21, NVCC221, 3, 5
1,3
FVCC, MVCC, SVCC, UVCC
4
Release POR
Figure 2. Option 1 Power-Up Sequence (Silicon Revision 2.0.1)
Notes:
1
The board design must guarantee that supplies reach
Hold POR Asserted
90% level before transition to the next state, using Power
Management IC or other means.
2
3
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
QVCC, QVCC1, QVCC41
Raising NVCC2, NVCC21, and NVCC22 at the same
time as IOQVDD does not produce the slight increase in
current drain on IOQVDD (as described in Figure 2,
Note 5).
1, 2,3
4
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0.1. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22
1
FVCC, MVCC, SVCC, UVCC
4
Release POR
Figure 3. Option 2 Power-Up Sequence (Silicon Revision 2.0.1)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
19
Electrical Characteristics
4.2.2
Powering Down
For silicon revisions beginning with Revision 2.0.1 there is no special requirements for the power down
sequence.
4.3
Module-Level Electrical Specifications
This section contains the MCIMX31 electrical information including timing specifications, arranged in
alphabetical order by module name.
4.3.1
I/O Pad (PADIO) Electrical Specifications
This section specifies the AC/DC characterization of functional I/O of the MCIMX31. There are two main
types of I/O: regular and DDR. In this document, the “Regular” type is referred to as GPIO.
4.3.1.1
DC Electrical Characteristics
The MCIMX31 I/O parameters appear in Table 14 for GPIO. See Table 8 for temperature and supply
voltage ranges.
NOTE
The term NVCC in this section refers to the associated supply rail of an
input or output. The association is shown in the Signal Multiplexing chapter
of the reference manual. NVCC for Table 14 refers to NVCC1 and
NVCC3–10; QVCC refers to QVCC, QVCC1, and QVCC4.
Table 14. GPIO DC Electrical Parameters
Parameter
Symbol
Test Conditions
= –1 mA
Min
Typ
Max
Units
High-level output voltage
V
I
NVCC –0.15
—
—
—
—
—
—
—
V
V
OH
OH
I
= specified Drive
0.8*NVCC
OH
Low-level output voltage
V
I
= 1 mA
—
—
0.15
V
OL
OL
I
= specified Drive
0.2*NVCC
—
V
OL
High-level output current, slow slew rate
I
V
=0.8*NVCC
mA
OH_S
OH
Std Drive
High Drive
Max Drive
–2
–4
–8
High-level output current, fast slew rate
Low-level output current, slow slew rate
I
V
=0.8*NVCC
OH
—
—
—
—
mA
mA
OH_F
Std Drive
High Drive
Max Drive
–4
–6
–8
I
V
=0.2*NVCC
OL
OL_S
Std Drive
High Drive
Max Drive
2
4
8
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
20
Freescale Semiconductor
Electrical Characteristics
Table 14. GPIO DC Electrical Parameters (continued)
Parameter
Symbol
Test Conditions
=0.2*NVCC
Min
Typ
Max
Units
Low-level output current, fast slew rate
I
V
—
—
mA
OL_F
OL
Std Drive
High Drive
Max Drive
4
6
8
High-Level DC input voltage
Low-Level DC input voltage
Input Hysteresis
V
—
—
0.7*NVCC
—
—
NVCC
V
V
V
V
V
IH
V
0
0.3*QVCC
IL
V
Hysteresis enabled
0.25
—
—
HYS
Schmitt trigger VT+
V +
Hysteresis enabled
0.5*QVCC
—
—
T
Schmitt trigger VT–
V –
Hysteresis enabled
—
—
—
—
—
—
0.5*QVCC
T
Pull-up resistor (100 kΩ PU)
Pull-down resistor (100 kΩ PD)
Input current (no PU/PD)
Input current (100 kΩ PU)
R
—
—
100
100
—
—
—
1
PU
kΩ
μA
R
PD
I
V = NVCC or GND
IN
I
I
V = 0
—
25
0.1
μA
μA
IN
I
V = NVCC
I
Input current (100 kΩ PD)
I
V = 0
V = NVCC
—
—
—
—
0.25
28
μA
μA
IN
I
I
Tri-state leakage current
I
V = NVCC or GND
2
μA
OZ
I
I/O = High Z
The MCIMX31 I/O parameters appear in Table 15 for DDR (Double Data Rate). See Table 8, "Operating
Ranges," on page 13 for temperature and supply voltage ranges.
NOTE
NVCC for Table 15 refers to NVCC2, NVCC21, and NVCC22.
Table 15. DDR (Double Data Rate) I/O DC Electrical Parameters
Parameter
High-level output voltage
Symbol
Test Conditions
= –1 mA
Min
Typ
Max
Units
V
I
NVCC –0.12
—
—
—
—
—
—
—
V
V
OH
OH
I
I
= specified Drive 0.8*NVCC
OH
Low-level output voltage
High-level output current
V
I
= 1 mA
OL
—
—
0.08
V
OL
= specified Drive
0.2*NVCC
—
V
OL
I
V
=0.8*NVCC
mA
OH
OH
Std Drive
High Drive
Max Drive
DDR Drive
=0.2*NVCC
OL
–3.6
–7.2
–10.8
–14.4
1
Low-level output current
I
V
—
—
mA
OL
Std Drive
High Drive
Max Drive
3.6
7.2
10.8
14.4
1
DDR Drive
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
21
Electrical Characteristics
Table 15. DDR (Double Data Rate) I/O DC Electrical Parameters (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
High-Level DC input voltage
Low-Level DC input voltage
Tri-state leakage current
V
—
—
0.7*NVCC NVCC NVCC+0.3
V
V
IH
V
I
–0.3
—
0
0.3*NVCC
2
IL
V = NVCC or GND
—
μA
OZ
I
I/O = High Z
1
Use of DDR Drive can result in excessive overshoot and ringing.
4.3.2
AC Electrical Characteristics
Figure 4 depicts the load circuit for outputs. Figure 5 depicts the output transition time waveform. The
range of operating conditions appears in Table 16 for slow general I/O, Table 17 for fast general I/O, and
Table 18 for DDR I/O (unless otherwise noted).
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
NVCC
0V
80%
20%
80%
20%
Output (at I/O)
PA1
PA1
Figure 5. Output Transition Time Waveform
1
Table 16. AC Electrical Characteristics of Slow General I/O
Test
Condition
ID
Parameter
Symbol
Min
Typ
Max
Units
PA1 Output Transition Times (Max Drive)
Output Transition Times (High Drive)
Output Transition Times (Std Drive)
tpr
25 pF
50 pF
0.92
1.5
1.95
2.98
3.17
4.75
ns
tpr
tpr
25 pF
50 pF
1.52
2.75
—
4.81
8.42
ns
ns
25 pF
50 pF
2.79
5.39
—
8.56
16.43
1
Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
22
Freescale Semiconductor
Electrical Characteristics
1
2
Table 17. AC Electrical Characteristics of Fast General I/O
Test
Condition
ID
Parameter
Symbol
Min
Typ
Max
Units
PA1
Output Transition Times (Max Drive)
tpr
25 pF
50 pF
0.68
1.34
1.33
2.6
2.07
4.06
ns
Output Transition Times (High Drive)
Output Transition Times (Std Drive)
tpr
tpr
25 pF
50 pF
.91
1.79
1.77
3.47
2.74
5.41
ns
ns
25 pF
50 pF
1.36
2.68
2.64
5.19
4.12
8.11
1
2
Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual.
Use of GPIO in fast mode with the associated NVCC > 1.95 V can result in excessive overshoot and ringing.
Table 18. AC Electrical Characteristics of DDR I/O
Test
ID
Parameter
Symbol
Min
Typ
Max
Units
Condition
1
PA1
Output Transition Times (DDR Drive)
tpr
25 pF
50 pF
0.51
0.97
0.82
1.58
1.28
2.46
ns
Output Transition Times (Max Drive)
Output Transition Times (High Drive)
Output Transition Times (Std Drive)
tpr
tpr
tpr
25 pF
50 pF
0.67
1.29
1.08
2.1
1.69
3.27
ns
ns
ns
25 pF
50 pF
.99
1.93
1.61
3.13
2.51
4.89
25 pF
50 pF
1.96
3.82
3.19
6.24
4.99
9.73
1
Use of DDR Drive can result in excessive overshoot and ringing.
4.3.3
Clock Amplifier Module (CAMP) Electrical Characteristics
This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 19
shows clock amplifier electrical characteristics.
Table 19. Clock Amplifier Electrical Characteristics for CKIH Input
Parameter
Input Frequency
Min
Typ
Max
Units
15
0
—
—
—
—
50
75
0.3
3
MHz
V
VIL (for square wave input)
VIH (for square wave input)
Sinusoidal Input Amplitude
Duty Cycle
1
(VDD – 0.25)
V
2
0.4
VDD
55
Vp-p
%
45
1
2
VDD is the supply voltage of CAMP. See reference manual.
This value of the sinusoidal input will be measured through characterization.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
23
Electrical Characteristics
4.3.4
1-Wire Electrical Specifications
Figure 6 depicts the RPP timing, and Table 20 lists the RPP timing parameters.
OWIRE Tx
DS2502 Tx
“Presence Pulse”
“Reset Pulse”
OW2
1-Wire bus
(BATT_LINE)
OW3
OW1
OW4
Figure 6. Reset and Presence Pulses (RPP) Timing Diagram
Table 20. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min
Typ
Max
Units
OW1
OW2
OW3
OW4
Reset Time Low
Presence Detect High
Presence Detect Low
Reset Time High
t
480
15
511
—
—
60
µs
µs
µs
µs
RSTL
t
PDH
t
60
—
240
—
PDL
t
480
512
RSTH
Figure 7 depicts Write 0 Sequence timing, and Table 21 lists the timing parameters.
OW6
1-Wire bus
(BATT_LINE)
OW5
Figure 7. Write 0 Sequence Timing Diagram
Table 21. WR0 Sequence Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Units
OW5
OW6
Write 0 Low Time
Transmission Time Slot
t
60
100
117
120
120
µs
µs
WR0_low
t
OW5
SLOT
Figure 8 depicts Write 1 Sequence timing, Figure 9 depicts the Read Sequence timing, and Table 22 lists
the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
24
Freescale Semiconductor
Electrical Characteristics
OW8
1-Wire bus
(BATT_LINE)
OW7
Figure 8. Write 1 Sequence Timing Diagram
OW8
1-Wire bus
(BATT_LINE)
OW7
OW9
Figure 9. Read Sequence Timing Diagram
Table 22. WR1/RD Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Units
OW7
OW8
OW9
Write 1 / Read Low Time
Transmission Time Slot
Release Time
t
1
5
15
120
45
µs
µs
µs
LOW1
t
60
15
117
—
SLOT
t
RELEASE
4.3.5
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA specification.
The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
25
Electrical Characteristics
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 23 shows ATA
timing parameters.
Table 23. ATA Timing Parameters
Value/
Contributing Factor
Name
Description
1
T
Bus clock period (ipg_clk_ata)
peripheral clock
frequency
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
15 ns
10 ns
7 ns
5 ns
UDMA5
4 ns
ti_dh
tco
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
Propagation delay bus clock L-to-H to
12.0 ns
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
tsu
tsui
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
8.5 ns
8.5 ns
2.5 ns
7 ns
thi
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
tskew2
tskew3
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
transceiver
transceiver
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
tbuf
Max buffer propagation delay
transceiver
cable
tcable1
tcable2
tskew4
tskew5
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
Max difference in cable propagation delay between ata_iordy and ata_data (read)
cable
cable
Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
cable
1
Values provided where applicable.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
26
Freescale Semiconductor
Electrical Characteristics
4.3.5.2
PIO Mode Timing
Figure 10 shows timing for PIO read, and Table 24 lists the timing parameters for PIO read.
Figure 10. PIO Read Timing Diagram
Table 24. PIO Read Timing Parameters
ATA
Parameter
Controlling
Variable
Value
Parameter from Figure 10
t1
t2
t9
t5
t1
t2r
t9
t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5)
t2 min) = time_2r * T – (tskew1 + tskew2 + tskew5)
t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6)
t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
time_1
time_2r
time_3
t5
If not met, increase
time_2
t6
tA
t6
tA
0
—
tA (min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
time_ax
trd
trd1
trd1 (max) = (–trd) + (tskew3 + tskew4)
time_pio_rdx
trd1 (min) = (time_pio_rdx – 0.5)*T – (tsu + thi)
(time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4
t0
—
t0 (min) = (time_1 + time_2 + time_9) * T
time_1, time_2r, time_9
Figure 11 shows timing for PIO write, and Table 25 lists the timing parameters for PIO write.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
27
Electrical Characteristics
Figure 11. Multiword DMA (MDMA) Timing
Table 25. PIO Write Timing Parameters
ATA
Parameter
Controlling
Variable
Value
Parameter from Figure 11
t1
t2
t9
t3
t1
t2w
t9
t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5)
t2 (min) = time_2w * T – (tskew1 + tskew2 + tskew5)
t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6)
t3 (min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5)
time_1
time_2w
time_9
—
If not met, increase
time_2w
t4
tA
t0
t4
tA
—
t4 (min) = time_4 * T – tskew1
time_4
tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
t0(min) = (time_1 + time_2 + time_9) * T
time_ax
time_1, time_2r,
time_9
—
—
—
—
Avoid bus contention when switching buffer on by making ton long enough.
Avoid bus contention when switching buffer off by making toff long enough.
—
—
Figure 12 shows timing for MDMA read, Figure 13 shows timing for MDMA write, and Table 26 lists the
timing parameters for MDMA read and write.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
28
Freescale Semiconductor
Electrical Characteristics
Figure 12. MDMA Read Timing Diagram
Figure 13. MDMA Write Timing Diagram
Table 26. MDMA Read and Write Timing Parameters
Parameter
from
Figure 12,
Figure 13
ATA
Parameter
Controlling
Variable
Value
tm, ti
tm
td, td1
tk
tm (min) = ti (min) = time_m * T – (tskew1 + tskew2 + tskew5)
td1.(min) = td (min) = time_d * T – (tskew1 + tskew2 + tskew6)
tk.(min) = time_k * T – (tskew1 + tskew2 + tskew6)
t0 (min) = (time_d + time_k) * T
time_m
time_d
td
tk
time_k
t0
—
time_d, time_k
time_d
tg(read)
tgr
tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr.(min-drive) = td – te(drive)
tf(read)
tg(write)
tf(write)
tL
tfr
—
tfr (min-drive) = 0
—
time_d
tg (min-write) = time_d * T – (tskew1 + tskew2 + tskew5)
tf (min-write) = time_k * T – (tskew1 + tskew2 + tskew6)
tL (max) = (time_d + time_k–2)*T – (tsu + tco + 2*tbuf + 2*tcable2)
—
time_k
—
time_d, time_k
tn, tj
tkjn
tn= tj= tkjn = (max(time_k,. time_jn) * T – (tskew1 + tskew2 + tskew6)
time_jn
—
—
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
29
Electrical Characteristics
4.3.5.3
UDMA In Timing
Figure 14 shows timing when the UDMA in transfer starts, Figure 15 shows timing when the UDMA in
host terminates transfer, Figure 16 shows timing when the UDMA in device terminates transfer, and
Table 27 lists the timing parameters for UDMA in burst.
Figure 14. UDMA In Transfer Starts Timing Diagram
Figure 15. UDMA In Host Terminates Transfer Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
30
Freescale Semiconductor
Electrical Characteristics
Figure 16. UDMA In Device Terminates Transfer Timing Diagram
Table 27. UDMA In Burst Timing Parameters
Parameter
from
Figure 14,
Figure 15,
Figure 16
ATA
Parameter
Description
Controlling Variable
tack
tenv
tack
tenv
tack (min) = (time_ack * T) – (tskew1 + tskew2)
time_ack
time_env
tenv (min) = (time_env * T) – (tskew1 + tskew2)
tenv (max) = (time_env * T) + (tskew1 + tskew2)
tds
tdh
tds1
tdh1
tc1
tds – (tskew3) – ti_ds > 0
tskew3, ti_ds, ti_dh
should be low enough
tdh – (tskew3) – ti_dh > 0
tcyc
trp
(tcyc – tskew) > T
T big enough
time_rp
trp
trp (min) = time_rp * T – (tskew1 + tskew2 + tskew6)
(time_rp * T) – (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive)
tmli1 (min) = (time_mlix + 0.4) * T
1
—
tx1
time_rp
tmli
tzah
tdzfs
tcvh
—
tmli1
tzah
tdzfs
tcvh
time_mlix
time_zah
time_dzfs
time_cvh
—
tzah (min) = (time_zah + 0.4) * T
tdzfs = (time_dzfs * T) – (tskew1 + tskew2)
tcvh = (time_cvh *T) – (tskew1 + tskew2)
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff big enough to avoid bus contention
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
31
Electrical Characteristics
4.3.5.4
UDMA Out Timing
Figure 17 shows timing when the UDMA out transfer starts, Figure 18 shows timing when the UDMA out
host terminates transfer, Figure 19 shows timing when the UDMA out device terminates transfer, and
Table 28 lists the timing parameters for UDMA out burst.
Figure 17. UDMA Out Transfer Starts Timing Diagram
Figure 18. UDMA Out Host Terminates Transfer Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
32
Freescale Semiconductor
Electrical Characteristics
Figure 19. UDMA Out Device Terminates Transfer Timing Diagram
Table 28. UDMA Out Burst Timing Parameters
Parameter
from
Figure 17,
Figure 18,
Figure 19
ATA
Parameter
Controlling
Variable
Value
tack
tenv
tack
tenv
tack (min) = (time_ack * T) – (tskew1 + tskew2)
time_ack
time_env
tenv (min) = (time_env * T) – (tskew1 + tskew2)
tenv (max) = (time_env * T) + (tskew1 + tskew2)
tdvs
tdvh
tcyc
t2cyc
trfs1
—
tdvs
tdvh
tcyc
—
tdvs = (time_dvs * T) – (tskew1 + tskew2)
tdvs = (time_dvh * T) – (tskew1 + tskew2)
tcyc = time_cyc * T – (tskew1 + tskew2)
t2cyc = time_cyc * 2 * T
time_dvs
time_dvh
time_cyc
time_cyc
—
trfs
trfs = 1.6 * T + tsui + tco + tbuf + tbuf
tdzfs = time_dzfs * T – (tskew1)
tss = time_ss * T – (tskew1 + tskew2)
tdzfs_mli =max (time_dzfs, time_mli) * T – (tskew1 + tskew2)
tli1 > 0
tdzfs
tss
time_dzfs
time_ss
—
tss
tmli
tli
tdzfs_mli
tli1
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
—
tcvh
tcvh = (time_cvh *T) – (tskew1 + tskew2)
time_cvh
—
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
33
Electrical Characteristics
4.3.6
AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical
specifications.
4.3.7
CSPI Electrical Specifications
This section describes the electrical information of the CSPI.
4.3.7.1 CSPI Timing
Figure 20 and Figure 21 depict the master mode and slave mode timings of CSPI, and Table 29 lists the
timing parameters.
SPI_RDY
CS11
SSx
CS2
CS6
CS1
CS3
CS5
CS3
CS4
SCLK
MOSI
MISO
CS2
CS7 CS8
CS9
CS10
Figure 20. CSPI Master Mode Timing Diagram
SSx
CS2
CS6
CS1
CS3
CS5
CS3
CS4
SCLK
CS2
CS7 CS8
MISO
MOSI
CS9
CS10
Figure 21. CSPI Slave Mode Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
34
Freescale Semiconductor
Electrical Characteristics
Table 29. CSPI Interface Timing Parameters
Parameter Symbol
ID
Min
Max
Units
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
CS11
SCLK Cycle Time
t
60
30
—
25
25
25
5
—
—
7.6
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk
SCLK High or Low Time
SCLK Rise or Fall
t
SW
RISE/FALL
t
SSx pulse width
t
CSLH
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
Data Out Setup Time
Data Out Hold Time
Data In Setup Time
t
t
SCS
HCS
t
t
t
t
Smosi
Hmosi
Smiso
Hmiso
5
6
Data In Hold Time
5
1
SPI_RDY Setup Time
t
—
SRDY
1
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.3.8
DPLL Electrical Specifications
The three PLL’s of the MCIMX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The
characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics
are provided based on measurements done for both sources—external clock source (CKIH), and FPM
(Frequency Pre-Multiplier) source.
4.3.8.1
Electrical Specifications
Table 30 lists the DPLL specification.
Table 30. DPLL Specifications
Parameter
Min
Typ
Max Unit
Comments
1
2
CKIH frequency
15
—
26
75
MHz
—
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
32; 32.768, 38.4
—
kHz FPM lock time ≈ 480 µs.
Predivision factor (PD bits)
1
—
—
16
35
—
—
PLL reference frequency range after Predivider
15
MHz 15 ≤ CKIH frequency/PD ≤ 35 MHz
15 ≤ FPM output/PD ≤ 35 MHz
PLL output frequency range:
—
MPLL and SPLL 52
UPLL 190
532 MHz
240
—
Maximum allowed reference clock phase noise.
—
—
—
—
100 ps
—
Frequency lock time
398
—
Cycles of divided reference clock.
(FOL mode or non-integer MF)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
35
Electrical Characteristics
Table 30. DPLL Specifications (continued)
Parameter
Min
Typ
Max Unit
Comments
Phase lock time
—
—
—
—
—
—
—
—
—
—
—
—
100
25
µs In addition to the frequency
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
Maximum allowed PLL supply voltage ripple
PLL output clock phase jitter
mV
F
< 50 kHz
modulation
20
mV 50 kHz < F
< 300 kHz
modulation
25
mV
F
> 300 kHz
modulation
5.2
420
ns Measured on CLKO pin
ps Measured on CLKO pin
PLL output clock period jitter
1
2
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to
the DPTC–DVFS table, which is incorporated into operating system code.
The PLL reference frequency must be ≤ 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the
predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit
description, see the reference manual.
4.3.9
EMI Electrical Specifications
This section provides electrical parametrics and timings for EMI module.
4.3.9.1 NAND Flash Controller Interface (NFC)
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC
timings are provided as multiplications of the clock cycle and fixed delay. Figure 22, Figure 23, Figure 24,
and Figure 25 depict the relative timing requirements among different signals of the NFC at module level,
for normal mode, and Table 31 lists the timing parameters.
NFCLE
NF2
NF1
NF3
NF4
NFCE
NF5
NFWE
NFALE
NF6
NF7
NF8
NF9
Command
NFIO[7:0]
Figure 22. Command Latch Cycle Timing DIagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
36
Freescale Semiconductor
Electrical Characteristics
NFCLE
NFCE
NF1
NF3
NF4
NF10
NF11
NF5
NF8
NFWE
NFALE
NF7
NF9
NF6
NFIO[7:0]
Address
Figure 23. Address Latch Cycle Timing DIagram
NFCLE
NFCE
NF1
NF3
NF10
NF11
NF5
NFWE
NFALE
NF7
NF6
NF8
NF9
NFIO[15:0]
Data to NF
Figure 24. Write Data Latch Cycle Timing DIagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
37
Electrical Characteristics
NFCLE
NFCE
NF14
NF13
NF15
NFRE
NFRB
NF17
NF16
NF12
NFIO[15:0]
Data from NF
Figure 25. Read Data Latch Cycle Timing DIagram
1
Table 31. NFC Timing Parameters
Example Timing for
Timing
T = NFC Clock Cycle
NFC Clock ≈ 33 MHz
2
ID
Parameter
Symbol
Unit
T = 30 ns
Min
Max
Min
Max
NF1 NFCLE Setup Time
NF2 NFCLE Hold Time
NF3 NFCE Setup Time
NF4 NFCE Hold Time
NF5 NF_WP Pulse Width
NF6 NFALE Setup Time
NF7 NFALE Hold Time
NF8 Data Setup Time
NF9 Data Hold Time
tCLS
tCLH
tCS
T–1.0 ns
T–2.0 ns
T–1.0 ns
T–2.0 ns
—
—
—
—
29
28
29
28
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
tWP
tALS
tALH
tDS
T–1.5 ns
28.5
T
—
—
—
—
30
27
30
25
—
—
—
—
T–3.0 ns
T
tDH
T–5.0 ns
NF10 Write Cycle Time
NF11 NFWE Hold Time
NF12 Ready to NFRE Low
NF13 NFRE Pulse Width
NF14 READ Cycle Time
NF15 NFRE High Hold Time
NF16 Data Setup on READ
NF17 Data Hold on READ
tWC
tWH
tRR
2T
T–2.5 ns
60
27.5
6T
1.5T
2T
—
—
—
180
45
—
—
—
—
—
—
tRP
tRC
60
tREH
tDSR
tDHR
0.5T–2.5 ns
N/A
12.5
10
N/A
0
1
2
The flash clock maximum frequency is 50 MHz.
Subject to DPLL jitter specification on Table 30, "DPLL Specifications," on page 35.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
38
Freescale Semiconductor
Electrical Characteristics
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.3.9.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising
edge or falling edge according to corresponding assertion/negation control fields. Address always begins
related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according
to control register configuration. Output data begins related to BCLK rising edge except in muxed mode
where both rising and falling edge may be used according to control register configuration. Input data,
ECB and DTACK all captured according to BCLK rising edge time. Figure 26 depicts the timing of the
WEIM module, and Table 32 lists the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
39
Electrical Characteristics
WEIM Outputs Timing
WE22
WE21
WE23
...
BCLK
WE1
WE2
Address
CS[x]
WE3
WE5
WE4
WE6
RW
WE7
WE9
WE8
OE
WE10
EB[x]
WE11
WE13
WE12
WE14
LBA
Output Data
WEIM Inputs Timing
BCLK
WE16
Input Data
ECB
WE15
WE18
WE20
WE17
DTACK
WE19
Figure 26. WEIM Bus Timing Diagram
Table 32. WEIM Bus Timing Parameters
Parameter
ID
Min
Max
Unit
WE1
WE2
WE3
WE4
WE5
WE6
WE7
Clock fall to Address Valid
Clock rise/fall to Address Invalid
–0.5
–0.5
–3
2.5
5
ns
ns
ns
ns
ns
ns
ns
Clock rise/fall to CS[x] Valid
Clock rise/fall to CS[x] Invalid
Clock rise/fall to RW Valid
Clock rise/fall to RW Invalid
Clock rise/fall to OE Valid
3
–3
3
–3
3
–3
3
–3
3
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
40
Freescale Semiconductor
Electrical Characteristics
Table 32. WEIM Bus Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
WE8
WE9
Clock rise/fall to OE Invalid
Clock rise/fall to EB[x] Valid
–3
–3
3
3
ns
ns
ns
ns
ns
ns
ns
WE10 Clock rise/fall to EB[x] Invalid
WE11 Clock rise/fall to LBA Valid
–3
3
–3
3
WE12 Clock rise/fall to LBA Invalid
WE13 Clock rise/fall to Output Data Valid
WE14 Clock rise to Output Data Invalid
–3
3
–2.5
–2.5
4
4
WE15 Input Data Valid to Clock rise, FCE=0
FCE=1
8
2.5
—
ns
ns
ns
ns
WE16 Clock rise to Input Data Invalid, FCE=0
FCE=1
–2
–2
—
—
—
WE17 ECB setup time, FCE=0
FCE=1
6.5
3.5
WE18 ECB hold time, FCE=0
FCE=1
–2
2
1
WE19 DTACK setup time
0
—
—
ns
ns
ns
ns
ns
1
WE20 DTACK hold time
4.5
—
2, 3
WE21 BCLK High Level Width
T/2 – 3
T/2 – 3
—
2, 3
WE22 BCLK Low Level Width
—
2
WE23 BCLK Cycle time
15
1
2
3
Applies to rising edge timing
BCLK parameters are being measured from the 50% VDD.
The actual cycle time is derived from the AHB bus clock frequency.
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Test conditions: load capacitance, 25 pF. Recommended drive strength for all
controls, address, and BCLK is Max drive.
Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, and Figure 32 depict some examples of
basic WEIM accesses to external memory devices with the timing parameters mentioned in
Table 32 for specific control parameter settings.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
41
Electrical Characteristics
BCLK
WE2
WE1
WE3
V1
Next Address
WE4
Last Valid Address
ADDR
CS[x]
RW
WE11
WE12
WE8
LBA
WE7
WE9
OE
WE10
WE16
EB[y]
V1
WE15
DATA
Figure 27. Asynchronous Memory Timing Diagram for Read Access—WSC=1
BCLK
WE2
WE1
Last Valid Address
ADDR
CS[x]
Next Address
V1
WE3
WE5
WE4
WE6
RW
LBA
OE
WE11
WE12
WE10
WE9
EB[y]
DATA
WE14
V1
WE13
Figure 28. Asynchronous Memory Timing Diagram for Write Access—
WSC=1, EBWA=1, EBWN=1, LBN=1
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
42
Freescale Semiconductor
Electrical Characteristics
BCLK
WE1
Last Valid Addr
WE3
WE2
Address V1
Address V2
ADDR
CS[x]
WE4
RW
WE11
WE7
WE12
LBA
WE8
OE
WE10
WE9
EB[y]
WE18
WE18
WE17
ECB
WE17
V1+2
WE16
V1
WE16
WE15
V2
Halfword
V2+2
Halfword
DATA
Halfword Halfword
WE15
Figure 29. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—
WSC=2, SYNC=1, DOL=0
BCLK
WE2
WE4
WE6
WE1
ADDR
Last Valid Addr
Address V1
WE3
CS[x]
WE5
RW
WE12
WE11
LBA
OE
WE10
WE9
EB[y]
WE18
ECB
WE17
V1
WE14
WE14
WE13
V1+4 V1+8 V1+12
DATA
WE13
Figure 30. Synchronous Memory TIming Diagram for Burst Write Access—
BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
43
Electrical Characteristics
BCLK
WE1
WE2
WE14
WE4
WE6
ADDR/
M_DATA
Last Valid Addr
Write Data
Address V1
WE13
WE3
CS[x]
RW
WE5
Write
WE11
WE12
LBA
OE
WE9
WE10
EB[y]
Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Write Access—
WSC=7, LBA=1, LBN=1, LAH=1
BCLK
WE16
WE2
WE1
Last Valid Addr
WE3
ADDR/
M_DATA
Address V1
Read Data
WE15
CS[x]
WE4
RW
WE11
WE12
LBA
WE7
WE8
OE
WE9
WE10
EB[y]
Figure 32. Muxed A/D Mode Timing Diagram for Asynchronous Read Access—
WSC=7, LBA=1, LBN=1, LAH=1, OEA=7
4.3.9.3
ESDCTL Electrical Specifications
Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, and Figure 38 depict the timings pertaining to the
ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 33, Table 34, Table 35, Table 36,
Table 37, and Table 38 list the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
44
Freescale Semiconductor
Electrical Characteristics
SD1
SDCLK
SDCLK
SD2
SD3
SD4
CS
RAS
CAS
SD5
SD4
SD5
SD4
SD4
SD5
SD5
WE
ADDR
DQ
SD6
SD7
ROW/BA
COL/BA
SD8
SD10
SD9
Data
SD4
DQM
Note: CKE is high during the read/write cycle.
Figure 33. SDRAM Read Cycle Timing Diagram
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters
SD5
ID
Parameter
Symbol
Min
Max
Unit
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
tCH
tCL
3.4
3.4
7.5
2.0
1.8
2.0
1.8
—
4.1
4.1
—
ns
ns
ns
ns
ns
ns
ns
ns
tCK
CS, RAS, CAS, WE, DQM, CKE setup time
CS, RAS, CAS, WE, DQM, CKE hold time
Address setup time
tCMS
tCMH
tAS
—
—
—
Address hold time
tAH
—
SDRAM access time
tAC
6.47
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
45
Electrical Characteristics
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
1
SD9
Data out hold time
tOH
tRC
1.8
10
—
—
ns
SD10
Active to read/write command period
clock
1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 37 and Table 38.
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 33indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
46
Freescale Semiconductor
Electrical Characteristics
SD1
SDCLK
SDCLK
SD2
SD4
SD3
CS
SD5
RAS
CAS
SD11
SD4
SD5
SD5
SD4
SD4
WE
SD5
SD12
SD7
SD6
BA
ADDR
COL/BA
DATA
ROW / BA
SD13
SD14
DQ
DQM
Figure 34. SDR SDRAM Write Cycle Timing Diagram
Table 34. SDR SDRAM Write Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD11
SD12
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
tCH
tCL
3.4
3.4
7.5
2.0
1.8
2.0
1.8
1
4.1
4.1
—
—
—
—
—
4
ns
ns
tCK
ns
CS, RAS, CAS, WE, DQM, CKE setup time
CS, RAS, CAS, WE, DQM, CKE hold time
Address setup time
tCMS
tCMH
tAS
ns
ns
ns
Address hold time
tAH
ns
1
Precharge cycle period
tRP
clock
clock
1
Active to read/write command delay
tRCD
1
8
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
47
Electrical Characteristics
Table 34. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
SD13
SD14
Data setup time
Data hold time
tDS
tDH
2.0
1.3
—
—
ns
ns
1
SD11 and SD12 are determined by SDRAM controller register settings.
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 34indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
SD1
SDCLK
SDCLK
SD2
SD3
CS
RAS
CAS
SD11
SD10
SD10
WE
SD7
SD6
BA
ADDR
ROW/BA
Figure 35. SDRAM Refresh Timing Diagram
Table 35. SDRAM Refresh Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SD2
SDRAM clock high-level width
SDRAM clock low-level width
tCH
tCL
3.4
3.4
4.1
4.1
ns
ns
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
48
Freescale Semiconductor
Electrical Characteristics
Table 35. SDRAM Refresh Timing Parameters (continued)
ID
Parameter
SDRAM clock cycle time
Symbol
Min
Max
Unit
SD3
SD6
tCK
tAS
tAH
tRP
tRC
7.5
1.8
1.8
1
—
—
—
4
ns
ns
Address setup time
Address hold time
SD7
ns
1
SD10
SD11
Precharge cycle period
clock
clock
1
Auto precharge command period
2
20
1
SD10 and SD11 are determined by SDRAM controller register settings.
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 35indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
49
Electrical Characteristics
SDCLK
CS
RAS
CAS
WE
ADDR
CKE
BA
SD16
SD16
Don’t care
Figure 36. SDRAM Self-Refresh Cycle Timing Diagram
NOTE
The clock will continue to run unless both CKEs are low. Then the clock
will be stopped in low state.
Table 36. SDRAM Self-Refresh Cycle Timing Parameters
ID
SD16
Parameter
CKE output delay time
Symbol
Min
Max
Unit
tCKS
1.8
—
ns
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
50
Freescale Semiconductor
Electrical Characteristics
SDCLK
SDCLK
SD20
SD19
DQS (output)
DQ (output)
SD18
Data
SD17
Data
SD17
SD17
SD18
Data
Data
DM
Data
DM
Data
Data
Data
DM
DQM (output)
DM
DM
DM
DM
DM
SD17
SD18
SD18
Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 37. Mobile DDR SDRAM Write Cycle Timing Parameters
1
ID
Parameter
Symbol
Min
Max Unit
SD17 DQ and DQM setup time to DQS
tDS
tDH
0.95
0.95
1.8
—
—
—
—
ns
ns
ns
ns
SD18 DQ and DQM hold time to DQS
SD19 Write cycle DQS falling edge to SDCLK output delay time.
SD20 Write cycle DQS falling edge to SDCLK output hold time.
tDSS
tDSH
1.8
1
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 37indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
51
Electrical Characteristics
SDCLK
SDCLK
SD23
DQS (input)
DQ (input)
SD22
Data
SD21
Data
Data
Data
Data
Data
Data
Data
Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
Table 38. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol Min Max Unit
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
tDQSQ
tQH
—
2.3
—
0.85 ns
—
ns
ns
SD23 DQS output access time from SDCLK posedge
tDQSCK
6.7
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 38indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
4.3.10 ETM Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that
supports TRACECLK frequencies up to 133 MHz.
Figure 39 depicts the TRACECLK timings of ETM, and Table 39 lists the timing parameters.
Figure 39. ETM TRACECLK Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
52
Freescale Semiconductor
Electrical Characteristics
Table 39. ETM TRACECLK Timing Parameters
ID
Parameter
Min
Max
Unit
T
Clock period
Frequency dependent
—
—
—
3
ns
ns
ns
ns
ns
cyc
T
Low pulse width
2
2
wl
T
High pulse width
wh
T
Clock and data rise time
Clock and data fall time
—
—
r
T
3
f
Figure 40 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 40 lists the timing parameters.
Figure 40. Trace Data Timing Diagram
Table 40. ETM Trace Data Timing Parameters
ID
Parameter
Min
Max
Unit
T
T
Data setup
Data hold
2
1
—
—
ns
ns
s
h
4.3.10.1 Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and
falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 40.
4.3.11 FIR Electrical Specifications
®
FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA (Infrared Data
Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.
4.3.12 Fusebox Electrical Specifications
Table 41. Fusebox Timing Characteristics
Ref. Num
Description
Symbol
Minimum
Typical
Maximum
Units
1
1
Program time for eFuse
t
125
—
—
µs
program
1
The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program
is based on a 32 kHz clock source (4 * 1/32 kHz = 125 µs).
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
53
Electrical Characteristics
4.3.13 I2C Electrical Specifications
2
This section describes the electrical information of the I C Module.
4.3.13.1 I2C Module Timing
2
2
Figure 41 depicts the timing of I C module. Table 42 lists the I C module timing parameters where the I/O
supply is 2.7 V. 1
IC11
IC9
IC10
I2DAT
I2CLK
IC7
IC4
IC2
IC3
IC8
IC10
IC6
IC11
STOP
START
START
START
IC5
IC1
2
Figure 41. I C Bus Timing Diagram
2
2
Table 42. I C Module Timing Parameters—I C Pin I/O Supply=2.7 V
Standard Mode
Fast Mode
Min Max
ID
Parameter
Unit
Min
Max
IC1 I2CLK cycle time
10
4.0
4.0
—
—
—
2.5
0.6
0.6
—
—
—
0.9
—
—
—
—
—
μs
μs
μs
μs
μs
μs
μs
ns
μs
ns
ns
pF
IC2 Hold time (repeated) START condition
IC3 Set-up time for STOP condition
IC4 Data hold time
1
2
1
2
0
3.45
—
0
IC5 HIGH Period of I2CLK Clock
4.0
4.7
4.7
250
4.7
—
0.6
1.3
0.6
IC6 LOW Period of the I2CLK Clock
IC7 Set-up time for a repeated START condition
IC8 Data set-up time
—
—
3
—
100
1.3
IC9 Bus free time between a STOP and START condition
IC10 Rise time of both I2DAT and I2CLK signals
IC11 Fall time of both I2DAT and I2CLK signals
—
4
4
1000
300
400
20+0.1C
20+0.1C
—
300
300
400
b
b
—
IC12 Capacitive load for each bus line (C )
—
b
1
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2
3
The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
2
2
A Fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time
2
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I C-bus specification)
before the I2CLK line is released.
4
C = total capacitance of one bus line in pF.
b
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
54
Freescale Semiconductor
Electrical Characteristics
4.3.14 IPU—Sensor Interfaces
4.3.14.1 Supported Camera Sensors
Table 43 lists the known supported camera sensors at the time of publication.
1
Table 43. Supported Camera Sensors
Vendor
Model
2
2
Conexant
Agilant
CX11646, CX20490 , CX20450
2
2
HDCP–2010, ADCS–1021 , ADCS–1021
TC90A70
Toshiba
ICMedia
iMagic
2
ICM202A, ICM102
IM8801
Transchip
Fujitsu
TC5600, TC5600J, TC5640, TC5700, TC6000
MB86S02A
MI–SOC–0133
MN39980
Micron
Matsushita
STMicro
OmniVision
Sharp
2
2
2
2
W6411, W6500, W6501 , W6600 , W6552 , STV0974
OV7620, OV6630
LZ0P3714 (CCD)
2
2
2
2
2
Motorola
MC30300 (Python) , SCM20014 , SCM20114 , SCM22114 , SCM20027
2
National Semiconductor
LM9618
1
2
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
camera suppliers.
These sensors not validated at time of publication.
4.3.14.2 Functional Description
There are three timing modes supported by the IPU.
4.3.14.2.1 Pseudo BT.656 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing
syntax is defined by the BT.656 standard.
This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal
used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An
active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in
between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus
recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
55
Electrical Characteristics
4.3.14.2.2 Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 42.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
invalid
invalid
SENSB_DATA[9:0]
1st byte
1st byte
Figure 42. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is
valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.3.14.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 43. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
invalid
invalid
SENSB_DATA[7:0]
1st byte
1st byte
Figure 43. Non-Gated Clock Mode Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
56
Freescale Semiconductor
Electrical Characteristics
The timing described in Figure 43 is that of a Motorola sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.3.14.3 Electrical Characteristics
Figure 44 depicts the sensor interface timing, and Table 44 lists the timing parameters.
1/IP1
SENSB_MCLK
(Sensor Input)
SENSB_PIX_CLK
(Sensor Output)
1/IP4
IP2
IP3
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 44. Sensor Interface Timing Diagram
Table 44. Sensor Interface Timing Parameters
1
ID
Parameter
Symbol
Min.
Max.
Units
IP1
IP2
IP3
Sensor input clock frequency
Data and control setup time
Fmck
Tsu
0.01
5
133
—
MHz
ns
Data and control holdup time
Sensor output (pixel) clock frequency
Thd
3
—
ns
IP4
Fpck
0.01
133
MHz
1
The timing specifications for Figure 44 are referenced to the rising edge of SENS_PIX_CLK when the
SENS_PIX_CLK_POL bit in the CSI_SENS_CONF register is cleared. When the SENS_PIX_CLK_POL is set,
the clock is inverted and all timing specifications will remain the same but are referenced to the falling edge of
the clock.
4.3.15 IPU—Display Interfaces
4.3.15.1 Supported Display Components
Table 45 lists the known supported display components at the time of publication.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
57
Electrical Characteristics
1
Table 45. Supported Display Components
Vendor
Type
Model
TFT displays
(memory-less)
Sharp (HR-TFT Super
Mobile LCD family)
LQ035Q7 DB02, LM019LC1Sxx
Samsung (QCIF and
QVGA TFT modules for
mobile phones)
LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1,
LTS350Q1-PD1, LTS220Q1-HE1
2
2
2
Toshiba (LTM series)
LTM022P806 , LTM04C380K ,
2
2
2
2
LTM018A02A , LTM020P332 , LTM021P337 , LTM019P334 ,
2
2
LTM022A783 , LTM022A05ZZ
NEC
NL6448BC20-08E, NL8060BC31-27
S1D15xxx series, S1D19xxx series, S1D13713, S1D13715
SSD1301 (OLED), SSD1828 (LDCD)
HD66766, HD66772
Display controllers
Epson
Solomon Systech
Hitachi
ATI
W2300
2
2
2
2
2
Smart display modules
Epson
L1F10043 T , L1F10044 T , L1F10045 T , L2D22002 , L2D20014 ,
2
2
L2F50032 , L2D25001 T
Hitachi
120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766
controller
Densitron Europe LTD
All displays with MPU 80/68K series interface and serial peripheral
interface
Sharp
LM019LC1Sxx
ACX506AKM
ADV7174/7179
CS49xx series
FS453/4
Sony
Digital video encoders
(for TV)
Analog Devices
Crystal (Cirrus Logic)
Focus
1
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
display component suppliers.
2
These display components not validated at time of publication.
4.3.15.2 Synchronous Interfaces
4.3.15.2.1 Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 45 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
•
DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
•
•
DISPB_D3_HSYNC causes the panel to start a new line.
DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
58
Freescale Semiconductor
Electrical Characteristics
•
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DISPB_D3_HSYNC
DISPB_D3_DRDY
1
2
3
m-1
m
DISPB_D3_CLK
DISPB_D3_DATA
Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 46 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
IP7
IP6
IP9
IP10
IP8
IP5
Start of line
DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 47 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
59
Electrical Characteristics
End of frame
Start of frame
IP13
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
IP15
IP11
IP14
IP12
Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse
Table 46 shows timing parameters of signals presented in Figure 46 and Figure 47.
Table 46. Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
1
IP5
IP6
Display interface clock period
Display pixel clock period
Screen width
Tdicp
Tdpcp
Tsw
Tdicp
ns
ns
ns
ns
ns
ns
ns
ns
ns
(DISP3_IF_CLK_CNT_D+1) * Tdicp
(SCREEN_WIDTH+1) * Tdpcp
(H_SYNC_WIDTH+1) * Tdpcp
BGXP * Tdpcp
IP7
IP8
HSYNC width
Thsw
Thbi1
Thbi2
Thsd
Tsh
IP9
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
IP10
IP11
IP12
IP13
(SCREEN_WIDTH – BGXP – FW) * Tdpcp
H_SYNC_DELAY * Tdpcp
Screen height
(SCREEN_HEIGHT+1) * Tsw
VSYNC width
Tvsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
IP14
IP15
Vertical blank interval 1
Vertical blank interval 2
Tvbi1
Tvbi2
BGYP * Tsw
ns
ns
(SCREEN_HEIGHT – BGYP – FH) * Tsw
1
Display interface clock period immediate value.
⎧
⎪
⎪
⎨
⎪
⎪
⎩
DISP3_IF_CLK_PER_WR
-----------------------------------------------------------------
DISP3_IF_CLK_PER_WR
-----------------------------------------------------------------
T
⋅
,
for integer
HSP_CLK
HSP_CLK_PERIOD
HSP_CLK_PERIOD
Tdicp =
DISP3_IF_CLK_PER_WR
DISP3_IF_CLK_PER_WR
⎛
⎞
+ 0.5 0.5 ,
⎠
-----------------------------------------------------------------
-----------------------------------------------------------------
T
⋅ floor
for fractional
HSP_CLK
⎝
HSP_CLK_PERIOD
HSP_CLK_PERIOD
Display interface clock period average value.
DISP3_IF_CLK_PER_WR
-----------------------------------------------------------------
⋅
Tdicp = T
HSP_CLK
HSP_CLK_PERIOD
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
60
Freescale Semiconductor
Electrical Characteristics
NOTE
HSP_CLK is the High-Speed Port Clock, which is the input to the Image
Processing Unit (IPU). Its frequency is controlled by the Clock Control
Module (CCM) settings. The HSP_CLK frequency must be greater than or
equal to the AHB clock frequency.
The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and
V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,
SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA
channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters
are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC
Registers.
Figure 48 depicts the synchronous display interface timing for access level, and Table 47 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
IP20
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
other controls
DISPB_D3_CLK
IP18
IP16
IP17
IP19
DISPB_DATA
Figure 48. Synchronous Display Interface Timing Diagram—Access Level
Table 47. Synchronous Display Interface Timing Parameters—Access Level
1
ID
Parameter
Symbol
Min
Typ
Max
Units
2
3
IP16 Display interface clock low time
Tckl
Tdicd–Tdicu–1.5
Tdicd –Tdicu
Tdicd–Tdicu+1.5
ns
ns
IP17 Display interface clock high
time
Tckh Tdicp–Tdicd+Tdicu–1.5 Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.5
IP18 Data setup time
IP19 Data holdup time
Tdsu Tdicd–3.5
Tdicu
—
—
—
ns
ns
ns
Tdhd Tdicp–Tdicd–3.5
Tcsu Tdicd–3.5
Tdicp–Tdicu
Tdicu
IP20 Control signals setup time to
display interface clock
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
61
Electrical Characteristics
2
Display interface clock down time
1
2
2 ⋅ DISP3_IF_CLK_DOWN_WR
--------------------------------------------------------------------------------
⋅ ceil
HSP_CLK
--
Tdicd =
T
HSP_CLK_PERIOD
3
Display interface clock up time
1
2
2 ⋅ DISP3_IF_CLK_UP_WR
---------------------------------------------------------------------
⋅ ceil
HSP_CLK
--
Tdicu =
T
HSP_CLK_PERIOD
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49 depicts the Sharp HR-TFT panel interface timing, and Table 48 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing
images correspond to straight polarity of the Sharp signals.
Horizontal timing
DISPB_D3_CLK
D1 D2
D320
DISPB_D3_DATA
DISPB_D3_SPL
IP21
1 DISPB_D3_CLK period
DISPB_D3_HSYNC
IP23
IP22
DISPB_D3_CLS
DISPB_D3_PS
IP24
IP25
IP26
DISPB_D3_REV
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
62
Freescale Semiconductor
Electrical Characteristics
Table 48. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
SPL rise time
Symbol
Value
(BGXP – 1) * Tdpcp
Units
IP21
IP22
IP23
IP24
IP25
IP26
Tsplr
Tclsr
Tclsf
Tpsf
Tpsr
Trev
ns
ns
ns
ns
ns
ns
CLS rise time
CLS_RISE_DELAY * Tdpcp
CLS_FALL_DELAY * Tdpcp
PS_FALL_DELAY * Tdpcp
PS_RISE_DELAY * Tdpcp
REV_TOGGLE_DELAY * Tdpcp
CLS fall time
CLS rise and PS fall time
PS rise time
REV toggle time
4.3.15.4 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.3.15.2.2, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics.”
4.3.15.4.1 Interface to a TV Encoder, Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 50 depicts the
interface timing,
•
•
•
The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).
The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.
It remains low for a single clock cycle.
•
The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
•
The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
63
Electrical Characteristics
DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
DISPB_DATA
Cb
Y
Cr
Y
3
Cb
Y
Cr
Pixel Data Timing
523
524
525
1
2
4
5
6
10
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
262 263
Odd Field
268 269
261
264
265
266
267
273
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
621
622
623
624
625
1
2
3
4
23
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
315
308
309
310
311
312
313
314
316
336
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 50. TV Encoder Interface Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
64
Freescale Semiconductor
Electrical Characteristics
4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics.”
4.3.15.5 Asynchronous Interfaces
4.3.15.5.1 Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
•
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
•
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal
(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system
68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when
transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD
signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during
the whole burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 51,
Figure 52, Figure 53, and Figure 54. These timing images correspond to active-low DISPB_D#_CS,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
65
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 51. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
66
Freescale Semiconductor
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 52. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
67
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 53. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
68
Freescale Semiconductor
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by ENABLE signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 54. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Display read operation can be performed with wait states when each read access takes up to four display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers.
Figure 55 shows timing of the parallel interface with read wait states.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
69
Electrical Characteristics
WRITE OPERATION
DISP0_RD_WAIT_ST=00
READ OPERATION
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=01
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=10
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
Figure 55. Parallel Interface Timing Diagram—Read Wait States
4.3.15.5.2 Parallel Interfaces, Electrical Characteristics
Figure 56, Figure 58, Figure 57, and Figure 59 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 49 lists the timing parameters at display access level. All
timing images are based on active low control signals (signals polarity is controlled via the
DI_DISP_SIG_POL Register).
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
70
Freescale Semiconductor
Electrical Characteristics
IP28, IP27
DISPB_PAR_RS
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
IP35, IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP40
IP39
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 56. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
71
Electrical Characteristics
IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35, IP33
IP36, IP34
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 57. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
72
Freescale Semiconductor
Electrical Characteristics
IP28, IP27
DISPB_PAR_RS
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
IP35,IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
IP31, IP29
IP32, IP30
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 58. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
73
Electrical Characteristics
IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35,IP33
IP36, IP34
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
DISPB_WR
(READ/WRITE)
IP32, IP30
IP31, IP29
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 49. Asynchronous Parallel Interface Timing Parameters—Access Level
1
ID
Parameter
Symbol
Min.
Typ.
Max.
Tdicpr+1.5
Units
2
IP27 Read system cycle time
IP28 Write system cycle time
IP29 Read low pulse width
IP30 Read high pulse width
Tcycr Tdicpr–1.5
Tdicpr
ns
ns
ns
ns
3
Tcycw Tdicpw–1.5
Tdicpw
Tdicpw+1.5
4
5
Trl
Tdicdr–Tdicur–1.5
Tdicdr –Tdicur
Tdicdr–Tdicur+1.5
Tdicpr–Tdicdr+Tdicur+1.5
Trh
Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+
Tdicur
6
7
IP31 Write low pulse width
IP32 Write high pulse width
Twl
Tdicdw–Tdicuw–1.5
Tdicdw –Tdicuw
Tdicdw–Tdicuw+1.5
ns
ns
Twh
Tdicpw–Tdicdw+
Tdicuw–1.5
Tdicpw–Tdicdw+
Tdicuw
Tdicpw–Tdicdw+
Tdicuw+1.5
IP33 Controls setup time for read
IP34 Controls hold time for read
Tdcsr Tdicur–1.5
Tdicur
—
—
—
ns
ns
ns
Tdchr Tdicpr–Tdicdr–1.5
Tdicpr–Tdicdr
Tdicuw
IP35 Controls setup time for write Tdcsw Tdicuw–1.5
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
74
Freescale Semiconductor
Electrical Characteristics
Table 49. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
1
ID
Parameter
Symbol
Min.
Typ.
Max.
Units
IP36 Controls hold time for write
Tdchw Tdicpw–Tdicdw–1.5
Tdicpw–Tdicdw
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
9
10
IP37 Slave device data delay
Tracc
Troh
Tds
0
Tdrp –Tlbd –Tdicur–1.5
Tdicpr–Tdicdr–1.5
—
8
IP38 Slave device data hold time
IP39 Write data setup time
IP40 Write data hold time
Tdrp–Tlbd–Tdicdr+1.5
Tdicdw–1.5
—
Tdicdw
Tdicpw–Tdicdw
Tdicpr
Tdh
Tdicpw–Tdicdw–1.5
—
2
IP41 Read period
Tdicpr Tdicpr–1.5
Tdicpw Tdicpw–1.5
Tdicdr Tdicdr–1.5
Tdicur Tdicur–1.5
Tdicdw Tdicdw–1.5
Tdicuw Tdicuw–1.5
Tdrp Tdrp–1.5
Tdicpr+1.5
Tdicpw+1.5
Tdicdr+1.5
Tdicur+1.5
Tdicdw+1.5
Tdicuw+1.5
Tdrp+1.5
3
IP42 Write period
Tdicpw
Tdicdr
4
IP43 Read down time
5
IP44 Read up time
Tdicur
6
IP45 Write down time
Tdicdw
Tdicuw
Tdrp
7
IP46 Write up time
9
IP47 Read time point
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
2
Display interface clock period value for read:
DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
⋅ ceil
Tdicpr = T
HSP_CLK
3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
-----------------------------------------------------------------
⋅ ceil
Tdicpw = T
HSP_CLK
4
Display interface clock down time for read:
1
2
2 ⋅ DISP#_IF_CLK_DOWN_RD
--
-------------------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicdr =
T
HSP_CLK_PERIOD
5
6
7
Display interface clock up time for read:
1
2
2 ⋅ DISP#_IF_CLK_UP_RD
--
--------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicur =
T
HSP_CLK_PERIOD
Display interface clock down time for write:
1
2
2 ⋅ DISP#_IF_CLK_DOWN_WR
--
--------------------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicdw =
T
HSP_CLK_PERIOD
Display interface clock up time for write:
1
2
2 ⋅ DISP#_IF_CLK_UP_WR
--
---------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicuw =
T
HSP_CLK_PERIOD
8
9
This parameter is a requirement to the display connected to the IPU
Data read point
DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
⋅ ceil
Tdrp = T
HSP_CLK
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
75
Electrical Characteristics
The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.3.15.5.3 Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces:
•
•
•
•
3-wire (with bidirectional data line)
4-wire (with separate data input and output lines)
5-wire type 1 (with sampling RS by the serial clock)
5-wire type 2 (with sampling RS by the chip select signal)
Figure 60 depicts timing of the 3-wire serial interface. The timing images correspond to active-low
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D
signal provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF
Registers.
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
RW
RS
D7
D6
D5
D4
D3
D2
D1
D0
Input or output data
Preamble
Figure 60. 3-Wire Serial Interface Timing Diagram
Figure 61 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
data lines both inside and outside the device.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
76
Freescale Semiconductor
Electrical Characteristics
Write
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
D7
D6
D5
D4
D3
D2
D1
D0
Preamble
Output data
DISPB_SD_D
(Input)
Read
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 61. 4-Wire Serial Interface Timing Diagram
Figure 62 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is
added. When a burst is transmitted within single active chip select interval, the RS can be changed at
boundaries of words.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
77
Electrical Characteristics
Write
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
D4
D3
D2
D1
D0
Preamble
Output data
DISPB_SD_D
(Input)
DISPB_SER_RS
Read
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
DISPB_SER_RS
Figure 62. 5-Wire Serial Interface (Type 1) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
78
Freescale Semiconductor
Electrical Characteristics
Figure 63 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within single active chip select interval, the RS can be changed at
boundaries of words.
Write
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
D4
D3
D2
D1
D0
Output data
Preamble
DISPB_SD_D
(Input)
1 display IF
clock cycle
DISPB_SER_RS
Read
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
1 display IF
clock cycle
DISPB_SER_RS
Figure 63. 5-Wire Serial Interface (Type 2) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
79
Electrical Characteristics
4.3.15.5.4 Serial Interfaces, Electrical Characteristics
Figure 64 depicts timing of the serial interface. Table 50 lists the timing parameters at display access level.
IP49, IP48
DISPB_SER_RS
IP56,IP54
IP57, IP55
DISPB_SD_D_CLK
IP51, IP53
IP50, IP52
read point
IP59
IP58
DISPB_DATA
(Input)
Read Data
IP60
IP61
DISPB_DATA
(Output)
IP67,IP65
IP47
IP64, IP66
IP62, IP63
Figure 64. Asynchronous Serial Interface Timing Diagram
Table 50. Asynchronous Serial Interface Timing Parameters—Access Level
1
ID
Parameter
Symbol
Min.
Typ.
Max.
Tdicpr+1.5
Units
2
IP48 Read system cycle time
IP49 Write system cycle time
IP50 Read clock low pulse width
IP51 Read clock high pulse width
Tcycr Tdicpr–1.5
Tdicpr
ns
ns
ns
ns
3
Tcycw Tdicpw–1.5
Tdicpw
Tdicpw+1.5
4
5
Trl
Tdicdr–Tdicur–1.5
Tdicdr –Tdicur
Tdicdr–Tdicur+1.5
Tdicpr–Tdicdr+Tdicur+1.5
Trh
Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+
Tdicur
6
7
IP52 Write clock low pulse width
IP53 Write clock high pulse width
Twl
Tdicdw–Tdicuw–1.5
Tdicdw –Tdicuw
Tdicdw–Tdicuw+1.5
ns
ns
Twh
Tdicpw–Tdicdw+
Tdicuw–1.5
Tdicpw–Tdicdw+ Tdicpw–Tdicdw+
Tdicuw
Tdicuw+1.5
IP54 Controls setup time for read
IP55 Controls hold time for read
Tdcsr Tdicur–1.5
Tdicur
—
—
ns
ns
Tdchr Tdicpr–Tdicdr–1.5
Tdicpr–Tdicdr
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
80
Freescale Semiconductor
Electrical Characteristics
Table 50. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
1
ID
Parameter
Symbol
Min.
Typ.
Max.
Units
IP56 Controls setup time for write Tdcsw Tdicuw–1.5
Tdicuw
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IP57 Controls hold time for write
Tdchw Tdicpw–Tdicdw–1.5
Tdicpw–Tdicdw
—
—
8
9
10
IP58 Slave device data delay
Tracc
Troh
Tds
0
Tdrp –Tlbd –Tdicur–1.5
Tdicpr–Tdicdr–1.5
—
8
IP59 Slave device data hold time
IP60 Write data setup time
IP61 Write data hold time
Tdrp–Tlbd–Tdicdr+1.5
Tdicdw–1.5
—
Tdicdw
Tdicpw–Tdicdw
Tdicpr
Tdh
Tdicpw–Tdicdw–1.5
—
2
IP62 Read period
Tdicpr Tdicpr–1.5
Tdicpw Tdicpw–1.5
Tdicdr Tdicdr–1.5
Tdicur Tdicur–1.5
Tdicdw Tdicdw–1.5
Tdicuw Tdicuw–1.5
Tdrp Tdrp–1.5
Tdicpr+1.5
Tdicpw+1.5
Tdicdr+1.5
Tdicur+1.5
Tdicdw+1.5
Tdicuw+1.5
Tdrp+1.5
3
IP63 Write period
Tdicpw
Tdicdr
4
IP64 Read down time
5
IP65 Read up time
Tdicur
6
IP66 Write down time
Tdicdw
Tdicuw
Tdrp
7
IP67 Write up time
9
IP68 Read time point
1
2
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
Display interface clock period value for read:
DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
⋅ ceil
Tdicpr = T
HSP_CLK
3
4
5
6
7
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
-----------------------------------------------------------------
⋅ ceil
Tdicpw = T
HSP_CLK
Display interface clock down time for read:
1
2
2 ⋅ DISP#_IF_CLK_DOWN_RD
--
-------------------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicdr =
T
HSP_CLK_PERIOD
Display interface clock up time for read:
1
2
2 ⋅ DISP#_IF_CLK_UP_RD
--
--------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicur =
T
HSP_CLK_PERIOD
Display interface clock down time for write:
1
2
2 ⋅ DISP#_IF_CLK_DOWN_WR
--
--------------------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicdw =
T
HSP_CLK_PERIOD
Display interface clock up time for write:
1
2
2 ⋅ DISP#_IF_CLK_UP_WR
--
---------------------------------------------------------------------
⋅ ceil
HSP_CLK
Tdicuw =
T
HSP_CLK_PERIOD
8
9
This parameter is a requirement to the display connected to the IPU.
Data read point:
DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
⋅ ceil
Tdrp = T
HSP_CLK
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
81
Electrical Characteristics
The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.3.16 Memory Stick Host Controller (MSHC)
Figure 65, Figure 66, and Figure 67 depict the MSHC timings, and Table 51 and Table 52 list the timing
parameters.
tSCLKc
tSCLKwh
tSCLKwl
MSHC_SCLK
tSCLKr
tSCLKf
Figure 65. MSHC_CLK Timing Diagram
tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
Figure 66. Transfer Operation Timing Diagram (Serial)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
82
Freescale Semiconductor
Electrical Characteristics
tSCLKc
MSHC_SCLK
MSHC_BS
tBSsu
tBSh
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
Figure 67. Transfer Operation Timing Diagram (Parallel)
NOTE
The Memory Stick Host Controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications
document. Tables in this section details the specifications requirements for
parallel and serial modes, and not the MCIMX31 timing.
1
Table 51. Serial Interface Timing Parameters
Standards
Signal
Parameter
Symbol
Unit
Min.
Max.
Cycle
H pulse length
L pulse length
Rise time
tSCLKc
tSCLKwh
tSCLKwl
tSCLKr
tSCLKf
tBSsu
tBSh
50
15
15
—
—
5
—
—
—
10
10
—
—
—
—
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSHC_SCLK
Fall time
Setup time
Hold time
MSHC_BS
5
Setup time
Hold time
tDsu
5
MSHC_DATA
tDh
5
Output delay time
tDd
—
1
Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See
NVCC restrictions described in Table 8, "Operating Ranges," on page 13.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
83
Electrical Characteristics
1
Table 52. Parallel Interface Timing Parameters
Standards
Signal
Parameter
Symbol
Unit
Min
Max
Cycle
H pulse length
L pulse length
Rise time
tSCLKc
tSCLKwh
tSCLKwl
tSCLKr
tSCLKf
tBSsu
tBSh
25
5
—
—
—
10
10
—
—
—
—
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSHC_SCLK
MSHC_BS
5
—
—
8
Fall time
Setup time
Hold time
1
Setup time
Hold time
tDsu
8
MSHC_DATA
tDh
1
Output delay time
tDd
—
1
Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions
described in Table 8, "Operating Ranges," on page 13.
4.3.17 Personal Computer Memory Card International Association
(PCMCIA)
Figure 68 and Figure 69 depict the timings pertaining to the PCMCIA module, each of which is an
example of one clock of strobe set-up time and one clock of strobe hold time. Table 53 lists the timing
parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
84
Freescale Semiconductor
Electrical Characteristics
HCLK
HADDR
ADDR 1
CONTROL 1
CONTROL
HWDATA
HREADY
HRESP
DATA write 1
OKAY
OKAY
OKAY
ADDR 1
A[25:0]
DATA write 1
D[15:0]
WAIT
REG
REG
OE/WE/IORD/IOWR
CE1/CE2
RW
POE
PSHT
PSST
PSL
Figure 68. Write Accesses Timing Diagram—PSHT=1, PSST=1
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
85
Electrical Characteristics
HCLK
HADDR
ADDR 1
CONTROL 1
CONTROL
RWDATA
HREADY
HRESP
DATA read 1
OKAY
OKAY
OKAY
ADDR 1
A[25:0]
D[15:0]
WAIT
REG
REG
OE/WE/IORD/IOWR
CE1/CE2
RW
POE
PSST
PSHT
PSL
Figure 69. Read Accesses Timing Diagram—PSHT=1, PSST=1
Table 53. PCMCIA Write and Read Timing Parameters
Symbol
Parameter
Min
Max
Unit
PSHT
PSST
PSL
PCMCIA strobe hold time
0
1
1
63
63
clock
clock
clock
PCMCIA strobe set up time
PCMCIA strobe length
128
4.3.18 PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
86
Freescale Semiconductor
Electrical Characteristics
4.3.18.1 PWM Timing
Figure 70 depicts the timing of the PWM, and Table 54 lists the PWM timing characteristics.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 70. PWM Timing
Table 54. PWM Output Timing Parameters
ID
Parameter
Min
Max
Unit
1
1
System CLK frequency
Clock high time
Clock low time
0
12.29
9.91
—
ipg_clk
—
MHz
ns
2a
2b
3a
3b
4a
4b
—
ns
Clock fall time
0.5
ns
Clock rise time
—
0.5
ns
Output delay time
Output setup time
—
9.37
—
ns
8.71
ns
1
CL of PWMO = 30 pF
4.3.19 SDHC Electrical Specifications
This section describes the electrical information of the SDHC.
4.3.19.1 SDHC Timing
Figure 71 depicts the timings of the SDHC, and Table 55 lists the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
87
Electrical Characteristics
SD4
SD3
SD2
SD1
CLK
SD5
SD6
CMD
DATA[3:0]
Output from SDHC to card
Input to SDHC
SD7
CMD
DATA[3:0]
SD8
Figure 71. SDHC Timing Diagram
Table 55. SDHC Interface Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
Card Input Clock
1
SD1
Clock Frequency (Low Speed)
Clock Frequency (SD/SDIO Full Speed)
Clock Frequency (MMC Full Speed)
Clock Frequency (Identification Mode)
Clock Low Time
f
f
f
0
0
400
25
20
400
—
kHz
MHz
MHz
kHz
ns
PP
PP
PP
2
3
4
0
f
100
10
10
—
—
OD
SD2
SD3
SD4
SD5
t
WL
Clock High Time
t
—
ns
WH
Clock Rise Time
t
10
10
ns
TLH
THL
Clock Fall Time
t
ns
SDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6 SDHC output delay
SDHC Input/Card Outputs CMD, DAT (Reference to CLK)
t
–6.5
3
ns
ODL
SD7
SD8
SDHC input setup
SDHC input hold
t
—
—
18.5
ns
ns
IS
t
–11.5
IH
1
2
3
4
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 V–3.3 V.
In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 MHz–25 MHz.
In normal data transfer mode for MMC card, clock frequency can be any value between 0 MHz–20 MHz.
In card identification mode, card clock must be 100 kHz–400 kHz, voltage ranges from 2.7 V–3.3 V.
4.3.20 SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port
with 5 pins is used).
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
88
Freescale Semiconductor
Electrical Characteristics
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides
a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the
TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART.
All six (or 5 in case bi-directional TXRX is used) of the pins for each half of the SIM module are
asynchronous to each other.
There are no required timing relationships between the signals in normal mode, but there are some in two
specific cases: reset and power down sequences.
4.3.20.1 General Timing Requirements
Figure 72 shows the timing of the SIM module, and Figure 56 lists the timing parameters.
1/Sfreq
CLK
Sfall
Srise
Figure 72. SIM Clock Timing Diagram
Table 56. SIM Timing Specification—High Drive Strength
Num
Description
Symbol
Min
Max
Unit
1
1
SIM Clock Frequency (CLK)
S
0.01
5 (Some new cards
may reach 10)
MHz
freq
2
2
3
4
SIM CLK Rise Time
S
—
—
—
20
20
25
ns
ns
ns
rise
3
SIM CLK Fall Time
S
fall
SIM Input Transition Time (RX, SIMPD)
S
trans
1
2
3
50% duty cycle clock
With C = 50pF
With C = 50pF
4.3.20.2 Reset Sequence
4.3.20.2.1 Cards with Internal Reset
The sequence of reset for this kind of SIM Cards is as follows (see Figure 73):
•
•
•
After powerup, the clock signal is enabled on SGCLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40000 clock
cycles after T0.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
89
Electrical Characteristics
SVEN
CLK
response
RX
1
2
< 200 clock cycles
1
2
T0
400 clock cycles <
< 40000 clock cycles
Figure 73. Internal-Reset Card Reset Sequence
4.3.20.2.2 Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 74):
1. After powerup, the clock signal is enabled on CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on
RX during those 40000 clock cycles)
4. RST is set High (time T1)
5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received
on RX between 400 and 40000 clock cycles after T1.
SVEN
RST
CLK
response
RX
2
1
3
3
T0
T1
< 200 clock cycles
1
2
3
400 clock cycles <
< 40000 clock cycles
400000 clock cycles <
Figure 74. Active-Low-Reset Card Reset Sequence
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
90
Freescale Semiconductor
Electrical Characteristics
4.3.20.3 Power Down Sequence
Power down sequence for SIM interface is as follows:
1. SIMPD port detects the removal of the SIM Card
2. RST goes Low
3. CLK goes Low
4. TX goes Low
5. VEN goes Low
Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a
SIM Card removal detection or launched by the processor. Figure 75 and Table 57 show the usual timing
requirements for this sequence, with Fckil = CKIL frequency value.
Spd2rst
SIMPD
RST
Srst2clk
CLK
Srst2dat
DATA_TX
Srst2ven
SVEN
Figure 75. SmartCard Interface Power Down AC Timing
Table 57. Timing Requirements for Power Down Sequence
Num
Description
Symbol
Min
Max
Unit
1
2
3
4
SIM reset to SIM clock stop
S
0.9*1/FCKIL
1.8*1/FCKIL
2.7*1/FCKIL
0.9*1/FCKIL
0.8
1.2
1.8
25
µs
µs
µs
ns
rst2clk
rst2dat
rst2ven
SIM reset to SIM TX data low
S
SIM reset to SIM Voltage Enable Low
SIM Presence Detect to SIM reset Low
S
S
pd2rst
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
91
Electrical Characteristics
4.3.21 SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 76 depicts the SJC test clock
input timing. Figure 77 depicts the SJC boundary scan timing, Figure 78 depicts the SJC test access port,
Figure 79 depicts the SJC TRST timing, and Table 58 lists the SJC timing parameters.
SJ1
SJ2
VM
SJ2
VM
TCK
(Input)
VIH
VIL
SJ3
SJ3
Figure 76. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ5
SJ4
Input Data Valid
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 77. Boundary Scan (JTAG) Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
92
Freescale Semiconductor
Electrical Characteristics
TCK
(Input)
VIH
VIL
SJ8
SJ9
TDI
TMS
Input Data Valid
(Input)
SJ10
SJ11
SJ10
TDO
(Output)
Output Data Valid
TDO
(Output)
TDO
(Output)
Output Data Valid
Figure 78. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 79. TRST Timing Diagram
Table 58. SJC Timing Parameters
All Frequencies
ID
Parameter
Unit
Min
Max
1
SJ1 TCK cycle time
100
40
—
—
—
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
SJ2 TCK clock pulse width measured at VM
SJ3 TCK rise and fall times
SJ4 Boundary scan input data set-up time
SJ5 Boundary scan input data hold time
SJ6 TCK low to output data valid
SJ7 TCK low to output high impedance
SJ8 TMS, TDI data set-up time
10
50
—
—
—
50
50
—
—
44
—
10
50
—
SJ9 TMS, TDI data hold time
SJ10 TCK low to TDO data valid
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
93
Electrical Characteristics
Table 58. SJC Timing Parameters (continued)
Parameter
All Frequencies
Min Max
44
ID
Unit
SJ11 TCK low to TDO high impedance
SJ12 TRST assert time
—
ns
ns
ns
100
40
—
—
SJ13 TRST set-up time to TCK low
1
2
On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
VM - mid point voltage
4.3.22 SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
•
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
•
•
•
All timings are on AUDMUX signals when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.22.1 SSI Transmitter Timing with Internal Clock
Figure 80 depicts the SSI transmitter timing with internal clock, and Table 59 lists the timing parameters.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
94
Freescale Semiconductor
Electrical Characteristics
SS1
SS3
SS5
SS4
SS2
AD1_TXC
(Output)
SS8
SS6
AD1_TXFS (bl)
(Output)
SS10
SS12
AD1_TXFS (wl)
(Output)
SS14
SS17
SS15
SS16
SS18
AD1_TXD
(Output)
SS43
SS42
SS19
AD1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS1
SS3
SS5
SS4
SS2
DAM1_T_CLK
(Output)
SS8
SS6
DAM1_T_FS (bl)
(Output)
SS10
SS12
DAM1_T_FS (wl)
(Output)
SS14
SS17
SS15
SS18
SS16
DAM1_TXD
(Output)
SS43
SS42
SS19
DAM1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
Figure 80. SSI Transmitter with Internal Clock Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
95
Electrical Characteristics
Table 59. SSI Transmitter with Internal Clock Timing Parameters
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
SS2
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS3
(Tx/Rx) CK clock rise time
6
SS4
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
36.0
—
—
SS5
6
SS6
(Tx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
—
15.0
15.0
15.0
15.0
6
SS8
—
SS10
SS12
SS14
SS15
SS16
SS17
SS18
SS19
(Tx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
(Tx/Rx) Internal FS rise time
(Tx/Rx) Internal FS fall time
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
STXD rise/fall time
—
—
—
—
6
—
15.0
15.0
15.0
6
—
—
—
Synchronous Internal Clock Operation
SS42
SS43
SS52
SRXD setup before (Tx) CK falling
10.0
0
—
—
25
ns
ns
pF
SRXD hold after (Tx) CK falling
Loading
—
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
96
Freescale Semiconductor
Electrical Characteristics
4.3.22.2 SSI Receiver Timing with Internal Clock
Figure 81 depicts the SSI receiver timing with internal clock, and Table 60 lists the timing parameters.
SS1
SS3
SS5
SS4
SS2
AD1_TXC
(Output)
SS9
SS7
AD1_TXFS (bl)
(Output)
SS11
SS13
AD1_TXFS (wl)
(Output)
SS20
SS21
AD1_RXD
(Input)
SS51
SS50
SS47
SS49
SS48
AD1_RXC
(Output)
SS1
SS3
SS5
SS4
SS2
DAM1_T_CLK
(Output)
SS9
SS7
DAM1_T_FS (bl)
(Output)
SS11
SS13
DAM1_T_FS (wl)
(Output)
SS20
SS21
DAM1_RXD
(Input)
SS47
SS51
SS50
SS49
SS48
DAM1_R_CLK
(Output)
Figure 81. SSI Receiver with Internal Clock Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
97
Electrical Characteristics
Table 60. SSI Receiver with Internal Clock Timing Parameters
ID
Internal Clock Operation
Parameter
Min
Max
Unit
SS1
SS2
SS3
SS4
SS5
SS7
SS9
(Tx/Rx) CK clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
6
36.0
—
—
6
—
15.0
15.0
15.0
15.0
—
—
SS11 (Rx) CK high to FS (wl) high
SS13 (Rx) CK high to FS (wl) low
SS20 SRXD setup time before (Rx) CK low
SS21 SRXD hold time after (Rx) CK low
Oversampling Clock Operation
—
—
10.0
0
—
SS47 Oversampling clock period
SS48 Oversampling clock high period
SS49 Oversampling clock rise time
SS50 Oversampling clock low period
SS51 Oversampling clock fall time
15.04
6
—
—
3
ns
ns
ns
ns
ns
—
6
—
3
—
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
98
Freescale Semiconductor
Electrical Characteristics
4.3.22.3 SSI Transmitter Timing with External Clock
Figure 82 depicts the SSI transmitter timing with external clock, and Table 61 lists the timing parameters.
SS22
SS23
SS25
SS26
SS24
AD1_TXC
(Input)
SS27
SS29
AD1_TXFS (bl)
(Input)
SS33
SS31
AD1_TXFS (wl)
(Input)
SS39
SS37
SS38
AD1_TXD
(Output)
SS45
SS44
AD1_RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
SS22
SS26
SS25
SS24
SS23
DAM1_T_CLK
(Input)
SS29
SS27
DAM1_T_FS (bl)
(Input)
SS33
SS31
DAM1_T_FS (wl)
(Input)
SS39
SS37
SS38
DAM1_TXD
(Output)
SS45
SS44
DAM1_RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
Figure 82. SSI Transmitter with External Clock Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
99
Electrical Characteristics
Table 61. SSI Transmitter with External Clock Timing Parameters
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22 (Tx/Rx) CK clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS23 (Tx/Rx) CK clock high period
SS24 (Tx/Rx) CK clock rise time
6.0
—
SS25 (Tx/Rx) CK clock low period
SS26 (Tx/Rx) CK clock fall time
36.0
—
6.0
15.0
—
SS27 (Tx) CK high to FS (bl) high
SS29 (Tx) CK high to FS (bl) low
SS31 (Tx) CK high to FS (wl) high
SS33 (Tx) CK high to FS (wl) low
SS37 (Tx) CK high to STXD valid from high impedance
SS38 (Tx) CK high to STXD high/low
SS39 (Tx) CK high to STXD high impedance
Synchronous External Clock Operation
SS44 SRXD setup before (Tx) CK falling
SS45 SRXD hold after (Tx) CK falling
SS46 SRXD rise/fall time
–10.0
10.0
–10.0
10.0
—
15.0
—
15.0
15.0
15.0
—
—
10.0
2.0
—
—
—
ns
ns
ns
6.0
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
100
Freescale Semiconductor
Electrical Characteristics
4.3.22.4 SSI Receiver Timing with External Clock
Figure 83 depicts the SSI receiver timing with external clock, and Table 62 lists the timing parameters.
SS22
SS26
SS25
SS24
SS23
AD1_TXC
(Input)
SS30
SS28
AD1_TXFS (bl)
(Input)
SS32
SS35
SS34
AD1_TXFS (wl)
(Input)
SS41
SS36
SS40
AD1_RXD
(Input)
SS22
SS24
SS26
SS25
SS23
DAM1_T_CLK
(Input)
SS30
SS28
DAM1_T_FS (bl)
(Input)
SS32
SS35
SS34
DAM1_T_FS (wl)
(Input)
SS41
SS36
SS40
DAM1_RXD
(Input)
Figure 83. SSI Receiver with External Clock Timing Diagram
Table 62. SSI Receiver with External Clock Timing Parameters
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22 (Tx/Rx) CK clock period
SS23 (Tx/Rx) CK clock high period
SS24 (Tx/Rx) CK clock rise time
SS25 (Tx/Rx) CK clock low period
SS26 (Tx/Rx) CK clock fall time
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
6.0
—
36.0
—
6.0
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
101
Electrical Characteristics
Table 62. SSI Receiver with External Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS28 (Rx) CK high to FS (bl) high
SS30 (Rx) CK high to FS (bl) low
SS32 (Rx) CK high to FS (wl) high
SS34 (Rx) CK high to FS (wl) low
SS35 (Tx/Rx) External FS rise time
SS36 (Tx/Rx) External FS fall time
SS40 SRXD setup time before (Rx) CK low
SS41 SRXD hold time after (Rx) CK low
–10.0
10.0
–10.0
10.0
—
15.0
—
ns
ns
ns
ns
ns
ns
ns
ns
15.0
—
6.0
6.0
—
—
10.0
2.0
—
4.3.23 USB Electrical Specifications
This section describes the electrical information of the USBOTG port. The OTG port supports both serial
and parallel interfaces.
The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 84
depicts the USB ULPI timing diagram, and Table 63 lists the timing parameters.
Clock
TSC
THC
Control out (stp)
TSD
THD
Data out
TDC
TDC
Control in (dir, nxt)
TDD
Data in
Figure 84. USB ULPI Interface Timing Diagram
Table 63. USB ULPI Interface Timing Specification
1
Parameter
Symbol
Min
Max
Units
Setup time (control in, 8-bit data in)
Hold time (control in, 8-bit data in)
Output delay (control out, 8-bit data out)
TSC, TSD
THC, THD
TDC, TDD
6
0
—
—
9
ns
ns
ns
—
1
Timing parameters are given as viewed by transceiver side.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
102
Freescale Semiconductor
Package Information and Pinout
5 Package Information and Pinout
This section includes the contact assignment information and mechanical package drawing for the
MCIMX31.
5.1
MAPBGA Production Package—457 14 x 14 mm, 0.5 mm Pitch
This section contains the outline drawing, signal assignment map (see Section 7, “Revision History,”
Table 69 for the 0.5 mm 14 × 14 MAPBGA signal assignments), and MAPBGA ground/power ID by ball
grid location for the 457 14 x 14 mm, 0.5 mm pitch package.
5.1.1
Production Package Outline Drawing–14 x 14 mm 0.5 mm
Figure 85. Production Package: Case 1581—0.5 mm Pitch
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
103
Package Information and Pinout
5.1.2
MAPBGA Signal Assignment–14 × 14 mm 0.5 mm
See Section 7, “Revision History,” Figure 69 for the 0.5 mm 14 × 14 MAPBGA signal assignments.
5.1.3
Connection Tables–14 x 14 mm 0.5 mm
Table 64 shows the device connection list for power and ground, alpha-sorted. Table 65 shows the device
connection list for signals.
5.1.3.1
Ground and Power ID Locations–14 x 14 mm 0.5 mm
Table 64. 14 x 14 MAPBGA Ground/Power ID by Ball Grid Location
GND/PWR ID
Ball Location
FGND
AB24
FUSE_VDD AC24
FVCC
GND
AA24
A1, A2, A25, A26, B1, B2, B25, B26, C1, C2, C24, C25, C26, D1, D25, E22, E24, F21, L12, M11, M12, M13, M14,
M15, M16, N12, N13, N14, N15, N16, P12, P13, P14, P15, P16, R12, R13, R14, R15, R16, T12, T13, V17, AC2,
AC26, AD1, AD2, AD24, AD25, AD26, AE1, AE2, AE24, AE25, AE26, AF1, AF2, AF25, AF26
IOQVDD
MGND
MVCC
Y6
T15
V15
NVCC1
NVCC2
NVCC3
NVCC4
NVCC5
NVCC6
NVCC7
NVCC8
NVCC9
NVCC10
NVCC21
NVCC22
QVCC
G19, G21, K18
Y17, Y18, Y19, Y20
L9, M9, N11
L18, L19
E5, F6, G7
J15, J16, K15
N18, P18, R18, T18
J12, J13
J17
P9, P11, R11, T11
Y14, Y15, Y16
W7, Y7, Y8, Y9, Y10, Y11, Y12, Y13, AA6
J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13
QVCC1
QVCC4
SGND
J10, J11, K9, L11
N9, R9, T9, U9
T14
V14
V16
T16
SVCC
UVCC
UGND
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
104
Freescale Semiconductor
Package Information and Pinout
5.1.3.2
BGA Signal ID by Ball Grid Location–14 x 14 0.5 mm
Table 65 shows the device connection list for signals only, alpha-sorted by signal identification.
Table 65. 14 x 14 BGA Signal ID by Ball Grid Location
Signal ID
Ball Location
Signal ID
Ball Location
A0
AD6
AF5
AF18
AC3
AD3
AD4
AF17
AF16
AF15
AF14
AF13
AF12
AB5
AF11
AF10
AF9
AF8
AF7
AF6
AE4
AA3
AF4
AB3
AE3
AD5
AF3
J6
CKIL
CLKO
H21
C23
G26
G18
R24
AE23
AF23
AE21
AD22
AF24
AF22
M24
L26
M21
M25
M20
M26
L21
K25
L24
K26
L20
L25
K20
K24
J26
J25
P7
A1
A10
CLKSS
A11
COMPARE
CONTRAST
CS0
A12
A13
A14
CS1
A15
CS2
A16
CS3
A17
CS4
A18
CS5
A19
CSI_D10
A2
CSI_D11
A20
CSI_D12
A21
CSI_D13
A22
CSI_D14
A23
CSI_D15
A24
CSI_D4
A25
CSI_D5
A3
CSI_D6
A4
CSI_D7
A5
CSI_D8
A6
CSI_D9
A7
CSI_HSYNC
CSI_MCLK
CSI_PIXCLK
CSI_VSYNC
CSPI1_MISO
CSPI1_MOSI
CSPI1_SCLK
CSPI1_SPI_RDY
CSPI1_SS0
CSPI1_SS1
CSPI1_SS2
CSPI2_MISO
CSPI2_MOSI
CSPI2_SCLK
CSPI2_SPI_RDY
CSPI2_SS0
CSPI2_SS1
CSPI2_SS2
CSPI3_MISO
CSPI3_MOSI
A8
A9
ATA_CS0
ATA_CS1
ATA_DIOR
ATA_DIOW
ATA_DMACK
ATA_RESET
BATT_LINE
BCLK
F2
E2
P2
H6
N2
F1
N3
H3
P3
F7
P1
AB26
F20
C21
D24
C22
D26
A22
AD20
A14
F24
P6
BOOT_MODE0
BOOT_MODE1
BOOT_MODE2
BOOT_MODE3
BOOT_MODE4
CAPTURE
CAS
A4
E3
C7
B6
B5
C6
A5
CE_CONTROL
CKIH
G3
D2
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
105
Package Information and Pinout
Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
CSPI3_SCLK
CSPI3_SPI_RDY
CTS1
E1
G6
GPIO1_3
GPIO1_4
GPIO1_5 (PWR RDY)
GPIO1_6
GPIO3_0
GPIO3_1
HSYNC
F25
F19
B24
A23
K21
H26
N25
J24
B11
G13
AB2
Y3
CTS2
D0
D1
D10
Y1
D11
U7
I2C_CLK
I2C_DAT
IOIS16
D12
W2
H25
J3
D13
V3
D14
W1
KEY_COL0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_COL5
KEY_COL6
KEY_COL7
KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW3
KEY_ROW4
KEY_ROW5
KEY_ROW6
KEY_ROW7
L2PG
C15
B17
G15
A17
C16
B18
F15
D15
U6
D2
AB1
W6
D3
D3_CLS
D3_REV
D3_SPL
D4
R20
T26
U25
AA2
V7
A18
F13
D5
D6
AA1
W3
B15
C14
A15
G14
B16
F14
D7
D8
Y2
D9
V6
DCD_DCE1
DCD_DTE1
DE
B12
B13
C18
AE19
AD19
AA20
AE18
N26
A11
A12
C11
F12
C12
E25
G24
W21
Y24
AD23
N21
F18
B23
C20
W25
A16
See VPG1
AE22
P26
P21
T24
DQM0
DQM1
DQM2
DQM3
DRDY0
DSR_DCE1
DSR_DTE1
DTR_DCE1
DTR_DCE2
DTR_DTE1
DVFS0
DVFS1
EB0
LBA
LCS0
LCS1
LD0
LD1
U26
V24
Y25
Y26
V21
AA25
W24
AA26
V20
T21
LD10
LD11
LD12
LD13
LD14
LD15
LD16
EB1
LD17
ECB
LD2
FPSHIFT
GPIO1_0
GPIO1_1
GPIO1_2
LD7
LD3
V25
T20
V26
U24
T2
LD4
LD5
LD6
SCK6
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
106
Freescale Semiconductor
Package Information and Pinout
Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
LD8
LD9
U21
W26
Y21
AC25
AC1
See VPG0
V1
SCLK0
SD_D_CLK
SD_D_I
SD_D_IO
SD0
B22
P24
M_GRANT
M_REQUEST
MA10
N20
P25
AD18
AE17
M7
MCUPG
NFALE
SD1
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD10
NFCE
T6
L2
NFCLE
NFRB
U3
M6
U1
L1
NFRE
V2
L3
NFWE
T7
K2
NFWP
U2
AE15
AE14
AD14
AA14
AE13
AD13
AA13
AD12
AA12
AE11
AA19
AE10
AA11
AE9
OE
AB25
R21
H2
SD11
PAR_RS
PC_BVD1
PC_BVD2
PC_CD1
PC_CD2
PC_POE
PC_PWRON
PC_READY
PC_RST
PC_RW
PC_VS1
PC_VS2
PC_WAIT
POR
SD12
SD13
K6
SD14
L7
SD15
K1
SD16
J7
SD17
K3
SD18
J2
SD19
H1
SD2
G2
SD20
J1
SD21
K7
SD22
L6
SD23
AA10
AE8
H24
E26
G1
SD24
POWER_FAIL
PWMO
RAS
SD25
AD10
AE7
SD26
AF19
P20
J21
F11
G12
C17
G11
B14
AB22
A10
A13
R2
SD27
AA9
READ
SD28
AA8
RESET_IN
RI_DCE1
RI_DTE1
RTCK
SD29
AD9
AA18
AE6
SD3
SD30
SD31
AA7
RTS1
SD4
AD17
AA17
AE16
AA16
AD15
AA15
AD7
AE5
RTS2
SD5
RW
SD6
RXD1
SD7
RXD2
SD8
SCK3
SD9
SCK4
C4
SDBA0
SDBA1
TRSTB
TTM_PAD
SCK5
D3
SDCKE0
SDCKE1
AD21
AF21
B20
U20
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
107
Package Information and Pinout
Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
SDCLK
SDCLK
SDQS0
SDQS1
SDQS2
SDQS3
SDWE
SER_RS
SFS3
AA21
AE20
AD16
AE12
AD11
AD8
AF20
T25
R6
TXD1
TXD2
F10
C13
A9
USB_BYP
USB_OC
C10
B10
N1
USB_PWR
USBH2_CLK
USBH2_DATA0
USBH2_DATA1
USBH2_DIR
USBH2_NXT
USBH2_STP
USBOTG_CLK
USBOTG_DATA0
USBOTG_DATA1
USBOTG_DATA2
USBOTG_DATA3
USBOTG_DATA4
USBOTG_DATA5
USBOTG_DATA6
USBOTG_DATA7
USBOTG_DIR
USBOTG_NXT
USBOTG_STP
VPG0
M1
M3
N7
SFS4
F3
N6
SFS5
A3
M2
G10
F9
SFS6
T3
SIMPD0
SJC_MOD
SRST0
SRX0
G17
A20
C19
B21
R3
B8
G9
A7
SRXD3
SRXD4
SRXD5
SRXD6
STX0
C8
C3
B7
B4
F8
R7
A6
F17
R1
B9
STXD3
STXD4
STXD5
STXD6
SVEN0
TCK
A8
B3
C9
C5
G25
J20
F26
N24
R26
A24
R25
T1
VPG1
A21
B19
F16
A19
G16
VSTBY
VSYNC0
TDI
VSYNC3
TDO
WATCHDOG_RST
WRITE
TMS
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
108
Freescale Semiconductor
Package Information and Pinout
5.2
MAPBGA Production Package—473 19 x 19 mm, 0.8 mm Pitch
This section contains the outline drawing, signal assignment map (see Section 7, “Revision History,”
Table 70 for the 19 x 19 mm, 0.8 mm pitch signal assignments), and MAPBGA ground/power ID by ball
grid location for the 473 19 x 19 mm, 0.8 mm pitch package.
5.2.1
Production Package Outline Drawing–19 x 19 mm 0.8 mm
Figure 86. Production Package: Case 1931—0.8 mm Pitch
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
109
Package Information and Pinout
5.2.2
MAPBGA Signal Assignment–19 × 19 mm 0.8 mm
See Table 70 for the 19 × 19 mm, 0.8 mm pitch signal assignments/ball map.
5.2.3
Connection Tables–19 x 19 mm 0.8 mm
Table 66 shows the device connection list for power and ground, alpha-sorted followed by Table 67, which
shows the no-connects. Table 68 shows the device connection list for signals.
5.2.3.1
Ground and Power ID Locations—19 x 19 mm 0.8 mm
Table 66. 19 x 19 BGA Ground/Power ID by Ball Grid Location
GND/PWR ID
Ball Location
FGND
U16
FUSE_VDD T15
FVCC
GND
T16
A1, A2, A3, A21, A22, A23, B1, B2, B22, B23, C1, C2, C22, C23, D22, D23, J12, J13, K10, K11, K12, K13, K14,
L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N10, N11, N12, N13, N14, P10, P11, P12, P13, P14,
R12, Y1, Y23, AA1, AA2, AA22, AA23, AB1, AB2, AB21, AB22, AB23, AC1, AC2, AC21, AC22, AC23
IOQVDD
MGND
MVCC
T8
U14
U15
NVCC1
NVCC2
NVCC3
NVCC4
NVCC5
NVCC6
NVCC7
NVCC8
NVCC9
NVCC10
NVCC21
NVCC22
QVCC
G15, G16, H16, J17
N16, P16, R15, R16, T14
K7, K8, L7, L8
H14, J15, K15
G9, G10, H8, H9
G11, G12, G13, H12
H15, J16, K16, L16, M16
H10, H11, J11
G14
P8, R7, R8, R9, T9
T11, T12, T13, U11
T10, U7, U8, U9, U10, V6, V7, V8, V9, V10
H13, J14, L15, M15, N9, N15, P9, P15, R10, R11, R13, R14
QVCC1
QVCC4
SGND
J8, J9, J10, K9
L9, M7, M8, N8
U13
U12
P18
P17
SVCC
UVCC
UGND
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
110
Freescale Semiconductor
Package Information and Pinout
1
Table 67. 19 x 19 BGA No Connects
Signal
Ball Location
NC
NC
NC
N7
P7
U21
1
These contacts are not used and must be floated by the user.
5.2.3.2
BGA Signal ID by Ball Grid Location—19 x 19 0.8 mm
Table 68. 19 x 19 BGA Signal ID by Ball Grid Location
Signal ID
Ball Location
Signal ID
Ball Location
A0
A1
Y6
AC5
V15
AB3
AA3
Y3
CKIL
CLKO
E21
C20
H17
A20
N21
U17
Y22
Y18
Y19
Y20
AA21
K21
K22
K23
L20
L18
L21
J20
J21
L17
J22
J23
K20
H22
H20
H23
H21
N2
A10
CLKSS
A11
COMPARE
CONTRAST
CS0
A12
A13
A14
Y15
Y14
V14
Y13
V13
Y12
AB5
V12
Y11
V11
Y10
Y9
CS1
A15
CS2
A16
CS3
A17
CS4
A18
CS5
A19
CSI_D10
CSI_D11
CSI_D12
CSI_D13
CSI_D14
CSI_D15
CSI_D4
A2
A20
A21
A22
A23
A24
A25
Y8
CSI_D5
A3
AA5
Y5
CSI_D6
A4
CSI_D7
A5
AC4
AB4
AA4
Y4
CSI_D8
A6
CSI_D9
A7
CSI_HSYNC
CSI_MCLK
CSI_PIXCLK
CSI_VSYNC
CSPI1_MISO
CSPI1_MOSI
CSPI1_SCLK
CSPI1_SPI_RDY
CSPI1_SS0
CSPI1_SS1
CSPI1_SS2
A8
A9
AC3
E1
ATA_CS0
ATA_CS1
ATA_DIOR
ATA_DIOW
ATA_DMACK
ATA_RESET
BATT_LINE
BCLK
G4
E3
N1
H6
M4
E2
M1
F3
M2
F6
N6
W20
M3
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
111
Package Information and Pinout
Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
BOOT_MODE0
BOOT_MODE1
BOOT_MODE2
BOOT_MODE3
BOOT_MODE4
CAPTURE
CAS
F17
C21
D20
F18
E20
D18
AA20
D12
F23
H7
CSPI2_MISO
CSPI2_MOSI
CSPI2_SCLK
CSPI2_SPI_RDY
CSPI2_SS0
CSPI2_SS1
CSPI2_SS2
CSPI3_MISO
CSPI3_MOSI
GPIO1_3
B4
D5
B5
D6
C5
A4
F7
CE_CONTROL
CKIH
D2
E4
CSPI3_SCLK
CSPI3_SPI_RDY
CTS1
G20
D21
D19
G18
G23
K17
L23
J18
F4
GPIO1_4
A9
GPIO1_5 (PWR RDY)
GPIO1_6
CTS2
C12
U6
D0
GPIO3_0
D1
W4
V1
GPIO3_1
D10
HSYNC
D11
U4
I2C_CLK
D12
U3
I2C_DAT
K18
J7
D13
R6
IOIS16
D14
U2
KEY_COL0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_COL5
KEY_COL6
KEY_COL7
KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW3
KEY_ROW4
KEY_ROW5
KEY_ROW6
KEY_ROW7
L2PG
A15
B15
D14
C15
F13
A16
B16
A17
A13
B13
C13
A14
F12
D13
B14
C14
See VPG1
V17
M22
N23
R23
R22
U22
R18
U20
V23
V22
D15
U1
D2
W3
V4
D3
D3_CLS
D3_REV
D3_SPL
D4
P20
P21
N17
T7
D5
W2
V3
D6
D7
W1
T6
D8
D9
V2
DCD_DCE1
DCD_DTE1
DE
C10
D11
D16
AB19
Y16
AA18
AB18
M17
B10
A11
F10
C11
A10
E22
DQM0
DQM1
LBA
DQM2
LCS0
DQM3
LCS1
DRDY0
DSR_DCE1
DSR_DTE1
DTR_DCE1
DTR_DCE2
DTR_DTE1
DVFS0
LD0
LD1
LD10
LD11
LD12
LD13
LD14
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
112
Freescale Semiconductor
Package Information and Pinout
Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
DVFS1
EB0
E23
W22
W21
Y21
M23
C19
G17
B20
T20
R17
U23
U18
T17
Y2
LD15
LD16
V21
V20
EB1
LD17
W23
R21
R20
T23
ECB
LD2
FPSHIFT
GPIO1_0
GPIO1_1
GPIO1_2
LD7
LD3
LD4
LD5
T22
LD6
T21
SCK6
R2
LD8
SCLK0
SD_D_CLK
SD_D_I
SD_D_IO
SD0
B19
LD9
M21
M20
M18
AC18
AA17
K2
M_GRANT
M_REQUEST
MA10
MCUPG
NFALE
See VPG0
T2
SD1
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD10
NFCE
R4
K3
NFCLE
NFRB
T1
K4
R3
J1
NFRE
T4
J2
NFWE
T3
L6
NFWP
P6
AB14
AC14
AA13
AB13
AC13
AA12
AC12
AA11
AB11
AC11
AB17
AA10
AB10
AC10
AC9
AA9
AC8
AB8
AC7
AA8
AB7
AC17
AA7
AC6
AA16
OE
T18
P22
G2
SD11
PAR_RS
PC_BVD1
PC_BVD2
PC_CD1
PC_CD2
PC_POE
PC_PWRON
PC_READY
PC_RST
PC_RW
PC_VS1
PC_VS2
PC_WAIT
POR
SD12
SD13
H4
SD14
J3
SD15
H1
SD16
J6
SD17
K6
SD18
H2
SD19
F1
SD2
G3
SD20
H3
SD21
G1
SD22
J4
SD23
F21
F20
F2
SD24
POWER_FAIL
PWMO
SD25
SD26
RAS
AA19
N18
F22
D10
B11
D15
B9
SD27
READ
SD28
RESET_IN
RI_DCE1
RI_DTE1
RTCK
SD29
SD3
SD30
SD31
RTS1
SD4
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
113
Package Information and Pinout
Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)
Signal ID
Ball Location
Signal ID
Ball Location
RTS2
RW
B12
V18
C9
SD5
SD6
AC16
AA15
AB15
AC15
AA14
AA6
Y7
RXD1
SD7
RXD2
A12
P1
SD8
SCK3
SD9
SCK4
G6
SDBA0
SCK5
D4
SDBA1
SDCKE0
SDCKE1
SDCLK
SDCLK
SDQS0
SDQS1
SDQS2
SDQS3
SDWE
SER_RS
SFS3
Y17
V16
AC20
AC19
AB16
AB12
AB9
AB6
AB20
P23
P2
TRSTB
F15
D9
TXD1
TXD2
F11
C8
USB_BYP
USB_OC
B8
USB_PWR
USBH2_CLK
USBH2_DATA0
USBH2_DATA1
USBH2_DIR
USBH2_NXT
USBH2_STP
USBOTG_CLK
USBOTG_DATA0
USBOTG_DATA1
USBOTG_DATA2
USBOTG_DATA3
USBOTG_DATA4
USBOTG_DATA5
USBOTG_DATA6
USBOTG_DATA7
USBOTG_DIR
USBOTG_NXT
USBOTG_STP
VPG0
A8
L1
M6
K1
L2
L4
SFS4
D3
L3
SFS5
G7
D8
SFS6
P4
G8
SIMPD0
SJC_MOD
SRST0
SRX0
B18
C17
C18
A19
N3
C7
A6
F8
D7
SRXD3
SRXD4
SRXD5
SRXD6
STX0
B6
C3
A5
C4
C6
R1
A7
F16
N4
B7
STXD3
STXD4
STXD5
STXD6
SVEN0
TCK
F9
B3
G21
G22
H18
L22
N20
B21
N22
D1
VPG1
P3
VSTBY
D17
F14
A18
B17
C16
VSYNC0
VSYNC3
TDI
WATCHDOG_RST
WRITE
TDO
TMS
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
114
Freescale Semiconductor
5.3
Ball Maps
Table 69. Ball Map—14 x 14 0.5 mm Pitch
1
2
3
4
5
6
7
8
9
10
SFS5 CSPI2 CSPI2_ USBOT USBOT USBOT USB_ RXD1 DSR_D DSR_D RXD2 CE_CO KEY_R KEY_R KEY_C KEY_C TDO
_MISO SS2 G_DAT G_DAT G_NXT BYP CE1 TE1 NTROL OW3 OW7 OL3 OL7
A7 A3
STXD4 SRXD CSPI2_ CSPI2_ USBOT USBOT USBOT USB_P CTS1 DCD_D DCD_D RTS2 KEY_R KEY_R KEY_C KEY_C TCK
SS0 SPI_R G_DAT G_DAT G_DIR WR CE1 TE1 OW1 OW5 OL1 OL5
DY A5 A1
SRXD4 SCK4 STXD5 CSPI2_ CSPI2_ USBOT USBOT USB_O DTR_D DTR_D TXD2 KEY_R KEY_C KEY_C RTCK DE
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
C
GND
GND
GND
GND
GND
SJC_M SVEN0 CAPTU GPIO1_ WATCH GND
OD
GND
A
B
C
RE
6
DOG_R
ST
GND
GND
TRSTB SRX0
SCLK0 GPIO1_ GPIO1_ GND
GND
GND
5
1
5
SRST0 GPIO1 BOOT_ BOOT_ CLKO
GND
GND
SS1
SCLK G_DAT G_STP C
A4
CE1
TE1
OW2
OL0
OL4
_2
MODE1 MODE3
D
E
F
CSPI3_ SCK5
MOSI
BOOT_ GND
MODE2
BOOT_
MODE4
D
E
F
CSPI3_ ATA_DI CSPI2_
SCLK OR MOSI
NVCC5
GND
GND
DVFS0 POWER
_FAIL
ATA_D ATA_C SFS4
MACK S1
NVCC5 BATT_L USBOT USBOT TXD1 RI_DC DTR_D KEY_R KEY_R KEY_C TDI
STX0 GPIO1 GPIO1 BOOT_ GND
CKIH
GPIO1_ VSTBY
3
INE
G_DAT G_DAT
A6 A0
USBOT USBOT RTS1 RI_DT CTS2 KEY_R KEY_C TMS
E1
CE2
OW0
OW6
OL6
_0
_4
MODE
0
PC_RW
G
PWMO
CSPI3_
MISO
CSPI3_ NVCC5
SIMPD COMP NVCC1
NVCC1
CKIL
DVFS1 VPG0
CLKSS
G
SPI_R
DY
G_DAT G_CLK
A2
E1
OW4
OL2
0
ARE
H
J
PC_RS PC_BV ATA_R
ATA_DI
OW
POR
I2C_DA GPIO3_
H
J
T
D1
PC_VS PC_RE
ADY
PC_CD SD1_D PC_PW
ATA3 RON
SD1_D SD1_C SD1_D
ATA1 MD ATA2
ESET
IOIS16
T
1
ATA_C PC_PO
QVCC1 QVCC1 NVCC8 NVCC8 QVCC NVCC6 NVCC6 NVCC9
NVCC6
VPG1 RESET_
IN
I2C_CL CSI_VS CSI_PIX
K YNC CLK
1
S0
PC_BV PC_VS
D2
PC_WA PC_CD
IT
SD1_D SD1_C
ATA0 LK
E
K
L
QVCC1
NVCC3
NVCC3
QVCC4
NVCC1
CSI_H GPIO3_
CSI_MC CSI_D5 CSI_D7
LK
K
L
2
2
SYNC
0
QVCC1 GND
GND GND
QVCC QVCC QVCC QVCC
NVCC4 NVCC4 CSI_D8 CSI_D4
CSI_D6 CSI_D9 CSI_D1
1
1
M
N
USBH2 USBH2 USBH2
_DATA0 _STP _DATA1
GND
GND
GND
GND
GND
GND
GND
GND
QVCC
CSI_D1 CSI_D1
CSI_D1 CSI_D1 CSI_D1
0
M
N
4
2
3
5
USBH2 CSPI1_ CSPI1_
_CLK SCLK SPI_RD
Y
USBH2 USBH2
_NXT _DIR
NVCC3 GND
NVCC7
SD_D_I FPSHIF
T
VSYNC HSYNC DRDY0
0
P
R
T
CSPI1_ CSPI1_ CSPI1_
CSPI1_ CSPI1_
NVCC1
0
NVCC1 GND
0
GND
GND
GND
GND
GND
GND
GND
GND
GND
NVCC7
NVCC7
NVCC7
QVCC
READ LCS1
SD_D_ SD_D_I LCS0
P
R
T
SS1
MOSI SS0
SS2
MISO
CLK
O
STXD3 SCK3 SRXD3
STXD6 SCK6 SFS6
NFRB NFWP NFCLE
NFALE NFRE D13
SFS3 SRXD6
QVCC4
QVCC4
QVCC4
NVCC1 GND
0
D3_CL PAR_RS
S
CONTR WRITE VSYNC
AST
LD0
3
NFCE NFWE
NVCC1 GND
0
SGND MGND UGND
LD4
LD2
SER_R D3_REV
S
U
D15
D11
D5
TTM_P LD8
AD
LD6
D3_SPL LD1
U
V
D9
D3
QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND
LD17 LD13
EB0
LD10
LD15
LD3
LD7
LD5
LD9
V
W
D14
D12
D7
D1
A4
NVCC2
2
W
Y
D10
D8
IOQVD NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 M_GRA
EB1
LD11
LD14
LD12
LD16
BCLK
Y
D
2
2
2
2
2
2
2
1
1
1
NT
AA D6
D4
NVCC2 SD31 SD28 SD27 SD23 SD21 SD18 SD16 SD13 SD9
2
SD7
SD5
SD3
SD2
DQM2 SDCLK
FVCC
AA
AB D2
D0
A6
A2
A8
RW
FGND OE
AB
AC
AC MA10 GND
A11
FUSE_V M_REQ GND
DD
UEST
AD GND
GND
A12
A13
A0
SDBA0 SDQS3 SD29 SD25 SDQS2 SD17 SD15 SD12 SD8
SDQS0 SD4
SD0
DQM1 CAS
SDCKE CS3
0
ECB
GND
GND
GND
AD
AE GND
AF GND
GND
GND
A7
A9
A3
A5
SDBA1 SD30 SD26 SD24 SD22 SD20 SD19 SDQS1 SD14 SD11 SD10 SD6
A1 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15
SD1
A14
DQM3 DQM0 SDCLK CS2
LBA
CS0
CS1
GND
CS4
GND
GND
GND
GND
AE
AF
A10
RAS
SDWE SDCKE CS5
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 70. Ball Map—19 x 19 0.8 mm Pitch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CSPI2_ USBOTG_ USBOTG USBOTG
SS1 DATA6 _DATA2 _DIR
USB_
PWR
DTR_
DTE1
DSR_
DTE1
KEY_
KEY_
KEY_
COL0
KEY_
COL5
KEY_
COL7
COMPARE
A
B
C
D
E
F
GND
GND
GND
CTS1
RXD2
TDI
SRX0
GND
GND
GND
A
B
C
D
E
F
ROW0 ROW3
KEY_ KEY_
ROW1 ROW6
KEY_ KEY_
ROW2 ROW7
KEY_ KEY_
CSPI2_ CSPI2_ USBOTG_ USBOTG_ USB_
DSR_
DCE1
RI_
DTE1
KEY_
COL1
KEY_
COL6
WATCH
DOG_RST
GND
GND
GND
GND
STXD4
RTS1
RXD1
TXD1
RTS2
TDO
SIMPD0 SCLK0 GPIO1_2
GPIO1
GND
GND
GND
GND
GND
GND
MISO
SCLK
CSPI2_ USBOTG_ USBOTG_ USB_
SS0 DATA7 DATA1 BYP
CSPI2_ CSPI2_SPI USBOTG_ USBOTG_
DATA5
NXT
OC
DCD_
DCE1
DTR_
DCE2
KEY_
COL3
SJC_
MOD
BOOT_
MODE1
SRXD4 SRXD5
CTS2
CE_
TMS
DE
SRST0
CLKO
_0
CSPI3_
MISO
RI_
DCE1
DCD_
GPIO1 BOOT_
STXD5
SFS4
SCK5
RTCK
SVEN0 CAPTURE
GPIO1_4
CKIL
MOSI
_RDY
DATA4
CLK
DTE1 CONTROL ROW5 COL2
_5
MODE2
ATA_
CS0
ATA_
DMACK DIOR
ATA_ CSPI3_
MOSI
BOOT_
MODE4
DVFS0 DVFS1
PC_
RST
ATA_ CSPI3_
RESET SPI_RDY
BATT_
LINE
CSPI2_ USBOTG_ USBOT DTR_
SS2
KEY_
ROW4
KEY_
COL4
BOOT_
MODE0
BOOT_
MODE3
POWER_
FAIL
RESET_
CKIH
IN
PWMO
TXD2
TCK
TRSTB STX0
POR
DATA3 G_STP DCE1
PC_
BVD1
PC_
RW
ATA_
CS1
USBOTG_
DATA0
G PC_VS2
H PC_CD2
SCK4
SFS5
NVCC5 NVCC5 NVCC6 NVCC6 NVCC6 NVCC9 NVCC1 NVCC1 GPIO1_1 GPIO1_6
GPIO1_3 VPG0
VPG1 GPIO3_0 G
PC_
READY
PC_
VS1
PC_
BVD2
ATA_
DIOW
CSPI3_
SCLK
CSI_
CSI_
CSI_HSY CSI_PIX
NVCC5 NVCC5 NVCC8 NVCC8 NVCC6
QVCC NVCC4 NVCC7 NVCC1 CLKSS
VSTBY
H
MCLK
VSYNC
NC
CLK
SD1_
DATA1 DATA2
SD1_
PC_
CD1
PC_
WAIT
I2C_
CLK
J
PC_POE IOIS16
QVCC1 QVCC1 QVCC1 NVCC8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
QVCC NVCC4 NVCC7 NVCC1
CSI_D4 CSI_D5 CSI_D7 CSI_D8
J
K
L
USBH2_ SD1_
DATA1
SD1_
CMD
SD1_
DATA0
PC_
I2C_
DAT
CSI_
D10
CSI_
D11
CSI_
D12
K
L
NVCC3
PWRON
NVCC3 QVCC1 GND
NVCC3 QVCC4 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NVCC4 NVCC7 GPIO3_1
QVCC NVCC7 CSI_D6
QVCC NVCC7 DRDY0
CSI_D9
CLK
USBH2_ USBH2_ USBH2_ USBH2_
CLK DIR STP NXT
SD1_
CSI_
D14
NVCC3
DATA3
CSI_D13 CSI_D15 VSYNC0 HSYNC
CSPI1_S CSPI1_ CSPI1_ CSPI1_
PI_RDY
USBH2_
QVCC4
DATA0
SD_D_
IO
SD_D_
CLK
M
N
P
R
T
QVCC4
GND
GND
SD_D_I
VSYNC3
D3_CLS
LD3
LCS0 FPSHIFT M
SS0
SS2
SCLK
CSPI1_ CSPI1_
CSPI1_
SS1
D3_
QVCC NVCC2
SPL
1
CONTRAST
SRXD3 STXD3
QVCC4 QVCC GND
READ
UVCC
LD11
OE
WRITE LCS1
N
P
R
T
NC
MOSI
SCK3
MISO
SFS3 STXD6 SFS6
D3_
REV
PAR_
RS
SER_
RS
1
NFWP
D13
D8
NVCC10 QVCC GND
NVCC1
QVCC NVCC2
UGND
LD8
NC
SRXD6 SCK6
NFRB
NFCE
NVCC10 NVCC10
QVCC QVCC
QVCC QVCC NVCC2 NVCC2
FUSE_
LD2
LD6
NC
LD1
LD5
LD0
LD4
0
NVCC1
0
M_
REQUEST
NFCLE NFALE NFWE NFRE
D4
IOQVDD
NVCC22 NVCC21 NVCC21 NVCC21 NVCC2
FVCC
LD7
VDD
NVCC2
2
M_
GRANT
U
V
W
Y
D15
D10
D7
D14
D9
D12
D6
D11
D3
D1
A8
A7
A6
D0
NVCC22 NVCC22
NVCC22 NVCC21 SVCC
SGND MGND MVCC FGND
CS0
LBA
LD12
LD10
LD14
EB0
LD9
U
V
W
Y
NVCC2
2
NVCC22 NVCC22 NVCC22
NVCC22 A22
A20
A18
A16
A10 SDCKE1
RW
LD16
LD15
EB1
ECB
CS5
GND
LD13
LD17
GND
D5
D2
BCLK
CS4
GND
MA10
GND
GND
A13
A12
A11
A4
A3
A2
A0
SDBA1
SD30
A25
A24
A23
A21
A19
SD15
A17
A15
SD9
A14
SD6
SD7
DQM1 SDCKE0
CS2
CS3
RAS
CS1
AA GND
AB GND
AC GND
SDBA0
SDQS3
SD28
SD26
SD24
SD20
SD17
SD18
SD12
SD13
SD4
SD1
SD2
DQM2
CAS
GND
GND
GND AA
GND AB
SD29
SDQS2 SD21
SDQS1
SD10
SDQS0
DQM3 DQM0 SDWE
GND
A9
A5
A1
SD31
SD27
SD25
SD23
SD22
SD19
SD16
SD14
SD11
SD8
SD5
SD3
SD0
SDCLK SDCLK
19 20
GND
GND
GND AC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
21
22
23
1
These contacts are not used and must be floated by the user.
Product Documentation
6 Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data.
Definitions of these types are available at: http://www.freescale.com.
MCIMX31 Product Brief (order number MCIMX31PB)
MCIMX31 Reference Manual (order number MCIMX31RM)
MCIMX31 Chip Errata (order number MCIMX31CE)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com.
7 Revision History
Table 71 summarizes revisions to this document since the release of Rev. 4.1.
Table 71. Revision History
Rev.
Location
Revision
4.3 Table 1, "Ordering Information," on page 3 Added a footnote and new part numbers for silicon revision 2.0.1.
4.2 Global Replaced all references to silicon 2.0 with silicon revision 2.0.1.
4.2 Table 1, "Ordering Information," on page 3 Added new part numbers for revision 2.0.1.
4.2 Section 1.2.1, “Feature Differences
Between Mask Sets
Updated for revision 2.0.1.
4.2 Table 8, "Operating Ranges," on page 13 Updated Core Operating voltage ranges and respective footnotes.
4.2 Table 12, "Current Consumption for
–40×C to 85×C, for Silicon Revision
2.0.1," on page 16
Updated for silicon revision 2.0.1.
4.2 Table 13, "Current Consumption for
–20×C to 70×C, for Silicon Revision
2.0.1," on page 17
Updated values for silicon revision 2.0.1.
4.2 Section 3, “Signal Descriptions
Removed reference to the TTM_PAD as it is no longer connected.
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
117
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Document Number: MCIMX31_5
Rev. 4.3
12/2009
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