MCIMX508CVK1B_技术文档

Document Number: IMX50CEC

Rev. 7, 10/2013

Freescale Semiconductor

Data Sheet: Technical Data

MCIMX50

Package Information

Plastic Package

i.MX50 Applications

Processors for

Case 416 MAPBGA 13 x 13 mm, 0.5 mm pitch

Case 416 PoPBGA 13 x 13 mm, 0.5 mm pitch

Case 400 MAPBGA 17 x 17 mm, 0.8 mm pitch

Consumer Products

Ordering Information

See Table 1 on page 7 for ordering information.

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7

1.4. Part Number Feature Comparison . . . . . . . . . . . . . 8

1.5. Package Feature Comparison . . . . . . . . . . . . . . . . 9

2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21

4.2. Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31

4.4. Output Buffer Impedance Characteristics . . . . . . 37

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41

4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 48

4.7. External Interface Module (EIM) . . . . . . . . . . . . . . 60

4.8. DRAM Timing Parameters . . . . . . . . . . . . . . . . . . 68

4.9. External Peripheral Interfaces . . . . . . . . . . . . . . . 73

5. Package Information and Contact Assignments . . . . . 101

5.1. 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

1 Introduction

The i.MX50 applications processors are

multimedia-focused products offering high-performance

processing optimized for lowest power consumption.

The i.MX50 processors are Freescale Energy Efficiency

Solutions products.

The i.MX50 is optimized for portable multimedia

applications and features Freescale’s advanced

implementation of the ARM Cortex-A8 core, which

®

operates at speeds as high as 1 GHz. The i.MX50

provides a powerful display architecture, including a 2D

Graphics Processing Unit (GPU) and Pixel Processing

Pipeline (ePXP). Additionally, the i.MX50 includes a

complete integration of the electrophoretic display

function. The i.MX50 supports DDR2, LPDDR2, and

LPDDR1 DRAM at clock rate up to 266 MHz to enable

a range of performance and power trade-offs.

5.2. 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.3. 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.4. Signal Assignments . . . . . . . . . . . . . . . . . . . . . . 124

6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

The flexibility of the i.MX50 architecture allows it to be

used in a variety of applications. As the heart of the

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

Introduction

application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as

WLAN, Bluetooth™, GPS, and displays.

1.1

Product Overview

The i.MX50 is designed to enable high-tier portable applications by satisfying the performance

requirements of advanced operating systems and applications.

1.1.1

Dynamic Performance Scaling

Freescale’s dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage

and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant

power reduction.

1.1.2

Multimedia Processing Powerhouse

The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level

cache system, a NEON™ coprocessor with SIMD media processing architecture and 32-bit

single-precision floating point support, and two vector floating point coprocessors. The system is further

enhanced by a programmable smart DMA (SDMA) controller.

1.1.3

Powerful Display System

The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper).

The display subsystem consists of the following modules:

•

Electrophoretic Display Controller (EPDC) (i.MX508 only)

The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD

TM

controller. It is specifically designed to drive E-INK EPD panels, supporting a wide variety of

TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this

functionality for e-paper applications, allowing a significant bill of materials cost savings over an

external solution while reaching much higher levels of performance and lower power. The EPDC

module is defined in the context of an optimized hardware/software partitioning and works in

conjunction with the ePXP (see Section 1.1.4, “Graphics Accelerators”).

•

Enhanced LCD Controller Interface (eLCDIF)

The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and

allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart

panels. The module also supports synchronous operation with the ePXP to allow the processed

frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF

can support up to 32-bit interfaces.

1.1.4

Graphics Accelerators

Integrated graphics accelerators offload processing from the ARM processor, enabling high performance

graphic applications at minimum power.

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Introduction

•

Pixel Processing Pipeline (ePXP)

The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for

combined operations, such as color-space conversion, alpha blending, gamma mapping, and

rotation. The ePXP is enhanced with features specifically for grayscale applications working in

conjunction with the electrophoretic display controller to form a full grayscale display solution. In

addition, the ePXP supports traditional pixel/frame processing paths for still-image and video

processing applications, allowing it to interface with the integrated LCD controller (eLCDIF).

•

Graphics acceleration

The i.MX50 provides a 2D graphics accelerator with performance up to 200 Mpix/s.

1.1.5

Multilevel Memory System

The multilevel memory system of the i.MX50 is based on the L1 instruction and data caches, L2 cache,

and internal and external memory. The i.MX50 supports many types of external memory devices,

including DDR2, LPDDR2, LPDDR1, NOR Flash, PSRAM, Cellular RAM, NAND Flash (MLC and

SLC) and OneNAND™, and managed NAND including eMMC up to rev. 4.4.

1.1.6

Smart Speed™ Technology

The i.MX50 device has power management throughout the SOC that enables the rich suite of multimedia

features and peripherals to consume minimum power in both active and various low power modes. Smart

Speed technology enables the designer to deliver a feature-rich product that requires levels of power that

are far less than industry expectations.

1.1.7

Interface Flexibility

The i.MX50 supports connection to a variety of interfaces, including an LCD controller for displays, two

high-speed USB on-the-go-capable PHYs, multiple expansion card ports (high-speed MMC/SDIO host

2

and others), 10/100 Ethernet controller, and a variety of other popular interfaces (for example, UART, I C,

2

and I S serial audio).

1.1.8

Advanced Security

The i.MX50 delivers hardware-enabled security features, such as High-Assurance Boot 4 (HAB4) for

signed/authenticated firmware images, basic DRM support with random private keys and AES

encryption/decryption, and storage and programmability of on-chip fuses.

1.2

Features

The i.MX50 applications processor is based on the ARM Cortex-A8 platform and has the following

features:

•

MMU, L1 instruction cache, and L1 data cache

Unified L2 cache

800 MHz or 1 GHz target frequency of the core (including NEON, VFPv3, and L1 cache)

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Introduction

•

NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite)

coprocessor supporting VFPv3

The memory system consists of the following components:

•

Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

•

Level 2 cache:

— Unified instruction and data (256 Kbyte)

Level 2 (internal) memory:

— Boot ROM, including HAB (96 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

External memory interfaces:

•

— 16/32-bit DDR2-533, LPDDR2-533, or LPDDR1-400 up to a total of 2 GByte

— 8-bit NAND SLC/MLC Flash with up to 100 MHz synchronous clock rate and up to 32-bit

hardware ECC for 1 Kbyte block size

— 16/32-bit NOR Flash with a dedicated 16-bit muxed-mode interface. I/O muxing logic selects

EIMv2 port as primary muxing at system boot.

— 16-bit PSRAM, Cellular RAM

— Managed NAND, including eMMC up to rev 4.4

The i.MX50 introduces a next generation system bus fabric architecture that aggregates various

sub-system buses and masters for access to system peripherals and memories. The various bus-systems

and components are as follows:

•

64-bit AXI Fabric (266 MHz)—This bus-fabric is the SoC’s central bus aggregation point.

— Provides access to all slave targets in the SoC:

– ROM (ROMCP)

– On-chip RAM (OCRAM)

– External DRAM (DRAM MC)

– External static RAM (EIM)

– Interrupt controller (TZIC)

– Decode into the AHB MAX crossbar second level AHB fabric.

— Provides arbitration to the following masters in the system:

– ARM CPU complex

– Pixel processing pipeline (ePXP)

– Electrophoretic display controller (EPDC)

– eLCDIF LCD display controller

– DCP Crypto engine

– BCH ECC engine

– MAX AHB crossbar

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Introduction

– GPU 2D

– SDMA

– USBOH1 (USB OTG and host controller complex)

– FEC Ethernet controller

•

MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system

and provides decode into the following slaves:

— IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and

without DMA capability

— IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and

without DMA capability

— APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its

memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing

peripheral access to many of the high-speed IP blocks on the i.MX50.

•

IP-Bus 3 (66 MHz)—This third peripheral bus segment contains peripherals accessible by the

ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be

accessed by the ARM CPU through IP-Bus 1 and SPBA.

Quality of service controller (QoSC)—This provides both soft and dynamic arbitration/priority

control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and

EPDC to provide dynamic priority control, based on real-time metrics.

The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia

performance. The use of hardware accelerators provides both high performance and low power

consumption, while freeing up the CPU core for other tasks.

The i.MX50 incorporates the following hardware accelerators:

•

GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance

ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required

to support both LCD and EPD display applications

The i.MX50 includes the following interfaces to external devices:

NOTE

Not all the interfaces are available simultaneously depending on I/O

multiplexer configuration.

•

Displays:

— EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048 × 1536 at

106 Hz refresh (or 4096 × 4096 at 20 Hz)

— eLCDIF—Supporting beyond SXGA + (1400 × 1050) at 60 Hz resolutions with up to a 32-bit

display interface

— On the i.MX508, both displays can be active simultaneously. If both displays are active, the

eLCDIF only provides a 16-bit interface due to pin muxing.

Expansion cards:

— Four SD/MMC card

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Introduction

•

USB:

— One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY

— One High Speed (HS) USB 2.0 host port with integrated HS USB PHY

Miscellaneous interfaces:

•

— One-wire (OWIRE) port

— Two I2S/SSI/AC97 ports, supporting up to 1.4 Mbps each connected to the Audio Multiplexer

(AUDMUX) providing four external ports

— Five UART RS232 ports, up to 4.0 Mbps each

— Two eCSPI (Enhanced CSPI) ports, up to 66 Mbps each plus CSPI port, up to 16.6 Mbps

2

— Three I C ports, supporting 400 kbps

— Fast Ethernet controller IEEE 802.3, 10/100 Mbps

— Key pad port (KPP)

— Two pulse width modulators (PWM)

— GPIO with interrupt capabilities

— Secure JTAG controller (SJC)

The system supports efficient and smart power control and clocking:

•

Supporting DVFS techniques for low power modes, including auto slow architecture

Power gating-SRPG (state retention power gating) for ARM core and NEON

Support for various levels of system power modes

Flexible clock gating control scheme

On-chip temperature monitor

On-chip 32 kHz and 24 MHz oscillators

A total of four PLLs with the fourth PLL providing up to eight independently controllable outputs,

improving the ease of clocking control, especially for display and connectivity modules

Security functions are enabled and accelerated by the following hardware:

•

Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features

Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and

mechanism to detect voltage and clock glitches

Advanced high assurance boot (A-HAB)—HAB with the next embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

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Introduction

1.3

Ordering Information

Table 1 provides the ordering information.

Table 1. Ordering Information

Temperature

Range ( C)

Maximum

ARM CLK

Frequency

Mask

Set

°

Part Number

Features

Package¹

T_ambientT_junction

MCIMX508CVK1B

MCIMX508CVM1B

1 GHz

N78A Full Specification

0 to 70

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

MCIMX508CVK8B 800 MHz N78A Full Specification

MCIMX508CZK8B 800 MHz N78A Full Specification

MCIMX508CVM8B 800 MHz N78A Full Specification

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 PoPBGA

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

MCIMX507CVM1B

MCIMX507CVK1B

1 GHz

N78A No GPU

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

MCIMX507CVM8B 800 MHz N78A No GPU

MCIMX507CVK8B 800 MHz N78A No GPU

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

MCIMX503CVK8B 800 MHz N78A No EPD controller

MCIMX503CVM8B 800 MHz N78A No EPD controller

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

MCIMX503EVM8B 800 MHz N78A No EPD controller,

Extended Temperature

-20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

MCIMX502CVK8B 800 MHz N78A No GPU, no EPD controller

0 to 70

0 to 90 13 x 13 mm, 0.5 mm pitch BGA

Case: 416 MAPBGA

MCIMX502CVM8B 800 MHz N78A No GPU, no EPD controller

0 to 70

0 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

MCIMX502EVM8B 800 MHz N78A No GPU, no EPD controller,

Extended Temperature

-20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA

Case: 400 MAPBGA

1

Case MAPBGA is RoHS compliant, lead-free MSL (Moisture Sensitivity Level) 3.

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Introduction

1.4

Part Number Feature Comparison

Table 2 provides an overview of the feature differences between the i.MX50 part numbers.

Table 2. Part Number Feature Comparison

Part Number Disabled Features

Comments

MCIMX508

MCIMX507

MCIMX503

None

GPU

EPDC

The i.MX503 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist

on the i.MX503, but because the EPDC block is disabled, those pins cannot be used for

EPDC functionality (ALT0) and must be configured in the IOMUX with another ALT-mode

setting.

MCIMX502

GPU, EPDC

The i.MX502 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist

on the i.MX502, but because the EPDC block is disabled, those pins cannot be used for

EPDC functionality (ALT0) and must be

configured in the IOMUX with another ALT-mode setting.

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Introduction

1.5

Package Feature Comparison

Table 3 provides an overview of the feature and pin differences between the i.MX50 packages.

Table 3. Package Feature Comparison

I/O Pin Differences

Versus 416 MAPBGA

Package

Dimensions

Notes on Package Differences

416 MAPBGA 13 x 13 mm,

0.5 mm pitch

—

• USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted

together on the 416 MAPBGA package substrate.

• USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted

together on the 416 MAPBGA package substrate.

416 PoPBGA 13 x 13 mm, Deleted Pins:

0.5 mm pitch DRAM_A10

DRAM_A11

• The i.MX50 PoPBGA package supports 168-FBGA

LPDDR2 DRAM memory only. It is not possible to support

LPDDR1 or DDR2 on the i.MX50 PoPBGA.

DRAM_A12

DRAM_A13

DRAM_A14

DRAM_CAS

DRAM_OPEN

DRAM_OPENFB

DRAM_RAS

• i.MX50 PoPBGA was designed to accommodate a

combined LPDDR2 / eMMC PoP memory. The PoP eMMC

device uses the SD3_DATA[7:0], SD3_CLK, and

SD3_CMD pins. Because the PoP eMMC I/O and memory

supplies are tied together on the substrate, 1.8 V eMMC

I/O operation is not supported for the PoP eMMC device.

POP_NAND_VCC and NVCC_NANDF must use a 3 V

supply.

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

• The NVCC_EMI_DRAM power pins supply 1.2 V power to

the i.MX50 DRAM controller as well as the PoP LPDDR2

DRAM.

DRAM_SDCLK_1

DRAM_SDCLK_1_B

DRAM_SDODT0

DRAM_SDODT1

DRAM_SDWE

• Additional PoP package pin descriptions may be found in

the Special Signals Considerations section (Table 5).

• On the PoPBGA package, the DRAM Address, Data, and

clock pins are routed to the bottom balls for Freescale test

purposes only. It is recommended that these bottom

DRAM pins are left unconnected on the customer PCB.

• USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted

together on the 416 PoPBGA package substrate.

• USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted

together on the 416 PoPBGA package substrate.

DRAM_OPEN

DRAM_OPENFB

Added Pins:

POP_EMMC_RST

POP_LPDDR2_ZQ0

POP_LPDDR2_ZQ1

POP_LPDDR2_1.8V

POP_NAND_VCC

400 MAPBGA 17 x 17 mm, Deleted Pins:

0.8 mm pitch DRAM_SDCLK_1

DRAM_SDCLK_1_B

DRAM_A14

• USB_OTG_VDDA25 and USB_H1_VDDA25 are

independent and NOT shorted together on the 400

MAPBGA package substrate.

• USB_OTG_VDDA33 and USB_H1_VDDA33 are

independent and NOT shorted together on the 400

MAPBGA package substrate.

DRAM_SDODT1

UART2_CTS

UART2_RTS

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Architectural Overview

2 Architectural Overview

The following sections provide an architectural overview of the i.MX50 processor system.

2.1

Block Diagram

Figure 1 shows the functional modules in the i.MX50 processor system.

Figure 1. i.MX50 System Block Diagram

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Modules List

NOTE

The numbers in brackets indicate the number of module instances. For

example, PWM (2) indicates two separate PWM peripherals.

3 Modules List

The i.MX50 processor contains a variety of digital and analog modules that are described in Table 4 in

alphabetical order.

Table 4. i.MX50 Digital and Analog Modules

Block

Mnemonic

Block Name

Subsystem

Brief Description

ARM

Cortex-A8

ARMCortex-A8 ARM

Platform

The ARM Cortex-A8 Core Platform consists of the ARM Cortex-A8 processor

and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache,

32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache.

The platform also contains an event monitor and debug modules. It also has

a NEON coprocessor with SIMD media processing architecture, register file

with 32 × 64-bit general-purpose registers, an Integer execute pipeline (ALU,

Shift, MAC), dual, single-precision floating point execute pipeline (FADD,

FMUL), load/store and permute pipeline, and a non-pipelined vector floating

point (VFP Lite) coprocessor supporting VFPv3.

EPDC

ePXP

Electrophoretic Display

The EPDC is a feature-rich, low power, and high-performance direct-drive

active matrix EPD controller. It is specifically designed to drive E-INK^TMEPD

panels supporting a wide variety of TFT backplanes.

Display

Peripherals

Controller

enhancedPiXel Display

A high-performance pixel processor capable of 1 pixel/clock performance for

combined operations such as color-space conversion, alpha blending,

gamma-mapping, and rotation. The ePXP is enhanced with features

specifically for grayscale applications. In addition, the ePXP supports

traditional pixel/frame processing paths for still-image and video processing

applications allowing it to interface with the integrated LCD controller

(eLCDIF).

Processing

Pipeline

Peripherals

eLCDIF

AUDMUX

CAMP-1

enhanced LCD Display

The eLCDIF is a high-performance LCD controller interface supporting a rich

set of modes allowing inter operability with a wide variety of LCD panels,

including DOTCK/RGB and smart panels. The module also supports a

synchronous operation with the ePXP to allow the processed frames to be

passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The

eLCDIF can support up to 32-bit interfaces.

Interface

Peripherals

Digital Audio

Mux

Slave

The AUDMUX is a programmable interconnect for voice, audio, and

Connectivity synchronous data routing between host serial interfaces (for example, SSI1

Peripherals

and SSI2) and peripheral serial interfaces (audio and voice codecs). The

AUDMUX has six ports (two internal and four external) with identical

functionality and programming models. A desired connectivity is achieved by

configuring two or more AUDMUX ports.

Clock Amplifier Clocks,

Resets, and

Power Control

Clock Amplifier

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Modules List

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

CCM

GPC

SRC

Clock Control

Module

Global Power

Controller

Clocks,

Resets, and

Power Control The system includes four PLLs.

These modules are responsible for clock and reset distribution in the system,

and also for system power management.

System Reset

Controller

CSPI

Configurable

Slave

Full-duplex enhanced synchronous serial interface, with data rate up to

eCSPI-1

eCSPI-2

SPI, Enhanced Connectivity 66.5 Mbit/s (for eCSPI, master mode). It is configurable to support

CSPI

Peripherals

Master/Slave modes, four chip selects to support multiple peripherals.

DAP

TPIU

CTI

Debug System System

Control

The Debug System provides real-time trace debug capability of both

instructions and data. It supports a trace protocol that is an integral part of the

ARM Real Time Debug solution (RealView).

Peripherals

Real-time tracing is controlled by specifying a set of triggering and filtering

resources, which include address and data comparators, three cross-system

triggers (CTI), counters, and sequencers.

Debug access port (DAP)—The DAP provides real-time access for the

debugger without halting the core to System memory and peripheral

registers. All debug configuration registers and Debugger access to JTAG

scan chains.

DRAM MC DRAM Memory External

The DRAM MC consists of a DRAM memory controller and PHY, supporting

LPDDR2, DDR2, and LPDDR1 memories with clock frequencies up to

266 MHz with 32-bit interface. It is tightly linked with the system bus fabric and

employs advanced arbitration mechanism to maximize DRAM bandwidth

efficiency.

Controller

Memory

Interface

EIM

Static Memory External

The EIM is an external static memory and generic host interface. It supports

up to a 32-bit interface (through pin-muxing) or a dedicated 16-bit muxed

interface. It can be used to interface to PSRAMs (sync and async), NOR-flash

or any external memory mapped peripheral.

Controller

Memory

Interface

BCH32/GPMI2 Raw NAND

System with

RawNAND

and SSP

Peripherals

The i.MX50 contains a fully hardware accelerated raw NAND flash solution

supporting SLC and MLC devices. The system consists of the GPMI2

module, which is driven by the APBH DMA engine to perform the NAND flash

interface function (supporting up to ONFI2.1). Coupled with the GPMI2 is the

BCH32 hardware error-correction engine which is an AXI bus-master and

supports up to 32-bits of correction over block sizes up to 1 Kbyte (that is,

supports up to 2 Kbyte code-size).

ECC

System Fabric System Fabric System

In order to aggregate the multitude of masters and memory mapped devices,

the i.MX50 contains a next-generation AMBA3 AXI bus fabric. In addition, the

i.MX50 contains a Quality of Service Controller IP (QoSC) which allows both

soft priority control and dynamic priority elevation. Software priority control

works for all masters but dynamic hardware control only works for EPDC and

eLCDIF.

and QoS

Peripherals

EPIT

Enhanced

Periodic

Interrupt Timer

Timer

Peripherals

Each EPIT is a 32-bit set and forget timer that starts counting after the EPIT

is enabled by software. It is capable of providing precise interrupts at regular

intervals with minimal processor intervention. It has a 12-bit prescaler for

division of input clock frequency to get the required time setting for the

interrupts to occur, and counter values can be programmed on the fly.

i.MX50 Applications Processors for Consumer Products, Rev. 7

12

Freescale Semiconductor

Modules List

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

Ultra High-Speed eSDHC, enhanced to support eMMC 4.4 standard

eSDHCv3-3 Ultra-High-

(eMMC 4.4) Speed

Multi-Media

Master

Connectivity specification, for 832 Mbps.

Peripherals IP is backward compatible to eSDHCv2 IP. See complete features listing in

Card/

eSDHCv2 entry below.

Secure Digital

card host

Port 3 is specifically enhanced to support eMMC 4.4 specification, for double

data rate (832 Mbps, 8-bit port).

controller, ver. 3

eSDHCv2-1 Enhanced

eSDHCv2-2 Multi-Media

Card/

In Enhanced Multi-Media Card/Secure Digital Host Controller the Ports 1, 2,

and 4 are compatible with the MMC System Specification version 4.3, full

support

eSDHCv2-4 Secure Digital

Host Controller,

The generic features of the eSDHCv2 module, when serving as SD/MMC

host, include the following:

ver. 2

• Can be configured either as SD/MMC controller

• Supports eSD and eMMC standard, for SD/MMC embedded type cards

• Conforms to SD Host Controller Standard Specification version 2.0, full

support

• Compatible with the SD Memory Card Specification version 1.1

• Compatible with the SDIO Card Specification version 1.2

• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD

Combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full/High speed mode

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data

lines

• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines

FEC

Fast Ethernet

Controller

Master

The Ethernet Media Access Controller (MAC) is designed to support both

Connectivity 10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external

Peripherals

transceiver interface and transceiver function are required to complete the

interface to the media.

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

General

Purpose I/O

Modules

Slave

These modules are used for general purpose input/output to external ICs.

Connectivity Each GPIO module supports up to 32 bits of I/O.

Peripherals

GPT

General

Purpose Timer Peripherals

Timer

Each GPT is a 32-bit free-running or set and forget mode timer with a

programmable prescaler and compare and capture register. A timer counter

value can be captured using an external event, and can be configured to

trigger a capture event on either the leading or trailing edges of an input pulse.

When the timer is configured to operate in “set and forget” mode, it is capable

of providing precise interrupts at regular intervals with minimal processor

intervention. The counter has output compare logic to provide the status and

interrupt at comparison. This timer can be configured to run either on an

external clock or on an internal clock.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

13

Modules List

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

GPU2Dv1

Graphics

Processing

Unit-2D, ver. 1

Display

Peripherals

The GPU2Dv1 provides hardware acceleration for 2D graphic algorithms with

sufficient processor power to run desk-top quality interactive graphics

applications on displays up to HD1080 resolution.

I²C-1

I²C-2

I²C-3

I²C Interface

Connectivity I²C provides serial interface for controlling peripheral devices. Data rates of

Peripherals

up to 400 kbps are supported.

OCOTP

Controller

On-chip OTP

controller

Security

Peripherals

The on-chip one-time -programmable (OCOTP) ROM serves the functions of

hardware and software capability bits, Freescale operations and unique-ID,

the customer-programmable cryptography key, and storage of various ROM

and general purpose configuration bits.

IOMUXC

KPP

IOMUX Control Slave

This module enables flexible I/O multiplexing. Each I/O pad has default as

Connectivity well as several alternate functions. The alternate functions are software

Peripherals

configurable.

Keypad Port

Slave

The KPP supports an 8 × 8 external keypad matrix. The KPP features are as

Connectivity follows:

Peripherals

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

OWIRE

One-Wire

Interface

Slave

One-Wire support provided for interfacing with an on-board EEPROM, and

Connectivity smart battery interfaces, for example, Dallas DS2502.

Peripherals

PWM-1

PWM-2

Pulse Width

Modulation

Slave

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

Connectivity generate sound from stored sample audio images. It can also generate tones.

Peripherals

The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.

RAM

128 Kbytes

Internal RAM

Boot ROM

Internal

Memory

The On-Chip Memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus.

ROM

96 Kbytes

Internal

Memory

Supports secure and regular Boot Modes.

The ROM Controller supports ROM Patching.

i.MX50 Applications Processors for Consumer Products, Rev. 7

14

Freescale Semiconductor

Modules List

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

SDMA

Smart Direct

Memory

Master

Connectivity system performance by offloading various cores in dynamic data routing.

Access

Peripherals

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM Cortex-A8 and SDMA

• Very fast context-switching with two-level priority-based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement,

and no address changes on source and destination address)

• DMA ports can handle uni-directional and bi-directional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers for EMI

• Support of byte-swapping and CRC calculations

• A library of scripts and API is available

SJC

Secure JTAG

Controller

System

Control

Peripherals

The Secure JTAG Controller provides a mechanism for regulating JTAG

access, preventing unauthorized JTAG usage while allowing JTAG access for

manufacturing tests and software debugging.

The i.MX50 JTAG port provides debug access to several hardware blocks

including the ARM processor and the system bus, therefore, it must be

accessible for initial laboratory bring-up, manufacturing tests and

troubleshooting, and for software debugging by authorized entities. However,

if the JTAG port is left unsecured it provides a method for executing

unauthorized program code, getting control over secure applications, and

running code in privileged modes.

The Secure JTAG controller provides three different security modes that can

be selected through an e-fuse configuration to prevent unauthorized JTAG

access.

SPBA

SRTC

Shared

Peripheral Bus Control

Arbiter

System

SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP

bus) arbiter.

Peripherals

Secure Real

Time Clock

Security

Peripherals

The SRTC incorporates a special System State Retention Register (SSRR)

that stores system parameters during system shutdown modes. This register

and all SRTC counters are powered by dedicated supply rail NVCC_SRTC.

The NVCC_SRTC can be energized separately even if all other supply rails

are shut down. This register is helpful for storing warm boot parameters. The

SSRR also stores the system security state. In case of a security violation,

the SSRR marks the event (security violation indication).

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

15

Modules List

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

SSI-1

SSI-2

I2S/SSI/AC97

Interface

Slave

The SSI is a full-duplex synchronous interface used on the i.MX50 processor

Connectivity to provide connectivity with off-chip audio peripherals. The SSI interfaces

Peripherals

connect internally to the AUDMUX for mapping to external ports. The SSI

supports a wide variety of protocols (SSI normal, SSI network, I2S, and

AC-97), bit depths (up to 24 bits per word), and clock/frame sync options.

Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an external

DMA controller in order to minimize its impact on system performance. The

second pair of FIFOs provides hardware interleaving of a second audio

stream, which reduces CPU overhead in use cases where two time slots are

being used simultaneously.

Temperature

Monitor

Temp Sensor Analog

UARTInterface, Slave

The temperature sensor is an internal module to the i.MX50 that monitors the

die temperature.

UART-1

UART-2

UART-3

UART-4

UART-5

Each of the UARTv2 modules supports the following serial data

ver. 2

Connectivity transmit/receive protocols and configurations:

Peripherals

• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or

none)

• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate

relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F

standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

USB-OH-1

WDOG-1

USB 2.0

Master

Connectivity

Peripherals

USB-OH-1 supports USB2.0 HS/FS/LS, and contains:

• One high-speed OTG-capable module with integrated HS USB PHY

• One high-speed Host module with integrated HS USB PHY

High-Speed

OTG-capable

and Host ports

Watch Dog

Timer

Peripherals

The Watchdog (WDOG) timer module protects against system failures by

providing a method of escaping from unexpected events or programming

errors. The WDOG Timer supports two comparison points during each

counting period. Each of the comparison points is configurable to invoke an

interrupt to the ARM core, and a second point invokes an external event on

the WDOG line.

XTALOSC

Crystal

Oscillator I/F

Clocking

The XTALOSC module combined with an external 24 MHz crystal with load

capacitors implements a crystal oscillator.

i.MX50 Applications Processors for Consumer Products, Rev. 7

16

Freescale Semiconductor

Modules List

3.1

Special Signal Considerations

Table 5 lists special signal considerations for the i.MX50. The signal names are listed in alphabetical

order. The package contact assignments are found in Section 5, “Package Information and Contact

Assignments.” The signal descriptions are defined in the MCIMX50 Applications Processor Reference

Manual (MCIMX50RM).

Table 5. Special Signal Considerations

Signal Name

BOOT_MODE0,

Remarks

These two input pins are sampled out of reset and set the boot mode. For Internal boot, they

should be set to 00. For Internal Fuse Only boot, they should be set to 10. For USB

downloader, they should be set to 11. The BOOTMODE pins are in the NVCC_RESET domain

and include an internal 100K pull-up resistor at start-up.

BOOT_MODE1

BOOT_CONFIG1[7:0],

BOOT_CONFIG2[7:0],

BOOT_CONFIG3[7:0]

These 24 pins are the GPIO boot override pins and may be driven at power up to select the

boot mode. They are sampled 4 x CKIL clock cycles after POR is de-asserted. Consult the

“System Boot” chapter of the Reference Manual for more details.

Note that these are not dedicated pins: the BOOT_CONFIG pins appear over 24 pins of the

EIM interface.

BT_LPB_FREQ[1:0]

CHGR_DET_B

If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the BT_LPB_FREQ[1:0] pins

will be sampled to determine the ARM core frequency. Consult the “System Boot” chapter of

the Reference Manual for more details.

Note that these are not dedicated pins: BT_LPB_FREQ0 appears on SSI_TXFS and

BT_LPB_FREQ1 appears on SSI_TXC.

This is the USB Charger Detect pin. It is an open drain output pin that expects a 100 K pull-up.

This pin is asserted low when a USB charger is detected on the OTG PHY DP and DM. This

detection occurs with the application of VBUS. This pin is a raw sensor output and care must

be taken to follow the system timings outlined in the USB charger specification Rev 1.1. The

maximum current leakage at this pin is 8.5 μA. This pin can be controlled by software control

as well. If not used, this pin should be tied to ground or left floating.

CKIH

This is an input to the CAMPs (Clock Amplifiers), which include on-chip AC-coupling

precluding the need for external coupling capacitors. The CAMPs are enabled by default, but

the main clocks feeding the on-chip clock tree are sourced from XTAL/EXTAL by default.

Optionally, the use of a low jitter external oscillators to feed CKIH (while not required) can be

an advantage if low jitter or special frequency clock sources are required by modules sourced

by CKIH. See CCM chapter in the MCIMX50 Applications Processor Reference Manual

(MCIMX50RM) for details on the respective clock trees.

After initialization, the CAMPs may be disabled if not used by programming the CCR

CAMPx_EN field. If disabled, the on-chip CAMP output is low and the input is irrelevant. CKIH

is on the NVCC_JTAG power domain, so the input clock amplitude should not exceed

NVCC_JTAG.

If unused, the user should tie CKIH to GND for best practice.

CKIL/ECKIL

The user must tie a fundamental mode 32.768 K crystal across ECKIL and CKIL. The target

ESR should be 50 K or less. The bias resistor for the amplifier is integrated and approximately

14 MΩ. The target load capacitance for the crystal is approximately 10 pF. The load capacitors

on the board should be slightly less than double this value after taking parasitics into account.

While driving in an external 32 KHz signal into ECKIL, CKIL should be left floating so that it

biases. A differential amplifier senses these two pins to propagate the clock inside the

i.MX508. Care must be taken to minimize external leakages on ECKIL and CKIL. If they are

significant to the 14 MΩ feedback or 1 μA, then loss of oscillation margin or cessation of

oscillation may result.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

17

Modules List

Table 5. Special Signal Considerations (continued)

Remarks

Signal Name

DRAM_OPEN,

DRAM_OPENFB (for 416

These pins are the echo gating output and feedback pins used by the DRAM PHY to bound a

window around the DQS transition. For an application using a single DRAM device, these pins

MAPBGA and 400 MAPBGA) should be routed so that the

trace length (DRAM_OPEN + DRAM_OPENFB) =

trace length (DRAM_SDCLK0 + DRAM_SDQS0).

For an application using two DRAM devices, they should be routed so that the

trace length (DRAM_OPEN + DRAM_OPENFB) =

trace length (AVG(DRAM_SDCLK0+DRAM_SDCLK1) + AVG (DRAM_SDQS0_to_Device0 +

DRAM_SDQS0_to_Device1)).

This connection is required for LPDDR1, LPDDR2, and DDR2. For the i.MX50 PoP package,

these signals are connected on the substrate.

DRAM_SDODT0 (for 416

These pins are the On-die termination outputs from the i.MX50.

MAPBGA and 400 MAPBGA), For DDR2, these pins should be connected to the DDR2 DRAM ODT pins. For LPDDR1 and

DRAM_SDODT1 (for 416

MAPBGA only)

LPDDR2, these pins should be left floating. Note that both SDODT pins are removed on the

416 PoPBGA package, and only SDODT0 exists on the 400 MAPBGA package.

DRAM_CALIBRATION

JTAG_MOD

This pin is the ZQ calibration used to calibrate DRAM Ron and ODT.

For LPDDR2, this pin should be connected to ground through a 240 Ω 1% resistor. For DDR2

and LPDDR1, this pin should be connected to ground through a 300 Ω 1% resistor.

This input has an internal 100K pull-up, by default. Note that JTAG_MOD is referenced as

SJC_MOD in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) - both

names refer to the same signal. JTAG_MOD must be externally connected to GND for normal

operation. Termination to GND through an external pull-down resistor (such as 1 kΩ) is

allowed. If JTAG port is not needed, the internal pull-up can be disabled in order to reduce

supply current to the pin.

JTAG_TCK

JTAG_TDI

JTAG_TDO

This input has an internal 100K pull-down. This pin is in the NVCC_JTAG domain.

This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.

This is a 3-state output with an internal gate keeper enable to prevent a floating condition. An

external pull-up or pull-down resistor on JTAG_TDO is detrimental and should be avoided. This

pin is in the NVCC_JTAG domain.

JTAG_TMS

JTAG_TRSTB

NC

This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.

These signals are No Connect (NC) and should be floated by the user.

LOW_BATT_GPIO

If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the i.MX50 will boot up at a

lower ARM clock frequency to reduce system power. The actual ARM clock frequency used

when LOW_BATT_GPIO is asserted is determined by the BT_LPB_FREQ[1:0] pins (220 MHz

to 55.3 MHz). The polarity of the LOW_BATT_GPIO is active high by default, but may be set

to active low by setting the LOW_BATT_GPIO_LEVEL OTP bit.

See the “System Boot” chapter of the Reference Manual for more details.

Note that this is not a dedicated pin: LOW_BATT_GPIO appears on the UART4_TXD pin.

PMIC_STBY_REQ

PMIC_ON_REQ

This output may be driven high when the i.MX50 enters the STOP mode to notify the PMIC to

enter its low power standby state. This output is in the NVCC_SRTC domain.

This output from the i.MX50 can instruct the PMIC to turn on when the i.MX50 only has

NVCC_SRTC power. This may be useful for an alarm application, as it allows the i.MX50 to

turn off all blocks except for the RTC and then power on again at a specified time. This output

is in the NVCC_SRTC domain.

i.MX50 Applications Processors for Consumer Products, Rev. 7

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Freescale Semiconductor

Modules List

Table 5. Special Signal Considerations (continued)

Remarks

Signal Name

PMIC_RDY

This input may be used by a PMIC to signal to the i.MX50 that the PMIC supply outputs are at

operating levels when resuming from STOP mode. The PMIC_RDY input is pin muxed on ALT3

of the I2C3_SCL pin and is in the NVCC_MISC domain.

POP_EMMC_RST

(416 PoPBGA Only)

This pin is the PoP eMMC 4.4 Reset pin. The customer may connect this on their PCB to any

free GPIO, or just leave floating for non-4.4 eMMC. This pin does not connect to the i.MX50 die.

POP_LPDDR2_ZQ0/ZQ1

(416 PoPBGA Only)

These pins connect to the PoP LPDDR2 DRAM ZQ pins and should be connected on the

customer PCB to a 240 Ω 1% resistor to ground if used. These pins do not connect to the

i.MX50 die.

POP_LPDDR2_1.8V

(416 PoPBGA Only)

These pins are the 1.8 V supply for the PoP LPDDR2 DRAM. These pins do not connect to the

i.MX50 die.

POP_NAND_VCC

(416 PoPBGA Only)

This is the 3.3V I/O and memory supply for the PoP eMMC. Note that most eMMC can operate

with a 1.8V I/O or a 3.3V I/O voltage. However, because we tied the eMMC memory and I/O

domains together, you can't use the 1.8 V I/O option for the PoP eMMC, only 3.3 V I/O.

POR_B

This POWER-ON RESET input is a cold reset negative logic input that resets all modules and

logic in the IC. The POR_B pin should have an external 68 K pull-up to NVCC_RESET and a

1 μF capacitor to ground.

Note: The POR_B input must be immediately asserted at power-up and remain asserted until

after the last power rail is at its working voltage.

RESET_IN_B

This warm reset negative logic input resets all modules and logic except for the following:

• Test logic (JTAG, IOMUXC, DAP)

• SRTC

• Cold reset logic of WDOG—Some WDOG logic is only reset by POR_B. See WDOG

chapter in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for

details.

SSI_EXT1_CLK,

SSI_EXT2_CLK

The SSI_EXT1_CLK and SSI_EXT2_CLK outputs are recommended for generating a clock

output from the i.MX50. Use of the CKO1 and CKO2 clock outputs is not recommended, as the

large number of combinational logic muxes on those signals will impact jitter and duty-cycle.

Note that these two clock outputs do not have dedicated pins: SSI_EXT1_CLK is IOMUX ALT3

on the OWIRE pin, and SSI_EXT2_CLK is IOMUX ALT3 of the EPITO pin.

TEST_MODE

TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip

pull-down device. The user must either float this signal or tie it to GND.

USB_H1_GPANAIO,

USB_OTG_GPANAIO

These signals are reserved for Freescale manufacturing use only. Users should float these

outputs.

USB_H1_RREFEXT,

USB_OTG_RREFEXT

These signals determine the reference current for the USB PHY bandgap reference. An

external 6.04 kΩ 1% resistor to GND is required. This resistor should be connected through a

short (low impedance connection) and placed away from other noisy regions.

If USB_H1 is not used, the H1 RREFEXT resistor may be eliminated and the pin left floating.

If USB_OTG is not used, the OTG RREFEXT resistor may be eliminated and the pin left

floating.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

19

Electrical Characteristics

Signal Name

Table 5. Special Signal Considerations (continued)

Remarks

USB_H1_VBUS,

USB_OTG_VBUS

These inputs are used by the i.MX50 to detect the presence and level of USB 5 V. If either

VBUS input pin is connected to an external USB connector, there is a possibility that a fast 5

V edge rate during a cable attach could trigger the VBUS input ESD protection, which could

result in damage to the i.MX50 silicon. To prevent this, the system should use some circuitry

to prevent the 5 V edge rate from exceeding 5.25 V / 1 μs. Freescale recommends the use of

a low pass filter consisting of 100 Ω resistor in series and a 1 μF capacitor close to the i.MX50

pin. In the case when the USB interface is connected on an on-board USB device (for example,

3G modem), the corresponding USB_VBUS pin may be left floating.

VREF

This pin is the DRAM MC reference voltage input. For LPDDR2 and DDR2, this pin should be

connected to ½ of NVCC_EMI_DRAM. For LPDDR1, this pin should be left floating. The user

may generate VREF using a precision external resistor divider. Use a 1 kΩ 0.5% resistor to

GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

WDOG_B

This output can be used to reset the system PMIC when the i.MX50 processor is locked up.

This output is in the NVCC_MISC domain.

WDOG_RST_B_DEB

XTAL/EXTAL

This output may be used to drive out the internal system reset signal to the system reset

controller. This is only intended for debug purposes.

These pins are the 24 MHz crystal driver as well as the external 24 MHz clock input.

If using these pins to directly drive a 24 MHz crystal:

• The user should tie a 24 MHz fundamental-mode crystal across XTAL and EXTAL.

• The crystal must be rated for a maximum drive level of 100 μW or higher.

• The recommended crystal ESR (equivalent series resistance) is 80 Ω or less.

If using these pins as a clock input from an external 24 MHz oscillator:

• The crystal may be eliminated and EXTAL driven directly driven by the external oscillator.

The clock signal level on EXTAL must swing from NVCC_SRTC to GND.

• In this configuration, the XTAL pin must be floated and the COSC_EN bit (bit 12 in the CCR

register in the Clock Control Module) must be cleared to put the on-chip oscillator circuit in

bypass mode which allows EXTAL to be externally driven.

• Note there are strict jitter requirements if using an external oscillator in a USB application:

< 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the

USB PHY.

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics of the i.MX50 processor.

NOTE

These electrical specifications are preliminary. These specifications are not

fully tested or guaranteed at this early stage of the product life cycle.

Finalized specifications are published after thorough characterization and

device qualifications have been completed.

i.MX50 Applications Processors for Consumer Products, Rev. 7

20

Freescale Semiconductor

Electrical Characteristics

4.1

Chip-Level Conditions

This section provides the chip-level electrical characteristics for the IC. See Table 6 for a quick reference

to the individual tables and sections.

Table 6. i.MX50 Chip-Level Conditions

For these characteristics, see

Absolute Maximum Ratings

Topic appears …

on page 21

on page 22

on page 23

on page 24

on page 26

13 x 13 mm MAPBGA Package Thermal Resistance Data

13 x 13 mm PoPBGA Package Thermal Resistance Data

17 x 17 mm MAPBGA Package Thermal Resistance Data

Operating Ranges

Operating Frequencies

Supply Current

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 7 may cause permanent damage to

the device. These are stress ratings only. Functional operation of the device

at these or any other conditions beyond those indicated in Table 11 is not

implied. Exposure to absolute-maximum-rated conditions for extended

periods may affect device reliability.

Table 7. Absolute Maximum Ratings

Parameter Description

Peripheral core supply voltage

Symbol

Min

Max

Unit

VCC

–0.3

–0.5

–0.3

–0.5

1.5

1.35

3.6

V

ARM core supply voltage

Bandgap and 480 MHz PLL supply

PLL digital supplies

VDDGP

VDD3P0

VDD1P2

VDD1P8

VDD2P5

1.35

2.25

2.85

PLL analog supplies

Efuse, 24 MHz oscillator, 32 kHz oscillator mux

supply

Memory array supply

Supply voltage (HVIO)

Supply voltage (GPIO, LVIO)

Input/output voltage range

USB VBUS

VDDA/VDDAL1

Supplies denoted as I/O supply

V_in/V_out

–0.5

1.35

3.6

V

3.3

OVDD + 0.3¹

VBUS

DC

Transient (t<30ms, duty cycle < 0.05%)

—

6.00

7.00

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

21

Electrical Characteristics

Table 7. Absolute Maximum Ratings (continued)

Parameter Description

Symbol

Min

Max

Unit

ESD damage immunity:

V_esd

V

Human Body Model (HBM)

Charge Device Model (CDM)

—

2000

500

Storage temperature range

T_STORAGE

–40

125

^oC

1

The term OVDD in this section refers to the associated supply rail of an input or output. The maximum range can be

superseded by the DC tables.

4.1.2

Thermal Resistance Data

4.1.2.1

13 x 13 mm MAPBGA Package Thermal Resistance Data

Table 8 provides thermal resistance data for a 13 x 13 mm MAPBGA package.

Table 8. 13 x 13 mm MAPBGA Package Thermal Resistance Data

Rating

Board

Symbol

Value

Unit

Junction to Ambient (natural convection)^{1, 2}

Junction to Ambient (natural convection)^{1, 2, 3}

Junction to Ambient (at 200 ft/min)^{1, 3}

Junction to Board⁴

Single layer board (1s)

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

51

28

40

24

14

9

°C/W

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Junction to Case⁵

Junction to Package Top (natural convection)⁶

2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

3

4

Per JEDEC JESD51-2 with the single layer board horizontal. The thermal test board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by using the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as

Psi-JT.

i.MX50 Applications Processors for Consumer Products, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

4.1.2.2

13 x 13 mm PoPBGA Package Thermal Resistance Data

Table 9 provides thermal resistance data for a 13 x 13 mm PoPBGA package.

Table 9. 13 x 13 mm PoPBGA Package Thermal Resistance Data

Rating

Board

Symbol

Value

Unit

Junction to Ambient (natural convection)^{1, 2}

Junction to Ambient (natural convection)^{1, 2, 3}

Junction to Ambient (at 200 ft/min)^{1, 3}

Junction to Board⁴

Single layer board (1s)

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

57

31

46

28

18

6

°C/W

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Junction to Case⁵

Junction to Package Top (natural convection)⁶

2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

3

4

Per JEDEC JESD51-2 with the single layer board horizontal. The thermal test board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by using the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as

Psi-JT.

4.1.2.3

17 x 17 mm MAPBGA Package Thermal Resistance Data

Table 10 provides thermal resistance data for a 17 x 17 mm MAPBGA package.

Table 10. 17 x 17 mm MAPBGA Package Thermal Resistance Data

Rating

Board

Symbol

Value

Unit

Junction to Ambient (natural convection)^{1, 2}

Junction to Ambient (natural convection)^{1, 2, 3}

Junction to Ambient (at 200 ft/min)^{1, 3}

Junction to Board⁴

Single layer board (1s)

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

53

30

44

26

19

8

°C/W

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Junction to Case⁵

Junction to Package Top (natural convection)⁶

2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

Per JEDEC JESD51-2 with the single layer board horizontal. The thermal test board meets JESD51-9 specification.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

23

Electrical Characteristics

3

Per JEDEC JESD51-6 with the board horizontal.

4

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

Thermal resistance between the die and the case top surface as measured by using the cold plate method (MIL SPEC-883

Method 1012.1).

6

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as

Psi-JT.

4.1.3

Operating Ranges

Table 11 provides the operating ranges of the i.MX50 processor.

Table 11. i.MX50 Operating Ranges

Symbol

Parameter

ARM core supply voltage

Minimum¹Nominal²Maximum¹

Unit

1.20

0.95

0.85

0.8

1.275

1.05

0.95

0.9

1.35

1.15

V

f

_ARM= 1 GHz

ARM core supply voltage

400 f_ARM800 MHz

V

VDDGP

<

≤

ARM core supply voltage

167 f_ARM400 MHz

1.15

<

≤

ARM core supply voltage

24 f_ARM167 MHz

1.15

≤

ARM core supply voltage

Stop mode

0.75

1³

0.85

1.05

1.225

1.15

Peripheral supply voltage Low Performance

mode (LPM). The DDR clock rate is 24 MHz.

1.275

Peripheral supply voltage Reduced Performance

mode (RPM). The DDR clock rate is 133 MHz.

1³

VCC

Peripheral supply voltage High Performance

mode (HPM). The clock frequencies are derived

from AHB bus using 133 MHz and AXI bus using

266 MHz (as needed). The DDR clock rate is

266 MHz.

1.175

Peripheral supply voltage Stop mode

0.9³

1.15

0.95

1.20

1.275

V

VDDA/VDDAL1

Memory arrays voltage—Run mode

24 ≤ f_ARM≤ 800 MHz

Memory arrays voltage—Run mode

f_ARM= 1 GHz

1.25

1.30

1.35

V

Memory arrays voltage—Stop mode

Bandgap and 480 MHz PLL supply

0.9

2.7

0.95

3.0

1.275

3.3

V

VDD3P0

VDD2P5

Efuse, 24 MHz oscillator, 32 kHz oscillator mux

supply

2.375

2.5

2.625

VDD1P2

VDD1P8

PLL digital supplies

PLL analog supplies

1.15

1.75

1.2

1.8

1.32

1.95

V

i.MX50 Applications Processors for Consumer Products, Rev. 7

24

Freescale Semiconductor

Electrical Characteristics

Table 11. i.MX50 Operating Ranges (continued)

Parameter

Symbol

Minimum¹Nominal²Maximum¹

Unit

NVCC_JTAG

GPIO digital power supplies

1.65

1.875 or

2.775

3.1

V

NVCC_EMI_DRAM

VREF

DDR supply DDR2/LPDDR1 range

DDR supply LPDDR2 range

1.71

1.14

1.8

1.2

1.95

1.3

V

DRAM Reference Voltage Input

1/2

NVCC_E

MI_DRAM

VDDO25

EMI Pad Predriver supply

2.375

2.5

2.625

V

NVCC_NANDF

NVCC_SD1

NVCC_SD2

NVCC_KEYPAD

NVCC_EIM

High voltage I/O (HVIO) supplies

HVIO_L

HVIO_H

1.65

2.7

1.875

3.0

1.95

3.3

NVCC_EPDC

NVCC_LCD

NVCC_MISC

NVCC_SPI

NVCC_SSI

NVCC_UART

NVCC_SRTC

SRTC core and I/O supply (LVIO)

LVIO

1.1

1.2

1.3

3.1

V

NVCC_RESET

1.65

1.875 or

2.775

USB_H1_VDDA25

USB_PHY analog supply

2.25

3.0

—

2.5

3.3

—

2.75

3.6

—

V

USB_OTG_VDDA25⁴

USB_H1_VDDA33

USB PHY I/O analog supply

USB_OTG_VDDA33⁵

VBUS

See Table 7 and Table 78 for details. This is not

a power supply.

—

T_A

T_j

Ambient Temperature, Consumer

0

-20

0

—

70

90

^oC

Extended Ambient Temperature, Consumer

Junction Temperature, Consumer

T_j

Extended Junction Temperature, Consumer

-20

1

2

Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design

must allow for supply tolerances and system voltage drops.

The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mV. Use of supplies with a

tighter tolerance allows reduction of the setpoint with commensurate power savings.

3

4

5

VCC minimum voltage is 1.02 V for extended temperature (-20°C) devices.

USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 MAPBGA and 416 PoPBGA package substrates.

USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 MAPBGA and 416 PoPBGA package substrates.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

25

Electrical Characteristics

4.1.4

Operating Frequencies

Table 12 shows the interface frequency requirements.

Table 12. Interface Frequency

Parameter Description

Symbol

Min

See Table 64

Max

Unit

JTAG: TCK operating frequency

CKIL: operating frequency

CKIH: operating frequency

XTAL oscillator

f_tck

f_ckil

f_ckih

f_xtal

MHz

kHz

32.768¹

See Table 38

22

MHz

27

1

Generated Internally or applied externally.

4.1.5

Supply Current

Table 13 shows the run mode current consumption of the i.MX50.

Table 13. EFuse Supply Current

Description

Symbol

Min

Typ

Max

Unit

eFuse program current¹

VDD2P5 current is required to program one eFuse bit.

I_program

—

40

55

mA

1

The current I_programis only required during program time (t_program).

i.MX50 Applications Processors for Consumer Products, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

Table 14 shows the maximum supply current consumption of the i.MX50 for PMIC specification

purposes.

Table 14. Maximum Supply Current Consumption—ARM CLK = 800 MHz

Condition

Supply

Voltage (V) Current (mA) Power (mW)

• T

a

= 70°C

VDDGP

VCC

1.15

1.275

1.3

628

185

723

236

• ARM core in Run mode

• ARM CLK = 800 MHz

• SYS CLK = 266 MHz

• AHB CLK = 133 MHz

• DDR CLK = 266 MHz

• All voltages operating at maximum

levels

• External (MHz) crystal and on-chip

oscillator enabled

• All modules enabled

VDDA/VDDAL1

VDD1P2

40

51

5.92

1.53

1.13

1.61

8.3

7.70

2.99

3.11

5.32

16.17

0.041

38.8

VDD1P8

1.95

2.75

3.3

VDD2P5¹

VDD3P0

NVCC_EMI_DRAM

VDD_DCDCI

1.95

3.6

0.021

10.8

USB_OTG_VDDA33 +

USB_H1_VDDA33

VDDO25 + USB_OTG_VDDA25 +

USB_H1_VDDA25

2.75

12.45

34.239

NVCC_RESET

NVCC_SRTC

Total

3.1

1.3

—

0.226

0.0035

—

0.701

0.0045

1120

1

During eFuse programming, the maximum current on VDD2P5 will exceed these values. See Table 13 on page 26 for the

maximum VDD2P5 current during eFuse programming.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

27

Electrical Characteristics

Table 15. Maximum Supply Current Consumption—ARM CLK = 1 GHz

Condition

Supply

Voltage (V) Current (mA) Power (mW)

• T

a

= 70°C

VDDGP

VCC

1.35

1.275

1.35

1.3

1000

220

40

1350

280.5

54

• ARM core in Run mode

• ARM CLK = 1GHz

• SYS CLK = 266 MHz

• AHB CLK = 133 MHz

• DDR CLK = 266 MHz

• All voltages operating at maximum

levels

• External (MHz) crystal and on-chip

oscillator enabled

• All modules enabled

VDDA/VDDAL1

VDD1P2

15

19.5

5.9

VDD1P8

1.95

2.75

3.3

3

VDD2P5¹

2

5.5

VDD3P0

2

6.6

NVCC_EMI_DRAM

VDD_DCDCi

1.95

3.6

8.3

0.021

10.8

16.17

0.041

38.8

USB_OTG_VDDA33 +

USB_H1_VDDA33

VDDO25 + USB_OTG_VDDA25 +

USB_H1_VDDA25

2.75

12.45

34.239

NVCC_RESET

NVCC_SRTC

Total

3.1

1.3

—

0.226

0.0035

—

0.701

0.0045

1812

1

During eFuse programming, the maximum current on VDD2P5 will exceed these values. See Table 13 on page 26 for the

maximum VDD2P5 current during eFuse programming.

Table 16. Stop Mode Current and Power Consumption ¹

Current (mA)

Supply

Voltage (V)

Typical, T

a

= 25°C

Max, Ta = 25°C

VDDGP

VCC

0.85

0.95

0.057

0.544

0.071

0.198

1.890

0.247

VDDA/VDDAL1

1

The typical power, at Ta = 25°C, will be < 1 mW, including all supplies. Total max power, at Ta=25°C, will not exceed 2.5 mW,

including all supplies.

4.1.5.1

Conditions for Stop Mode Current and Power Consumption

•

ARM core in STOP mode and power gated

VDDGP, VCC, and VDDA/VDDAL1 voltages at suspend levels

VDD3P0, VDD2P5, VDD1P8, and VDD1P2 powered off

USB_VDDA25 and USB_VDDA33 powered off

i.MX50 Applications Processors for Consumer Products, Rev. 7

28

Freescale Semiconductor

Electrical Characteristics

•

All other supply voltages at nominal levels

External (MHz) crystal and on-chip oscillator disabled

CKIL input ON with 32 kHz signal present

All PLLs OFF, all CCM-generated clocks OFF

All modules disabled

No external resistive loads that cause current

4.1.6

USB-OH-1 (OTG + 1 Host Port) Current Consumption

Table 17 shows the USB interface current consumption.

Table 17. USB Interface Current Consumption

Parameter

Conditions

Full speed

Typical @ 25 °C

Max

Unit

Analog supply 3.3 V

USB_H1_VDDA33

USB_OTG_VDDA33

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

5.5

7

6

8

mA

High speed

Full speed

High speed

Full speed

High speed

5

6

5

6

Analog supply 2.5 V

USB_H1_VDDA25

USB_OTG_VDDA25

6.5

12

21

6

7

mA

7

13

22

7

Digital supply

VCC (1.2 V)

6

7

6

7

6

7

4.2

Supply Power-Up/Power-Down Requirements and Restrictions

The system design must comply with the power-up and power-down sequence guidelines as described in

this section to guarantee reliable operation of the device. Any deviation from these sequences can result in

the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the i.MX50 processor (worst-case scenario)

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

29

Electrical Characteristics

4.2.1

Power-Up Sequence

Figure 2 shows the power-up sequence.

Figure 2. Power-Up Sequence

NOTE

1) The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail is at its working voltage.

2) No power-up sequence dependencies exist between the supplies shown

shaded in gray.

4.2.2

Power-Down Sequence

The power-down sequence is recommended to be the opposite of the power-up sequence. In other words,

the same power supply constraints exist while powering off as while powering on.

4.2.3

Resume Sequence

When the i.MX50 is resuming from STOP mode, there are some special sequencing considerations. The

resume timing is determined by the following internal counters:

1. STBY_COUNT. This register is in the CCM block and may be set to a maximum of 16 x 32 kHz

cycles, or 500 μsec.

i.MX50 Applications Processors for Consumer Products, Rev. 7

30

Freescale Semiconductor

Electrical Characteristics

2. OSCNT. This register is in the CCM block and may be set to a maximum of 256 x 32 kHz cycles,

or 8 msec. This counter is intended to give the 24MHz clock time to start up and stabilize.

If the PMIC_RDY input is used and BYPASS_PMIC_VFUNCTIONAL_READY = 0, the i.MX50 will

wait for STBY_COUNT cycles after PMIC_STBY_REQ negation before checking PMIC_RDY status.

Once the STBY_COUNT has expired AND the PMIC_RDY signal has been asserted, the OSCNT counter

begins and the 24MHz oscillator is powered up. After OSCNT expires the processor will enter RUN mode.

If the PMIC_RDY input is not used, the processor will attempt to start the 24 MHz oscillator after

STBY_COUNT expires. So at a minimum, all the supplies necessary to start up the 24 MHz oscillator need

to be powered before STBY_COUNT expires: NVCC_SRTC,VDD1P2, VDD1P8, VDD2P5, VDD3P0.

After STBY_COUNT expires, the OSCNT counter begins and the 24 MHz oscillator is powered up. After

OSCNT expires the processor will enter RUN mode, so all other supplies need to be at the appropriate

operating levels before OSCNT expires.

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O and High-Speed General Purpose I/O (GPIO)

Double Data Rate 2 (DDR2)

Low Power Double Data Rate 2 (LPDDR2)

Low Power Double Data Rate 1(LPDDR1)

Low Voltage I/O (LVIO)

High Voltage I/O (HVIO)

Secure Digital Host Controllers (eSDHCv2 and eSDHCv3)

USB-OTG and USB Host ports

NOTE

The term OVDD in this section refers to the associated supply rail of an

input or output.

4.3.1

GPIO I/O DC Parameters

The parameters in Table 18 are guaranteed per the operating ranges in Table 11, unless otherwise noted.

Table 18. GPIO DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

MIN

Typ

MAX

Units

High-level output voltage

Voh

Ioh=-1mA

Ioh=spec’ed Drive

OVDD-0.15

0.8*OVDD

—

V

Low-level output voltage

Vol

Iol=1mA

—

0.15

V

Iol=specified Drive

0.2*OVDD

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

31

Electrical Characteristics

Table 18. GPIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

MIN

Typ

MAX

Units

High-level output current

(1.1-1.3V ovdd)

I

Voh=0.8*OVDD

Low Drive

Medium Drive

High Drive

—

-0.85

-1.7

-2.5

-3.4

Ioh

mA

Max Drive

Low-level output current (1.1-1.3V

ovdd)

I

Vol=0.2*OVDD

Low Drive

Medium Drive

High Drive

—

0.9

1.9

2.9

3.8

Iol

mA

Max Drive

High-level output current

(1.65-3.1V ovdd)

I

Voh=0.8*OVDD

Low Drive

Medium Drive

High Drive

-2.1

-4.2

-6.3

-8.4

Ioh

Max Drive

Low-level output current

(1.65-3.1V ovdd)

I

Vol=0.2*OVDD

Low Drive

Medium Drive

High Drive

2.1

4.2

6.3

8.4

Iol

Max Drive

High-Level DC input voltage ¹

Low-Level DC input voltage

Input Hysteresis

VIH

VIL

—

0.7*OVDD

0V

—

OVDD

0.3*OVDD

—

V

VHYS

OVDD=1.875

OVDD=2.775

0.25

0.34

0.45

Schmitt trigger VT+ ²

VT+

VT-

—

0.5*OVDD

—

0.5*OVDD

28

V

Schmitt trigger VT-

—

20

43

91

—

V

Pull-up resistor (22 KΩ PU)

Pull-up resistor (47 KΩ PU)

Pull-up resistor (100 KΩ PU)

Pull-down resistor (100 KΩ PD)

Input current (no pull-up/down)

Rpu

Rpd

IIN

Vi=OVDD/2

24

KΩ

nA

51

59

108

1.7

125

126

VI = 0

VI=OVDD

250

120

Input current (22 KΩ PU)

Input current (47 KΩ PU)

Input current (100 KΩ PU)

IIN

VI = 0

VI=OVDD

—

161

0.12

μA

VI = 0

VI=OVDD

76

0.12

VI = 0

VI=OVDD

36

0.12

i.MX50 Applications Processors for Consumer Products, Rev. 7

32

Freescale Semiconductor

Electrical Characteristics

Table 18. GPIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

MIN

Typ

MAX

Units

Input current (100 KΩ PD)

IIN

VI = 0

VI=OVDD

—

0.25

36

μA

External pull-up / pull-down

resistor required to overdrive

internal keeper

Rext

—

47

KΩ

1

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. VIL and VIH do not apply

when hysteresis is enabled.

2

Hysteresis of 250 mV is guaranteed overall operating conditions when hysteresis is enabled.

4.3.2

DDR2 I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The

JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. The

parameters in Table 19 are guaranteed per the operating ranges in Table 11, unless otherwise noted.

Table 19. DDR2 DC Electrical Characteristics

Test

Conditions

DC Electrical Characteristics

Symbol

MIN

TYP

MAX

Units

High-level output voltage

Low-level output voltage

Output min source current¹

Voh

Vol

—

0.9*ovdd

—

V

0.1*ovdd

—

Ioh(dc)

Iol(dc)

Vref

-7.5

—

mA

—

V

Output min sink current²

7.5

—

Input reference voltage

0.49*ovdd

Vref+0.125

-0.3

0.5*ovdd

—

0.51*ovdd

ovdd+0.3

Vref-0.125

ovdd+0.3

ovdd+0.6

Vref+0.04

DC input high voltage (data pins)

DC input low voltage (data pins)

DC input voltage³(clk pins)

DC differential input voltage⁴

Termination voltage⁵

Vihd(dc)

Vild(dc)

Vin(dc)

Vid(dc)

Vtt

—

V

-0.3

—

V

0.25

—

V

Vref-0.04

—

Vref

—

nA

Input current⁶(no pull-up/down)

Iin

VI = 0

VI=ovdd

0.07

2

5

360

Tri-state I/O supply current⁶

Icc-ovdd

VI = ovdd or 0

—

2.3

6.4

480

750

nA

Tri-state 2.5V predrivers supply

current⁶

Icc-vdd2p5

Tri-state core supply current⁶

Icc-vddi

VI = ovdd or 0

—

3.1

720

nA

1

ovdd=1.7 V; Vout=1.42 V. (Vout-ovdd)/Ioh must be less than 21 Ω for values of Vout between ovdd and ovdd-0.28 V.

ovdd=1.7 V; Vout=280 mV. Vout/Iol must be less than 21 Ω for values of Vout between 0 V and 280 mV.

Vin(dc) specifies the allowable dc excursion of each differential input.

2

3

4

Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “pure” input level and Vcp is the

“complementary” input level. the minimum value is equal to Vih(dc) - Vil(dc).

5

6

Vtt is expected to track ovdd/2.

Typ condition: typ model, 1.8 V, and 25 °C. Max condition: BCS model, 1.9 V, and 125 °C. Min condition: WCS model, 1.7 V,

and -40 °C.

i.MX50 Applications Processors for Consumer Products, Rev. 7

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33

Electrical Characteristics

4.3.3

Low Power DDR2 I/O DC Parameters

The LPDDR2 interface fully complies with JEDEC standard release April, 2008. The parameters in

Table 20 are guaranteed per the operating ranges in Table 11, unless otherwise noted.

Table 20. LPDDR2 I/O DC Electrical Parameters

DC Electrical Characteristics

Symbol

Test Conditions

MIN

TYP

MAX

Units

High-level output voltage

Low-level output voltage

Input reference voltage

DC input high voltage

Voh

Vol

—

0.9*ovdd

—

0.1*ovdd

0.51*ovdd

ovdd

V

—

0.5*ovdd

—

Vref

0.49*ovdd

Vref+0.13

ovss

—

V

Vih(dc)

Vil(dc)

Vih(diff)

Vil(diff)

Iin

DC input low voltage

—

Vref-0.13

—

V

Differential input logic high¹

Differential input logic low¹

Input current (no pull-up/down)

0.26

—

V

—

-0.26

V

VI = 0

VI=ovdd

—

0.02

1.5

12.8

290

nA

Tri-state I/O supply current²

Icc-ovdd

VI = ovdd or 0

—

1.85

5

400

700

nA

Tri-state 2.5 V predrivers supply

current²

Icc-vdd2p5

Tri-state core supply current²

Icc-vddi

—

VI = ovdd or 0

—

3

700

+15

nA

%

Pullup/Pulldown impedance

mismatch²

-15

—

240 Ω unit calibration resolution

—

10

Ω

1

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

2

Typ condition: typ model, 1.2V, and 25 °C. Max condition: BCS model, 1.3V, and 125 °C. Min condition: WCS model, 1.14V,

and -40 °C.

4.3.4

Low Power DDR1 I/O DC Parameters

The LPDDR1 interface fully complies with JEDEC standard release April, 2008. The parameters in

Table 21 are guaranteed per the operating ranges in Table 11, unless otherwise noted.

Table 21. LPDDR1 Mode DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

MIN

TYP

MAX

Units

High-level output voltage

Voh

Vol

Ioh=-0.1mA

0.9*ovdd

—

V

Low-level output voltage

Iol=0.1mA

0.1*ovdd

ovdd+0.3

0.3*ovdd

ovdd+0.3

ovdd+0.6

DC input high voltage (data pins)

DC input low voltage (data pins)

DC input voltage¹(clk pins)

DC input differential voltage²

Input current³(no pull-up/down)

Vihd(dc)

Vild(dc)

Vin(dc)

Vid(dc)

Iin

—

0.7*ovdd

-0.3

V

-0.3

V

0.4*ovdd

—

V

VI = 0

VI=ovdd

0.07

2

5

360

nA

Tri-state I/O supply current³

Icc-ovdd

VI = ovdd or 0

—

2.3

5.3

480

680

nA

Tri-state 2.5V predrivers supply

current³

Icc-vdd2

p5

Tri-state core supply current³

Icc-vddi

VI = ovdd or 0

—

3.1

720

nA

i.MX50 Applications Processors for Consumer Products, Rev. 7

34

Freescale Semiconductor

Electrical Characteristics

1

2

Vin(dc) specifies the allowable dc excursion of each differential input.

Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “pure” input level and Vcp is

the “complementary” input level. the minimum value is equal to Vih(dc) - Vil(dc).

3

Typ condition: typ model, 1.8 V, and 25 °C. Max condition: BCS model, 1.9 V, and 105 °C. Min condition: WCS model, 1.7 V,

and -20 °C.

4.3.5

Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 22 are guaranteed per the operating ranges in Table 11, unless otherwise noted.

Table 22. LVIO DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

MIN

Typ

MAX

Units

High-level output voltage

Voh

Ioh=-1mA

Ioh=spec’ed Drive

OVDD-0.15

0.8*OVDD

—

V

Low-level output voltage

High-level output current

Vol

Iol=1mA

Iol=specified Drive

—

0.15

0.2*OVDD

V

I

Voh=0.8*OVDD

Low Drive

Medium Drive

High Drive

—

-2.1

-4.2

-6.3

-8.4

Ioh

mA

Max Drive

Low-level output current

I

Vol=0.2*OVDD

Low Drive

Medium Drive

High Drive

—

2.1

4.2

6.3

8.4

Iol

mA

Max Drive

High-Level DC input voltage ¹

Low-Level DC input voltage

Input Hysteresis

VIH

VIL

—

0.7*OVDD

0V

—

OVDD

0.3*OVDD

—

V

VHYS

OVDD=1.875

OVDD=2.775

0.35

0.62

1.27

Schmitt trigger VT+ ²

VT+

VT-

—

0.5*OVDD

—

0.5*OVDD

28

V

Schmitt trigger VT-

—

20

43

91

—

V

Pull-up resistor (22 KΩ PU)

Pull-up resistor (47 KΩ PU)

Pull-up resistor (100 KΩ PU)

Pull-down resistor (100 KΩ PD)

Input current (no pull-up/down)

Rpu

Rpd

IIN

Vi=OVDD/2

24

KΩ

nA

51

59

108

1.7

125

126

VI = 0

VI=OVDD

250

120

Input current (22 KΩ PU)

Input current (47 KΩ PU)

Input current (100 KΩ PU)

IIN

VI = 0

VI=OVDD

—

161

0.12

μA

VI = 0

VI=OVDD

76

0.12

VI = 0

VI=OVDD

36

0.12

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

35

Electrical Characteristics

Table 22. LVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

MIN

Typ

MAX

Units

Input current (100 KΩ PD)

IIN

VI = 0

VI=OVDD

—

0.25

36

μA

External pull-up / pull-down

resistor required to overdrive

internal keeper

Rext

—

47

KΩ

1

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

2

Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.3.6

High Voltage I/O (HVIO) DC Parameters

Table 23 shows the HVIO DC electrical operating conditions. The parameters are guaranteed per the

operating ranges in Table 11, unless otherwise noted.

Table 23. HVIO DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

MIN

TYP

MAX

Units

High-level output voltage

Voh

Ioh=-1mA

Ioh=spec’ed Drive

OVDD-0.15

0.8*OVDD

—

V

Low-level output voltage

Vol

Iol=1mA

Iol=specified Drive

—

0.15

0.2*OVDD

V

High-level output current, low voltage

mode

Voh=0.8*OVDD

Low Drive

Medium Drive

High Drive

—

Ioh_lv

-2.2

-4.4

-6.6

mA

High-level output current, high voltage

mode

Vol=0.8*OVDD

Low Drive

Medium Drive

High Drive

—

Ioh_hv

Iol_lv

-5.1

-10.2

-15.3

Low-level output current, low voltage mode

Voh=0.2*OVDD

Low Drive

Medium Drive

High Drive

2.2

4.4

6.6

Low-level output current, high voltage

mode

Voh=0.2*OVDD

Low Drive

Medium Drive

High Drive

5.1

10.2

15.3

Iol_hv

High-Level DC input voltage¹

Low-Level DC input voltage

Input Hysteresis

VIH

VIL

—

0.7*OVDD

0V

—

OVDD

0.3*OVDD

—

V

VHYS

OVDD=1.875

OVDD=3.0

0.25

0.36

0.80

Schmitt trigger VT+²

Schmitt trigger VT-

VT+

VT-

—

0.5*OVDD

—

V

0.5*OVDD

i.MX50 Applications Processors for Consumer Products, Rev. 7

36

Freescale Semiconductor

Electrical Characteristics

Table 23. HVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

MIN

TYP

MAX

Units

Pull-up resistor (22 KΩ PU)

Pull-up resistor (47 KΩ PU)

Pull-up resistor (100 KΩ PU)

Pull-down resistor (100 KΩ PD)

Input current (no pull-up/down)

Rpu

Rpd

IIN

Vi=OVDD/2

22

43

46

53

—

29

59

62

77

2.8

71

KΩ

nA

148

156

256

VI = 0

VI=OVDD

470

50

Input current (22 KΩ PU)

Input current (47 KΩ PU)

Input current (100 KΩ PU)

Input current (100 KΩ PD)

IIN

VI = 0

VI=OVDD

—

153

0.05

μA

VI = 0

VI=OVDD

77

0.05

VI = 0

VI=OVDD

73

0.05

VI = 0

VI=OVDD

0.47

63

High-level output current, high voltage

mode

Vol=0.8*OVDD

Low Drive

Medium Drive

High Drive

—

Ioh_hv

Rext

-5.1

-10.2

-15.3

mA

External pull-up / pull-down

resistor required to overdrive

internal keeper

—

2.5

KΩ

1

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

2

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.4

Output Buffer Impedance Characteristics

This section defines the I/O impedance parameters of the i.MX50 processor.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

37

Electrical Characteristics

4.4.1

GPIO Output Buffer Impedance

Table 24 shows the GPIO output buffer impedance of the i.MX50 processor.

Table 24. GPIO Output Buffer Impedance

Typ

Parameter

Symbol

Test Conditions

Min

Max

Unit

OVDD

2.775 V

1.875V

Output driver

impedance

Rpu

Low drive strength, Ztl = 150 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

Max drive strength, Ztl = 37.5 Ω

80

40

27

20

104

52

35

150

75

51

250

125

83

Ω

26

38

62

Output driver

impedance

Rpd

Low drive strength, Ztl = 150 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

Max drive strength, Ztl = 37.5 Ω

64

32

21

16

88

44

30

22

134

66

44

243

122

81

Ω

34

61

4.4.2

LVIO Output Buffer Impedance

Table 25 shows the LVIO output buffer impedance of the i.MX50 processor.

Table 25. LVIO Output Buffer Impedance

Typ

Parameter

Symbol

Test Conditions

Min

Max

Unit

OVDD

2.775 V

1.875V

Output driver

impedance

Rpu

Low drive strength, Ztl = 150 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

Max drive strength, Ztl = 37.5 Ω

80

40

27

20

104

52

35

150

75

51

250

125

83

Ω

26

38

62

Output driver

impedance

Rpd

Low drive strength, Ztl = 150 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

Max drive strength, Ztl = 37.5 Ω

64

32

21

16

88

44

30

22

134

66

44

243

122

81

Ω

34

61

i.MX50 Applications Processors for Consumer Products, Rev. 7

38

Freescale Semiconductor

Electrical Characteristics

4.4.3

HVIO Output Buffer Impedance

Table 26 shows the HVIO output buffer impedance of the i.MX50 processor.

Table 26. HVIO Output Buffer Impedance

Min

Typ

Max

Unit

Parameter Symbol

Test Conditions

OVDD OVDD OVDD OVDD OVDD OVDD

1.95 V 3.3 V 1.875 V 3.30V 1.65 V 2.68 V

Output driver

impedance

Rpu

Rpd

Low drive strength, Ztl = 150 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

113.5 103.8

130.6

66

45.9

133

69.2

41

219.4 212.2

109.7 111.1

Ω

56.2

37.8

51.9

35.1

73.1

71.8

Output driver

impedance

Low drive strength, Ztl =1 50 Ω

Medium drive strength, Ztl = 75 Ω

High drive strength, Ztl = 50 Ω

78.5

39.7

26.8

70

34.5

23

113.6

56.8

38.3

102

50

33.3

230.8 179.5

115.4

76.9

89.8

60.7

NOTE

Output driver impedance is measured with long transmission line of

impedance Ztl attached to I/O pad and incident wave launched into

transmission line. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 3).

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

39

Electrical Characteristics

OVDD

PMOS (Rpu)

Ztl W, L = 20 inches

ipp_do

Pad

Predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

(do)

Vin

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

× Ztl

Vref2

Rpd =

Vovdd – Vref2

Figure 3. Impedance Matching Load for Measurement

i.MX50 Applications Processors for Consumer Products, Rev. 7

40

Freescale Semiconductor

Electrical Characteristics

4.5

I/O AC Parameters

The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. The AC

electrical characteristics for slow and fast I/O are presented in the Table 27 and Table 28, respectively.

Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUX control

registers.

From output

Under test

Test point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

NVCC

0V

80%

20%

80%

20%

Output (at I/O)

tf

tr

Figure 5. Output Transition Time Waveform

4.5.1

GPIO I/O Slow AC Parameters

Table 27 shows the AC parameters for GPIO slow I/O.

Table 27. GPIO I/O Slow AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (Max Drive)

tr, tf

tps

15 pF

35 pF

1.91/1.52

3.07/2.65

ns

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)¹

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

Output Pad di/dt (Max Drive)

15 pF

35 pF

2.22/1.81

3.81/3.42

ns

15 pF

35 pF

2.88/2.42

5.43/5.02

15 pF

35 pF

4.94/4.50

10.55/9.70

ns

15 pF

35 pF

0.5/0.65

0.32/0.37

V/ns

mA/ns

tps

15 pF

35 pF

0.43/0.54

0.26/0.41

tps

15 pF

35 pF

0.34/0.41

0.18/0.2

tps

15 pF

35 pF

0.20/0.22

0.09/0.1

tdit

30

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

41

Electrical Characteristics

Parameter

Table 27. GPIO I/O Slow AC Parameters (continued)

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

tdit

trm

23

15

7

mA/ns

ns

Input Transition Times²

25

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

4.5.2

GPIO I/O Fast AC Parameters

Table 28 shows the AC parameters for GPIO fast I/O.

Table 28. GPIO I/O Fast AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (Max Drive)

tr, tf

tps

15 pF

35 pF

1.45/1.24

2.76/2.54

ns

Output Pad Transition Times (High

Drive)

15 pF

35 pF

1.81/1.59

3.57/3.33

ns

Output Pad Transition Times (Medium

Drive)

15 pF

35 pF

2.54/2.29

5.25/5.01

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)¹

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

4.82/4.50

10.54/9.95

ns

15 pF

35 pF

0.69/0.78

0.36/0.39

V/ns

tps

15 pF

35 pF

0.55/0.62

0.28/0.30

tps

15 pF

35 pF

0.39/0.44

0.19/0.20

tps

15 pF

35 pF

0.21/0.22

0.09/0.1

Output pad di/dt (Max drive)

Output pad di/dt (High drive)

Output pad di/dt (Medium drive)

Output pad di/dt (Low drive)

Input transition times²

tdit

trm

—

70

53

35

18

25

mA/ns

ns

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

i.MX50 Applications Processors for Consumer Products, Rev. 7

42

Freescale Semiconductor

Electrical Characteristics

4.5.3

LVIO I/O Slow AC Parameters

Table 27 shows the AC parameters for LVIO slow I/O.

Table 29. LVIO I/O Slow AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (Max Drive)

tr, tf

tps

15 pF

35 pF

1.97/1.57

3.12/2.70

ns

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)¹

Output Pad Slew Rate (High Drive)

15 pF

35 pF

2.29/1.87

3.79/3.44

ns

15 pF

35 pF

2.93/2.48

5.42/4.98

15 pF

35 pF

4.92/4.57

10.64/9.85

ns

15 pF

35 pF

0.50/0.63

0.32/0.37

V/ns

tps

15 pF

35 pF

0.43/0.53

0.26/0.29

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

tps

15 pF

35 pF

0.34/0.40

0.18/0.20

tps

15 pF

35 pF

0.20/0.22

0.09/0.10

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

Input Transition Times²

tdit

trm

30

24

16

8

mA/ns

ns

25

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

43

Electrical Characteristics

4.5.4

LVIO I/O Fast AC Parameters

Table 30 shows the AC parameters for LVIO fast I/O.

Table 30. LVIO I/O Fast AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (Max Drive)

tr, tf

tps

15 pF

35 pF

1.44/1.27

2.78/2.56

ns

Output Pad Transition Times (High

Drive)

15 pF

35 pF

1.80/1.61

3.59/3.34

ns

Output Pad Transition Times (Medium

Drive)

15 pF

35 pF

2.55/2.28

5.32/5.01

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)¹

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

4.74/4.59

10.59/10.21

ns

15 pF

35 pF

0.69/0.78

0.36/0.39

V/ns

tps

15 pF

35 pF

0.55/0.61

0.28/0.30

tps

15 pF

35 pF

0.39/0.44

0.19/0.20

tps

15 pF

35 pF

0.21/0.22

0.09/0.10

Output pad di/dt (Max drive)

Output pad di/dt (High drive)

Output pad di/dt (Medium drive)

Output pad di/dt (Low drive)

Input transition times²

tdit

trm

—

70

54

35

18

25

mA/ns

ns

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

4.5.5

HVIO I/O Low Voltage (1.8 V) AC Parameters

Table 27 shows the AC parameters for HVIO I/O Low Voltage (1.8 V).

Table 31. HVIO I/O Low Voltage (1.8 V) AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (High Drive)

tr, tf

15 pF

35 pF

1.82/1.97

3.39/3.57

ns

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

15 pF

35 pF

2.48/2.62

4.95/5.14

ns

15 pF

35 pF

4.57/4.77

9.60/9.91

i.MX50 Applications Processors for Consumer Products, Rev. 7

44

Freescale Semiconductor

Electrical Characteristics

Table 31. HVIO I/O Low Voltage (1.8 V) AC Parameters (continued)

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Slew Rate (High Drive)¹

tr, tf

15 pF

35 pF

0.54/0.50

0.29/0.28

V/ns

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

0.40/0.38

0.20/0.19

V/ns

15 pF

35 pF

0.22/0.21

0.10/0.10

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

Input Transition Times²

tdit

trm

34

22

11

25

mA/ns

ns

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

4.5.6

HVIO I/O High Voltage (3.0 V) AC Parameters

Table 32 shows the AC parameters for HVIO I/O High Voltage (3.0 V).

Table 32. HVIO I/O High Voltage (3.0 V) AC Parameters

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times (High

Drive)

tpr

tps

15 pF

35 pF

2.16/1.79

3.75/3.28

ns

Output Pad Transition Times (Medium

Drive)

15 pF

35 pF

2.81/2.40

5.06/4.58

ns

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (High Drive)¹

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

4.69/4.15

8.91/8.51

ns

15 pF

35 pF

0.75/0.90

0.43/0.49

V/ns

15 pF

35 pF

0.57/0.67

0.32/0.35

15 pF

35 pF

0.34/0.39

0.18/0.19

Output pad di/dt (High drive)

Output pad di/dt (Medium drive)

Output pad di/dt (Low drive)

Input transition times²

tdit

trm

—

55

36

16

25

mA/ns

ns

1

tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

2

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4.5.7

DDR2 I/O AC Parameters

Table 33 shows the AC parameters for DDR2 I/O.

Table 33. DDR2 I/O AC Parameters

Parameter

AC input logic high

Symbol

Min

Max

Unit

Vih(ac)

Vil(ac)

Vid(ac)

Vix(ac)

Vref+0.25

-

AC input logic low

-

Vref-0.25

ovdd

AC differential input voltage¹

AC Input differential cross point voltage²

0.5

V

0.5*ovdd

-0.175

0.5*ovdd +

0.175

AC output differential cross point voltage ³

Vox(ac)

0.5*ovdd

-0.125

0.5*ovdd+

0.125

Output propagation delay high to low

Output propagation delay low to high

Input propagation delay high to low

Input propagation delay low to high

Single output slew rate

t

POHLD

POLHD

3.5

1.5

2

t

ns

t

PIHLD

t

PILHD

tsr

0.4

V/ns

¹Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the

“true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to

Vih(ac)-Vil(ac)

²The typical value of Vix(ac) is expected to be about 0.5*OVDD. and Vix(ac) is expected to track

variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

³The typical value of Vox(ac) is expected to be about 0.5*OVDD and Vox(ac) is expected to track

variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross.

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4.5.8

LPDDR1 I/O AC Parameters

Table 34 shows the AC parameters for LPDDR1 I/O.

Table 34. LPDDR1 I/O AC Parameters

Parameter

AC input logic high

Symbol

Min

Max

Unit

Vihd(ac)

Vild(ac)

Vid(ac)

Vix(ac)

0.8*ovdd

-0.3

ovdd+0.3

0.2*ovdd

ovdd+0.6

0.6*ovdd

2.5

AC input logic low

AC input differential voltage¹

0.6*ovdd

0.4*ovdd

V

AC input differential crosspoint voltage²

Output propagation delay high to low

Output propagation delay low to high

Input propagation delay high to low

Input propagation delay low to high

Single output slew rate

t

POHLD

POLHD

ns

t

2.5

t

PIHLD

PILHD

tsr

1.5

t

1.5

0.3

2.5

V/ns

¹Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is

the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is

equal to Vih(ac)-Vil(ac)

²The typical value of Vix(ac) is expected to be about 0.5*ovdd. and Vix(ac) is expected to

track variation of ovdd. Vix(ac) indicates the voltage at which differential input signal must

cross.

4.5.9

LPDDR2 I/O AC Parameters

Table 35 shows the AC parameters for LPDDR2 I/O.

Table 35. LPDDR2 I/O AC Parameters

Parameter

AC input logic high

Symbol

Min

Max

Unit

Vih(ac)

Vil(ac)

Vref+0.22

ovss

0.44

ovdd

Vref-0.22

-

AC input logic low

AC differential input high voltage¹

AC differential input low voltage

Vidh(ac)

Vidhl(ac)

Vix(ac)

V

-

0.44

AC input differential cross point voltage (relative

to ovdd / 2)²

-0.12

0.12

Over/undershoot peak

Vpeak

Varea

0.35

ns

Over/undershoot area (above OVDD or below

OVSS)

0.6 (at 266

MHz)

V-ns

Output propagation delay high to low

Output propagation delay low to high

Input propagation delay high to low

Input propagation delay low to high

t

POHLD

POLHD

3.5

1.5

ns

t

PIHLD

t

PILHD

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Table 35. LPDDR2 I/O AC Parameters (continued)

Parameter

Single output slew rate

Symbol

Min

Max

Unit

tsr

1.5

3.5

V/ns

(Driver impedance =40Ω+/-30%)

Single output slew rate

tsr

1

2.5

V/ns

(Driver impedance =60Ω+/-30%

¹Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the

“true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to

Vih(ac)-Vil(ac).

²The typical value of Vix(ac) is expected to be about 0.5*OVDD. and Vix(ac) is expected to track

variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

4.6

System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX50 processor.

4.6.1

Reset Timings Parameters

Figure 6 shows the reset timing and Table 36 lists the timing parameters.

RESET_IN_B

(Input)

CC1

Figure 6. Reset Timing Diagram

Table 36. Reset Timing Parameters

ID

Parameter

Min

Max

Unit

CC1

Duration of RESET_IN_B assertion to be qualified as valid (input slope =

5 ns)

50

—

ns

4.6.2

WDOG Reset Timing Parameters

Figure 7 shows the WDOG reset timing and Table 37 lists the timing parameters.

WDOG_RST_B

(Input)

CC5

Figure 7. WDOG_RST_B Timing Diagram

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Table 37. WDOG_RST_B Timing Parameters

ID

Parameter

Min

Max

Unit

CC5

Duration of WDOG_RST_B Assertion

1

—

T_CKIL

NOTE

is one period or approximately

CKIL is approximately 32 kHz. T

CKIL

30 μs.

4.6.3

Clock Amplifier Parameters (CKIH)

The input to clock amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required.

Table 38 shows the electrical parameters of CAMP.

Table 38. CAMP Electrical Parameters (CKIH)

Parameter

Min

Typ

Max

Unit

Input frequency

8.0

—

50

40.0

0.3

3

MHz

V

VIL (for square wave input)

VIH (for square wave input)

Sinusoidal input amplitude

Output duty cycle

0

(VCC¹– 0.25)

0.4 ²

V

VDD

55

Vp-p

%

45

1

VCC is the supply voltage of CAMP.

2

This value of the sinusoidal input is determined during characterization.

4.6.4

DPLL Electrical Parameters

Table 39 shows the electrical parameters of digital phase-locked loop (DPLL).

Table 39. DPLL Electrical Parameters

Parameter

Test Conditions/Remarks

Min

Typ

Max

Unit

Reference clock frequency range¹

—

10

—

100

40

MHz

Reference clock frequency range after

pre-divider

Output clock frequency range (dpdck_2)

Pre-division factor²

—

300

—

50

1025

16

MHz

—

1

Multiplication factor integer part

Multiplication factor numerator³

Multiplication factor denominator²

Output duty cycle

—

5

–67108862

1

15

—

Should be less than denominator

67108862

67108863

51.5

—

48.5

%

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Electrical Characteristics

Parameter

Table 39. DPLL Electrical Parameters (continued)

Test Conditions/Remarks

Min

Typ

Max

Unit

Frequency lock time⁴

—

398

T_dpdref

(FOL mode or non-integer MF)

Phase lock time

—

0.02

2.0

—

100

0.04

3.5

µs

Frequency jitter⁵(peak value)

Phase jitter (peak value)

Power dissipation

—

T_dck

ns

FPL mode, integer and fractional MF

f_dck= 300 MHz @ avdd = 1.8 V,

dvdd = 1.2 V

f_dck= 650 MHz @ avdd = 1.8 V,

dvdd = 1.2 V

0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd)

mW

1

Device input range cannot exceed the electrical specifications of the CAMP, see Table 38.

2

3

4

5

The values specified here are internal to DPLL. Inside the DPLL, a 1 is added to the value specified by the user. Therefore, the

user has to enter a value 1 less than the desired value at the inputs of DPLL for PDF and MFD.

The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be

zero.

T_dpdrefis the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL

mode is 398 cycles of divided reference clock when DPLL starts after full reset.

T_dckis the time period of the output clock, dpdck_2.

4.6.5

General Purpose Media Interface (GPMI) Parameters

The i.MX50 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to

200 MB/s I/O speed and individual chip select.

It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing

mode separately described in the following paragraphs.

4.6.5.1

Asynchronous Mode AC Timing (ONFI 1.0 Compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 8, Figure 9, Figure 10

and Figure 11 depict the relative timing between GPMI signals at the module level for different

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operations under Asynchronous mode. Table 40 describes the timing parameters (NF1–NF17) that are

shown in the figures.

CLE

NF2

NF1

NF3

NF4

CEn

NF5

WE

NF6

NF7

ALE

NF8

NF9

Command

IO[7:0]

Figure 8. Command Latch Cycle Timing Diagram

CLE

CEn

NF1

NF4

NF3

NF10

NF11

NF5

NF8

WE

NF7

NF9

NF6

ALE

IO[7:0]

Address

Figure 9. Address Latch Cycle Timing Diagram

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CLE

NF1

NF3

CEn

NF10

NF11

NF5

NF8

WE

NF7

NF6

ALE

NF9

IO[7:0]

Data to NF

Figure 10. Write Data Latch Cycle Timing Diagram

CLE

CEn

NF14

NF15

NF13

RE

RB

NF17

NF16

NF12

IO[7:0]

Data from NF

Figure 11. Read Data Latch Cycle Timing Diagram

Table 40. Asynchronous Mode Timing Parameters¹

^GP^E^M^xa^I^m^C^p^lo^le^ck^T≈^im1ⁱⁿ0^g0^fM^oH^rz

Timing

T²= GPMI Clock Cycle³

ID

Parameter

Symbol

Unit

T = 10ns

Min.

Max.

Min.

Max.

NF1

NF2

NF3

NF4

CLE setup time

CLE hold time

CEn setup time

CE hold time

tCLS

tCLH

tCS

(AS+1)*T

(DH+1)*T

(AS+1)*T

(DH+1)*T

—

10

20

10

20

—

ns

tCH

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Table 40. Asynchronous Mode Timing Parameters¹(continued)

^GP^E^M^xa^I^m^C^p^lo^le^ck^T≈^im1ⁱⁿ0^g0^fM^oH^rz

Timing

T²= GPMI Clock Cycle³

ID

Parameter

Symbol

Unit

T = 10ns

Min.

Max.

Min.

Max.

NF5

NF6

WE pulse width

tWP

tALS

tALH

tDS

DS*T

10

ns

ALE setup time

ALE hold time

(AS+1)*T

(DH+1)*T

DS*T

—

10

20

10

—

NF7

NF8

Data setup time

Data hold time

NF9

tDH

DH*T

NF10

NF11

NF12

NF13

NF14

NF15

NF16

NF17

Write cycle time

WE hold time

tWC

tWH

tRR

(DS+DH)*T

DH*T

20

10

Ready to RE low

RE pulse width

READ cycle time

RE high hold time

Data setup on read

Data hold on read

(AS+1)*T

—

10

20

10

—

tRP

DS*T

tRC

(DS+DH)*T

tREH

tDSR

tDHR

DH*T

N/A

1

GPMI’s Async Mode output timing could be controlled by module’s internal register, say

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers’ setting. In the above table, we use AS/DS/DH representing these settings each.

2

3

T represents for the GPMI clock period.

AS minimum value could be 0, while DS/DH minimum value is 1.

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4.6.5.2

Source Synchronous Mode AC Timing (ONFI 2.x Compatible)

The following diagrams show the write and read timing of Source Synchronous Mode.

NF19

NF18

CE_N

NF20

CLE

NF21

NF20

ALE

CLK

NF21

NF22

W/R#

DQS

output

enable

CMD

ADD

DQ[7:0]

Output

enable

NF24

NF23

Figure 12. Source Synchronous Mode Command and Address Timing Diagram

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NF19

NF18

CE_N

CLE

NF25

NF23

NF26

NF24

NF25

ALE

CLK

NF22

W/R#

DQS

NF27

DQS

output

enable

DQ[7:0]

Output

enable

Figure 13. Source Synchronous Mode Data Write Timing Diagram

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Electrical Characteristics

NF19

NF18

CE_N

CLE

NF25

NF26

NF24

NF25

NF23

ALE

CLK

NF22

NF25

W/R#

DQS

output

enable

DQ[7:0]

Output

enable

Figure 14. Source Synchronous Mode Data Read Timing Diagram

Table 41. Source Synchronous Mode Timing Parameters¹

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF18

NF19

NF20

CE# access time

t_CE

t_CH

CE_DELAY*t_CK

0.5 *t_CK

—

ns

CE# hold time

Command/address DQ setup

time

t_CAS

0.5*t_CK

NF21

Command/address DQ hold

time

t_CAH

0.5*t_CK

—

ns

NF22

NF23

clock period

t_CK

5

—

ns

preamble delay

t_PRE

PRE_DELAY*t_CK

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Table 41. Source Synchronous Mode Timing Parameters¹(continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF24

NF25

NF26

NF27

postamble delay

t_POST

t_CALS

t_CALH

t_DQSS

POST_DELAY*t_CK

0.5*t_CK

—

ns

CLE and ALE setup time

CLE and ALE hold time

0.5*t_CK

Data input to first DQS

latching transition

t_CK

1

GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY,

HW_GPMI_TIMING_PREAMBLE_DELAY, and HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these

registers’ setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each.

4.6.5.3

Samsung Toggle Mode AC Timing

4.6.5.3.1

Command and Address Timing

NOTE

Samsung Toggle Mode command and address timing is the same as ONFI

1.0 compatible Async mode AC timing. Please refer to the above chapter for

details.

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4.6.5.3.2

Read and Write Timing

NF22

dev_clk

CE_N

0

CLE

ALE

0

WE_N

RE_N

1

NF24

NF23

0.5 tCK

DQS

0.5 tCK

DQ[7:0]

Figure 15. Samsung Toggle Mode Data Write Timing

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dev_clk

CE_N

NF18

0

CLE

ALE

0

1

1 tCK

WE_N

RE_N

NF24

1 tCK

NF23

1 tCK

DQS

DQ[7:0]

Figure 16. Samsung Toggle Mode Data Read Timing

Table 42. Samsung Toggle Mode Timing Parameters¹

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF18

NF19

NF20

CE# access time

CE# hold time

t_CE

t_CH

CE_DELAY*t_CK

0.5 *t_CK

—

ns

Command/address DQ setup

time

t_CAS

0.5*t_CK

NF21

NF22

Command/address DQ hold

time

t_CAH

t_CK

0.5*t_CK

7.5

—

ns

clock period

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Table 42. Samsung Toggle Mode Timing Parameters¹(continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF23

NF24

NF25

NF26

preamble delay

t_PRE

t_POST

t_CALS

t_CALH

(PRE_DELAY+1)*t_CK

POST_DELAY*t_CK

0.5*t_CK

—

ns

postamble delay

CLE and ALE setup time

CLE and ALE hold time

0.5*t_CK

1

GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY,

HW_GPMI_TIMING_PREAMBLE_DELAY, HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers’

setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each.

4.7

External Interface Module (EIM)

The following sections provide information on the EIM.

4.7.1

General EIM Timing

Figure 17, Figure 18, and Table 43 specify the timings related to the EIM module. All EIM output control

signals may be asserted and de-asserted by an internal clock synchronized to the EIM_BCLK rising edge

according to corresponding assertion/negation control fields.

,

WE1

WE2

WE3

...

EIM_BCLK

EIM_ADDR

WE4

WE5

WE7

WE9

WE6

EIM_CSx

WE8

EIM_RW

WE10

EIM_OE

WE11

WE13

WE12

EIM_EBx

WE14

EIM_LBA

WE15

WE17

WE16

EIM_DATA

Figure 17. EIM Outputs Timing Diagram

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EIM_BCLK

EIM_DATA

WE18

WE20

WE19

WE21

EIM_WAIT

Figure 18. EIM Inputs Timing Diagram

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Table 43. EIM Bus Timing Parameters ¹

BCD = 0 BCD = 1

Max

BCD = 2

BCD = 3

ID

Parameter

Min

Max

Min

Max

Min

Max

WE1 EIM_BCLK Cycle time²

t

—

2t

—

3t

—

4t

—

WE2 EIM_BCLK Low Level Width

0.4t

0.8t

1.2t

1.6t

WE3 EIM_BCLK High Level

Width

WE4 Clock rise to address valid³0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE5 Clock rise to address invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE6 Clock rise to EIM_CSx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE7 Clock rise to EIM_CSx

invalid

0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE8 Clock rise to EIM_RW valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE9 Clock rise to EIM_RW

invalid

0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE10 Clock rise to EIM_OE valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE11 Clock rise to EIM_OE invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE12 Clock rise to EIM_EBx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE13 Clock rise to EIM_EBx

invalid

0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE14 Clock rise to EIM_LBA valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

WE15 Clock rise to EIM_LBA

invalid

0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75

0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 2t – 1.25 2t + 1.75

WE16 Clock rise to Output Data

valid

WE17 Clock rise to Output Data

Invalid

WE18 Input Data setup time to

Clock rise

2

—

2

—

2

—

2

2.5

2

—

WE19 Input Data hold time from

Clock rise

2.5

2

2.5

2

2.5

2

WE20 EIM_WAIT setup time to

Clock rise

WE21 EIM_WAIT hold time from

Clock rise

2.5

1

t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed EIM_BCLK

frequency is 66.5 MHz. As a result, if BCD = 0, axi_clk must be 66.5 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk,

resulting in a EIM_BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 66.5 MHz, other buses are impacted

which are clocked from this source. See the CCM chapter of the MCIMX50 Applications Processor Reference Manual

(MCIMX50RM) for a detailed clock tree description.

≤

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2

3

EIM_BCLK parameters are being measured from the 50% point that is, high is defined as 50% of signal value and low is defined

as 50% as signal value.

For signal measurements High is defined as 80% of signal value and Low is defined as 20% of signal value.

4.7.2

Examples of EIM Accesses

Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, and Figure 24 give a few examples of basic EIM

accesses to external memory devices with the timing parameters mentioned previously for specific control

parameters settings.

EIM_BCLK

WE4

Last Valid Address

WE5

EIM_ADDR

EIM_CSx

EIM_RW

EIM_LBA

EIM_OE

Next Address

Address v1

WE6

WE7

WE14

WE10

WE12

WE15

WE11

WE13

EIM_EBx

WE18

EIM_DATA

D(v1)

WE19

Figure 19. Synchronous Memory Read Access, WSC=1

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EIM_BCLK

WE5

Address V1

WE4

Last Valid Address

EIM_ADDR

EIM_CSx

EIM_RW

EIM_LBA

EIM_OE

Next Address

WE6

WE7

WE8

WE9

WE14

WE15

WE13

WE12

WE16

EIM_EBx

WE17

EIM_DATA

D(V1)

Figure 20. Synchronous Memory, Write Access, WSC=1, WBEA=1, WBEN=1, and WADVN=0

EIM_BCLK

WE5

WE4

EIM_ADDR Last Valid Addr

Address V1

Address V2

WE15

WE6

WE7

EIM_CSx

EIM_RW

WE14

WE15

WE14

EIM_LBA

WE10

WE11

WE13

EIM_OE

WE12

EIM_EBx

WE21

WE20

EIM_WAIT

WE19

D(V1)

D(V1+1)

D(V2+1)

D(V2)

EIM_DATA

HalfworHdalfword

Halfword

WE18

Figure 21. Synchronous 16-Bit Memory, Two Non-Sequential 32-Bit Read Accesses, WSC=2, SRD=1, BCD=0

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Electrical Characteristics

EIM_BCLK

EIM_ADDR

EIM_CSx

EIM_RW

WE4

Last Valid Addr

WE6

WE5

Address V1

WE7

WE9

WE8

WE14

WE15

EIM_LBA

EIM_OE

WE12

WE13

EIM_EBx

WE21

WE20

EIM_WAIT

WE17

WE16

D(V2) D(V3) D(V4)

D(V1)

EIM_DATA

WE16

Figure 22. Synchronous Memory, Burst Write, BCS=1, WSC=4, SRD=1, and BCD=0

EIM_BCLK

WE17

WE5

WE16

WE4

EIM_ADDR/

EIM_DATA

Write Data

Address V1

LastValid Addr

WE6

WE7

WE9

EIM_CSx

EIM_RW

WE8

WE14

WE15

EIM_LBA

EIM_OE

WE10

WE11

EIM_EBx

Figure 23. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,

ADVA=1, ADVN=1, and ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode, the 16 MSBs are driven on the

data bus.

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Electrical Characteristics

EIM_BCLK

WE4

WE19

WE5

EIM_ADDR/

EIM_DATA

Last Valid Addr Address V1

WE6

Data

WE18

EIM_CSx

EIM_RW

WE7

WE15

WE14

EIM_LBA

EIM_OE

WE10

WE11

WE13

WE12

EIM_EBx

Figure 24. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=2

Figure 25, Figure 26, Figure 27, and Table 44 help to determine timing parameters relative to the chip

select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the

timing parameters mentioned above.

EIM_CSx

WE31

WE32

EIM_ADDR

EIM_RW

EIM_LBA

EIM_OE

Next Address

Last Valid Address

Address V1

WE39

WE35

WE37

WE40

WE36

WE38

EIM_EBx

WE44

EIM_DATA

D(V1)

WE43

Figure 25. Asynchronous Memory Read Access

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EIM_CSx

WE31

Last Valid Address

WE32

WE34

WE40

EIM_ADDR

Next Address

Address V1

WE33

EIM_RW

EIM_LBA

EIM_OE

WE39

WE45

WE41

WE46

EIM_EBx

WE42

EIM_DATA

D(V1)

Figure 26. Asynchronous Memory Write Access

EIM_CSx

WE31

WE32

EIM_ADDR

Next Address

Last Valid Address

Address V1

EIM_RW

EIM_LBA

EIM_OE

WE39

WE35

WE37

WE40

WE36

WE38

EIM_EBx

WE44

EIM_DATA

D(V1)

WE43

WE48

EIM_DTACK

WE47

Figure 27. DTACK Read Access

Table 44. EIM Asynchronous Timing Parameters Table Relative Chip Select

Determination by

ID

Parameter

Synchronous Measured

Min

Max

Unit

Parameters ¹

WE31 EIM_CSx valid to Address valid

WE4 – WE6 – CSA²

—

3 – CSA

3 – CSN

ns

WE32 Address invalid to EIM_CSx invalid WE7 – WE5 – CSN³

WE33 EIM_CSx valid to EIM_RW valid WE8 – WE6 + (WEA – CSA)

3 + (WEA – CSA)

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Electrical Characteristics

Table 44. EIM Asynchronous Timing Parameters Table Relative Chip Select (continued)

Determination by

Synchronous Measured

Parameters ¹

ID

Parameter

Min

Max

Unit

WE34 EIM_RW invalid to EIM_CSx invalid WE7 – WE9 + (WEN – CSN)

WE35 EIM_CSx valid to EIM_OE valid WE10 – WE6 + (OEA – CSA)

WE36 EIM_OE invalid to EIM_CSx invalid WE7 – WE11 + (OEN – CSN)

—

3 – (WEN_CSN)

3 + (OEA – CSA)

ns

3 – (OEN – CSN)

4

WE37 EIM_CSx valid to EIM_EBx valid

(Read access)

WE12 – WE6 + (RBEA – CSA)

3 + (RBEA – CSA) ns

5

WE38 EIM_EBx invalid to EIM_CSx invalid WE7 – WE13 + (RBEN – CSN)

(Read access)

—

3 – (RBEN – CSN) ns

WE39 EIM_CSx valid to EIM_LBA valid

WE14 – WE6 + (ADV – CSA)

—

3 + (ADVA – CSA)

3 – CSN

ns

WE40 EIM_LBA invalid to EIM_CSx invalid WE7 – WE15 – CSN

(ADVL is asserted)

WE41 EIM_CSx valid to Output Data valid WE16 – WE6 – WCSA

—

3 – WCSA

3 – CSN

ns

WE42 Output Data invalid to EIM_CSx

invalid

WE17 – WE7 – CSN

6

WE43 Input Data valid to EIM_CSx invalid

MAXCO + MAXDI

MAXCO +

—

ns

7

MAXDI

WE44 EIM_CSx invalid to Input Data invalid

0

—

ns

WE45 EIM_CSx valid to EIM_EBx valid

(Write access)

WE12 – WE6 + (WBEA – CSA)

—

3 + (WBEA – CSA) ns

–3 + (WBEN – CSN) ns

WE46 EIM_EBx invalid to EIM_CSx invalid WE7 – WE13 + (WBEN – CSN)

(Write access)

—

6

WE47 EIM_DTACK valid to EIM_CSx

invalid

MAXCO + MAXDTI

MAXCO + MA

—

ns

8

XDTI

WE48 EIM_CSx invalid to EIM_DTACK

invalid

0

1

2

3

4

5

6

Parameters WE4–WE21 value, see in the Table 44.

EIM_CSx Assertion. This bit field determines when EIM_CSx signal is asserted during read/write cycles.

EIM_CSx Negation. This bit field determines when EIM_CSx signal is negated during read/write cycles.

EIM_EBx Assertion. This bit field determines when EIM_EBx signal is asserted during read cycles.

EIM_EBx Negation. This bit field determines when EIM_EBx signal is negated during read cycles.

Output maximum delay from internal driving the FFs to chip outputs. The maximum delay between all memory controls

(EIM_ADDR, EIM_CSx, EIM_OE, EIM_RW, EIM_EBx, and EIM_LBA).

7

8

Maximum delay from chip input data to internal FFs. The maximum delay between all data input pins.

DTACK maximum delay from chip input data to internal FF.

4.8

DRAM Timing Parameters

This section includes descriptions of the electrical specifications of DRAM MC module which interfaces

external DDR2, LPDDR1, and LPDDR2 memory devices.

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Electrical Characteristics

4.8.1

DRAM Command & Address Output Timing—DDR2 and LPDDR1

The following diagrams and tables specify the timings related to the address and command pins, which

interfaces DDR2 and LPDDR1 memory devices.

DDR2

DDR3

DRAM_SDCLK_B

DRAM_SDCLK

DDR1

DRAM_CS0

DRAM_RAS

DRAM_CAS

DRAM_SDWE

DDR4

DDR5

DDR4

DDR5

DDR4

bank

row

bank

column

DRAM_ADDR

Figure 28. DRAM Command/Address Output Timing—DDR2 and LPDDR1

Table 45. EMI Command/Address AC Timing

ID

Description

Symbol

Min

Max

Unit

DDR1

DDR2

DDR3

DDR4

CK cycle time

tCK

tCH

tCL

tIS

3.75

—

ns

CK high level width

0.48 tCK

0.52 tCK

—

CK low level width

Address and control output setup time

0.5 tCK

- 0.3

DDR5

Address and control output hold time

tIH

0.5 tCK

- 0.3

—

ns

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Electrical Characteristics

4.8.2

DRAM Command and Address Output Timing—LPDDR2

The following diagrams and tables specify the timings related to the address and command pins, which

interface LPDDR2 memory devices.

DDR2

DDR3

DRAM_SDCLK_B

DRAM_SDCLK

DDR1

DRAM_CS0

DDR4

DDR5

DDR6

DRAM_A[9:0]

rise fall

DDR7

Figure 29. DRAM Command/Address Output Timing—LPDDR2

Table 46. EMI Command/Address AC Timing

ID

Description

Symbol

Min

Max

Unit

DDR1

DDR2

DDR3

DDR4

CK cycle time

tCK

tCH

tCL

tIS

3.75

—

ns

CK high level width

CK low level width

0.48 tCK

0.52 tCK

—

Control output setup time

0.5 tCK

- 0.3

DDR5

Control output hold time

Address output setup time

Address output hold time

Address output setup time

Address output hold time

tIH

tIS

tIH

tIS

tIH

0.5 tCK

- 0.3

—

ns

DDR6

CK >= 200 MHz

0.5 tCK

- 1.3

DDR7

CK >= 200 MHz

0.5 tCK

- 1.3

DDR6

CK < 200 MHz

1

DDR7

1

CK < 200 MHz

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NOTE

DDR6 and DDR7 can be adjusted by the parameter -DLL_WR_DELAY-;

The ideal case is that SDCLK is center aligned to the DRAM_A[9:0] data

valid window;

For this table, HW_DRAM_PHY23[14:8] (DLL_WR_DELAY) = 0x10;

4.8.3

DRAM Data Output Timing

The DRAM data output timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.

DRAM_SDCLK_B

DRAM_SDCLK

DDR10

DDR11

DDR12

DRAM_SDQS_B

DRAM_SDQS

DDR13

DDR14

DRAM_D &

DRAM_DQM

d0 d1 d2 d3

DDR15

DDR16

Figure 30. DRAM Data Output Timing

Table 47. DDR Output AC Timing

ID

Description

Symbol

Min

Max

Unit

DDR10

DDR11

Positive DQS latching edge to associated CK edge

DQS falling edge from CK rising edge—hold time

tDQSS

tDSH

-0.3

0.3

ns

0.5 tCK

- 0.3

0.5 tCK

+ 0.3

DDR12

DQS falling edge to CK rising edge—setup time

tDSS

0.5 tCK

- 0.3

0.5 tCK

+ 0.3

ns

DDR13

DDR14

DQS output high pulse width

tDQSH

tDQSL

tDS

0.48 tCK 0.52 tCK

ns

DQS output low pulse width

DDR15

CK >= 200 MHz

DQ & DQM output setup time relative to DQS

0.5 tCK

- 1.3

—

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Electrical Characteristics

Table 47. DDR Output AC Timing

Description Symbol

ID

Min

Max

Unit

DDR16

CK >= 200 MHz

DQ & DQM output hold time relative to DQS

DQ & DQM output setup time relative to DQS

DQ & DQM output hold time relative to DQS

tDH

tDS

tDH

0.5 tCK

- 1.3

—

ns

DDR15

CK < 200 MHz

1

—

ns

DDR16

1

CK < 200 MHz

NOTE

The DDR15,16 could be adjusted by the parameter “DLL_WR_DELAY”;

The ideal case is that SDQS is center aligned to the DRAM_D data valid

window;

For this table, HW_DRAM_PHY15[14:8] (DLL_WR_DELAY) = 0x10;

4.8.4

DRAM Data Input Timing

DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.

DRAM_SDCLK_B

DRAM_SDCLK

DDR20

DRAM_SDQS_B

DRAM_SDQS

DDR22

DDR21

DRAM_D

d0 d1 d2 d3

Figure 31. DRAM Data Input Timing

Table 48. DDR2 Input AC Timing

ID

Description

Positive DQS latching edge to associated CK edge

Symbol

Min

Max

Unit

DDR20

tDQSCK

-0.5 tCK

—

ns

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Electrical Characteristics

Table 48. DDR2 Input AC Timing

Description Symbol

ID

Min

Max

Unit

DDR21

DDR22

DQS to DQ input skew

DQS to DQ input hold time

tDQSQ

tQH

—

0.65

—

ns

0.45 tCK

-0.85

NOTE

The timing parameter DDR20(tDQSCK) is not strictly required by this

DRAM MC design.

4.9

External Peripheral Interfaces

The following sections provide information on external peripheral interfaces.

4.9.1

AUDMUX Timing Parameters

The AUDMUX provides programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module.

4.9.2

CSPI and eCSPI Timing Parameters

This section describes the timing parameters of the CSPI and eCSPI modules. The CSPI and eCSPI have

separate timing parameters for master and slave modes. The nomenclature used with the CSPI/eCSPI

modules and the respective routing of these signals is shown in Table 49.

Table 49. CSPI Nomenclature and Routing

Module

I/O Access

eCSPI1

eCSPI2

CSPI

GPIO, KPP, DISP0_DAT, CSI0_DAT, and EIM_D through IOMUX

DISP0_DAT, CSI0_DAT, and EIM through IOMUX

DISP0_DAT, EIM_A/D, SD1, and SD2 through IOMUX

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Electrical Characteristics

4.9.2.1

CSPI Master Mode Timing

Figure 32 depicts the timing of CSPI in master mode and Table 50 lists the CSPI master mode timing

characteristics.

CSPIx_DRYN1

CS11

CSPIx_CS_x

CS6

CS5

CS2

CS1

CS3

CS4

CSPIx_CLK

CSPIx_DO

CSPIx_DI

CS2

CS7 CS8

CS3

CS9

CS10

Figure 32. CSPI Master Mode Timing Diagram

Table 50. CSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

CS11

CSPIx_CLK Cycle Time

t

60

6

—

ns

clk

CSPIx_CLK High or Low Time

CSPIx_CLK Rise or Fall

t

SW

RISE/FALL

t

—

15

5

CSPIx_CS_x pulse width

CSPIx_CS_x Lead Time (CS setup time)

CSPIx_CS_x Lag Time (CS hold time)

CSPIx_DO Setup Time

t

CSLH

t

SCS

HCS

t

5

t

5

Smosi

Hmosi

CSPIx_DO Hold Time

t

5

CSPIx_DI Setup Time

t

5

Smiso

Hmiso

CSPIx_DI Hold Time

t

5

CSPIx_DRYN Setup Time

t

5

SDRY

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Electrical Characteristics

4.9.2.2

CSPI Slave Mode Timing

Figure 33 depicts the timing of CSPI in slave mode. Table 51 lists the CSPI slave mode timing

characteristics.

CSPIx_CS_x

CS5

CS6

CS2

CS1

CS3

CS4

CSPIx_CLK

CSPIx_DI

CS2

CS3

CS9

CS7

CS10

CS8

CSPIx_DO

Figure 33. CSPI Slave Mode Timing Diagram

Table 51. CSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

CSPIx_CLK Cycle Time

t

60

15

—

30

5

—

ns

clk

CSPIx_CLK High or Low Time

CSPIx_CLK Rise or Fall

t

SW

RISE/FALL

t

CSPIx_CS_x pulse width

CSPIx_CS_x Lead Time (CS setup time)

CSPIx_CS_x Lag Time (CS hold time)

CSPIx_DO Setup Time

t

CSLH

t

SCS

HCS

t

5

t

5

Smosi

Hmosi

CSPIx_DO Hold Time

t

5

CSPIx_DI Setup Time

t

5

Smiso

Hmiso

CSPIx_DI Hold Time

t

5

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Electrical Characteristics

4.9.2.3

eCSPI Master Mode Timing

Figure 34 depicts the timing of eCSPI in master mode and Table 52 lists the eCSPI master mode timing

characteristics.

eCSPIx_DRYN1

CS11

eCSPIx_CS_x

CS6

CS5

CS2

CS1

CS3

CS4

eCSPIx_CLK

eCSPIx_DO

eCSPIx_DI

CS2

CS7 CS8

CS3

CS9

CS10

Figure 34. eCSPI Master Mode Timing Diagram

Table 52. eCSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

eCSPIx_CLK Cycle Time–Read

eCSPIx_CLK Cycle Time–Write

t

60

15

—

ns

clk

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

CS11

eCSPIx_CLK High or Low Time

eCSPIx_CLK Rise or Fall

t

6

—

15

5

—

ns

SW

t

RISE/FALL

eCSPIx_CS_x pulse width

eCSPIx_CS_x Lead Time (CS setup time)

eCSPIx_CS_x Lag Time (CS hold time)

eCSPIx_DO Setup Time

t

CSLH

t

SCS

HCS

t

5

t

5

Smosi

Hmosi

eCSPIx_DO Hold Time

t

5

eCSPIx_DI Setup Time

t

5

Smiso

Hmiso

eCSPIx_DI Hold Time

t

5

eCSPIx_DRYN Setup Time

t

5

SDRY

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4.9.2.4

eCSPI Slave Mode Timing

Figure 35 depicts the timing of eCSPI in slave mode and Table 53 lists the eCSPI slave mode timing

characteristics.

eCSPIx_CS_x

CS5

CS6

CS2

CS1

CS3

CS4

eCSPIx_CLK

eCSPIx_DI

CS2

CS3

CS9

CS7

CS10

CS8

eCSPIx_DO

Figure 35. eCSPI Slave Mode Timing Diagram

Table 53. eCSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

eCSPIx_CLK Cycle Time–Read

eCSPIx_CLK Cycle Time–Write

t

60

15

—

ns

clk

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

eCSPIx_CLK High or Low Time

eCSPIx_CLK Rise or Fall

t

6

—

15

5

—

ns

SW

t

RISE/FALL

eCSPIx_CS_x pulse width

eCSPIx_CS_x Lead Time (CS setup time)

eCSPIx_CS_x Lag Time (CS hold time)

eCSPIx_DO Setup Time

t

CSLH

t

SCS

HCS

t

5

t

5

Smosi

Hmosi

eCSPIx_DO Hold Time

t

5

eCSPIx_DI Setup Time

t

5

Smiso

Hmiso

eCSPIx_DI Hold Time

t

5

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Electrical Characteristics

4.9.3

Enhanced Secured Digital Host Controller (eSDHCv2/v3) and uSDHC

AC Timing

This section describes the electrical information of the eSDHCv2/v3 and the uSDHC, which includes

SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.

4.9.3.1

SD/eMMC4.3 (Single Data Rate) eSDHCv3 and uSDHC AC Timing

Figure 36 depicts the timing of SD/eMMC4.3, and Table 54 lists the SD/eMMC4.3 timing characteristics.

SD4

SD2

SD1

SD5

SCK

SD3

CMD

SD6

DAT0

DAT1

output from eSDHCv2 to card

......

DAT7

SD7

SD8

CMD

DAT0

DAT1

......

input from card to eSDHCv2

DAT7

Figure 36. SD/eMMC4.3 Timing

Table 54. SD/eMMC4.3 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock Frequency (Low Speed)

f

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

PP

2

3

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

0

f

100

7

OD

WL

WH

SD2 Clock Low Time

t

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

t

7

—

ns

t

—

3

ns

TLH

THL

3

ns

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Electrical Characteristics

Table 54. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter Symbols Min

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

–2

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

ID

Max

Unit

SD6 eSDHC Output Delay

t

2

ns

OD

eSDHC Input Setup Time

t

2.5

—

ns

SD7

SD8

ISU

4

eSDHC Input Hold Time

t

IH

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

3

4

In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.9.3.2

eMMC4.4 (Dual Data Rate) eSDHCv3 and uSDHC AC Timing

Figure 37 depicts the timing of eMMC4.4, and Table 55 lists the eMMC4.4 timing characteristics. Be

aware that only DAT0-7 is sampled on both edges of clock (not applicable to CMD).

SD1

SCK

SD2

DAT0

DAT1

......

output from eSDHCv3 to card

......

DAT7

SD3

SD4

DAT0

DAT1

......

DAT7

input from card to eSDHCv3

Figure 37. eMMC4.4 Timing

Table 55. eMMC4.4 Interface Timing Specification

ID

Parameter

Symbols

Card Input Clock

Clock Frequency (MMC Full Speed/High Speed)

Min

Max

Unit

SD1

f

0

52

MHz

PP

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

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Electrical Characteristics

ID

Table 55. eMMC4.4 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

SD2

eSDHC Output Delay

t

–5

5

ns

OD

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD3

SD4

eSDHC Input Setup Time

eSDHC Input Hold Time

t

2.5

1.5

—

ns

ISU

t

IH

4.9.4

FEC AC Timing Parameters

This section describes the AC timing specifications of the FEC. The i.MX50 FEC supports 10/100 Mbps

RMII with MII serial management interface. The RMII and serial management signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.9.4.1

RMII Async Inputs Signal Timing (FEC_COL)

Table 56 lists RMII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous

input timings listed in Table 56.

Table 56. RMII Async Inputs Signal Timing

Num

Characteristics

Min

Max

Unit

M9

FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

.

FEC_COL

M9

Figure 38. MII Async Inputs Timing Diagram

4.9.4.2

RMII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 57 lists RMII serial management channel timings. Figure 39 shows RMII serial management

channel timings listed in Table 57. The MDC frequency should be equal to or less than 2.5 MHz to be

compliant with the IEEE 802.3 RMII specification. However, the FEC can function correctly with a

maximum MDC frequency of 15 MHz.

Table 57. RMII Transmit Signal Timing

ID

Characteristics

Min Max

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

0

—

18

0

—

5

ns

—

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

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Electrical Characteristics

Table 57. RMII Transmit Signal Timing (continued)

Characteristics

ID

Min Max

Unit

M14 FEC_MDC pulse width high

M15 FEC_MDC pulse width low

40% 60% FEC_MDC period

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

FEC_MDIO (input)

M11

M12

M13

Figure 39. RMII Serial Management Channel Timing Diagram

4.9.4.3

RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ± 50 ppm continuous

reference clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode

include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.

The RMII mode timings are shown in Table 58 and Figure 40.

Table 58. RMII Signal Timing

No.

Characteristics

Min

Max

Unit

M16

M17

M18

M19

M20

REF_CLK(FEC_TX_CLK) pulse width high

REF_CLK(FEC_TX_CLK) pulse width low

REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid

REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid

35%

2

65%

—

REF_CLK period

ns

—

16

FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to

REF_CLK setup

4

—

M21

REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold

2

—

ns

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Electrical Characteristics

M16

M17

REF_CLK (input)

M18

FEC_TXD[1:0] (output)

FEC_TX_EN

M19

CRS_DV (input)

FEC_RXD[1:0]

FEC_RX_ER

M20

M21

Figure 40. RMII Mode Signal Timing Diagram

2

4.9.5

I C Module Timing Parameters

2

This section describes the timing parameters of the I C module. Figure 41 depicts the timing of I C

2

module, and Table 59 lists the I C module timing characteristics.

IC11

IC9

IC10

I2DAT

I2CLK

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

Figure 41. I²C Bus Timing

Table 59. I²C Module Timing Parameters

Standard Mode

Supply Voltage =

1.65 V–1.95 V, 2.7 V–3.3 V

Fast Mode

Supply Voltage =

2.7 V–3.3 V

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

I2CLK cycle time

10

4.0

—

2.5

0.6

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

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Electrical Characteristics

Table 59. I²C Module Timing Parameters (continued)

Standard Mode

Fast Mode

Supply Voltage =

ID

Parameter

1.65 V–1.95 V, 2.7 V–3.3 V

2.7 V–3.3 V

Unit

Min

Max

Min

Max

1

2

1

2

IC4

IC5

Data hold time

0

3.45

—

0

0.9

—

µs

ns

µs

HIGH Period of I2CLK Clock

4.0

4.7

250

4.7

—

0.6

1.3

0.6

IC6

LOW Period of the I2CLK Clock

—

IC7

Set-up time for a repeated START condition

Data set-up time

—

3

IC8

—

100

1.3

IC9

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

—

4

IC10

IC11

IC12

1000

300

400

20 + 0.1C

—

300 ns

400 pF

b

—

Capacitive load for each bus line (C )

—

b

1

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the

falling edge of I2CLK.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.

2

A Fast-mode I C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line

2

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I C-bus specification)

before the I2CLK line is released.

4

C = total capacitance of one bus line in pF.

b

4.9.6

One-Wire (OWIRE) Timing Parameters

Figure 42 depicts the RPP timing, and Table 60 lists the RPP timing parameters.

One-WIRE Tx

“Reset Pulse”

One Wire Device Tx

“Presence Pulse”

OW2

OW3

One-Wire bus

(BATT_LINE)

OW1

OW4

t_R

Figure 42. Reset and Presence Pulses (RPP) Timing Diagram

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Electrical Characteristics

Table 60. RPP Sequence Delay Comparisons Timing Parameters

ID

OW1

Parameters

Reset Time Low

Symbol

Min

Typ

Max

Unit

1

t

480

15

511

—

µs

RSTL

OW2

OW3

OW4

Presence Detect High

Presence Detect Low

t

60

240

—

PDH

t

60

—

PDL

Reset Time High

t

480

512

RSTH

(includes recovery time)

1

In order not to mask signaling by other devices on the 1-Wire bus, t

+ t should always be less than 960 µs.

R

RSTL

Figure 43 depicts Write 0 Sequence timing, and Table 61 lists the timing parameters.

OW6

t

REC

One-Wire bus

(BATT_LINE)

OW5

Figure 43. Write 0 Sequence Timing Diagram

Table 61. WR0 Sequence Timing Parameters

ID

Parameter

Symbol

Min

Typ

Max

Unit

OW5

OW6

—

Write 0 Low Time

Transmission Time Slot

Recovery time

t

60

OW5

1

100

117

—

120

—

µs

LOW0

t

SLOT

t

REC

Figure 44 depicts Write 1 Sequence timing, Figure 45 depicts the Read Sequence timing, and Table 62

lists the timing parameters.

OW8

One-Wire bus

(BATT_LINE)

OW7

Figure 44. Write 1 Sequence Timing Diagram

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Freescale Semiconductor

Electrical Characteristics

OW8

One-Wire bus

(BATT_LINE)

t

SU

OW11

OW9

OW10

Figure 45. Read Sequence Timing Diagram

Table 62. WR1 /RD Timing Parameters

ID

Parameter

Write 1 Low Time

Symbol

Min

Typ

Max

Unit

OW7

OW8

—

t

1

60

—

1

5

117

—

5

15

120

1

µs

LOW1

Transmission Time Slot

Read Data Setup

Read Low Time

Read Data Valid

Release Time

t

SLOT

t

SU

OW9

OW10

OW11

t

15

—

LOWR

t

—

0

15

—

RDV

RELEASE

t

45

4.9.7

Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 46 depicts the timing of the PWM, and Table 63 lists the PWM timing parameters.

1

2a

3b

System Clock

2b

4b

3a

4a

PWM Output

Figure 46. PWM Timing

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Electrical Characteristics

Ref. No.

Table 63. PWM Output Timing Parameter

Parameter

Min

Max

Unit

1

System CLK frequency

0

12.29

9.91

—

ipg_clk

—

MHz

ns

2a

2b

3a

3b

4a

4b

Clock high time

Clock low time

Clock fall time

—

ns

0.5

ns

Clock rise time

Output delay time

Output setup time

—

0.5

ns

—

9.37

—

ns

8.71

ns

1

CL of PWMO = 30 pF

4.9.8

Secure JTAG Controller (SJC) Timing Parameters

Figure 47 depicts the SJC test clock input timing. Figure 48 depicts the SJC boundary scan timing.

Figure 49 depicts the SJC test access port. Figure 50 depicts the TRST timing. The signal parameters are

listed in Table 64.

SJ1

SJ2

VM

SJ2

VM

TCK

(Input)

VIH

VIL

SJ3

Figure 47. Test Clock Input Timing Diagram

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Electrical Characteristics

TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 48. Boundary Scan (JTAG) Timing Diagram

TCK

(Input)

VIH

VIL

SJ8

Input Data Valid

SJ9

TDI

TMS

(Input)

SJ10

SJ11

SJ10

TDO

Output Data Valid

(Output)

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 49. Test Access Port Timing Diagram

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Electrical Characteristics

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 50. TRST Timing Diagram

Table 64. JTAG Timing

All Frequencies

Min Max

ID

Parameter^1,2

Unit

1

SJ0

TCK frequency of operation 1/(3•T

TCK cycle time in crystal mode

)

0.001

45

22.5

—

22

—

3

MHz

ns

DC

SJ1

2

SJ2

SJ3

SJ4

SJ5

SJ6

TCK clock pulse width measured at

TCK rise and fall times

V

M

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data set-up time

5

—

40

—

44

—

24

—

SJ7

SJ8

—

5

SJ9

SJ10

SJ11

SJ12

SJ13

TMS, TDI data hold time

25

—

TCK low to TDO data valid

TCK low to TDO high impedance

TRST assert time

—

100

40

TRST set-up time to TCK low

= target frequency of SJC

1

T

DC

2

V = mid-point voltage

M

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Electrical Characteristics

4.9.9

SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 65.

Table 65. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

AUDMUX port 6

SSI 1

SSI 2

AUD3

AUD4

AUD5

AUD6

Internal

External— AUD3 I/O

External—EIM or CSPI1 I/O through IOMUX

External—EIM or SD1 I/O through IOMUX

External—EIM or DISP2 through IOMUX

NOTE

•

The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

The SSI timing diagrams use generic signal names wherein the names

used in the MCIMX50 Applications Processor Reference Manual

(MCIMX50RM) are channel specific signal names. For example, a

channel clock referenced in the IOMUXC chapter as AUD3_TXC

appears in the timing diagram as TXC.

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Electrical Characteristics

4.9.9.1

SSI Transmitter Timing with Internal Clock

Figure 51 depicts the SSI transmitter internal clock timing and Table 66 lists the timing parameters for

the SSI transmitter internal clock.

.

SS1

SS5

SS4

SS3

SS2

TXC

(Output)

SS8

SS6

TXFS (bl)

(Output)

SS10

SS12

SS14

SS17

TXFS (wl)

(Output)

SS15

SS16

SS18

TXD

(Output)

SS43

SS42

SS19

RXD

(Input)

Note: SRXD input in synchronous mode only

Figure 51. SSI Transmitter Internal Clock Timing Diagram

Table 66. SSI Transmitter Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

SS3

6.0

SS4

36.0

—

SS5

6.0

SS6

—

15.0

6.0

SS8

—

SS10

SS12

SS14

SS15

SS16

—

6.0

(Tx) CK high to STXD valid from high impedance

—

15.0

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Electrical Characteristics

Table 66. SSI Transmitter Timing with Internal Clock (continued)

ID

Parameter

(Tx) CK high to STXD high/low

Min

Max

Unit

SS17

SS18

SS19

—

15.0

6.0

ns

(Tx) CK high to STXD high impedance

STXD rise/fall time

Synchronous Internal Clock Operation

SS42

SS43

SS52

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

Loading

10.0

0.0

—

ns

pF

25.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in both the

tables and figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to word length (WL) and bit length (BL).

Tx and Rx refer to the transmit and receive sections of the SSI.

For internal frame sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.9.9.2

SSI Receiver Timing with Internal Clock

Figure 52 depicts the SSI receiver internal clock timing and Table 67 lists the timing parameters for the

receiver timing with internal clock.

SS1

SS3

SS5

SS4

SS2

TXC

(Output)

SS9

SS7

TXFS (bl)

(Output)

SS11

SS13

TXFS (wl)

(Output)

SS20

SS21

RXD

(Input)

SS51

SS50

SS47

SS49

SS48

RXC

(Output)

Figure 52. SSI Receiver Internal Clock Timing Diagram

Table 67. SSI Receiver Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

SS3

6.0

—

SS4

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

36.0

—

SS5

6.0

15.0

—

SS7

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

—

SS9

—

SS11

SS13

SS20

SS21

—

10.0

0.0

—

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Electrical Characteristics

Table 67. SSI Receiver Timing with Internal Clock (continued)

ID

Parameter

Min

Max

Unit

Oversampling Clock Operation

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

15.04

6.0

—

ns

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

3.0

—

6.0

—

3.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS as shown in both the

tables and figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

Tx and Rx refer to the transmit and receive sections of the SSI.

The terms WL and BL refer to word length (WL) and bit length (BL).

For internal frame sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.9.9.3

SSI Transmitter Timing with External Clock

Figure 53 depicts the SSI transmitter external clock timing and Table 68 lists the timing parameters for the

transmitter timing with external clock.

SS22

SS23

SS25

SS26

SS24

TXC

(Input)

SS27

SS29

TXFS (bl)

(Input)

SS33

SS31

TXFS (wl)

(Input)

SS39

SS37

SS38

TXD

(Output)

SS45

SS44

RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 53. SSI Transmitter External Clock Timing Diagram

Table 68. SSI Transmitter Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

6.0

—

36.0

—

6.0

15.0

—

–10.0

10.0

–10.0

10.0

—

15.0

—

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

15.0

—

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Electrical Characteristics

Table 68. SSI Transmitter Timing with External Clock (continued)

ID

Parameter

Min

Max

Unit

SS39

(Tx) CK high to STXD high impedance

—

15.0

ns

Synchronous External Clock Operation

SS44

SS45

SS46

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

SRXD rise/fall time

10.0

2.0

—

ns

6.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in both the

tables and figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

Tx and Rx refer to the transmit and receive sections of the SSI.

The terms WL and BL refer to word length (WL) and bit length (BL).

For internal frame sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.9.9.4

SSI Receiver Timing with External Clock

Figure 54 depicts the SSI receiver external clock timing and Table 69 lists the timing parameters for the

receiver timing with external clock.

SS22

SS26

SS25

SS24

SS23

TXC

(Input)

SS30

SS28

TXFS (bl)

(Input)

SS32

SS35

SS34

TXFS (wl)

(Input)

SS41

SS36

SS40

RXD

(Input)

Figure 54. SSI Receiver External Clock Timing Diagram

Table 69. SSI Receiver Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

(Tx/Rx) CK clock period

81.4

36

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

6.0

—

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

36

—

6.0

15.0

—

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

–10

10

–10

10

—

15.0

—

6.0

—

10

2

—

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Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in both the

tables and figures.

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

Tx and Rx refer to the transmit and receive sections of the SSI.

The terms WL and BL refer to word length (WL) and bit length (BL).

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

4.9.10 UART I/O Configuration and Timing Parameters

The following sections describe the UART I/O configuration and timing parameters.

4.9.10.1 UART RS-232 I/O Configuration in Different Modes

Table 70 shows the UART I/O configuration based on which mode is enabled.

Table 70. UART I/O Configuration vs. Mode

DTE Mode

Description

DCE Mode

Description

RTS from DTE to DCE

Port

Direction

RTS

Output

Input

RTS from DTE to DCE

Input

Output

Input

CTS

CTS from DCE to DTE

TXD_MUX

RXD_MUX

Input

Serial data from DCE to DTE

Serial data from DTE to DCE

Serial data from DCE to DTE

Serial data from DTE to DCE

Output

4.9.10.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

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Electrical Characteristics

4.9.10.2.1 UART Transmitter

Figure 55 depicts the transmit timing of UART in the RS-232 serial mode with 8 data bit/1 stop bit

format. Table 71 lists the UART RS-232 serial mode transmit timing characteristics.

Possible

UA1

Bit 3

Parity

Bit

Start

Bit

TXD

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 55. UART RS-232 Serial Mode Transmit Timing Diagram

Table 71. RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Transmit Bit Time

Symbol

Min

Max

+ T

Units

1

2

UA1

t

1/F

– T

1/F

—

Tbit

baud_rate

ref_clk

baud_rate

ref_clk

1

2

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

T

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

ref_clk

4.9.10.2.2 UART Receiver

Figure 56 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 72 lists

serial mode receive timing characteristics.

Possible

UA2

Parity

Bit

UA2

Bit 3

Bit

Start

Bit

RXD

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 56. UART RS-232 Serial Mode Receive Timing Diagram

Table 72. RS-232 Serial Mode Receive Timing Parameters

ID

UA2

Parameter

Symbol

Min

Max

+ 1/(16*F )

baud_rate

Units

1

2

Receive Bit Time

t

1/F

– 1/(16*F

)

1/F

—

Rbit

baud_rate

1

2

The UART receiver can tolerate 1/(16*F

) tolerance in each bit. But accumulation tolerance in one frame must not

baud_rate

exceed 3/(16*F

).

baud_rate

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

4.9.10.3 UART IrDA Mode Timing

The following sections give the UART transmit and receive timings in IrDA mode.

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Electrical Characteristics

4.9.10.3.1 UART IrDA Mode Transmitter

Figure 57 depicts the UART IrDA mode transmit timing with 8 data bit/1 stop bit format. Table 73 lists the

transmit timing characteristics.

UA4

UA3

TXD

(output)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 57. UART IrDA Mode Transmit Timing Diagram

Table 73. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

+ T

ref_clk

Units

1

2

UA3 Transmit Bit Time in IrDA mode

UA4 Transmit IR Pulse Duration

t

1/F

– T

1/F

—

TIRbit

baud_rate

ref_clk

baud_rate

t

(3/16)*(1/F

) – T

(3/16)*(1/F

) + T

baud_rate ref_clk

TIRpulse

baud_rate

ref_clk

1

2

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

T

: The period of UART reference clock ref_clk

(

ipg_perclk after RFDIV divider).

ref_clk

4.9.10.3.2

UART IrDA Mode Receiver

Figure 58 depicts the UART IrDA mode receive timing with 8 data bit/1 stop bit format. Table 74 lists the

receive timing characteristics.

UA6

UA5

RXD

(input)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 58. UART IrDA Mode Receive Timing Diagram

Table 74. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min.

Max.

+ 1/(16*F

Units

1

2

UA5 Receive Bit Time in IrDA mode

UA6 Receive IR Pulse Duration

t

1/F

– 1/(16*F

)

1/F

)

—

RIRbit

baud_rate

t

1.41

μ

s

(5/16)*(1/F

)

RIRpulse

baud_rate

1

2

The UART receiver can tolerate 1/(16*F

) tolerance in each bit. But accumulation tolerance in one frame must not

baud_rate

exceed 3/(16*F

).

baud_rate

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

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Electrical Characteristics

4.9.11 USB PHY Parameters

This section describes the USB OTG PHY and the USB host port PHY parameters.

4.9.11.1 USB PHY AC Parameters

Table 75 lists the AC timing parameters for USB PHY.

Table 75. USB PHY AC Timing Parameters

Parameter

Conditions

Min

Typ

Max

Unit

trise

1.5Mbps

12Mbps

480Mbps

75

4

0.5

—

300

20

ns

tfall

1.5Mbps

12Mbps

480Mbps

75

4

0.5

—

300

20

ns

Jitter

1.5Mbps

12Mbps

480Mbps

—

10

1

0.2

4.9.11.2 USB PHY Additional Electrical Parameters

Table 76 lists the parameters for additional electrical characteristics for USB PHY.

Table 76. Additional Electrical Characteristics for USB PHY

Parameter

Conditions

HS Mode

Min

Typ

Max

Unit

Vcm DC

–0.05

0.8

—

0.5

2.5

V

(dc level measured at receiver connector)

LS/FS Mode

Crossover Voltage

LS Mode

FS Mode

1.3

—

0

2

V

Power supply ripple noise

(analog 3.3 V)

< 160 MHz

–50

50

mV

Power supply ripple noise

(analog 2.5 V)

< 1.2 MHz

> 1.2 MHz

–10

–50

0

10

50

Power supply ripple noise

(Digital 1.2 V)

All conditions

–50

0

50

4.9.11.3 USB PHY System Clocking (SYSCLK)

Table 77 lists the USB PHY system clocking parameters

Table 77. USB PHY System Clocking Parameters

Parameter

Conditions

Min

Typ

Max

Unit

Clock deviation

Reference Clock

frequency 24 MHz

–150

—

150

200

ppm

ps

Rise/fall time

—

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Package Information and Contact Assignments

Table 77. USB PHY System Clocking Parameters (continued)

Parameter

Conditions

Min

Typ

Max

Unit

Jitter (peak-peak)

Duty-cycle

<1.2 MHz

>1.2 MHz

0

—

50

100

60

ps

%

Reference Clock

frequency 24 MHz

40

4.9.11.4 USB VBUS Parameters

Table 78 lists the USB VBUS input parameters.

Table 78. VBUS Comparators Thresholds

Parameter

Conditions

Min

Typ

Max

Unit

A-Device Session Valid Comparator

Threshold

—

0.8

1.4

2.0

V

B-Device Session Valid Comparator

Threshold

—

0.8

0.2

1.4

4.0

0.8

V

B-Device Session End Comparator

Threshold

0.45

1

VBUS Valid Comparator Threshold

—

4.4

3.0

—

4.6

—

4.75

—

V

VBUS for CHGR_DET_B Operation

VBUS Input Current

VBUS = 5.25 V

—

350

μA

1

For VBUS maximum rating, see Table 7.

5 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

5.1

13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information

This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball

grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin MAPBGA package.

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Package Information and Contact Assignments

5.1.1

Case 416 MAPBGA, 13 x 13 mm, 0.5 mm Pitch Package Views

Figure 59 shows the top view of the 13 x 13 mm package, Figure 60 shows the bottom view (416 soldier

balls) of the 13 x 13 mm package, and Figure 61 shows the side view of the 13 x 13 mm package.

Figure 59. 416 MAPBGA 13x13 mm Package Top View

Figure 60. 416 MAPBGA 13x13 mm Package Bottom View

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Package Information and Contact Assignments

Figure 61. 416 MAPBGA 13x13 mm Package Side View

The following notes apply to Figure 59, Figure 60, and Figure 61:

•

Unless otherwise specified dimensions are in millimeters.

All dimensions and tolerances conform to ASME Y14.5M-1994.

Parallelism measurement shall exclude any effect of mark on top surface of package.

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Package Information and Contact Assignments

5.1.2

416 MAPBGA 13 x 13 mm, 0.5 mm Pitch Ball Map

Table 79 shows the 416 MAPBGA 13 x 13 mm, 0.5 mm pitch ball map.

Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map

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Package Information and Contact Assignments

Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued)

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Package Information and Contact Assignments

Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued)

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Package Information and Contact Assignments

Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued)

5.1.3

416 MAPBGA 13 x 13 Power Rails

Table 80. 416 MAPBGA 13x13 Ground, Power, Sense, and Reference Contact Signals

Pin Name

Ball Number

Comments

GND_DCDC

W5

—

NVCC_EIM

L7, M7, M8

NVCC_EMI_DRAM

A21, AA21, AA23, AA24, AC21, AD21, B21, D21,

D23, D24, K21, K23, K24, R21, R23, R24

NVCC_EPDC

NVCC_JTAG

NVCC_KEYPAD

NVCC_LCD

M10, N10, P10, R10, U10

—

U9

N8

U11

P8

NVCC_MISC

NVCC_NANDF

NVCC_RESET

NVCC_SD1

V9, V10

V8

T7

NVCC_SD2

U8

NVCC_SPI

R7

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Table 80. 416 MAPBGA 13x13 Ground, Power, Sense, and Reference Contact Signals (continued)

NVCC_SRTC

NVCC_SSI

AA1

R8

—

NVCC_UART

USB_H1_VDDA25

T8

AD9

Note that on the 416 MAPBGA package,

USB_OTG_VDDA25 and USB_H1_VDDA25

are shorted together on the substrate.

USB_H1_VDDA33

USB_OTG_VDDA25

USB_OTG_VDDA33

AC11

AC9

Note that on the 416 MAPBGA package,

USB_OTG_VDDA33 and USB_H1_VDDA33

are shorted together on the substrate.

Note that on the 416 MAPBGA package,

USB_OTG_VDDA25 and USB_H1_VDDA25

are shorted together on the substrate.

AD11

Note that on the 416 MAPBGA package,

USB_OTG_VDDA33 and USB_H1_VDDA33

are shorted together on the substrate.

VCC

H14, H15, H16, H17, J17, K14, K15, K17, L15

—

VDD_DCDCI

VDD_DCDCO

VDD1P2

VDD1P8

VDD2P5

VDD3P0

VDDA

Y6

Y5

AD6

AD7

AD4

AD3

P17, R17

P15, R15

VDDAL1

VDDGP

G10, G8, G9, H10, H11, H8, H9, J8, K10, K11, K7,

K8, L10, L11, L8

VDDO25

VSS

N23

—

A1, A18, A24, AA11, AA2, AA9, AC18, AC3, AC4,

AC6, AC7, AD1, AD18, AD24, B18, G20, G21,

G23, H12, H13, K12, K13, L12, L13, L14, L17,

M11, M14, M15, M17, M18, M20, M21, N11, N14,

N15, N17, P11, P12, P13, P14, R11, R12, R13,

R14, T17, T18, U12, U13, U14, U15, U16, U17,

U18, V17, V18, V20, V21, V23

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Package Information and Contact Assignments

5.2

13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information

This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball

grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin PoPBGA package.

5.2.1

416 PoPBGA 13 x 13 mm Package Views

Figure shows the top view of the 416 PoPBGA 13 x 13 package, Figure 63 shows the side view of the

package, and Figure 64 shows the bottom view of the package.

Figure 62. 416 PoPBGA 13 x 13 mm Package Top View

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Package Information and Contact Assignments

Figure 63. 416 PoPBGA 13 x 13 Package Side View

Figure 64. 416 PoPBGA 13 x 13 mm Package Bottom View

The following notes apply to Figure , Figure 63, and Figure 64:

Unless otherwise specified dimensions are in millimeters.

•

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Package Information and Contact Assignments

•

All dimensions and tolerances conform to ASME Y14.5M-1994.

Parallelism measurement shall exclude any effect of mark on top surface of package.

5.2.2

416 PoPBGA 13 x 13 mm, 0.5 Pitch Ball Map

Table 81 shows the 416 PoPBGA 13 x 13 mm ball map.

Table 81. 416 PoPBGA 13 x 13 mm Ball Map

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Package Information and Contact Assignments

Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued)

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Package Information and Contact Assignments

Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued)

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Package Information and Contact Assignments

Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued)

5.2.3

416 PoPBGA 13 x 13 mm Power Rails

Table 82 shows the device connection list for ground, power, sense, and reference contact signals. Table 85

displays an alpha-sorted list of the signal assignments including power rails and associated power supplies.

Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals

Pin Name

GND_DCDC

Ball Number

Comments

W5

—

NVCC_EIM

N7 M7 M8

NVCC_EMI_DRAM

A21, B21, D21, D23, D24, E5, E6, E7, F5, G5, G7, K20, These are the 1.2V supply to both the

L20, M20, N20, P20, R20, V18, V20, W20, Y18, Y19, Y20 i.MX50 DRAM controller as well as the

PoP LPDDR2.

NVCC_EPDC

NVCC_JTAG

NVCC_KEYPAD

NVCC_LCD

M10, N10, P10, R10, U10

—

U9

N8

U11

P8

NVCC_MISC

NVCC_NANDF

V9, V10

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Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals (continued)

NVCC_RESET

NVCC_SD1

V8

—

T7

NVCC_SD2

U8

R7

AA1

R8

T8

NVCC_SPI

NVCC_SRTC

NVCC_SSI

NVCC_UART

POP_EMMC_RST

A19

This is PoP eMMC 4.4 NAND Reset

input pin. This pin does not connect to

the i.MX50. If using eMMC 4.4 NAND,

this pin can be connected to a GPIO.

For non 4.4 eMMC applications, leave

floating.

POP_LPDDR2_1.8V

POP_LPDDR2_ZQ0

A20, B19, B20, M5, N5

AA24

This is the 1.8V supply for the PoP

LPDDR2. These pins do not connect to

the i.MX50.

This is the PoP LPDDR2 ZQ0 pin. This

pin does not connect to the i.MX50.

This should be connected on the PCB

to a 240

Ω 1% resistor to ground

POP_LPDDR2_ZQ1

POP_NAND_VCC

AA23

This is the PoP LPDDR2 ZQ1 pin. This

pin does not connect to the i.MX50. If

used, this should be connected on the

PCB to a 240

Ω 1% resistor to ground

D19, D20

This is the 3.3V I/O and memory supply

for the PoP eMMC NAND. Note that

because the eMMC memory and I/O

domains are shorted together, it is not

possible to support 1.8 V I/O for the PoP

eMMC NAND.

USB_VDDA25

USB_VDDA33

AC9, AD9

Note that on the PoPBGA package,

USB_OTG_VDDA25 and

USB_H1_VDDA25 are shorted

together.

AC11, AD11

Note that on the PoPBGA package,

USB_OTG_VDDA33 and

USB_H1_VDDA33 are shorted

together.

VCC

H14, H15, H16, H17, J17, K14, K15, K17, L15

—

VDD_DCDCI

VDD_DCDCO

VDD1P2

Y6

Y5

AD6

AD7

VDD1P8

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Package Information and Contact Assignments

Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals (continued)

VDD2P5

VDD3P0

VDDA

AD4

—

AD3

P17, R17

P15, R15

VDDAL1

VDDGP

G10, G8, G9, H10, H7, H8, H9, J7, J8, K10, K7, K8, L10,

L7, L8

VDDO25

VSS

N23

—

A1, A24, AA11, AA18, AA2, AA9, AC18, AC3, AC4, AC6,

AC7, AD1, AD18, AD24, E17, E18, E21, E8, E9, F21,

G11, G12, G13, G21, G23, H11, H12, H13, K11, K12,

K13, L11, L12, L13, L14, L17, M11, M14, M15, M17, N11,

N14, N15, N17, P11, P12, P13, P14, R11, R12, R13,

R14, T17, U12, U13, U14, U15, U16, U17

5.3

17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package Information

This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball

grid location) for the 17 x 17 mm, 0.8 mm pitch, 400 pin MAPBGA package.

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Package Information and Contact Assignments

5.3.1

400 MAPBGA 17 x 17 mm Package Views

Figure 65 shows the top view of the 17 x 17 mm package, Figure 66 shows the bottom view of the

package, and Figure 67 shows the side view of the package.

C

B

17

A1 INDEX AREA

17

0.15

4x

Top View

Figure 65. 400 MAPBGA 17x17 mm Package Top view

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Package Information and Contact Assignments

Figure 66. 400 MAPBGA 17x17 mm Package Bottom View

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Package Information and Contact Assignments

Figure 67. 400 MAPBGA 17x17 mm Package Side View

The following notes apply to Figure 65, Figure 66, and Figure 67:

•

Unless otherwise specified dimensions are in millimeters.

All dimensions and tolerances conform to ASME Y14.5M-1994.

Parallelism measurement shall exclude any effect of mark on top surface of package.

5.3.2

400 MAPBGA 17 x 17 mm Ball Map

Table 83 shows the 400 MAPBGA 17 x 17 mm ball map.

Table 83. 400 MAPBGA 17 x 17 mm Ball Map

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Package Information and Contact Assignments

Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued)

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Package Information and Contact Assignments

Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued)

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Package Information and Contact Assignments

Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued)

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Package Information and Contact Assignments

5.3.3

400 MAPBGA 17 x 17 Power Rails

Table 84. 400 MAPBGA 17x17 Ground, Power, Sense, and Reference Contact Signals

Pin Name Ball Number

NC

A1 Y1 A20 Y20

F6 F7 F8

NVCC_EIM

NVCC_EMI_DRAM

NVCC_EPDC

NVCC_JTAG

NVCC_KEYPAD

NVCC_LCD

NVCC_MISC

NVCC_NANDF

NVCC_RESET

NVCC_SD1

NVCC_SD2

NVCC_SPI

NVCC_SRTC

NVCC_SSI

NVCC_UART

USB_H1_VDDA25

USB_H1_VDDA33

USB_OTG_VDDA25

USB_OTG_VDDA33

VCC

K14 N14 J15 K15 L15 N15 P15 H16 J16 K16 L16 M16 N16 P16 R16

F9 F10 F11 F12

P9

H5

P10

J5

P11 P12

P6

N5

P5

M5

R5

K5

L5

Y9

W11

W9

Y11

K10 L10 M10 K11 L11 M11 J12 K12 L12

VDD1P2

U6

VDD1P8

V6

VDD2P5

V5

VDD3P0

U5

VDDA

K9 J11

VDDAL1

J9 J10

VDDGP

G6 H6 J6 K6 L6 G7 H7 J7 K7 G8 H8 G9 H9 G10 H10

L17

VDDO25

VSS

T5 W5 M6 N6 L7 M7 N7 P7 J8 K8 L8 M8 N8 P8 L9 M9 N9 N10 R10 G11 H11 N11 R11 G12 H12

M12 N12 R12 G13 H13 J13 K13 L13 M13 N13 P13 R13 G14 H14 J14 L14 M14 P14 R14 H15

M15 R15

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Table 84. 400 MAPBGA 17x17 Ground, Power, Sense, and Reference Contact Signals (continued)

VDD_DCDCI

VDD_DCDCO

GND_DCDC

R7

T6

R6

5.4

Signal Assignments

Table 85. Alphabetical List of Signal Assignments

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

BOOT_MODE0

BOOT_MODE1

CHGR_DET_B

AB1

AB2

V11

AB1

AB2

V3

U3

NVCC_RESET

LVIO

ALT0

—

IN

100K PU

—

AA15

T10

USB_H1_VDDA25, ANALOG25

USB_H1_VDDA33

OUT-OD

CKIH

AA6

Y1

AA6

Y1

V4

Y4

NVCC_JTAG

NVCC_SRTC

NVCC_SPI

ANALOG

HVIO

—

IN

—

CKIL

—

CSPI_MISO

CSPI_MOSI

CSPI_SCLK

CSPI_SS0

DISP_BUSY

DISP_CS

DISP_D0

DISP_D1

DISP_D10

DISP_D11

DISP_D12

DISP_D13

DISP_D14

DISP_D15

DISP_D2

DISP_D3

DISP_D4

DISP_D5

M5

H2

K4

ALT1

ALT3

ALT1

ALT3

Keeper

M2

J1

L3

NVCC_SPI

M1

H1

M1

NVCC_SPI

M4

J2

J4

NVCC_SPI

AC12

AD14

AA12

Y12

Y17

V12

V13

V14

V15

V16

AA13

Y13

AA14

Y14

AA21

AC21

AC17

AC16

AD22

AD19

AC22

AC23

AB23

AD21

AD15

AC15

AC24

AB24

U11

T12

V11

T11

Y16

W14

V14

T13

U14

Y15

W12

W13

Y13

U13

NVCC_LCD

NVCC_NANDF

NVCC_LCD

OUT-LO 100K PU

IN

Keeper

OUT-LO 100K PU

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Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

DISP_D6

DISP_D7

AA15

Y15

AD16

AC19

AD17

AC20

AA20

AA19

AD23

AD20

V7

U12

V13

W15

V15

V12

T14

Y12

V10

T17

T18

J19

H19

E19

F19

—

NVCC_LCD

HVIO

ALT3

ALT1

ALT3

ALT1

ALT3

ALT0

—

OUT-LO 100K PU

DISP_D8

AA16

Y16

NVCC_NANDF

HVIO

IN

Keeper

DISP_D9

NVCC_NANDF

HVIO

DISP_RD

AD13

AC14

AC13

AD12

W20

W21

K20

NVCC_LCD

HVIO

OUT-LO 100K PU

IN Keeper

DISP_RESET

DISP_RS

NVCC_LCD

HVIO

NVCC_LCD

HVIO

OUT-LO 100K PU

DISP_WR

DRAM_A0

DRAM_A1

DRAM_A10

DRAM_A11

DRAM_A12

DRAM_A13

DRAM_A14

DRAM_A2

DRAM_A3

DRAM_A4

DRAM_A5

DRAM_A6

DRAM_A7

DRAM_A8

DRAM_A9

NVCC_LCD

HVIO

NVCC_EMI_DRAM

DRAM

OUT-LO

—

Keeper

—

Y7

—

J20

—

H20

F21

—

F20

—

Y20

Y8

U18

V18

R17

K19

L19

K20

L20

G19

F20

Y21

Y9

AA20

P20

Y10

P7

P21

L5

N20

N21

L21

K5

J5

H5

DRAM_CALIBRATI

ON

L20

P4

NVCC_EMI_DRAM DRAMCALI

B

DRAM_CAS

DRAM_CS0

DRAM_CS1

DRAM_D0

DRAM_D1

J21

T21

U21

Y24

Y23

—

U5

G20

P17

P18

R20

R19

NVCC_EMI_DRAM

DRAM

ALT0

OUT-HI

IN

Keeper

U7

V16

Y17

IN

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

DRAM_D10

DRAM_D11

DRAM_D12

DRAM_D13

DRAM_D14

DRAM_D15

DRAM_D16

DRAM_D17

DRAM_D18

DRAM_D19

DRAM_D2

DRAM_D20

DRAM_D21

DRAM_D22

DRAM_D23

DRAM_D24

DRAM_D25

DRAM_D26

DRAM_D27

DRAM_D28

DRAM_D29

DRAM_D3

DRAM_D30

DRAM_D31

DRAM_D4

DRAM_D5

DRAM_D6

DRAM_D7

DRAM_D8

DRAM_D9

G24

H23

F23

G20

H18

G18

F20

E20

E19

V11

Y11

V12

Y12

V17

V13

Y13

V14

Y14

G15

E15

E14

G14

E13

E12

U20

E11

E10

T20

U18

T18

R18

J18

E17

D19

D18

E18

C18

C17

Y19

Y18

V19

W19

P20

W20

W18

V20

U19

B19

B18

A16

B17

A17

A18

P19

A19

B20

N20

N18

M20

N19

D17

F18

NVCC_EMI_DRAM

DRAM

ALT0

IN

Keeper

F24

E24

E23

AC19

AD19

AC20

AD20

W23

AC22

AD22

AC23

AD23

B23

A23

A22

B22

B20

A20

W24

A19

B19

V24

U23

T23

U24

J23

H24

H20

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_OPEN

DRAM_OPENFB

DRAM_RAS

T24

J24

M18

L18

Y16

G17

—

N17

F17

U20

D20

H18

H17

E20

J20

NVCC_EMI_DRAM

DRAM

ALT0

IN

Keeper

—

IN

AC24

B24

J18

IN

OUT-LO

IN

H18

H21

K18

L18

—

OUT-HI

OUT-LO

OUT-HI

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE

DRAM_SDCLK_0

—

H20

M19

R18

J17

N18

U20

N24

M24

—

T5

R5

P5

NVCC_EMI_DRAM DRAMCLK

DRAM_SDCLK_0_

B

J18

DRAM_SDCLK_1

T20

R20

—

NVCC_EMI_DRAM DRAMCLK

ALT0

OUT-LO

OUT-HI

Keeper

—

DRAM_SDCLK_1_

B

DRAM_SDODT0

DRAM_SDODT1

DRAM_SDQS0

DRAM_SDQS0_B

DRAM_SDQS1

DRAM_SDQS1_B

DRAM_SDQS2

DRAM_SDQS2_B

DRAM_SDQS3

DRAM_SDQS3_B

DRAM_SDWE

ECKIL

G18

R18

P23

P24

L23

L24

AB23

AB24

C23

C24

P18

Y2

—

K18

—

NVCC_EMI_DRAM

DRAM

ALT0

—

OUT-LO

Keeper

—

OUT-LO

IN

N18

P18

J20

K18

Y15

V15

E16

G16

—

M17

M18

G17

G18

T19

T20

C19

C20

L18

W4

NVCC_EMI_DRAM DRAMCLK

IN

—

IN

—

IN

—

IN

—

IN

—

IN

—

IN

—

NVCC_EMI_DRAM

NVCC_SRTC

NVCC_SPI

DRAM

ANALOG

HVIO

OUT-HI

—

Keeper

—

Y2

ECSPI1_MISO

ECSPI1_MOSI

N7

K4

M3

ALT1

IN

Keeper

N2

N4

M4

NVCC_SPI

HVIO

IN

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

ECSPI1_SCLK

ECSPI1_SS0

ECSPI2_MISO

ECSPI2_MOSI

ECSPI2_SCLK

ECSPI2_SS0

EIM_BCLK

EIM_CRE

EIM_CS0

N1

P7

N5

P5

P4

N4

A5

A3

B10

D10

E10

A9

B9

D7

E7

A6

B6

D6

E6

D9

E9

A8

B8

D8

E8

A7

B7

A4

B4

E5

M4

L4

N2

N3

L4

NVCC_SPI

NVCC_EIM

HVIO

ALT1

ALT0

IN

Keeper

L2

K2

N1

N4

M2

A5

A3

B11

C9

D9

B10

B9

C6

D6

A6

B6

C5

D5

C8

D8

A9

B8

C7

D7

A7

B7

A4

B4

D4

L1

K1

A12

D13

B24

D17

D16

B23

C24

A14

B16

A16

A15

A13

B15

C23

A22

A23

B22

B18

B17

A18

A17

D15

D14

B13

OUT-LO 100K PU

OUT-HI

IN

100K PU

EIM_CS1

EIM_CS2

EIM_DA0

EIM_DA1

IN

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_DA2

IN

EIM_DA3

IN

EIM_DA4

IN

EIM_DA5

IN

EIM_DA6

IN

EIM_DA7

IN

EIM_DA8

IN

EIM_DA9

IN

EIM_EB0

OUT-HI

EIM_EB1

EIM_LBA

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

EIM_OE

EIM_RDY

B3

B12

B11

B14

A11

Y21

Y23

Y24

W24

V23

R21

J23

B3

NVCC_EIM

HVIO

ALT0

ALT1

OUT-HI

IN

100K PU

Keeper

A2

EIM_RW

B5

NVCC_EIM

OUT-HI

IN

EIM_WAIT

EPDC_BDR0

EPDC_BDR1

EPDC_D0

D5

C4

NVCC_EIM

E20

E21

A17

B17

D15

E15

A14

B14

D14

E14

D17

E17

A16

B16

D16

E16

A15

B15

A11

B11

A12

B12

G11

G12

A15

D16

B15

A14

D13

F14

F13

E14

E11

E13

B16

C16

D15

A13

C14

D14

E15

E16

A11

C10

A10

D11

E7

NVCC_EPDC

IN

EPDC_D1

IN

EPDC_D10

EPDC_D11

EPDC_D12

EPDC_D13

EPDC_D14

EPDC_D15

EPDC_D2

IN

M21

N21

P21

U23

V24

R24

T24

U24

T23

W23

T21

G24

J24

IN

EPDC_D3

IN

EPDC_D4

IN

EPDC_D5

IN

EPDC_D6

IN

EPDC_D7

IN

EPDC_D8

IN

EPDC_D9

IN

EPDC_GDCLK

EPDC_GDOE

EPDC_GDRL

EPDC_GDSP

EPDC_PWRCOM

IN

L23

P23

E23

E24

IN

EPDC_PWRCTRL

0

E10

IN

EPDC_PWRCTRL

1

G13

K23

E9

NVCC_EPDC

HVIO

ALT1

IN

Keeper

i.MX50 Applications Processors for Consumer Products, Rev. 7

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129

Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

EPDC_PWRCTRL

2

G14

G15

F23

L21

E12

F15

NVCC_EPDC

HVIO

ALT1

IN

Keeper

EPDC_PWRCTRL

3

EPDC_PWRSTAT

EPDC_SDCE0

EPDC_SDCE1

EPDC_SDCE2

EPDC_SDCE3

EPDC_SDCE4

EPDC_SDCE5

EPDC_SDCLK

EPDC_SDCLKN

EPDC_SDLE

EPDC_SDOE

EPDC_SDOED

EPDC_SDOEZ

EPDC_SDSHR

EPDC_VCOM0

EPDC_VCOM1

EPITO

G16

D13

E13

D12

E12

D11

E11

A13

B13

D18

E18

D19

E19

A10

G17

D20

G4

F24

N24

P24

H21

J21

K21

D18

K24

L24

M24

V21

R23

U21

H23

H24

W21

D8

C12

B12

A12

C11

E8

NVCC_EPDC

NVCC_MISC

VDD2P5

HVIO

ANALOG

HVIO

GPIO

ALT1

—

IN

—

IN

Keeper

—

D10

E6

B13

D12

C15

C13

G16

F16

A8

B14

G15

F5

EXTAL

AC5

AA7

E1

AC5

AA7

A6

W6

T7

GND_KEL

VDD2P5

—

I2C1_SCL

E1

NVCC_MISC

NVCC_JTAG

ALT1

ALT0

Keeper

100K PU

100K PD

I2C1_SDA

E2

B7

E2

I2C2_SCL

F1

A5

F1

I2C2_SDA

F2

B6

F2

I2C3_SCL

G1

A4

G1

I2C3_SDA

G2

B5

G2

JTAG_MOD

V7

V5

T8

JTAG_TCK

W4

R8

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRSTB

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

OWIRE

AA4

U7

Y4

AA4

V4

U8

T9

R9

U7

B1

B2

C1

C2

D1

D2

C3

D3

E5

Y3

Y2

Y5

E4

E3

W3

R1

P4

R2

P1

P3

P2

T1

T3

V1

R3

U1

NVCC_JTAG

NVCC_KEYPAD

NVCC_MISC

NVCC_SRTC

NVCC_RESET

NVCC_MISC

NVCC_RESET

NVCC_SD1

GPIO

HVIO

GPIO

LVIO

ALT0

ALT1

ALT0

ALT1

ALT0

ALT1

IN

OUT-LO

IN

47K PU

Keeper

47K PU

Keeper

—

Y4

AA5

B1

AA5

A9

IN

B2

A10

B9

IN

C1

C2

D1

D2

D4

E4

IN

B10

A8

IN

B8

IN

D7

IN

A7

IN

G7

W1

W2

AD2

F5

D12

W1

W2

AD2

D11

D10

AC1

M1

N1

IN

PMIC_ON_REQ

PMIC_STBY_REQ

POR_B

OUT-LO

IN

—

100K PU

Keeper

100K PU

Keeper

PWM1

HVIO

LVIO

IN

PWM2

F4

IN

RESET_IN_B

SD1_CLK

SD1_CMD

SD1_D0

AC1

P1

IN

HVIO

IN

R1

R2

P2

NVCC_SD1

IN

P2

NVCC_SD1

IN

SD1_D1

N2

NVCC_SD1

IN

SD1_D2

R4

R5

T4

M2

R4

NVCC_SD1

IN

SD1_D3

NVCC_SD1

IN

SD2_CD

J4

NVCC_SD2

IN

SD2_CLK

SD2_CMD

SD2_D0

U1

V5

E1

NVCC_SD2

IN

G1

D1

NVCC_SD2

IN

T1

NVCC_SD2

IN

SD2_D1

T2

D2

NVCC_SD2

IN

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131

Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

SD2_D2

SD2_D3

V1

V2

F1

F2

W2

T4

NVCC_SD2

HVIO

LVIO

ALT1

ALT0

ALT1

IN

Keeper

100K PD

Keeper

SD2_D4

V4

G2

V2

NVCC_SD2

SD2_D5

U2

E2

U2

NVCC_SD2

SD2_D6

U4

H4

R4

NVCC_SD2

SD2_D7

U5

F4

W1

T2

NVCC_SD2

SD2_WP

SD3_CLK

SD3_CMD

SD3_D0

T5

G4

NVCC_SD2

AD16

AD17

AC15

AC16

AC17

AA17

AA18

Y18

AA19

Y19

AD15

J7

T1

Y14

U16

Y17

V16

T16

U15

W17

U17

V17

T15

W16

H4

NVCC_NANDF

NVCC_SSI

T2

V1

SD3_D1

V2

SD3_D2

R1

SD3_D3

U2

SD3_D4

P1

SD3_D5

U1

SD3_D6

R2

SD3_D7

U4

SD3_WP

SSI_RXC

SSI_RXD

SSI_RXFS

SSI_TXC

SSI_TXD

SSI_TXFS

TEST_MODE

UART1_CTS

UART1_RTS

UART1_RXD

UART1_TXD

UART2_CTS

T4

AD12

AC14

AD13

AC13

AD14

AC12

AC2

B4

J5

F3

NVCC_SSI

H7

G5

NVCC_SSI

J4

G3

NVCC_SSI

H5

G4

NVCC_SSI

H4

H3

NVCC_SSI

AC2

H2

U4

NVCC_RESET

NVCC_UART

J1

HVIO

J2

B3

K2

J1

A2

K1

H1

A3

H1

K2

B2

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Package Information and Contact Assignments

Table 85. Alphabetical List of Signal Assignments (continued)

IOMUX

MUX

CTL

After

Reset

416

MAPBGA PoPBGA MAPBGA

Ball Ball Ball

Number Number Number

416

400

IOMUX

PAD CTL

After

Direction

After

Reset

Pin Power

Domain

Pin Name

Pad Type

Reset

UART2_RTS

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

UART4_RXD

UART4_TXD

USB_H1_DN

L2

L1

C2

C1

NVCC_UART

HVIO

ALT1

—

IN

—

Keeper

—

L2

L1

K1

B1

L4

E4

K3

J2

K4

D4

L5

D5

J3

K5

D6

H2

W10

AC10

USB_H1_VDDA25, ANALOG50

USB_H1_VDDA33

USB_H1_DP

AD10

Y11

AA10

Y10

AC8

AD8

Y7

AD10

AA17

AA10

AA16

AC8

Y10

U10

U9

V9

USB_H1_VDDA25, ANALOG50

USB_H1_VDDA33

—

USB_H1_GPANAI

O

USB_H1_VDDA25, ANALOG25

USB_H1_VDDA33

USB_H1_RREFEX

T

USB_H1_VDDA25, ANALOG25

USB_H1_VDDA33

USB_H1_VBUS

USB_OTG_DN

USB_OTG_DP

USB_H1_VDDA25, ANALOG50

USB_H1_VDDA33

W8

Y8

USB_OTG_VDDA25, ANALOG50

USB_OTG_VDDA33

AD8

USB_OTG_VDDA25, ANALOG50

USB_OTG_VDDA33

USB_OTG_GPANA

IO

AA14

AA12

AA8

V7

USB_OTG_VDDA25, ANALOG25

USB_OTG_VDDA33

USB_OTG_ID

Y8

Y7

USB_OTG_VDDA25, ANALOG25

USB_OTG_VDDA33

USB_OTG_RREFE

XT

AA8

Y9

W7

V8

USB_OTG_VDDA25, ANALOG25

USB_OTG_VDDA33

USB_OTG_VBUS

AA13

USB_OTG_VDDA25, ANALOG50

USB_OTG_VDDA33

VREF

WDOG

XTAL

M23

G5

M23

D9

K17

F4

VDDO25

NVCC_MISC

VDD2P5

ANALOG

HVIO

—

ALT1

—

IN

—

AD5

Y6

ANALOG

i.MX50 Applications Processors for Consumer Products, Rev. 7

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133

Revision History

6 Revision History

Table 86 provides a revision history for this data sheet.

Table 86. i.MX50 Data Sheet Document Revision History

Substantive Change(s)

Rev.

Number

Date

Rev. 7 10/2013 • Added new part number information for parts with 1 GHz core frequencies:

— MCIMX508CVK1B

— MCIMX508CVM1B

— MCIMX507CVM1B

— MCIMX507CVK1B

Updated sections:

— Section 1, “Introduction”

— Table 1, “Ordering Information”

— Table 11, “i.MX50 Operating Ranges”

— Table 15, “Maximum Supply Current Consumption—ARM CLK = 1 GHz” (added)

Rev. 6 07/2013 • In Table 11, “i.MX50 Operating Ranges,” added VCC Stop mode ranges.

Rev. 5 05/2013 • In Table 11, “i.MX50 Operating Ranges,” changed VCC peripheral supply (LPM) minimum voltage from

0.9 V to 1 V, and changed nominal voltage from 0.95 V to 1.05 V.

Rev. 4 01/2013 • In Table 1, "Ordering Information," on page 7, added new part number information for MCIMX507CVK8B.

• In Figure 27, "DTACK Read Access," on page 67, updated timing of EIM_DTACK.

Rev. 3 10/2012 • In Table 11, "i.MX50 Operating Ranges," on page 24:

—Changed DDR clock rate for reduced performance mode (RPM) of VCC from 100 MHz to 133 MHz

—Changed DDR clock rate for high performance mode (HPM) of VCC from 200 MHz to 266 MHz

Rev. 2 05/2012 • In Table 1, "Ordering Information," on page 7, added the following new part numbers: MCIMX508CZK8B,

MCIMX503CVK8B, MCIMX503EVM8B, MCIMX502CVK8B, and MCIMX502EVM8B.

• In Table 1, "Ordering Information," on page 7, added a new column, T

.

junction

• In Table 3, "Package Feature Comparison," on page 9, added a new row for 416 PoPBGA package.

• Updated Figure 1, "i.MX50 System Block Diagram," on page 10 by removing “LDOx3” and “DC-DC 1.2V.”

• In Table 5, "Special Signal Considerations," on page 17, updated details for the following signals:

DRAM_OPEN/DRAM_OPENFB and DRAM_SDODT0/DRAM_SDODT1

• In Table 5, "Special Signal Considerations," on page 17, added new rows for the following signals:

POP_EMMC_RST, POP_LPDDR2_ZQ0/ZQ1, POP_LPDDR2_1.8V, and POP_NAND_VCC.

• Added Section 4.1.2.1, “13 x 13 mm MAPBGA Package Thermal Resistance Data.”

• Added Section 4.1.2.2, “13 x 13 mm PoPBGA Package Thermal Resistance Data.”

• Added Section 4.1.2.3, “17 x 17 mm MAPBGA Package Thermal Resistance Data.”

• In Table 11, "i.MX50 Operating Ranges," on page 24, added footnotes for USB_OTG_VDDA25 and

USB_OTG_VDDA33.

• In Table 78, "VBUS Comparators Thresholds," on page 101, changed VBUS input max current to 350

• Added Section 5.2, “13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information.”

• In Table 85, "Alphabetical List of Signal Assignments," on page 124:

—Added a new column “416 PoPBGA Ball Number”

μA.

—Changed “USB_H1_VDDA” to “USB_H1_VDDA25, USB_H1_VDDA33”

—Changed “USB_OTG_VDDA” to “USB_OTG_VDDA25, USB_OTG_VDDA33”

• Replace mDDR with LPDDR1 throughout the document.

i.MX50 Applications Processors for Consumer Products, Rev. 7

134

Freescale Semiconductor

Revision History

Table 86. i.MX50 Data Sheet Document Revision History (continued)

Substantive Change(s)

Rev.

Number

Date

Rev. 1 10/2011 • Table 5, "Special Signal Considerations," on page 17 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 in the CHGR_DET_B signal remarks, added “The

maximum current leakage at this pin is 8.5 μA.”

• Table 5, "Special Signal Considerations," on page 17 in the JTAG_MOD remarks, changed “pull-down”

to “pull-up, by default” and added “If JTAG port is not needed, the internal pull-up can be disabled in order

to reduce supply current to the pin.”

th

• Table 14, "Maximum Supply Current Consumption—ARM CLK = 800 MHz," on page 27 in the 11 row

under the Supply column, changed VDDO2P5 to VDDO25.

• Table 78, "VBUS Comparators Thresholds," on page 101 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_0 pin number

was changed to N24 and DRAM_SDCLK_0_B pin number was changed to M24.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_1 pin number

was changed to T20 and DRAM_SDCLK_1_B pin number was changed to R20.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDQS0 pin number was

changed to P23 and DRAM_SDQS0_B pin number was changed to P24.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pin DRAM_CALIBRATION to

DRAMCALIB.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pins DRAM_SDCLK_0,

DRAM_SDCLK_0_B, DRAM_SDCLK_1, DRAM_SDCLK_1_B, DRAM_SDQS0, DRAM_SDQS0_B,

DRAM_SDQS1, DRAM_SDQS1_B, DRAM_SDQS2, DRAM_SDQS2_B, DRAM_SDQS3, and

DRAM_SDQS3_B to DRAMCLK.

Rev. 0 07/2011 Initial release.

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

135

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Document Number: IMX50CEC

Rev. 7

10/2013


型号：	MCIMX508CVK1B
厂家：	NXP
描述：	i.MX50 Applications Processors for Consumer Products
文件：	总136页 (文件大小：2523K)
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