MCIMX6G1AVM07AA [NXP]
i.MX 6UltraLite;型号: | MCIMX6G1AVM07AA |
厂家: | NXP |
描述: | i.MX 6UltraLite 时钟 以太网:16GBASE-T 外围集成电路 |
文件: | 总119页 (文件大小:1919K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: IMX6ULAEC
Rev. 2.2, 05/2017
NXP Semiconductors
Data Sheet: Technical Data
MCIMX6G1AVM05AA
MCIMX6G1AVM05AB
MCIMX6G1AVM07AB
MCIMX6G2AVM05AB
MCIMX6G2AVM07AB
MCIMX6G1AVM07AA
MCIMX6G2AVM05AA
MCIMX6G2AVM07AA
i.MX 6UltraLite
Automotive Applications
Processors
Package Information
Plastic Package
BGA 14 x 14 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
1. i.MX 6UltraLite introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Special signal considerations . . . . . . . . . . . . . . . 17
3.2. Recommended connections for unused analog
1 i.MX 6UltraLite introduction
The i.MX 6UltraLite is a high performance, ultra
efficient processor family featuring NXP’s advanced
®
implementation of the single ARM Cortex -A7 core,
which operates at speeds up to 696 MHz. The i.MX
6UltraLite includes an integrated power management
module that reduces the complexity of the external
power supply and simplifies the power sequencing. Each
processor in this family provides various memory
interfaces, including LPDDR2, DDR3, DDR3L, Raw
and Managed NAND flash, NOR flash, eMMC, Quad
SPI, and a wide range of other interfaces for connecting
peripherals, such as WLAN, Bluetooth™, GPS,
displays, and camera sensors.
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Chip-Level conditions . . . . . . . . . . . . . . . . . . . . . 20
4.2. Power supplies requirements and restrictions . . . 28
4.3. Integrated LDO voltage regulator parameters . . . 30
4.4. PLL’s electrical characteristics . . . . . . . . . . . . . . . 31
4.5. On-Chip oscillators . . . . . . . . . . . . . . . . . . . . . . . 33
4.6. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 34
4.7. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.8. Output buffer impedance parameters . . . . . . . . . 40
4.9. System modules timing . . . . . . . . . . . . . . . . . . . . 43
4.10. Multi-Mode DDR Controller (MMDC) . . . . . . . . . . 53
4.11. General-Purpose Media Interface (GPMI) timing 54
4.12. External peripheral interface parameters . . . . . . 62
4.13. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 95
5.2. Boot device interface allocation . . . . . . . . . . . . . . 96
6. Package information and contact assignments . . . . . . 103
6.1. 14x14 mm package information . . . . . . . . . . . . 103
6.2. GPIO reset behaviors during reset . . . . . . . . . . 116
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
The i.MX 6UltraLite is specifically useful for
automotive applications such as:
•
•
Telematics
Human Machine Interfaces (HMI)
© 2016-2017 NXP B.V.
i.MX 6UltraLite introduction
1
The features of the i.MX 6UltraLite processor include :
•
Single-core ARM Cortex-A7—The single core A7 provides a cost-effective and power-efficient
solution.
•
Multilevel memory system—The multilevel memory system of each device is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The device supports
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, NAND Flash (MLC and SLC), OneNAND™, Quad SPI, and managed NAND, including
eMMC up to rev 4.4/4.41/4.5.
•
Smart speed technology—Power management implemented throughout the IC that enables
multimedia features and peripherals to consume minimum power in both active and various low
power modes.
•
•
Dynamic voltage and frequency scaling—The processor improves the power efficiency by scaling
the voltage and frequency to optimize performance.
Multimedia powerhouse—Multimedia performance is enhanced by a multilevel cache system,
NEON™ MPE (Media Processor Engine) co-processor, a programmable smart DMA (SDMA)
controller, an asynchronous audio sample rate converter, and a Pixel processing pipeline (PXP) to
support 2D image processing, including color-space conversion, scaling, alpha-blending, and
rotation.
•
•
•
Ethernet interfaces—10/100 Mbps Ethernet controllers.
Human-machine interface—Support digital parallel display interface.
Interface flexibility—Each processor supports connections to a variety of interfaces: High-speed
USB on-the-go with PHY, multiple expansion card port (high-speed MMC/SDIO host and other),
12-bit ADC module, CAN port, smart card interface compatible with EMV Standard v4.3, and a
2
2
variety of other popular interfaces (such as UART, I C, and I S serial audio).
•
•
Automotive environment support—Each processor includes interfaces, such as CAN, three SAI
audio interfaces, and an asynchronous sample rate converter for multichannel/multisource audio.
Advanced security—The processor delivers hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6UltraLite Security
Reference Manual (IMX6ULSRM).
•
Integrated power management—The processor integrates linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
For a comprehensive list of the i.MX 6UltraLite features, see Section 1.2, “Features"”.
1. The actual feature set depends on the part numbers as described in the Table 1 and Table 2.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
2
NXP Semiconductors
i.MX 6UltraLite introduction
1.1
Ordering information
Table 1 provides examples of orderable part numbers covered by this data sheet. The automotive parts in
this subset of the i.MX 6UltraLite derivatives are single core devices offered in a 14x14 mm, 0.8 pitch
o
o
BGA whose temperature range is -40 C to 125 C. Each of these devices have differences in
characteristics or features according to the Table 2.
Table 1. Ordering Information
Core
Frequency
eFuse
Bits
Ethernet Ports
(10/100M)
Part Number
CAN
ADC
CSI
LCD IF
MCIMX6G1AVM05AA
MCIMX6G1AVM05AB
MCIMX6G1AVM07AA
MCIMX6G1AVM07AB
MCIMX6G2AVM05AA
MCIMX6G2AVM05AB
MCIMX6G2AVM07AA
MCIMX6G2AVM07AB
528 MHz
528 MHz
696 MHz
696 MHz
528 MHz
528 MHz
696 MHz
696 MHz
1024
1024
1024
1024
1536
1536
1536
1536
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
.
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
•
The i.MX 6UltraLite Automotive Applications Processors Data Sheet (IMX6ULAEC) covers parts
listed with an “A (Automotive temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/imx6series
or contact an NXP representative for details.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
3
i.MX 6UltraLite introduction
+
A
MC
IMX6
X
@
VV
$$
%
Silicon Rev
A
Rev. 1.0 (Maskset ID:
0N52P)
A
Qualification Level
MC
Prototype Samples
Mass Production
Special
PC
MC
SC
Rev. 1.1 (Maskset ID:
1N52P)
Rev. 1.2 (Maskset ID
2N52P)
B
Fuse Option
%
Reserved
A
i.MX 6 Family
X
ARM Cortex-A7 Frequency
528 MHz
$$
05
07
i.MX 6UltraLite
G
696 MHz
ROHS
VM
Package Type
Part Differentiator
@
Pac Enha Stand eFuse L2
USB Ethernet
with (10/100M)
PHY
C
A
N
U
A
R
T
I2 SPI I2S Timer ADC CSI
L
C
D
MAPBGA 14x14 0.8 mm
kage nced ard
Secur Secur
bit
Cache
C
/PWM
MAPBGA 9x9 0.5 mm
VK
ity
Y
Y
Y
Y
-
ity
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Commercial
Industrial
Commercial
Industrial
Automotive
Commercial
Industrial
Commercial
Industrial
2048 128 KB
2048 128 KB
2048 128 KB
2048 128 KB
1536 128 KB
1536 128 KB
1536 128 KB
1536 128 KB
1536 128 KB
1024 128 KB
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
4/8
4/8
4/8
4/8
4/8
4/8
4/8
4/8
4/8
4/8
2
2
2
2
2
2
2
2
2
1
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
VM
VK
3
2
Junction Temperature (Tj)
+
D
C
A
VM
VK
-
Commercial: 0 to + 95 °C
Industrial: -40 to +105 °C
Auto: -40 to + 125 °C
-
-
Automotive
Industrial
VM
VM
-
-
Y
-
1024 128 KB
2
1
1
1
1
0
8
4
4
2
4
2
3
1
4/8
2/4
1
1
-
-
-
-
1
0
Commercial
512
0 KB
Figure 1. Part Number Nomenclature—i.MX 6UltraLite
Table 2 shows the detailed information about peripherals.
1,2,3
Table 2. Detailed Peripherals Information
Peripheral Name
Ethernet
Instance G0 G1
G2
G3
ENET1
ENET2
OTG1
OTG2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NA
Y
NA
Y
USB with PHY
CAN
NA
NA
NA
NA
NA
Y
Y
FLEXCAN1
FLEXCAN2
CSI
Y
NA
NA
NA
Y
CSI
LCD
QSPI
LCDIF
QSPI
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
4
NXP Semiconductors
i.MX 6UltraLite introduction
1,2,3
Table 2. Detailed Peripherals Information (continued)
Instance G0 G1
uSDHC1
Peripheral Name
G2
G3
SDIO
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
uSDHC2
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART8
SIM1
Y
UART
Y
Y
Y
Y
NA
NA
NA
NA
NA
NA
Y
ISO7816-3
I2C
SIM2
I2C1
I2C2
Y
I2C3
NA
NA
Y
I2C4
SPI
ECSPI1
ECSPI2
ECSPI3
ECSPI4
SAI1
Y
NA
NA
Y
I2S/SAI
SAI2
NA
NA
SAI3
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
5
i.MX 6UltraLite introduction
1,2,3
Table 2. Detailed Peripherals Information (continued)
Peripheral Name
Instance G0 G1
G2
G3
Timer/PWM
EPIT1
EPIT2
GPT1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NA
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NA
Y
GPT2
NA
Y
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
ADC1
ADC2
Y
Y
Y
NA
NA
NA
NA
Y
ADC
NA
1
For detailed pin mux information, please refer to “Chapter 4 External Signals and Pin Multiplexing” of i.MX 6UltraLite
Reference Manual (IMX6ULRM).
2
Y stands for yes, NA stands for not available.
3
G0 and G3 are offered in automotive grade.
1.2
Features
The i.MX 6UltraLite processors are based on ARM Cortex-A7 MPCore™ Platform, which has the
following features:
•
Supports single ARM Cortex-A7 MPCore (with TrustZone) with:
— 32 KBytes L1 Instruction Cache
— 32 KBytes L1 Data Cache
— Private Timer
— Cortex-A7 NEON Media Processing Engine (MPE) Co-processor
General Interrupt Controller (GIC) with 128 interrupts support
Global Timer
•
•
•
•
•
•
Snoop Control Unit (SCU)
128 KB unified I/D L2 cache
Single Master AXI bus interface output of L2 cache
Frequency of the core (including Neon and L1 cache), as per Table 10, "Operating Ranges," on
page 23.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
6
NXP Semiconductors
i.MX 6UltraLite introduction
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia/shared, fast access RAM (OCRAM, 128 KB)
— Secure/non-secure RAM (32 KB)
•
External memory interfaces: The i.MX 6UltraLite processors support handheld DRAM, NOR, and
NAND Flash memory standards.
— 16-bit LP-DDR2-800, 16-bit DDR3-800 and LV-DDR3-800
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits.
— 16/8-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 6UltraLite processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
•
Displays:
— One parallel display port supports max 85 MHz display clock and up to WXGA (1366 x 768)
at 60 Hz
— Support 24-bit, 18-bit, 16-bit, and 8-bit parallel display
1
•
Camera sensors :
— One parallel camera port, up to 24 bit and 148.5 MHz pixel clock
— Support 24-bit, 16-bit, 10-bit, and 8-bit input
— Support BT.656 interface
•
Expansion cards:
— Two MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
•
•
USB:
— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps) with integrated HS USB Phy
Miscellaneous IPs and interfaces:
— Three SAI supporting up to three I2S
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Eight UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– Support RTS/CTS for hardware flow control
— Four enhanced CSPI (eCSPI)
1. G2 and G3 only
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
7
i.MX 6UltraLite introduction
2
— Four I C
— Two 10/100M Ethernet Controller (IEEE1588 compliant)
— Eight Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— One Quad SPI
— Two Flexible Controller Area Network (FlexCAN)
— Three Watchdog timers (WDOG)
— Two 12-bit Analog to Digital Converters (ADC) with up to 10 input channels in total
— Touch Screen Controller (TSC)
The i.MX 6UltraLite processors integrate advanced power management unit and controllers:
•
•
•
•
•
•
•
•
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Use Voltage Sensor for monitoring the die voltage
Support DVFS techniques for low power modes
Use SW State Retention and Power Gating for ARM and NEON
Support various levels of system power modes
Use flexible clock gating control scheme
Two smart card interfaces compatible with EVM Standard 4.3
The i.MX 6UltraLite processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption, while having the CPU core relatively free for performing other tasks.
The i.MX 6UltraLite processors incorporate the following hardware accelerators:
1
•
PXP—Pixel Processing Pipeline for imagine resize, rotation, overlay and CSC . Off loading key
pixel processing operations are required to support the LCD display applications.
•
ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
•
•
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
•
CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash
engines, 32 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).
•
•
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock.
CSU—Central Security Unit. CSU is configured during boot and by eFUSEs and determine the
security level operation mode as well as the TZ policy.
1. G2 and G3 only
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
8
NXP Semiconductors
i.MX 6UltraLite introduction
•
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1
and Table 2. Functions such as display and camera interfaces, connectivity
interfaces, and security features are not offered on all derivatives.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
9
Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX 6UltraLite processor system.
2.1
Block diagram
Figure 2 shows the functional modules in the i.MX 6UltraLite processor system.
/3ꢇ''5ꢅꢀ
ꢆꢀ''5ꢄ
%DWWHU\ꢀ&WUOꢀ
'HYLFH
-7$*
ꢁ,(((ꢈꢈꢊꢋ ꢌꢂꢃ
&U\VWDOꢀꢍꢀ
&ORFNꢀ6RXUFH
6HQVRUV
([WHUQDOꢀ0HPRU\
$50ꢀ&RUWH[ꢀ$ ꢃ
03&RUHꢀ3ODWIRUP
'HEXJ
&ORFNꢀꢁꢀ5HVHW
00&ꢆ6'
H00&ꢆH6'
1$1'ꢀ)/$6+
00'&
'$3
3//ꢀꢁꢂꢃ
&RUWH[ꢇ$ꢏꢀ&RUH
(,0
*30,ꢀꢍꢀ%&+
463,
73,8
&7,V
6-&
&&0
*3&
65&
,ꢐ ꢄꢅ.%ꢀ
1(21
'ꢐ ꢄꢅ.%ꢀ
(70
00&ꢆ6'
6';&
125ꢀ)/$6+
ꢁ3DUDOOHOꢃ
6&8ꢀꢍꢀ7LPHU
;7$/ꢀ26&
ꢄꢅ.ꢀ26&
/ꢅꢀ&DFKHꢀꢈꢅꢎ.%
7LPHUꢂ&RQWURO
6HFXULW\
:'2*ꢀꢁꢄꢃ
&$$0ꢀ
ꢁꢄꢅ.%ꢀ5$0 ꢃ
7RXFKꢀ3DQHOꢀ
&RQWURO
ꢁꢅꢃ
*37
,QWHUQDOꢀ0HPRU\
125ꢀ)/$6+
ꢁ4XDGꢀ63,ꢃ
&68
2&5$0ꢀꢈꢅꢎ.%
$3ꢀ3HULSKHUDOV
(3,7ꢀꢁꢅꢃ
)XVHꢀ%R[
X6'+&ꢀꢁꢅꢃ
520ꢀꢋꢂ.%
7HPSꢀ0RQLWRU
6196ꢀ
,ꢅ&ꢀꢁꢊꢃ
3:0ꢀꢁꢎꢃ
2&273
,208;&
76&
ꢁ657& ꢃ
.H\SDG
6PDUWꢀ'0$
6KDUHGꢀ3HULSKHUDOV
6'0$
$65&ꢀ
/&'ꢀ3DQHO
046ꢀ
ꢈꢉꢆꢈꢉꢉ0ꢀ
(WKHUQHWꢀ[ꢅ
H&63,ꢀꢁꢊꢃ
63',)ꢀ7[ꢆ5[
6$,ꢀꢁꢄꢃ
'LVSOD\ꢀ,QWHUIDFH
.33
,PDJHꢀ3URFVVLQJ
/&',)
3L[HOꢀ3URFHVVLQJꢀ3LSHOLQHꢀ
ꢁ3;3ꢃ
*3,2
(WKHUQHWꢀꢁꢅꢃ
&$1ꢀꢁꢅꢃ
86%ꢀ27*ꢀꢁꢅꢃ
&RQWUROOHUꢀ$UHD
1HWZRUN
8$57ꢀꢁꢎꢃ
&026ꢀ6HQVRU
&DPHUDꢀ,QWHUIDFH
3RZHUꢀ0DQDJHPHQW
6,0Yꢅꢀꢁꢅꢃ
&6,
/'2V
(096,0ꢀꢁꢅꢃ
86%ꢀ27*
ꢁGHYꢆKRVWꢃ
:/$1
0RGHPꢀ,&
'LJLWDOꢀ$XGLR
&$1ꢀ[ꢅ
.
1
Figure 2. i.MX 6UltraLite System Block Diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 2 for exceptions.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
10
NXP Semiconductors
Modules list
3 Modules list
The i.MX 6UltraLite processors contain a variety of digital and analog modules. Table 3 describes these
1
modules in alphabetical order.
Table 3. i.MX 6UltraLite Modules List
Block Mnemonic
Block Name
Subsystem
Brief Description
ADC1
ADC2
Analog to Digital
Converter
—
The ADC is a 12-bit general purpose analog to digital
converter.
ARM
ARM Platform
ARM
The ARM Core Platform includes 1x Cortex-A7 core. It
also includes associated sub-blocks, such as the Level
2 Cache Controller, SCU (Snoop Control Unit), GIC
(General Interrupt Controller), private timers, watchdog,
and CoreSight debug modules.
ASRC
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC)
converts the sampling rate of a signal associated to an
input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about -120dB
THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling
rates. The ASRC supports up to three sampling rate
pairs.
BCH
Binary-BCH ECC
Processor
System Control
Peripherals
The BCH module provides up to 40-bit ECC for NAND
Flash controller (GPMI)
CAAM
Cryptographic
accelerator and
assurance module
Security
CAAM is a cryptographic accelerator and assurance
module. CAAM implements several encryption and
hashing functions, a run-time integrity checker, and a
Pseudo Random Number Generator (PRNG). The
pseudo random number generator is certified by
Cryptographic Algorithm Validation Program (CAVP) of
National Institute of Standards and Technology (NIST).
Its deterministic random bit generator (DRBG)
validation number is 94 and its SHS validation number
is 1455.
CAAM also implements a Secure Memory mechanism.
In i.MX 6UltraLite processors, the security memory
provided is 32 KB.
CCM
GPC
SRC
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power
Controller, System Reset
Controller
Power Control
distribution in the system, and also for the system
power management.
CSI
Parallel CSI
Multimedia
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
1. Note that some modules listed in this table are not offered on all derivatives. See Table 2 for exceptions.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
11
Modules list
Table 3. i.MX 6UltraLite Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
CSU
Central Security Unit
Debug Access Port
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
6UltraLite platform.
DAP
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A7
Core Platform.
eCSPI1
eCSPI2
eCSPI3
eCSPI4
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit PSRAM memories (sync and async
operating modes), at slow frequency
• Support 16-bit NOR-Flash memories, at slow
frequency
• Multiple chip selects
EMV SIM1
EMV SIM2
Europay, Master and Visa
Subscriber Identification
Module
Connectivity
peripherals
EMV SIM is designed to facilitate communication to
Smart Cards compatible to the EMV version 4.3
standard (Book 1) and Smart Cards compatible with
ISO/IEC 7816-3 standard.
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EPIT1
EPIT2
Enhanced Periodic
Interrupt Timer
Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler for division of input clock frequency to
get the required time setting for the interrupts to occur,
and counter value can be programmed on the fly.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
12
NXP Semiconductors
Modules list
Table 3. i.MX 6UltraLite Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPMI
General Purpose
Memory Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices and
40-bit ECC for NAND Flash Controller (GPMI2). GPMI
supports separate DMA channels for each NAND
device.
GPT1
GPT2
General Purpose Timer
Timer peripherals Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
LCDIF
MQS
LCD interface
Connectivity
peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capability. The LCDIF is designed to support dumb
(synchronous 24-bit Parallel RGB interface) and smart
(asynchronous parallel MPU interface) LCD devices.
Medium Quality Sound
Pulse Width Modulation
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
Connectivity
peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
PXP
Pixel Processing Pipeline Display peripherals A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications, allowing it to interface with the integrated
EPD.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
13
Modules list
Table 3. i.MX 6UltraLite Modules List (continued)
Block Mnemonic
Block Name
Quad SPI
Subsystem
Brief Description
QSPI
Connectivity
peripherals
Quad SPI module act as an interface to external serial
flash devices. This module contains the following
features:
• Flexible sequence engine to support various flash
vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of
operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash
devices
• Multi-master access with priority and flexible and
configurable buffer for each master
SAI1
SAI2
SAI3
—
—
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SDMA
Smart Direct Memory
Access
System Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It
helps in maximizing system performance by off-loading
the various cores in dynamic data routing. It has the
following features:
• Powered by a 16-bit instruction-set micro-RISC
engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any
combination of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals between ARM and SDMA
• Very fast context-switching with 2-level priority based
preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unit-directional and
bi-directional flows (copy mode)
• Support of byte-swapping
• Library of Scripts and API is available
2x SIMv2
Smart Card
Connectivity
peripherals
Smart card interface compliant with ISO7816.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
14
NXP Semiconductors
Modules list
Table 3. i.MX 6UltraLite Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
6UltraLite processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard
support, which complies with IEEE1149.1 and
IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6UltraLite SJC
incorporates three security modes for protecting
against unauthorized accesses. Modes are selected
through eFUSE configuration.
SNVS
SPDIF
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
System Counter
—
—
The system counter module is a programmable system
counter which provides a shared time base to the
Cortex A series cores as part of ARM’s generic timer
architecture. It is intended for use in application where
the counter is always powered on and supports
multiple, unrelated clocks.
TSC
Touch Screen
Touch Controller
Security
With touch controller to support 4-wire and 5-wire
resistive touch panel.
TZASC
Trust-Zone Address
Space Controller
The TZASC (TZC-380 by ARM) provides security
address region control functions required for intended
application. It is used on the path to the DRAM
controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
15
Modules list
Table 3. i.MX 6UltraLite Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX 6UltraLite specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
USB
Universal Serial Bus 2.0
Connectivity
Peripherals
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
WDOG1
WDOG3
Watch Dog
Timer Peripherals The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the ARM
core, and a second point evokes an external event on
the WDOG line.
WDOG2
(TZ)
Watch Dog (TrustZone)
Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such
situation is undesirable as it can compromise the
system’s security. Once the TZ WDOG module is
activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer
times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode.
If it is still not served, the TZ WDOG asserts a security
violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal
mode SW.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
16
NXP Semiconductors
Modules list
3.1
Special signal considerations
Table 4 lists special signal considerations for the i.MX 6UltraLite processors. The signal names are listed
in alphabetical order.
The package contact assignments can be found in Section 6, “Package information and contact
assignments".” Signal descriptions are provided in the i.MX 6UltraLite Reference Manual
(IMX6ULRM).
Table 4. Special Signal Considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX 6UltraLite Reference Manual (IMX6ULRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of
the CLK1_N/P pairs may remain unconnected.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical
conditions.
In case when high accuracy real time clock are not required system may use internal low frequency
ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO
unconnected.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80 is recommended. NXP BSP (board support package) software requires
24 MHz on XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI is mounted with 18 pF
capacitor. Please refer to the EVK board reference design for details. The logic level of this forcing
clock cannot exceed NVCC_PLL level.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
17
Modules list
Table 4. Special Signal Considerations (continued)
Remarks
Signal Name
DRAM_VREF
When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the
NVCC_DRAM supply. The user can tie DDR_VREF to a precision external resistor divider. Use a
1 k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a
closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is
maintained when two DDR3 ICs plus the i.MX 6UltraLite are drawing current on the resistor divider.
ZQPAD
DRAM calibration resistor 240 1% used as reference during DRAM output buffer driver
calibration should be connected between this pad and GND.
GPANAIO
This signal is reserved for NXP manufacturing use only. This output must remain unconnected.
JTAG_nnnn
The JTAG interface is summarized in Table 5. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated
if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX 6UltraLite reference manual. Both names refer
to the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC
These signals are No Connect (NC) and should be floated by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the
debounce time, the power off interrupt is generated. Off to on time supports the time it takes to
request power on after a configured button press time has been reached. While in the OFF state,
if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.
Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration
supports the time it takes to request power down after ONOFF button has been pressed for the
defined time.
TEST_MODE
TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
Table 5. JTAG Controller Interface Summary
JTAG
I/O Type
On-chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
Input
47 kpull-up
47 kpull-up
47 kpull-up
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
18
NXP Semiconductors
Modules list
Table 5. JTAG Controller Interface Summary (continued)
JTAG
I/O Type
On-chip Termination
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
Keeper
47 kpull-up
100 kpull-up
Input
3.2
Recommended connections for unused analog interfaces
Table 6 shows the recommended connections for unused analog interfaces.
Table 6. Recommended Connections for Unused Analog Interfaces
Recommendations
if Unused
Module
Pad Name
CCM
USB
CCM_CLK1_N, CCM_CLK1_P
Float
Float
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS,
USB_OTG2_CHD_B, USB_OTG2_DN, USB_OTG2_DP, USB_OTG2_VBUS
ADC
ADC_VREFH
Tie to
VDDA_ADC_3P3
VDDA_ADC_3P3
VDDA_ADC_3P3
must be powered
even if the ADC is
not used.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
19
Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6UltraLite
processors.
4.1
Chip-Level conditions
This section provides the device-level electrical characteristics for the IC. See Table 7 for a quick reference
to the individual tables and sections.
Table 7. i.MX 6UltraLite Chip-Level Conditions
For these characteristics
Topic appears
Absolute maximum ratings
Thermal resistance
on page 20
on page 21
on page 22
on page 24
on page 25
on page 27
on page 28
Operating ranges
External clock sources
Maximum supply currents
Low power mode supply currents
USB PHY current consumption
4.1.1
Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 8 may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
Table 8 shows the absolute maximum operating ratings.
Table 8. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
Core Supplies Input Voltage
(LDO Enabled)
VDD_SOC_IN
-0.3
1.6
V
Core Supplies Input Voltage
(LDO Bypass)
VDD_SOC_IN
VDD_HIGH_IN
-0.3
1.4
V
VDD_HIGH_IN Supply voltage
-0.3
-0.3
3.6
1.4
V
V
Core Supplies Output Voltage (LDO
Enabled)
VDD_ARM_CAP
VDD_SOC_CAP
VDD_HIGH_CAP LDO Output Supply
Voltage
VDD_HIGH_CAP
-0.3
2.6
V
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
20
NXP Semiconductors
Electrical characteristics
Table 8. Absolute Maximum Ratings (continued)
Supply Input Voltage to Secure
VDD_SNVS_IN
-0.3
3.6
Non-Volatile Storage and Real Time Clock
USB VBUS Supply
USB_OTG_VBUS
NVCC_DRAM
—
5.5
V
V
V
V
(See note 1)
IO Supply for DDR Interface
Supply for DDR pre-drivers
IO Supply for GPIO Type Pins
-0.4
-0.3
-0.5
1.975
NVCC_DRAM_2P5
2.85
3.7
NVCC_CSI
NVCC_ENET
NVCC_GPIO
NVCC_LCD
NVCC_NAND
NVCC_SD1
Supply for ADC 3P3V
VDDA_ADC_3P3
Supplies denoted as I/O Supply
Vin/Vout
—
3.7
2.8
V
V
V
MLB I/O Supply Voltage
-0.3
-0.5
Input/Output Voltage range (Non-DDR
pins)
OVDD + 0.3 (See
note 2)
Input/Output Voltage range (DDR Pins)
Vin/Vout
-0.5
OVDD + 0.4 (See
V
note 1, 2)
ESD damage Immunity:
Vesd
Human Body Model (HBM)
Charge Device Model (CDM)
—
—
2000
500
V
Storage Temperature range
TSTORAGE
-40
150
o C
1
The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575 V.
2
OVDD is the I/O supply voltage.
4.1.2
Thermal resistance
4.1.2.1
14x14 MM (VM) package thermal resistance
Table 9 displays the 14x14 MM (VM) package thermal resistance data.
1
Table 9. 14x14 MM (VM) Thermal Resistance Data
Rating
Test Conditions
Single-layer board (1s)
Symbol
Value
Unit
Notes
2,3
Junction to Ambient
Natural convection
RJA
58.4
oC/W
3,3,4
2,4
Junction to Ambient
Natural convection
Four-layer board (2s2p)
RJA
RJMA
RJMA
37.6
48.6
32.9
oC/W
oC/W
oC/W
Junction to Ambient (@200 Single layer board (1s)
ft/min)
2,4
Junction to Ambient (@200 Four layer board (2s2p)
ft/min)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
21
Electrical characteristics
Rating
1
Table 9. 14x14 MM (VM) Thermal Resistance Data
Test Conditions
Symbol
Value
Unit
Notes
5
Junction to Board
—
—
RJB
RJC
JT
21.8
19.3
2.3
oC/W
oC/W
oC/W
oC/W
6
7
8
Junction to Case
Junction to Package Top
Natural Convection
Junction to Package Bottom Natural Convection
JB
12.0
1
As per JEDEC JESD51-2 the intent of (thermal resistance) measurement is solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment.
2
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
3
4
5
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
6
7
8
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JB
4.1.3
Operating ranges
Table 10 provides the operating ranges of the i.MX 6UltraLite processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6UltraLite Reference Manual
(IMX6ULRM).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
22
NXP Semiconductors
Electrical characteristics
Comment
Table 10. Operating Ranges
Operating
Parameter
Description
Symbol
Min
Typ Max1 Unit
Conditions
Run Mode: LDO
Enabled
VDD_SOC_IN
—
1.375
—
1.5
V
VDD_SOC_IN must be 125 mV
higher than the LDO Output Set
Point (VDD_ARM_CAP and
VDD_SOC_CAP) for correct
supply voltage regulation.
VDD_ARM_CAP
A7 core at 696
MHz
1.25
1.15
1.00
—
—
—
—
1.3
1.3
1.3
1.3
V
Output voltage must be set to the
following rules:
• VDD_ARM_CAP <=
VDD_SOC_CAP
• VDD_SOC_CAP -
VDD_ARM_CAP < 330 mV
A7 core at 528
MHz
A7 core at 396
MHz
A7 core at 198 0.925
MHz
VDD_SOC_CAP
VDD_SOC_IN
—
1.15
1.15
—
—
1.3
1.3
V
V
—
Run Mode: LDO
Bypassed
A7 core
operation at 528
MHz or below
A7 core operation above 528 MHz
is not supported when LDO is
bypassed.
SUSPEND (DSM)
Mode
VDD_SOC_IN
VDD_HIGH_IN2
VDD_SNVS_IN3
—
—
—
0.90
2.80
2.40
—
—
—
1.3
3.6
3.6
V
V
V
Refer to Table 14 Low Power Mode
Current and Power Consumption
on page 14
VDD_HIGH
internal Regulator
Must match the range of voltages
that the rechargeable backup
battery supports.
Backup battery
supply range
Can be combined with
VDDHIGH_IN, if the system does
not require keeping real time and
other data on OFF state.
USB supply
voltages
USB_OTG1_VBUS
USB_OTG2_VBUS
NVCC_DRAM
—
—
4.40
4.40
1.14
—
—
5.5
5.5
1.3
V
V
V
V
V
V
—
—
—
—
—
—
DDR I/O supply
LPDDR2
DDR3L
DDR3
—
1.2
1.28 1.35 1.45
1.43
2.25
1.5 1.575
2.5 2.75
NVCC_DRAM2P5
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
23
Electrical characteristics
Table 10. Operating Ranges (continued)
GPIO supplies
NVCC_CSI
—
1.65
1.8,
2.8,
3.3
3.6
V
All digital I/O supplies
(NVCC_xxxx) must be powered
(unless otherwise specified in this
data sheet) under normal
conditions whether the associated
I/O pins are in use or not.
NVCC_ENET
NVCC_GPIO
NVCC_UART
NVCC_LCD
NVCC_NAND
NVCC_SD1
A/D converter
VDDA_ADC_3P3
—
3.0
3.15
3.6
V
VDDA_ADC_3P3 must be
powered when chip is in RUN
mode, IDLE mode, or SUSPEND
mode.
VDDA_ADC_3P3 should not be
powered when chip is in SNVS
mode.
Temperature Operating Ranges
Automotive -40 125
Junction
temperature
TJ
oC See the application note, i.MX
6UltraLite Product Lifetime Usage
Estimates for information on
product lifetime (power-on years)
for this processor.
1
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
2
3
In setting VDD_HIGH_IN voltage, refer to the Errata ERR010690 (SNVS_LP Registers Reset Issue).
In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX 6UltraLite Hardware
Development Guide (IMX6ULHDG).
Table 11 shows on-chip LDO regulators that can supply on-chip loads.
1
Table 11. On-Chip LDOs and their On-Chip Loads
Voltage Source
Load
Comment
VDD_HIGH_CAP
NVCC_DRAM_2P5
Board-level connection to VDD_HIGH_CAP
1
On-chip LDOs are designed to supply i.MX6UltraLite loads and must not be used to supply external loads.
4.1.4
External clock sources
Each i.MX 6UltraLite processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
24
NXP Semiconductors
Electrical characteristics
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 12 shows the interface frequency requirements.
Table 12. External Input Clock Frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1,2
XTALI Oscillator2,4
fckil
fxtal
—
—
32.7683/32.0
24
—
—
kHz
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX 6UltraLite Applications Processors (IMX6ULHDG).
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
The typical values shown in Table 12 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
•
•
On-chip 40 kHz ring oscillator—this clock source has the following characteristics:
— Approximately 25 µA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
External crystal oscillator with on-chip support circuit:
— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
4.1.5
Maximum supply currents
The data shown in Table 13 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to
specifically show the worst case power consumption.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
25
Electrical characteristics
See the i.MX 6UltraLite Power Consumption Measurement Application Note (AN5170) for more details
on typical power consumption under various use case definitions.
Table 13. Maximum Supply Currents
Power Line
Conditions
Max Current
Unit
VDD_SOC_IN
VDD_SOC_IN
696 MHz ARM clock
based on Dhrystone
test
600
mA
528 MHz ARM clock
based on Dhrystone
test
500
mA
VDD_HIGH_IN
VDD_SNVS_IN
—
—
—
1251
5002
503
mA
A
USB_OTG1_VBUS
USB_OTG2_VBUS
mA
VDDA_ADC_3P3
100 Ohm maximum
35
mA
loading for touch panel
Primary Interface (IO) Supplies
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_GPIO
NVCC_UART
NVCC_ENET
NVCC_LCD
—
(See4)
—
mA
—
—
—
—
—
—
—
—
50
N=16
N=16
N=16
N=29
N=17
N=6
N=12
MISC
—
Use maximum IO Equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
NVCC_NAND
NVCC_SD1
NVCC_CSI
DRAM_VREF
1
mA
1
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_DRAM_2P5 supplies).
2
The maximum VDD_SNVS_IN current may be higher depending on specific operating configurations, such as
BOOT_MODE[1:0] not equal to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1
mA, if available. VDD_SNVS_CAP charge time will increase if less than 1 mA is available.
3
4
This is the maximum current per active USB physical interface.
The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power
calculators are typically available from the memory vendors. They take in account factors, such as signal termination. See
the i.MX 6UltraLite Power Consumption Measurement Application Note (AN5170) or examples of DRAM power consumption
during specific use case scenarios.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
26
NXP Semiconductors
Electrical characteristics
5
General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
4.1.6
Low power mode supply currents
Table 14 shows the current core consumption (not including I/O) of i.MX 6UltraLite processors in selected
low power modes.
Table 14. Low Power Mode Current and Power Consumption
Mode
Test Conditions
Supply
Typical1
Units
SYSTEM IDLE:
LDO Enabled
• LDO_ARM and LDO_SOC are set to 1.15 V
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• DDR is in self refresh
VDD_SOC_IN (1.275 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
7.7
mA
10.5
0.06
41.5
• 24 MHz XTAL is ON
mW
mA
• 528 PLL is active, other PLLS are power down
• High-speed peripheral clock gated, but remain
powered
SYSTEM IDLE:
LDO Bypassed
• LDO_ARM and LDO_SOC are set to bypass
mode
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• DDR is in self refresh
VDD_SOC_IN (1.15 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
7.5
9.5
0.06
37.3
mW
mA
• 24 MHz XTAL is ON
• 528 PLL is active, other PLLs are power down
• High-speed peripheral clock gated, but remain
powered
LOW POWER IDLE: • LDO_SOC is set to 1.15 V, LDO_ARM is in PG
VDD_SOC_IN (1.275 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
3.2
1.5
LDO Enabled
mode
• LDO_2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
0.05
8.7
mW
mA
• High-speed peripheral are powered off
LOW POWER IDLE: • LDO_SOC is in bypass mode, LDO_ARM is in PG VDD_SOC_IN (1.15 V)
2.8
0.4
LDO Bypassed
mode
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
• LDO-2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
0.05
4.57
mW
• High-speed peripheral are powered off
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
27
Electrical characteristics
Table 14. Low Power Mode Current and Power Consumption (continued)
SUSPEND
(DSM)
• LDO_SOC is in bypass mode, LDO_ARM is in PG
mode
• LDO_2P5 and LDO_1P1 are shut off
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• High-speed peripheral are powered off
VDD_SOC_IN (0.9 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
0.44
0.03
0.03
0.58
mA
mW
mA
SNVS (RTC)
• All SOC digital logic, analog module are shut off
• 32 kHz RTC is alive
• Tamper detection circuit remains active
VDD_SOC_IN (0 V)
VDD_HIGH_IN (0 V)
VDD_SNVS_IN (3.0 V)
Total
0
0
0.02
0.06
mW
1
Typical process material in fab
4.1.7
USB PHY current consumption
Power down mode
4.1.7.1
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical
condition. Table 15 shows the USB interface current consumption in power down mode.
Table 15. USB PHY Current Consumption in Power Down Mode
VDD_USB_CAP (3.0 V)
VDD_HIGH_CAP (2.5 V)
NVCC_PLL (1.1 V)
Current
5.1 A
1.7 A
< 0.5 A
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
28
NXP Semiconductors
Electrical characteristics
4.2.1
Power-Up sequence
The below restrictions must be followed:
•
•
•
VDD_SNVS_IN supply must be turned on before any other power supply or be connected
(shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
VDD_HIGH_IN should be turned on before VDD_SOC_IN.
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. See the i.MX 6UltraLite Reference Manual
(IMX6ULRM) for further details and to ensure that all necessary
requirements are being met.
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use both the 1.8 V and 3.3 V supplies).
NOTE
USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power
supply sequence and may be powered at any time.
4.2.2
Power-Down sequence
The following restrictions must be followed:
•
VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted)
with VDD_HIGH_IN supply.
•
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
CAUTION
For power sequence control on VDD_HIGH_IN and VDD_SOC_IN, refer to the ERR010690 (SNVS_LP
Registers Reset Issue).
4.2.3
Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package information
and contact assignments".”
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
29
Electrical characteristics
4.3
Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6UltraLite Reference Manual
(IMX6ULRM) for details on the power tree scheme.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO operation only.
4.3.1
Digital regulators (LDO_ARM, LDO_SOC)
There are two digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of
their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on-die trimming. This translates into more stable voltage for
the on-chip logics.
These regulators have two basic modes:
•
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
•
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
For additional information, see the i.MX 6UltraLite Reference Manual (IMX6ULRM).
4.3.2
Regulators for analog modules
LDO_1P1
4.3.2.1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0
V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6UltraLite Applications Processors (IMX6ULHDG).
For additional information, see the i.MX 6UltraLite Reference Manual (IMX6ULRM).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
30
NXP Semiconductors
Electrical characteristics
4.3.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is
2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the DDR IOs, USB Phy,
E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be
used by the system to determine when the load capability of the regulator is being exceeded, to take the
necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up,
if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 .
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6UltraLite Applications Processors (IMX6ULHDG).
For additional information, see the i.MX 6UltraLite Reference Manual (IMX6ULRM).
4.3.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6UltraLite Applications Processors (IMX6ULHDG).
For additional information, see the i.MX 6UltraLite Reference Manual (IMX6ULRM).
4.4
PLL’s electrical characteristics
4.4.1
Audio/Video PLL’s electrical parameters
Table 16. Audio/Video PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz ~1.3 GHz
24 MHz
<11250 reference cycles
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
31
Electrical characteristics
4.4.2
4.4.3
4.4.4
4.4.5
528 MHz PLL
Table 17. 528 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
528 MHz PLL output
24 MHz
<11250 reference cycles
Ethernet PLL
Table 18. Ethernet PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
500 MHz
24 MHz
<11250 reference cycles
480 MHz PLL
Table 19. 480 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
480 MHz PLL output
24 MHz
<383 reference cycles
ARM PLL
Table 20. ARM PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
648 MHz ~ 1296 MHz
24 MHz
<2250 reference cycles
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
32
NXP Semiconductors
Electrical characteristics
4.5
On-Chip oscillators
OSC24M
4.5.1
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.5.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
•
•
Average Discharge Voltage is 2.5 V
Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 21. OSC32K Main Characteristics
Min
Typ
Max Comments
Fosc
—
32.768 KHz
—
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption
—
4 A
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in
the power_detect block. So, the total current is 6.5 A on vdd_rtc when the
ring oscillator is not running.
Bias resistor
—
14 M
—
This integrated bias resistor sets the amplifier into a high gain state. Any
leakage through the ESD network, external board leakage, or even a
scope probe that is significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact the circuit's ability to start
up and maintain oscillations.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
33
Electrical characteristics
Table 21. OSC32K Main Characteristics
Min
Typ
Max
Comments
Crystal Properties
Cload
ESR
—
10 pF
—
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
—
50 k
100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
4.6
I/O DC parameters
This section includes the DC parameters of the following I/O types:
•
•
•
•
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3 modes
LVDS I/O DC Parameters
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output.
Figure 3. Circuit for Parameters Voh and Vol for I/O Cells
4.6.1
XTALI and RTC_XTALI (Clock Inputs) DC parameters
Table 22 shows the DC parameters for the clock inputs.
1
Table 22. XTALI and RTC_XTALI DC Parameters
Symbol Test Conditions Min
Parameter
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
0.8 x NVCC_PLL
0
NVCC_PLL
0.2
V
V
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
34
NXP Semiconductors
Electrical characteristics
1
Table 22. XTALI and RTC_XTALI DC Parameters (continued)
Parameter
Symbol Test Conditions
Min
Max
Unit
RTC_XTALI high-level DC input voltage
RTC_XTALI low-level DC input voltage
Vih
Vil
—
—
0.8
0
1.1
0.2
V
V
1
The DC parameters are for external clock input only.
4.6.2
Single voltage General Purpose I/O (GPIO) DC parameters
Table 23 shows DC parameters for GPIO pads. The parameters in Table 23 are guaranteed per the
operating ranges in Table 10, unless otherwise noted.
Table 23. Single Voltage GPIO DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage1
VOH
Ioh= -0.1mA (ipp_dse=001,010) OVDD-0.15
Ioh= -1mA
–
V
(ipp_dse=011,100,101,110,111)
Low-level output voltage1
VOL
Iol= 0.1mA (ipp_dse=001,010)
Iol= 1mA
–
0.15
V
(ipp_dse=011,100,101,110,111)
High-Level input voltage1,2
Low-Level input voltage1,2
Input Hysteresis (OVDD= 1.8V)
Input Hysteresis (OVDD=3.3V)
Schmitt trigger VT+2,3
VIH
VIL
—
0.7*OVDD
OVDD
V
—
OVDD=1.8V
OVDD=3.3V
—
0
0.3*OVDD
V
VHYS_LowVDD
VHYS_HighVDD
VTH+
250
—
—
—
mV
mV
mV
250
0.5*OVDD
Schmitt trigger VT-2,3
VTH-
—
—
—
—
—
—
—
—
—
—
-1
0.5*OVDD mV
Pull-up resistor (22_k PU)
Pull-up resistor (22_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (100_k PU)
Pull-up resistor (100_k PU)
Pull-down resistor (100_k PD)
Pull-down resistor (100_k PD)
Input current (no PU/PD)
RPU_22K
RPU_22K
RPU_47K
RPU_47K
RPU_100K
RPU_100K
RPD_100K
RPD_100K
IIN
Vin=0V
212
1
A
A
A
A
A
A
A
A
A
k
Vin=OVDD
Vin=0V
100
1
Vin=OVDD
Vin=0V
48
1
Vin=OVDD
Vin=OVDD
Vin=0V
48
1
VI = 0, VI = OVDD
VI =0.3*OVDD, VI = 0.7* OVDD
1
Keeper Circuit Resistance
R_Keeper
105
175
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
35
Electrical characteristics
2
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
3
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.6.3
DDR I/O DC parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. For details on supported
DDR memory configurations, see Section 4.10, “Multi-Mode DDR Controller (MMDC)".
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX
6UltraLite Applications Processor (IMX6ULHDG).
4.6.3.1
LPDDR2 mode I/O DC parameters
1
Table 24. LPDDR2 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
Low-level output voltage
Input Reference Voltage
VOH
VOL
Ioh= -0.1mA
0.9*OVDD
—
—
0.1*OVDD
0.51*OVDD
OVDD
Vref-0.13
Note2
-0.26
V
V
Iol= 0.1mA
Vref
—
0.49*OVDD
Vref+0.13
OVSS
0.26
V
DC High-Level input voltage
DC Low-Level input voltage
Vih_DC
Vil_DC
Vih_diff
Vil_diff
Mmpupd
Rres
—
V
—
V
Differential Input Logic High
—
—
—
%
Differential Input Logic Low
—
Note2
-15
Pull-up/Pull-down Impedance Mismatch
240 unit calibration resolution
Keeper Circuit Resistance
—
15
—
—
—
10
Rkeep
Iin
110
175
k
A
Input current (no pull-up/down)
VI = 0, VI = OVDD
-2.5
2.5
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4.6.3.2
DDR3/DDR3L mode I/O DC parameters
The parameters in Table 26 are guaranteed per the operating ranges in Table 10, unless otherwise noted.
Table 26. DDR3/DDR3L I/O DC Electrical Characteristics
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
VOH
Ioh= -0.1mA
0.8*OVDD1
—
V
Voh (for ipp_dse=001)
Low-level output voltage
VOL
Iol= 0.1mA
0.2*OVDD
—
V
Vol (for ipp_dse=001)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
36
NXP Semiconductors
Electrical characteristics
Table 26. DDR3/DDR3L I/O DC Electrical Characteristics (continued)
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
VOH
Ioh= -1mA
0.8*OVDD
—
V
Voh (for all except ipp_dse=001)
Low-level output voltage
VOL
Iol= 1mA
0.2*OVDD
—
V
Vol (for all except ipp_dse=001)
Input Reference Voltage
DC High-Level input voltage
DC Low-Level input voltage
Differential Input Logic High
Differential Input Logic Low
Termination Voltage
Vref
Vih_DC
Vil_DC
Vih_diff
Vil_diff
Vtt
—
0.49*ovdd
Vref2+0.1
OVSS
0.2
0.51*ovdd
OVDD
Vref-0.1
—
V
V
—
—
V
—
V
—
—
-0.2
V
Vtt tracking OVDD/2
0.49*OVDD
-10
0.51*OVDD
10
V
Pull-up/Pull-down Impedance Mismatch Mmpupd
—
%
240 unit calibration resolution
Keeper Circuit Resistance
Rres
Rkeep
Iin
—
—
—
10
105
165
k
A
Input current (no pull-up/down)
VI = 0,VI = OVDD
-2.9
2.9
1
2
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L)
Vref – DDR3/DDR3L external reference voltage
4.6.4
LVDS I/O DC parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 27 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
Table 27. LVDS I/O DC Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
VOH
VOL
VOS
Rload-100 Diff
IOH = 0 mA
IOL = 0 mA
—
250
1.25
0.9
350
1.375
1.025
1.2
450
1.6
mV
V
1.25
1.375
V
1.125
V
4.7
I/O AC parameters
This section includes the AC parameters of the following I/O types:
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and
Figure 5.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
37
Electrical characteristics
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 5. Output Transition Time Waveform
4.7.1
General Purpose I/O AC parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 28 and Table 29,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 28. General Purpose I/O AC Parameters 1.8 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=111)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.72/2.79
1.51/1.54
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=101)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.20/3.36
1.96/2.07
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=100)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.64/3.88
2.27/2.53
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=011)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
4.32/4.50
3.16/3.17
—
—
—
—
Input Transition Times1
—
25
ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
38
NXP Semiconductors
Electrical characteristics
Table 29. General Purpose I/O AC Parameters 3.3 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=101)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
1.70/1.79
1.06/1.15
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=011)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.35/2.43
1.74/1.77
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=010)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.13/3.29
2.46/2.60
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=001)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
5.14/5.57
4.77/5.15
—
—
—
—
ns
ns
Input Transition Times1
—
25
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.7.2
DDR I/O AC parameters
The Multi-mode DDR Controller (MMDC) is compatible with JEDEC-compliant SDRAMs. For details
on supported DDR memory configurations, see Section 4.10, “Multi-Mode DDR Controller (MMDC)".
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX
6UltraLite Applications Processor (IMX6ULHDG).
Table 30 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
1
Table 30. DDR I/O LPDDR2 Mode AC Parameters
Parameter
AC input logic high
Symbol
Test Condition
Min
Max
Unit
Vih(ac)
Vil(ac)
—
Vref + 0.22
OVDD
Vref - 0.22
—
V
V
AC input logic low
—
0
0.44
—
AC differential input high voltage2
AC differential input low voltage
Input AC differential cross point voltage3
Over/undershoot peak
Vidh(ac)
Vidl(ac)
Vix(ac)
Vpeak
Varea
—
V
—
Relative to Vref
—
0.44
V
-0.12
—
0.12
V
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
400 MHz
—
0.3
V-ns
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
39
Electrical characteristics
1
Table 30. DDR I/O LPDDR2 Mode AC Parameters (continued)
Parameter
Symbol
Test Condition
Min
Max
Unit
tsr
50 to Vref.
5 pF load.
1.5
3.5
V/ns
Drive impedance = 40
± 30%
Single output slew rate, measured between
Vol (ac) and Voh (ac)
50 to Vref.
5pF load.Drive
impedance = 60 ±
30%
1
2.5
0.1
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
clk = 400 MHz
ns
—
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp
is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 31 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
1
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters
Parameter
AC input logic high
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
Vid(ac)
Vix(ac)
Vpeak
Varea
—
Vref + 0.175
—
—
—
—
—
—
OVDD
Vref - 0.175
—
V
V
AC input logic low
—
0
0.35
AC differential input voltage2
Input AC differential cross point voltage3
Over/undershoot peak
—
Relative to Vref
—
V
Vref - 0.15
—
Vref + 0.15
0.4
V
V
Over/undershoot area (above OVDD
or below OVSS)
400 MHz
—
0.5
V-ns
Single output slew rate, measured between Vol
(ac) and Voh (ac)
tsr
Driver impedance = 34
2.5
—
—
5
V/ns
ns
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
clk = 400 MHz
0.1
—
1
2
Note that the JEDEC JESD79_3D specification supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
4.8
Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX 6UltraLite processors for the following
I/O types:
•
Single Voltage General Purpose I/O (GPIO)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
40
NXP Semiconductors
Electrical characteristics
•
Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes
NOTE
GPIO and DDR I/O output driver impedance is measured with “long”
transmission line of impedance Ztl attached to I/O pad and incident wave
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that
defines specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 6).
OVDD
PMOS (Rpu)
Ztl , L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
OVDD
Vout (pad)
Vref2
Vref1
Vref
t,(ns)
0
Vovdd - Vref1
Vref1
Rpu =
Rpd =
Ztl
Ztl
Vref2
Vovdd - Vref2
Figure 6. Impedance Matching Load for Measurement
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
41
Electrical characteristics
4.8.1
Single voltage GPIO output buffer impedance
Table 32 shows the GPIO output buffer impedance (OVDD 1.8 V).
Table 32. GPIO Output Buffer Average Impedance (OVDD 1.8 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
260
130
88
65
52
Output Driver
Impedance
Rdrv
43
37
Table 33 shows the GPIO output buffer impedance (OVDD 3.3 V).
Table 33. GPIO Output Buffer Average Impedance (OVDD 3.3 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
157
78
53
39
32
26
23
Output Driver
Impedance
Rdrv
4.8.2
DDR I/O output buffer impedance
Table 34 shows DDR I/O output buffer impedance of i.MX 6UltraLite processors.
Table 34. DDR I/O Output Buffer Impedance
Typical
Test Conditions DSE
Parameter
Symbol
Unit
NVCC_DRAM=1.5 V
(DDR3)
NVCC_DRAM=1.2 V
(LPDDR2)
(Drive Strength)
DDR_SEL=11
DDR_SEL=10
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
Hi-Z
240
120
80
60
48
Output Driver
Impedance
Rdrv
40
34
40
34
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4. It is recommended to use a strong driver strength (<= 48 ) for all DDR pads and all DDR type (DDR3/DDR3L/LPDDR2).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
42
NXP Semiconductors
Electrical characteristics
4.9
System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 6UltraLite
processor.
4.9.1
Reset timings parameters
Figure 7 shows the reset timing and Table 35 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset Timing Diagram
Table 35. Reset Timing Parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
4.9.2
WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 36 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 8. WDOGn_B Timing Diagram
Table 36. WDOGn_B Timing Parameters
ID
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
43
Electrical characteristics
4.9.3
External Interface Module (EIM)
The following subsections provide information on the EIM. Maximum operating frequency for EIM data
transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or
clock periods are valid for the entire range of allowed frequencies (0–104 MHz).
4.9.3.1
EIM interface pads allocation
EIM supports 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. Table 37
provides EIM interface pads allocation in different modes.
1
Table 37. EIM Internal Module Multiplexing
Multiplexed
Non Multiplexed Address/Data Mode
8 Bit
Address/Data
mode
Setup
16 Bit
MUM = 0,
16 Bit
MUM = 0,
DSZ = 100
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 110
MUM = 0,
DSZ = 111
MUM = 0,
MUM = 1,
DSZ = 001
DSZ = 001
DSZ = 010
EIM_ADDR
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_ADDR
[26:16]
EIM_DATA
[07:00],
EIM_DATA
[07:00]
—
Reserved
Reserved
EIM_DATA
[07:00]
Reserved
EIM_AD
[07:00]
EIM_EB0_B
EIM_DATA
[15:08],
—
EIM_DATA
[15:08]
Reserved
Reserved
EIM_DATA
[15:08]
Reserved
EIM_AD
[15:08]
EIM_EB1_B
1
For more information on configuration ports mentioned in this table, see the i.MX 6UltraLite Reference Manual (IMX6ULRM).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
44
NXP Semiconductors
Electrical characteristics
General EIM Timing-Synchronous Mode
Figure 9, Figure 10, and Table 38 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
,
WE2
...
WE3
EIM_BCLK
WE1
WE4
WE6
WE5
WE7
WE9
EIM_ADDRxx
EIM_CSx_B
WE8
WE10
WE12
EIM_WE_B
EIM_OE_B
EIM_EBx_B
WE11
WE13
WE15
WE17
WE14
WE16
EIM_LBA_B
Output Data
Figure 9. EIM Outputs Timing Diagram
EIM_BCLK
WE18
Input Data
WE19
WE20
EIM_WAIT_B
WE21
Figure 10. EIM Inputs Timing Diagram
4.9.3.2
Examples of EIM synchronous accesses
Table 38. EIM Bus Timing Parameters
ID
Parameter
Min1
Max1
Unit
WE1
WE2
WE3
WE4
EIM_BCLK Cycle time2
t x (k + 1)
0.4 x t x (k + 1)
—
ns
ns
ns
ns
EIM_BCLK Low Level Width
EIM_BCLK High Level Width
Clock rise to address valid
—
0.4 x t x (k + 1)
—
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) + 2.25
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
45
Electrical characteristics
Table 38. EIM Bus Timing Parameters (continued)
ID
Parameter
Clock rise to address invalid
Min1
Max1
Unit
WE5
WE6
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
-0.5 x t x (k + 1) - 1.25
2.3
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
-0.5 x t x (k + 1) + 2.25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock rise to EIM_CSx_B valid
Clock rise to EIM_CSx_B invalid
Clock rise to EIM_WE_B Valid
Clock rise to EIM_WE_B Invalid
Clock rise to EIM_OE_B Valid
Clock rise to EIM_OE_B Invalid
Clock rise to EIM_EBx_B Valid
Clock rise to EIM_EBx_B Invalid
Clock rise to EIM_LBA_B Valid
Clock rise to EIM_LBA_B Invalid
Clock rise to Output Data Valid
Clock rise to Output Data Invalid
Input Data setup time to Clock rise
Input Data hold time from Clock rise
EIM_WAIT_B setup time to Clock rise
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
WE18
WE19
WE20
WE21
2
—
2
—
EIM_WAIT_B hold time from Clock
rise
2
—
1
2
k represents register setting BCD value.
t is clock period (1/Freq.) For 104 MHz, t = 9.165 ns.
Figure 11 to Figure 14 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
EIM_BCLK
WE4
WE6
WE5
WE7
EIM_ADDRxx
Address v1
Last Valid Address
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
WE14
WE10
WE12
WE15
WE18
WE11
WE13
EIM_OE_B
EIM_EBx_B
EIM_DATAxx
D(v1)
WE19
Figure 11. Synchronous Memory Read Access, WSC=1
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
46
NXP Semiconductors
Electrical characteristics
EIM_BCLK
WE5
WE4
EIM_ADDRxx
Last Valid Address
Address V1
WE7
WE6
WE8
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE9
WE14
WE15
WE13
WE12
WE16
EIM_EBx_B
WE17
EIM_DATAxx
D(V1)
Figure 12. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0
EIM_BCLK
WE16
WE17
WE5
WE4
EIM_ADDRxx/
EIM_ADxx
Write Data
Last Valid Address
Address V1
WE6
WE7
WE9
EIM_CSx_B
EIM_WE_B
WE8
WE14
WE15
EIM_LBA_B
EIM_OE_B
WE10
WE11
EIM_EBx_B
Figure 13. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
47
Electrical characteristics
EIM_BCLK
WE4
Valid Address
WE6
WE5
Address V1
WE19
WE18
EIM_ADDRxx/
EIM_ADxx
Last
Data
EIM_CSx_B
EIM_WE_B
WE7
WE15
WE10
WE14
WE12
EIM_LBA_B
EIM_OE_B
WE11
WE13
EIM_EBx_B
Figure 14. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0
4.9.3.3
General EIM timing-asynchronous mode
Figure 15 through Figure 19, and Table 39 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read & write access length in cycles may vary from what is shown in Figure 15 through
Figure 18 as RWSC, OEN and CSN is configured differently. See the i.MX 6UltraLite Reference Manual
(IMX6ULRM) for the EIM programming model.
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
EIM_ADxx
WE31
WE32
Next Address
Last Valid Address
Address V1
EIM_WE_B
EIM_LBA_B
WE39
WE40
WE36
WE38
WE35
WE37
EIM_OE_B
EIM_EBx_B
WE44
MAXCO
EIM_DATAxx[7:0]
D(V1)
WE43
MAXDI
Figure 15. Asynchronous Memory Read Access (RWSC = 5)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
48
NXP Semiconductors
Electrical characteristics
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
MAXDI
WE31
EIM_ADDRxx/
EIM_ADxx
D(V1)
Addr. V1
WE32A
WE44
EIM_WE_B
EIM_LBA_B
WE40A
WE39
WE35A
WE37
WE36
WE38
EIM_OE_B
EIM_EBx_B
MAXCO
Figure 16. Asynchronous A/D Muxed Read Access (RWSC = 5)
EIM_CSx_B
EIM_ADDRxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE31
Last Valid Address
WE33
WE32
WE34
WE40
Next Address
Address V1
WE39
WE45
WE41
WE46
EIM_EBx_B
WE42
EIM_DATAxx
D(V1)
Figure 17. Asynchronous Memory Write Access
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
49
Electrical characteristics
EIM_CSx_B
WE41
WE31
EIM_ADDRxx/
D(V1)
Addr. V1
WE32A
WE42
EIM_DATAxx
EIM_WE_B
WE33
WE39
WE34
WE40A
EIM_LBA_B
EIM_OE_B
WE46
WE45
EIM_EBx_B
Figure 18. Asynchronous A/D Muxed Write Access
EIM_CSx_B
WE31
WE32
EIM_ADDRxx
Next Address
Last Valid Address
Address V1
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE39
WE35
WE37
WE40
WE36
WE38
EIM_EBx_B
WE44
D(V1)
EIM_DATAxx[7:0]
EIM_DTACK_B
WE43
WE48
WE47
Figure 19. DTACK Mode Read Access (DAP=0)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
50
NXP Semiconductors
Electrical characteristics
EIM_CSx_B
WE31
WE32
WE34
WE40
EIM_ADDRxx
EIM_WE_B
Next Address
Last Valid Address
Address V1
WE33
WE39
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
WE45
WE41
WE46
WE42
EIM_DATAxx
D(V1)
WE48
EIM_DTACK_B
WE47
Figure 20. DTACK Mode Write Access (DAP=0)
1,2
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip to Select
Determination by
Ref No.
Parameter
Synchronous measured
parameters
Min
Max
Unit
WE31
WE32
EIM_CSx_B valid to
Address Valid
WE4 - WE6 - CSA x t
WE7 - WE5 - CSN x t
-3.5 - CSA x t
-3.5 - CSN x t
3.5 - CSA x t
3.5 - CSN x t
ns
ns
ns
Address Invalid to
EIM_CSx_B Invalid
WE32A(mu EIM_CSx_B valid to
xed A/D Address Invalid
t + WE4 - WE7 + (ADVN +
ADVA + 1 - CSA) x t
t - 3.5 + (ADVN + ADVA
+ 1 - CSA) x t
t + 3.5 + (ADVN +
ADVA + 1 - CSA) x t
WE33
WE34
EIM_CSx_B Valid to WE8 - WE6 + (WEA - WCSA) x -3.5 + (WEA - WCSA) x t 3.5 + (WEA - WCSA) x t ns
EIM_WE_B Valid
t
EIM_WE_B Invalid WE7 - WE9 + (WEN - WCSN) x -3.5 + (WEN - WCSN) x t 3.5 + (WEN - WCSN) x t ns
to EIM_CSx_B
Invalid
t
WE35
EIM_CSx_B Valid to WE10 - WE6 + (OEA - RCSA) x -3.5 + (OEA - RCSA) x t 3.5 + (OEA - RCSA) x t
EIM_OE_B Valid
ns
ns
t
WE35A
(muxed
A/D)
EIM_CSx_B Valid to WE10 - WE6 + (OEA + RADVN -3.5 + (OEA + RADVN + 3.5 + (OEA + RADVN +
EIM_OE_B Valid
+ RADVA + ADH + 1 - RCSA) x
t
RADVA + ADH + 1 -
RCSA) x t
RADVA + ADH + 1 -
RCSA) x t
WE36
EIM_OE_B Invalid
to EIM_CSx_B
Invalid
WE7 - WE11 + (OEN - RCSN) x -3.5 + (OEN - RCSN) x t 3.5 + (OEN - RCSN) x t ns
t
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
51
Electrical characteristics
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip to Select
1,2
Determination by
Synchronous measured
parameters
Ref No.
Parameter
Min
Max
Unit
WE37
EIM_CSx_B Valid to WE12 - WE6 + (RBEA - RCSA) -3.5 + (RBEA - RCSA) x t 3.5 + (RBEA - RCSA) x
ns
EIM_EBx_B Valid
(Read access)
x t
t
WE38
EIM_EBx_B Invalid WE7 - WE13 + (RBEN - RCSN) -3.5 + (RBEN - RCSN) x t 3.5 + (RBEN- RCSN) x t ns
to EIM_CSx_B
Invalid (Read
access)
x t
WE39
WE40
EIM_CSx_B Valid to WE14 - WE6 + (ADVA - CSA) x -3.5 + (ADVA - CSA) x t 3.5 + (ADVA - CSA) x t
ns
ns
EIM_LBA_B Valid
t
EIM_LBA_B Invalid
to EIM_CSx_B
Invalid (ADVL is
asserted)
WE7 - WE15 - CSN x t
-3.5 - CSN x t
3.5 - CSN x t
WE40A
(muxed
A/D)
EIM_CSx_B Valid to WE14 - WE6 + (ADVN + ADVA -3.5 + (ADVN + ADVA + 3.5 + (ADVN + ADVA +
ns
EIM_LBA_B Invalid
+ 1 - CSA) x t
1 - CSA) x t
1 - CSA) x t
WE41
EIM_CSx_B Valid to
Output Data Valid
WE16 - WE6 - WCSA x t
-3.5 - WCSA x t
3.5 - WCSA x t
ns
ns
WE41A
(muxed
A/D)
EIM_CSx_B Valid to
Output Data Valid
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA) x t
-3.5 + (WADVN +
WADVA + ADH + 1 -
WCSA) x t
3.5 + (WADVN +
WADVA + ADH + 1 -
WCSA) x t
WE42
Output Data Invalid
to EIM_CSx_B
Invalid
WE17 - WE7 - CSN x t
-3.5 - CSN x t
3.5 - CSN x t
ns
ns
MAXCO Output maximum
delay from internal
driving
10
—
10
EIM_ADDRxx/contr
ol flip-flops to chip
outputs
MAXCSO Output maximum
delay from internal
chip selects driving
flip-flops to
10
5
—
—
10
5
ns
ns
EIM_CSx_B out
MAXDI
EIM_DATAxx
maximum delay
from chip input data
to its internal flip-flop
WE43
WE44
Input Data Valid to
EIM_CSx_B Invalid
MAXCO - MAXCSO + MAXDI
0
MAXCO - MAXCSO +
MAXDI
—
—
ns
ns
EIM_CSx_B Invalid
to Input Data Invalid
0
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
52
NXP Semiconductors
Electrical characteristics
1,2
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip to Select
Determination by
Synchronous measured
parameters
Ref No.
Parameter
Min
Max
Unit
WE45
EIM_CSx_B Valid to
EIM_EBx_B Valid
(Write access)
WE12 - WE6 + (WBEA -
WCSA) x t
-3.5 + (WBEA - WCSA) x 3.5 + (WBEA - WCSA)
x t
ns
t
WE46
EIM_EBx_B Invalid
to EIM_CSx_B
Invalid (Write
access)
WE7 - WE13 + (WBEN -
WCSN) x t
-3.5 + (WBEN - WCSN) x 3.5 + (WBEN - WCSN)
ns
—
t
x t
10
MAXDTI MAXIMUM delay
from
10
—
EIM_DTACK_B to
its internal flip-flop +
2 cycles for
synchronization
WE47
WE48
EIM_DTACK_B
Active to
EIM_CSx_B Invalid
MAXCO - MAXCSO + MAXDTI MAXCO - MAXCSO +
MAXDTI
—
—
ns
ns
EIM_CSx_B Invalid
to EIM_DTACK_B
Invalid
0
0
1
2
For more information on configuration parameters mentioned in this table, see the i.MX 6UltraLite Reference Manual
(IMX6ULRM).
In this table, CSA means WCSA when write operation or RCSA when read operation
— t means clock period from axi_clk frequency.
—CSA means register setting for WCSA when in write operations or RCSA when in read operations.
—CSN means register setting for WCSN when in write operations or RCSN when in read operations.
—ADVN means register setting for WADVN when in write operations or RADVN when in read operations.
—ADVA means register setting for WADVA when in write operations or RADVA when in read operations.
4.10 Multi-Mode DDR Controller (MMDC)
The Multi-Mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.
4.10.1 MMDC compatibility with JEDEC-compliant SDRAMs
The i.MX 6UltraLite MMDC supports the following memory types:
•
•
LPDDR2 SDRAM compliant with JESD209-2B LPDDR2 JEDEC standard release June, 2009
DDR3/DDR3L SDRAM compliant with JESD79-3D DDR3 JEDEC standard release April, 2008
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX
6UltraLite Applications Processor (IMX6ULHDG).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
53
Electrical characteristics
4.10.2 MMDC supported DDR3/DDR3L/LPDDR2 configurations
Table 40 shows the MMDC supported DDR3/DDR3L/LPDDR2 configurations.
Table 40. i.MX 6UltraLite Supported DDR3/DDR3L/LPDDR2 Configurations
Parameter
DDR3
DDR3L
LDDDR2
Clock frequency
Bus width
400 MHz
16-bit
Single
2
400 MHz
16-bit
Single
2
400 MHz
16-bit
Single
2
Channel
Chip selects
4.11 General-Purpose Media Interface (GPMI) timing
The i.MX 6UltraLite GPMI controller is a flexible interface NAND Flash controller with 8-bit data width,
up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following subsections.
4.11.1 Asynchronous mode AC timing (ONFI 1.0 compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 21 through Figure 24
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode. Table 41 describes the timing parameters (NF1–NF17) that are shown in the figures.
E&Ϯ
E&ϭ
ꢁ
.!.$?#,%
ꢁ
ꢁ
ꢀ
ꢁ
E&ϯ
E&ϰ
.!.$?#%ꢀ?"
.!.$?7%?"
ꢀ
ꢀ
ꢀ
ꢁ
E&ϱ
ꢁ
ꢁ
.!.$?!,%
E&ϲ
E&ϳ
E&ϴ
E&ϵ
ꢀŽŵŵĂŶĚꢁ
ꢁ
.!.$?$!4!XX
ꢁ
Figure 21. Command Latch Cycle Timing Diagram
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
54
NXP Semiconductors
Electrical characteristics
ꢁ
E&ϭ
.!.$?#,%
.!.$?#%ꢀ?"
.!.$?7%?"
ꢀ
ꢀ
ꢀ
ꢀ
ꢁ
E&ϯ
E&ϭϬꢁ
E&ϱ
E&ϭϭ
ꢁ
ꢁ
.!.$?!,%
E&ϳ
E&ϲ
ꢁ
ꢁ
E&ϴ
E&ϵ
EꢂEꢃͺꢃꢂdꢂdždž
ꢂĚĚƌĞƐƐꢁ
Figure 22. Address Latch Cycle Timing Diagram
ꢁ
E&ϭ
.!.$?#,%
.!.$?#%ꢀ?"
.!.$?7%?"
ꢀ
ꢀ
ꢀ
ꢀ
ꢁ
E&ϯ
E&ϭϬꢁ
E&ϱ
E&ϭϭ
ꢁ
ꢁ
ꢁ
ꢁ
E&ϲ
E&ϳ
.!.$?!,%
E&ϴ
ꢃĂƚĂꢁꢁƚŽꢁꢁE&ꢁ
E&ϵ
.!.$?$!4!XX
Figure 23. Write Data Latch Cycle Timing Diagram
ꢀ
.!.$?#,%
ꢀ
.!.$?#%ꢀ?"
E&ϭϰꢁ
ꢀ
E&ϭϱ
E&ϭϯ
.!.$?2%?"
ꢁ
ꢁ
ꢀ
ꢀ
.!.$?2%!$9?"
E&ϭϮ
ꢁ
E&ϭϲ
E&ϭϳ
ꢃĂƚĂꢁĨƌŽŵꢁE&ꢁ
.!.$?$!4!XX
Figure 24. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)
.!.$?#,%
ꢀ
.!.$?#%ꢀ?"
E&ϭϰꢁ
ꢀ
E&ϭϯ
E&ϭϱ
.!.$?2%?"
ꢁ
ꢁ
ꢀ
ꢀ
.!.$?2%!$9?"
E&ϭϮ
E&ϭϳ
ꢁ
ꢁ
E&ϭϲ
EꢂEꢃͺꢃꢂdꢂdždž
ꢃĂƚĂꢁĨƌŽŵꢁE&
ꢁ
Figure 25. Read Data Latch Cycle Timing Diagram (EDO Mode)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
55
Electrical characteristics
1
Table 41. Asynchronous Mode Timing Parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2,3
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
NF9
NAND_CLE setup time
NAND_CLE hold time
NAND_CE0_B setup time
NAND_CE0_B hold time
NAND_WE_B pulse width
NAND_ALE setup time
NAND_ALE hold time
Data setup time
tCLS
tCLH
tCS
(AS + DS) T - 0.12 [see
DH T - 0.72 [see 2]
(AS + DS + 1) T [see 3,2
(DH+1) T - 1 [see 2]
DS T [see 2]
]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
]
tCH
tWP
tALS
tALH
tDS
(AS + DS) T - 0.49 [see 3,2
(DH T - 0.42 [see 2]
DS T - 0.26 [see 2]
DH T - 1.37 [see 2]
(DS + DH) T [see 2]
DH T [see 2]
]
Data hold time
tDH
NF10 Write cycle time
tWC
tWH
tRR4
tRP
NF11 NAND_WE_B hold time
NF12 Ready to NAND_RE_B low
NF13 NAND_RE_B pulse width
NF14 READ cycle time
(AS + 2) T [see 3,2
]
—
DS T [see 2]
(DS + DH) T [see 2]
DH T [see 2]
tRC
NF15 NAND_RE_B high hold time
NF16 Data setup on read
NF17 Data hold on read
tREH
tDSR
tDHR
—
(DS T -0.67)/18.38 [see 5,6
]
0.82/11.83 [see 5,6
]
—
1
GPMI’s Async Mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
In EDO mode (Figure 24), NF16/NF17 is different from the definition in non-EDO mode (Figure 23).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will
sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The
delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX
6UltraLite Reference Manual). The typical value of this control register is 0x8 at 50 MT/s EDO mode. But
if the board delay is big enough and cannot be ignored, the delay value should be made larger to
compensate the board delay.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
56
NXP Semiconductors
Electrical characteristics
4.11.2 Source synchronous mode AC timing (ONFI 2.x compatible)
Figure 26 to Figure 28 show the write and read timing of Source Synchronous Mode.
1)ꢀꢈ
1)ꢀꢁ
.!.$?#%?"
1)ꢂꢆ
1$1'B&/(
1)ꢂꢄ
1)ꢂꢃ
1)ꢂꢇ
1$1'B$/(
1)ꢂꢃ 1)ꢂꢄ
1$1'B:(ꢉ5(B%
1)ꢂꢂ
1$1'B&/.
1$1'B'46
1$1'B'46
2XWSXWꢊHQDEOH
1)ꢂꢅ
1)ꢂꢅ
1)ꢂꢀ
1)ꢂꢀ
&0'
$''
1$1'B'$7$>ꢋꢌꢅ@
1$1'B'$7$>ꢋꢌꢅ@
2XWSXWꢊHQDEOH
Figure 26. Source Synchronous Mode Command and Address Timing Diagram
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
57
Electrical characteristics
1)ꢀꢈ
1)ꢀꢁ
.!.$?#%ꢀ?"
.!.$?#,%
1)ꢂꢆ
1)ꢂꢆ
1)ꢂꢇ
1)ꢂꢇ
1)ꢂꢃ
1)ꢂꢃ
1)ꢂꢄ
1)ꢂꢄ
.!.$?!,%
1$1'B:(ꢉ5(B%
1)ꢂꢂ
.!.$?#,+
.!.$?$13
1)ꢂꢋ
1)ꢂꢋ
.!.$?$13
2XWSXWꢊHQDEOH
1)ꢂꢈ
1)ꢂꢈ
.!.$?$1;ꢁꢂꢀ=
1)ꢂꢁ
1)ꢂꢁ
.!.$?$1;ꢁꢂꢀ=
2XWSXWꢊHQDEOH
Figure 27. Source Synchronous Mode Data Write Timing Diagram
1)ꢀꢁ
1)ꢀꢈ
.!.$?#%?"
.!.$?#,%
1)ꢂꢇ
1)ꢂꢇ
1)ꢂꢆ
1)ꢂꢆ
1)ꢂꢄ
1)ꢂꢄ
1)ꢂꢃ
1)ꢂꢃ
1$1'B$/(
1)ꢂꢃ
.!.$?7%ꢃ2%
1)ꢂꢃ
1)ꢂꢂ
1)ꢂꢄ
.!.$?#,+
.!.$?$13
.!.$?$13
/UTPUT ENABLE
.!.$?$!4!;ꢁꢂꢀ=
.!.$?$!4!;ꢁꢂꢀ=
/UTPUT ENABLE
Figure 28. Source Synchronous Mode Data Read Timing Diagram
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
58
NXP Semiconductors
Electrical characteristics
.!.$?$13
E&ϯϬꢁ
ꢁ
.!.$?$!4!;ꢁꢂꢀ=
ꢃϬꢁ
ꢃϭꢁ
ꢃϮꢁ
ꢃϯꢁ
ꢁ
ꢁ
E&ϯϬ
E&ϯϭ
E&ϯϭ
Figure 29. NAND_DQS/NAND_DQ Read Valid Window
1
Table 42. Source Synchronous Mode Timing Parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2
NF18 NAND_CE0_B access time
NF19 NAND_CE0_B hold time
tCE
tCH
CE_DELAY T - 0.79 [see ]
0.5 tCK - 0.63 [see 2]
0.5 tCK - 0.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
NF20 Command/address NAND_DATAxx setup time
NF21 Command/address NAND_DATAxx hold time
NF22 Clock period
tCAS
tCAH
tCK
0.5 tCK - 1.23
—
NF23 Preamble delay
tPRE
tPOST
tCALS
tCALH
tDQSS
—
PRE_DELAY T - 0.29 [see 2]
POST_DELAY T - 0.78 [see 2]
0.5 tCK - 0.86
NF24 Postamble delay
NF25 NAND_CLE and NAND_ALE setup time
NF26 NAND_CLE and NAND_ALE hold time
NF27 NAND_CLK to first NAND_DQS latching transition
NF28 Data write setup
0.5 tCK - 0.37
T - 0.41 [see 2]
0.25 tCK - 0.35
NF29 Data write hold
—
0.25 tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
—
2.06
1.95
—
1
GPMI’s source synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing
depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2
T = tCK(GPMI clock period) -0.075ns (half of maximum p-p jitter).
For DDR Source sync mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read
valid window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s. GPMI
will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which
can be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6UltraLite
Reference Manual). Generally, the typical delay value of this register is equal to 0x7 which means 1/4
clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
59
Electrical characteristics
4.11.3 Samsung toggle mode AC timing
4.11.3.1 Command and address timing
NOTE
Samsung Toggle Mode command and address timing is the same as ONFI
1.0 compatible Async mode AC timing. See Section 4.11.1, “Asynchronous
mode AC timing (ONFI 1.0 compatible)",” for details.
4.11.3.2 Read and write timing
DEV?CLK
ꢀ
ꢀ
.!.$?#%X?"
.!.$?#,%
.!.$?!,%
ꢀ
ꢄ
ꢄ
.!.$?7%?"
.!.$?2%?"
.!.$?$13
.&ꢇꢉ
.&ꢇꢈ
ꢀꢅꢆ T#+
ꢀꢅꢆ T#+
.!.$?$!4!;ꢁꢂꢀ=
Figure 30. Samsung Toggle Mode Data Write Timing
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
60
NXP Semiconductors
Electrical characteristics
DEV?CLK
.!.$?#%X?"
.& ꢄꢊ
.!.$?#,%
.!.$?!,%
ꢄ T #+
ꢄ
.&ꢇꢉ
.!.$?7%?"
.!.$?2%?"
ꢄ T #+
.& ꢇꢈ
ꢄ T #+
ꢄ T #+
ꢄ T #+
.!.$?$13
.!.$?$!4!;ꢁꢂꢀ=
Figure 31. Samsung Toggle Mode Data Read Timing
1
Table 43. Samsung Toggle Mode Timing Parameters
Timing
T = GPMI Clock Cycle
Min.
ID
Parameter
Symbol
Unit
Max.
2,3
NF1 NAND_CLE setup time
NF2 NAND_CLE hold time
tCLS
tCLH
tCS
(AS + DS) T - 0.12 [see
DH T - 0.72 [see 2]
(AS + DS) T - 0.58 [see 3,2
DH T - 1 [see 2]
]
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
NF3 NAND_CE0_B setup time
NF4 NAND_CE0_B hold time
NF5 NAND_WE_B pulse width
NF6 NAND_ALE setup time
NF7 NAND_ALE hold time
]
tCH
tWP
tALS
tALH
tCAS
tCAH
tCE
DS T [see 2]
(AS + DS) T - 0.49 [see 3,2
DH T - 0.42 [see 2]
DS T - 0.26 [see 2]
]
NF8 Command/address NAND_DATAxx setup time
NF9 Command/address NAND_DATAxx hold time
NF18 NAND_CEx_B access time
NF22 clock period
DH T - 1.37 [see 2]
4,2
CE_DELAY T [see
]
—
—
—
—
tCK
—
5,2
NF23 preamble delay
tPRE
PRE_DELAY T [see
]
NF24 postamble delay
tPOST POST_DELAY T +0.43 [see 2]
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
61
Electrical characteristics
1
Table 43. Samsung Toggle Mode Timing Parameters (continued)
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF28 Data write setup
NF29 Data write hold
tDS6
tDH6
0.25 tCK - 0.32
—
—
ns
ns
—
—
0.25 tCK - 0.79
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
tDQSQ7
tQHS7
—
—
3.18
3.27
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
5
6
7
PRE_DELAY+1) (AS+DS)
Shown in Figure 30.
Shown in Figure 31.
For DDR Toggle mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will
sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6UltraLite
Reference Manual). Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay
expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger
to compensate the board delay.
4.12 External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
4.12.1 CMOS Sensor Interface (CSI) timing parameters
4.12.1.0.1 Gated clock mode timing
Figure 32 and Figure 33 shows the gated clock mode timings for CSI, and Table 44 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
62
NXP Semiconductors
Electrical characteristics
(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 32. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 33. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 44. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
33.5
1
—
—
—
ns
ns
ns
1
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
63
Electrical characteristics
Table 44. CSI Gated Clock Mode Timing Parameters (continued)
ID
Parameter
CSI DATA hold time
CSI pixel clock high time
Symbol
Min.
Max.
Units
P4
P5
P6
P7
tDh
1
—
—
ns
ns
tCLKh
tCLKl
fCLK
3.75
3.75
—
CSI pixel clock low time
CSI pixel clock frequency
—
ns
133
MHz
4.12.1.0.2 Ungated clock mode timing
Figure 34 shows the ungated clock mode timings of CSI, and Table 45 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[23:00]
Figure 34. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 45. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
33.5
1
—
—
ns
ns
CSI DATA hold time
tDh
1
—
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
—
ns
—
ns
133
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
64
NXP Semiconductors
Electrical characteristics
The following subsections describe the CSI timing in gated and ungated clock modes.
4.12.2 ECSPI timing parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
4.12.2.1 ECSPI master mode timing
Figure 35 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS5
CS2
CS6
CS3
CS1
CS4
ECSPIx_SCLK
ECSPIx_MOSI
ECSPIx_MISO
CS2
CS3
CS7
CS9
CS8
Figure 35. ECSPI Master Mode Timing Diagram
Table 46. ECSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
43
15
—
—
ns
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
21.5
7
CS3 ECSPIx_SCLK Rise or Fall1
tRISE/FALL
tCSLH
tSCS
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
CS4 ECSPIx_SS_B pulse width
Half ECSPIx_SCLK period
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
CS8 ECSPIx_MISO Setup Time
Half ECSPIx_SCLK period - 4
tHCS
Half ECSPIx_SCLK period - 2
tPDmosi
tSmiso
tHmiso
tSDRY
-1
14
0
—
—
—
CS9 ECSPIx_MISO Hold Time
CS10 RDY to ECSPIx_SS_B Time2
5
1
See specific I/O AC parameters Section 4.7, “I/O AC parameters".”
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
65
Electrical characteristics
2
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.12.2.2 ECSPI slave mode timing
Figure 36 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing
characteristics.
ECSPIx_SS_B
CS5
CS6
CS2
CS1
CS4
ECSPIx_SCLK
ECSPIx_MISO
CS2
CS9
CS8
CS7
ECSPIx_MOSI
Figure 36. ECSPI Slave Mode Timing Diagram
Table 47. ECSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
tclk
15
43
—
—
ns
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
7
21.5
CS4 ECSPIx_SS_B pulse width
tCSLH
tSCS
Half ECSPIx_SCLK period
—
—
—
—
—
19
ns
ns
ns
ns
ns
ns
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Setup Time
5
5
4
4
4
tHCS
tSmosi
tHmosi
tPDmiso
CS8 ECSPIx_MOSI Hold Time
CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
66
NXP Semiconductors
Electrical characteristics
4.12.3 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.12.3.1 SD/eMMC4.3 (single data rate) AC timing
Figure 37 depicts the timing of SD/eMMC4.3, and Table 48 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 37. SD/eMMC4.3 Timing
Table 48. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD -6.6
3.6
ns
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
67
Electrical characteristics
Table 48. SD/eMMC4.3 Interface Timing Specification (continued)
Parameter Symbols Min
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ID
Max
Unit
SD7 uSDHC Input Setup Time
SD8 uSDHC Input Hold Time4
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
4
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.12.3.2 eMMC4.4/4.41 (dual data rate) AC timing
Figure 38 depicts the timing of eMMC4.4/4.41. Table 49 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 38. eMMC4.4/4.41 Timing
Table 49. eMMC4.4/4.41 Interface Timing Specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1 Clock Frequency (eMMC4.4/4.41 DDR)
SD1 Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2 uSDHC Output Delay tOD 2.5 7.1
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ns
SD3 uSDHC Input Setup Time
SD4 uSDHC Input Hold Time
tISU
tIH
1.7
1.5
—
—
ns
ns
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
68
NXP Semiconductors
Electrical characteristics
4.12.3.3 SDR50/SDR104 AC timing
Figure 39 depicts the timing of SDR50/SDR104, and Table 50 lists the SDR50/SDR104 timing
characteristics.
6'ꢀ
6'ꢂ
6'ꢆ
6'ꢋ
6&.
ꢇꢍELWꢊRXWSXWꢊIURPꢊX6'+&ꢊWRꢊFDUG
ꢇꢍELWꢊLQSXWꢊIURPꢊFDUGꢊWRꢊX6'+&
6'ꢇꢉ6'ꢃ
6'ꢄ
6'ꢁ
Figure 39. SDR50/SDR104 Timing
Table 50. SDR50/SDR104 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay tOD –3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
1
ns
ns
SD5
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
SD6
SD7
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
—
ns
SD8
1Data window in SDR104 mode is variable.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
69
Electrical characteristics
4.12.3.4 HS200 mode timing
Figure 40 depicts the timing of HS200 mode, and Table 51 lists the HS200 timing characteristics.
6'ꢈ
6'ꢅ
6'ꢄ
6&.
6'ꢊꢆ6'ꢑ
ꢎꢇELWꢀRXWSXWꢀIURPꢀX6'+&ꢀWRꢀH00&
ꢎꢇELWꢀLQSXWꢀIURPꢀH00&ꢀWRꢀX6'+&
6'ꢎ
Figure 40. HS200 Mode Timing
Table 51. HS200 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
ns
ns
SD5
—
SD8
1HS200 is for 8 bits while SDR104 is for 4 bits.
4.12.3.5 Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 23,
"Single Voltage GPIO DC Parameters," on page 35.
4.12.4 Ethernet Controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
70
NXP Semiconductors
Electrical characteristics
4.12.4.1 ENET MII mode timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.12.4.1.1 MII receive signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 41 shows MII receive signal timings. Table 52 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 41. MII Receive Signal Timing Diagram
Table 52. MII Receive Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M1
M2
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
M4
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
35%
35%
65%
65%
ENET_RX_CLK period
ENET_RX_CLK period
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.12.4.1.2 MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
71
Electrical characteristics
Figure 42 shows MII transmit signal timings. Table 53 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 42. MII Transmit Signal Timing Diagram
Table 53. MII Transmit Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M5
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
M8
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
35%
35%
65%
65%
ENET_TX_CLK period
ENET_TX_CLK period
1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.12.4.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 43 shows MII asynchronous input timings. Table 54 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 43. MII Async Inputs Timing Diagram
Table 54. MII Asynchronous Inputs Signal Timing
ID
M91
Characteristic
Min.
Max.
Unit
ENET_CRS to ENET_COL minimum pulse width
1.5
—
ENET_TX_CLK period
1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
72
NXP Semiconductors
Electrical characteristics
4.12.4.1.4 MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 44 shows MII asynchronous input timings. Table 55 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 44. MII Serial Management Channel Timing Diagram
Table 55. MII Serial Management Channel Timing
ID
M10
Characteristic
Min.
Max.
Unit
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
M13
M14
M15
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
18
0
—
—
ns
ns
40%
40%
60%
60%
ENET_MDC period
ENET_MDC period
ENET_MDC pulse width low
4.12.4.2 RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
73
Electrical characteristics
Figure 45 shows RMII mode timings. Table 56 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 45. RMII Mode Signal Timing Diagram
Table 56. RMII Signal Timing
ID
M16
Characteristic
Min.
Max.
Unit
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
M17
M18
M19
M20
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
13
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.12.5 Flexible Controller Area Network (FLEXCAN) AC electrical
specifications
The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing
the CAN protocol according to the CAN 2.0B protocol specification. The processor has two CAN modules
available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See
the IOMUXC chapter of the i.MX 6UltraLite Reference Manual (IMX6ULRM) to see which pins expose
Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
74
NXP Semiconductors
Electrical characteristics
4.12.6 I2C module timing parameters
2
2
This section describes the timing parameters of the I C module. Figure 46 depicts the timing of I C
2
module, and Table 57 lists the I C module timing characteristics.
IC11
IC9
IC10
I2Cx_SDA
I2Cx_SCL
IC7
IC4
IC2
IC3
IC8
IC10
IC6
IC11
STOP
START
START
START
IC5
IC1
2
Figure 46. I C Bus Timing
2
Table 57. I C Module Timing Parameters
Standard Mode
Fast Mode
ID
Parameter
Unit
Min
Max
Min
Max
IC1
IC2
IC3
I2Cx_SCL cycle time
10
4.0
4.0
01
—
—
2.5
0.6
0.6
01
—
—
—
µs
µs
µs
Hold time (repeated) START condition
Set-up time for STOP condition
—
IC4
Data hold time
3.452
—
0.92 µs
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
HIGH Period of I2Cx_SCL Clock
LOW Period of the I2Cx_SCL Clock
Set-up time for a repeated START condition
Data set-up time
4.0
4.7
4.7
250
4.7
—
0.6
1.3
0.6
1003
1.3
—
—
—
—
—
µs
µs
µs
ns
µs
—
—
—
Bus free time between a STOP and START condition
Rise time of both I2Cx_SDA and I2Cx_SCL signals
Fall time of both I2Cx_SDA and I2Cx_SCL signals
Capacitive load for each bus line (Cb)
—
4
1000
300
400
20 + 0.1Cb 300 ns
4
—
20 + 0.1Cb 300 ns
—
—
400 pF
1
A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling
edge of I2Cx_SCL.
2
3
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2Cx_SCL line is released.
4
Cb = total capacitance of one bus line in pF.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
75
Electrical characteristics
4.12.7 Pulse Width Modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 47 depicts the timing of the PWM, and Table 58 lists the PWM timing parameters.
0ꢄ
0ꢇ
07-N?/54
Figure 47. PWM Timing
Table 58. PWM Output Timing Parameters
ID
Parameter
Min
Max
Unit
PWM Module Clock Frequency
PWM output pulse width high
PWM output pulse width low
0
ipg_clk
—
MHz
ns
P1
P2
15
15
—
ns
4.12.8 LCD Controller (LCDIF) parameters
Figure 48 shows the LCDIF timing and Table 59 lists the timing parameters.
/ꢀ
/ꢂ
/ꢆ
/&'QB&/.
ꢎIDOOLQJꢊHGJHꢊFDSWXUHꢏ
/&'QB&/.
ꢎULVLQJꢊHGJHꢊFDSWXUHꢏ
/&'QB'$7$>ꢂꢆꢌꢅꢅ@
/&'Qꢊ&RQWUROꢊ6LJQDOV
/ꢇ
/ꢃ
/ꢄ
/ꢋ
Figure 48. LCD Timing
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
76
NXP Semiconductors
Electrical characteristics
Table 59. LCD Timing Parameters
Parameter
ID
Symbol
Min
Max
Unit
L1
L2
L3
L4
L5
L6
L7
LCD pixel clock frequency
tCLK(LCD)
tCLKH(LCD)
tCLKL(LCD)
td(CLKH-DV)
td(CLKL-DV)
—
3
150
—
—
1
MHz
ns
LCD pixel clock high (falling edge capture)
LCD pixel clock low (rising edge capture)
3
ns
LCD pixel clock high to data valid (falling edge capture)
LCD pixel clock low to data valid (rising edge capture)
-1
-1
-1
-1
ns
1
ns
LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV)
LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV)
1
ns
1
ns
4.12.8.1 LCDIF signal mapping
Table 60 lists the details about the mapping signals.
Table 60. LCD Signal Parameters
8-bit DOTCLK LCD 16-bit DOTCLK LCD 18-bit DOTCLK LCD 24-bit DOTCLK LCD 8-bit DVI LCD
Pin name
IF
IF
IF
IF
IF
LCD_RS
—
—
—
—
CCIR_CLK
—
LCD_VSYNC*
(Two options)
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
LCD_HSYNC
LCD_DOTCLK
LCD_ENABLE
LCD_D23
LCD_HSYNC
LCD_HSYNC
LCD_HSYNC
LCD_HSYNC
—
—
—
—
—
—
—
—
—
—
—
—
LCD_DOTCLK
LCD_DOTCLK
LCD_DOTCLK
LCD_DOTCLK
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
R[7]
—
—
—
—
—
—
—
—
—
—
—
—
—
LCD_D22
R[6]
LCD_D21
—
—
R[5]
LCD_D20
—
—
R[4]
LCD_D19
—
—
R[3]
LCD_D18
—
—
R[2]
LCD_D17
—
R[5]
R[4]
R[3]
R[1]
LCD_D16
—
R[0]
LCD_D15 /
VSYNC*
R[4]
G[7]
LCD_D14 /
HSYNC**
—
—
R[3]
R[2]
R[1]
G[6]
G[5]
—
—
LCD_D13 /
LCD_DOTCLK
**
R21]
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
77
Electrical characteristics
Table 60. LCD Signal Parameters (continued)
LCD_D12 /
ENABLE**
—
R[1]
R[0]
G[4]
—
LCD_D11
LCD_D10
LCD_D9
LCD_D8
LCD_D8
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD_RESET
—
—
R[0]
G[5]
G[5]
G[4]
G[3]
G[2]
—
—
—
G[4]
G[3]
G[1]
—
—
G[3]
G[2]
G[0]
—
—
G[3]
G[2]
G[0]
—
R[2]
R[1]
R[0]
G[2]
G[1]
G[0]
B[1]
G[2]
G[1]
B[7]
Y/C[7]
Y/C[6]
Y/C[5]
Y/C[4]
Y/C[3]
Y/C[2]
Y/C[1]
Y/C[0]
—
G[1]
G[0]
B[6]
G[0]
B[5]
B[5]
B[4]
B[4]
B[4]
B[3]
B[3]
B[3]
B[2]
B[2]
B[2]
B[1]
B[1]
B[1]
B[0]
B[0]
B[0]
B[0]
LCD_RESET
LCD_RESET
LCD_RESET
LCD_RESET
LCD_BUSY /
LCD_VSYNC
LCD_BUSY (or
optional
LCD_BUSY (or
optional LCD_VSYNC)
LCD_BUSY (or
optional
LCD_BUSY (or
optional
—
LCD_VSYNC)
LCD_VSYNC)
LCD_VSYNC)
4.12.9 QUAD SPI (QSPI) timing parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
4.12.9.1 SDR mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢅꢌꢆ@
Figure 49. QuadSPI Input/Read Timing (SDR mode with internal sampling)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
78
NXP Semiconductors
Electrical characteristics
Table 61. QuadSPI Input Timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
TIS
TIH
Setup time for incoming data
—
—
ns
ns
Hold time requirement for incoming data
0
ꢈ
ꢅ
ꢄ
ꢊ
463,[B6&/.
463,[B'$7$>ꢉꢒꢄ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 50. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Table 62. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
463,[B&6
7&6+
7&66
7&.
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 51. QuadSPI Output/Write Timing (SDR mode)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
79
Electrical characteristics
Table 63. QuadSPI Output/Write Timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
TDHO
TCK
Output data valid time
Output data hold time
SCK clock period
—
0
2
ns
ns
ns
—
—
—
—
10
3
TCSS
TCSH
Chip select output setup time
Chip select output hold time
SCK cycle(s)
SCK cycle(s)
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register, the default
T
css
csh
value of 3 are shown on the timing. Please refer to the i.MX 6UltraLite
Reference Manual (IMX6ULRM) for more details.
4.12.9.2 DDR mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢉꢒꢄ@
Figure 52. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Table 64. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
TIS
TIH
Setup time for incoming data
—
—
ns
ns
Hold time requirement for incoming data
0
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
80
NXP Semiconductors
Electrical characteristics
ꢈ
ꢅ
ꢄ
ꢊ
463,[B6&/.
463,[B'$7$>ꢉꢒꢄ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 53. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Table 65. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
ꢈ
ꢅ
463,[B6&/.
463,[B&6
7&66
7&.
7&6+
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 54. QuadSPI Output/Write Timing (DDR mode)
Table 66. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
TDHO
TCK
Output data valid time
Output data hold time
SCK clock period
—
0.25 x TSCLK + 2 ns
ns
ns
ns
0.25 x TSCLK
20
—
—
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
81
Electrical characteristics
Table 66. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TCSS
TCSH
Chip select output setup time
Chip select output hold time
3
3
—
—
SCK cycle(s)
SCK cycle(s)
NOTE
T
and T are configured by the QuadSPIx_FLSHCR register, the default
csh
css
value of 3 are shown on the timing. Please refer to the i.MX 6UltraLite
Reference Manual (IMX6ULRM) for more details.
4.12.10 SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 67. Master Mode SAI Timing
Num
Characteristic
SAI_MCLK cycle time
Min
2 x tsys
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
40%
4 x tsys
40%
—
60%
—
MCLK period
ns
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
60%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
SAI_BCLK to SAI_TXD invalid
0
—
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
—
0
—
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
82
NXP Semiconductors
Electrical characteristics
Figure 55. SAI Timing — Master Modes
Table 68. Master Mode SAI Timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
4 x tsys
Max
Unit
S11
S12
S13
S14
S15
S16
S17
S18
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
SAI_RXD setup before SAI_BCLK
40%
10
2
60%
—
BCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
SAI_RXD hold after SAI_BCLK
—
Figure 56. SAI Timing — Slave Modes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
83
Electrical characteristics
4.12.11 SCAN JTAG Controller (SJC) timing parameters
Figure 57 depicts the SJC test clock input timing. Figure 58 depicts the SJC boundary scan timing.
Figure 59 depicts the SJC test access port. Signal parameters are listed in Table 69.
SJ1
SJ2
SJ2
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ3
SJ3
Figure 57. Test Clock Input Timing Diagram
JTAG_TCK
(Input)
VIH
SJ5
VIL
SJ4
Input Data Valid
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 58. Boundary Scan (JTAG) Timing Diagram
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
84
NXP Semiconductors
Electrical characteristics
JTAG_TCK
(Input)
VIH
SJ9
VIL
SJ8
Input Data Valid
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 59. Test Access Port Timing Diagram
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
Figure 60. JTAG_TRST_B Timing Diagram
Table 69. JTAG Timing
All Frequencies
Min Max
ID
Parameter1,2
Unit
1
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
JTAG_TCK frequency of operation 1/(3•TDC
)
0.001
45
22.5
—
22
—
—
3
MHz
ns
JTAG_TCK cycle time in crystal mode
2
JTAG_TCK clock pulse width measured at VM
JTAG_TCK rise and fall times
ns
ns
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
5
—
—
40
40
—
ns
24
—
ns
ns
—
ns
5
ns
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
85
Electrical characteristics
Table 69. JTAG Timing (continued)
Parameter1,2
All Frequencies
ID
Unit
Min
Max
SJ9
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
25
—
—
44
44
—
—
ns
ns
ns
ns
ns
SJ10
SJ11
SJ12
SJ13
—
100
40
JTAG_TRST_B set-up time to JTAG_TCK low
1
2
T
= target frequency of SJC
DC
VM = mid-point voltage
4.12.12 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 70 and Figure 61 and Figure 62 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 70. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
ns
SPDIF_OUT output (Load = 50pf)
—
—
—
—
—
—
1.5
24.2
31.3
• Skew
• Transition rising
• Transition falling
SPDIF_OUT1 output (Load = 30pf)
—
—
—
ns
• Skew
• Transition rising
• Transition falling
—
—
—
1.5
13.6
18.0
Modulating Rx clock (SPDIF_SR_CLK) period
SPDIF_SR_CLK high period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
SPDIF_ST_CLK low period
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
86
NXP Semiconductors
Electrical characteristics
srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 61. SPDIF_SR_CLK Timing Diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 62. SPDIF_ST_CLK Timing Diagram
4.12.13 UART I/O configuration and timing parameters
4.12.13.1 UART RS-232 serial mode timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.12.13.1.1 UART transmitter
Figure 63 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit
format. Table 71 lists the UART RS-232 serial mode transmits timing characteristics.
Possible
UA1
UA1
Parity
Bit
Next
Start
Bit
Start
Bit
UARTx_TX_DATA
(output)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Par Bit
UA1
UA1
Figure 63. UART RS-232 Serial Mode Transmit Timing Diagram
Table 71. RS-232 Serial Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + Tref_clk
Unit
2
UA1 Transmit Bit Time
tTbit
1/Fbaud_rate1 - Tref_clk
—
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
87
Electrical characteristics
4.12.13.1.2 UART receiver
Figure 64 depicts the RS-232 serial mode receives timing with 8 data bit/1 stop bit format. Table 72 lists
serial mode receive timing characteristics.
Possible
Parity
UA2
UA2
Bit 3
Bit
Next
Start
Bit
Start
Bit
STOP
BIT
UARTx_RX_DATA
(output)
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA2
UA2
Figure 64. UART RS-232 Serial Mode Receive Timing Diagram
Table 72. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16
1/Fbaud_rate
+
—
x Fbaud_rate
)
1/(16 x Fbaud_rate)
1
2
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.13.1.3 UART IrDA mode timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA mode transmitter
Figure 65 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 73 lists
the transmit timing characteristics.
UA4
UA3
UA3
UA3
UA3
UARTX_TX_
DATA
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 65. UART IrDA Mode Transmit Timing Diagram
Table 73. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + Tref_clk
Unit
1
UA3
Transmit Bit Time in IrDA mode
Transmit IR Pulse Duration
tTIRbit
1/Fbaud_rate
-
—
2
Tref_clk
UA4
tTIRpulse (3/16) x (1/Fbaud_rate
- Tref_clk
)
(3/16) x (1/Fbaud_rate
)
—
+ Tref_clk
1
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
88
NXP Semiconductors
Electrical characteristics
2
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
UART IrDA mode receiver
Figure 66 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 74 lists
the receive timing characteristics.
UA6
UA5
UA5
UA5
UA5
UARTx_RX_
DATA
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 66. UART IrDA Mode Receive Timing Diagram
Table 74. IrDA Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA5
Receive Bit Time1 in IrDA mode
tRIRbit
1/Fbaud_rate2 - 1/(16 1/Fbaud_rate + 1/(16 x
—
x Fbaud_rate
)
Fbaud_rate
)
UA6
Receive IR Pulse Duration
tRIRpulse
1.41 s
(5/16) x (1/Fbaud_rate
)
—
1
2
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.14 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
89
Electrical characteristics
— Applies to: Universal Serial Bus Specification, Revision 2.0
•
•
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
— Portable device only
4.13 A/D converter
4.13.1 12-bit ADC electrical characteristics
4.13.1.1 12-bit ADC operating conditions
Table 75. 12-bit ADC Operating Conditions
Typ1
Characteristic
Supply voltage
Conditions
Absolute
Symb
Min
Max
Unit
Comment
VDDAD
3.0
-
3.6
V
—
—
Delta to VDD
VDDAD -100
0
100
mV
(VDD-VDDAD)2
Ground voltage
Delta to VSS
VSSAD
-100
0
100
mV
—
(VSS-VSSAD)
Ref Voltage High
Ref Voltage Low
Input Voltage
—
VREFH
VREFL
VADIN
CADIN
RADIN
1.13
VSSAD
VREFL
—
VDDAD
VSSAD
—
VDDAD
V
—
—
—
—
—
—
—
—
VSSAD
V
—
VREFH
V
Input Capacitance
Input Resistance
8/10/12 bit modes
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
1.5
2
pF
—
5
7
kohms
kohms
kohms
kohms
—
12.5
25
15
30
1
—
Analog Source
Resistance
12 bit mode fADCK
40MHz ADLSMP=0,
=
RAS
—
—
Tsamp=150
ns
ADSTS=10, ADHSC=1
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1
fADCK
4
4
4
—
—
—
40
30
20
MHz
MHz
MHz
—
—
—
Frequency
12 bit mode
ADLPC=0, ADHSC=0
12 bit mode
ADLPC=1, ADHSC=0
12 bit mode
1
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
90
NXP Semiconductors
Electrical characteristics
2
DC potential differences
Figure 67. 12-bit ADC Input Impedance Equivalency Diagram
4.13.1.1.1
12-bit ADC characteristics
Table 76. 12-bit ADC Characteristics (V
= V
, V
= V
)
REFH
DDAD
REFL
SSAD
Characteristic
[L:] Supply Current
Conditions1
Symb
IDDAD
Min
Typ2
Max
Unit
Comment
ADLSMP=0
ADLPC=1,
ADHSC=0
—
250
350
400
0.01
—
µA
ADSTS=10 ADCO=1
ADLPC=0,
ADHSC=0
ADLPC=0,
ADHSC=1
[L:] Supply Current
Stop, Reset, Module IDDAD
Off
—
0.8
µA
—
ADC Asynchronous ADHSC=0
fADACK
—
—
10
20
—
—
MHz
tADACK = 1/fADACK
Clock Source
ADHSC=1
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
91
Electrical characteristics
Table 76. 12-bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSAD
REFH
Min
DDAD
Typ2
REFL
Characteristic
Conditions1
Symb
Max
Unit
cycles
Comment
Sample Cycles
ADLSMP=0,
Csamp
—
2
4
6
8
—
—
ADSTS=00
ADLSMP=0,
ADSTS=01
ADLSMP=0,
ADSTS=10
ADLSMP=0,
ADSTS=11
ADLSMP=1,
ADSTS=00
12
ADLSMP=1,
ADSTS=01
16
20
24
28
30
32
34
38
42
46
50
ADLSMP=1,
ADSTS=10
ADLSMP=1,
ADSTS=11
Conversion Cycles
ADLSMP=0
ADSTS=00
Cconv
—
—
cycles
—
ADLSMP=0
ADSTS=01
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
92
NXP Semiconductors
Electrical characteristics
) (continued)
Table 76. 12-bit ADC Characteristics (V
= V
, V
= V
REFL SSAD
REFH
DDAD
Typ2
Characteristic
Conditions1
Symb
Tconv
Min
Max
Unit
Comment
Conversion Time
ADLSMP=0
—
0.7
—
µs
Fadc=40 MHz
ADSTS=00
ADLSMP=0
ADSTS=01
0.75
0.8
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
0.85
0.95
1.05
1.15
1.25
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
[P:][C:] Total
Unadjusted Error
12 bit mode
10 bit mode
8 bit mode
TUE
—
—
—
4.5
2
—
—
—
LSB
1 LSB =
(VREFH
VREFL)/2
N
—
-
1.5
[P:][C:] Differential
Non-Linearity
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
LSB
LSB
LSB
LSB
—
—
—
—
0.5
0.2
[P:][C:] Integral
Non-Linearity
2.6
0.8
0.3
Zero-Scale Error
Full-Scale Error
EZS
-0.3
-0.15
-0.15
-2.5
-0.6
-0.3
10.7
EFS
[L:] Effective Number 12 bit mode
of Bits
ENOB
SINAD
10.1
Bits
dB
—
—
[L:] Signal to Noise
plus Distortion
See ENOB
SINAD = 6.02 x ENOB + 1.76
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
93
Electrical characteristics
2
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
94
NXP Semiconductors
Boot mode configuration
5 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot mode configuration pins
Table 77 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX
6UltraLite Fuse Map document and the System Boot chapter in i.MX 6UltraLite Reference Manual
(IMX6ULRM).
Table 77. Fuses and Associated Pins Used for Boot
Pin
Direction at reset
eFuse name
Details
BOOT_MODE0
BOOT_MODE1
Input with 100 K pull-down N/A
Input with 100 K pull-down N/A
Boot mode selection
Boot mode selection
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
95
Boot mode configuration
Table 77. Fuses and Associated Pins Used for Boot (continued)
Pin
Direction at reset
eFuse name
Details
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
Input with 100 K pull-down BT_CFG1[0]
Input with 100 K pull-down BT_CFG1[1]
Input with 100 K pull-down BT_CFG1[2]
Input with 100 K pull-down BT_CFG1[3]
Input with 100 K pull-down BT_CFG1[4]
Input with 100 K pull-down BT_CFG1[5]
Input with 100 K pull-down BT_CFG1[6]
Input with 100 K pull-down BT_CFG1[7]
Input with 100 K pull-down BT_CFG2[0]
Input with 100 K pull-down BT_CFG2[1]
Input with 100 K pull-down BT_CFG2[2]
Input with 100 K pull-down BT_CFG2[3]
Input with 100 K pull-down BT_CFG2[4]
Input with 100 K pull-down BT_CFG2[5]
Input with 100 K pull-down BT_CFG2[6]
Input with 100 K pull-down BT_CFG2[7]
Input with 100 K pull-down BT_CFG4[0]
Input with 100 K pull-down BT_CFG4[1]
Input with 100 K pull-down BT_CFG4[2]
Input with 100 K pull-down BT_CFG4[3]
Input with 100 K pull-down BT_CFG4[4]
Input with 100 K pull-down BT_CFG4[5]
Input with 100 K pull-down BT_CFG4[6]
Input with 100 K pull-down BT_CFG4[7]
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
5.2
Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the
specific boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC
allocation, which are configured during boot when appropriate.
Table 78. QSPI Boot trough QSPI
Mux
Mode
Quad
Mode
+ Port A + Port A + Port + Port B + Port B
DQS CS1 DQS CS1
Ball Name
Signal Name
Common
B
NAND_WP_B
NAND_DQS
qspi.A_SCLK
qspi.A_SS0_B
Alt2
Alt2
Yes
Yes
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
96
NXP Semiconductors
Boot mode configuration
Table 78. QSPI Boot trough QSPI (continued)
NAND_READY_B qspi.A_DATA[0]
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_CE0_B
NAND_CE1_B
NAND_CLE
qspi.A_DATA[1]
qspi.A_DATA[2]
qspi.A_DATA[3]
qspi.B_DATA[3]
qspi.B_DATA[2]
qspi.B_DATA[1]
qspi.B_DATA[0]
qspi.B_SS0_B
qspi.B_SCLK
qspi.A_SS1_B
qspi.A_DQS
NAND_DATA05
NAND_DATA04
NAND_DATA03
NAND_DATA02
NAND_WE_B
NAND_RE_B
NAND_DATA07
NAND_ALE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_DATA00
NAND_DATA01
qspi.B_SS1_B
qspi.B_DQS
Yes
Yes
Table 79. SPI Boot through ECSPI1
Mux
Mode
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
Ball Name
Signal Name
Common
[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
CSI_DATA07
CSI_DATA06
CSI_DATA04
CSI_DATA05
LCD_DATA05
LCD_DATA06
LCD_DATA07
ecspi1.MISO
ecspi1.MOSI
ecspi1.SCLK
ecspi1.SS0
ecspi1.SS1
ecspi1.SS2
ecspi1.SS3
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 80. SPI Boot through ECSPI2
BOOT_CFG BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
Ball Name
Signal Name
Mux Mode Common
4[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
CSI_DATA03
CSI_DATA02
CSI_DATA00
CSI_DATA01
LCD_HSYNC
ecspi2.MISO
ecspi2.MOSI
ecspi2.SCLK
ecspi2.SS0
ecspi2.SS1
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Yes
Yes
Yes
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
97
Boot mode configuration
Table 80. SPI Boot through ECSPI2 (continued)
LCD_VSYNC
LCD_RESET
ecspi2.SS2
Alt 8
Alt 8
Yes
ecspi2.SS3
Yes
Table 81. SPI Boot through ECSPI3
Mux
Mode
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[ BOOT_CFG4
Ball Name
Signal Name
Common
[5:4]=00b
5:4]=01b
5:4]=10b
[5:4]=11b
UART2_RTS_B
UART2_CTS_B
ecspi3.MISO
ecspi3.MOSI
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
UART2_RX_DATA ecspi3.SCLK
UART2_TX_DATA
NAND_ALE
ecspi3.SS0
ecspi3.SS1
ecspi3.SS2
ecspi3.SS3
Yes
Yes
NAND_RE_B
NAND_WE_B
Yes
Yes
Table 82. SPI Boot through ECSPI4
Mux
Mode
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4[ BOOT_CFG
Ball Name
Signal Name
Common
[5:4]=00b
[5:4]=01b
5:4]=10b
4[5:4]=11b
ENET2_TX_CLK
ENET2_TX_EN
ecspi4.MISO
ecspi4.MOSI
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
ENET2_TX_DATA1 ecspi4.SCLK
ENET2_RX_ER
NAND_DATA01
NAND_DATA02
NAND_DATA03
ecspi4.SS0
ecspi4.SS1
ecspi4.SS2
ecspi4.SS3
Yes
Yes
Yes
Yes
Table 83. NAND Boot through GPMI
BOOT_CFG1[3:2]= BOOT_CFG1[3:2]=
Ball Name
Signal Name
Mux Mode Common
01b
10b
NAND_CLE
NAND_ALE
rawnand.CLE
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Yes
Yes
Yes
Yes
Yes
rawnand.ALE
rawnand.WP_B
rawnand.READY_B
rawnand.CE0_B
rawnand.CE1_B
rawnand.RE_B
rawnand.WE_B
NAND_WP_B
NAND_READY_B
NAND_CE0_B
NAND_CE1_B
NAND_RE_B
NAND_WE_B
Yes
Yes
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
98
NXP Semiconductors
Boot mode configuration
Table 83. NAND Boot through GPMI (continued)
BOOT_CFG1[3:2]= BOOT_CFG1[3:2]=
Ball Name
Signal Name
Mux Mode Common
01b
10b
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
rawnand.DATA00
rawnand.DATA01
rawnand.DATA02
rawnand.DATA03
rawnand.DATA04
rawnand.DATA05
rawnand.DATA06
rawnand.DATA07
rawnand.DQS
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 2
Alt 2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CSI_MCLK
rawnand.CE2_B
rawnand.CE3_B
Yes
Yes
CSI_PIXCLK
Table 84. SD/MMC Boot through USDHC1
Mux
SDMMC
MFG
mode
BOOT_CFG1[1]=1
(SD Power Cycle)
Ball Name
Signal Name
Common
4-bit
8-bit
Mode
UART1_RTS_B
SD1_CLK
usdhc1.CD_B
usdhc1.CLK
Alt 2
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 1
Alt 1
Alt 1
Alt 1
Alt 5
Alt 4
Yes
Yes
Yes
Yes
SD1_CMD
usdhc1.CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
NAND_READY_B
NAND_CE0_B
NAND_CE1_B
NAND_CLE
usdhc1.DATA0
usdhc1.DATA1
usdhc1.DATA2
usdhc1.DATA3
usdhc1.DATA4
usdhc1.DATA5
usdhc1.DATA6
usdhc1.DATA7
usdhc1.RESET_B
usdhc1.VSELECT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GPIO1_IO09
GPIO1_IO05
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
99
Boot mode configuration
Ball Name
Table 85. SD/MMC Boot through USDHC2
Commo
BOOT_CFG1[1]=1
(SD Power Cycle)
Signal Name
Mux Mode
4-bit
8-bit
n
NAND_RE_B
NAND_WE_B
usdhc2.CLK
usdhc2.CMD
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 5
Alt 4
Yes
Yes
Yes
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
usdhc2.DATA0
usdhc2.DATA1
usdhc2.DATA2
usdhc2.DATA3
usdhc2.DATA4
usdhc2.DATA5
usdhc2.DATA6
usdhc2.DATA7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_ALE
GPIO1_IO08
usdhc2.RESET_B
usdhc2.VSELECT
Yes
Yes
Table 86. NOR/OneNAND Boot through EIM
ADL16
Non-Mux
Ball Name
Signal Name
Mux Mode
Common
AD16 Mux
CSI_DATA00
CSI_DATA01
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_CLE
weim.AD[0]
weim.AD[1]
weim.AD[2]
weim.AD[3]
weim.AD[4]
weim.AD[5]
weim.AD[6]
weim.AD[7]
weim.AD[8]
weim.AD[9]
weim.AD[10]
weim.AD[11]
weim.AD[12]
weim.AD[13]
weim.AD[14]
weim.AD[15]
weim.ADDR[16]
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
100
NXP Semiconductors
Boot mode configuration
Table 86. NOR/OneNAND Boot through EIM (continued)
ADL16
Non-Mux
Ball Name
Signal Name
Mux Mode
Common
AD16 Mux
NAND_ALE
NAND_CE1_B
SD1_CMD
weim.ADDR[17]
weim.ADDR[18]
weim.ADDR[19]
weim.ADDR[20]
weim.ADDR[21]
weim.ADDR[22]
weim.ADDR[23]
weim.ADDR[24]
weim.ADDR[25]
weim.ADDR[26]
weim.CS0_B
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SD1_CLK
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
ENET2_RXER
ENET2_CRS_DV
CSI_MCLK
Yes
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
NAND_RE_B
NAND_WE_B
CSI_HSYNC
CSI_PIXCLK
CSI_VSYNC
weim.DATA[0]
weim.DATA[1]
weim.DATA[2]
weim.DATA[3]
weim.DATA[4]
weim.DATA[5]
weim.DATA[6]
weim.DATA[7]
weim.DATA[8]
weim.DATA[9]
weim.DATA[10]
weim.DATA[11]
weim.DATA[12]
weim.DATA[13]
weim.DATA[14]
weim.DATA[15]
weim.EB_B[0]
weim.EB_B[1]
weim.LBA_B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
weim.OE
weim.RW
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
101
Boot mode configuration
Ball Name
Table 87. Serial Download through UART1
Signal Name
Mux Mode
Common
UART1_TX_DATA
UART1_RX_DATA
uart1.TX_DATA
uart1.RX_DATA
Alt 0
Alt 0
Yes
Yes
Table 88. Serial Download through UART2
Ball Name
Signal Name
Mux Mode
Common
UART2_TX_DATA
UART2_RX_DATA
uart2.TX_DATA
uart2.RX_DATA
Alt 0
Alt 0
Yes
Yes
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
102
NXP Semiconductors
Package information and contact assignments
6 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
14x14 mm package information
14x14 mm, 0.8 mm pitch, ball matrix
6.1.1
Figure 68 shows the top, bottom, and side views of the 14x14 mm BGA package.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
103
Package information and contact assignments
Figure 68. 14x14 mm BGA, Case x Package Top, Bottom, and Side Views
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
104
NXP Semiconductors
Package information and contact assignments
6.1.2
14x14 mm supplies contact assignments and functional contact
assignments
Table 89 shows the device connection list for ground, sense, and reference contact signals.
Table 89. 14x14 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
DRAM_VREF
GPANAIO
M13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
p4
R13
NGND_KEL0
NVCC_CSI
M12
F4
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_ENET
NVCC_GPIO
NVCC_LCD
G6, H6, J6, K6, L6, M6
N6
F13
J13
E13
NVCC_NAND
NVCC_PLL
E7
P13
NVCC_SD1
C4
NVCC_UART
VDD_ARM_CAP
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_CAP
VDD_SOC_IN
VDD_USB_CAP
VDDA_ADC_3P3
VSS
H13
G9, G10, G11, H11
R14, R15
N13
N12
P12
G8, H8, J8, J11, K8, K11, L8, L9, L10, L11
H9, H10, J9, J10, K9, K10
R12
L13
A1, A17, C3, C7, C11, C15, E8, E11, F6, F7, F8, F9, F10,F11, F12, G3, G5, G7,
G12, G15, H7, H12, J5, J7, J12, K7, K12, L3, L7, L12, M7, M8, M9, M10, M11,
N3, N5, R3, R5, R7, R11, R16, R17, T14, U1, U14, U17
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
105
Package information and contact assignments
Table 90 shows an alpha-sorted list of functional contact assignments for the 14x14 mm package.
Table 90. 14x14 mm Functional Contact Assignments
Out of Reset Condition
14x14
Ball
Power
Group
Ball
Type
Ball Name
Default
Mode
Default
Function
Input/
Output
Value
BOOT_MODE0
T10
U10
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
ALT5
ALT5
BOOT_MODE0
BOOT_MODE1
Input
Input
100 k
pull-down
BOOT_MODE1
100 k
pull-down
CCM_CLK1_N
CCM_CLK1_P
CCM_PMIC_STBY_REQ
CSI_DATA00
CSI_DATA01
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
CSI_HSYNC
P16
P17
U9
E4
E3
E2
E1
D4
D3
D2
D1
F3
VDD_HIGH_CAP
VDD_HIGH_CAP
VDD_SNVS_IN
NVCC_CSI
LVDS
LVDS
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DDR
—
—
CCM_CLK1_N
CCM_CLK1_P
—
—
—
—
ALT0 CCM_PMIC_STBY_REQ Output
—
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
CSI_DATA00
CSI_DATA01
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
CSI_HSYNC
CSI_MCLK
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
CSI_MCLK
F5
NVCC_CSI
CSI_PIXCLK
CSI_VSYNC
E5
F2
NVCC_CSI
CSI_PIXCLK
CSI_VSYNC
DRAM_ADDR00
NVCC_CSI
DRAM_ADDR00
L5
NVCC_DRAM
100 k
pull-up
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
H2
K1
M2
K4
L1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
Output
Output
Output
Output
Output
Output
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
G2
100 k
pull-up
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
106
NXP Semiconductors
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
H4
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
J4
100 k
pull-up
L2
100 k
pull-up
M4
K3
L4
100 k
pull-up
100 k
pull-up
100 k
pull-up
H3
G1
K5
J2
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
N2
H5
T4
U6
T6
U7
U8
T8
T5
U4
U2
100 k
pull-up
100 k
pull-up
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
107
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
U3
U5
R4
P5
P3
R2
R1
T7
T3
N1
F1
M5
G4
M1
H1
K2
M3
J3
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
Input
Input
100 k
pull-up
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
DRAM_DQM1
DRAM_DQM1
100 k
pull-up
DRAM_ODT0
DRAM_ODT0
100 k
pull-down
DRAM_ODT1
DRAM_ODT1
100 k
pull-down
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
100 k
pull-up
100 k
pull-down
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-down
100 k
pull-down
P2
P1
P7
DDRCLK ALT0
DDRCLK ALT0
DDRCLK ALT0
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-down
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
108
NXP Semiconductors
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDWE_B
P6
T2
T1
J1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDRCLK ALT0
DDRCLK ALT0
DDRCLK ALT0
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDWE_B
Input
100 k
pull-down
Input
100 k
pull-down
Input
100 k
pull-down
DDR
ALT0
Output
100 k
pull-up
DRAM_ZQPAD
ENET1_RX_DATA0
ENET1_RX_DATA1
ENET1_RX_EN
ENET1_RX_ER
ENET1_TX_CLK
ENET1_TX_DATA0
ENET1_TX_DATA1
ENET1_TX_EN
ENET2_RX_DATA0
ENET2_RX_DATA1
ENET2_RX_EN
ENET2_RX_ER
ENET2_TX_CLK
ENET2_TX_DATA0
ENET2_TX_DATA1
ENET2_TX_EN
GPIO1_IO00
N4
NVCC_DRAM
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
DRAM_ZQPAD
ENET1_RX_DATA0
ENET1_RX_DATA1
ENET1_RX_EN
ENET1_RX_ER
ENET1_TX_CLK
ENET1_TX_DATA0
ENET1_TX_DATA1
ENET1_TX_EN
ENET2_RX_DATA0
ENET2_RX_DATA1
ENET2_RX_EN
ENET2_RX_ER
ENET2_TX_CLK
ENET2_TX_DATA0
ENET2_TX_DATA1
ENET2_TX_EN
GPIO1_IO00
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
F16
E17
E16
D15
F14
E15
E14
F15
C17
C16
B17
D16
D17
A15
A16
B15
K13
L15
L14
L17
M16
M17
K17
L16
N17
M15
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_IO01
GPIO1_IO01
GPIO1_IO02
GPIO1_IO02
GPIO1_IO03
GPIO1_IO03
GPIO1_IO04
GPIO1_IO04
GPIO1_IO05
GPIO1_IO05
GPIO1_IO06
GPIO1_IO06
GPIO1_IO07
GPIO1_IO07
GPIO1_IO08
GPIO1_IO08
GPIO1_IO09
GPIO1_IO09
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
109
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
JTAG_MOD
JTAG_TCK
JTAG_TDI
P15
M14
N16
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
JTAG_MOD
JTAG_TCK
JTAG_TDI
Input
Input
Input
100 k
pull-up
47 k
pull-up
47 k
pull-up
JTAG_TDO
JTAG_TMS
N15
P14
NVCC_GPIO
NVCC_GPIO
GPIO
GPIO
ALT5
ALT5
JTAG_TDO
JTAG_TMS
Output
Input
Keeper
47 k
pull-up
JTAG_TRST_B
N14
NVCC_GPIO
GPIO
ALT5
JTAG_TRST_B
Input
47 k
pull-up
LCD_CLK
A8
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
LCD_CLK
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
B9
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
A9
E10
D10
C10
B10
A10
D11
B11
A11
E12
D12
C12
B12
A12
D13
C13
B13
A13
D14
C14
B14
A14
B16
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
110
NXP Semiconductors
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
NAND_ALE
B8
D9
E9
C9
B4
C5
B5
A4
D7
B7
A7
D6
C6
B6
A6
A5
E6
D8
A3
C8
D5
R8
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
VDDSOC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC_LCD
NVCC_LCD
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
VDD_SNVS_IN
NAND_CE0_B
NAND_CE1_B
NAND_CLE
NAND_CE0_B
NAND_CE1_B
NAND_CLE
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
NAND_RE_B
NAND_READY_B
NAND_WE_B
NAND_WP_B
ONOFF
NAND_RE_B
NAND_READY_B
NAND_WE_B
NAND_WP_B
ONOFF
100 k
pull-up
POR_B
P8
VDD_SNVS_IN
GPIO
ALT0
POR_B
Input
100 k
pull-up
RTC_XTALI
T11
U11
C1
C2
B3
B2
B1
A2
T9
VDD_SNVS_CAP ANALOG
VDD_SNVS_CAP ANALOG
—
RTC_XTALI
RTC_XTALO
SD1_CLK
—
—
—
RTC_XTALO
SD1_CLK
—
—
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
VDD_SNVS_IN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
Input
Input
Input
Input
Input
Input
Output
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
SD1_CMD
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SNVS_PMIC_ON_REQ
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SNVS_PMIC_ON_REQ
100 k
pull-up
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
111
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER3
SNVS_TAMPER4
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
R10
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
—
—
—
—
—
—
—
—
—
GPIO5_IO00/SNVS_TAM Input
PER0
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
Keeper1
R9
GPIO5_IO01/SNVS_TAM Input
PER1
P11
P10
P9
GPIO5_IO02/SNVS_TAM Input
PER2
GPIO5_IO03/SNVS_TAM Input
PER3
GPIO5_IO04/SNVS_TAM Input
PER4
N8
GPIO5_IO05/SNVS_TAM Input
PER5
N11
N10
N9
GPIO5_IO06/SNVS_TAM Input
PER6
GPIO5_IO07/SNVS_TAM Input
PER7
GPIO5_IO08/SNVS_TAM Input
PER8
R6
GPIO5_IO09/SNVS_TAM Input
PER9
TEST_MODE
N7
VDD_SNVS_IN
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
OPEN DRAIN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
—
TEST_MODE
UART1_CTS_B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
—
UART1_CTS_B
K15
J14
K16
K14
J15
H14
J16
J17
H15
G14
H16
H17
G16
G17
G13
F17
U16
UART1_RTS_B
UART1_RTS_B
UART1_RX_DATA
UART1_TX_DATA
UART2_CTS_B
UART1_RX_DATA
UART1_TX_DATA
UART2_CTS_B
UART2_RTS_B
UART2_RTS_B
UART2_RX_DATA
UART2_TX_DATA
UART3_CTS_B
UART2_RX_DATA
UART2_TX_DATA
UART3_CTS_B
UART3_RTS_B
UART3_RTS_B
UART3_RX_DATA
UART3_TX_DATA
UART4_RX_DATA
UART4_TX_DATA
UART5_RX_DATA
UART5_TX_DATA
USB_OTG1_CHD_B
UART3_RX_DATA
UART3_TX_DATA
UART4_RX_DATA
UART4_TX_DATA
UART5_RX_DATA
UART5_TX_DATA
USB_OTG1_CHD_B
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
112
NXP Semiconductors
Package information and contact assignments
Table 90. 14x14 mm Functional Contact Assignments (continued)
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_VBUS
T15
U15
T12
VDD_USB_CAP ANALOG
VDD_USB_CAP ANALOG
—
—
—
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_VBUS
—
—
—
—
—
—
USB_VBUS
VBUS
POWER
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
T13
U13
U12
VDD_USB_CAP ANALOG
VDD_USB_CAP ANALOG
—
—
—
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
—
—
—
—
—
—
USB_VBUS
VBUS
POWER
XTALI
T16
T17
NVCC_PLL
NVCC_PLL
ANALOG
ANALOG
—
—
XTALI
—
—
—
—
XTALO
XTALO
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0].
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
113
Package information and contact assignments
6.1.3
14x14 mm, 0.8 mm pitch, ball map
Table 91 shows the 14x14 mm, 0.8 mm pitch ball map for the i.MX 6UltraLite.
Table 91. 14x14 mm, 0.8 mm Pitch, Ball Map
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
114
NXP Semiconductors
Package information and contact assignments
Table 91. 14x14 mm, 0.8 mm Pitch, Ball Map (continued)
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
115
Package information and contact assignments
Table 91. 14x14 mm, 0.8 mm Pitch, Ball Map (continued)
6.2
GPIO reset behaviors during reset
Table 92 shows the GPIO behaviors during reset.
1
Table 92. GPIO Behaviors during Reset
Ball Name
Mux Mode
Function
Input/Output
Value
GPIO01_IO03
UART3_TX_DATA
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
ALT7
ALT7
ALT6
ALT6
ALT6
ALT6
ALT6
Reserved
Input
Output
Input
Input
Input
Input
Input
100 k pull-down
0
SJC_JTAG_ACT
SRC_BT_CFG[0]
SRC_BT_CFG[1]
SRC_BT_CFG[2]
SRC_BT_CFG[3]
SRC_BT_CFG[4]
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
116
NXP Semiconductors
Package information and contact assignments
1
Table 92. GPIO Behaviors during Reset (continued)
Ball Name
Mux Mode
Function
Input/Output
Value
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
ALT6
SRC_BT_CFG[5]
SRC_BT_CFG[6]
SRC_BT_CFG[7]
SRC_BT_CFG[8]
SRC_BT_CFG[9]
SRC_BT_CFG[10]
SRC_BT_CFG[11]
SRC_BT_CFG[12]
SRC_BT_CFG[13]
SRC_BT_CFG[14]
SRC_BT_CFG[15]
SRC_BT_CFG[16]
SRC_BT_CFG[17]
SRC_BT_CFG[18]
SRC_BT_CFG[19]
SRC_BT_CFG[20]
SRC_BT_CFG[21]
SRC_BT_CFG[22]
SRC_BT_CFG[23]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
100 k pull-down
1
Others are same as value in the column “Out of Reset Condition” of Table 90.
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
NXP Semiconductors
117
Revision history
7 Revision history
Table 93 provides a revision history for this data sheet.
Table 93. i.MX 6UltraLite Data Sheet Document Revision History
Substantive Change(s)
Rev.
Number
Date
0
01/2016 • Initial release
0.1
02/2016 • Updated Figure 1 Part Number Nomenclature—i.MX 6UltraLite
• Updated Table 1 Ordering Information
• Updated Table 3 i.MX 6UltraLite Modules List
1
04/2016 • Updated Table 3 i.MX 6UltraLite Module list for BCH descriptions
• Updated Table 4 Special Signal Considerations
• Added a note for Table 9 14x14 MM Package Thermal Resistance
• Updated Table 14 Low Power Mode Current and Power Consumption
• Added a note for Table 22 XTALI and RTC_XTALI DC Parameters
• Updated Table 37 EIM Internal Module Multiplexing
• Updated Table 50 SDR50/SDR104 Interface Timing Specification
• Updated Table 90 14x14 mm Functional Contact Assignments and footnote
• Updated Section 4.1.1, “Absolute maximum ratings"
• Updated Section 4.6.3, “DDR I/O DC parameters"
• Added Section 4.12.8, “LCD Controller (LCDIF) parameters"
• Updated Section 4.12.9, “QUAD SPI (QSPI) timing parameters"
2
02/2017 • Updated Table 8, "Absolute Maximum Ratings"
• Updated and added a footnote Table 10, "Operating Ranges"
• Updated Section 4.2.1, “Power-Up sequence" and Section 4.2.2, “Power-Down sequence"
• Removed Section 4.9.4 DDR SDRAM Specific Parameters (DDR3 and LPDDR2)
• Updated Figure 18, "Asynchronous A/D Muxed Write Access"
• Added a new Section 4.10, “Multi-Mode DDR Controller (MMDC)"
• Added a new Section 4.12.8.1, “LCDIF signal mapping"
• Updated Table 50, "SDR50/SDR104 Interface Timing Specification"
• Updated Figure 40, "HS200 Mode Timing"
• Updated Table 51, "HS200 Interface Timing Specification"
2.1
2.2
03/2017 • Updated the silicon revision definition in the Figure 1, "Part Number Nomenclature—i.MX 6UltraLite"
• Added Rev.1.2 part numbers in the Table 1, "Ordering Information"
05/2017 • Changed terminology from “floating” to “not connected”
• Added a footnote regarding maximum voltage allowance in the Table 8, "Absolute Maximum Ratings"
• Replaced the MMDC compatible information with a cross reference in the Section 4.6.3, “DDR I/O DC
parameters" and Section 4.7.2, “DDR I/O AC parameters"
• Changed SD3 min to 1.7 ns in the Table 50, "SDR50/SDR104 Interface Timing Specification"
i.MX 6UltraLite Automotive Applications Processors, Rev. 2.2, 05/2017
118
NXP Semiconductors
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright licenses
granted hereunder to design or fabricate any integrated circuits based on the
information in this document. NXP reserves the right to make changes without further
notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its
products for any particular purpose, nor does NXP assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation consequential or incidental damages. “Typical”
parameters that may be provided in NXP data sheets and/or specifications can and do
vary in different applications, and actual performance may vary over time. All operating
parameters, including “typicals” must be validated for each customer application by
customer‚ customer’s technical experts. NXP does not convey any license under its
patent rights nor the rights of others. NXP sells products pursuant to standard terms
and conditions of sale, which can be found at the following address:
nxp.com/SalesTermsandConditions.
NXP, the NXP logo, Freescale, the Freescale logo, and the Energy Efficient Solutions
logo are trademarks of NXP B.V. All other product or service names are the property
of their respective owners. ARM, the ARM Powered logo, and Cortex are trademarks
of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. The USB-IF Logo is a
registered trademark of USB Implementers Forum, Inc. All rights reserved.
© 2016-2017 NXP B.V.
Document Number: IMX6ULAEC
Rev. 2.2
05/2017
相关型号:
©2020 ICPDF网 联系我们和版权申明