MCIMX6Q7CVT12AE [NXP]

i.MX 6Dual/6Quad Applications Processors for Industrial Products;
MCIMX6Q7CVT12AE
型号: MCIMX6Q7CVT12AE
厂家: NXP    NXP
描述:

i.MX 6Dual/6Quad Applications Processors for Industrial Products

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中文:  中文翻译
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Document Number: IMX6DQIEC  
Rev. 6, 11/2018  
NXP Semiconductors  
Data Sheet: Technical Data  
MCIMX6QxCxxxxC  
MCIMX6QxCxxxxD  
MCIMX6QxCxxxxE  
MCIMX6DxCxxxxC  
MCIMX6DxCxxxxD  
MCIMX6DxCxxxxE  
i.MX 6Dual/6Quad  
ApplicationsProcessorsfor  
Industrial Products  
Package Information  
FCPBGA Package  
21 x 21 mm, 0.8 mm pitch  
Ordering Information  
See Table 1  
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2  
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7  
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 17  
3.2 Recommended Connections for Unused Analog  
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
1 Introduction  
The i.MX 6Dual/6Quad processors represent the latest  
achievement in integrated multimedia applications  
processors. These processors are part of a growing  
family of multimedia-focused products that offer high  
performance processing and are optimized for lowest  
2
3
power consumption.  
4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18  
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 18  
4.2 Power Supplies Requirements and Restrictions . . 31  
4.3 Integrated LDO Voltage Regulator Parameters . . 32  
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34  
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35  
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36  
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41  
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 45  
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48  
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 60  
4.11 General-Purpose Media Interface (GPMI) Timing. 60  
4.12 External Peripheral Interface Parameters . . . . . . . 69  
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 130  
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 130  
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 131  
Package Information and Contact Assignments. . . . . . 133  
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 133  
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 133  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156  
The i.MX 6Dual/6Quad processors feature advanced  
®
®
implementation of the quad Arm Cortex -A9 core,  
which operates at speeds up to 800 MHz. They include  
2D and 3D graphics processors, 1080p video processing,  
and integrated power management. Each processor  
provides a 64-bit DDR3/DDR3L/LPDDR2-800 memory  
interface and a number of other interfaces for connecting  
®
peripherals, such as WLAN, Bluetooth , GPS, hard  
drive, displays, and camera sensors.  
5
6
7
NXP Reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
Introduction  
The i.MX 6Dual/6Quad processors are specifically useful for applications such as the following:  
The i.MX 6Dual/6Quad processors offers numerous advanced features, such as:  
Multilevel memory system—The multilevel memory system of each processor is based on the L1  
instruction and data caches, L2 cache, and internal and external memory. The processors support  
many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,  
PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,  
including eMMC up to rev 4.4/4.41.  
Smart speed technology—The processors have power management throughout the device that  
enables the rich suite of multimedia features and peripherals to consume minimum power in both  
active and various low power modes. Smart speed technology enables the designer to deliver a  
feature-rich product, requiring levels of power far lower than industry expectations.  
Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices  
by scaling the voltage and frequency to optimize performance.  
Multimedia powerhouse—The multimedia performance of each processor is enhanced by a  
®
multilevel cache system, Neon MPE (Media Processor Engine) co-processor, a multi-standard  
hardware video codec, 2 autonomous and independent image processing units (IPU), and a  
programmable smart DMA (SDMA) controller.  
Powerful graphics acceleration—Each processor provides three independent, integrated graphics  
processing units: an OpenGL ES 2.0 3D graphics accelerator with four shaders (up to 200 MTri/s  
and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.  
®
Interface flexibility—Each processor supports connections to a variety of interfaces: LCD  
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS  
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with  
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host  
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces  
2
2
(such as UART, I C, and I S serial audio, SATA-II, and PCIe-II).  
Advanced security—The processors deliver hardware-enabled security features that enable secure  
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure  
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad  
security reference manual (IMX6DQ6SDLSRM).  
Integrated power management—The processors integrate linear regulators and internally generate  
voltage levels for different domains. This significantly simplifies system power management  
structure.  
1.1  
Ordering Information  
Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include  
all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your  
desired part number is not listed in the table, or you have questions about available parts, see  
nxp.com/imx6series or contact your NXP representative.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
2
NXP Semiconductors  
Introduction  
Table 1. Example Orderable Part Numbers  
Speed1  
Grade  
Temperature  
Part Number  
Quad/Dual CPU  
Options  
Package  
Grade  
MCIMX6Q7CVT08AC  
i.MX 6Quad  
Includes VPU, GPU  
800 MHz  
800 MHz  
800 MHz  
800 MHz  
800 MHz  
800 MHz  
Industrial  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
MCIMX6Q7CVT08AD  
MCIMX6Q7CVT08AE  
MCIMX6D7CVT08AC  
MCIMX6D7CVT08AD  
MCIMX6D7CVT08AE  
i.MX 6Quad  
i.MX 6Quad  
i.MX 6Dual  
i.MX 6Dual  
i.MX 6Dual  
Includes VPU, GPU  
Includes VPU, GPU  
Includes VPU, GPU  
Includes VPU, GPU  
Includes VPU, GPU  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
21 mm x 21 mm, 0.8 mm  
pitch, FCPBGA (lidded)  
1
If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.  
Figure 1 describes the part number nomenclature to identify the characteristics of the specific part number  
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision). Figure 1  
applies to the i.MX 6Dual/6Quad.  
The two characteristics that identify which data sheet a specific part applies to are the part number series  
field and the temperature grade (junction) field:  
The i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors data sheet  
(IMX6DQAEC) covers parts listed with “A (Automotive temp)”  
The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet (IMX6DQCEC)  
covers parts listed with “D (Commercial temp)” or “E (Extended Commercial temp)”  
The i.MX 6Dual/6Quad Applications Processors for Industrial Products data sheet (IMX6DQIEC)  
covers parts listed with “C (Industrial temp)”  
The Ensure that you have the right data sheet for your specific part by checking the temperature grade  
(junction) field and matching it to the right data sheet. If you have questions, see nxp.com/imx6series or  
contact your NXP representative.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
3
Introduction  
MC  
IMX6 X @  
+
VV  
$$ % A  
Qualification level  
MC  
Silicon revision1  
Rev 1.2  
A
C
D
E
Prototype Samples  
Mass Production  
Special  
PC  
MC  
SC  
Rev 1.3  
Rev 1.6  
Part # series  
i.MX 6Quad  
i.MX 6Dual  
X
Q
D
Fusing  
%
A
Default setting  
HDCP enabled  
C
Part differentiator  
@
7
Frequency  
$$  
Industrial with VPU, GPU, no MLB  
Automotive with VPU, GPU  
Consumer with VPU, GPU  
800 MHz2 (Industrial grade)  
852 MHz (Automotive grade)  
1 GHz3  
08  
08  
10  
12  
6
5
Automotive with GPU, no VPU  
4
1.2 GHz  
Temperature Tj  
RoHS  
Package type  
+
E
C
A
Extended commercial: -20 to +105°C  
Industrial: -40 to +105°C  
FCPBGA 21x21 0.8mm (lidded)  
VT  
FCPBGA 21x21 0.8mm (non lidded)  
YM  
Automotive: -40 to +125°C  
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.  
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.  
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.  
Figure 1. Part Number Nomenclature—i.MX 6Quad and i.MX 6Dual  
1.2  
Features  
The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the  
following features:  
®
Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone )  
The core configuration is symmetric, where each core includes:  
— 32 KByte L1 Instruction Cache  
— 32 KByte L1 Data Cache  
— Private Timer and Watchdog  
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor  
The Arm Cortex-A9 MPCore complex includes:  
General Interrupt Controller (GIC) with 128 interrupt support  
Global Timer  
Snoop Control Unit (SCU)  
1 MB unified I/D L2 cache, shared by two/four cores  
Two Master AXI (64-bit) bus interfaces output of L2 cache  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
4
NXP Semiconductors  
Introduction  
Frequency of the core (including Neon and L1 cache) as per Table 6.  
NEON MPE coprocessor  
— SIMD Media Processing Architecture  
— NEON register file with 32x64-bit general-purpose registers  
— NEON Integer execute pipeline (ALU, Shift, MAC)  
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)  
— NEON load/store and permute pipeline  
The SoC-level memory system consists of the following additional components:  
Boot ROM, including HAB (96 KB)  
Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)  
Secure/non-secure RAM (16 KB)  
External memory interfaces:  
— 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels,  
supporting DDR interleaving mode, for dual x32 LPDDR2  
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,  
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.  
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.  
— 16/32-bit PSRAM, Cellular RAM  
Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are  
muxed and not available simultaneously):  
Hard Disk Drives—SATA II, 3.0 Gbps  
Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450  
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.  
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual  
HD1080 and WXGA at 60 Hz)  
— LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two  
ports up to 85 MP/sec each  
— HDMI 1.4 port  
— MIPI/DSI, two lanes at 1 Gbps  
Camera sensors:  
— Parallel Camera port (up to 20 bit and up to 240 MHz peak)  
— MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to  
800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to  
four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.  
Expansion cards:  
— Four MMC/SD/SDIO card ports all supporting:  
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104  
mode (104 MB/s max)  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
5
Introduction  
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR  
and DDR modes (104 MB/s max)  
USB:  
— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY  
— Three USB 2.0 (480 Mbps) hosts:  
– One HS host with integrated High Speed PHY  
– Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY  
Expansion PCI Express port (PCIe) v2.0 one lane  
— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint  
operations. Uses x1 PHY configuration.  
Miscellaneous IPs and interfaces:  
— SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and  
2
outputs with I S mode  
— ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with  
7.1 multi channel outputs  
— Five UARTs, up to 5.0 Mbps each:  
– Providing RS232 interface  
– Supporting 9-bit RS485 multidrop mode  
– One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This  
is due to the SoC IOMUX limitation, because all UART IPs are identical.  
— Five eCSPI (Enhanced CSPI)  
— Three I2C, supporting 400 kbps  
1
— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/1000 Mbps  
— Four Pulse Width Modulators (PWM)  
— System JTAG Controller (SJC)  
— GPIO with interrupt capabilities  
— 8x8 Key Pad Port (KPP)  
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx  
— Two Controller Area Network (FlexCAN), 1 Mbps each  
— Two Watchdog timers (WDOG)  
— Audio MUX (AUDMUX)  
The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:  
Provide PMU, including LDO supplies, for on-chip resources  
Use Temperature Sensor for monitoring the die temperature  
Support DVFS techniques for low power modes  
Use Software State Retention and Power Gating for Arm and MPE  
1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus  
throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the  
ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
6
NXP Semiconductors  
Introduction  
Support various levels of system power modes  
Use flexible clock gating control scheme  
The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia  
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power  
consumption numbers, while having the CPU core relatively free for performing other tasks.  
The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:  
VPU—Video Processing Unit  
IPUv3H—Image Processing Unit version 3H (2 IPUs)  
GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4  
GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2  
GPUVG—OpenVG 1.1 Graphics Processing Unit  
ASRC—Asynchronous Sample Rate Converter  
Security functions are enabled and accelerated by the following hardware:  
Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)  
SJC—SystemJTAGController. ProtectingJTAGfromdebugportattacks by regulating or blocking  
the access to the system debug features.  
CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and  
True and Pseudo Random Number Generator (NIST certified)  
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock  
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be  
configured during boot and by eFUSEs and will determine the security level operation mode as  
well as the TZ policy.  
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:  
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.  
1.3  
Signal Naming Convention  
Throughout this document, the updated signal names are used except where referenced as a ball name  
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal  
name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be  
used to map the signal names used in older documentation to the new standardized naming conventions.  
The signal names of the i.MX6 series of products are standardized to align the signal names within the  
family and across the documentation. Benefits of this standardization are as follows:  
Signal names are unique within the scope of an SoC and within the series of products  
Searches will return all occurrences of the named signal  
Signal names are consistent between i.MX 6 series products implementing the same modules  
The module instance is incorporated into the signal name  
This standardization applies only to signal names. The ball names are preserved to prevent the need to  
change schematics, BSDL models, IBIS models, and so on.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
7
Architectural Overview  
2 Architectural Overview  
The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system.  
2.1  
Block Diagram  
Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system.  
MIPI  
Raw/ONFI 2.2 LPDDR2 (400MHz) NOR Flash Battery Ctrl 4x Camera 1 / 2 LVDS 1 / 2 LCD HDMI 1.4  
Display  
Nand-Flash  
DDR3 (532MHz)  
PSRAM  
Device  
Parallel/MIPI (WUXGA+) Displays  
Display  
Application Processor  
Domain (AP)  
CSI2/MIPI LDB  
HDMI  
DSI/MIPI  
External  
Memory  
Interface  
Digital  
Audio  
GPMI  
MMDC  
EIM  
Internal  
RAM  
(272KB)  
Clock and Reset  
PLL (8)  
Crystals  
& Clock sources  
Image Processing  
Subsystem  
2x IPUv3H  
CCM  
Boot  
ROM  
GPC  
SRC  
(96KB)  
SATA II  
3.0Gbps  
ARM Cortex A9  
MPCore Platform  
Smart DMA  
(SDMA)  
XTALOSC  
OSC32K  
Debug  
DAP  
4x  
A9-Core  
L1 I/D Cache  
Timer, Wdog  
TPIU  
CTIs  
SJC  
SPBA  
MMC/SD  
eMMC/eSD  
2xCAN  
Interface  
AP Peripherals  
1MB L2 cache  
SCU, Timer  
PTM’s CTI’s  
uSDHC (4)  
MMC/SD  
SDXC  
Shared Peripherals  
AUDMUX  
2
Security  
I C(3)  
Video  
eCSPI (5)  
ESAI  
SSI (3)  
CAAM  
(16KB Ram)  
Proc. Unit  
PWM (4)  
OCOTP  
IOMUXC  
KPP  
5xFast-UART  
SPDIF Rx/Tx  
Modem IC  
PCIe Bus  
GPS  
(VPU + Cache)  
SNVS  
(SRTC)  
ASRC  
3D Graphics  
Proc. Unit  
(GPU3D)  
CSU  
Fuse Box  
2D Graphics  
Proc. Unit  
(GPU2D)  
Keypad  
GPIO  
CAN(2)  
Industrial  
Standard  
Block Diagram  
Timers/Control  
WDOG (2)  
GPT  
OpenVG 1.1  
Proc. Unit  
(GPUVG)  
1-Gbps ENET  
HSI/MIPI  
Ethernet  
10/100/1000  
Mbps  
EPIT (2)  
Audio,  
Power  
USB OTG +  
3 HS Ports  
Temp Monitor  
Mngmnt  
.
OTG PHY1  
Host PHY2  
2xHSIC  
PHY  
USB OTG  
(dev/host)  
JTAG  
(IEEE1149.6)  
Bluetooth  
WLAN  
Figure 2. i.MX 6Dual/6Quad Industrial Grade System Block Diagram  
NOTE  
The numbers in brackets indicate number of module instances. For example,  
PWM (4) indicates four separate PWM peripherals.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
8
NXP Semiconductors  
Modules List  
3 Modules List  
The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these  
modules in alphabetical order.  
Table 2. i.MX 6Dual/6Quad Modules List  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
512 x 8 Fuse Electrical Fuse Array Security  
Box  
Electrical Fuse Array. Enables to setup Boot Modes, Security Levels,  
Security Keys, and many other system parameters.  
The i.MX 6Dual/6Quad processors consist of 512x8-bit fuse box  
accessible through OCOTP_CTRL interface.  
APBH-DMA NAND Flash and  
BCH ECC DMA  
System  
Control  
DMA controller used for GPMI2 operation.  
Controller  
Peripherals  
Arm  
Arm Platform  
Arm  
The Arm Cortex-A9 platform consists of 4x (four) Cortex-A9 cores version  
r2p10 and associated sub-blocks, including Level 2 Cache Controller,  
SCU (Snoop Control Unit), GIC (General Interrupt Controller), private  
timers, Watchdog, and CoreSight debug modules.  
ASRC  
Asynchronous  
Sample Rate  
Converter  
Multimedia  
Peripherals  
The Asynchronous Sample Rate Converter (ASRC) converts the  
sampling rate of a signal associated to an input clock into a signal  
associated to a different output clock. The ASRC supports concurrent  
sample rate conversion of up to 10 channels of about -120dB THD+N. The  
sample rate conversion of each channel is associated to a pair of  
incoming and outgoing sampling rates. The ASRC supports up to three  
sampling rate pairs.  
AUDMUX  
Digital Audio Mux  
Multimedia  
Peripherals  
The AUDMUX is a programmable interconnect for voice, audio, and  
synchronous data routing between host serial interfaces (for example,  
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice  
codecs). The AUDMUX has seven ports with identical functionality and  
programming models. A desired connectivity is achieved by configuring  
two or more AUDMUX ports.  
BCH40  
CAAM  
Binary-BCH ECC  
Processor  
System  
Control  
Peripherals  
The BCH40 module provides up to 40-bit ECC error correction for NAND  
Flash controller (GPMI).  
Cryptographic  
Accelerator and  
Assurance Module  
Security  
CAAM is a cryptographic accelerator and assurance module. CAAM  
implements several encryption and hashing functions, a run-time integrity  
checker, and a Pseudo Random Number Generator (PRNG). The pseudo  
random number generator is certified by Cryptographic Algorithm  
Validation Program (CAVP) of National Institute of Standards and  
Technology (NIST). Its DRBG validation number is 94 and its SHS  
validation number is 1455.  
CAAM also implements a Secure Memory mechanism. In i.MX  
6Dual/6Quad processors, the security memory provided is 16 KB.  
CCM  
GPC  
SRC  
Clock Control  
Module, General  
Power Controller,  
System Reset  
Controller  
Clocks,  
These modules are responsible for clock and reset distribution in the  
Resets, and system, and also for the system power management.  
Power Control  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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9
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
CSI  
MIPI CSI-2 Interface Multimedia  
Peripherals  
The CSI IP provides MIPI CSI-2 standard camera interface port. The  
CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800  
Mbps for 4 data lanes.  
CSU  
Central Security Unit Security  
The Central Security Unit (CSU) is responsible for setting comprehensive  
security policy within the i.MX 6Dual/6Quad platform. The Security  
Control Registers (SCR) of the CSU are set during boot time by the HAB  
and are locked to prevent further writing.  
CTI-0  
CTI-1  
CTI-2  
CTI-3  
CTI-4  
Cross Trigger  
Interfaces  
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from  
masters attached to CTIs. The CTI module is internal to the Cortex-A9  
Core Platform.  
CTM  
Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.  
The CTM module is internal to the Cortex-A9 Core Platform.  
DAP  
Debug Access Port System  
Control  
The DAP provides real-time access for the debugger without halting the  
core to:  
Peripherals  
• System memory and peripheral registers  
• All debug configuration registers  
The DAP also provides debugger access to JTAG scan chains. The DAP  
module is internal to the Cortex-A9 Core Platform.  
DCIC-0  
DCIC-1  
Display Content  
Integrity Checker  
Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX  
6Dual/6Quad processor has two such modules, one for each IPU.  
DSI  
MIPI DSI interface  
Multimedia  
Peripherals  
The MIPI DSI IP provides DSI standard display port interface. The DSI  
interface support 80 Mbps to 1 Gbps speed per data lane.  
eCSPI1-5  
Configurable SPI  
Connectivity Full-duplex enhanced Synchronous Serial Interface. It is configurable to  
Peripherals  
support Master/Slave modes, four chip selects to support multiple  
peripherals.  
ENET  
Ethernet Controller Connectivity The Ethernet Media Access Controller (MAC) is designed to support  
Peripherals  
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external  
transceiver interface and transceiver function are required to complete the  
interface to the media. The i.MX 6Dual/6Quad processors also consist of  
hardware assist for IEEE 1588 standard. For details, see the ENET  
chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
Note: The theoretical maximum performance of 1 Gbps ENET is limited  
to 470 Mbps (total for Tx and Rx) due to internal bus throughput  
limitations. The actual measured performance in optimized environment  
is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX  
6Dual/6Quad errata document (IMX6DQCE).  
EPIT-1  
EPIT-2  
Enhanced Periodic Timer  
Interrupt Timer Peripherals  
Each EPIT is a 32-bit “set and forget” timer that starts counting after the  
EPIT is enabled by software. It is capable of providing precise interrupts  
at regular intervals with minimal processor intervention. It has a 12-bit  
prescaler for division of input clock frequency to get the required time  
setting for the interrupts to occur, and counter value can be programmed  
on the fly.  
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10  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block Name Subsystem Brief Description  
Connectivity The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial  
Block  
Mnemonic  
ESAI  
Enhanced Serial  
Audio Interface  
Peripherals  
port for serial communication with a variety of serial devices, including  
industry-standard codecs, SPDIF transceivers, and other processors.  
The ESAI consists of independent transmitter and receiver sections, each  
section with its own clock generator. All serial transfers are synchronized  
to a clock. Additional synchronization signals are used to delineate the  
word frames. The normal mode of operation is used to transfer data at a  
periodic rate, one word per period. The network mode is also intended for  
periodic transfers; however, it supports up to 32 words (time slots) per  
period. This mode can be used to build time division multiplexed (TDM)  
networks. In contrast, the on-demand mode is intended for non-periodic  
transfers of data and to transfer data serially at high speed when the data  
becomes available.  
The ESAI has 12 pins for data and clocking connection to external  
devices.  
FlexCAN-1 Flexible Controller  
FlexCAN-2 Area Network  
Connectivity The CAN protocol was primarily, but not only, designed to be used as a  
Peripherals  
vehicle serial data bus, meeting the specific requirements of this field:  
real-time processing, reliable operation in the Electromagnetic  
interference (EMI) environment of a vehicle, cost-effectiveness and  
required bandwidth. The FlexCAN module is a full implementation of the  
CAN protocol specification, Version 2.0 B, which supports both standard  
and extended message frames.  
GPIO-1  
GPIO-2  
GPIO-3  
GPIO-4  
GPIO-5  
GPIO-6  
GPIO-7  
General Purpose I/O System  
Used for general purpose input/output to external devices. Each GPIO  
module supports 32 bits of I/O.  
Modules  
Control  
Peripherals  
GPMI  
General Purpose  
Media Interface  
Connectivity The GPMI module supports up to 8x NAND devices. 40-bit ECC error  
Peripherals  
correction for NAND Flash controller (GPMI2). The GPMI supports  
separate DMA channels per NAND device.  
GPT  
General Purpose  
Timer  
Timer  
Peripherals  
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with  
programmable prescaler and compare and capture register. A timer  
counter value can be captured using an external event and can be  
configured to trigger a capture event on either the leading or trailing edges  
of an input pulse. When the timer is configured to operate in “set and  
forget” mode, it is capable of providing precise interrupts at regular  
intervals with minimal processor intervention. The counter has output  
compare logic to provide the status and interrupt at comparison. This  
timer can be configured to run either on an external clock or on an internal  
clock.  
GPU2Dv2  
GPU3Dv4  
Graphics Processing Multimedia  
Unit-2D, ver. 2 Peripherals  
The GPU2Dv2 provides hardware acceleration for 2D graphics  
algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.  
Graphics Processing Multimedia  
Unit-3D, ver. 4 Peripherals  
The GPU2Dv4 provides hardware acceleration for 3D graphics algorithms  
with sufficient processor power to run desktop quality interactive graphics  
applications on displays up to HD1080 resolution. The GPU3D provides  
OpenGL ES 2.0, including extensions, OpenGL ES 1.1, and OpenVG 1.1  
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11  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
GPUVGv2  
Vector Graphics  
Processing Unit,  
ver. 2  
Multimedia  
Peripherals  
OpenVG graphics accelerator provides OpenVG 1.1 support as well as  
other accelerations, including Real-time hardware curve tesselation of  
lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and  
various Vector Drawing functions.  
HDMI Tx  
HSI  
HDMI Tx interface  
MIPI HSI interface  
I2C Interface  
Multimedia  
Peripherals  
The HDMI module provides HDMI standard interface port to an HDMI 1.4  
compliant display.  
Connectivity The MIPI HSI provides a standard MIPI interface to the applications  
Peripherals processor.  
I2C-1  
I2C-2  
I2C-3  
Connectivity I2C provide serial interface for external devices. Data rates of up to 400  
Peripherals  
kbps are supported.  
IOMUXC  
IOMUX Control  
System  
Control  
Peripherals  
This module enables flexible IO multiplexing. Each IO pad has default and  
several alternate functions. The alternate functions are software  
configurable.  
IPUv3H-1  
IPUv3H-2  
Image Processing  
Unit, ver. 3H  
Multimedia  
Peripherals  
IPUv3H enables connectivity to displays and video sources, relevant  
processing and synchronization and control capabilities, allowing  
autonomous operation.  
The IPUv3H supports concurrent output to two display ports and  
concurrent input from two camera ports, through the following interfaces:  
• Parallel Interfaces for both display and camera  
• Single/dual channel LVDS display interface  
• HDMI transmitter  
• MIPI/DSI transmitter  
• MIPI/CSI-2 receiver  
The processing includes:  
• Image conversions: resizing, rotation, inversion, and color space  
conversion  
• A high-quality de-interlacing filter  
• Video/graphics combining  
• Image enhancement: color adjustment and gamut mapping, gamma  
correction, and contrast enhancement  
• Support for display backlight reduction  
KPP  
LDB  
Key Pad Port  
Connectivity KPP Supports 8 x 8 external key pad matrix. KPP features are:  
Peripherals  
• Open drain design  
• Glitch suppression circuit design  
• Multiple keys detection  
• Standby key press detection  
LVDS Display Bridge Connectivity LVDS Display Bridge is used to connect the IPU (Image Processing Unit)  
Peripherals  
to External LVDS Display Interface. LDB supports two channels; each  
channel has following signals:  
• One clock pair  
• Four data pairs  
Each signal pair contains LVDS special differential pad (PadP, PadM).  
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12  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
MMDC  
Multi-Mode DDR  
Controller  
Connectivity DDR Controller has the following features:  
Peripherals  
• Supports 16/32/64-bit DDR3 / DDR3L or LPDDR2  
• Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2  
configurations (including 2x32 interleaved mode)  
• Supports up to 4 GByte DDR memory space  
OCOTP_CTRL OTP Controller  
Security  
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for  
reading, programming, and/or overriding identification and control  
information stored in on-chip fuse elements. The module supports  
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also  
provides a set of volatile software-accessible signals that can be used for  
software control of hardware elements, not requiring non-volatility. The  
OCOTP_CTRL provides the primary user-visible mechanism for  
interfacing with on-chip fuse elements. Among the uses for the fuses are  
unique chip identifiers, mask revision numbers, cryptographic keys, JTAG  
secure mode, boot characteristics, and various control signals, requiring  
permanent non-volatility.  
OCRAM  
On-Chip Memory  
Controller  
Data Path  
Clocking  
The On-Chip Memory controller (OCRAM) module is designed as an  
interface between system’s AXI bus and internal (on-chip) SRAM memory  
module.  
In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the  
256 KB multimedia RAM through a 64-bit AXI bus.  
OSC 32 kHz OSC 32 kHz  
Generates 32.768 kHz clock from an external crystal.  
PCIe  
PCI Express 2.0  
Connectivity The PCIe IP provides PCI Express Gen 2.0 functionality.  
Peripherals  
PMU  
Power-Management Data Path  
Functions  
Integrated power management unit. Used to provide power to various  
SoC domains.  
PWM-1  
PWM-2  
PWM-3  
PWM-4  
Pulse Width  
Modulation  
Connectivity The pulse-width modulator (PWM) has a 16-bit counter and is optimized  
Peripherals  
to generate sound from stored sample audio images and it can also  
generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate  
sound.  
RAM  
Secure/non-secure Secured  
Secure/non-secure Internal RAM, interfaced through the CAAM.  
16 KB  
RAM  
Internal  
Memory  
RAM  
256 KB  
Internal RAM  
Boot ROM  
Internal  
Memory  
Internal RAM, which is accessed through OCRAM memory controllers.  
ROM  
96 KB  
Internal  
Memory  
Supports secure and regular Boot Modes. Includes read protection on 4K  
region for content protection  
ROMCP  
ROM Controller with Data Path  
Patch  
ROM Controller with ROM Patch support  
SATA  
Serial ATA  
Connectivity The SATA controller and PHY is a complete mixed-signal IP solution  
Peripherals designed to implement SATA II, 3.0 Gbps HDD connectivity.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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13  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block Name Subsystem Brief Description  
Smart Direct Memory System  
Block  
Mnemonic  
SDMA  
The SDMA is multi-channel flexible DMA engine. It helps in maximizing  
system performance by off-loading the various cores in dynamic data  
routing. It has the following features:  
Access  
Control  
Peripherals  
• Powered by a 16-bit Instruction-Set micro-RISC engine  
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA  
channels  
• 48 events with total flexibility to trigger any combination of channels  
• Memory accesses including linear, FIFO, and 2D addressing  
• Shared peripherals between Arm and SDMA  
• Very fast context-switching with 2-level priority based preemptive  
multi-tasking  
• DMA units with auto-flush and prefetch capability  
• Flexible address management for DMA transfers (increment,  
decrement, and no address changes on source and destination  
address)  
• DMA ports can handle unit-directional and bi-directional flows (copy  
mode)  
• Up to 8-word buffer for configurable burst transfers  
• Support of byte-swapping and CRC calculations  
• Library of Scripts and API is available  
SJC  
System JTAG  
Controller  
System  
Control  
Peripherals  
The SJC provides JTAG interface, which complies with JTAG TAP  
standards, to internal logic. The i.MX 6Dual/6Quad processors use JTAG  
port for production, testing, and system debugging. In addition, the SJC  
provides BSR (Boundary Scan Register) standard support, which  
complies with IEEE1149.1 and IEEE1149.6 standards.  
The JTAG port must be accessible during platform initial laboratory  
bring-up, for manufacturing tests and troubleshooting, as well as for  
software debugging by authorized entities. The i.MX 6Dual/6Quad SJC  
incorporates three security modes for protecting against unauthorized  
accesses. Modes are selected through eFUSE configuration.  
SNVS  
SPDIF  
Secure Non-Volatile Security  
Storage  
Secure Non-Volatile Storage, including Secure Real Time Clock, Security  
State Machine, Master Key Control, and Violation/Tamper Detection and  
reporting.  
Sony Philips Digital Multimedia  
Interconnect Format Peripherals  
A standard audio file transfer format, developed jointly by the Sony and  
Phillips corporations. It supports Transmitter and Receiver functionality.  
SSI-1  
SSI-2  
SSI-3  
I2S/SSI/AC97  
Interface  
Connectivity The SSI is a full-duplex synchronous interface, which is used on the  
Peripherals  
processor to provide connectivity with off-chip audio peripherals. The SSI  
supports a wide variety of protocols (SSI normal, SSI network, I2S, and  
AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.  
The SSI has two pairs of 8x24 FIFOs and hardware support for an  
external DMA controller to minimize its impact on system performance.  
The second pair of FIFOs provides hardware interleaving of a second  
audio stream that reduces CPU overhead in use cases where two time  
slots are being used simultaneously.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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14  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block Name Subsystem Brief Description  
Block  
Mnemonic  
TEMPMON Temperature Monitor System  
Control  
The temperature monitor/sensor IP module for detecting high temperature  
conditions. The temperature read out does not reflect case or ambient  
temperature. It reflects the temperature in proximity of the sensor location  
on the die. Temperature distribution may not be uniformly distributed;  
therefore, the read out value may not be the reflection of the temperature  
value for the entire die.  
Peripherals  
TZASC  
Trust-Zone Address Security  
Space Controller  
The TZASC (TZC-380 by Arm) provides security address region control  
functions required for intended application. It is used on the path to the  
DRAM controller.  
UART-1  
UART-2  
UART-3  
UART-4  
UART-5  
UART Interface  
Connectivity Each of the UARTv2 modules support the following serial data  
Peripherals  
transmit/receive protocols and configurations:  
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd  
or none)  
• Programmable baud rates up to 5 MHz  
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud  
• IrDA 1.0 support (up to SIR speed of 115200 bps)  
• Option to operate as 8-pins full UART, DCE, or DTE  
USBOH3A USB 2.0 High Speed Connectivity USBOH3 contains:  
OTG and 3x HS  
Hosts  
Peripherals  
• One high-speed OTG module with integrated HS USB PHY  
• One high-speed Host module with integrated HS USB PHY  
• Two identical high-speed Host modules connected to HSIC USB ports.  
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15  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
uSDHC-1  
uSDHC-2  
uSDHC-2  
uSDHC-4  
SD/MMC and SDXC Connectivity i.MX 6Dual/6Quad specific SoC characteristics:  
Enhanced  
Peripherals  
All four MMC/SD/SDIO controller IPs are identical and are based on the  
uSDHC IP. They are:  
Multi-Media Card /  
Secure Digital Host  
Controller  
• Conforms to the SD Host Controller Standard Specification version 3.0  
• Fully compliant with MMC command/response sets and Physical Layer  
as defined in the Multimedia Card System Specification,  
v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.  
Hardware reset as specified for eMMC cards is supported at ports #3  
and #4 only.  
• Fully compliant with SD command/response sets and Physical Layer  
as defined in the SD Memory Card Specifications, v3.0 including  
high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.  
• Fully compliant with SDIO command/response sets and  
interrupt/read-wait mode as defined in the SDIO Card Specification,  
Part E1, v1.10  
• Fully compliant with SD Card Specification, Part A2, SD Host  
Controller Standard Specification, v2.00  
All four ports support:  
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to  
UHS-I SDR104 mode (104 MB/s max)  
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52  
MHz in both SDR and DDR modes (104 MB/s max)  
However, the SoC-level integration and I/O muxing logic restrict the  
functionality to the following:  
• Instances #1 and #2 are primarily intended to serve as external slots or  
interfaces to on-board SDIO devices. These ports are equipped with  
“Card Detection” and “Write Protection” pads and do not support  
hardware reset.  
• Instances #3 and #4 are primarily intended to serve interfaces to  
embedded MMC memory or interfaces to on-board SDIO devices.  
These ports do not have “Card detection” and “Write Protection” pads  
and do support hardware reset.  
• All ports can work with 1.8 V and 3.3 V cards. There are two completely  
independent I/O power domains for Ports #1 and #2 in four bit  
configuration (SD interface). Port #3 is placed in his own independent  
power domain and port #4 shares power domain with some other  
interfaces.  
VDOA  
VPU  
VDOA  
Multimedia  
Peripherals  
The Video Data Order Adapter (VDOA) is used to re-order video data from  
the “tiled” order used by the VPU to the conventional raster-scan order  
needed by the IPU.  
Video Processing  
Unit  
Multimedia  
Peripherals  
A high-performing video processing unit (VPU), which covers many  
SD-level and HD-level video decoders and SD-level encoders as a  
multi-standard video codec engine as well as several important video  
processing, such as rotation and mirroring.  
See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete  
list of VPU’s decoding/encoding capabilities.  
WDOG-1  
Watchdog  
Timer  
Peripherals  
The Watchdog Timer supports two comparison points during each  
counting period. Each of the comparison points is configurable to evoke  
an interrupt to the Arm core, and a second point evokes an external event  
on the WDOG line.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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16  
Modules List  
Table 2. i.MX 6Dual/6Quad Modules List (continued)  
Block  
Mnemonic  
Block Name  
Subsystem  
Brief Description  
The TrustZone Watchdog (TZ WDOG) timer module protects against  
WDOG-2  
(TZ)  
Watchdog  
(TrustZone)  
Timer  
Peripherals  
TrustZone starvation by providing a method of escaping normal mode and  
forcing a switch to the TZ mode. TZ starvation is a situation where the  
normal OS prevents switching to the TZ mode. Such a situation is  
undesirable as it can compromise the system’s security. Once the TZ  
WDOG module is activated, it must be serviced by TZ software on a  
periodic basis. If servicing does not take place, the timer times out. Upon  
a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces  
switching to the TZ mode. If it is still not served, the TZ WDOG asserts a  
security violation signal to the CSU. The TZ WDOG module cannot be  
programmed or deactivated by a normal mode Software.  
EIM  
NOR-Flash /PSRAM Connectivity The EIM NOR-FLASH / PSRAM provides:  
interface  
Peripherals  
• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and  
async operating modes), at slow frequency  
• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow  
frequency  
• Multiple chip selects  
XTALOSC  
Crystal Oscillator  
interface  
The XTALOSC module enables connectivity to external crystal oscillator  
device. In a typical application use-case, it is used for 24 MHz oscillator.  
3.1  
Special Signal Considerations  
The package contact assignments can be found in Section 6, “Package Information and Contact  
Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
Special signal consideration information is contained in the Hardware Development Guide for i.MX  
6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).  
3.2  
Recommended Connections for Unused Analog Interfaces  
The recommended connections for unused analog interfaces can be found in the section, “Unused analog  
interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of  
Applications Processors (IMX6DQ6SDLHDG).  
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17  
Electrical Characteristics  
4 Electrical Characteristics  
This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad  
processors.  
4.1  
Chip-Level Conditions  
This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick  
reference to the individual tables and sections.  
Table 3. i.MX 6Dual/6Quad Chip-Level Conditions  
For these characteristics, …  
Absolute Maximum Ratings  
Topic appears …  
on page 19  
on page 20  
on page 21  
on page 23  
on page 25  
on page 26  
on page 28  
on page 28  
on page 29  
on page 30  
FCPBGA Package Thermal Resistance  
Operating Ranges  
External Clock Sources  
Maximum Measured Supply Currents  
Low Power Mode Supply Currents  
USB PHY Current Consumption  
SATA Typical Power Consumption  
PCIe 2.0 Maximum Power Consumption  
HDMI Maximum Power Consumption  
4.1.1  
Absolute Maximum Ratings  
CAUTION  
Stresses beyond those listed under Table 4 may affect reliability or cause  
permanent damage to the device. These are stress ratings only. Functional  
operation of the device at these or any other conditions beyond those  
indicated in the Operating Ranges or Parameters tables is not implied.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
18  
NXP Semiconductors  
Electrical Characteristics  
Table 4. Absolute Maximum Ratings  
Symbol  
Parameter Description  
Min  
Max  
Unit  
Core supply input voltage (LDO enabled)  
VDD_ARM_IN  
VDD_ARM23_IN  
VDD_SOC_IN  
-0.3  
1.6  
V
Core supply input voltage (LDO bypass)  
Core supply output voltage (LDO enabled)  
VDD_ARM_IN  
VDD_ARM23_IN  
VDD_SOC_IN  
-0.3  
-0.3  
1.4  
1.4  
V
V
VDD_ARM_CAP  
VDD_SOC_CAP  
VDD_PU_CAP  
NVCC_PLL_OUT  
VDD_HIGH_IN supply voltage  
DDR I/O supply voltage  
VDD_HIGH_IN  
NVCC_DRAM  
-0.3  
-0.4  
3.7  
V
V
1.975 (See note 1)  
GPIO I/O supply voltage  
NVCC_CSI  
NVCC_EIM  
NVCC_ENET  
NVCC_GPIO  
NVCC_LCD  
NVCC_NAND  
NVCC_SD  
-0.5  
3.7  
V
NVCC_JTAG  
HDMI, PCIe, and SATA PHY high (VPH) supply voltage  
HDMI, PCIe, and SATA PHY low (VP) supply voltage  
LVDS and MIPI I/O supply voltage (2.5V supply)  
HDMI_VPH  
PCIE_VPH  
SATA_VPH  
-0.3  
2.85  
V
HDMI_VP  
PCIE_VP  
SATA_VP  
-0.3  
-0.3  
1.4  
V
V
NVCC_LVDS_2P5  
NVCC_MIPI  
2.85  
PCIe PHY supply voltage  
RGMII I/O supply voltage  
PCIE_VPTX  
NVCC_RGMII  
VDD_SNVS_IN  
-0.3  
-0.5  
-0.3  
1.4  
2.725  
3.4  
V
V
V
SNVS IN supply voltage  
(Secure Non-Volatile Storage and Real Time Clock)  
USB I/O supply voltage  
USB_H1_DN  
USB_H1_DP  
USB_OTG_DN  
USB_OTG_DP  
USB_OTG_CHD_B  
-0.3  
3.73  
5.35  
V
V
USB VBUS supply voltage  
USB_H1_VBUS  
USB_OTG_VBUS  
Vin/Vout input/output voltage range (non-DDR pins)  
Vin/Vout input/output voltage range (DDR pins)  
ESD immunity (HBM)  
Vin/Vout  
Vin/Vout  
-0.5  
-0.5  
OVDD+0.3 (See note 2)  
OVDD+0.4 (See notes1&2)  
V
V
Vesd_HBM  
Vesd_CDM  
Tstorage  
2000  
500  
V
ESD immunity (CDM)  
V
Storage temperature range  
-40  
150  
°C  
1
The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the  
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.  
2
OVDD is the I/O supply voltage.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
19  
Electrical Characteristics  
4.1.2  
Thermal Resistance  
NOTE  
Per JEDEC JESD51-2, the intent of thermal resistance measurements is  
solely for a thermal performance comparison of one package to another in a  
standardized environment. This methodology is not meant to and will not  
predict the performance of a package in an application-specific  
environment.  
4.1.2.1  
FCPBGA Package Thermal Resistance  
Table 5 provides the FCPBGA package thermal resistance data.  
Table 5. FCPBGA Package Thermal Resistance Data  
Value  
No Lid  
Thermal Parameter  
Test Conditions  
Symbol  
Unit  
Lid  
Junction to Ambient1  
Single-layer board (1s); natural convection2  
RθJA  
RθJA  
31  
22  
24  
15  
17  
12  
5
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Four-layer board (2s2p); natural convection2  
Junction to Ambient1  
Single-layer board (1s); air flow 200 ft/min3  
RθJMA  
RθJMA  
RθJB  
24  
Four-layer board (2s2p); air flow 200 ft/min3  
18  
Junction to Board1,4  
12  
Junction to Case (top)1,5  
RθJCtop  
<0.1  
1
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)  
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal  
resistance.  
2
Per JEDEC JESD51-3 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified  
package.  
3
4
Per JEDEC JESD51-6 with the board horizontal.  
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on  
the top surface of the board near the package.  
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method  
1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the  
interface layer.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
20  
NXP Semiconductors  
Electrical Characteristics  
4.1.3  
Operating Ranges  
Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors.  
Table 6. Operating Ranges  
Parameter  
Description  
Symbol  
Min  
Typ  
Max1  
Unit  
Comment2  
Run mode:  
LDO enabled  
VDD_ARM_IN  
1.2754  
1.5  
V
LDO Output Set Point (VDD_ARM_CAP5) of  
1.150 V minimum for operation up to 792 MHz.  
VDD_ARM23_IN3  
1.054  
1.5  
1.5  
V
V
LDO Output Set Point (VDD_ARM_CAP5) of  
0.925 V minimum for operation up to 396 MHz.  
VDD_SOC_IN6  
1.3504  
264 MHz < VPU 352 MHz; VDDSOC and  
VDDPU LDO outputs (VDD_SOC_CAP and  
VDD_PU_CAP) require 1.225 V minimum.  
1.2754,7  
1.5  
V
VPU 264 MHz; VDDSOC and VDDPU LDO  
outputs (VDD_SOC_CAP and VDD_PU_CAP)  
require 1.15 V minimum.  
Run mode:  
VDD_ARM_IN  
1.150  
0.925  
1.225  
1.15  
1.3  
1.3  
1.3  
1.3  
1.3  
V
V
V
V
V
LDO bypassed for operation up to 792 MHz.  
LDO bypassed for operation up to 396 MHz.  
264 MHz < VPU 352 MHz  
LDO bypassed8  
VDD_ARM23_IN3  
VDD_SOC_IN6  
VPU 264 MHz  
Standby/DSM mode  
VDD_ARM_IN  
0.9  
See Table 9, “Stop Mode Current and Power  
Consumption,” on page 26.  
VDD_ARM23_IN3  
VDD_SOC_IN  
VDD_HIGH_IN9  
0.9  
2.7  
1.3  
3.3  
V
V
VDD_HIGH internal  
regulator  
Must match the range of voltages that the  
rechargeable backup battery supports.  
Backup battery supply VDD_SNVS_IN9  
range  
2.8  
3.3  
V
Should be supplied from the same supply as  
VDD_HIGH_IN, if the system does not require  
keeping real time and other data on OFF state.  
USB supply voltages USB_OTG_VBUS  
USB_H1_VBUS  
4.4  
4.4  
5.25  
5.25  
1.3  
V
V
V
V
V
V
DDR I/O supply  
NVCC_DRAM  
1.14  
1.425  
1.283  
1.15  
1.2  
1.5  
1.35  
LPDDR2  
1.575  
1.45  
2.625  
DDR3  
DDR3L  
Supply for RGMII I/O  
power group10  
NVCC_RGMII  
• 1.15 V – 1.30 V in HSIC 1.2 V mode  
• 1.43 V – 1.58 V in RGMII 1.5 V mode  
• 1.70 V – 1.90 V in RGMII 1.8 V mode  
• 2.25 V – 2.625 V in RGMII 2.5 V mode  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
21  
Electrical Characteristics  
Table 6. Operating Ranges (continued)  
Parameter  
Description  
Symbol  
Min  
Typ  
Max1  
Unit  
Comment2  
GPIO supplies10  
NVCC_CSI,  
NVCC_EIM0,  
NVCC_EIM1,  
NVCC_EIM2,  
1.65  
1.8,  
2.8,  
3.3  
3.6  
V
Isolation between the NVCC_EIMx and  
NVCC_SDx different supplies allow them to  
operate at different voltages within the specified  
range.  
NVCC_ENET,  
NVCC_GPIO,  
NVCC_LCD,  
NVCC_NANDF,  
NVCC_SD1,  
NVCC_SD2,  
NVCC_SD3,  
NVCC_JTAG  
Example: NVCC_EIM1 can operate at 1.8 V  
while NVCC_EIM2 operates at 3.3 V.  
NVCC_LVDS_2P511  
NVCC_MIPI  
2.25  
2.5  
2.75  
V
HDMI supply voltages  
PCIe supply voltages  
HDMI_VP  
HDMI_VPH  
PCIE_VP  
PCIE_VPH  
PCIE_VPTX  
SATA_VP  
SATA_VPH  
TJ  
0.99  
2.25  
1.023  
2.325  
1.023  
0.99  
2.25  
-40  
1.1  
2.5  
1.1  
2.5  
1.1  
1.1  
2.5  
90  
1.3  
2.75  
1.3  
V
V
V
V
V
V
V
2.75  
1.3  
SATA Supply voltages  
Junction temperature  
1.3  
2.75  
105  
°C See i.MX 6Dual/6Quad Product Lifetime Usage  
Estimates Application Note, AN4724, for  
information on product lifetime (power-on  
years) for this processor.  
1
2
3
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set  
point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.  
See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors  
(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.  
For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with  
VDD_ARM23_CAP to reduce leakage.  
4
5
VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.  
VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed  
VDD_ARM_CAP by more than 200 mV.  
6
7
VDDSOC and VDDPU output voltages must be set according to this rule: VDDARM-VDDSOC/PU<50mV.  
In LDO enabled mode, the internal LDO output set points must be configured such that the:  
VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.  
VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.  
The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set  
points shown in this table must be maintained.  
8
9
In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more  
than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages  
shown in this table must be maintained.  
To set VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for i.MX  
6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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NXP Semiconductors  
Electrical Characteristics  
10 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or  
not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current.  
11 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used.  
4.1.4  
External Clock Sources  
Each i.MX 6Dual/6Quad processor has two external input system clocks: a low frequency (RTC_XTALI)  
and a high frequency (XTALI).  
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,  
power-down real time clock operation, and slow system and watchdog counters. The clock input can be  
connected to either an external oscillator or a crystal using the internal oscillator amplifier. Additionally,  
there is an internal ring oscillator, that can be used instead of RTC_XTALI when accuracy is not important.  
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other  
peripherals. The system clock input can be connected to either an external oscillator or a crystal using the  
internal oscillator amplifier.  
NOTE  
The internal RTC oscillator does not provide an accurate frequency and is  
affected by process, voltage and temperature variations. NXP strongly  
recommends using an external crystal as the RTC_XTALI reference. If the  
internal oscillator is used instead, careful consideration should be given to  
the timing implications on all of the SoC modules dependent on this clock.  
Table 7 shows the interface frequency requirements.  
Table 7. External Input Clock Frequency  
Parameter Description  
Symbol  
Min  
Typ  
Max  
Unit  
RTC_XTALI Oscillator1,2  
XTALI Oscillator2,4  
fckil  
fxtal  
32.7683/32.0  
24  
kHz  
MHz  
1
External oscillator or a crystal with internal oscillator amplifier.  
2
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware  
Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).  
3
4
Recommended nominal frequency 32.768 kHz.  
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.  
The typical values shown in Table 7 are required for use with NXP BSPs to ensure precise time keeping  
and USB operation. For RTC_XTALI operation, two clock sources are available:  
On-chip 40 kHz ring oscillator: This clock source has the following characteristics:  
— Approximately 25 μA more Idd than crystal oscillator  
— Approximately 50ꢀ tolerance  
— No external component required  
— Starts up quicker than 32 kHz crystal oscillator  
External crystal oscillator with on-chip support circuit  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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Electrical Characteristics  
— At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit  
switches over to the crystal oscillator automatically.  
— Higher accuracy than ring oscillator.  
— If no external crystal is present, then the ring oscillator is used.  
The decision to choose a clock source should be based on real-time clock use and precision timeout.  
4.1.5  
Maximum Measured Supply Currents  
Power consumption is highly dependent on the application. Estimating the maximum supply currents  
required for power supply design is difficult because the use case that requires maximum supply current is  
not a realistic use case.  
To help illustrate the effect of the application on power consumption, data was collected while running  
industry standard benchmarks that are designed to be compute and graphic intensive. The results provided  
are intended to be used as guidelines for power supply design.  
Description of test conditions:  
The Power Virus data shown in Table 8 represent a use case designed specifically to show the  
maximum current consumption possible for the Arm core complex. All cores are running at the  
defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls.  
Although a valid condition, it would have a very limited, if any, practical use case, and be limited  
to an extremely low duty cycle unless the intention was to specifically cause the worst case power  
consumption.  
EEMBC CoreMark: Benchmark designed specifically for the purpose of measuring the  
performance of a CPU core. More information available at www.eembc.org/coremark. Note that  
this benchmark is designed as a core performance benchmark, not a power benchmark. This use  
case is provided as an example of power consumption that would be typical in a  
computationally-intensive application rather than the Power Virus.  
3DMark Mobile 2011: Suite of benchmarks designed for the purpose of measuring graphics and  
overall system performance. Note that this benchmark is designed as a graphics performance  
benchmark, not a power benchmark. This use case is provided as an example of power  
consumption that would be typical in a very graphics-intensive application.  
Devices used for the tests were from the high current end of the expected process variation.  
The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor  
family, supports the power consumption shown in Table 8, however a robust thermal design is required for  
the increased system power dissipation.  
See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for more  
details on typical power consumption under various use case definitions.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
24  
NXP Semiconductors  
Electrical Characteristics  
Table 8. Maximum Supply Currents  
Conditions  
Maximum Current  
Power Supply  
Unit  
Power Virus  
CoreMark  
i.MX 6Quad:  
VDD_ARM_IN + VDD_ARM23_IN  
• ARM frequency = 792 MHz  
• ARM LDOs set to 1.3V  
• Tj = 105°C  
3270  
2090  
mA  
i.MX 6Dual: VDD_ARM_IN  
• ARM frequency = 792 MHz  
• ARM LDOs set to 1.3V  
• Tj = 105°C  
1960  
1250  
mA  
mA  
i.MX 6Dual or i.MX 6Quad:  
VDD_SOC_IN  
• GPU frequency = 600 MHz  
• SOC LDO set to 1.3 V  
• Tj = 105°C  
2370  
VDD_HIGH_IN  
VDD_SNVS_IN  
1251  
2752  
253  
mA  
μA  
USB_OTG_VBUS/  
mA  
USB_H1_VBUS (LDO 3P0)  
Primary Interface (IO) Supplies  
NVCC_DRAM  
NVCC_ENET  
NVCC_LCD  
NVCC_GPIO  
NVCC_CSI  
(see note4)  
N=10  
N=29  
N=24  
N=20  
N=19  
N=14  
N=20  
N=6  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
Use maximum IO equation5  
25.5  
NVCC_EIM0  
NVCC_EIM1  
NVCC_EIM2  
NVCC_JTAG  
NVCC_RGMII  
NVCC_SD1  
N=6  
N=6  
NVCC_SD2  
N=6  
NVCC_SD3  
N=11  
N=26  
NVCC_NANDF  
NVCC_MIPI  
NVCC_LVDS2P5  
mA  
NVCC_LVDS2P5 is connected to  
VDD_HIGH_CAP at the board  
level. VDD_HIGH_CAP is capable  
of handing the current required by  
NVCC_LVDS2P5.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
25  
Electrical Characteristics  
Power Supply  
Table 8. Maximum Supply Currents (continued)  
Maximum Current  
Power Virus CoreMark  
Conditions  
Unit  
MISC  
DRAM_VREF  
1
mA  
1
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the  
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or  
HDMI, PCIe, and SATA VPH supplies).  
2
Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN  
current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of  
the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that  
current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.  
3
4
This is the maximum current per active USB physical interface.  
The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators  
are typically available from memory vendors which take into account factors such as signal termination.  
See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power  
consumption during specific use case scenarios.  
5
General equation for estimated, maximum power consumption of an IO power supply:  
Imax = N x C x V x (0.5 x F)  
Where:  
N—Number of IO pins supplied by the power line  
C—Equivalent external capacitive load  
V—IO voltage  
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)  
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.  
4.1.6  
Low Power Mode Supply Currents  
Table 9 shows the current core consumption (not including I/O) of the i.MX 6Dual/6Quad processors in  
selected low power modes.  
Table 9. Stop Mode Current and Power Consumption  
Mode  
Test Conditions  
Supply  
Typical1  
Unit  
WAIT  
• Arm, SoC, and PU LDOs are set to 1.225 V  
• HIGH LDO set to 2.5 V  
• Clocks are gated  
• DDR is in self refresh  
• PLLs are active in bypass (24 MHz)  
• Supply voltages remain ON  
VDD_ARM_IN (1.4 V)  
VDD_SOC_IN (1.4 V)  
VDD_HIGH_IN (3.0 V)  
Total  
6
mA  
mA  
mA  
mW  
mA  
mA  
mA  
mW  
23  
3.7  
52  
7.5  
22  
3.7  
52  
STOP_ON  
• Arm LDO set to 0.9 V  
• SoC and PU LDOs set to 1.225 V  
• HIGH LDO set to 2.5 V  
• PLLs disabled  
VDD_ARM_IN (1.4 V)  
VDD_SOC_IN (1.4 V)  
VDD_HIGH_IN (3.0 V)  
Total  
• DDR is in self refresh  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
26  
Electrical Characteristics  
Table 9. Stop Mode Current and Power Consumption (continued)  
Mode  
Test Conditions  
• Arm LDO set to 0.9 V  
• SoC LDO set to 1.225 V  
• PU LDO is power gated  
• HIGH LDO set to 2.5 V  
• PLLs disabled  
Supply  
Typical1  
Unit  
STOP_OFF  
VDD_ARM_IN (1.4 V)  
VDD_SOC_IN (1.4 V)  
VDD_HIGH_IN (3.0 V)  
Total  
7.5  
13.5  
3.7  
41  
mA  
mA  
mA  
mW  
mA  
mA  
mA  
mW  
• DDR is in self refresh  
STANDBY  
• Arm and PU LDOs are power gated  
• SoC LDO is in bypass  
• HIGH LDO is set to 2.5 V  
• PLLs are disabled  
• Low voltage  
• Well Bias ON  
VDD_ARM_IN (0.9 V)  
VDD_SOC_IN (0.9 V)  
VDD_HIGH_IN (3.0 V)  
Total  
0.1  
13  
3.7  
22  
• Crystal oscillator is enabled  
Deep Sleep Mode  
(DSM)  
• Arm and PU LDOs are power gated  
• SoC LDO is in bypass  
• HIGH LDO is set to 2.5 V  
• PLLs are disabled  
• Low voltage  
• Well Bias ON  
VDD_ARM_IN (0.9 V)  
VDD_SOC_IN (0.9 V)  
VDD_HIGH_IN (3.0 V)  
Total  
0.1  
2
mA  
mA  
mA  
mW  
0.5  
3.4  
• Crystal oscillator and bandgap are disabled  
SNVS Only  
• VDD_SNVS_IN powered  
• All other supplies off  
• SRTC running  
VDD_SNVS_IN (2.8V)  
Total  
41  
μA  
115  
μW  
1
The typical values shown here are for information only and are not guaranteed. These values are average values measured  
on a worst-case wafer at 25°C.  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
NXP Semiconductors  
27  
Electrical Characteristics  
4.1.7  
USB PHY Current Consumption  
4.1.7.1  
Power Down Mode  
In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.  
Table 10 shows the USB interface current consumption in power down mode.  
Table 10. USB PHY Current Consumption in Power Down Mode  
VDD_USB_CAP (3.0 V)  
VDD_HIGH_CAP (2.5 V)  
NVCC_PLL_OUT (1.1 V)  
Current  
5.1 μA  
1.7 μA  
<0.5 μA  
NOTE  
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were  
identified to be the voltage divider circuits in the USB-specific level shifters.  
4.1.8  
SATA Typical Power Consumption  
Table 11 provides SATA PHY currents for certain Tx operating modes.  
NOTE  
Tx power consumption values are provided for a single transceiver. If  
T = single transceiver power and C = Clock module power, the total power  
required for N lanes = N x T + C.  
Table 11. SATA PHY Current Drain  
Mode  
Test Conditions  
Supply  
Typical Current  
Unit  
P0: Full-power state1  
Single Transceiver  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
11  
13  
mA  
Clock Module  
Single Transceiver  
Clock Module  
6.9  
6.2  
11  
P0: Mobile2  
mA  
mA  
11  
6.9  
6.2  
9.4  
2.9  
6.9  
6.2  
P0s: Transmitter idle  
Single Transceiver  
Clock Module  
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Electrical Characteristics  
Table 11. SATA PHY Current Drain (continued)  
Mode  
Test Conditions  
Supply  
Typical Current  
Unit  
P1: Transmitter idle, Rx powered  
down, LOS disabled  
Single Transceiver  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
SATA_VP  
SATA_VPH  
0.67  
0.23  
6.9  
mA  
Clock Module  
Single Transceiver  
Clock Module  
6.2  
P2: Powered-down state, only  
LOS and POR enabled  
0.53  
0.11  
0.036  
0.12  
0.13  
0.012  
0.008  
0.004  
mA  
mA  
PDDQ mode3  
Single Transceiver  
Clock Module  
1
Programmed for 1.0 V peak-to-peak Tx level.  
2
3
Programmed for 0.9 V peak-to-peak Tx level with no boost or attenuation.  
LOW power non-functional.  
4.1.9  
PCIe 2.0 Maximum Power Consumption  
Table 12 provides PCIe PHY currents for certain operating modes.  
Table 12. PCIe PHY Current Drain  
Mode  
Test Conditions  
Supply  
Max Current  
Unit  
P0: Normal Operation  
5G Operations  
PCIE_VP (1.1 V)  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
PCIE_VP (1.1 V)  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
PCIE_VP (1.1 V)  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
PCIE_VP (1.1 V)  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
40  
20  
21  
27  
20  
20  
30  
2.4  
18  
20  
2.4  
18  
mA  
2.5G Operations  
5G Operations  
2.5G Operations  
P0s: Low Recovery Time  
Latency, Power Saving State  
mA  
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Electrical Characteristics  
Mode  
Table 12. PCIe PHY Current Drain (continued)  
Test Conditions  
Supply  
Max Current  
Unit  
P1: Longer Recovery Time  
Latency, Lower Power State  
PCIE_VP (1.1 V)  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
PCIE_VP (1.1 V)  
12  
2.4  
mA  
12  
Power Down  
1.3  
mA  
PCIE_VPTX (1.1 V)  
PCIE_VPH (2.5 V)  
0.18  
0.36  
4.1.10 HDMI Maximum Power Consumption  
Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down  
modes.  
Table 13. HDMI PHY Current Drain  
Mode  
Test Conditions  
Supply  
Max Current  
Unit  
Active  
Bit rate 251.75 Mbps  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
HDMI_VPH  
HDMI_VP  
14  
4.1  
14  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
μA  
Bit rate 279.27 Mbps  
Bit rate 742.5 Mbps  
Bit rate 1.485 Gbps  
Bit rate 2.275 Gbps  
Bit rate 2.97 Gbps  
4.2  
17  
7.5  
17  
12  
16  
17  
19  
22  
Power-down  
49  
1100  
μA  
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Electrical Characteristics  
4.2  
Power Supplies Requirements and Restrictions  
The system design must comply with power-up sequence, power-down sequence, and steady state  
guidelines as described in this section to ensure the reliable operation of the device. Any deviation from  
these sequences may result in the following situations:  
Excessive current during power-up phase  
Prevention of the device from booting  
Irreversible damage to the processor  
4.2.1  
Power-Up Sequence  
For power-up sequence, the restrictions are as follows:  
VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected  
(shorted) with VDD_HIGH_IN supply.  
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other  
supply is switched on.  
The SRC_POR_B signal controls the processor POR and must be immediately asserted at  
power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP  
supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no  
restrictions.  
NOTE  
Ensure that there is no back voltage (leakage) from any supply on the board  
towards the 3.3 V supply (for example, from the external components that  
use both the 1.8 V and 3.3 V supplies).  
NOTE  
USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply  
sequence and can be powered at any time.  
4.2.2  
Power-Down Sequence  
There are no special restrictions for i.MX 6Dual/6Quad SoC.  
4.2.3  
Power Supplies Usage  
All I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx) is  
OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For  
information about I/O power supply of each pin, see the “Power Group” column of Table 87, “21  
x 21 mm Functional Contact Assignments”.  
WhentheSATAinterfaceisnotused, theSATA_VPandSATA_VPHsuppliesshouldbegrounded.  
The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N,  
SATA_PHY_RX_P, and SATA_PHY_TX_N) can remain unconnected. It is recommended not to  
turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive  
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Electrical Characteristics  
power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain  
powered.  
When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should  
be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N,  
PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to  
turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive  
power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must  
remain powered.  
4.3  
Integrated LDO Voltage Regulator Parameters  
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins  
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use  
only and should not be used to power any external circuitry. See the i.MX 6Dual/6Quad reference manual  
(IMX6DQRM) for details on the power tree scheme recommended operation.  
NOTE  
The *_CAP signals should not be powered externally. These signals are  
intended for internal LDO or LDO bypass operation only.  
4.3.1  
Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)  
There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because  
of their construction). The advantages of the regulators are to reduce the input supply variation because of  
their input supply ripple rejection and their on die trimming. This translates into more voltage for the die  
producing higher operating frequencies. These regulators have three basic modes.  
Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the  
load unaltered. The analog part of the regulator is powered down in this state, removing any loss  
other than the IR drop through the power grid and FET.  
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.  
The analog part of the regulator is powered down here limiting the power consumption.  
Analog regulation mode. The regulation FET is controlled such that the output voltage of the  
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV  
steps.  
Optionally LDO_SOC/VDD_SOC_CAP can be used to power the HDMI, PCIe, and SATA PHY's through  
external connections.  
For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
4.3.2  
Regulators for Analog Modules  
LDO_1P1 / NVCC_PLL_OUT  
4.3.2.1  
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see  
Table 6 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V  
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Electrical Characteristics  
to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs,  
and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the  
system to determine when the load capability of the regulator is being exceeded to take the necessary steps.  
Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.  
Active-pull-down can also be enabled for systems requiring this feature.  
For information on external capacitor requirements for this regulator, see the Hardware Development  
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors  
(IMX6DQ6SDLHDG).  
For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
4.3.2.2  
LDO_2P5  
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see  
Table 6 for min and max input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V  
with the nominal default setting as 2.5 V. The LDO_2P5 supplies the SATA PHY, USB PHY, LVDS PHY,  
HDMI PHY, MIPI PHY, E-fuse module and PLLs. A programmable brown-out detector is included in the  
regulator that can be used by the system to determine when the load capability of the regulator is being  
exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current  
requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this  
feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for  
applications needing to keep the output voltage alive during low-power modes where the main regulator  
driver and its associated global bandgap reference module are disabled. The output of the weak-regulator  
is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V  
input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 Ω.  
For information on external capacitor requirements for this regulator, see the Hardware Development  
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors  
(IMX6DQ6SDLHDG).  
For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
4.3.2.3  
LDO_USB  
The LDO_USB module implements a programmable linear-regulator function from the  
USB_OTG_VBUS and USB_H1_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output  
voltage. A programmable brown-out detector is included in the regulator that can be used by the system to  
determine when the load capability of the regulator is being exceeded, to take the necessary steps. This  
regulator has a built in power-mux that allows the user to select to run the regulator from either VBUS  
supply, when both are present. If only one of the VBUS voltages is present, then the regulator  
automatically selects this supply. Current limit is also included to help the system meet in-rush current  
targets. If no VBUS voltage is present, then the VBUSVALID threshold setting will prevent the regulator  
from being enabled.  
For information on external capacitor requirements for this regulator, see the Hardware Development  
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors  
(IMX6DQ6SDLHDG).  
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Electrical Characteristics  
For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).  
4.4  
PLL Electrical Characteristics  
4.4.1  
Audio/Video PLL Electrical Parameters  
Table 14. Audio/Video PLL Electrical Parameters  
Parameter  
Value  
Clock output range  
Reference clock  
Lock time  
650 MHz ~1.3 GHz  
24 MHz  
<11250 reference cycles  
4.4.2  
4.4.3  
4.4.4  
528 MHz PLL  
Table 15. 528 MHz PLL Electrical Parameters  
Parameter  
Value  
Clock output range  
Reference clock  
Lock time  
528 MHz PLL output  
24 MHz  
<11250 reference cycles  
Ethernet PLL  
Table 16. Ethernet PLL Electrical Parameters  
Parameter  
Value  
Clock output range  
Reference clock  
Lock time  
500 MHz  
24 MHz  
<11250 reference cycles  
480 MHz PLL  
Table 17. 480 MHz PLL Electrical Parameters  
Parameter  
Value  
Clock output range  
Reference clock  
Lock time  
480 MHz PLL output  
24 MHz  
<383 reference cycles  
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4.4.5  
Arm PLL  
Table 18. Arm PLL Electrical Parameters  
Parameter  
Value  
Clock output range  
Reference clock  
Lock time  
650 MHz~1.3 GHz  
24 MHz  
<2250 reference cycles  
4.5  
On-Chip Oscillators  
OSC24M  
4.5.1  
This block implements an amplifier that when combined with a suitable quartz crystal and external load  
capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.  
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight  
forward biased-inverter implementation is used.  
4.5.2  
OSC32K  
This block implements an amplifier that when combined with a suitable quartz crystal and external load  
capacitors implements a low power oscillator. It also implements a power mux such that it can be powered  
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes  
power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when  
VDD_HIGH_IN is lost.  
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz  
clock will automatically switch to the internal ring oscillator.  
CAUTION  
The internal RTC oscillator does not provide an accurate frequency and is  
affected by process, voltage, and temperature variations. NXP strongly  
recommends using an external crystal as the RTC_XTALI reference. If the  
internal oscillator is used instead, careful consideration must be given to the  
timing implications on all of the SoC modules dependent on this clock.  
The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN  
power mux.  
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Table 19. OSC32K Main Characteristics  
Max Comments  
Parameter Min  
Typ  
Fosc  
32.768 kHz  
This frequency is nominal and determined mainly by the crystal selected. 32.0 K  
would work as well.  
Current  
consumption  
4 μA  
The typical value shown is only for the oscillator, driven by an external crystal.  
If the internal ring oscillator is used instead of an external crystal, then  
approximately 25 μA must be added to this value.  
Bias resistor  
14 MΩ  
This the integrated bias resistor that sets the amplifier into a high gain state. Any  
leakage through the ESD network, external board leakage, or even a scope probe  
that is significant relative to this value will debias the amplifier. The debiasing will  
result in low gain, and will impact the circuit's ability to start up and maintain  
oscillations.  
Target Crystal Properties  
Cload  
ESR  
10 pF  
Usually crystals can be purchased tuned for different Cloads. This Cload value is  
typically 1/2 of the capacitances realized on the PCB on either side of the quartz.  
A higher Cload will decrease oscillation margin, but increases current oscillating  
through the crystal.  
50 kΩ  
100 kΩ Equivalent series resistance of the crystal. Choosing a crystal with a higher value  
will decrease the oscillating margin.  
4.6  
I/O DC Parameters  
This section includes the DC parameters of the following I/O types:  
General Purpose I/O (GPIO)  
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes  
LVDS I/O  
NOTE  
The term ‘OVDD’ in this section refers to the associated supply rail of an  
input or output.  
ovdd  
pmos (Rpu)  
Voh min  
1
Vol max  
or  
0
pdat  
pad  
Predriver  
nmos (Rpd)  
ovss  
Figure 3. Circuit for Parameters Voh and Vol for I/O Cells  
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4.6.1  
XTALI and RTC_XTALI (Clock Inputs) DC Parameters  
Table 20 shows the DC parameters for the clock inputs.  
Table 20. XTALI and RTC_XTALI DC Parameters  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
XTALI high-level DC input voltage  
XTALI low-level DC input voltage  
Vih  
Vil  
0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT  
V
V
V
0
0.2  
RTC_XTALI high-level DC input  
voltage  
Vih  
0.8  
1.1(See note 1)  
RTC_XTALI low-level DC input  
voltage  
Vil  
0
0.2  
V
Input capacitance  
CIN  
Simulated data  
5
pF  
XTALI input leakage current at  
startup  
IXTALI_STARTUP Power-on startup for  
0.15 msecwithadriven  
24 MHz clock  
600  
μA  
at 1.1 V. 2  
DC input current  
IXTALI_DC  
2.5  
μA  
1
This voltage specification must not be exceeded and, as such, is an absolute maximum specification.  
This current draw is present even if an external clock source directly drives XTALI.  
2
NOTE  
The Vil and Vih specifications only apply when an external clock source is  
used. If a crystal is used, Vil and Vih do not apply.  
4.6.2  
General Purpose I/O (GPIO) DC Parameters  
Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the  
operating ranges in Table 6, unless otherwise noted.  
Table 21. GPIO I/O DC Parameters  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
Unit  
High-level output voltage1  
Voh  
Ioh = -0.1 mA (DSE2 = 001, 010)  
Ioh = -1 mA  
OVDD – 0.15  
V
(DSE = 011, 100, 101, 110, 111)  
Low-level output voltage1  
Vol  
Iol = 0.1 mA (DSE2 = 001, 010)  
Iol = 1mA  
0.15  
V
(DSE = 011, 100, 101, 110, 111)  
High-Level DC input voltage1, 3  
Low-Level DC input voltage1, 3  
Input Hysteresis  
Vih  
Vil  
0.7 × OVDD  
OVDD  
0.3 × OVDD  
V
V
V
0
Vhys  
OVDD = 1.8 V  
OVDD = 3.3 V  
0.25  
Schmitt trigger VT+3, 4  
Schmitt trigger VT–3, 4  
VT+  
VT–  
0.5 × OVDD  
V
V
0.5 × OVDD  
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Electrical Characteristics  
Parameter  
Table 21. GPIO I/O DC Parameters (continued)  
Symbol  
Test Conditions  
Min  
Max  
Unit  
Input current (no pull-up/down)  
Iin  
Iin  
Vin = OVDD or 0  
-1  
1
μA  
Input current (22 kΩ pull-up)  
Vin = 0 V  
Vin = OVDD  
212  
1
μA  
μA  
μA  
μA  
kΩ  
Input current (47 kΩ pull-up)  
Input current (100 kΩ pull-up)  
Input current (100 kΩ pull-down)  
Keeper circuit resistance  
Iin  
Iin  
Vin = 0 V  
Vin = OVDD  
100  
1
Vin = 0 V  
Vin= OVDD  
48  
1
Iin  
Vin = 0 V  
Vin = OVDD  
1
48  
Rkeep  
Vin = 0.3 x OVDD  
Vin = 0.7 x OVDD  
105  
175  
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,  
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be  
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.  
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.  
2
3
DSE is the Drive Strength Field setting in the associated IOMUX control register.  
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC  
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.  
4
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.  
4.6.3  
DDR I/O DC Parameters  
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.  
4.6.4  
RGMII I/O 2.5V I/O DC Electrical Parameters  
The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 22 are  
guaranteed per the operating ranges in Table 6, unless otherwise noted.  
1
Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
Units  
High-level output voltage1  
VOH  
Ioh= -0.1 mA (DSE=001,010)  
V
OVDD-0.15  
Ioh= -1.0 mA (DSE=011,100,101,110,111)  
Low-level output voltage1  
VOL  
Iol= 0.1 mA (DSE=001,010)  
0.15  
V
Iol= 1.0 mA (DSE=011,100,101,110,111)  
0.49xOVDD 0.51xOVDD  
Input Reference Voltage  
High-Level input voltage 2, 3  
Low-Level input voltage 2, 3  
Vref  
VIH  
VIL  
V
V
0.7xOVDD  
OVDD  
0.3xOVDD  
0
V
Input Hysteresis(OVDD=1.8V) VHYS_HighVDD  
Input Hysteresis(OVDD=2.5V) VHYS_HighVDD  
OVDD=1.8V  
OVDD=2.5V  
250  
250  
mV  
mV  
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Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters (continued)  
1
Schmitt trigger VT+ 3, 4  
VTH+  
VTH-  
0.5xOVDD  
mV  
Schmitt trigger VT- 3, 4  
0.5xOVDD mV  
Pull-up resistor (22 kΩ PU)  
Pull-up resistor (22 kΩ PU)  
Pull-up resistor (47 kΩ PU)  
Pull-up resistor (47 kΩ PU)  
Pull-up resistor (100 kΩ PU)  
Pull-up resistor (100 kΩ PU)  
Pull-down resistor (100 kΩ PD)  
Pull-down resistor (100 kΩ PD)  
Keeper Circuit Resistance  
Input current (no pull-up/down)  
RPU_22K  
RPU_22K  
RPU_47K  
RPU_47K  
RPU_100K  
RPU_100K  
RPD_100K  
RPD_100K  
Rkeep  
Vin=0V  
212  
1
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
kΩ  
μA  
Vin=OVDD  
Vin=0V  
100  
1
Vin=OVDD  
Vin=0V  
48  
1
Vin=OVDD  
Vin=OVDD  
Vin=0V  
48  
1
105  
-2.9  
165  
2.9  
Iin  
VI = 0,VI = OVDD  
1
Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode)  
SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode).  
2
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6  
V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must  
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other  
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.  
3
4
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC  
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.  
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled  
(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).  
4.6.4.1  
LPDDR2 Mode I/O DC Parameters  
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported  
DDR3/DDR3L/LPDDR2 Configurations.”  
The parameters in Table 23 are guaranteed per the operating ranges in Table 6, unless otherwise noted.  
1
Table 23. LPDDR2 I/O DC Electrical Parameters  
Parameters  
Symbol  
Test Conditions  
Min  
Max  
Unit  
High-level output voltage  
Low-level output voltage  
Input reference voltage  
DC input High Voltage  
Voh  
Vol  
Ioh = -0.1 mA  
0.9 × OVDD  
V
V
Iol = 0.1 mA  
0.1 × OVDD  
0.51 × OVDD  
OVDD  
Vref  
0.49 × OVDD  
Vref+0.13V  
OVSS  
Vih(dc)  
Vil(dc)  
Vih(diff)  
Vil(diff)  
Iin  
V
V
DC input Low Voltage  
Vref-0.13V  
See Note 2  
-0.26  
Differential Input Logic High  
Differential Input Logic Low  
Input current (no pull-up/down)  
0.26  
μA  
See Note 2  
-2.5  
Vin = 0 or OVDD  
2.5  
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Parameters  
1
Table 23. LPDDR2 I/O DC Electrical Parameters (continued)  
Symbol  
Test Conditions  
Min  
Max  
Unit  
Pull-up/pull-down impedance mismatch  
MMpupd  
Rres  
-15  
+15  
10  
%
Ω
240 Ω unit calibration resolution  
Keeper circuit resistance  
Rkeep  
110  
175  
kΩ  
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.  
2
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as  
the limitations for overshoot and undershoot (see Table 28).  
4.6.4.2  
DDR3/DDR3L Mode I/O DC Parameters  
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported  
DDR3/DDR3L/LPDDR2 Configurations.”  
The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted.  
Table 24. DDR3/DDR3L I/O DC Electrical Parameters  
Parameters  
Symbol  
Test Conditions  
Min  
Max  
Unit  
High-level output voltage  
Ioh = -0.1 mA  
Voh (DSE = 001)  
Voh  
0.8 × OVDD1  
V
Ioh = -1 mA  
Voh (for all except DSE = 001)  
Low-level output voltage  
Iol = 0.1 mA  
Vol (DSE = 001)  
Vol  
0.2 × OVDD  
V
Iol = 1 mA  
Vol (for all except DSE = 001)  
Input reference voltage  
Vref2  
Vih(dc)  
Vil(dc)  
Vih(diff)  
Vil(diff)  
Vtt  
0.49 × OVDD 0.51 × OVDD  
DC input Logic High  
Vref+0.1  
OVSS  
OVDD  
Vref-0.1  
See Note3  
-0.2  
V
V
DC input Logic Low  
Differential input Logic High  
Differential input Logic Low  
Termination Voltage  
0.2  
V
See Note3  
V
Vtt tracking OVDD/2  
0.49 × OVDD 0.51 × OVDD  
V
Input current (no pull-up/down)  
Pull-up/pull-down impedance mismatch  
240 Ω unit calibration resolution  
Keeper circuit resistance  
Iin  
Vin = 0 or OVDD  
-2.9  
-10  
2.9  
10  
μA  
%
Ω
MMpupd  
Rres  
10  
Rkeep  
105  
175  
kΩ  
1
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L).  
Vref – DDR3/DDR3L external reference voltage.  
2
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as  
the limitations for overshoot and undershoot (see Table 29).  
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4.6.5  
LVDS I/O DC Parameters  
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,  
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.  
Table 25 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.  
Table 25. LVDS I/O DC Parameters  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
Unit  
Output Differential Voltage  
Output High Voltage  
Output Low Voltage  
Offset Voltage  
VOD  
VOH  
VOL  
VOS  
Rload=100 Ω between padP and padN  
250  
1.25  
0.9  
450  
1.6  
mV  
IOH = 0 mA  
IOL = 0 mA  
1.25  
1.375  
V
1.125  
4.7  
I/O AC Parameters  
This section includes the AC parameters of the following I/O types:  
General Purpose I/O (GPIO)  
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes  
LVDS I/O  
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and  
Figure 5.  
From Output  
Under Test  
Test Point  
CL  
CL includes package, probe and fixture capacitance  
Figure 4. Load Circuit for Output  
OVDD  
0 V  
80%  
20%  
80%  
20%  
tr  
Output (at pad)  
tf  
Figure 5. Output Transition Time Waveform  
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Electrical Characteristics  
4.7.1  
General Purpose I/O AC Parameters  
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 26 and Table 27,  
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the  
IOMUXC control registers.  
Table 26. General Purpose I/O AC Parameters 1.8 V Mode  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Output Pad Transition Times, rise/fall  
(Max Drive, DSE=111)  
tr, tf  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
2.72/2.79  
1.51/1.54  
Output Pad Transition Times, rise/fall  
(High Drive, DSE=101)  
tr, tf  
tr, tf  
tr, tf  
trm  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
3.20/3.36  
1.96/2.07  
ns  
ns  
Output Pad Transition Times, rise/fall  
(Medium Drive, DSE=100)  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
3.64/3.88  
2.27/2.53  
Output Pad Transition Times, rise/fall  
(Low Drive. DSE=011)  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
4.32/4.50  
3.16/3.17  
Input Transition Times1  
25  
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.  
Table 27. General Purpose I/O AC Parameters 3.3 V Mode  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Output Pad Transition Times, rise/fall  
(Max Drive, DSE=101)  
tr, tf  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
1.70/1.79  
1.06/1.15  
Output Pad Transition Times, rise/fall  
(High Drive, DSE=011)  
tr, tf  
tr, tf  
tr, tf  
trm  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
2.35/2.43  
1.74/1.77  
ns  
Output Pad Transition Times, rise/fall  
(Medium Drive, DSE=010)  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
3.13/3.29  
2.46/2.60  
Output Pad Transition Times, rise/fall  
(Low Drive. DSE=001)  
15 pF Cload, slow slew rate  
15 pF Cload, fast slew rate  
5.14/5.57  
4.77/5.15  
Input Transition Times1  
25  
ns  
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.  
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4.7.2  
DDR I/O AC Parameters  
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported  
DDR3/DDR3L/LPDDR2 Configurations.”  
Table 28 shows the AC parameters for DDR I/O operating in LPDDR2 mode.  
1
Table 28. DDR I/O LPDDR2 Mode AC Parameters  
Parameter  
AC input logic high  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Vih(ac)  
Vil(ac)  
Vref + 0.22  
OVDD  
Vref – 0.22  
V
V
AC input logic low  
0
0.44  
AC differential input high voltage2  
AC differential input low voltage  
Input AC differential cross point voltage3  
Over/undershoot peak  
Vidh(ac)  
Vidl(ac)  
Vix(ac)  
Vpeak  
V
Relative to Vref  
0.44  
V
-0.12  
0.12  
V
0.35  
V
Over/undershoot area (above OVDD  
or below OVSS)  
Varea  
400 MHz  
0.2  
V-ns  
Single output slew rate, measured  
between Vol(ac) and Voh(ac)  
tsr  
50 Ω to Vref.  
5 pF load.  
Drive impedance = 4 0 Ω 30%  
1.5  
1
3.5  
2.5  
0.1  
V/ns  
50 Ω to Vref.  
5pF load.  
Drive impedance = 60 Ω 30%  
Skew between pad rise/fall asymmetry +  
skew caused by SSN  
tSKD  
clk = 400 MHz  
ns  
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.  
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is  
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).  
3
The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)  
indicates the voltage at which differential input signal must cross.  
Table 29 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.  
1
Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters  
Parameter  
AC input logic high  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Vih(ac)  
Vil(ac)  
Vid(ac)  
Vix(ac)  
Vpeak  
Varea  
Vref + 0.175  
OVDD  
Vref – 0.175  
V
V
AC input logic low  
0
0.35  
AC differential input voltage2  
Input AC differential cross point voltage3  
Over/undershoot peak  
Relative to Vref  
V
Vref – 0.15  
Vref + 0.15  
0.4  
V
V
Over/undershoot area (above OVDD  
or below OVSS)  
533 MHz  
0.5  
V-ns  
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Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters (continued)  
1
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Single output slew rate, measured between  
Vol(ac) and Voh(ac)  
tsr  
Driver impedance =  
2.5  
5
V/ns  
34 Ω  
Skew between pad rise/fall asymmetry +  
skew caused by SSN  
tSKD  
clk = 533 MHz  
0.1  
ns  
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.  
2
3
Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is  
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).  
The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)  
indicates the voltage at which differential input signal must cross.  
4.7.3  
LVDS I/O AC Parameters  
The differential output transition time waveform is shown in Figure 6.  
padp  
V
OH  
0V  
0V  
0V (Differential)  
padn  
V
OL  
80%  
80%  
0V  
VDIFF  
VDIFF = {padp} - {padn}  
20%  
20%  
t
t
THL  
TLH  
Figure 6. Differential LVDS Driver Transition Time Waveform  
Table 30 shows the AC parameters for LVDS I/O.  
Table 30. I/O AC Parameters of LVDS Pad  
Parameter  
Differential pulse skew1  
Symbol Test Condition  
Min  
Typ  
Max  
Unit  
tSKD  
0.25  
0.5  
Rload = 100 Ω,  
Cload = 2 pF  
Transition Low to High Time2  
Transition High to Low Time2  
Operating Frequency  
tTLH  
ns  
tTHL  
0.5  
f
600  
800  
150  
MHz  
mV  
Offset voltage imbalance  
Vos  
1
tSKD = | tPHLD – tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and  
the negative going edge of the same channel.  
2
Measurement levels are 20–80% from output voltage.  
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4.8  
Output Buffer Impedance Parameters  
This section defines the I/O impedance parameters of the i.MX 6Dual/6Quad processors for the following  
I/O types:  
General Purpose I/O (GPIO)  
Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes  
LVDS I/O  
NOTE  
GPIO and DDR I/O output driver impedance is measured with “long”  
transmission line of impedance Ztl attached to I/O pad and incident wave  
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that  
defines specific voltage of incident wave relative to OVDD. Output driver  
impedance is calculated from this voltage divider (see Figure 7).  
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OVDD  
PMOS (Rpu)  
Ztl Ω, L = 20 inches  
ipp_do  
pad  
predriver  
Cload = 1p  
NMOS (Rpd)  
OVSS  
U,(V)  
VDD  
Vin (do)  
t,(ns)  
0
U,(V)  
Vout (pad)  
OVDD  
Vref2  
Vref1  
Vref  
t,(ns)  
0
Vovdd – Vref1  
Vref1  
Rpu =  
Rpd =  
× Ztl  
× Ztl  
Vref2  
Vovdd – Vref2  
Figure 7. Impedance Matching Load for Measurement  
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4.8.1  
GPIO Output Buffer Impedance  
Table 31 shows the GPIO output buffer impedance (OVDD 1.8 V).  
Table 31. GPIO Output Buffer Average Impedance (OVDD 1.8 V)  
Parameter  
Symbol  
Drive Strength (DSE)  
Typ Value  
Unit  
001  
010  
011  
100  
101  
110  
111  
260  
130  
90  
60  
50  
Output Driver  
Impedance  
Rdrv  
Ω
40  
33  
Table 32 shows the GPIO output buffer impedance (OVDD 3.3 V).  
Table 32. GPIO Output Buffer Average Impedance (OVDD 3.3 V)  
Parameter  
Symbol  
Drive Strength (DSE)  
Typ Value  
Unit  
001  
010  
011  
100  
101  
110  
111  
150  
75  
50  
37  
30  
25  
20  
Output Driver  
Impedance  
Rdrv  
Ω
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4.8.2  
DDR I/O Output Buffer Impedance  
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported  
DDR3/DDR3L/LPDDR2 Configurations.”  
Table 33 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors.  
Table 33. DDR I/O Output Buffer Impedance  
Typical  
NVCC_DRAM=1.5 V  
(DDR3)  
NVCC_DRAM=1.2 V  
(LPDDR2)  
Parameter  
Symbol  
Test Conditions  
Unit  
DDR_SEL=11  
DDR_SEL=10  
Drive Strength (DSE) =  
000  
001  
010  
011  
100  
101  
110  
111  
Hi-Z  
240  
120  
80  
60  
48  
Hi-Z  
240  
120  
80  
60  
48  
Output Driver  
Impedance  
Rdrv  
Ω
40  
34  
40  
34  
Note:  
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.  
2. Calibration is done against 240 W external reference resistor.  
3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.  
4.8.3  
LVDS I/O Output Buffer Impedance  
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,  
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.  
4.9  
System Modules Timing  
This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad  
processor.  
4.9.1  
Reset Timing Parameters  
Figure 8 shows the reset timing and Table 34 lists the timing parameters.  
SRC_POR_B  
(Input)  
CC1  
Figure 8. Reset Timing Diagram  
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Table 34. Reset Timing Parameters  
ID  
Parameter  
Min  
Max  
Unit  
CC1  
Duration of SRC_POR_B to be qualified as valid  
1
XTALOSC_RTC_ XTALI cycle  
4.9.2  
WDOG Reset Timing Parameters  
Figure 9 shows the WDOG reset timing and Table 35 lists the timing parameters.  
WDOG1_B  
(Output)  
CC3  
Figure 9. WDOG1_B Timing Diagram  
Table 35. WDOG1_B Timing Parameters  
ID  
Parameter  
Min  
Max  
Unit  
CC3 Duration of WDOG1_B Assertion  
1
XTALOSC_RTC_ XTALI cycle  
NOTE  
XTALOSC_RTC_XTALI is approximately 32 kHz.  
XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.  
NOTE  
WDOG1_B output signals (for each one of the Watchdog modules) do not  
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX  
manual for detailed information.  
4.9.3  
External Interface Module (EIM)  
The following subsections provide information on the EIM. Maximum operating frequency for EIM data  
transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or  
clock periods are valid for the entire range of allowed frequencies (0–104 MHz).  
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4.9.3.1  
EIM Interface Pads Allocation  
EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.  
Table 36 provides EIM interface pads allocation in different modes.  
1
Table 36. EIM Internal Module Multiplexing  
Multiplexed  
Non Multiplexed Address/Data Mode  
Address/Data mode  
Setup  
8 Bit  
16 Bit  
32 Bit  
16 Bit  
32 Bit  
MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 1, MUM = 1,  
DSZ = 100 DSZ = 101 DSZ = 110 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011  
EIM_ADDR  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_AD  
[15:00]  
EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_DATA  
[25:16]  
[25:16]  
[25:16]  
[25:16]  
[25:16]  
[25:16]  
[25:16]  
[25:16]  
EIM_DATA EIM_AD  
[07:00] [07:00]  
[25:16]  
[09:00]  
EIM_DATA EIM_DATA  
[07:00],  
EIM_EB0_B  
EIM_DATA  
[07:00]  
EIM_AD  
[07:00]  
[07:00]  
EIM_DATA  
[15:08],  
EIM_EB1_B  
EIM_DATA  
[15:08]  
EIM_DATA  
[15:08]  
EIM_DATA EIM_AD  
EIM_AD  
[15:08]  
[15:08]  
[15:08]  
EIM_DATA  
[23:16],  
EIM_EB2_B  
EIM_DATA  
[23:16]  
EIM_DATA EIM_DATA  
[23:16] [23:16]  
EIM_DATA  
[07:00]  
EIM_DATA  
[31:24],  
EIM_DATA  
[31:24]  
EIM_DATA EIM_DATA  
[31:24] [31:24]  
EIM_DATA  
[15:08]  
EIM_EB3_B  
1
For more information on configuration ports mentioned in this table, see the i.MX 6Dual/6Quad reference manual  
(IMX6DQRM).  
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4.9.3.2  
General EIM Timing-Synchronous Mode  
Figure 10, Figure 11, and Table 37 specify the timings related to the EIM module. All EIM output control  
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge  
according to corresponding assertion/negation control fields.  
WE2  
EIM_BCLK  
...  
WE3  
WE1  
WE4  
WE6  
WE5  
WE7  
WE9  
EIM_ADDRxx  
EIM_CSx_B  
WE8  
WE10  
WE12  
EIM_WE_B  
EIM_OE_B  
EIM_EBx_B  
WE11  
WE13  
WE15  
WE17  
WE14  
WE16  
EIM_LBA_B  
Output Data  
Figure 10. EIM Output Timing Diagram  
EIM_BCLK  
WE18  
Input Data  
WE19  
WE20  
EIM_WAIT_B  
WE21  
Figure 11. EIM Input Timing Diagram  
4.9.3.3  
Examples of EIM Synchronous Accesses  
Table 37. EIM Bus Timing Parameters  
ID  
Parameter  
Min1  
Max1  
Unit  
WE1  
WE2  
WE3  
EIM_BCLK cycle time2  
t × (k+1)  
ns  
ns  
ns  
EIM_BCLK high level width  
EIM_BCLK low level width  
0.4 × t × (k+1)  
0.4 × t × (k+1)  
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Table 37. EIM Bus Timing Parameters (continued)  
ID  
Parameter  
Clock rise to address valid  
Min1  
Max1  
Unit  
WE4  
WE5  
WE6  
WE7  
WE8  
WE9  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
-0.5 × t × (k+1) - 1.25  
0.5 × t × (k+1) - 1.25  
2.3  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
-0.5 × t × (k+1) + 2.25  
0.5 × t × (k+1) + 2.25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock rise to address invalid  
Clock rise to EIM_CSx_B valid  
Clock rise to EIM_CSx_B invalid  
Clock rise to EIM_WE_B valid  
Clock rise to EIM_WE_B invalid  
WE10 Clock rise to EIM_OE_B valid  
WE11 Clock rise to EIM_OE_B invalid  
WE12 Clock rise to EIM_EBx_B valid  
WE13 Clock rise to EIM_EBx_B invalid  
WE14 Clock rise to EIM_LBA_B valid  
WE15 Clock rise to EIM_LBA_B invalid  
WE16 Clock rise to output data valid  
WE17 Clock rise to output data invalid  
WE18 Input data setup time to clock rise  
WE19 Input data hold time from clock rise  
WE20 EIM_WAIT_B setup time to clock rise  
WE21 EIM_WAIT_B hold time from clock rise  
k represents register setting BCD value.  
2
2
2
1
2
t is clock period (1/Freq). For 104 MHz, t = 9.165 ns.  
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Figure 12 to Figure 15 provide few examples of basic EIM accesses to external memory devices with the  
timing parameters mentioned previously for specific control parameters settings.  
EIM_BCLK  
EIM_ADDRxx  
WE5  
WE7  
WE4  
WE6  
Address v1  
Last Valid Address  
WE6  
EIM_CSx_B  
EIM_WE_B  
EIM_LBA_B  
EIM_OE_B  
WE14  
WE15  
WE10  
WE12  
WE11  
WE13  
EIM_EBx_B  
WE18  
WE19  
D(v1)  
EIM_DATAxx  
Figure 12. Synchronous Memory Read Access, WSC=1  
EIM_BCLK  
WE4  
WE6  
WE5  
WE7  
WE9  
EIM_ADDRxx  
Last Valid Address  
Address V1  
EIM_CSx_B  
EIM_WE_B  
EIM_LBA_B  
EIM_OE_B  
WE8  
WE14  
WE15  
WE13  
WE17  
WE12  
WE16  
EIM_EBx_B  
EIM_DATAxx  
D(V1)  
Figure 13. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0  
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Electrical Characteristics  
EIM_BCLK  
WE16  
WE17  
WE5  
WE4  
Last Valid Address  
WE6  
EIM_ADDRxx/  
EIM_ADxx  
Write Data  
Address V1  
WE7  
WE9  
EIM_CSx_B  
EIM_WE_B  
WE8  
WE14  
WE15  
EIM_LBA_B  
EIM_OE_B  
WE10  
WE11  
EIM_EBx_B  
Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access,  
WSC=6,ADVA=0, ADVN=1, and ADH=1  
NOTE  
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the  
data bus.  
EIM_BCLK  
WE4  
WE5  
Address V1  
WE19  
WE18  
EIM_ADDRxx/  
EIM_ADxx  
Data  
Last Valid  
Address  
WE6  
EIM_CSx_B  
EIM_WE_B  
WE7  
WE15  
WE10  
WE14  
WE12  
EIM_LBA_B  
EIM_OE_B  
WE11  
WE13  
EIM_EBx_B  
Figure 15. 16-Bit Muxed A/D Mode, Synchronous Read Access,  
WSC=7, RADVN=1, ADH=1, OEA=0  
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4.9.3.4  
General EIM Timing-Asynchronous Mode  
Figure 16 through Figure 20 and Table 38 provide timing parameters relative to the chip select (CS) state  
for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing  
parameters mentioned above.  
Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through  
Figure 19 as RWSC, OEN & CSN is configured differently. See the i.MX 6Dual/6Quad reference manual  
(IMX6DQRM) for the EIM programming model.  
end of  
access  
start of  
access  
INT_CLK  
MAXCSO  
EIM_CSx_B  
WE31  
WE32  
EIM_ADDRxx/  
EIM_ADxx  
Next Address  
Last Valid Address  
Address V1  
EIM_WE_B  
EIM_LBA_B  
WE39  
WE40  
WE35  
WE37  
WE36  
WE38  
EIM_OE_B  
EIM_EBx_B  
WE44  
MAXCO  
EIM_DATA[07:00]  
D(V1)  
WE43  
MAXDI  
Figure 16. Asynchronous Memory Read Access (RWSC = 5)  
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end of  
access  
start of  
access  
INT_CLK  
MAXCSO  
EIM_CSx_B  
MAXDI  
WE31  
EIM_ADDRxx/  
EIM_ADxx  
D(V1)  
Addr. V1  
WE44  
WE32A  
WE40A  
WE35A  
EIM_WE_B  
EIM_LBA_B  
WE39  
WE37  
WE36  
WE38  
EIM_OE_B  
EIM_EBx_B  
MAXCO  
Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5)  
EIM_CSx_B  
WE31  
Last Valid Address  
WE32  
WE34  
WE40  
EIM_ADDRxx  
Next Address  
Address V1  
WE33  
EIM_WE_B  
EIM_LBA_B  
EIM_OE_B  
WE39  
WE45  
WE41  
WE46  
EIM_EBx_B  
WE42  
EIM_DATAxx  
D(V1)  
Figure 18. Asynchronous Memory Write Access  
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EIM_CSx_B  
WE41A  
WE31  
EIM_ADDRxx/  
EIM_DATAxx  
D(V1)  
Addr. V1  
WE32A  
WE42  
WE33  
WE39  
WE34  
EIM_WE_B  
WE40A  
EIM_LBA_B  
EIM_OE_B  
WE45  
WE46  
EIM_EBx_B  
Figure 19. Asynchronous A/D Muxed Write Access  
EIM_CSx_B  
EIM_ADDRxx  
WE31  
WE32  
Next Address  
Last Valid Address  
Address V1  
EIM_WE_B  
EIM_LBA_B  
EIM_OE_B  
EIM_EBx_B  
WE39  
WE35  
WE37  
WE40  
WE36  
WE38  
WE44  
D(V1)  
EIM_DATAxx[07:00]  
EIM_DTACK_B  
WE43  
WE48  
WE47  
Figure 20. DTACK Mode Read Access (DAP=0)  
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EIM_CSx_B  
WE31  
WE32  
WE34  
WE40  
EIM_ADDRxx  
Next Address  
Last Valid Address  
Address V1  
WE33  
EIM_WE_B  
EIM_LBA_B  
EIM_OE_B  
EIM_EBx_B  
WE39  
WE45  
WE41  
WE46  
WE42  
WE48  
D(V1)  
EIM_DATAxx  
EIM_DTACK_B  
WE47  
Figure 21. DTACK Mode Write Access (DAP=0)  
1 2  
,
Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select  
DeterminationbySynchronous  
Ref No.  
Parameter  
Min  
Max  
Unit  
measured parameters  
WE31 EIM_CSx_B valid to Address Valid  
WE4-WE6-CSA×t  
WE7-WE5-CSN× t  
-3.5-CSA×t  
-3.5-CSN×t  
3.5-CSA×t  
3.5-CSN×t  
ns  
ns  
WE32 Address Invalid to EIM_CSx_B  
Invalid  
WE32A EIM_CSx_B valid to Address  
(muxed Invalid  
A/D)  
t+WE4-WE7+  
(ADVN+ADVA+1-CSA)×t  
t - 3.5+(ADVN+A t + 3.5+(ADVN+ADVA+ ns  
DVA+1-CSA)×t 1-CSA)×t  
WE33 EIM_CSx_B Valid to EIM_WE_B  
Valid  
WE8-WE6+(WEA-WCSA)×t -3.5+(WEA-WCS 3.5+(WEA-WCSA)×t  
A)×t  
ns  
ns  
ns  
WE34 EIM_WE_B Invalid to EIM_CSx_B WE7-WE9+(WEN-WCSN)×t -3.5+(WEN-WCS 3.5+(WEN-WCSN)×t  
Invalid  
N)×t  
WE35 EIM_CSx_B Valid to EIM_OE_B  
Valid  
WE10- WE6+(OEA-RCSA)×t -3.5+(OEA-RCS 3.5+(OEA-RCSA)×t  
A)×t  
WE35A EIM_CSx_B Valid to EIM_OE_B WE10-WE6+(OEA+RADVN+R -3.5+(OEA+RAD 3.5+(OEA+RADVN+RA ns  
(muxed Valid  
A/D)  
ADVA+ADH+1-RCSA)×t  
VN+RADVA+ADH DVA+ADH+1-RCSA)×t  
+1-RCSA)×t  
WE36 EIM_OE_B Invalid to EIM_CSx_B WE7-WE11+(OEN-RCSN)×t -3.5+(OEN-RCS 3.5+(OEN-RCSN)×t  
Invalid N)×t  
ns  
WE37 EIM_CSx_B Valid to EIM_EBx_B WE12-WE6+(RBEA-RCSA)× t -3.5+(RBEA- RC 3.5+(RBEA - RCSA)×t ns  
Valid (Read access)  
SA)×t  
WE38 EIM_EBx_B Invalid to  
WE7-WE13+(RBEN-RCSN)×t  
-3.5+  
(RBEN-RCSN)×t  
3.5+(RBEN-RCSN)×t ns  
EIM_CSx_B Invalid (Read access)  
WE39 EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVA-CSA)×t  
-3.5+  
(ADVA-CSA)×t  
3.5+(ADVA-CSA)×t  
ns  
Valid  
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1 2  
,
Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select  
(continued)  
DeterminationbySynchronous  
Ref No.  
Parameter  
Min  
Max  
Unit  
measured parameters  
WE40 EIM_LBA_B Invalid to  
EIM_CSx_B Invalid (ADVL is  
asserted)  
WE7-WE15-CSN×t  
-3.5-CSN×t  
3.5-CSN×t  
ns  
WE40A EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVN+ADVA+1- -3.5+(ADVN+AD  
3.5+(ADVN+ADVA  
ns  
ns  
(muxed Invalid  
A/D)  
CSA)×t  
VA+1-CSA)×t  
+1-CSA)×t  
WE41 EIM_CSx_B Valid to Output Data  
Valid  
WE16-WE6-WCSA×t  
-3.5-WCSA×t  
3.5-WCSA×t  
WE41A EIM_CSx_B Valid to Output Data WE16-WE6+(WADVN+WADVA -3.5+(WADVN+ 3.5+(WADVN+WADVA ns  
(muxed Valid  
A/D)  
+ADH+1-WCSA)×t  
WADVA  
+ADH+1-WCSA)  
×t  
+ADH+1-WCSA)×t  
WE42 OutputData InvalidtoEIM_CSx_B  
Invalid  
WE17-WE7-CSN×t  
-3.5-CSN×t  
3.5-CSN×t  
ns  
ns  
MAXCO Output maximum delay from  
internal driving  
10  
10  
EIM_ADDRxx/control flip-flops to  
chip outputs.  
MAXCSO Output maximum delay from  
internal chip selects driving  
10  
5
10  
5
ns  
ns  
flip-flops to EIM_CSx_B out.  
MAXDI EIM_DATAxx MAXIMUM delay  
from chip input data to its internal  
flip-flop  
WE43 Input Data Valid to EIM_CSx_B  
Invalid  
MAXCO-MAXCSO+MAXDI MAXCO-MAXCS  
O+MAXDI  
ns  
ns  
WE44 EIM_CSx_B Invalid to Input Data  
Invalid  
0
0
WE45 EIM_CSx_B Valid to EIM_EBx_B WE12-WE6+(WBEA-WCSA)×t -3.5+(WBEA-WC 3.5+(WBEA-WCSA)×t ns  
Valid (Write access)  
SA)×t  
WE46 EIM_EBx_B Invalid to  
WE7-WE13+(WBEN-WCSN)×t -3.5+(WBEN-WC 3.5+(WBEN-WCSN)×t ns  
SN)×t  
EIM_CSx_B Invalid (Write access)  
MAXDTI Maximum delay from  
EIM_DTACK_B input to its internal  
10  
10  
ns  
flip-flop + 2 cycles for  
synchronization  
WE47 EIM_DTACK_B Active to  
EIM_CSx_B Invalid  
MAXCO-MAXCSO+MAXDTI MAXCO-MAXCS  
O+MAXDTI  
ns  
ns  
WE48 EIM_CSx_B Invalid to  
EIM_DTACK_B invalid  
0
0
1
For more information on configuration parameters mentioned in this table, see the i.MX 6Dual/6Quad reference manual  
(IMX6DQRM).  
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2
In this table:  
• t means clock period from axi_clk frequency.  
• CSA means register setting for WCSA when in write operations or RCSA when in read operations.  
• CSN means register setting for WCSN when in write operations or RCSN when in read operations.  
• ADVN means register setting for WADVN when in write operations or RADVN when in read operations.  
• ADVA means register setting for WADVA when in write operations or RADVA when in read operations.  
4.10 Multi-Mode DDR Controller (MMDC)  
The Multi-mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.  
4.10.1 MMDC Compatibility with JEDEC-Compliant SDRAMs  
The i.MX 6Dual/6Quad MMDC supports the following memory types:  
LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009  
DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008  
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to  
the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,  
6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).  
4.10.2 MMDC Supported DDR3/DDR3L/LPDDR2 Configurations  
The table below shows the supported DDR3/DDR3L/LPDDR2 configurations:  
Table 39. i.MX 6Dual/6Quad Supported DDR3/DDR3L/LPDDR2 Configurations  
Parameter  
LPDDR2  
DDR3  
DDR3L  
Clock frequency  
Bus width  
400 MHz  
32-bit per channel  
Dual  
532 MHz  
16/32/64-bit  
Single  
532 MHz  
16/32/64-bit  
Single  
Channel  
Chip selects  
2 per channel  
2
2
4.11 General-Purpose Media Interface (GPMI) Timing  
The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data  
width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source  
Synchronous timing mode, and Samsung Toggle timing mode separately described in the following  
subsections.  
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4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)  
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The  
Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 22 through Figure 25  
depict the relative timing between GPMI signals at the module level for different operations under  
Asynchronous mode. Table 40 describes the timing parameters (NF1–NF17) that are shown in the figures.  
NF2  
NF1  
.!.$?#,%  
NF3  
NF4  
.!.$?#%ꢀ?"  
.!.$?7%?"  
NF5  
.!.$?!,%  
NF6  
NF8  
Command  
NF7  
NF9  
.!.$?$!4!XX  
Figure 22. Command Latch Cycle Timing Diagram  
NF1  
.!.$?#,%  
NF3  
.!.$?#%ꢀ?"  
.!.$?7%?"  
NF10  
NF5  
NF11  
NF7  
.!.$?!,%  
NF6  
NF8  
Address  
NF9  
NAND_DATAxx  
Figure 23. Address Latch Cycle Timing Diagram  
NF1  
.!.$?#,%  
.!.$?#%ꢀ?"  
.!.$?7%?"  
NF3  
NF10  
NF5  
NF11  
NF7  
NF6  
.!.$?!,%  
NF8  
Data to NF  
NF9  
.!.$?$!4!XX  
Figure 24. Write Data Latch Cycle Timing Diagram  
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.!.$?#,%  
.!.$?#%ꢀ?"  
.!.$?2%?"  
NF14  
NF13  
NF15  
.!.$?2%!$9?"  
NF12  
NF16  
NF17  
Data from NF  
.!.$?$!4!XX  
Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)  
.!.$?#,%  
.!.$?#%ꢀ?"  
NF14  
NF13  
NF15  
.!.$?2%?"  
.!.$?2%!$9?"  
NF12  
NF17  
NF16  
NAND_DATAxx  
Data from NF  
Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode)  
1
Table 40. Asynchronous Mode Timing Parameters  
Timing  
T = GPMI Clock Cycle  
ID  
Parameter  
Symbol  
Unit  
Min  
(AS + DS) × T - 0.12 [see 2,3  
Max  
NF1  
NF2  
NF3  
NF4  
NF5  
NF6  
NF7  
NF8  
NF9  
NAND_CLE setup time  
NAND_CLE hold time  
NAND_CEx_B setup time  
NAND_CEx_B hold time  
NAND_WE_B pulse width  
NAND_ALE setup time  
NAND_ALE hold time  
Data setup time  
tCLS  
tCLH  
tCS  
]
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DH × T - 0.72 [see 2]  
(AS + DS + 1) × T [see 3,2  
(DH+1) × T - 1 [see 2]  
DS × T [see 2]  
]
tCH  
tWP  
tALS  
tALH  
tDS  
(AS + DS) × T - 0.49 [see 3,2  
(DH × T - 0.42 [see 2]  
DS × T - 0.26 [see 2]  
DH × T - 1.37 [see 2]  
(DS + DH) × T [see 2]  
DH × T [see 2]  
]
Data hold time  
tDH  
NF10 Write cycle time  
tWC  
tWH  
tRR4  
tRP  
NF11 NAND_WE_B hold time  
NF12 Ready to NAND_RE_B low  
NF13 NAND_RE_B pulse width  
NF14 READ cycle time  
(AS + 2) × T [see 3,2  
]
DS × T [see 2]  
(DS + DH) × T [see 2]  
DH × T [see 2]  
tRC  
NF15 NAND_RE_B high hold time  
tREH  
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Table 40. Asynchronous Mode Timing Parameters (continued)  
Timing  
T = GPMI Clock Cycle  
ID  
Parameter  
Symbol  
Unit  
Min  
Max  
NF16 Data setup on read  
NF17 Data hold on read  
tDSR  
tDHR  
(DS × T -0.67)/18.38 [see 5,6  
]
ns  
ns  
0.82/11.83 [see 5,6  
]
1
The GPMI asynchronous mode output timing can be controlled by the module’s internal registers  
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.  
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.  
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.  
T = GPMI clock period -0.075ns (half of maximum p-p jitter).  
NF12 is met automatically by the design.  
Non-EDO mode.  
EDO mode, GPMI clock 100 MHz  
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).  
In EDO mode (Figure 26), NF16/NF17 are different from the definition in non-EDO mode (Figure 25).  
They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The  
typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO  
mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an  
internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter  
of the i.MX 6Dual/6Quad reference manual (IMX6DQRM)). The typical value of this control register is  
0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay  
value should be made larger to compensate the board delay.  
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4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)  
Figure 27 shows the write and read timing of Source Synchronous mode.  
NF19  
NF18  
.!.$?#%?"  
NF23  
NAND_CLE  
NF26  
NF25  
NF24  
NAND_ALE  
NF25 NF26  
NAND_WE/RE_B  
NF22  
NAND_CLK  
NAND_DQS  
NAND_DQS  
Output enable  
NF20  
NF20  
NF21  
NF21  
CMD  
ADD  
NAND_DATA[7:0]  
NAND_DATA[7:0]  
Output enable  
Figure 27. Source Synchronous Mode Command and Address Timing Diagram  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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64  
Electrical Characteristics  
NF19  
NF18  
.!.$?#%ꢀ?"  
.!.$?#,%  
NF23  
NF23  
NF24  
NF24  
NF25  
NF25  
NF26  
NF26  
.!.$?!,%  
NAND_WE/RE_B  
NF22  
.!.$?#,+  
.!.$?$13  
NF27  
NF27  
.!.$?$13  
Output enable  
NF29  
NF29  
.!.$?$1;ꢁꢂꢀ=  
NF28  
NF28  
.!.$?$1;ꢁꢂꢀ=  
Output enable  
Figure 28. Source Synchronous Mode Data Write Timing Diagram  
NF18  
NF19  
.!.$?#%?"  
.!.$?#,%  
NF24  
NF24  
NF23  
NF23  
NF26  
NF26  
NF25  
NF25  
NAND_ALE  
NF25  
.!.$?7%ꢃ2%  
NF25  
NF22  
NF26  
.!.$?#,+  
.!.$?$13  
.!.$?$13  
/UTPUT ENABLE  
.!.$?$!4!;ꢁꢂꢀ=  
.!.$?$!4!;ꢁꢂꢀ=  
/UTPUT ENABLE  
Figure 29. Source Synchronous Mode Data Read Timing Diagram  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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Electrical Characteristics  
.!.$?$13  
NF30  
.!.$?$!4!;ꢁꢂꢀ=  
D0  
D1  
D2  
D3  
NF30  
NF31  
NF31  
Figure 30. NAND_DQS/NAND_DQ Read Valid Window  
1
Table 41. Source Synchronous Mode Timing Parameters  
Timing  
T = GPMI Clock Cycle  
ID  
Parameter  
Symbol  
Unit  
Min  
Max  
2
NF18 NAND_CEx_B access time  
tCE  
tCH  
CE_DELAY × T - 0.79 [see ]  
0.5 × tCK - 0.63 [see 2]  
0.5 × tCK - 0.05  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
NF19 NAND_CEx_B hold time  
NF20 Command/address NAND_DATAxx setup time  
NF21 Command/address NAND_DATAxx hold time  
NF22 clock period  
tCAS  
tCAH  
tCK  
0.5 × tCK - 1.23  
NF23 preamble delay  
tPRE  
tPOST  
tCALS  
tCALH  
tDQSS  
tDS  
PRE_DELAY × T - 0.29 [see 2]  
POST_DELAY × T - 0.78 [see 2]  
0.5 × tCK - 0.86  
NF24 postamble delay  
NF25 NAND_CLE and NAND_ALE setup time  
NF26 NAND_CLE and NAND_ALE hold time  
NF27 NAND_CLK to first NAND_DQS latching transition  
NF28 Data write setup  
0.5 × tCK - 0.37  
T - 0.41 [see 2]  
0.25 × tCK - 0.35  
NF29 Data write hold  
tDH  
0.25 × tCK - 0.85  
NF30 NAND_DQS/NAND_DQ read setup skew  
tDQSQ  
tQHS  
2.06  
1.95  
NF31 NAND_DQS/NAND_DQ read hold skew  
1
2
The GPMI source synchronous mode output timing can be controlled by the module’s internal registers  
GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends  
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.  
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).  
Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source  
Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200MB/s.  
GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,  
which can be provided by an internal DPLL. The delay value can be controlled by GPMI register  
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX  
6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value of this register is equal  
to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot  
be ignored, the delay value should be made larger to compensate the board delay.  
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Electrical Characteristics  
4.11.3 Samsung Toggle Mode AC Timing  
4.11.3.1 Command and Address Timing  
Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC  
timing. See Section 4.11.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” for details.  
4.11.3.2 Read and Write Timing  
DEV?CLK  
.!.$?#%X?"  
.!.$?#,%  
.!.$?!,%  
.!.$?7%?"  
.!.$?2%?"  
.&ꢇꢉ  
.&ꢇꢈ  
.!.$?$13  
ꢀꢅꢆ T#+  
ꢀꢅꢆ T#+  
.!.$?$!4!;ꢁꢂꢀ=  
Figure 31. Samsung Toggle Mode Data Write Timing  
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018  
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67  
Electrical Characteristics  
DEV?CLK  
.!.$?#%X?"  
.& ꢄꢊ  
.!.$?#,%  
.!.$?!,%  
ꢄ T #+  
.&ꢇꢉ  
.!.$?7%?"  
.!.$?2%?"  
ꢄ T #+  
.& ꢇꢈ  
ꢄ T #+  
ꢄ T #+  
ꢄ T #+  
.!.$?$13  
.!.$?$!4!;ꢁꢂꢀ=  
Figure 32. Samsung Toggle Mode Data Read Timing  
1
Table 42. Samsung Toggle Mode Timing Parameters  
Timing  
T = GPMI Clock Cycle  
Min  
ID  
Parameter  
Symbol  
Unit  
Max  
NF1 NAND_CLE setup time  
NF2 NAND_CLE hold time  
NF3 NAND_CEx_B setup time  
NF4 NAND_CEx_B hold time  
NF5 NAND_WE_B pulse width  
NF6 NAND_ALE setup time  
NF7 NAND_ALE hold time  
tCLS  
tCLH  
tCS  
(AS + DS) × T - 0.12 [see 2,3  
DH × T - 0.72 [see 2]  
(AS + DS) × T - 0.58 [see 3,2  
DH × T - 1 [see 2]  
]
ns  
ns  
ns  
ns  
]
tCH  
tWP  
tALS  
tALH  
DS × T [see 2]  
(AS + DS) × T - 0.49 [see 3,2  
DH × T - 0.42 [see 2]  
DS × T - 0.26 [see 2]  
DH × T - 1.37 [see 2]  
]
NF8 Command/address NAND_DATAxx setup time tCAS  
NF9 Command/address NAND_DATAxx hold time  
NF18 NAND_CEx_B