MCIMX6Y2DVM09AB [NXP]
i.MX 6ULL;型号: | MCIMX6Y2DVM09AB |
厂家: | NXP |
描述: | i.MX 6ULL |
文件: | 总139页 (文件大小:2236K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: IMX6ULLCEC
Rev. 1.2, 11/2017
NXP Semiconductors
Data Sheet: Technical Data
MCIMX6Y0DVM05AA MCIMX6Y0DVM05AB
MCIMX6Y1DVM05AA MCIMX6Y1DVM05AB
MCIMX6Y1DVK05AA MCIMX6Y1DVK05AB
MCIMX6Y2DVM05AA MCIMX6Y2DVM05AB
MCIMX6Y2DVM09AA MCIMX6Y2DVM09AB
MCIMX6Y7DVM09AA MCIMX6Y7DVM09AB
MCIMX6Y7DVK05AA MCIMX6Y7DVK05AB
MCIMX6Y2DVK09AB
i.MX 6ULL Applications
Processors for Consumer
Products
Package Information
Plastic Package
MAPBGA 14 x 14 mm, 0.8 mm pitch
MAPBGA 9 x 9 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
1. i.MX 6ULL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 18
3.2. Recommended Connections for Unused Analog
1 i.MX 6ULL Introduction
The i.MX 6ULL processors represent NXP’s latest
achievement in integrated multimedia-focused products
offering high performance processing with a high degree
of functional integration, targeted towards the growing
market of connected devices.
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21
4.2. Power Supplies Requirements and Restrictions . 31
4.3. Integrated LDO Voltage Regulator Parameters . . 32
4.4. PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 34
4.5. On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . 35
4.6. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.7. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 40
4.8. Output Buffer Impedance Parameters . . . . . . . . . 43
4.9. System Modules Timing . . . . . . . . . . . . . . . . . . . . 45
4.10. Multi-Mode DDR Controller (MMDC) . . . . . . . . . . 57
4.11. General-Purpose Media Interface (GPMI) Timing 58
4.12. External Peripheral Interface Parameters . . . . . . . 66
4.13. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 103
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 103
5.2. Boot Device Interface Allocation . . . . . . . . . . . . . 104
6. Package Information and Contact Assignments . . . . . 111
6.1. 14 x 14 mm Package Information . . . . . . . . . . . . 111
6.2. 9 x 9 mm Package Information . . . . . . . . . . . . . . 124
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
The i.MX 6ULL is a high performance, ultra efficient
processor family with featuring NXP’s advanced
®
implementation of the single Arm Cortex -A7 core,
which operates at speeds of up to 900 MHz. i.MX 6ULL
includes integrated power management module that
reduces the complexity of external power supply and
simplifies the power sequencing. Each processor in this
family provides various memory interfaces, including
LPDDR2, DDR3, DDR3L, Raw and Managed NAND
flash, NOR flash, eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors.
© 2016-2017 NXP B.V.
i.MX 6ULL Introduction
The i.MX 6ULL processors are specifically useful for applications such as:
•
•
•
•
•
•
•
•
•
•
Telematics
Audio playback
Connected devices
IoT Gateway
Access control panels
Human Machine Interfaces (HMI)
Portable medical and health care
IP phones
Smart appliances
eReaders
The features of the i.MX 6ULL processors include:
•
Single-core Arm Cortex-A7—The single core A7 provides a cost-effective and power-efficient
solution.
•
Multilevel memory system—The multilevel memory system of processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, NAND Flash (MLC and SLC), OneNAND™, Quad SPI, and managed NAND, including
eMMC up to rev 4.4/4.41/4.5.
•
Smart speed technology—Power management implemented throughout the IC that enables
multimedia features and peripherals to consume minimum power in both active and various low
power modes.
•
•
Dynamic voltage and frequency scaling—The power efficiency of devices by scaling the voltage
and frequency to optimize performance.
Multimedia powerhouse—The multimedia performance of processor is enhanced by a multilevel
cache system, NEON™ MPE (Media Processor Engine) co-processor, a programmable smart
DMA (SDMA) controller, an asynchronous audio sample rate converter, an Electrophoretic
Display (EPD) controller, and a Pixel processing pipeline (PXP) to support 2D image processing,
including color-space conversion, scaling, alpha-blending, and rotation.
•
•
•
2x Ethernet interfaces—2x 10/100 Mbps Ethernet controllers.
Human-machine interface—Each processor supports one digital parallel display interface.
Interface flexibility—Each processor supports connections to a variety of interfaces: two
high-speed USB on-the-go with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), two 12-bit ADC modules with up to 10 total input channels and two CAN ports.
•
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, AES-128
encryption, SHA-1, SHA-256 HW acceleration engine, and secure software downloads. The
security features are discussed in the i.MX 6ULL Security Reference Manual (IMX6ULLSRM).
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
•
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
For a comprehensive list of the i.MX 6ULL features, see Section 1.2, “Features"”.
1.1
Ordering Information
Table 1 provides examples of orderable part numbers covered by this data sheet.
Table 1. Ordering Information
Junction
Temperature Tj
(C)
Part Number
Feature
Package
MCIMX6Y0DVM05AA
MCIMX6Y0DVM05AB
Features supports:
• 528 MHz, commercial grade for general purpose MAPBGA
14 x 14 mm, 0.8 pitch
0 to +95
• No security
• No LCD/CSI
• No CAN
• Ethernet x1
• USB OTG x1
• ADC x1
• UART x4
• SAI x1
• No ESAI
• Timer x2
• PWM x4
• I2C x2
• SPI x2
MCIMX6Y1DVM05AA
MCIMX6Y1DVM05AB
Features supports:
• 528 MHz, commercial grade for general purpose MAPBGA
14 x 14 mm, 0.8 pitch
0 to +95
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
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3
i.MX 6ULL Introduction
Part Number
Table 1. Ordering Information
Feature
Junction
Temperature Tj
(C)
Package
MCIMX6Y2DVM05AA
MCIMX6Y2DVM05AB
Features supports:
• 528 MHz, commercial grade for general purpose MAPBGA
14 x 14 mm, 0.8 pitch
0 to +95
0 to +95
0 to +95
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
MCIMX6Y1DVK05AA
MCIMX6Y1DVK05AB
Features supports:
• 528 MHz, commercial grade for general purpose MAPBGA
9 x 9 mm, 0.5 pitch
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
MCIMX6Y7DVK05AA
MCIMX6Y7DVK05AB
Features supports:
• 528 MHz, commercial grade for general purpose MAPBGA
9 x 9 mm, 0.5 pitch
• Basic security
• With LCD/CSI
• EPDC
• No CAN
• Ethernet x1
• USB OTG x2
• ADC x2
• UART x4
• SAI x3
• ESAI x1
• Timer x4
• PWM x4
• I2C x4
• SPI x4
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NXP Semiconductors
i.MX 6ULL Introduction
Table 1. Ordering Information
Feature
Junction
Temperature Tj
(C)
Part Number
Package
MCIMX6Y2DVK09AB
Features supports:
9 x 9 mm, 0.5 pitch
0 to +95
• 900 MHz, commercial grade for general purpose MAPBGA
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
MCIMX6Y2DVM09AB
MCIMX6Y2DVM09AB
Features supports:
• 900 MHz, commercial grade for general purpose MAPBGA
14 x 14mm, 0.8 pitch
0 to +95
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
MCIMX6Y7DVM09AA
MCIMX6Y7DVM09AB
Features supports:
• 900 MHz, commercial grade for general purpose MAPBGA
14 x 14mm, 0.8 pitch
0 to +95
• Basic security
• With LCD/CSI
• EPDC
• No CAN
• Ethernet x1
• USB OTG x2
• ADC x2
• UART x4
• SAI x3
• ESAI x1
• Timer x4
• PWM x4
• I2C x4
• SPI x4
Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
5
i.MX 6ULL Introduction
revision). The primary characteristic which describes which data sheet applies to a specific part is the
temperature grade (junction) field.
•
The i.MX 6ULL Applications Processors for Consumer Products Data Sheet (IMX6ULLCEC)
covers parts listed with a “D (Commercial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there will be any questions, visit the web page
NXP.com/imx6series or contact a NXP representative for details.
MC
IMX6
X
@
+
VV $$
%
A
Silicon Rev
A
A
B
Qualification Level
MC
Rev 1.0 (Mask number: 0N70S)
Rev 1.1 (Mask number: 1N70S)
Prototype Samples
Mass Production
Special
PC
MC
SC
Fuse Option
%
i.MX 6 Family
X
Reserved
A
i.MX 6ULL
Y
Arm Cortex-A7 Frequency
$$
05
08
09
@
Part differentiator
With EPDC
528 MHz
792 MHz
900 MHz
7
6
5
4
3
2
1
0
Reserved
ROHS
VM
Package Type
General Purpose 2 (Full Feature)
General Purpose 1 (Reduced Feature)
Baseline
MAPBGA 14 x 14 mm, 0.8 pitch
MAPBGA 9 x 9 mm, 0.5 pitch
VK
Junction Temperature (Tj)
+
D
C
Consumer: 0 to + 95 °C
Industrial: -40 to +105 °C
Figure 1. Part Number Nomenclature—i.MX 6ULL
1.2
Features
The i.MX 6ULL processors are based on Arm Cortex-A7 MPCore™ Platform, which has the following
features:
•
Supports single Arm Cortex-A7 MPCore (with TrustZone) with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Private Timer and Watchdog
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
— Cortex-A7 NEON Media Processing Engine (MPE) Co-processor
General Interrupt Controller (GIC) with 128 interrupts support
Global Timer
•
•
•
•
•
•
Snoop Control Unit (SCU)
128 KB unified I/D L2 cache
Single Master AXI bus interface output of L2 cache
Frequency of the core (including Neon and L1 cache), as per Table 10, "Operating Ranges," on
page 24.
•
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
— 32 double-precision VFPv3 floating point registers
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia/shared, fast access RAM (OCRAM, 128 KB)
•
External memory interfaces: The i.MX 6ULL processors support latest, high volume, cost effective
handheld DRAM, NOR, and NAND Flash memory standards.
— 16-bit LP-DDR2-800, 16-bit DDR3-800 and DDR3L-800
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits.
— 16/8-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 6ULL processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
•
Displays:
— One parallel display port, support max 85 MHz display clock and up to WXGA (1366 x 768)
at 60 Hz
— Support 24-bit, 18-bit, 16-bit, and 8-bit parallel display
— Electrophoretic display controller support direct-driver for E-Ink EPD panel, with up to
2048x1536 resolution at 106 Hz
•
•
Camera sensors:
— One parallel camera port, up to 24 bit and 133.3 MHz pixel clock
— Support 24-bit, 16-bit, 10-bit, and 8-bit input
— Support BT.656 interface
Expansion cards:
— Two MMC/SD/SDIO card ports all supporting:
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
7
i.MX 6ULL Introduction
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
•
•
USB:
— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
Miscellaneous IPs and interfaces:
— Three I2S/SAI/AC97, up to 1.4 Mbps each
— ESAI
— Sony Philips Digital Interface Format (SPDIF), Rx and Tx
— Eight UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– Support RTS/CTS for hardware flow control
— Four eCSPI (Enhanced CSPI), up to 52 Mbps each
2
— Four I C, supports 400 kbps
— Two 10/100 Ethernet Controller (IEEE1588 compliant)
— Eight Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— One Quad SPI to connect to serial NOR flash
— Two Flexible Controller Area Network (FlexCAN)
— Three Watchdog timers (WDOG)
— 8-bit/10-bit/12-bit/16-bit camera interface
— Two 12-bit Analog to Digital Converters (ADC) with up to 10 input channels in total
The i.MX 6ULL processors integrate advanced power management unit and controllers:
•
•
•
•
•
•
•
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Use Voltage Sensor for monitoring the die voltage
Support DVFS techniques for low power modes
Use SW State Retention and Power Gating for Arm and NEON
Support various levels of system power modes
Use flexible clock gating control scheme
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
The i.MX 6ULL processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6ULL processors incorporate the following hardware accelerators:
•
PXP—Pixel Processing Pipeline for image resize, rotation, overlay and CSC. Off loading key pixel
processing operations are required to support the LCD display applications.
•
ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
•
•
Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
•
•
•
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock, both active tamper and
passive tamper detection logic has up to 10 tamper inputs. Voltage monitor, temperature monitor,
and clock frequency monitor protects the secure key storage.
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
AES-128 encryption, SHA-1, and SHA-256 HW acceleration engine, 2048-bit RSA key, version
control mechanism, warm boot, CSU, and TZ initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions, such as display and camera interfaces, connectivity interfaces.
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
9
Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX 6ULL processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6ULL processor system.
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Figure 2. i.MX 6ULL System Block Diagram
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
10
NXP Semiconductors
Modules List
3 Modules List
The i.MX 6ULL processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6ULL Modules List
Block Mnemonic
Block Name
Subsystem
Brief Description
ADC1
ADC2
Analog to Digital
Converter
—
The ADC is a 12-bit general purpose analog to digital
converter.
Arm
Arm Platform
Arm
The Arm Core Platform includes 1x Cortex-A7 core. It
also includes associated sub-blocks, such as the Level
2 Cache Controller, SCU (Snoop Control Unit), GIC
(General Interrupt Controller), private timers, watchdog,
and CoreSight debug modules.
ASRC
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC)
converts the sampling rate of a signal associated to an
input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about -120dB
THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling
rates. The ASRC supports up to three sampling rate
pairs.
BCH
Binary-BCH ECC
Processor
System Control
Peripherals
The BCH module provides up to 40-bit ECC
encryption/decryption for NAND Flash controller
(GPMI)
CCM
GPC
SRC
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
GeneralPowerController,
System Reset Controller
Power Control
distribution in the system, and also for the system power
management.
CSI
Parallel CSI
Multimedia
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU
DAP
Central Security Unit
Debug Access Port
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
6ULL platform.
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A7
Core Platform.
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
11
Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCP
Data co-processor
Security
This module provides support for general encryption
and hashing functions typically used for security
functions. Because its basic job is moving data from
memory to memory, it also incorporates a memory-copy
(memcopy) function for both debugging and as a more
efficient method of copying data between memory
blocks than the DMA-based approach.
eCSPI1
eCSPI2
eCSPI3
eCSPI4
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM
memories (sync and async operating modes), at
slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash
memories, at slow frequency
• Multiple chip selects
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EPDC
Electrophoretic Display
Controller
Multimedia
Peripherals
The EPDC is a feature-rich, low power, and high
performance direct-drive active matrix EPD controller. It
is specially designed to drive E-INKTM EPD panels,
supporting a wide variety of TFT backplanes.
EPIT1
EPIT2
Enhanced Periodic
Interrupt Timer
Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler for division of input clock frequency to
get the required time setting for the interrupts to occur,
and counter value can be programmed on the fly.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ESAI
Enhanced Serial Audio
Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and
receiver sections, each section with its own clock
generator. All serial transfers are synchronized to a
clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one
word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words
(time slots) per period. This mode can be used to build
time division multiplexed (TDM) networks. In contrast,
the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high
speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection
to external devices.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
GPMI
General Purpose
Memory Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices and
40-bit ECC encryption/decryption for NAND Flash
Controller (GPMI2). GPMI supports separate DMA
channels for each NAND device.
GPT1
GPT2
General Purpose Timer
Timer peripherals Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
LCDIF
LCD interface
Connectivity
peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capability. The LCDIF is designed to support dumb
(synchronous 24-bit Parallel RGB interface) and smart
(asynchronous parallel MPU interface) LCD devices.
MQS
Medium Quality Sound
Pulse Width Modulation
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
Connectivity
peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
PXP
Pixel Processing Pipeline Display peripherals A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications, allowing it to interface with the integrated
EPD.
RNGB
QSPI
Random Number
Generator
Security
Random number generating module.
Quad SPI
Connectivity
peripherals
Quad SPI module acts as an interface to external serial
flash devices. This module contains the following
features:
• Flexible sequence engine to support various flash
vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of
operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash
devices
• Multi-master access with priority and flexible and
configurable buffer for each master
SAI1
SAI2
SAI3
—
—
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
The SDMA is multi-channel flexible DMA engine. It
helps in maximizing system performance by off-loading
the various cores in dynamic data routing. It has the
following features:
SDMA
Smart Direct Memory
Access
System Control
Peripherals
• Powered by a 16-bit Instruction-Set micro-RISC
engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any
combination of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority
based preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unit-directional and
bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX 6ULL
processors use JTAG port for production, testing, and
system debugging. In addition, the SJC provides BSR
(Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6ULL SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
SPDIF
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
System Counter
—
—
The system counter module is a programmable system
counter which provides a shared time base to the
Cortex A series cores as part of Arm’s generic timer
architecture. It is intended for use in application where
the counter is always powered on and supports
multiple, unrelated clocks.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
TSC
Touch Screen
Touch Controller
With touch controller to support 4-wire and 5-wire
resistive touch panel.
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by Arm) provides security
address region control functions required for intended
application. It is used on the path to the DRAM
controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART Interface
Connectivity
Peripherals
Each of the UARTv2 module supports the following
serial data transmit/receive protocols and
configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card/SecureDigital Host
Controller
Connectivity
Peripherals
i.MX 6ULL specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card
System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
However, the SoC level integration and I/O muxing logic
restrict the functionality to the following:
• Instances #1 and #2 are primarily intended to serve
as interfaces to on-board peripherals. These ports
are equipped with “Card detection” and “Write
Protection” pads and do not support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There
are two completely independent I/O power domains
for Ports #1 and #2 in four bit configuration (SD
interface).
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Universal Serial Bus 2.0
Subsystem
Brief Description
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
USB
Connectivity
Peripherals
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
WDOG1
WDOG3
Watch Dog
Timer Peripherals The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the Arm
core, and a second point evokes an external event on
the WDOG line.
WDOG2
(TZ)
Watch Dog (TrustZone)
Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such
situation is undesirable as it can compromise the
system’s security. Once the TZ WDOG module is
activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer
times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode.
If it is still not served, the TZ WDOG asserts a security
violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal
mode SW.
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17
Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6ULL processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments".” Signal descriptions are provided in the i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX 6ULL Reference Manual (IMX6ULLRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused, either or both of
the CLK1_N/P pairs may remain unconnected.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should
be remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical
conditions.
In case when high accuracy real time clock are not required, system may use internal low
frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO
unconnected.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80 is recommended. NXP BSP (board support package) software requires
24 MHz on XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI is not connected.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
DRAM_VREF
When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the
NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a
1 k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a
closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the 2% DDR_VREF tolerance (per the DDR3 specification) is
maintained when two DDR3 ICs plus the i.MX 6ULL are drawing current on the resistor divider.
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Modules List
Table 3. Special Signal Considerations (continued)
Remarks
Signal Name
ZQPAD
DRAM calibration resistor 240 1% used as reference during DRAM output buffer driver
calibration should be connected between this pad and GND.
GPANAIO
This signal is reserved for NXP manufacturing use only. This output must remain unconnected.
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated
if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX 6ULL reference manual. Both names refer to
the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC
These signals are No Connect (NC) and should be disconnected by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the
debounce time, the power off interrupt is generated. Off to on time supports the time it takes to
request power on after a configured button press time has been reached. While in the OFF state,
if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.
Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration
supports the time it takes to request power down after ONOFF button has been pressed for the
defined time.
TEST_MODE
TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
Table 4. JTAG Controller Interface Summary
JTAG
I/O Type
On-chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
47 kpull-up
47 kpull-up
47 kpull-up
Keeper
Input
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
47 kpull-up
100 kpull-up
Input
3.2
Recommended Connections for Unused Analog Interfaces
Table 5 shows the recommended connections for unused analog interfaces.
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Modules List
Module
Table 5. Recommended Connections for Unused Analog Interfaces
Pad Name
Recommendations
if Unused
CCM
USB
CCM_CLK1_N, CCM_CLK1_P
Not connect
Not connect
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS,
USB_OTG2_DN, USB_OTG2_DP, USB_OTG2_VBUS
ADC
ADC_VREFH
Tie to
VDDA_ADC_3P3
VDDA_ADC_3P3
VDDA_ADC_3P3
must be powered
even if the ADC is
not used.
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Electrical Characteristics
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6ULL processors.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX 6ULL Chip-Level Conditions
For these characteristics
Topic appears
Absolute Maximum Ratings
Thermal Resistance
Operating Ranges
on page 22
on page 22
on page 24
on page 26
on page 27
on page 28
on page 31
External Clock Sources
Maximum Supply Currents
Power Modes
USB PHY Current Consumption
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Electrical Characteristics
4.1.1
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
Core Supply Voltage
VDDSOC_IN
-0.3
-0.3
1.6
1.4
V
V
Internal Supply Voltage
VDDARM_CAP
VDDSOC_CAP
GPIO Supply Voltage
NVCC_CSI
NVCC_ENET
NVCC_GPIO
NVCC_UART
NVCC_LCD
NVCC_NAND
NVCC_SD1
-0.5
3.7
V
DDR IO Supply Voltage
VDD_SNVS_IN Supply Voltage
VDDHIGH_IN Supply voltage
USB VBUS
NVCC_DRAM
VDD_SNVS_IN
VDD_HIGH_IN
-0.4
-0.3
-0.3
—
1.9751
3.6
V
V
V
V
3.7
USB_OTG1_VBUS
USB_OTG2_VBUS
5.5
Input voltage on USB_OTG_DP and
USB_OTG_DN pins
USB_OTG1_DP/USB_OTG1_DN
USB_OTG2_DP/USB_OTG2_DN
-0.3
-0.5
3.63
V
V
Input/Output Voltage Range
ESD damage Immunity:
Vin/Vout
Vesd
OVDD+0.32
Human Body Model (HBM)
Charge Device Model (CDM)
—
—
2000
500
V
Storage Temperature Range
TSTORAGE
-40
150
o C
1
The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575 V.
2
OVDD is the I/O supply voltage.
4.1.2
Thermal Resistance
4.1.2.1
14 x 14 mm (VM) Package Thermal Resistance
Table 8 displays the 14 x 14 mm (VM) package thermal resistance data.
Table 8. 14 x 14 (VM) Thermal Resistance Data
Rating
Test Conditions
Single-layer board (1s)
Symbol
Value
Unit
Notes
1,2
Junction to Ambient
Natural convection
RJA
58.4
oC/W
1,2,3
Junction to Ambient
Natural convection
Four-layer board (2s2p)
RJA
37.6
oC/W
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Electrical Characteristics
Table 8. 14 x 14 (VM) Thermal Resistance Data (continued)
Rating
Test Conditions
Symbol
Value
Unit
Notes
1,3
Junction to Ambient (@200 Single layer board (1s)
ft/min)
RJMA
48.6
oC/W
1,3
Junction to Ambient (@200 Four layer board (2s2p)
ft/min)
RJMA
32.9
oC/W
4
5
6
7
Junction to Board
—
RJB
RJC
JT
21.8
19.3
2.3
oC/W
oC/W
oC/W
oC/W
Junction to Case
—
Junction to Package Top
Natural Convection
Junction to Package Bottom Natural Convection
JB
12.0
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
7
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JB
4.1.2.2
9 x 9 MM (VK) Package Thermal Resistance
Table 9 displays the 9 x 9 MM (VK) thermal resistance data.
Table 9. 9 x 9 MM (VK) Thermal Resistance Data
Rating
Test Conditions
Single-layer board (1s)
Symbol
Value
Unit
Notes
1,2
Junction to Ambient
Natural Convection
RJA
65.6
oC/W
1,2,3
1,3
Junction to Ambient
Natural Convection
Four-layer board (2s2p)
RJA
RJMA
RJMA
36.2
51.2
31.8
oC/W
oC/W
oC/W
Junction to Ambient (@200 Single layer board (1s)
ft/min)
1,3
Junction to Ambient (@200 Four layer board (2s2p)
ft/min)
4
5
6
7
Junction to Board
—
RJB
RJC
17.1
14.5
0.6
oC/W
oC/W
oC/W
oC/W
Junction to Case
—
Junction to Package Top
Natural Convection
JT
Junction to Package Bottom Natural Convection
JB_CSB
11.1
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Electrical Characteristics
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistances between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
7
Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
4.1.3
Operating Ranges
Table 10 provides the operating ranges of the i.MX 6ULL processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6ULL Reference Manual
(IMX6ULLRM).
Table 10. Operating Ranges
Parameter
Description
Operating
Conditions
Symbol
Min
Typ Max1 Unit
Comment
Run Mode: LDO
Enabled
VDD_SOC_IN
A7 core at 900 1.375
MHz
—
—
1.5
1.5
V
V
VDD_SOC_IN must be 125 mV
higher than the LDO Output Set
Point (VDD_ARM_CAP and
VDD_SOC_CAP) for correct
supply voltage regulation.
A7 core at 528 1.275
MHz and below
VDD_ARM_CAP
A7 core at 900
MHz
1.25 1.275 1.3
—
A7 core at 528
MHz
1.15
1.00
—
—
—
1.3
1.3
1.3
A7 core at 396
MHz
A7 core at 198 0.925
MHz
VDD_SOC_CAP
VDD_SOC_IN
—
1.15
1.15
—
—
1.3
1.3
V
V
—
Run Mode: LDO
Bypassed
A7 core
operationsat528
MHz or below.
A7 core operation above 528 MHz
is not supported when LDO is
bypassed.
Low Power Run
Mode: LDO
Enabled
VDD_SOC_IN
—
1.275
—
1.5
V
VDD_SOC_IN must be 125 mV
higher than the LDO Output Set
Point (VDD_ARM_CAP and
VDD_SOC_CAP) for correct
supply voltage regulation.
VDD_SOC_CAP
VDD_ARM_CAP
All PLL
bypassed, all
clocks running at
24 MHz or below.
0.925
0.925
—
—
1.3
1.3
V
V
—
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Table 10. Operating Ranges (continued)
Low Power Run
Mode: LDO
Bypassed
VDD_SOC_IN
All PLL
bypassed, all
clocks running at
24 MHz or below.
0.925
—
1.3
V
—
SUSPEND (DSM)
Mode
VDD_SOC_IN
VDD_HIGH_IN
VDD_SNVS_IN2
—
—
—
0.9
—
—
—
1.3
3.6
3.6
V
V
V
Refer to Table 15 Low Power Mode
Current and Power Consumption
on page -29
VDD_HIGH
internal regulator
2.80
2.40
Must match the range of voltages
that the rechargeable backup
battery supports.
Backup battery
supply range
Can be combined with
VDDHIGH_IN, if the system does
not require keeping real time and
other data on OFF state.
USB supply
voltages
USB_OTG1_VBUS
USB_OTG2_VBUS
NVCC_DRAM
—
—
4.40
4.40
1.14
—
—
5.5
5.5
1.3
V
V
V
V
V
V
V
—
—
—
—
—
—
DDR I/O supply
LPDDR2
DDR3L
DDR3
—
1.2
1.28 1.35 1.45
1.43
2.25
1.65
1.5 1.575
NVCC_DRAM2P5
NVCC_CSI
2.5
2.75
3.6
GPIO supplies
—
1.8,
2.8,
3.3
All digital I/O supplies
(NVCC_xxxx) must be powered
(unless otherwise specified in this
data sheet) under normal
conditions whether the associated
I/O pins are in use or not.
NVCC_ENET
NVCC_GPIO
NVCC_UART
NVCC_LCD
NVCC_NAND
NVCC_SD1
A/D converter
VDDA_ADC_3P3
—
3.0
3.15
3.6
V
VDDA_ADC_3P3 must be
powered when chip is in RUN
mode, IDLE mode, or SUSPEND
mode.
VDDA_ADC_3P3 should not be
powered when chip is in SNVS
mode.
Temperature Operating Ranges
Junction
temperature
TJ
Standard
Commercial
0
—
95
oC See i.MX 6ULL Product Lifetime
Usage Estimates for information on
product lifetime (power-on years)
for this processor.
1
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
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Electrical Characteristics
2
In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX 6ULL Hardware Development
Guide (IMX6ULLHDG).
Table 11 shows on-chip LDO regulators that can supply on-chip loads.
1
Table 11. On-Chip LDOs and their On-Chip Loads
Voltage Source
Load
Comment
VDD_HIGH_CAP
NVCC_DRAM_2P5
Board-level connection to VDD_HIGH_CAP
1
On-chip LDOs are designed to supply i.MX 6ULL loads and must not be used to supply external loads.
4.1.4
External Clock Sources
Each i.MX 6ULL processor has two external input system clocks: a low frequency (RTC_XTALI) and a
high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 12 shows the interface frequency requirements.
Table 12. External Input Clock Frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1,2
XTALI Oscillator2,4
fckil
fxtal
—
—
32.7683/32.0
24
—
—
kHz
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
The typical values shown in Table 12 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
•
•
On-chip 40 kHz ring oscillator—this clock source has the following characteristics:
— Approximately 25 µA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
External crystal oscillator with on-chip support circuit:
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— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
4.1.5
Maximum Supply Currents
The data shown in Table 13 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to
specifically show the worst case power consumption.
See the i.MX 6ULL Power Consumption Measurement Application Note (AN4581) for more details on
typical power consumption under various use case definitions.
Table 13. Maximum Supply Currents
Power Line
Conditions
Max Current
Unit
VDD_SOC_IN
900 MHz Arm clock
based on Dhrystone
test
500
mA
VDD_HIGH_IN
VDD_SNVS_IN
—
—
—
1251
5002
503
mA
A
USB_OTG1_VBUS
USB_OTG2_VBUS
mA
VDDA_ADC_3P3
100 Ohm maximum
35
mA
loading for touch panel
Primary Interface (IO) Supplies
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_GPIO
NVCC_UART
NVCC_ENET
NVCC_LCD
—
(See4)
—
mA
—
—
—
—
—
—
—
—
50
N=16
N=16
N=16
N=29
N=17
N=6
N=12
MISC
—
Use maximum IO Equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
Use maximum IO equation5
NVCC_NAND
NVCC_SD
NVCC_CSI
DRAM_VREF
1
mA
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Electrical Characteristics
1
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_DRAM_2P5 supplies).
2
The maximum VDD_SNVS_IN current may be higher depending on specific operating configurations, such as
BOOT_MODE[1:0] not equal to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1
mA, if available. VDD_SNVS_CAP charge time will increase if less than 1 mA is available.
3
This is the maximum current per active USB physical interface.
4
The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power
calculators are typically available from the memory vendors. They take in account factors, such as signal termination. See
the i.MX 6ULL Power Consumption Measurement Application Note (AN4581) or examples of DRAM power consumption
during specific use case scenarios.
5
General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
4.1.6
Power Modes
The i.MX 6ULL has the following power modes:
•
RUN Mode: CPU is active, some portion of the chip can be clock gated or power gated. Support
multiple voltage/frequency scaling set point for power saving;
•
Low Power Mode: CPU in WFI state or power gate, some portion of the chip can be shut off for
power saving. The Suspend, Low Power Idle, System Idle are consider as sub-modes of the RUN
mode;
•
•
SNVS Mode: only RTC and tamper detection logic is active, with 12 GPIOs in low power state
retention mode;
OFF Mode: all power rails are off.
The following table summarizes the external power supply state in all the power modes.
Table 14. Power Supply State in Power Modes
Power Rail
RUN
Low Power
SNVS
OFF
VDD_SOC_IN
VDD_HIGH_IN
VDD_SNVS
ON
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
USB_OTG1_VBUS
USB_OTG2_VBUS
ON / OFF
ON / OFF
OFF
NVCC_DRAM_2P5
VDDA_ADC_3P3
NVCC_DRAM
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON / OFF
ON
ON / OFF
ON
NVCC_XXX
ON / OFF
ON / OFF
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4.1.6.1
RUN Mode
In RUN mode, the CPU is active and running, and the analog / digital peripheral modules inside the
processor will be enabled. In this mode, all the external power rails to the processor have to be ON and the
SoC will be able to draw as many current.
Typically, when the CPU is doing DVFS, it switches the VDD_ARM voltage according to Table 10.
4.1.6.2
Low Power Mode
When the CPU is not running, the processor can enter low power mode. i.MX 6ULL processor supports a
very flexible set of power mode configurations in low power mode.
Typically there are three low power modes used, System IDLE, Low Power IDLE, and SUSPEND:
•
System IDLE—This is a mode that the CPU can automatically enter when there is no thread
running. All the peripherals can keep working and the CPU’s state is retained so the interrupt
response can be very short. The cores are able to individually enter the WAIT state.
•
Low Power IDLE—This mode is for the case when the system needs to have lower power but still
keep some of the peripherals alive. Most of the peripherals, analog modules, and PHYs are shut
off. The interrupt response in this mode is expected to be longer than the System IDLE, but its
power is much lower.
•
Suspend—This mode has the greatest power savings; all clocks, unused analog/PHYs, and
peripherals are off. The external DRAM stays in Self-Refresh mode. The exit time from this mode
is much longer.
Table 15 shows the current core consumption (not including I/O) of i.MX 6ULL processors in selected low
power modes.
Table 15. Low Power Mode Current and Power Consumption
Mode
Test Conditions
Supply
Typical
Units
SYSTEM IDLE:
LDO Enabled
• LDO_ARM and LDO_SOC are set to 1.15 V
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• DDR is in self refresh
VDD_SOC_IN (1.275 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
9
mA
9.7
0.04
40.7
• 24 MHz XTAL is ON
mW
mA
• 528 PLL is active, other PLLs are power down
• High-speed peripheral clock gated, but remain
powered
SYSTEM IDLE:
LDO Bypassed
• LDO_ARM and LDO_SOC are set to bypass
mode
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• DDR is in self refresh
VDD_SOC_IN (1.25 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
8.5
8.8
0.04
37.15
mW
• 24 MHz XTAL is ON
• 528 PLL is active, other PLLs are power down
• High-speed peripheral clock gated, but remain
powered
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Electrical Characteristics
Table 15. Low Power Mode Current and Power Consumption (continued)
LOW POWER IDLE: • LDO_SOC is set to 1.15 V, LDO_ARM is in PG
VDD_SOC_IN (1.025 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
1.6
mA
LDO Enabled
mode
1.25
0.03
5.48
• LDO_2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
mW
mA
• High-speed peripheral are powered off
LOW POWER IDLE: • LDO_SOC is in bypass mode, LDO_ARM is in PG
VDD_SOC_IN (0.9 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
1.5
0.3
LDO Bypassed
mode
• LDO_2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
0.05
2.4
mW
mA
• High-speed peripheral are powered off
SUSPEND:
• LDO_SOC is in bypass mode, LDO_ARM is in PG
mode
VDD_SOC_IN (0.9 V)
VDD_HIGH_IN (3.0 V)
VDD_SNVS_IN (3.0 V)
Total
0.3
0.03
0.03
0.45
• LDO_2P5 and LDO_1P1 are shut off
• CPU in power gate mode
• DDR is in self refresh
mW
mA
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• High-speed peripheral are powered off
SNVS:
• All SOC digital logic, analog module are shut off
• 32 kHz RTC is alive
VDD_SOC_IN (0 V)
VDD_HIGH_IN (0 V)
VDD_SNVS_IN (3.0 V)
Total
0
0
• Tamper detection circuit remains active
0.03
0.09
mW
4.1.6.3
SNVS Mode
SNVS mode is also called RTC mode, where only the power for the SNVS domain remain on. In this
mode, only the RTC and tamper detection logic is still active.
The power consumption in SNVS model with all the tamper detection logic enabled will be less than 0.03
mA@3.0V on VDD_SNVS for typical silicon at 25C.
In SNVS mode, the supported wakeup source are RTC alarm, ONOFF event, and also the 12 GPIO pads
in VDD_SNVS_IN domain.
In some applications, the SNVS mode is powered by non-rechargeable coin cell battery, so the power
consumption in SNVS mode has to be very low.
4.1.6.4
OFF Mode
In OFF mode, all power rails are shut off.
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4.1.7
USB PHY Current Consumption
Power Down Mode
4.1.7.1
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical
condition. Table 16 shows the USB interface current consumption in power down mode.
Table 16. USB PHY Current Consumption in Power Down Mode
VDD_USB_CAP (3.0 V)
VDD_HIGH_CAP (2.5 V)
NVCC_PLL (1.1 V)
Current
5.1 A
1.7 A
< 0.5 A
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
4.2.1
Power-Up Sequence
The below restrictions must be followed:
•
•
VDD_SNVS_IN supply must be turned on before any other power supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
•
VDD_HIGH_IN should be turned on before VDD_SOC_IN.
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for further details and to ensure that all necessary
requirements are being met.
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Electrical Characteristics
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use both the 1.8 V and 3.3 V supplies).
NOTE
USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power
supply sequence and may be powered at any time.
4.2.2
Power-Down Sequence
The following restrictions must be followed:
•
•
VDD_SNVS_IN supply must be turned off after any other power supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
•
VDD_HIGH_IN should be turned off after VDD_SOC_IN is switched off.
4.2.3
Power Supplies Usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information
and Contact Assignments".”
4.3
Integrated LDO Voltage Regulator Parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for details on the power tree scheme.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO operation only.
4.3.1
Digital Regulators (LDO_ARM, LDO_SOC)
There are two digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of
their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on-die trimming. This translates into more stable voltage for
the on-chip logics.
These regulators have two basic modes:
•
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
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•
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2
Analog Regulators (LDO_1P1, LDO_2P5, and LDO_USB)
LDO_1P1
4.3.2.1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0
V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB PHY, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is
2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the DDR IOs, USB PHY,
E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be
used by the system to determine when the load capability of the regulator is being exceeded, to take the
necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up,
if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 ..
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
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Electrical Characteristics
regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.4
PLL’s Electrical Characteristics
4.4.1
Audio/Video PLL’s Electrical Parameters
Table 17. Audio/Video PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz ~1.3 GHz
24 MHz
<11250 reference cycles
4.4.2
4.4.3
528 MHz PLL
Table 18. 528 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
528 MHz PLL output
24 MHz
<11250 reference cycles
Ethernet PLL
Table 19. Ethernet PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
500 MHz
24 MHz
<11250 reference cycles
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4.4.4
4.4.5
480 MHz PLL
Table 20. 480 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
480 MHz PLL output
24 MHz
<383 reference cycles
Arm PLL
Table 21. Arm PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
648 MHz ~ 1296 MHz
24 MHz
<2250 reference cycles
4.5
On-Chip Oscillators
OSC24M
4.5.1
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.5.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
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Electrical Characteristics
connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
•
•
Average Discharge Voltage is 2.5 V
Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 22. OSC32K Main Characteristics
Max Comments
Min
Typ
Fosc
—
32.768 KHz
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption
—
4 A
—
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc
in the power_detect block. So, the total current is 6.5 A on vdd_rtc when
the ring oscillator is not running.
Bias resistor
—
14 M
—
—
This the integrated bias resistor that sets the amplifier into a high gain
state. Any leakage through the ESD network, external board leakage, or
even a scope probe that is significant relative to this value will debias the
amp. The debiasing will result in low gain, and will impact the circuit's ability
to start up and maintain oscillations.
Crystal Properties
Cload
ESR
—
—
10 pF
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
50 k
100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
4.6
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output.
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Figure 3. Circuit for Parameters Voh and Vol for I/O Cells
4.6.1
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
Table 23 shows the DC parameters for the clock inputs.
1
Table 23. XTALI and RTC_XTALI DC Parameters
Symbol Test Conditions Min
Parameter
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
—
—
0.8 x NVCC_PLL
NVCC_PLL
V
V
V
V
0
0.8
0
0.2
1.1
0.2
RTC_XTALI high-level DC input voltage
RTC_XTALI low-level DC input voltage
Vih
Vil
1
The DC parameters are for external clock input only.
4.6.2
Single Voltage General Purpose I/O (GPIO) DC Parameters
Table 24 shows DC parameters for GPIO pads. The parameters in Table 24 are guaranteed per the
operating ranges in Table 10, unless otherwise noted.
Table 24. Single Voltage GPIO DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage1
VOH
Ioh= -0.1mA (ipp_dse=001,010) OVDD-0.15
Ioh= -1mA
–
V
(ipp_dse=011,100,101,110,111)
Low-level output voltage1
VOL
Iol= 0.1mA (ipp_dse=001,010)
Iol= 1mA
–
0.15
V
(ipp_dse=011,100,101,110,111)
High-Level input voltage1,2
Low-Level input voltage1,2
VIH
VIL
—
—
0.7 x OVDD
0
OVDD
V
V
0.3 x
OVDD
Input Hysteresis (OVDD= 1.8V)
Input Hysteresis (OVDD=3.3V
VHYS_LowVDD
VHYS_HighVDD
OVDD=1.8V
OVDD=3.3V
200
200
—
—
mV
mV
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Parameter
Table 24. Single Voltage GPIO DC Parameters (continued)
Symbol
Test Conditions
Min
Max
Units
Schmitt trigger VT+2,3
Schmitt trigger VT-2,3
VTH+
VTH-
—
—
0.5 x OVDD
—
—
mV
mV
0.5 x
OVDD
Pull-up resistor (22_k PU)
Pull-up resistor (22_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (100_k PU)
Pull-up resistor (100_k PU)
Pull-down resistor (100_k PD)
Pull-down resistor (100_k PD)
Input current (no PU/PD)
RPU_22K
RPU_22K
RPU_47K
RPU_47K
RPU_100K
RPU_100K
RPD_100K
RPD_100K
IIN
Vin=0V
Vin=OVDD
—
—
—
—
—
—
—
—
-1
212
1
uA
uA
uA
uA
uA
uA
uA
uA
uA
k
Vin=0V
100
1
Vin=oOVDD
Vin=0V
48
1
Vin=OVDD
Vin=OVDD
48
1
Vin=0V
VI = 0, VI = OVDD
VI =0.3 x OVDD, VI = 0.7 x OVDD
1
Keeper Circuit Resistance
R_Keeper
105
175
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
3
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.6.3
DDR I/O DC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. For details on supported
DDR memory configurations, see Section 4.10, “Multi-Mode DDR Controller (MMDC)".
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX 6ULL
Applications Processor (IMX6ULLHDG).
4.6.3.1
LPDDR2 Mode I/O DC Parameters
1
Table 25. LPDDR2 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
Low-level output voltage
Input Reference Voltage
VOH
VOL
Ioh= -0.1mA
0.9 x OVDD
—
—
V
V
V
V
Iol= 0.1mA
0.1 x OVDD
0.51 x OVDD
OVDD
Vref
—
—
0.49 x OVDD
Vref+0.13
DC High-Level input voltage
Vih_DC
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1
Table 25. LPDDR2 I/O DC Electrical Parameters (continued)
Parameters
Symbol
Test Conditions
Min
Max
Unit
DC Low-Level input voltage
Differential Input Logic High
Vil_DC
Vih_diff
Vil_diff
Mmpupd
Rres
—
OVSS
0.26
Note2
-15
Vref-0.13
Note2
-0.26
15
V
—
—
%
—
Differential Input Logic Low
—
Pull-up/Pull-down Impedance Mismatch
240 unit calibration resolution
Keeper Circuit Resistance
—
—
—
—
10
Rkeep
Iin
110
175
k
A
Input current (no pull-up/down)
VI = 0, VI = OVDD
-2.5
2.5
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4.6.3.2
DDR3/DDR3L Mode I/O DC Parameters
The parameters in Table 27 are guaranteed per the operating ranges in Table 10, unless otherwise noted.
Table 27. DDR3/DDR3L I/O DC Electrical Characteristics
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
VOH
Ioh= -0.1mA
0.8 x OVDD1
—
V
Voh (for ipp_dse=001)
Low-level output voltage
High-level output voltage
Low-level output voltage
VOL
VOH
VOL
Iol= 0.1mA
Vol (for ipp_dse=001)
0.2 x OVDD
0.8 x OVDD
0.2 x OVDD
—
—
—
V
V
V
Ioh= -1mA
Voh (for all except ipp_dse=001)
Iol= 1mA
Vol (for all except ipp_dse=001)
Input Reference Voltage
DC High-Level input voltage
DC Low-Level input voltage
Differential Input Logic High
Differential Input Logic Low
Termination Voltage
Vref
Vih_DC
Vil_DC
Vih_diff
Vil_diff
Vtt
—
0.49 x OVDD
Vref2+0.1
OVSS
0.51 x ovdd
OVDD
V
V
—
—
Vref-0.1
See Note3
-0.2
V
—
0.2
V
—
—
V
Vtt tracking OVDD/2
0.49 x OVDD 0.51 x OVDD
V
Pull-up/Pull-down Impedance Mismatch Mmpupd
—
-10
—
10
10
%
240 unit calibration resolution
Keeper Circuit Resistance
Rres
Rkeep
Iin
—
—
105
-2.9
165
2.9
k
A
Input current (no pull-up/down)
VI = 0,VI = OVDD
1
2
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L)
Vref – DDR3/DDR3L external reference voltage
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3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4.6.4
LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 28 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
Table 28. LVDS I/O DC Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
VOH
VOL
VOS
Rload-100 Diff
IOH = 0 mA
IOL = 0 mA
—
250
1.25
0.9
350
1.375
1.025
1.2
450
1.6
mV
V
1.25
1.375
V
1.125
V
4.7
I/O AC Parameters
This section includes the AC parameters of the following I/O types:
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and
Figure 5.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 5. Output Transition Time Waveform
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4.7.1
General Purpose I/O AC Parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 29 and Table 30,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 29. General Purpose I/O AC Parameters 1.8 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=111)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
2.72/2.79
1.69/1.82
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=101)
tr, tf
tr, tf
tr, tf
trm
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
3.99/4.44
2.14/2.50
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=100)
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
4.52/5.01
2.52/3.07
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=011)
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
5.15/5.68
3.44/3.73
—
—
—
—
Input Transition Times1
—
25
ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Table 30. General Purpose I/O AC Parameters 3.3 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=101)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
1.84/2.06
1.09/1.35
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=011)
tr, tf
tr, tf
tr, tf
trm
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
2.44/2.75
1.75/2.02
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=010)
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
3.26/3.70
2.47/2.92
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=001)
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
5.26/6.19
4.88/5.77
—
—
—
—
ns
ns
Input Transition Times1
—
25
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.7.2
DDR I/O AC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. For details on supported
DDR memory configurations, see Section 4.10, “Multi-Mode DDR Controller (MMDC)".
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX 6ULL
Applications Processor (IMX6ULLHDG).
Table 31 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
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Parameter
1
Table 31. DDR I/O LPDDR2 Mode AC Parameters
Symbol
Test Condition
Min
Max
Unit
AC input logic high
Vih(ac)
Vil(ac)
—
Vref + 0.22
OVDD
Vref - 0.22
—
V
V
AC input logic low
—
0
0.44
—
AC differential input high voltage2
AC differential input low voltage
Input AC differential cross point voltage3
Over/undershoot peak
Vidh(ac)
Vidl(ac)
Vix(ac)
Vpeak
—
V
—
Relative to Vref
—
0.44
V
-0.12
—
0.12
V
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
400 MHz
—
0.3
V-ns
tsr
50 to Vref.
5 pF load.
Drive impedance = 40
30%
1.5
1
3.5
2.5
0.1
V/ns
Single output slew rate, measured between
Vol (ac) and Voh (ac)
50 to Vref.
5pF load.Drive
impedance = 60
30%
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
clk = 400 MHz
ns
—
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2
3
Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp
is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 32 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
1
Table 32. DDR I/O DDR3/DDR3L Mode AC Parameters
Parameter
AC input logic high
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
Vid(ac)
Vix(ac)
Vpeak
Varea
—
Vref + 0.175
—
—
—
—
—
—
OVDD
Vref - 0.175
—
V
V
AC input logic low
—
0
0.35
AC differential input voltage2
Input AC differential cross point voltage3
Over/undershoot peak
—
Relative to Vref
—
V
Vref - 0.15
—
Vref + 0.15
0.4
V
V
Over/undershoot area (above OVDD
or below OVSS)
400 MHz
—
0.5
V-ns
Single output slew rate, measured between Vol
(ac) and Voh (ac)
tsr
Driver impedance = 34
2.5
—
—
5
V/ns
ns
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
clk = 400 MHz
0.1
—
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1
2
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
4.8
Output Buffer Impedance Parameters
This section defines the I/O impedance parameters of the i.MX 6ULL processors for the following I/O
types:
•
•
Single Voltage General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes
NOTE
GPIO and DDR I/O output driver impedance is measured with “long”
transmission line of impedance Ztl attached to I/O pad and incident wave
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that
defines specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 6).
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OVDD
PMOS (Rpu)
Ztl , L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vovdd - Vref1
Vref1
Rpu =
Ztl
Ztl
Vref2
Rpd =
Vovdd - Vref2
Figure 6. Impedance Matching Load for Measurement
4.8.1
Single Voltage GPIO Output Buffer Impedance
Table 33 shows the GPIO output buffer impedance (OVDD 1.8 V).
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Unit
Table 33. GPIO Output Buffer Average Impedance (OVDD 1.8 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
001
010
011
100
101
110
111
260
130
88
65
52
Output Driver
Impedance
Rdrv
43
37
Table 34 shows the GPIO output buffer impedance (OVDD 3.3 V).
Table 34. GPIO Output Buffer Average Impedance (OVDD 3.3 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
157
78
53
39
32
26
23
Output Driver
Impedance
Rdrv
4.8.2
DDR I/O Output Buffer Impedance
Table 35 shows DDR I/O output buffer impedance of i.MX 6ULL processors.
Table 35. DDR I/O Output Buffer Impedance
Typical
Test Conditions DSE
Parameter
Symbol
Unit
NVCC_DRAM=1.5 V
(DDR3)
NVCC_DRAM=1.2 V
(LPDDR2)
(Drive Strength)
DDR_SEL=11
DDR_SEL=10
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
Hi-Z
240
120
80
60
48
Output Driver
Impedance
Rdrv
40
34
40
34
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.
4.9
System Modules Timing
This section contains the timing and electrical parameters for the modules in each i.MX 6ULL processor.
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4.9.1
Reset Timings Parameters
Figure 7 shows the reset timing and Table 36 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset Timing Diagram
Table 36. Reset Timing Parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
4.9.2
WDOG Reset Timing Parameters
Figure 8 shows the WDOG reset timing and Table 37 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 8. WDOGn_B Timing Diagram
Table 37. WDOGn_B Timing Parameters
ID
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
4.9.3
External Interface Module (EIM)
The following subsections provide information on the EIM.
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4.9.3.1
EIM Interface Pads Allocation
EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.
Table 38 provides EIM interface pads allocation in different modes.
1
Table 38. EIM Multiplexing
Non Multiplexed Address/Data Mode
8 Bit 16 Bit
Multiplexed Address/Data mode
16 Bit
32 Bit
Setup
MUM = 0,
DSZ = 100
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 001
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
A[15:0]
EIM_DA[15:0]
EIM_A[25:16]
EIM_D[7:0]
EIM_DA[15:0]
EIM_A[25:16]
—
EIM_DA[15:0]
EIM_A[25:16]
EIM_D[7:0]
EIM_DA[15:0]
EIM_A[25:16]
EIM_DA[7:0]
EIM_DA[15:0]
EIM_D[9:0]
A[25:16]
D[7:0],
EIM_DA[7:0]
EIM_EB0
D[15:8],
EIM_EB1
—
—
—
EIM_D[15:8]
EIM_D[15:8]
EIM_DA[15:8]
EIM_DA[15:8]
EIM_D[7:0]
D[23:16],
EIM_EB2
—
—
—
—
—
—
D[31:24],
EIM_EB3
EIM_D[15:8]
1
For more information on configuration ports mentioned in this table, see the i.MX 6ULL reference manual.
4.9.3.2
General EIM Timing-Synchronous Mode
Figure 9, Figure 10, and Table 39 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
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,
WE2
...
WE3
EIM_BCLK
WE1
WE4
WE6
WE5
WE7
WE9
EIM_ADDRxx
EIM_CSx_B
WE8
WE10
WE12
EIM_WE_B
EIM_OE_B
EIM_EBx_B
WE11
WE13
WE15
WE17
WE14
WE16
EIM_LBA_B
Output Data
Figure 9. EIM Outputs Timing Diagram
EIM_BCLK
WE18
Input Data
WE19
WE20
EIM_WAIT_B
WE21
Figure 10. EIM Inputs Timing Diagram
4.9.3.3
Examples of EIM Synchronous Accesses
1
Table 39. EIM Bus Timing Parameters
BCD = 0
BCD = 1
BCD = 2
Max
BCD = 3
Max
ID
Parameter
Min
Max
Min
Max
Min
Min
WE1 EIM_BCLK Cycle
time2
t
—
2 x t
—
3 x t
—
—
—
4 x t
—
—
—
WE2 EIM_BCLK Low
Level Width
0.4 x t
0.4 x t
—
—
0.8 x t
0.8 x t
—
—
1.2 x t
1.2 x t
1.6 x t
1.6 x t
WE3 EIM_BCLK High
Level Width
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BCD = 3
1
Table 39. EIM Bus Timing Parameters (continued)
BCD = 0 BCD = 1 BCD = 2
Max Min Max
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t -
ID
Parameter
Min
Min
Max
Min
Max
WE4 Clock rise to
address valid3
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE5 Clock rise to
address invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE6 Clock rise to
EIM_CSx_B valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE7 Clock rise to
EIM_CSx_B invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE8 Clock rise to
EIM_WE_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE9 Clock rise to
EIM_WE_B Invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE10 Clock rise to
EIM_OE_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE11 Clock rise to
EIM_OE_B Invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE12 Clock rise to
EIM_EBx_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE13 Clock rise to
EIM_EBx_B Invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE14 Clock rise to
EIM_LBA_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE15 Clock rise to
EIM_LBA_B Invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE16 Clock rise to
Output Data Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE17 Clock rise to
Output Data Invalid
0.5 x t -
1.25
0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t -
1.25
1.5 x t
+1.75
2 x t -
1.25
2 x t + 1.75
WE18 Input Data setup
time to Clock rise
2
—
—
4
2
—
—
—
—
—
—
WE19 Input Data hold
time from Clock
rise
2
—
—
—
—
WE20 EIM_WAIT_B
setup time to Clock
rise
2
2
—
—
4
2
—
—
—
—
—
—
—
—
—
—
WE21 EIM_WAIT_B hold
time from Clock
rise
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1
t is the maximum EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed
latency configuration, whereas the maximum allowed EIM_BCLK frequency is:
—Fixed latency for both read and write is 132 MHz.
—Variable latency for read only is 132 MHz.
—Variable latency for write only is 52 MHz.
In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz. Write BCD = 1 and
104 MHz axi_clk, will result in an EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses
are impacted which are clocked from this source. See the CCM chapter of the i.MX 6ULL Reference Manual (IMX6ULLRM) for
a detailed clock tree description.
2
EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is
defined as 50% as signal value.
3
For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
Figure 11 to Figure 14 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
EIM_BCLK
WE4
WE6
WE5
WE7
EIM_ADDRxx
Address v1
Last Valid Address
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
WE14
WE10
WE12
WE15
WE18
WE11
WE13
EIM_OE_B
EIM_EBx_B
EIM_DATAxx
D(v1)
WE19
Figure 11. Synchronous Memory Read Access, WSC=1
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EIM_BCLK
WE5
WE4
EIM_ADDRxx
Last Valid Address
Address V1
WE7
WE6
WE8
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE9
WE14
WE15
WE13
WE12
WE16
EIM_EBx_B
WE17
EIM_DATAxx
D(V1)
Figure 12. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0
EIM_BCLK
WE16
WE17
WE5
WE4
EIM_ADDRxx/
EIM_ADxx
Write Data
Last Valid Address
Address V1
WE6
WE7
WE9
EIM_CSx_B
EIM_WE_B
WE8
WE14
WE15
EIM_LBA_B
EIM_OE_B
WE10
WE11
EIM_EBx_B
Figure 13. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
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EIM_BCLK
WE4
Valid Address
WE6
WE5
Address V1
WE19
WE18
EIM_ADDRxx/
EIM_ADxx
Last
Data
EIM_CSx_B
EIM_WE_B
WE7
WE15
WE10
WE14
WE12
EIM_LBA_B
EIM_OE_B
WE11
WE13
EIM_EBx_B
Figure 14. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0
4.9.3.4
General EIM Timing-Asynchronous Mode
Figure 15 through Figure 19, and Table 40 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read & write access length in cycles may vary from what is shown in Figure 15 through
Figure 18 as RWSC, OEN and CSN is configured differently. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for the EIM programming model.
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
EIM_ADxx
WE31
WE32
Next Address
Last Valid Address
Address V1
EIM_WE_B
EIM_LBA_B
WE39
WE40
WE36
WE38
WE35
WE37
EIM_OE_B
EIM_EBx_B
WE44
MAXCO
EIM_DATAxx[7:0]
D(V1)
WE43
MAXDI
Figure 15. Asynchronous Memory Read Access (RWSC = 5)
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end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
MAXDI
WE31
EIM_ADDRxx/
EIM_ADxx
D(V1)
Addr. V1
WE32A
WE44
EIM_WE_B
EIM_LBA_B
WE40A
WE39
WE35A
WE37
WE36
WE38
EIM_OE_B
EIM_EBx_B
MAXCO
Figure 16. Asynchronous A/D Muxed Read Access (RWSC = 5)
EIM_CSx_B
WE41
WE31
EIM_ADDRxx/
D(V1)
Addr. V1
WE32A
WE42
EIM_DATAxx
EIM_WE_B
WE33
WE39
WE34
WE40A
EIM_LBA_B
EIM_OE_B
WE46
WE45
EIM_EBx_B
Figure 17. Asynchronous Memory Write Access
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EIM_CSx_B
WE41
WE31
EIM_ADDRxx/
D(V1)
Addr. V1
WE32A
WE42
EIM_DATAxx
EIM_WE_B
WE33
WE39
WE34
WE40A
EIM_LBA_B
EIM_OE_B
WE46
WE45
EIM_EBx_B
Figure 18. Asynchronous A/D Muxed Write Access
EIM_CSx_B
WE31
WE32
EIM_ADDRxx
Next Address
Last Valid Address
Address V1
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE39
WE35
WE37
WE40
WE36
WE38
EIM_EBx_B
WE44
D(V1)
EIM_DATAxx[7:0]
EIM_DTACK_B
WE43
WE48
WE47
Figure 19. DTACK Mode Read Access (DAP=0)
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EIM_CSx_B
WE31
WE32
WE34
WE40
EIM_ADDRxx
EIM_WE_B
Next Address
Last Valid Address
Address V1
WE33
WE39
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
WE45
WE41
WE46
WE42
EIM_DATAxx
D(V1)
WE48
EIM_DTACK_B
WE47
Figure 20. DTACK Mode Write Access (DAP=0)
Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select
Determination by
Synchronous measured
parameters1
Max
(If 132 MHz is
supported by SoC)
Ref No.
Parameter
Min
Unit
WE31
WE32
EIM_CSx_B valid to Address
Valid
WE4 - WE6 - CSA2
—
—
3 - CSA
3 - CSN
ns
ns
ns
ns
ns
ns
ns
Address Invalid to EIM_CSx_B
invalid
WE7 - WE5 - CSN3
WE32A(m EIM_CSx_B valid to Address
uxed A/D Invalid
t4 + WE4 - WE7 + (ADVN5 +
ADVA6 + 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
—
WE33
WE34
WE35
EIM_CSx_B Valid to
EIM_WE_B Valid
WE8 - WE6 + (WEA - WCSA)
WE7 - WE9 + (WEN - WCSN)
WE10 - WE6 + (OEA - RCSA)
WE10 - WE6 + (OEA + RADVN
—
3 + (WEA - WCSA)
3 - (WEN_WCSN)
3 + (OEA - RCSA)
3 + (OEA +
EIM_WE_B Invalid to
EIM_CSx_B Invalid
—
—
EIM_CSx_B Valid to
EIM_OE_B Valid
WE35A EIM_CSx_B Valid to
(muxed EIM_OE_B Valid
A/D)
-3 + (OEA +
+ RADVA + ADH + 1 - RCSA) RADVN+RADVA+ RADVN+RADVA+AD
ADH+1-RCSA)
H+1-RCSA)
WE36
EIM_OE_B Invalid to
EIM_CSx_B Invalid
WE7 - WE11 + (OEN - RCSN)
WE12 - WE6 + (RBEA - RCSA)
—
3 - (OEN - RCSN)
ns
ns
WE37
EIM_CSx_B Valid to
EIM_EBx_B Valid (Read
access)
—
3 + (RBEA - RCSA)
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Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)
Determination by
Synchronous measured
parameters1
Max
Ref No.
Parameter
Min
(If 132 MHz is
supported by SoC)
Unit
WE38
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Read
access)
WE7 - WE13 + (RBEN - RCSN)
—
3 - (RBEN- RCSN)
ns
WE39
WE40
EIM_CSx_B Valid to
EIM_LBA_B Valid
WE14 - WE6 + (ADVA - CSA)
WE7 - WE15 - CSN
—
—
3 + (ADVA - CSA)
3 - CSN
ns
ns
EIM_LBA_B Invalid to
EIM_CSx_B Invalid (ADVL is
asserted)
WE40A EIM_CSx_B Valid to
(muxed EIM_LBA_B Invalid
A/D)
WE14 - WE6 + (ADVN + ADVA
+ 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
3 + (ADVN + ADVA +
1 - CSA)
ns
WE41
EIM_CSx_B Valid to Output
Data Valid
WE16 - WE6 - WCSA
—
—
3 - WCSA
ns
ns
WE41A EIM_CSx_B Valid to Output
(muxed Data Valid
A/D)
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA)
3 + (WADVN +
WADVA + ADH + 1 -
WCSA)
WE42
Output Data Invalid to
EIM_CSx_B Invalid
WE17 - WE7 - CSN
10
—
—
3 - CSN
ns
ns
MAXCO Output maximum delay from
internal driving
—
EIM_ADDRxx/control FFs to
chip outputs
MAXCSO Output maximum delay from
CSx internal driving FFs to CSx
out
10
5
—
—
—
—
—
ns
ns
ns
MAXDI EIM_DATAxx maximum delay
from chip input data to its
internal FF
WE43
Input Data Valid to EIM_CSx_B MAXCO - MAXCSO + MAXDI
Invalid
MAXCO -
MAXCSO +
MAXDI
WE44
WE45
EIM_CSx_B Invalid to Input
Data invalid
0
0
—
ns
ns
EIM_CSx_B Valid to
EIM_EBx_B Valid (Write
access)
WE12 - WE6 + (WBEA -
WCSA)
—
3 + (WBEA - WCSA)
WE46
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Write
access)
WE7 - WE13 + (WBEN -
WCSN)
—
-3 + (WBEN - WCSN)
ns
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Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)
Determination by
Synchronous measured
parameters1
Max
Ref No.
Parameter
Min
(If 132 MHz is
supported by SoC)
Unit
MAXDTI MAXIMUM delay from
EIM_DTACK_B to its internal
FF + 2 cycles for
10
—
—
—
synchronization
WE47
WE48
EIM_DTACK_B Active to
EIM_CSx_B Invalid
MAXCO - MAXCSO + MAXDTI
MAXCO -
MAXCSO +
MAXDTI
—
—
ns
ns
EIM_CSx_B Invalid to
EIM_DTACK_B Invalid
0
0
1
2
3
4
5
6
For more information on configuration parameters mentioned in this table, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
In this table, CSA means WCSA when write operation or RCSA when read operation.
In this table, CSN means WCSN when write operation or RCSN when read operation.
t is axi_clk cycle time.
In this table, ADVN means WADVN when write operation or RADVN when read operation.
In this table, ADVA means WADVA when write operation or RADVA when read operation.
4.10 Multi-Mode DDR Controller (MMDC)
The Multi-Mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.
4.10.1 MMDC compatibility with JEDEC-compliant SDRAMs
The i.MX 6ULL MMDC supports the following memory types:
•
•
LPDDR2 SDRAM compliant with JESD209-2B LPDDR2 JEDEC standard release June, 2009
DDR3/DDR3L SDRAM compliant with JESD79-3D DDR3 JEDEC standard release April, 2008
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX 6ULL
Applications Processor (IMX6ULLHDG).
4.10.2 MMDC supported DDR3/DDR3L/LPDDR2 configurations
Table 41 shows the supported DDR3/DDR3L/LPDDR2 configurations:
Table 41. i.MX 6ULL Supported DDR3/DDR3L/LPDDR2 Configurations
Parameter
DDR3
DDR3L
LDDDR2
Clock frequency
Bus width
400 MHz
16-bit
Single
2
400 MHz
16-bit
Single
2
400 MHz
16-bit
Single
2
Channel
Chip selects
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4.11 General-Purpose Media Interface (GPMI) Timing
The i.MX 6ULL GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up
to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following subsections.
4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 21 through Figure 24
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode. Table 42 describes the timing parameters (NF1–NF17) that are shown in the figures.
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Figure 25. Read Data Latch Cycle Timing Diagram (EDO Mode)
1
Table 42. Asynchronous Mode Timing Parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
(AS + DS) T - 0.12 [see
Max.
2,3
NF1
NF2
NF3
NF4
NF5
NAND_CLE setup time
NAND_CLE hold time
tCLS
tCLH
tCS
]
ns
ns
ns
ns
ns
DH T - 0.72 [see 2]
(AS + DS + 1) T [see 3,2
(DH+1) T - 1 [see 2]
DS T [see 2]
NAND_CE0_B setup time
NAND_CE0_B hold time
NAND_WE_B pulse width
]
tCH
tWP
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Electrical Characteristics
1
Table 42. Asynchronous Mode Timing Parameters (continued)
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF6
NF7
NF8
NF9
NAND_ALE setup time
NAND_ALE hold time
Data setup time
tALS
tALH
tDS
(AS + DS) T - 0.49 [see 3,2
(DH T - 0.42 [see 2]
DS T - 0.26 [see 2]
DH T - 1.37 [see 2]
(DS + DH) T [see 2]
DH T [see 2]
]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data hold time
tDH
NF10 Write cycle time
tWC
tWH
tRR4
tRP
NF11 NAND_WE_B hold time
NF12 Ready to NAND_RE_B low
NF13 NAND_RE_B pulse width
NF14 READ cycle time
(AS + 2) T [see 3,2
]
—
DS T [see 2]
(DS + DH) T [see 2]
DH T [see 2]
tRC
NF15 NAND_RE_B high hold time
NF16 Data setup on read
NF17 Data hold on read
tREH
tDSR
tDHR
—
(DS T -0.67)/18.38 [see 5,6
]
0.82/11.83 [see 5,6
]
—
1
GPMI’s Async Mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
In EDO mode (Figure 24), NF16/NF17 is different from the definition in non-EDO mode (Figure 23).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will
sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The
delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 6ULL
Reference Manual). The typical value of this control register is 0x8 at 50 MT/s EDO mode. But if the board
delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board
delay.
4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)
Figure 26 to Figure 28 show the write and read timing of Source Synchronous Mode.
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Figure 26. Source Synchronous Mode Command and Address Timing Diagram
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Electrical Characteristics
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Figure 27. Source Synchronous Mode Data Write Timing Diagram
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Figure 28. Source Synchronous Mode Data Read Timing Diagram
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Figure 29. NAND_DQS/NAND_DQ Read Valid Window
1
Table 43. Source Synchronous Mode Timing Parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2
NF18 NAND_CE0_B access time
NF19 NAND_CE0_B hold time
tCE
tCH
CE_DELAY T - 0.79 [see ]
0.5 tCK - 0.63 [see 2]
0.5 tCK - 0.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
NF20 Command/address NAND_DATAxx setup time
NF21 Command/address NAND_DATAxx hold time
NF22 Clock period
tCAS
tCAH
tCK
0.5 tCK - 1.23
—
NF23 Preamble delay
tPRE
tPOST
tCALS
tCALH
tDQSS
—
PRE_DELAY T - 0.29 [see 2]
POST_DELAY T - 0.78 [see 2]
0.5 tCK - 0.86
NF24 Postamble delay
NF25 NAND_CLE and NAND_ALE setup time
NF26 NAND_CLE and NAND_ALE hold time
NF27 NAND_CLK to first NAND_DQS latching transition
NF28 Data write setup
0.5 tCK - 0.37
T - 0.41 [see 2]
0.25 tCK - 0.35
NF29 Data write hold
—
0.25 tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
—
2.06
1.95
—
1
GPMI’s source synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2
T = tCK(GPMI clock period) -0.075ns (half of maximum p-p jitter).
For DDR Source sync mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read
valid window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s. GPMI
will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which
can be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6ULL
Reference Manual). Generally, the typical delay value of this register is equal to 0x7 which means 1/4
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Electrical Characteristics
clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
4.11.3 Samsung Toggle Mode AC Timing
4.11.3.1 Command and Address Timing
NOTE
Samsung Toggle Mode command and address timing is the same as ONFI
1.0 compatible Async mode AC timing. See Section 4.11.1, “Asynchronous
Mode AC Timing (ONFI 1.0 Compatible)",” for details.
4.11.3.2 Read and Write Timing
DEV?CLK
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Figure 30. Samsung Toggle Mode Data Write Timing
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Electrical Characteristics
DEV?CLK
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Figure 31. Samsung Toggle Mode Data Read Timing
1
Table 44. Samsung Toggle Mode Timing Parameters
Timing
T = GPMI Clock Cycle
Symbo
l
Uni
t
ID
Parameter
Min.
Max.
2,3
NF1 NAND_CLE setup time
tCLS
tCLH
tCS
(AS + DS) T - 0.12 [see
DH T - 0.72 [see 2]
(AS + DS) T - 0.58 [see 3,2
DH T - 1 [see 2]
]
—
—
—
—
—
—
—
—
—
ns
ns
NF2 NAND_CLE hold time
NF3 NAND_CE0_B setup time
NF4 NAND_CE0_B hold time
NF5 NAND_WE_B pulse width
NF6 NAND_ALE setup time
]
tCH
tWP
tALS
tALH
tCAS
tCAH
tCE
DS T [see 2]
(AS + DS) T - 0.49 [see 3,2
DH T - 0.42 [see 2]
DS T - 0.26 [see 2]
]
NF7 NAND_ALE hold time
NF8 Command/address NAND_DATAxx setup time
NF9 Command/address NAND_DATAxx hold time
NF18 NAND_CEx_B access time
NF22 clock period
DH T - 1.37 [see 2]
4,2
CE_DELAY T [see
]
—
—
tCK
—
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Electrical Characteristics
1
Table 44. Samsung Toggle Mode Timing Parameters (continued)
Timing
Symbo
l
T = GPMI Clock Cycle
Uni
t
ID
Parameter
Min.
Max.
5,2
NF23 preamble delay
NF24 postamble delay
NF28 Data write setup
NF29 Data write hold
tPRE
PRE_DELAY T [see
]
—
—
ns
ns
ns
ns
—
tPOST POST_DELAY T +0.43 [see 2]
tDS6
tDH6
0.25 tCK - 0.32
0.25 tCK - 0.79
—
—
—
NF30 NAND_DQS/NAND_DQ read setup skew
tDQSQ
3.18
7
NF31 NAND_DQS/NAND_DQ read hold skew
tQHS7
—
3.27
—
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
5
6
7
PRE_DELAY+1) (AS+DS)
Shown in Figure 30.
Shown in Figure 31.
For DDR Toggle mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will
sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6ULL
Reference Manual). Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay
expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger
to compensate the board delay.
4.12 External Peripheral Interface Parameters
The following subsections provide information on external peripheral interfaces.
4.12.1 CMOS Sensor Interface (CSI) Timing Parameters
4.12.1.0.1 Gated Clock Mode Timing
Figure 32 and Figure 33 shows the gated clock mode timings for CSI, and Table 45 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
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Electrical Characteristics
(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 32. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 33. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 45. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
tDh
33.5
1
—
—
—
—
—
ns
ns
ns
ns
ns
1
CSI DATA hold time
1
CSI pixel clock high time
tCLKh
3.75
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Electrical Characteristics
Table 45. CSI Gated Clock Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min.
Max.
Units
P6
P7
CSI pixel clock low time
CSI pixel clock frequency
tCLKl
fCLK
3.75
—
—
ns
133.3
MHz
4.12.1.0.2 Ungated Clock Mode Timing
Figure 34 shows the ungated clock mode timings of CSI, and Table 46 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[15:00]
Figure 34. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 46. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
33.5
1
—
—
ns
ns
CSI DATA hold time
tDh
1
—
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
—
ns
—
ns
133.3
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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4.12.2 ECSPI Timing Parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
4.12.2.1 ECSPI Master Mode Timing
Figure 35 depicts the timing of ECSPI in master mode. Table 47 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS5
CS2
CS6
CS3
CS1
CS4
ECSPIx_SCLK
ECSPIx_MOSI
ECSPIx_MISO
CS2
CS3
CS7
CS9
CS8
Figure 35. ECSPI Master Mode Timing Diagram
Table 47. ECSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
43
15
—
—
ns
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
21.5
7
CS3 ECSPIx_SCLK Rise or Fall1
tRISE/FALL
tCSLH
tSCS
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
CS4 ECSPIx_SS_B pulse width
Half ECSPIx_SCLK period
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
CS8 ECSPIx_MISO Setup Time
Half ECSPIx_SCLK period - 4
tHCS
Half ECSPIx_SCLK period - 2
tPDmosi
tSmiso
tHmiso
tSDRY
-1
14
0
—
—
—
CS9 ECSPIx_MISO Hold Time
CS10 RDY to ECSPIx_SS_B Time2
5
1
2
See specific I/O AC parameters Section 4.7, “I/O AC Parameters".”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
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Electrical Characteristics
4.12.2.2 ECSPI Slave Mode Timing
Figure 36 depicts the timing of ECSPI in slave mode. Table 48 lists the ECSPI slave mode timing
characteristics.
ECSPIx_SS_B
CS5
CS6
CS2
CS1
CS4
ECSPIx_SCLK
ECSPIx_MISO
CS2
CS9
CS8
CS7
ECSPIx_MOSI
Figure 36. ECSPI Slave Mode Timing Diagram
Table 48. ECSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
tclk
15
43
—
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
7
21.5
—
ns
CS4 ECSPIx_SS_B pulse width
tCSLH
tSCS
Half ECSPIx_SCLK period
—
—
—
—
—
19
ns
ns
ns
ns
ns
ns
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Setup Time
5
5
4
4
4
tHCS
tSmosi
tHmosi
tPDmiso
CS8 ECSPIx_MOSI Hold Time
CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 49 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 37 and Figure 38.
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Max Condition3 Unit
Table 49. Enhanced Serial Audio Interface (ESAI) Timing
Characteristics1,2
No.
Symbol Expression2 Min
62 Clock cycle4
tSSICC
4 T
4 T
30.0
30.0
—
—
i ck
i ck
ns
ns
c
c
63 Clock high period:
• For internal clock
• For external clock
—
—
2 T 9.0
6
15
—
—
—
—
c
2 T
c
64 Clock low period:
• For internal clock
• For external clock
ns
—
—
2 T 9.0
6
15
—
—
—
—
c
2 T
c
65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)
high5
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5
69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high
70 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) low
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
—
—
—
—
—
—
16.0
6.0
x ck
i ck a
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
71 Data in setup time before ESAI_RX_CLK (SCK in
synchronous mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
72 Data in hold time after ESAI_RX_CLK falling edge
—
—
—
—
3.5
9.0
—
—
x ck
i ck
73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK
falling edge5
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK
falling edge
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling
edge
—
—
—
—
2.5
8.5
—
—
x ck
i ck a
76 Flags input setup before ESAI_RX_CLK falling edge
77 Flags input hold time after ESAI_RX_CLK falling edge
78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high
79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low
—
—
—
—
0.0
19.0
—
—
x ck
i ck s
—
—
—
—
6.0
0.0
—
—
x ck
i ck s
—
—
—
—
—
—
18.0
8.0
x ck
i ck
—
—
—
—
—
—
20.0
10.0
x ck
i ck
80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)
high5
—
—
—
—
—
—
20.0
10.0
x ck
i ck
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Table 49. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics1,2
No.
Symbol Expression2 Min
Max Condition3 Unit
81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low5
82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high
83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low
—
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
19.0
9.0
x ck
i ck
—
—
—
—
—
—
20.0
10.0
x ck
i ck
84 ESAI_TX_CLK rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
85 ESAI_TX_CLK rising edge to transmitter #0 drive enable
assertion
—
—
—
—
—
—
17.0
11.0
x ck
i ck
86 ESAI_TX_CLK rising edge to data out valid
—
—
—
—
—
—
18.0
13.0
x ck
i ck
87 ESAI_TX_CLK rising edge to data out high impedance 67
—
—
—
—
—
—
21.0
16.0
x ck
i ck
88 ESAI_TX_CLK rising edge to transmitter #0 drive enable
deassertion7
—
—
—
—
14.0
9.0
x ck
i ck
89 ESAI_TX_FS input (bl, wr) setup time before
ESAI_TX_CLK falling edge5
—
—
—
—
2.0
18.0
—
—
x ck
i ck
90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK
falling edge
—
—
—
—
2.0
18.0
—
—
x ck
i ck
91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling
edge
—
—
—
—
4.0
5.0
—
—
x ck
i ck
92 ESAI_TX_FS input (wl) to data out enable from high
impedance
—
—
—
—
—
—
—
21.0
—
93 ESAI_TX_FS input (wl) to transmitter #0 drive enable
assertion
—
14.0
—
94 Flag output valid after ESAI_TX_CLK rising edge
—
—
14.0
9.0
x ck
i ck
95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle
—
—
2 x TC
—
15
—
—
—
—
ns
ns
96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK
output
18.0
97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK
output
—
—
—
18.0
—
ns
1
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)
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2
3
bl = bit length
wl = word length
wr = word length relative
ESAI_TX_CLK(SCKT pin) = transmit clock
ESAI_RX_CLK(SCKR pin) = receive clock
ESAI_TX_FS(FST pin) = transmit frame sync
ESAI_RX_FS(FSR pin) = receive frame sync
ESAI_TX_HF_CLK(HCKT pin) = transmit high frequency clock
ESAI_RX_HF_CLK(HCKR pin) = receive high frequency clock
4
5
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6
Periodically sampled and not 100% tested.
62
63
64
ESAI_TX_CLK
(Input/Output)
78
79
ESAI_TX_FS
(Bit)
82
83
Out
ESAI_TX_FS
(Word)
86
84
86
Out
87
First Bit
Last Bit
Data Out
89
91
ESAI_TX_FS
(Bit) In
91
90
ESAI_TX_FS
(Word) In
Figure 37. ESAI Transmitter Timing
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Electrical Characteristics
62
63
64
ESAI_RX_CLK
(Input/Output)
65
66
ESAI_RX_FS
(Bit)
Out
69
70
ESAI_RX_FS
(Word)
Out
72
71
Data In
Last Bit
First Bit
75
73
ESAI_RX_FS
(Bit)
In
74
75
ESAI_RX_FS
(Word)
In
Figure 38. ESAI Receiver Timing
ESAI_TX_HF_CLK
95
ESAI_TX_CLK (output)
96
Figure 39. ESAI ESAI_TX_HF_CLK Timing
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Electrical Characteristics
4.12.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing, eMMC4.4/4.41 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.12.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing
Figure 40 depicts the timing of SD/eMMC4.3, and Table 50 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 40. SD/eMMC4.3 Timing
Table 50. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD -6.6
3.6
ns
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Electrical Characteristics
Table 50. SD/eMMC4.3 Interface Timing Specification (continued)
Parameter Symbols Min
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ID
Max
Unit
SD7 uSDHC Input Setup Time
SD8 uSDHC Input Hold Time4
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
4
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.12.4.2 eMMC4.4/4.41 (Dual Data Rate) AC Timing
Figure 41 depicts the timing of eMMC4.4/4.41. Table 51 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 41. eMMC4.4/4.41 Timing
Table 51. eMMC4.4/4.41 Interface Timing Specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1 Clock Frequency (eMMC4.4/4.41 DDR)
SD1 Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2 uSDHC Output Delay tOD 2.5 7.1
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ns
SD3 uSDHC Input Setup Time
SD4 uSDHC Input Hold Time
tISU
tIH
1.7
1.5
—
—
ns
ns
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4.12.4.3 SDR50/SDR104 AC Timing
Figure 42 depicts the timing of SDR50/SDR104, and Table 52 lists the SDR50/SDR104 timing
characteristics.
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6'ꢇꢉ6'ꢃ
6'ꢄ
6'ꢁ
Figure 42. SDR50/SDR104 Timing
Table 52. SDR50/SDR104 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay tOD –3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
1
ns
ns
SD5
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
SD6
SD7
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
—
ns
SD8
1Data window in SDR104 mode is variable.
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Electrical Characteristics
4.12.4.4 HS200 Mode Timing
Figure 43 depicts the timing of HS200 mode, and Table 53 lists the HS200 timing characteristics.
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6'ꢅ
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ꢎꢇELWꢀLQSXWꢀIURPꢀH00&ꢀWRꢀX6'+&
6'ꢎ
Figure 43. HS200 Mode Timing
Table 53. HS200 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
ns
ns
SD5
—
SD8
1HS200 is for 8 bits while SDR104 is for 4 bits.
4.12.4.5 Bus Operation Condition for 3.3 V and 1.8 V Signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 24,
"Single Voltage GPIO DC Parameters," on page 37.
4.12.5 Ethernet Controller (ENET) AC Electrical Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
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Electrical Characteristics
4.12.5.1 ENET MII Mode Timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.12.5.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 44 shows MII receive signal timings. Table 54 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 44. MII Receive Signal Timing Diagram
Table 54. MII Receive Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M1
M2
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
M4
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
35%
35%
65%
65%
ENET_RX_CLK period
ENET_RX_CLK period
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.12.5.1.2 MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
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Electrical Characteristics
Figure 45 shows MII transmit signal timings. Table 55 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 45. MII Transmit Signal Timing Diagram
Table 55. MII Transmit Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M5
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
M8
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
35%
35%
65%
65%
ENET_TX_CLK period
ENET_TX_CLK period
1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.12.5.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)
Figure 46 shows MII asynchronous input timings. Table 56 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 46. MII Async Inputs Timing Diagram
Table 56. MII Asynchronous Inputs Signal Timing
ID
M91
Characteristic
Min.
Max.
Unit
ENET_CRS to ENET_COL minimum pulse width
1.5
—
ENET_TX_CLK period
1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
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Electrical Characteristics
4.12.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 47 shows MII asynchronous input timings. Table 57 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 47. MII Serial Management Channel Timing Diagram
Table 57. MII Serial Management Channel Timing
ID
M10
Characteristic
Min.
Max.
Unit
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
M13
M14
M15
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
18
0
—
—
ns
ns
40%
40%
60%
60%
ENET_MDC period
ENET_MDC period
ENET_MDC pulse width low
4.12.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the RMII_CRS_DV in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0], and ENET_RX_ER.
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Electrical Characteristics
Figure 48 shows RMII mode timings. Table 58 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 48. RMII Mode Signal Timing Diagram
Table 58. RMII Signal Timing
ID
M16
Characteristic
Min.
Max.
Unit
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
M17
M18
M19
M20
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
13
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.12.6 Flexible Controller Area Network (FLEXCAN) AC Electrical
Specifications
The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing
the CAN protocol according to the CAN 2.0B protocol specification. The processor has two CAN modules
available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See
the IOMUXC chapter of the i.MX 6ULL Reference Manual (IMX6ULLRM) to see which pins expose Tx
and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.
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Electrical Characteristics
4.12.7 I2C Bus Characteristics
The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is
designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now
NXP Semiconductors).
4.12.8 Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 49 depicts the timing of the PWM, and Table 59 lists the PWM timing parameters.
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07-N?/54
Figure 49. PWM Timing
Table 59. PWM Output Timing Parameters
ID
Parameter
Min
Max
Unit
PWM Module Clock Frequency
PWM output pulse width high
PWM output pulse width low
0
66
—
—
MHz
ns
P1
P2
15
15
ns
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Electrical Characteristics
4.12.9 LCD Controller (LCDIF) Parameters
Figure 50 shows the LCDIF timing and Table 60 lists the timing parameters.
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Figure 50. LCD Timing
Table 60. LCD Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
L1
L2
L3
L4
L5
L6
L7
LCD pixel clock frequency
tCLK(LCD)
tCLKH(LCD)
tCLKL(LCD)
td(CLKH-DV)
td(CLKL-DV)
—
3
150
—
—
1
MHz
ns
LCD pixel clock high (falling edge capture)
LCD pixel clock low (rising edge capture)
3
ns
LCD pixel clock high to data valid (falling edge capture)
LCD pixel clock low to data valid (rising edge capture)
-1
-1
-1
-1
ns
1
ns
LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV)
LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV)
1
ns
1
ns
4.12.9.1 LCDIF Signal Mapping
Table 61 lists the details about the mapping signals.
Table 61. LCD Timing Parameters
8-bit DOTCLK LCD 16-bit DOTCLK LCD 18-bit DOTCLK LCD 24-bit DOTCLK LCD 8-bit DVI LCD
Pin name
IF
IF
IF
IF
IF
LCD_RS
—
—
—
—
CCIR_CLK
—
LCD_VSYNC*
(Two options)
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
LCD_HSYNC
LCD_DOTCLK
LCD_HSYNC
LCD_DOTCLK
LCD_HSYNC
LCD_DOTCLK
LCD_HSYNC
LCD_DOTCLK
LCD_HSYNC
LCD_DOTCLK
—
—
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Table 61. LCD Timing Parameters (continued)
LCD_ENABLE
LCD_D23
LCD_D22
LCD_D21
LCD_D20
LCD_D19
LCD_D18
LCD_D17
LCD_D16
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
G[7]
—
—
—
—
—
—
—
—
—
R[5]
R[4]
R[3]
—
LCD_D15 /
VSYNC*
R[4]
LCD_D14 /
HSYNC**
—
—
R[3]
R[2]
R[1]
G[6]
G[5]
—
—
LCD_D13 /
LCD_DOTCLK
**
R21]
LCD_D12 /
ENABLE**
—
R[1]
R[0]
G[4]
—
LCD_D11
LCD_D10
LCD_D9
LCD_D8
LCD_D8
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD_RESET
—
—
R[0]
G[5]
G[5]
G[4]
G[3]
G[2]
—
—
—
G[4]
G[3]
G[1]
—
—
G[3]
G[2]
G[0]
—
—
G[3]
G[2]
G[0]
—
R[2]
R[1]
R[0]
G[2]
G[1]
G[0]
B[1]
G[2]
G[1]
B[7]
Y/C[7]
Y/C[6]
Y/C[5]
Y/C[4]
Y/C[3]
Y/C[2]
Y/C[1]
Y/C[0]
—
G[1]
G[0]
B[6]
G[0]
B[5]
B[5]
B[4]
B[4]
B[4]
B[3]
B[3]
B[3]
B[2]
B[2]
B[2]
B[1]
B[1]
B[1]
B[0]
B[0]
B[0]
B[0]
LCD_RESET
LCD_RESET
LCD_RESET
LCD_RESET
LCD_BUSY /
LCD_VSYNC
LCD_BUSY (or
optional
LCD_BUSY (or
optional LCD_VSYNC)
LCD_BUSY (or
optional
LCD_BUSY (or
optional
—
LCD_VSYNC)
LCD_VSYNC)
LCD_VSYNC)
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4.12.10 QUAD SPI (QSPI) Timing Parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
4.12.10.1 SDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢅꢌꢆ@
Figure 51. QuadSPI Input/Read Timing (SDR mode with internal sampling)
Table 62. QuadSPI Input Timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
TIS
TIH
Setup time for incoming data
—
—
ns
ns
Hold time requirement for incoming data
0
ꢈ
ꢅ
ꢄ
ꢊ
463,[B6&/.
463,[B'$7$>ꢉꢑꢄ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 52. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Table 63. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
463,[B&6
7&6+
7&66
7&.
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 53. QuadSPI Output/Write Timing (SDR mode)
Table 64. QuadSPI Output/Write Timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
TDHO
TCK
Output data valid time
Output data hold time
SCK clock period
—
-0.5
10
3
2
ns
ns
ns
—
—
—
—
TCSS
TCSH
Chip select output setup time
Chip select output hold time
SCK cycle(s)
SCK cycle(s)
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register, the default
T
css
csh
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
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4.12.10.2 DDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢉꢑꢄ@
Figure 54. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Table 65. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
TIS
TIH
Setup time for incoming data
—
—
ns
ns
Hold time requirement for incoming data
0
ꢈ
ꢅ
ꢄ
ꢊ
463,[B6&/.
463,[B'$7$>ꢉꢑꢄ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 55. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Table 66. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
ꢈ
ꢅ
463,[B6&/.
463,[B&6
7&66
7&.
7&6+
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 56. QuadSPI Output/Write Timing (DDR mode)
Table 67. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
TDHO
TCK
TCSS
TCSH
Output data valid time
Output data hold time
SCK clock period
—
(0.25 x TSCLK) + 2
ns
ns
ns
(0.25 x TSCLK) - 0.5
—
—
—
—
20
3
Chip select output setup time
Chip select output hold time
SCK cycle(s)
SCK cycle(s)
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register, the default
T
css
csh
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
4.12.11 SAI/I2S Switching Specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 68. Master Mode SAI Timing
Num
Characteristic
SAI_MCLK cycle time
Min
2 x tsys
Max
Unit
S1
S2
S3
S4
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
40%
60%
—
MCLK period
ns
4 x tsys
40%
SAI_BCLK pulse width high/low
60%
BCLK period
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Num
Table 68. Master Mode SAI Timing (continued)
Characteristic Min
Max
Unit
S5
S6
S7
S8
S9
S10
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
—
0
15
—
15
—
—
—
ns
ns
ns
ns
ns
ns
—
0
SAI_BCLK to SAI_TXD invalid
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
0
Figure 57. SAI Timing — Master Modes
Table 69. Master Mode SAI Timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
4 x tsys
Max
Unit
S11
S12
S13
S14
S15
S16
S17
S18
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
SAI_RXD setup before SAI_BCLK
40%
10
2
60%
—
BCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
SAI_RXD hold after SAI_BCLK
—
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Figure 58. SAI Timing — Slave Modes
4.12.12 SCAN JTAG Controller (SJC) Timing Parameters
Figure 59 depicts the SJC test clock input timing. Figure 60 depicts the SJC boundary scan timing.
Figure 61 depicts the SJC test access port. Signal parameters are listed in Table 70.
SJ1
SJ2
VM
SJ2
VM
JTAG_TCK
(Input)
VIH
VIL
SJ3
SJ3
Figure 59. Test Clock Input Timing Diagram
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JTAG_TCK
(Input)
VIH
SJ5
Input Data Valid
VIL
SJ4
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 60. Boundary Scan (JTAG) Timing Diagram
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JTAG_TCK
(Input)
VIH
SJ9
VIL
SJ8
Input Data Valid
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 61. Test Access Port Timing Diagram
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
Figure 62. JTAG_TRST_B Timing Diagram
Table 70. JTAG Timing
All Frequencies
Min Max
ID
Parameter1,2
Unit
1
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
JTAG_TCK frequency of operation 1/(3•TDC
)
0.001
45
22
—
—
3
MHz
ns
JTAG_TCK cycle time in crystal mode
2
JTAG_TCK clock pulse width measured at VM
JTAG_TCK rise and fall times
22.5
—
ns
ns
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
5
—
—
40
40
ns
24
ns
—
ns
—
ns
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Table 70. JTAG Timing (continued)
Parameter1,2
All Frequencies
ID
Unit
Min
Max
SJ8
SJ9
JTAG_TMS, JTAG_TDI data set-up time
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
5
25
—
—
—
44
44
—
—
ns
ns
ns
ns
ns
ns
SJ10
SJ11
SJ12
SJ13
—
100
40
JTAG_TRST_B set-up time to JTAG_TCK low
1
2
T
= target frequency of SJC
DC
VM = mid-point voltage
4.12.13 SPDIF Timing Parameters
The Sony/Philips Digital Interface Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 71, Figure 63, and Figure 64 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 71. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
ns
SPDIF_OUT output (Load = 50pf)
—
—
—
—
—
—
1.5
24.2
31.3
• Skew
• Transition rising
• Transition falling
SPDIF_OUT1 output (Load = 30pf)
—
—
—
ns
• Skew
• Transition rising
• Transition falling
—
—
—
1.5
13.6
18.0
Modulating Rx clock (SPDIF_SR_CLK) period
SPDIF_SR_CLK high period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
SPDIF_ST_CLK low period
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srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 63. SPDIF_SR_CLK Timing Diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 64. SPDIF_ST_CLK Timing Diagram
4.12.14 UART I/O Configuration and Timing Parameters
4.12.14.1 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.12.14.1.1 UART Transmitter
Figure 65 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 72 lists the UART RS-232 serial mode transmits timing characteristics.
Possible
UA1
UA1
Bit 3
Parity
Bit
Next
Start
Bit
Start
Bit
UARTx_TX_DATA
(output)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA1
UA1
Figure 65. UART RS-232 Serial Mode Transmit Timing Diagram
Table 72. RS-232 Serial Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + T
Unit
2
UA1 Transmit Bit Time
tTbit
1/Fbaud_rate1 - T
—
ref_clk
ref_clk
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
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4.12.14.1.2 UART Receiver
Figure 66 depicts the RS-232 serial mode receives timing with 8 data bit/1 stop bit format. Table 73 lists
serial mode receive timing characteristics.
Possible
Parity
UA2
UA2
Bit 3
Bit
Next
Start
Bit
Start
Bit
STOP
BIT
UARTx_RX_DATA
(output)
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA2
UA2
Figure 66. UART RS-232 Serial Mode Receive Timing Diagram
Table 73. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16
1/Fbaud_rate
+
—
x Fbaud_rate
)
1/(16 x Fbaud_rate)
1
2
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.14.1.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA Mode Transmitter
Figure 67 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 74 lists
the transmit timing characteristics.
UA4
UA3
UA3
UA3
UA3
RGMII_TXD
(output)
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 67. UART IrDA Mode Transmit Timing Diagram
Table 74. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + T
Unit
1
UA3
Transmit Bit Time in IrDA mode
Transmit IR Pulse Duration
tTIRbit
1/Fbaud_rate
-
—
ref_clk
2
T
ref_clk
UA4
tTIRpulse (3/16) x (1/Fbaud_rate
- T
)
(3/16) x (1/Fbaud_rate
+ T
)
—
ref_clk
ref_clk
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1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
UART IrDA Mode Receiver
Figure 68 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 75 lists the
receive timing characteristics.
UA6
UA5
UA5
UA5
UA5
RGMII_RXD
(input)
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 68. UART IrDA Mode Receive Timing Diagram
Table 75. IrDA Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA5
Receive Bit Time1 in IrDA mode
tRIRbit
1/Fbaud_rate2 - 1/(16 1/Fbaud_rate + 1/(16 x
—
x Fbaud_rate
)
Fbaud_rate
)
UA6
Receive IR Pulse Duration
tRIRpulse
1.41 s
(5/16) x (1/Fbaud_rate
)
—
1
2
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.15 USB PHY Parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
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•
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
•
•
— Portable device only
4.13 A/D converter
The following subsections provide information about A/D converter.
4.13.1 12-bit ADC electrical characteristics
4.13.1.1 12-bit ADC operating conditions
Table 76. 12-bit ADC Operating Conditions
Characteristic
Supply voltage
Conditions
Absolute
Symb
VDDAD
Min
Typ1
Max
Unit
Comment
3.0
-
3.6
V
—
—
Delta to VDD
VDDAD
-100
0
100
mV
(VDD-VDDAD)2
Ground voltage
Delta to VSS
VSSAD
-100
0
100
mV
—
(VSS-VSSAD)
Ref Voltage High
Ref Voltage Low
Input Voltage
—
VREFH
VREFL
VADIN
CADIN
RADIN
1.13
VSSAD
VREFL
—
VDDAD
VSSAD
—
VDDAD
V
—
—
—
—
—
—
—
—
VSSAD
V
—
VREFH
V
Input Capacitance
Input Resistance
8/10/12 bit modes
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
1.5
2
pF
—
5
7
kohms
kohms
kohms
kohms
—
12.5
25
15
30
1
—
Analog Source
Resistance
12 bit mode fADCK
40MHz ADLSMP=0,
=
RAS
—
—
Tsamp=150
ns
ADSTS=10, ADHSC=1
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
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Table 76. 12-bit ADC Operating Conditions (continued)
Typ1
Characteristic
Conditions
Symb
fADCK
Min
Max
Unit
MHz
Comment
ADC Conversion Clock ADLPC=0, ADHSC=1
4
4
4
—
—
—
40
30
20
—
Frequency
12 bit mode
ADLPC=0, ADHSC=0
12 bit mode
MHz
MHz
—
—
ADLPC=1, ADHSC=0
12 bit mode
1
2
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential differences
Figure 69. 12-bit ADC Input Impedance Equivalency Diagram
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Electrical Characteristics
4.13.1.1.1 12-bit ADC characteristics
Table 77. 12-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
DDAD REFL
Characteristic
Conditions1
Symb
IDDAD
Min
Typ2
Max
Unit
Comment
ADLSMP=0
[L:] Supply Current
ADLPC=1,
ADHSC=0
—
250
350
400
0.01
—
µA
ADSTS=10 ADCO=1
ADLPC=0,
ADHSC=0
ADLPC=0,
ADHSC=1
[L:] Supply Current
Stop, Reset, Module IDDAD
Off
—
0.8
µA
—
ADC Asynchronous ADHSC=0
fADACK
—
—
—
10
20
2
—
—
—
MHz
tADACK = 1/fADACK
Clock Source
ADHSC=1
Sample Cycles
ADLSMP=0,
ADSTS=00
Csamp
cycles
—
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
16
20
24
ADLSMP=1,
ADSTS=01
ADLSMP=1,
ADSTS=10
ADLSMP=1,
ADSTS=11
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Electrical Characteristics
) (continued)
Table 77. 12-bit ADC Characteristics (V
= V
, V
= V
REFH
DDAD REFL SSAD
Characteristic
Conditions1
Symb
Cconv
Min
Typ2
Max
Unit
cycles
Comment
Conversion Cycles
ADLSMP=0
—
28
30
32
34
38
42
46
50
—
—
ADSTS=00
ADLSMP=0
ADSTS=01
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Conversion Time
ADLSMP=0
ADSTS=00
Tconv
—
0.7
—
µs
Fadc=40 MHz
ADLSMP=0
ADSTS=01
0.75
0.8
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
0.85
0.95
1.05
1.15
1.25
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
[P:][C:] Total
Unadjusted Error
12 bit mode
10 bit mode
8 bit mode
TUE
DNL
—
—
—
4.5
2
—
—
—
LSB
1 LSB =
(VREFH
VREFL)/2
N
—
—
-
1.5
[P:][C:] Differential
Non-Linearity
12 bit mode
10bit mode
8 bit mode
—
—
—
1
—
—
—
LSB
0.5
0.2
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Electrical Characteristics
Table 77. 12-bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSAD
REFH
DDAD REFL
Characteristic
Conditions1
12 bit mode
Symb
INL
Min
Typ2
2.6
Max
Unit
LSB
Comment
[P:][C:] Integral
Non-Linearity
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
0.8
0.3
Zero-Scale Error
Full-Scale Error
EZS
-0.3
-0.15
-0.15
-2.5
-0.6
-0.3
10.7
LSB
LSB
EFS
[L:] Effective Number 12 bit mode
of Bits
ENOB
SINAD
10.1
Bits
dB
—
—
[L:] Signal to Noise
plus Distortion
See ENOB
SINAD = 6.02 x ENOB + 1.76
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
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Boot Mode Configuration
5 Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 78 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX 6ULL Fuse
Map document and the System Boot chapter in i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 78. Fuses and Associated Pins Used for Boot
Pin
Direction at reset
eFuse name
Details
BOOT_MODE0
BOOT_MODE1
Input with 100 K pull-down N/A
Input with 100 K pull-down N/A
Boot mode selection
Boot mode selection
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Boot Mode Configuration
Table 78. Fuses and Associated Pins Used for Boot (continued)
Pin
Direction at reset
eFuse name
Details
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
Input with 100 K pull-down BT_CFG1[0]
Input with 100 K pull-down BT_CFG1[1]
Input with 100 K pull-down BT_CFG1[2]
Input with 100 K pull-down BT_CFG1[3]
Input with 100 K pull-down BT_CFG1[4]
Input with 100 K pull-down BT_CFG1[5]
Input with 100 K pull-down BT_CFG1[6]
Input with 100 K pull-down BT_CFG1[7]
Input with 100 K pull-down BT_CFG2[0]
Input with 100 K pull-down BT_CFG2[1]
Input with 100 K pull-down BT_CFG2[2]
Input with 100 K pull-down BT_CFG2[3]
Input with 100 K pull-down BT_CFG2[4]
Input with 100 K pull-down BT_CFG2[5]
Input with 100 K pull-down BT_CFG2[6]
Input with 100 K pull-down BT_CFG2[7]
Input with 100 K pull-down BT_CFG4[0]
Input with 100 K pull-down BT_CFG4[1]
Input with 100 K pull-down BT_CFG4[2]
Input with 100 K pull-down BT_CFG4[3]
Input with 100 K pull-down BT_CFG4[4]
Input with 100 K pull-down BT_CFG4[5]
Input with 100 K pull-down BT_CFG4[6]
Input with 100 K pull-down BT_CFG4[7]
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
5.2
Boot Device Interface Allocation
The following tables list the interfaces that can be used by the boot process in accordance with the
specific boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC
allocation, which are configured during boot when appropriate.
Table 79. QSPI Boot trough QSPI
Mux
Mode
Quad
Mode
+ Port A + Port A + Port + Port B + Port B
DQS CS1 DQS CS1
Ball Name
Signal Name
Common
B
NAND_WP_B
NAND_DQS
qspi.A_SCLK
qspi.A_SS0_B
Alt2
Alt2
Yes
Yes
Yes
Yes
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Boot Mode Configuration
Table 79. QSPI Boot trough QSPI (continued)
NAND_READY_B qspi.A_DATA[0]
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Alt2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_CE0_B
NAND_CE1_B
NAND_CLE
qspi.A_DATA[1]
qspi.A_DATA[2]
qspi.A_DATA[3]
qspi.B_DATA[3]
qspi.B_DATA[2]
qspi.B_DATA[1]
qspi.B_DATA[0]
qspi.B_SS0_B
qspi.B_SCLK
qspi.A_SS1_B
qspi.A_DQS
NAND_DATA05
NAND_DATA04
NAND_DATA03
NAND_DATA02
NAND_WE_B
NAND_RE_B
NAND_DATA07
NAND_ALE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_DATA00
NAND_DATA01
qspi.B_SS1_B
qspi.B_DQS
Yes
Yes
Table 80. SPI Boot through ECSPI1
Mux
Mode
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
Ball Name
Signal Name
Common
[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
CSI_DATA07
CSI_DATA06
CSI_DATA04
CSI_DATA05
LCD_DATA05
LCD_DATA06
LCD_DATA07
ecspi1.MISO
ecspi1.MOSI
ecspi1.SCLK
ecspi1.SS0
ecspi1.SS1
ecspi1.SS2
ecspi1.SS3
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 81. SPI Boot through ECSPI2
BOOT_CFG BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
Ball Name
Signal Name
Mux Mode Common
4[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
CSI_DATA03
CSI_DATA02
CSI_DATA00
CSI_DATA01
LCD_HSYNC
ecspi2.MISO
ecspi2.MOSI
ecspi2.SCLK
ecspi2.SS0
ecspi2.SS1
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Yes
Yes
Yes
Yes
Yes
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Boot Mode Configuration
Table 81. SPI Boot through ECSPI2 (continued)
LCD_VSYNC
LCD_RESET
ecspi2.SS2
Alt 8
Alt 8
Yes
ecspi2.SS3
Yes
Table 82. SPI Boot through ECSPI3
Mux
Mode
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[ BOOT_CFG4
Ball Name
Signal Name
Common
[5:4]=00b
5:4]=01b
5:4]=10b
[5:4]=11b
UART2_RTS_B
UART2_CTS_B
ecspi3.MISO
ecspi3.MOSI
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
UART2_RX_DATA ecspi3.SCLK
UART2_TX_DATA
NAND_ALE
ecspi3.SS0
ecspi3.SS1
ecspi3.SS2
ecspi3.SS3
Yes
Yes
NAND_RE_B
NAND_WE_B
Yes
Yes
Table 83. SPI Boot through ECSPI4
Mux
Mode
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[ BOOT_CFG
Ball Name
Signal Name
Common
[5:4]=00b
5:4]=01b
5:4]=10b
4[5:4]=11b
ENET2_TX_CLK
ENET2_TX_EN
ecspi4.MISO
ecspi4.MOSI
Alt 3
Alt 3
Alt 3
Alt 3
Alt 8
Alt 8
Alt 8
Yes
Yes
Yes
ENET2_TX_DATA1 ecspi4.SCLK
ENET2_RX_ER
NAND_DATA01
NAND_DATA02
NAND_DATA03
ecspi4.SS0
ecspi4.SS1
ecspi4.SS2
ecspi4.SS3
Yes
Yes
Yes
Yes
Table 84. NAND Boot through GPMI
BOOT_CFG1[3:2]= BOOT_CFG1[3:2]=
Ball Name
Signal Name
Mux Mode Common
01b
10b
NAND_CLE
NAND_ALE
rawnand.CLE
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Yes
Yes
Yes
Yes
Yes
rawnand.ALE
rawnand.WP_B
rawnand.READY_B
rawnand.CE0_B
rawnand.CE1_B
rawnand.RE_B
NAND_WP_B
NAND_READY_B
NAND_CE0_B
NAND_CE1_B
NAND_RE_B
Yes
Yes
Yes
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Boot Mode Configuration
Table 84. NAND Boot through GPMI (continued)
BOOT_CFG1[3:2]= BOOT_CFG1[3:2]=
Ball Name
Signal Name
Mux Mode Common
01b
10b
NAND_WE_B
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
rawnand.WE_B
rawnand.DATA00
rawnand.DATA01
rawnand.DATA02
rawnand.DATA03
rawnand.DATA04
rawnand.DATA05
rawnand.DATA06
rawnand.DATA07
rawnand.DQS
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 2
Alt 2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CSI_MCLK
rawnand.CE2_B
rawnand.CE3_B
Yes
Yes
CSI_PIXCLK
Table 85. SD/MMC Boot through USDHC1
Mux
SDMMC
MFG
mode
BOOT_CFG1[1]=1
(SD Power Cycle)
Ball Name
Signal Name
Common
4-bit
8-bit
Mode
UART1_RTS_B
SD1_CLK
usdhc1.CD_B
usdhc1.CLK
Alt 2
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 0
Alt 1
Alt 1
Alt 1
Alt 1
Alt 5
Alt 4
Yes
Yes
Yes
Yes
SD1_CMD
usdhc1.CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
NAND_READY_B
NAND_CE0_B
NAND_CE1_B
NAND_CLE
usdhc1.DATA0
usdhc1.DATA1
usdhc1.DATA2
usdhc1.DATA3
usdhc1.DATA4
usdhc1.DATA5
usdhc1.DATA6
usdhc1.DATA7
GPIO1_IO091
usdhc1.VSELECT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GPIO1_IO09
GPIO1_IO05
Yes
Yes
1
The Boot ROM uses GPIO1_IO09 to implement SD1_RESET_B.
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Boot Mode Configuration
Ball Name
Table 86. SD/MMC Boot through USDHC2
Commo
BOOT_CFG1[1]=1
(SD Power Cycle)
Signal Name
Mux Mode
4-bit
8-bit
n
NAND_RE_B
NAND_WE_B
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_ALE
usdhc2.CLK
usdhc2.CMD
usdhc2.DATA0
usdhc2.DATA1
usdhc2.DATA2
usdhc2.DATA3
usdhc2.DATA4
usdhc2.DATA5
usdhc2.DATA6
usdhc2.DATA7
NAND_ALE1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 1
Alt 5
Alt 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GPIO1_IO08
usdhc2.VSELECT
1
The Boot ROM uses NAND_ALE to implement SD2_RESET_B.
Table 87. NOR/OneNAND Boot through EIM
ADL16
Non-Mux
Ball Name
Signal Name
Mux Mode
Common
AD16 Mux
CSI_DATA00
CSI_DATA01
weim.AD[0]
weim.AD[1]
weim.AD[2]
weim.AD[3]
weim.AD[4]
weim.AD[5]
weim.AD[6]
weim.AD[7]
weim.AD[8]
weim.AD[9]
weim.AD[10]
weim.AD[11]
weim.AD[12]
weim.AD[13]
weim.AD[14]
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
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Boot Mode Configuration
Table 87. NOR/OneNAND Boot through EIM (continued)
ADL16
Non-Mux
Ball Name
Signal Name
Mux Mode
Common
AD16 Mux
NAND_DATA07
NAND_CLE
weim.AD[15]
weim.ADDR[16]
weim.ADDR[17]
weim.ADDR[18]
weim.ADDR[19]
weim.ADDR[20]
weim.ADDR[21]
weim.ADDR[22]
weim.ADDR[23]
weim.ADDR[24]
weim.ADDR[25]
weim.ADDR[26]
weim.CS0_B
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Alt 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NAND_ALE
NAND_CE1_B
SD1_CMD
SD1_CLK
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
ENET2_RXER
ENET2_CRS_DV
CSI_MCLK
Yes
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
NAND_RE_B
NAND_WE_B
CSI_HSYNC
weim.DATA[0]
weim.DATA[1]
weim.DATA[2]
weim.DATA[3]
weim.DATA[4]
weim.DATA[5]
weim.DATA[6]
weim.DATA[7]
weim.DATA[8]
weim.DATA[9]
weim.DATA[10]
weim.DATA[11]
weim.DATA[12]
weim.DATA[13]
weim.DATA[14]
weim.DATA[15]
weim.EB_B[0]
weim.EB_B[1]
weim.LBA_B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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Boot Mode Configuration
Ball Name
Table 87. NOR/OneNAND Boot through EIM (continued)
ADL16
Signal Name
Mux Mode
Common
AD16 Mux
Non-Mux
CSI_PIXCLK
CSI_VSYNC
weim.OE
weim.RW
Alt 4
Alt 4
Yes
Yes
Table 88. Serial Download through UART1
Ball Name
Signal Name
Mux Mode
Common
UART1_TX_DATA
UART1_RX_DATA
uart1.TX_DATA
uart1.RX_DATA
Alt 0
Alt 0
Yes
Yes
Table 89. Serial Download through UART2
Ball Name
Signal Name
Mux Mode
Common
UART2_TX_DATA
UART2_RX_DATA
uart2.TX_DATA
uart2.RX_DATA
Alt 0
Alt 0
Yes
Yes
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Package Information and Contact Assignments
6 Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
14 x 14 mm Package Information
14 x 14 mm, 0.8 mm Pitch, Ball Matrix
6.1.1
Figure 70 shows the top, bottom, and side views of the 14 x 14 mm BGA package.
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Package Information and Contact Assignments
Figure 70. 14 x 14 mm BGA, Case x Package Top, Bottom, and Side Views
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Package Information and Contact Assignments
6.1.2
14 x 14 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 90 shows the device connection list for ground, sense, and reference contact signals.
Table 90. 14 x 14 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
DRAM_VREF
GPANIO
M13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P4
R13
NGND_KEL0
NVCC_CSI
M12
F4
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_ENET
NVCC_GPIO
NVCC_LCD
G6, H6, J6, K6, L6, M6
N6
F13
J13
E13
NVCC_NAND
NVCC_PLL
E7
P13
NVCC_SD1
C4
NVCC_UART
VDD_ARM_CAP
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_CAP
VDD_SOC_IN
VDD_USB_CAP
VDDA_ADC_3P3
VSS
H13
G9, G10, G11, H11
R14, R15
N13
N12
P12
G8, H8, J8, J11, K8, K11, L8, L9, L10, L11
H9, H10, J9, J10, K9, 10
R12
L13
A1, A17, C3, C7, C11, C15, E8, E11, F6, F7, F8, F9, F10,F11, F12, G3, G5, G7,
G12, G15, H7, H12, J5, J7, J12, K7, K12, L3, L7, L12, M7, M8, M9, M10, M11,
N3, N5, R3, R5, R7, R11, R16, R17, T14, U1, U14, U17
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Package Information and Contact Assignments
Table 91 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.
Table 91. 14 x 14 mm Functional Contact Assignments
Out of Reset Condition
14x14
Ball
Power
Group
Ball
Type Default
Mode
Ball Name
Default
Function
Input/
Output
Value
BOOT_MODE0
T10
U10
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
ALT5
ALT5
GPIO5_IO10
GPIO5_IO11
Input
Input
100 k
pull-down
BOOT_MODE1
100 k
pull-down
CCM_CLK1_N
CCM_CLK1_P
CCM_PMIC_STBY_REQ
CSI_DATA00
CSI_DATA01
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
CSI_HSYNC
CSI_MCLK
P16
P17
U9
E4
E3
E2
E1
D4
D3
D2
D1
F3
VDD_HIGH_CAP CCM
VDD_HIGH_CAP CCM
—
CCM_CLK1_N
CCM_CLK1_P
CCM_PMIC_VSTBY_REQ
GPIO4_IO21
—
—
—
—
—
VDD_SNVS_IN
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_DRAM
CCM
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
—
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
GPIO4_IO22
GPIO4_IO23
GPIO4_IO24
GPIO4_IO25
GPIO4_IO26
GPIO4_IO27
GPIO4_IO28
GPIO4_IO20
F5
GPIO4_IO17
CSI_PIXCLK
CSI_VSYNC
E5
F2
GPIO4_IO18
GPIO4_IO19
DRAM_ADDR00
L5
MMDC ALT0
DRAM_ADDR00
100 k
pull-up
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
H2
K1
M2
K4
L1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
Output
Output
Output
Output
Output
Output
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
G2
100 k
pull-up
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
114
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
H4
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
J4
100 k
pull-up
L2
100 k
pull-up
M4
K3
L4
100 k
pull-up
100 k
pull-up
100 k
pull-up
H3
G1
K5
J2
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
N2
H5
T4
U6
T6
U7
U8
T8
T5
U4
U2
100 k
pull-up
100 k
pull-up
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
115
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
U3
U5
R4
P5
P3
R2
R1
T7
T3
N1
F1
M5
G4
M1
H1
K2
M3
J3
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
Input
Input
100 k
pull-up
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
DRAM_DQM1
DRAM_DQM1
100 k
pull-up
DRAM_ODT0
DRAM_ODT0
100 k
pull-down
DRAM_ODT1
DRAM_ODT1
100 k
pull-down
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
100 k
pull-up
100 k
pull-down
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-down
100 k
pull-down
P2
P1
P7
DDRCL ALT0
K
100 k
pull-up
DDRCL ALT0
K
Input
100 k
pull-up
DDRCL ALT0
K
Input
100 k
pull-down
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
116
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDWE_B
P6
T2
T1
J1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDRCL ALT0
K
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDWE_B
Input
100 k
pull-down
DDRCL ALT0
K
Input
100 k
pull-down
DDRCL ALT0
K
Input
100 k
pull-down
DDR
ALT0
Output
100 k
pull-up
DRAM_ZQPAD
ENET1_RX_DATA0
ENET1_RX_DATA1
ENET1_RX_EN
ENET1_RX_ER
ENET1_TX_CLK
ENET1_TX_DATA0
ENET1_TX_DATA1
ENET1_TX_EN
ENET2_RX_DATA0
ENET2_RX_DATA1
ENET2_RX_EN
ENET2_RX_ER
ENET2_TX_CLK
ENET2_TX_DATA0
ENET2_TX_DATA1
ENET2_TX_EN
GPIO1_IO00
N4
NVCC_DRAM
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
DRAM_ZQPAD
GPIO2_IO0
GPIO2_IO1
GPIO2_IO2
GPIO2_IO7
GPIO2_IO6
GPIO2_IO3
GPIO2_IO4
GPIO2_IO5
GPIO2_IO8
GPIO2_IO9
GPIO2_IO10
GPIO2_IO15
GPIO2_IO14
GPIO2_IO11
GPIO2_IO12
GPIO2_IO13
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
F16
E17
E16
D15
F14
E15
E14
F15
C17
C16
B17
D16
D17
A15
A16
B15
K13
L15
L14
L17
M16
M17
K17
L16
N17
M15
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
117
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
JTAG_MOD
JTAG_TCK
JTAG_TDI
P15
M14
N16
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
SJC
SJC
SJC
ALT0
ALT0
ALT0
SJC_MOD
SJC_TCK
SJC_TDI
Input
Input
Input
100 k
pull-up
47 k
pull-up
47 k
pull-up
JTAG_TDO
JTAG_TMS
N15
P14
NVCC_GPIO
NVCC_GPIO
SJC
SJC
ALT0
ALT0
SJC_TDO
SJC_TMS
Output
Input
Keeper
47 k
pull-up
JTAG_TRST_B
N14
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
A8
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO3_IO0
GPIO3_IO5
GPIO3_IO6
GPIO3_IO7
GPIO3_IO8
GPIO3_IO9
GPIO3_IO10
GPIO3_IO11
GPIO3_IO12
GPIO3_IO13
GPIO3_IO14
GPIO3_IO15
GPIO3_IO16
GPIO3_IO17
GPIO3_IO18
GPIO3_IO19
GPIO3_IO20
GPIO3_IO21
GPIO3_IO22
GPIO3_IO23
GPIO3_IO24
GPIO3_IO25
GPIO3_IO26
GPIO3_IO27
GPIO3_IO28
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
B9
A9
E10
D10
C10
B10
A10
D11
B11
A11
E12
D12
C12
B12
A12
D13
C13
B13
A13
D14
C14
B14
A14
B16
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
118
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
NAND_ALE
B8
D9
E9
C9
B4
C5
B5
A4
D7
B7
A7
D6
C6
B6
A6
A5
E6
D8
A3
C8
D5
R8
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
SRC
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
GPIO3_IO1
GPIO3_IO2
GPIO3_IO4
GPIO3_IO3
GPIO4_IO10
GPIO4_IO13
GPIO4_IO14
GPIO4_IO15
GPIO4_IO2
GPIO4_IO3
GPIO4_IO4
GPIO4_IO5
GPIO4_IO6
GPIO4_IO7
GPIO4_IO8
GPIO4_IO9
GPIO4_IO16
GPIO4_IO0
GPIO4_IO12
GPIO4_IO1
GPIO4_IO11
SRC_RESET_B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC_LCD
NVCC_LCD
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
VDD_SNVS_IN
NAND_CE0_B
NAND_CE1_B
NAND_CLE
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
NAND_RE_B
NAND_READY_B
NAND_WE_B
NAND_WP_B
ONOFF
100 k
pull-up
POR_B
P8
VDD_SNVS_IN
SRC
ALT0
—
SRC_POR_B
RTC_XTALI
RTC_XTALO
Input
—
100 k
pull-up
RTC_XTALI
RTC_XTALO
T11 VDD_SNVS_CAP ANALO
G
—
—
U11 VDD_SNVS_CAP ANALO
G
—
—
SD1_CLK
C1
C2
B3
B2
B1
A2
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2_IO17
GPIO2_IO16
GPIO2_IO18
GPIO2_IO19
GPIO2_IO20
GPIO2_IO21
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
119
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
T9
VDD_SNVS_IN
GPIO
ALT0
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
SNVS_TAMPER0
R10
VDD_SNVS_IN
GPIO
ALT5 GPIO5_IO00/SNVS_TAMPE
R01
Input Keeper/N
ot
connecte
d1,2
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER3
SNVS_TAMPER4
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
R9
P11
P10
P9
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5 GPIO5_IO01/SNVS_TAMPE
R11
Input Keeper/N
ot
connecte
d1,2
ALT5 GPIO5_IO02/SNVS_TAMPE
R21
Input Keeper/N
ot
connecte
d1,2
ALT5 GPIO5_IO03/SNVS_TAMPE
R31
Input Keeper/N
ot
connecte
d1,2
ALT5 GPIO5_IO04/SNVS_TAMPE
R41
Input Keeper/N
ot
connecte
d1,2
N8
ALT5 GPIO5_IO05/SNVS_TAMPE
R51
Input Keeper/N
ot
connecte
d1,2
N11
N10
N9
ALT5 GPIO5_IO06/SNVS_TAMPE
R61
Input Keeper/N
ot
connecte
d1,2
ALT5 GPIO5_IO07/SNVS_TAMPE
R71
Input Keeper/N
ot
connecte
d1,2
ALT5 GPIO5_IO08/SNVS_TAMPE
R81
Input Keeper/N
ot
connecte
d1,2
R6
ALT5 GPIO5_IO09/SNVS_TAMPE
R91
Input Keeper/N
ot
connecte
d1,2
TEST_MODE
N7
K15
J14
K16
VDD_SNVS_IN
NVCC_UART
NVCC_UART
NVCC_UART
TCU
GPIO
GPIO
GPIO
ALT0
ALT5
ALT5
ALT5
TCU_TEST_MODE
GPIO1_IO18
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
UART1_CTS_B
UART1_RTS_B
UART1_RX_DATA
GPIO1_IO19
GPIO1_IO17
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
120
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
UART1_TX_DATA
UART2_CTS_B
K14
J15
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
OPEN DRAIN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
—
GPIO1_IO16
GPIO1_IO22
GPIO1_IO23
GPIO1_IO21
GPIO1_IO20
GPIO1_IO26
GPIO1_IO27
GPIO1_IO25
GPIO1_IO24
GPIO1_IO29
GPIO1_IO28
GPIO1_IO31
GPIO1_IO30
USB_OTG1_CHD_B
USB_OTG1_DN
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
—
UART2_RTS_B
H14
J16
UART2_RX_DATA
UART2_TX_DATA
UART3_CTS_B
J17
H15
G14
H16
H17
G16
G17
G13
F17
U16
T15
UART3_RTS_B
UART3_RX_DATA
UART3_TX_DATA
UART4_RX_DATA
UART4_TX_DATA
UART5_RX_DATA
UART5_TX_DATA
USB_OTG1_CHD_B
USB_OTG1_DN
VDD_USB_CAP ANALO
G
—
—
—
USB_OTG1_DP
U15
T12
VDD_USB_CAP ANALO
G
—
—
USB_OTG1_DP
—
—
—
—
USB_OTG1_VBUS
USB_VBUS
VBUS
POWE
R
USB_OTG1_VBUS
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
T13
U13
U12
VDD_USB_CAP ANALO
G
—
—
—
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
—
—
—
—
—
—
VDD_USB_CAP ANALO
G
USB_VBUS
VBUS
POWE
R
XTALI
T16
T17
NVCC_PLL
NVCC_PLL
ANALO
G
—
—
XTALI
—
—
—
—
XTALO
ANALO
G
XTALO
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2
SNVS_TAMPER0 to SNVS_TAMPER9 is input unconnected in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
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Package Information and Contact Assignments
6.1.3
14 x 14 mm, 0.8 mm Pitch, Ball Map
Table 92 shows the 14 x 14 mm, 0.8 mm pitch ball map for the i.MX 6ULL.
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map
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Package Information and Contact Assignments
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map (continued)
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Package Information and Contact Assignments
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map (continued)
6.2
9 x 9 mm Package Information
6.2.1
9 x 9 mm, 0.5 mm Pitch, Ball Matrix
Figure 71 shows the top, bottom, and side views of the 9 x 9 mm BGA package.
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NXP Semiconductors
Package Information and Contact Assignments
Figure 71. 9 x 9 mm BGA, Case x Package Top, Bottom, and Side Views
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Package Information and Contact Assignments
6.2.2
9 x 9 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 93 shows the device connection list for ground, sense, and reference contact signals.
Table 93. 9 x 9 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
DRAM_VREF
GPANAIO
N13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1
T11
NGND_KEL0
NVCC_CSI
M10
E5
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_ENET
NVCC_GPIO
NVCC_LCD
G5, L5, M5, N6
K6
G13
M13
E13
NVCC_NAND
NVCC_PLL
E11
T13
NVCC_SD1
E7
NVCC_UART
VDD_ARM_CAP
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_CAP
VDD_SOC_IN
VDD_USB_CAP
VDDA_ADC_3P3
VSS
L13
G9, G10, G11, H9, H10, H11
U11
U15
N12
P12
G7, G8, H7, H8, J7, J8, K7, K8, L7, L8
J9, J10, J11, K9, K10, K11, L9, L10, L11
N11
T17
A2, A7, A12, A17, B1, C15, F1, F3, F8, F10, F17, H6, H12, J3, J15, K12, M1, M3,
M8, M17, R3, R9, R12, R15, U1, U6, U13, U17
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Table 94 shows an alpha-sorted list of functional contact assignments for the 9 x 9 mm package.
Table 94. 9 x 9 mm Functional Contact Assignments
Out of Reset Condition
9x9
Ball
Power
Group
Ball
Type Default
Mode
Ball Name
Default
Function
Input/
Output
Value
BOOT_MODE0
T8
U8
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
ALT5
ALT5
GPIO5_IO10
GPIO5_IO11
Input
Input
100 k
pull-down
BOOT_MODE1
100 k
pull-down
CCM_CLK1_N
CCM_CLK1_P
CCM_PMIC_STBY_REQ
CSI_DATA00
CSI_DATA01
CSI_DATA02
CSI_DATA03
CSI_DATA04
CSI_DATA05
CSI_DATA06
CSI_DATA07
CSI_HSYNC
U16 VDD_HIGH_CAP LVDS
T16 VDD_HIGH_CAP LVDS
—
CCM_CLK1_N
CCM_CLK1_P
CCM_PMIC_VSTBY_REQ
GPIO4_IO21
—
—
—
—
—
U7
C3
D4
B2
D1
C4
B3
A3
C2
D2
C1
D5
D3
G1
VDD_SNVS_IN GPIO
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
—
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_DRAM
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DDR
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
GPIO4_IO22
GPIO4_IO23
GPIO4_IO24
GPIO4_IO25
GPIO4_IO26
GPIO4_IO27
GPIO4_IO28
GPIO4_IO20
CSI_MCLK
GPIO4_IO17
CSI_PIXCLK
CSI_VSYNC
GPIO4_IO18
GPIO4_IO19
DRAM_ADDR00
DRAM_ADDR00
100 k
pull-up
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
G2
H1
J2
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
Output
Output
Output
Output
Output
Output
100 k
pull-up
100 k
pull-up
100 k
pull-up
M4
H2
E4
100 k
pull-up
100 k
pull-up
100 k
pull-up
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
J4
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
J5
100 k
pull-up
J1
100 k
pull-up
M2
K5
L3
H4
E3
E2
G4
L1
H5
T3
N5
T4
T5
U5
T6
R4
U3
P1
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
U2
P3
R2
P4
N2
N1
P2
U4
R1
K2
E1
L4
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DQM0
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Input
100 k
pull-up
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
100 k
pull-up
DRAM_DQM1
DRAM_DQM1
100 k
pull-up
DRAM_ODT0
DRAM_ODT0
100 k
pull-down
DRAM_ODT1
DRAM_ODT1
100 k
pull-down
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
100 k
pull-up
F2
H3
F5
G3
L2
100 k
pull-down
100 k
pull-up
100 k
pull-up
100 k
pull-up
100 k
pull-down
K1
K4
K3
R5
100 k
pull-down
DDRC ALT0
LK
100 k
pull-up
DDRC ALT0
LK
Input
100 k
pull-up
DDRC ALT0
LK
Input
100 k
pull-down
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDWE_B
P5
N4
N3
F4
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDRC ALT0
LK
DRAM_SDQS0_P
DRAM_SDQS1_P
DRAM_SDQS1_N
DRAM_SDWE_B
Input
Input
100 k
pull-down
DDRC ALT0
LK
100 k
pull-down
DDRC ALT0
LK
Input
100 k
pull-down
DDR
ALT0
Output
100 k
pull-up
DRAM_ZQPAD
ENET1_RX_DATA0
ENET1_RX_DATA1
ENET1_RX_EN
ENET1_RX_ER
ENET1_TX_CLK
ENET1_TX_DATA0
ENET1_TX_DATA1
ENET1_TX_EN
ENET2_RX_DATA0
ENET2_RX_DATA1
ENET2_RX_EN
ENET2_RX_ER
ENET2_TX_CLK
ENET2_TX_DATA0
ENET2_TX_DATA1
ENET2_TX_EN
GPIO1_IO00
T2
NVCC_DRAM
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
DRAM_ZQPAD
GPIO2_IO0
GPIO2_IO1
GPIO2_IO2
GPIO2_IO7
GPIO2_IO6
GPIO2_IO3
GPIO2_IO4
GPIO2_IO5
GPIO2_IO8
GPIO2_IO9
GPIO2_IO10
GPIO2_IO15
GPIO2_IO14
GPIO2_IO11
GPIO2_IO12
GPIO2_IO13
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
G17
F16
G16
G14
G15
E16
F13
F15
E17
D17
D16
H13
H14
E14
F14
E15
M14
M15
M16
N16
N17
P15
N15
N14
P14
P16
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
JTAG_MOD
JTAG_TCK
JTAG_TDI
R13
R17
P17
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
SJC
SJC
SJC
ALT0
ALT0
ALT0
SJC_MOD
SJC_TCK
SJC_TDI
Input
Input
Input
100 k
pull-up
47 k
pull-up
47 k
pull-up
JTAG_TDO
JTAG_TMS
R16
R14
NVCC_GPIO
NVCC_GPIO
SJC
SJC
ALT0
ALT0
SJC_TDO
SJC_TMS
Output
Input
Keeper
47 k
pull-up
JTAG_TRST_B
P13
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
C11
D11
B12
D10
B11
A11
D12
D13
C12
B13
A13
D14
C13
C14
A14
B14
A16
A15
D15
B15
E12
B17
C16
B16
C17
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO3_IO0
GPIO3_IO5
GPIO3_IO6
GPIO3_IO7
GPIO3_IO8
GPIO3_IO9
GPIO3_IO10
GPIO3_IO11
GPIO3_IO12
GPIO3_IO13
GPIO3_IO14
GPIO3_IO15
GPIO3_IO16
GPIO3_IO17
GPIO3_IO18
GPIO3_IO19
GPIO3_IO20
GPIO3_IO21
GPIO3_IO22
GPIO3_IO23
GPIO3_IO24
GPIO3_IO25
GPIO3_IO26
GPIO3_IO27
GPIO3_IO28
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
NAND_ALE
A10
B10
E10
C10
D8
E8
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
SRC
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
GPIO3_IO1
GPIO3_IO2
GPIO3_IO4
GPIO3_IO3
GPIO4_IO10
GPIO4_IO13
GPIO4_IO14
GPIO4_IO15
GPIO4_IO2
GPIO4_IO3
GPIO4_IO4
GPIO4_IO5
GPIO4_IO6
GPIO4_IO7
GPIO4_IO8
GPIO4_IO9
GPIO4_IO16
GPIO4_IO0
GPIO4_IO12
GPIO4_IO1
GPIO4_IO11
SRC_RESET_B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC_LCD
NVCC_LCD
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
VDD_SNVS_IN
NAND_CE0_B
NAND_CE1_B
NAND_CLE
B6
B7
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
D7
A9
C9
C7
C8
A6
B9
B8
E6
NAND_RE_B
NAND_READY_B
NAND_WE_B
NAND_WP_B
ONOFF
D9
E9
A8
D6
R6
100 k
pull-up
POR_B
R10
T12
U12
VDD_SNVS_IN
SRC
ALT0
—
SRC_POR_B
RTC_XTALI
RTC_XTALO
Input
—
100 k
pull-up
RTC_XTALI
RTC_XTALO
VDD_SNVS_CA ANAL
OG
—
—
P
VDD_SNVS_CA ANAL
—
—
P
OG
SD1_CLK
C5
C6
A5
A4
B5
B4
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
NVCC_SD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2_IO17
GPIO2_IO16
GPIO2_IO18
GPIO2_IO19
GPIO2_IO20
GPIO2_IO21
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
SNVS_TAMPER0
T7
R8
P6
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
ALT0
ALT5
ALT5
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
GPIO5_IO00/SNVS_TAMPE
R01
Input
Keeper1,
2
SNVS_TAMPER1
GPIO5_IO01/SNVS_TAMPE
R11
Input Keeper/N
ot
connecte
d1,2
SNVS_TAMPER2
SNVS_TAMPER3
SNVS_TAMPER4
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
N10
P10
P7
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
VDD_SNVS_IN GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO5_IO02/SNVS_TAMPE
R21
Input Keeper/N
ot
connecte
d1,2
GPIO5_IO03/SNVS_TAMPE
R31
Input Keeper/N
ot
connecte
d1,2
GPIO5_IO04/SNVS_TAMPE
R41
Input Keeper/N
ot
connecte
d1,2
P8
GPIO5_IO05/SNVS_TAMPE
R51
Input Keeper/N
ot
connecte
d1,2
R7
N9
N8
P9
GPIO5_IO06/SNVS_TAMPE
R61
Input Keeper/N
ot
connecte
d1,2
GPIO5_IO07/SNVS_TAMPE
R71
Input Keeper/N
ot
connecte
d1,2
GPIO5_IO08/SNVS_TAMPE
R81
Input Keeper/N
ot
connecte
d1,2
GPIO5_IO09/SNVS_TAMPE
R91
Input Keeper/N
ot
connecte
d1,2
TEST_MODE
N7
L14
K14
L17
L15
VDD_SNVS_IN
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
TCU
GPIO
GPIO
GPIO
GPIO
ALT0
ALT5
ALT5
ALT5
ALT5
TCU_TEST_MODE
GPIO1_IO18
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
UART1_CTS_B
UART1_RTS_B
UART1_RX_DATA
UART1_TX_DATA
GPIO1_IO19
GPIO1_IO17
GPIO1_IO16
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Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
UART2_CTS_B
J17
J14
K16
L16
H16
H15
K15
K17
H17
J16
J13
K13
T15
R11
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
OPEN DRAIN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
—
GPIO1_IO22
GPIO1_IO23
GPIO1_IO21
GPIO1_IO20
GPIO1_IO26
GPIO1_IO27
GPIO1_IO25
GPIO1_IO24
GPIO1_IO29
GPIO1_IO28
GPIO1_IO31
GPIO1_IO30
USB_OTG1_CHD_B
USB_OTG1_DN
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
—
UART2_RTS_B
UART2_RX_DATA
UART2_TX_DATA
UART3_CTS_B
UART3_RTS_B
UART3_RX_DATA
UART3_TX_DATA
UART4_RX_DATA
UART4_TX_DATA
UART5_RX_DATA
UART5_TX_DATA
USB_OTG1_CHD_B
USB_OTG1_DN
VDD_USB_CAP ANAL
OG
—
—
—
USB_OTG1_DP
P11
T9
VDD_USB_CAP ANAL
OG
—
—
USB_OTG1_DP
—
—
—
—
USB_OTG1_VBUS
USB_VBUS
VBUS
POWE
R
USB_OTG1_VBUS
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
T10
U10
U9
VDD_USB_CAP ANAL
OG
—
—
—
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
—
—
—
—
—
—
VDD_USB_CAP ANAL
OG
USB_VBUS
VBUS
POWE
R
XTALI
T14
U14
NVCC_PLL
NVCC_PLL
ANAL
OG
—
—
XTALI
—
—
—
—
XTALO
ANAL
OG
XTALO
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2
SNVS_TAMPER0 to SNVS_TAMPER9 is input unconnected in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
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Package Information and Contact Assignments
6.2.3
9 x 9 mm, 0.5 mm Pitch, Ball Map
Table 95 shows the 9 x 9 mm, 0.5 mm pitch ball map for the i.MX 6ULL.
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
NXP Semiconductors
135
Package Information and Contact Assignments
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
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NXP Semiconductors
Package Information and Contact Assignments
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Consumer Products, Rev. 1.2, 11/2017
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137
Revision History
7 Revision History
Table 96 provides a revision history for this data sheet.
Table 96. i.MX 6ULL Data Sheet Document Revision History
Substantive Change(s)
Rev.
Number
Date
1.2
09/2017 • Updated the part numbers and added a new part number (MCIMX6Y2DVK09AB) in the Table 1,
"Ordering Information"
• Updated the silicon revision number in the Figure 1, "Part Number Nomenclature—i.MX 6ULL"
• Updated the GPIO1_IO09 signal name in the Table 85, "SD/MMC Boot through USDHC1" and added
a footnote
• Updated the NAND_ALE signal name in the Table 86, "SD/MMC Boot through USDHC2" and added
a footnote
1.1
05/2017 • Changed terminology from “floating” to “not connected”
• Changed the LV-DDR3 to DDR3L in the Section 1.2, “Features"
• Added a footnote regarding maximum voltage allowance in the Table 7, "Absolute Maximum Ratings"
• Updated the minimum value of VDD_SOC_CAP in the Low Power Run Mode: LDO Enabled from the
Table 10, "Operating Ranges"
• Removed the LPSR mode in the Section 4.1.6, “Power Modes"
• Removed a note in the Section 4.2.1, “Power-Up Sequence"
• Replaced the MMDC compatible information with a cross reference in the Section 4.6.3, “DDR I/O DC
Parameters" and Section 4.7.2, “DDR I/O AC Parameters"
• Removed the Section 4.9.4, “DDR SDRAM Specific Parameters (DDR3 and LPDDR2)”
• Added a new Section 4.10, “Multi-Mode DDR Controller (MMDC)"
• Changed SD3 min to 1.7 ns in the Table 51, "eMMC4.4/4.41 Interface Timing Specification"
1
04/2017 • Added two new part numbers in the Table 1, "Ordering Information"
• Updated the Part differentiator number 3 to Reserved, removed 300 MHz from frequency, and added
900 MHz in the Figure 1, "Part Number Nomenclature—i.MX 6ULL"
• Updated the DDR I/O supply voltage and added a table not in the Table 7, "Absolute Maximum
Ratings"
• Updated Table 10, "Operating Ranges"
• Added Max. current for VDD_SOC_IN at 900 MHz in the Table 13, "Maximum Supply Currents"
• Updated the LDO_2P5 of the LOW POWER IDLE: LDO Bypassed row in the Table 15, "Low Power
Mode Current and Power Consumption"
• Updated the Figure 18, "Asynchronous A/D Muxed Write Access"
• Added a new Section 4.12.9.1, “LCDIF Signal Mapping"
• Added a note in the Section 4.2.1, “Power-Up Sequence"
• Updated VDD_HIGH_CAP pin assignment in the Table 90, "14 x 14 mm Supplies Contact
Assignment"
• Updated VDD_HIGH_CAP pin name in the Table 92, "14 x 14 mm, 0.8 mm Pitch, Ball Map"
0
09/2016 • Initial public release
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NXP Semiconductors
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Document Number: IMX6ULLCEC
Rev. 1.2
11/2017
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